├── ip ├── fpmult │ ├── iplauncher_debug.log │ ├── fpmult_inst.v │ ├── fpmult.qip │ ├── fpmult.inc │ ├── fpmult.cmp │ ├── fpmult.bsf │ └── fpmult_bb.v ├── fpacc │ ├── fpacc_sim │ │ ├── cadence │ │ │ ├── hdl.var │ │ │ ├── cds.lib │ │ │ └── ncsim_setup.sh │ │ ├── synopsys │ │ │ └── vcsmx │ │ │ │ └── synopsys_sim.setup │ │ └── dspba_library_package.vhd │ ├── fpacc_sim.f │ ├── fpacc.spd │ ├── fpacc.cmp │ ├── fpacc.sip │ ├── fpacc │ │ └── dspba_library_package.vhd │ ├── fpacc.v │ ├── fpacc.qip │ └── fpacc.bsf ├── spram_4096x32 │ ├── spram_4096x32_inst.v │ ├── spram_4096x32.qip │ ├── spram_4096x32.inc │ ├── spram_4096x32.cmp │ ├── spram_4096x32.bsf │ ├── spram_4096x32_bb.v │ └── spram_4096x32.v ├── fpadd │ ├── fpadd_inst.v │ ├── fpadd.qip │ ├── fpadd.inc │ ├── fpadd.cmp │ ├── fpadd.bsf │ └── fpadd_bb.v ├── dpram_16x32 │ ├── dpram_16x32_inst.v │ ├── dpram_16x32.qip │ ├── dpram_16x32.inc │ ├── dpram_16x32.cmp │ ├── dpram_16x32.bsf │ ├── dpram_16x32_bb.v │ └── dpram_16x32.v ├── fifo_32 │ ├── fifo_32_inst.v │ ├── fifo_32.qip │ ├── fifo_32.inc │ ├── fifo_32.cmp │ ├── fifo_32.bsf │ ├── fifo_32_bb.v │ └── fifo_32.v ├── dpram_256x32 │ ├── dpram_256x32_inst.v │ ├── dpram_256x32.qip │ ├── dpram_256x32.inc │ ├── dpram_256x32.cmp │ ├── dpram_256x32.bsf │ ├── dpram_256x32_bb.v │ └── dpram_256x32.v └── dpram_4096x32 │ ├── dpram_4096x32_inst.v │ ├── dpram_4096x32.qip │ ├── dpram_4096x32.inc │ ├── dpram_4096x32.cmp │ ├── dpram_4096x32.bsf │ └── dpram_4096x32_bb.v ├── ProcessingCore.qws ├── .gitattributes ├── README.md ├── LICENSE ├── instructions.txt ├── ProcessingCore.qpf ├── procControl.sv ├── procRegs.sv ├── ProcessingCore.ipregen.rpt ├── procUnit.sv ├── proc_top.sv ├── procRouter.sv ├── procRow.sv ├── ProcessingCore.qsf └── procCore.sv /ip/fpmult/iplauncher_debug.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /ProcessingCore.qws: -------------------------------------------------------------------------------- 1 | @(last_workspace -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim.f: -------------------------------------------------------------------------------- 1 | fpacc_sim/dspba_library_package.vhd 2 | fpacc_sim/dspba_library.vhd 3 | fpacc_sim/fpacc.vhd 4 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32_inst.v: -------------------------------------------------------------------------------- 1 | spram_4096x32 spram_4096x32_inst ( 2 | .address ( address_sig ), 3 | .clock ( clock_sig ), 4 | .data ( data_sig ), 5 | .wren ( wren_sig ), 6 | .q ( q_sig ) 7 | ); 8 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd_inst.v: -------------------------------------------------------------------------------- 1 | fpadd fpadd_inst ( 2 | .aclr ( aclr_sig ), 3 | .clk_en ( clk_en_sig ), 4 | .clock ( clock_sig ), 5 | .dataa ( dataa_sig ), 6 | .datab ( datab_sig ), 7 | .result ( result_sig ) 8 | ); 9 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult_inst.v: -------------------------------------------------------------------------------- 1 | fpmult fpmult_inst ( 2 | .aclr ( aclr_sig ), 3 | .clk_en ( clk_en_sig ), 4 | .clock ( clock_sig ), 5 | .dataa ( dataa_sig ), 6 | .datab ( datab_sig ), 7 | .result ( result_sig ) 8 | ); 9 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # CNN_Core 2 | * A CNN accelerator design inspired by MIT Eyeriss project 3 | * Uses Altera Avalon-MM bus 4 | * Compiled and tested on stratix IV using quartus prime ide. 5 | * Available instructions please refer to [instructions.txt](instructions.txt) 6 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32_inst.v: -------------------------------------------------------------------------------- 1 | dpram_16x32 dpram_16x32_inst ( 2 | .clock ( clock_sig ), 3 | .data ( data_sig ), 4 | .enable ( enable_sig ), 5 | .rdaddress ( rdaddress_sig ), 6 | .wraddress ( wraddress_sig ), 7 | .wren ( wren_sig ), 8 | .q ( q_sig ) 9 | ); 10 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32_inst.v: -------------------------------------------------------------------------------- 1 | fifo_32 fifo_32_inst ( 2 | .aclr ( aclr_sig ), 3 | .clock ( clock_sig ), 4 | .data ( data_sig ), 5 | .rdreq ( rdreq_sig ), 6 | .wrreq ( wrreq_sig ), 7 | .empty ( empty_sig ), 8 | .full ( full_sig ), 9 | .q ( q_sig ), 10 | .usedw ( usedw_sig ) 11 | ); 12 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32_inst.v: -------------------------------------------------------------------------------- 1 | dpram_256x32 dpram_256x32_inst ( 2 | .aclr ( aclr_sig ), 3 | .clock ( clock_sig ), 4 | .data ( data_sig ), 5 | .enable ( enable_sig ), 6 | .rdaddress ( rdaddress_sig ), 7 | .wraddress ( wraddress_sig ), 8 | .wren ( wren_sig ), 9 | .q ( q_sig ) 10 | ); 11 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32_inst.v: -------------------------------------------------------------------------------- 1 | dpram_4096x32 dpram_4096x32_inst ( 2 | .address_a ( address_a_sig ), 3 | .address_b ( address_b_sig ), 4 | .clock_a ( clock_a_sig ), 5 | .clock_b ( clock_b_sig ), 6 | .data_a ( data_a_sig ), 7 | .data_b ( data_b_sig ), 8 | .rden_a ( rden_a_sig ), 9 | .rden_b ( rden_b_sig ), 10 | .wren_a ( wren_a_sig ), 11 | .wren_b ( wren_b_sig ), 12 | .q_a ( q_a_sig ), 13 | .q_b ( q_b_sig ) 14 | ); 15 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim/synopsys/vcsmx/synopsys_sim.setup: -------------------------------------------------------------------------------- 1 | 2 | WORK > DEFAULT 3 | DEFAULT: ./libraries/work/ 4 | work: ./libraries/work/ 5 | altera: ./libraries/altera/ 6 | lpm: ./libraries/lpm/ 7 | sgate: ./libraries/sgate/ 8 | altera_mf: ./libraries/altera_mf/ 9 | altera_lnsim: ./libraries/altera_lnsim/ 10 | stratixiv_hssi: ./libraries/stratixiv_hssi/ 11 | stratixiv_pcie_hip: ./libraries/stratixiv_pcie_hip/ 12 | stratixiv: ./libraries/stratixiv/ 13 | LIBRARY_SCAN = TRUE 14 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTFP_ADD_SUB" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fpadd.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpadd.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpadd_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpadd_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpadd.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpadd.cmp"] 10 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "FIFO" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fifo_32.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_32.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_32_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_32_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_32.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fifo_32.cmp"] 10 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTFP_MULT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fpmult.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpmult.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpmult_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpmult_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpmult.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpmult.cmp"] 10 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dpram_16x32.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_16x32.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_16x32_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_16x32_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_16x32.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_16x32.cmp"] 10 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc.cmp: -------------------------------------------------------------------------------- 1 | component fpacc is 2 | port ( 3 | clk : in std_logic := 'X'; -- clk 4 | areset : in std_logic := 'X'; -- reset 5 | x : in std_logic_vector(31 downto 0) := (others => 'X'); -- x 6 | n : in std_logic := 'X'; -- n 7 | r : out std_logic_vector(31 downto 0); -- r 8 | xo : out std_logic; -- xo 9 | xu : out std_logic; -- xu 10 | ao : out std_logic; -- ao 11 | en : in std_logic_vector(0 downto 0) := (others => 'X') -- en 12 | ); 13 | end component fpacc; 14 | 15 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fpacc" -library "lib_fpacc" -name IP_TOOL_NAME "altera_fp_acc_custom" 2 | set_global_assignment -entity "fpacc" -library "lib_fpacc" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "fpacc" -library "lib_fpacc" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "lib_fpacc" -name SPD_FILE [file join $::quartus(sip_path) "fpacc.spd"] 5 | 6 | set_global_assignment -library "lib_fpacc" -name MISC_FILE [file join $::quartus(sip_path) "fpacc_sim/dspba_library_package.vhd"] 7 | set_global_assignment -library "lib_fpacc" -name MISC_FILE [file join $::quartus(sip_path) "fpacc_sim/dspba_library.vhd"] 8 | set_global_assignment -library "lib_fpacc" -name MISC_FILE [file join $::quartus(sip_path) "fpacc_sim/fpacc.vhd"] 9 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dpram_256x32.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_256x32.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_256x32_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_256x32_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_256x32.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_256x32.cmp"] 10 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "dpram_4096x32.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_4096x32.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_4096x32_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_4096x32_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_4096x32.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "dpram_4096x32.cmp"] 10 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "spram_4096x32.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spram_4096x32.bsf"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spram_4096x32_inst.v"] 7 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spram_4096x32_bb.v"] 8 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spram_4096x32.inc"] 9 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "spram_4096x32.cmp"] 10 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION fpadd 17 | ( 18 | aclr, 19 | clk_en, 20 | clock, 21 | dataa[31..0], 22 | datab[31..0] 23 | ) 24 | 25 | RETURNS ( 26 | result[31..0] 27 | ); 28 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION fpmult 17 | ( 18 | aclr, 19 | clk_en, 20 | clock, 21 | dataa[31..0], 22 | datab[31..0] 23 | ) 24 | 25 | RETURNS ( 26 | result[31..0] 27 | ); 28 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION spram_4096x32 17 | ( 18 | address[11..0], 19 | clock, 20 | data[31..0], 21 | wren 22 | ) 23 | 24 | RETURNS ( 25 | q[31..0] 26 | ); 27 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION fifo_32 17 | ( 18 | aclr, 19 | clock, 20 | data[31..0], 21 | rdreq, 22 | wrreq 23 | ) 24 | 25 | RETURNS ( 26 | empty, 27 | full, 28 | q[31..0], 29 | usedw[7..0] 30 | ); 31 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION dpram_16x32 17 | ( 18 | clock, 19 | data[31..0], 20 | enable, 21 | rdaddress[3..0], 22 | wraddress[3..0], 23 | wren 24 | ) 25 | 26 | RETURNS ( 27 | q[31..0] 28 | ); 29 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION dpram_256x32 17 | ( 18 | aclr, 19 | clock, 20 | data[31..0], 21 | enable, 22 | rdaddress[7..0], 23 | wraddress[7..0], 24 | wren 25 | ) 26 | 27 | RETURNS ( 28 | q[31..0] 29 | ); 30 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 0x5b25 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32.inc: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | FUNCTION dpram_4096x32 17 | ( 18 | address_a[11..0], 19 | address_b[11..0], 20 | clock_a, 21 | clock_b, 22 | data_a[31..0], 23 | data_b[31..0], 24 | rden_a, 25 | rden_b, 26 | wren_a, 27 | wren_b 28 | ) 29 | 30 | RETURNS ( 31 | q_a[31..0], 32 | q_b[31..0] 33 | ); 34 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component spram_4096x32 17 | PORT 18 | ( 19 | address : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 20 | clock : IN STD_LOGIC := '1'; 21 | data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 22 | wren : IN STD_LOGIC ; 23 | q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 24 | ); 25 | end component; 26 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component fpadd 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC ; 20 | clk_en : IN STD_LOGIC ; 21 | clock : IN STD_LOGIC ; 22 | dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 23 | datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 24 | result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component fpmult 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC ; 20 | clk_en : IN STD_LOGIC ; 21 | clock : IN STD_LOGIC ; 22 | dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 23 | datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 24 | result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 25 | ); 26 | end component; 27 | -------------------------------------------------------------------------------- /instructions.txt: -------------------------------------------------------------------------------- 1 | reset //stop all operations and reset system 2 | 8 3 | 4 | load len [src(r0)] dst //load data from external to internal buffer 5 | 8 12 12 6 | 7 | store len src [dst(r0)] //store internal buffer to external 8 | 8 12 12 9 | 10 | loadweight width height src //load weight data from internal buffer to processing array 11 | 8 4 4 16 12 | 13 | doconv | ldp | tobuf //do convolution calculation, uses conv descriptor: 14 | 8 | 1 | 1 15 | conv descriptor: 16 | +----------+----------+-------------+ 17 | r0 | Height | Width | | 18 | +----------+----------+ Input data | 19 | r1 | Pointer | | 20 | +----------+----------+-------------+ 21 | r2 | Height | Width | | 22 | +----------+----------+ Weight data | 23 | r3 | Pointer | | 24 | +----------+----------+-------------+ 25 | r4 | Data | Bias data | 26 | +---------------------+-------------+ 27 | r5 | Pointer | Destination | 28 | +---------------------+-------------+ 29 | 30 | 31 | 0 - 15: gpregs 32 | 16:instruction register 33 | 17:config register 34 | 18:status register -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component dpram_16x32 17 | PORT 18 | ( 19 | clock : IN STD_LOGIC := '1'; 20 | data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 21 | enable : IN STD_LOGIC := '1'; 22 | rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 23 | wraddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0); 24 | wren : IN STD_LOGIC := '0'; 25 | q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 26 | ); 27 | end component; 28 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component fifo_32 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC ; 20 | clock : IN STD_LOGIC ; 21 | data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 22 | rdreq : IN STD_LOGIC ; 23 | wrreq : IN STD_LOGIC ; 24 | empty : OUT STD_LOGIC ; 25 | full : OUT STD_LOGIC ; 26 | q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); 27 | usedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 28 | ); 29 | end component; 30 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component dpram_256x32 17 | PORT 18 | ( 19 | aclr : IN STD_LOGIC := '0'; 20 | clock : IN STD_LOGIC := '1'; 21 | data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 22 | enable : IN STD_LOGIC := '1'; 23 | rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 24 | wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0); 25 | wren : IN STD_LOGIC := '0'; 26 | q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 27 | ); 28 | end component; 29 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE altera ./libraries/altera/ 13 | DEFINE lpm ./libraries/lpm/ 14 | DEFINE sgate ./libraries/sgate/ 15 | DEFINE altera_mf ./libraries/altera_mf/ 16 | DEFINE altera_lnsim ./libraries/altera_lnsim/ 17 | DEFINE stratixiv_hssi ./libraries/stratixiv_hssi/ 18 | DEFINE stratixiv_pcie_hip ./libraries/stratixiv_pcie_hip/ 19 | DEFINE stratixiv ./libraries/stratixiv/ 20 | -------------------------------------------------------------------------------- /ProcessingCore.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 16:49:34 May 15, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "18.0" 26 | DATE = "16:49:34 May 15, 2019" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "ProcessingCore" 31 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32.cmp: -------------------------------------------------------------------------------- 1 | --Copyright (C) 2018 Intel Corporation. All rights reserved. 2 | --Your use of Intel Corporation's design tools, logic functions 3 | --and other software and tools, and its AMPP partner logic 4 | --functions, and any output files from any of the foregoing 5 | --(including device programming or simulation files), and any 6 | --associated documentation or information are expressly subject 7 | --to the terms and conditions of the Intel Program License 8 | --Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | --the Intel FPGA IP License Agreement, or other applicable license 10 | --agreement, including, without limitation, that your use is for 11 | --the sole purpose of programming logic devices manufactured by 12 | --Intel and sold by Intel or its authorized distributors. Please 13 | --refer to the applicable agreement for further details. 14 | 15 | 16 | component dpram_4096x32 17 | PORT 18 | ( 19 | address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 20 | address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); 21 | clock_a : IN STD_LOGIC := '1'; 22 | clock_b : IN STD_LOGIC ; 23 | data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 24 | data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); 25 | rden_a : IN STD_LOGIC := '1'; 26 | rden_b : IN STD_LOGIC := '1'; 27 | wren_a : IN STD_LOGIC := '0'; 28 | wren_b : IN STD_LOGIC := '0'; 29 | q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); 30 | q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) 31 | ); 32 | end component; 33 | -------------------------------------------------------------------------------- /procControl.sv: -------------------------------------------------------------------------------- 1 | //Processing unit control module 2 | module procControl( 3 | input clock, 4 | input reset, 5 | 6 | input [23:0] confin_i, 7 | input confvalid_i, 8 | output [23:0] confout_o 9 | ); 10 | //Config 11 | // +--------------------+ 12 | // | Enable | [23] 1 bit Enable this proc unit 13 | // +--------------------+ 14 | // | Psum input | [22] 1 bit Whether this proc unit shall accept psum from subsequent proc unit 15 | // +--------------------+ 16 | // | Psum output | [21] 1 bit 0:Psum to previous proc unit; 1:Psum to output mux 17 | // +--------------------+ 18 | // | In-cache mode | [20] 1 bit Whether use data inside cache or wait for new data input 19 | // +--------------------+ 20 | // | Weight row length | [19:16] 4 bit 21 | // +--------------------+ 22 | // | Cache valid length | [15:8] 8 bit Used with In-cache mode together to mark valid cache length 23 | // +--------------------+ 24 | // | PC ID | [7:0] 8 bit 25 | // +--------------------+ 26 | // 27 | 28 | reg enable; 29 | reg pinput; 30 | reg poutput; 31 | reg incache; 32 | reg [3:0] weightlen; 33 | reg [7:0] cachelen; 34 | reg [7:0] id; 35 | 36 | assign confout_o = { 37 | enable, 38 | pinput, 39 | poutput, 40 | incache, 41 | weightlen, 42 | cachelen, 43 | id 44 | }; 45 | 46 | always@(posedge clock or posedge reset) begin 47 | if(reset) begin 48 | enable <= 0; 49 | pinput <= 0; 50 | poutput <= 0; 51 | incache <= 0; 52 | weightlen <= 0; 53 | cachelen <= 0; 54 | id <= 0; 55 | end 56 | else begin 57 | if(confvalid_i) begin 58 | { 59 | enable, 60 | pinput, 61 | poutput, 62 | incache, 63 | weightlen, 64 | cachelen, 65 | id 66 | } <= confin_i; 67 | end 68 | end 69 | end 70 | 71 | endmodule -------------------------------------------------------------------------------- /procRegs.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ps/1ps 2 | module procRegs( 3 | input clock, 4 | input reset, 5 | 6 | input [4:0] addr_i, 7 | input [31:0] wrdata_i, 8 | output reg [31:0] rddata_o, 9 | input wren_i, 10 | 11 | output [31:0] gp[16], 12 | output [31:0] inst, 13 | output [31:0] conf, 14 | output reg inst_val, 15 | input [31:0] stat 16 | ); 17 | //General purpose registers 18 | reg [31:0] gpregs[16]; 19 | assign gp = gpregs; 20 | 21 | //Instruction register 22 | reg [31:0] ireg; 23 | assign inst = ireg; 24 | 25 | //Config register 26 | reg [31:0] creg; 27 | assign conf = creg; 28 | 29 | //Status, read only 30 | wire [31:0] stats; 31 | assign stats = stat; 32 | 33 | always begin 34 | #1; 35 | //Read data decoder 36 | if(addr_i[4] == 0) begin 37 | rddata_o <= gpregs[addr_i[3:0]]; 38 | end else 39 | begin 40 | case(addr_i[3:0]) 41 | 0:rddata_o <= ireg; 42 | 1:rddata_o <= creg; 43 | 2:rddata_o <= stats; 44 | default:rddata_o <= 32'h1CECAFFE; 45 | endcase 46 | end 47 | end 48 | 49 | always@(posedge clock, posedge reset) begin 50 | if(reset) begin 51 | creg = 0; 52 | inst_val = 0; 53 | end 54 | else begin 55 | inst_val = 0; 56 | if(wren_i) begin 57 | // 58 | if(addr_i[4] == 0) begin 59 | gpregs[addr_i[3:0]] = wrdata_i; 60 | end else 61 | begin 62 | case(addr_i[3:0]) 63 | 0:begin ireg = wrdata_i; inst_val = 1;end 64 | 1:begin creg = wrdata_i; end 65 | //2:begin stats = wrdata_i; end 66 | endcase 67 | end 68 | end 69 | end 70 | end 71 | 72 | endmodule -------------------------------------------------------------------------------- /ProcessingCore.ipregen.rpt: -------------------------------------------------------------------------------- 1 | IP Upgrade report for ProcessingCore 2 | Sun Jun 02 20:42:06 2019 3 | Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. IP Upgrade Summary 11 | 3. IP Upgrade Messages 12 | 13 | 14 | 15 | ---------------- 16 | ; Legal Notice ; 17 | ---------------- 18 | Copyright (C) 2018 Intel Corporation. All rights reserved. 19 | Your use of Intel Corporation's design tools, logic functions 20 | and other software and tools, and its AMPP partner logic 21 | functions, and any output files from any of the foregoing 22 | (including device programming or simulation files), and any 23 | associated documentation or information are expressly subject 24 | to the terms and conditions of the Intel Program License 25 | Subscription Agreement, the Intel Quartus Prime License Agreement, 26 | the Intel FPGA IP License Agreement, or other applicable license 27 | agreement, including, without limitation, that your use is for 28 | the sole purpose of programming logic devices manufactured by 29 | Intel and sold by Intel or its authorized distributors. Please 30 | refer to the applicable agreement for further details. 31 | 32 | 33 | 34 | +--------------------------------------------------------------------------------+ 35 | ; IP Upgrade Summary ; 36 | +------------------------------+-------------------------------------------------+ 37 | ; IP Components Upgrade Status ; Failed - Sun Jun 02 20:42:06 2019 ; 38 | ; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Standard Edition ; 39 | ; Revision Name ; ProcessingCore ; 40 | ; Top-level Entity Name ; proc_top ; 41 | ; Family ; Stratix IV ; 42 | +------------------------------+-------------------------------------------------+ 43 | 44 | 45 | +---------------------+ 46 | ; IP Upgrade Messages ; 47 | +---------------------+ 48 | Info (23030): Evaluation of Tcl script d:/intelfpga/18.0/quartus/common/tcl/internal/ip_regen/ip_regen.tcl was successful 49 | Info: Quartus Prime Shell was successful. 0 errors, 0 warnings 50 | Info: Peak virtual memory: 5167 megabytes 51 | Info: Processing ended: Sun Jun 02 20:42:08 2019 52 | Info: Elapsed time: 00:00:31 53 | Info: Total CPU time (on all processors): 00:00:34 54 | 55 | 56 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim/dspba_library_package.vhd: -------------------------------------------------------------------------------- 1 | -- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions and other 3 | -- software and tools, and its AMPP partner logic functions, and any output 4 | -- files any of the foregoing device programming or simulation files), and 5 | -- any associated documentation or information are expressly subject to the 6 | -- terms and conditions of the Intel FPGA Software License Agreement, 7 | -- Intel MegaCore Function License Agreement, or other applicable license 8 | -- agreement, including, without limitation, that your use is for the sole 9 | -- purpose of programming logic devices manufactured by Intel and sold by 10 | -- Intel or its authorized distributors. Please refer to the applicable 11 | -- agreement for further details. 12 | 13 | 14 | library IEEE; 15 | use IEEE.std_logic_1164.all; 16 | 17 | package dspba_library_package is 18 | 19 | component dspba_delay is 20 | generic ( 21 | width : natural := 8; 22 | depth : natural := 1; 23 | reset_high : std_logic := '1'; 24 | reset_kind : string := "ASYNC" 25 | ); 26 | port ( 27 | clk : in std_logic; 28 | aclr : in std_logic; 29 | ena : in std_logic := '1'; 30 | xin : in std_logic_vector(width-1 downto 0); 31 | xout : out std_logic_vector(width-1 downto 0) 32 | ); 33 | end component; 34 | 35 | component dspba_sync_reg is 36 | generic ( 37 | width1 : natural := 8; 38 | width2 : natural := 8; 39 | depth : natural := 2; 40 | init_value : std_logic_vector; 41 | pulse_multiplier : natural := 1; 42 | counter_width : natural := 8; 43 | reset1_high : std_logic := '1'; 44 | reset2_high : std_logic := '1'; 45 | reset_kind : string := "ASYNC" 46 | ); 47 | port ( 48 | clk1 : in std_logic; 49 | aclr1 : in std_logic; 50 | ena : in std_logic_vector(0 downto 0); 51 | xin : in std_logic_vector(width1-1 downto 0); 52 | xout : out std_logic_vector(width1-1 downto 0); 53 | clk2 : in std_logic; 54 | aclr2 : in std_logic; 55 | sxout : out std_logic_vector(width2-1 downto 0) 56 | ); 57 | end component; 58 | 59 | component dspba_pipe is 60 | generic( 61 | num_bits : positive; 62 | num_stages : natural; 63 | init_value : std_logic := 'X' 64 | ); 65 | port( 66 | clk: in std_logic; 67 | d : in std_logic_vector(num_bits-1 downto 0); 68 | q : out std_logic_vector(num_bits-1 downto 0) 69 | ); 70 | end component dspba_pipe; 71 | 72 | end dspba_library_package; 73 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 224 192) 24 | (text "fpmult" (rect 95 -1 136 15)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 176 25 188)(font "Arial" )) 26 | (port 27 | (pt 0 48) 28 | (input) 29 | (text "dataa[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "dataa[31..0]" (rect 4 34 59 47)(font "Arial" (font_size 8))) 31 | (line (pt 0 48)(pt 80 48)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 64) 35 | (input) 36 | (text "datab[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 37 | (text "datab[31..0]" (rect 4 50 59 63)(font "Arial" (font_size 8))) 38 | (line (pt 0 64)(pt 80 64)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 80) 42 | (input) 43 | (text "clk_en" (rect 0 0 36 14)(font "Arial" (font_size 8))) 44 | (text "clk_en" (rect 4 66 33 79)(font "Arial" (font_size 8))) 45 | (line (pt 0 80)(pt 80 80)) 46 | ) 47 | (port 48 | (pt 0 96) 49 | (input) 50 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 51 | (text "clock" (rect 4 82 27 95)(font "Arial" (font_size 8))) 52 | (line (pt 0 96)(pt 80 96)) 53 | ) 54 | (port 55 | (pt 0 112) 56 | (input) 57 | (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) 58 | (text "aclr" (rect 4 98 20 111)(font "Arial" (font_size 8))) 59 | (line (pt 0 112)(pt 80 112)) 60 | ) 61 | (port 62 | (pt 224 48) 63 | (output) 64 | (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 65 | (text "result[31..0]" (rect 164 34 219 47)(font "Arial" (font_size 8))) 66 | (line (pt 224 48)(pt 144 48)(line_width 3)) 67 | ) 68 | (drawing 69 | (text "Clock cycles: 5" (rect 158 129 380 269)(font "Arial" )) 70 | (text "Single Precision" (rect 158 145 380 301)(font "Arial" )) 71 | (text "Exponent Width: 8" (rect 147 161 369 333)(font "Arial" )) 72 | (text "Mantissa Width: 23" (rect 144 177 366 365)(font "Arial" )) 73 | (line (pt 80 32)(pt 144 32)) 74 | (line (pt 144 32)(pt 144 128)) 75 | (line (pt 80 128)(pt 144 128)) 76 | (line (pt 80 32)(pt 80 128)) 77 | (line (pt 0 0)(pt 224 0)) 78 | (line (pt 224 0)(pt 224 192)) 79 | (line (pt 0 192)(pt 224 192)) 80 | (line (pt 0 0)(pt 0 192)) 81 | ) 82 | ) 83 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 184 264) 24 | (text "fpadd" (rect 78 0 114 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 248 25 260)(font "Arial" )) 26 | (port 27 | (pt 0 40) 28 | (input) 29 | (text "dataa[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 30 | (text "dataa[31..0]" (rect 20 33 75 46)(font "Arial" (font_size 8))) 31 | (line (pt 0 40)(pt 16 40)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 56) 35 | (input) 36 | (text "datab[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 37 | (text "datab[31..0]" (rect 20 49 75 62)(font "Arial" (font_size 8))) 38 | (line (pt 0 56)(pt 16 56)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 88) 42 | (input) 43 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 44 | (text "clock" (rect 20 81 43 94)(font "Arial" (font_size 8))) 45 | (line (pt 0 88)(pt 16 88)) 46 | ) 47 | (port 48 | (pt 0 104) 49 | (input) 50 | (text "clk_en" (rect 0 0 36 14)(font "Arial" (font_size 8))) 51 | (text "clk_en" (rect 20 97 49 110)(font "Arial" (font_size 8))) 52 | (line (pt 0 104)(pt 16 104)) 53 | ) 54 | (port 55 | (pt 0 120) 56 | (input) 57 | (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) 58 | (text "aclr" (rect 20 113 36 126)(font "Arial" (font_size 8))) 59 | (line (pt 0 120)(pt 16 120)) 60 | ) 61 | (port 62 | (pt 184 40) 63 | (output) 64 | (text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) 65 | (text "result[31..0]" (rect 108 33 163 46)(font "Arial" (font_size 8))) 66 | (line (pt 184 40)(pt 168 40)(line_width 3)) 67 | ) 68 | (drawing 69 | (text "Clock Cycles: 7" (rect 20 130 106 271)(font "Arial" )) 70 | (text "Single Precision" (rect 20 146 104 303)(font "Arial" )) 71 | (text "Exponent Width: 8" (rect 20 162 115 335)(font "Arial" )) 72 | (text "Mantissa Width: 23" (rect 20 178 118 367)(font "Arial" )) 73 | (text "Direction: Add" (rect 20 194 97 399)(font "Arial" )) 74 | (text "Optimization: Speed" (rect 20 210 121 431)(font "Arial" )) 75 | (line (pt 0 0)(pt 186 0)) 76 | (line (pt 186 0)(pt 186 266)) 77 | (line (pt 0 266)(pt 186 266)) 78 | (line (pt 0 0)(pt 0 266)) 79 | (line (pt 16 24)(pt 170 24)) 80 | (line (pt 170 24)(pt 170 242)) 81 | (line (pt 16 242)(pt 170 242)) 82 | (line (pt 16 24)(pt 16 242)) 83 | ) 84 | ) 85 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTERA_FP_ACC_CUSTOM v18.0% 2 | // GENERATION: XML 3 | // fpacc.v 4 | 5 | // Generated using ACDS version 18.0 614 6 | 7 | `timescale 1 ps / 1 ps 8 | module fpacc ( 9 | input wire clk, // clk.clk 10 | input wire areset, // areset.reset 11 | input wire [31:0] x, // x.x 12 | input wire n, // n.n 13 | output wire [31:0] r, // r.r 14 | output wire xo, // xo.xo 15 | output wire xu, // xu.xu 16 | output wire ao, // ao.ao 17 | input wire [0:0] en // en.en 18 | ); 19 | 20 | fpacc_0002 fpacc_inst ( 21 | .clk (clk), // clk.clk 22 | .areset (areset), // areset.reset 23 | .x (x), // x.x 24 | .n (n), // n.n 25 | .r (r), // r.r 26 | .xo (xo), // xo.xo 27 | .xu (xu), // xu.xu 28 | .ao (ao), // ao.ao 29 | .en (en) // en.en 30 | ); 31 | 32 | endmodule 33 | // Retrieval info: 34 | // 59 | // Retrieval info: 60 | // Retrieval info: 61 | // Retrieval info: 62 | // Retrieval info: 63 | // Retrieval info: 64 | // Retrieval info: 65 | // Retrieval info: 66 | // Retrieval info: 67 | // Retrieval info: 68 | // Retrieval info: 69 | // IPFS_FILES : fpacc.vo 70 | // RELATED_FILES: fpacc.v, dspba_library_package.vhd, dspba_library.vhd, fpacc_0002.vhd 71 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 176 184) 24 | (text "fifo_32" (rect 70 0 113 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 168 25 180)(font "Arial" )) 26 | (port 27 | (pt 0 48) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 20 41 69 54)(font "Arial" (font_size 8))) 31 | (line (pt 0 48)(pt 16 48)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 72) 35 | (input) 36 | (text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8))) 37 | (text "wrreq" (rect 20 65 48 78)(font "Arial" (font_size 8))) 38 | (line (pt 0 72)(pt 16 72)) 39 | ) 40 | (port 41 | (pt 0 88) 42 | (input) 43 | (text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8))) 44 | (text "rdreq" (rect 20 81 44 94)(font "Arial" (font_size 8))) 45 | (line (pt 0 88)(pt 16 88)) 46 | ) 47 | (port 48 | (pt 0 112) 49 | (input) 50 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 51 | (text "clock" (rect 20 105 43 118)(font "Arial" (font_size 8))) 52 | (line (pt 0 112)(pt 16 112)) 53 | ) 54 | (port 55 | (pt 0 136) 56 | (input) 57 | (text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8))) 58 | (text "aclr" (rect 20 129 36 142)(font "Arial" (font_size 8))) 59 | (line (pt 0 136)(pt 16 136)) 60 | ) 61 | (port 62 | (pt 176 48) 63 | (output) 64 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 65 | (text "q[31..0]" (rect 121 41 155 54)(font "Arial" (font_size 8))) 66 | (line (pt 176 48)(pt 160 48)(line_width 3)) 67 | ) 68 | (port 69 | (pt 176 72) 70 | (output) 71 | (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) 72 | (text "full" (rect 143 65 155 78)(font "Arial" (font_size 8))) 73 | (line (pt 176 72)(pt 160 72)) 74 | ) 75 | (port 76 | (pt 176 88) 77 | (output) 78 | (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) 79 | (text "empty" (rect 128 81 155 94)(font "Arial" (font_size 8))) 80 | (line (pt 176 88)(pt 160 88)) 81 | ) 82 | (port 83 | (pt 176 104) 84 | (output) 85 | (text "usedw[7..0]" (rect 0 0 68 14)(font "Arial" (font_size 8))) 86 | (text "usedw[7..0]" (rect 99 97 155 110)(font "Arial" (font_size 8))) 87 | (line (pt 176 104)(pt 160 104)(line_width 3)) 88 | ) 89 | (drawing 90 | (text "32 bits x 256 words" (rect 78 133 235 277)(font "Arial" )) 91 | (line (pt 16 124)(pt 160 124)) 92 | (line (pt 16 32)(pt 160 32)) 93 | (line (pt 160 32)(pt 160 169)) 94 | (line (pt 160 169)(pt 16 169)) 95 | (line (pt 16 169)(pt 16 32)) 96 | (line (pt 0 0)(pt 177 0)) 97 | (line (pt 177 0)(pt 177 187)) 98 | (line (pt 0 187)(pt 177 187)) 99 | (line (pt 0 0)(pt 0 187)) 100 | (line (pt 0 0)(pt 0 0)) 101 | (line (pt 0 0)(pt 0 0)) 102 | (line (pt 0 0)(pt 0 0)) 103 | (line (pt 0 0)(pt 0 0)) 104 | ) 105 | ) 106 | -------------------------------------------------------------------------------- /ip/fpadd/fpadd_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTFP_ADD_SUB%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altfp_add_sub 5 | 6 | // ============================================================ 7 | // File Name: fpadd.v 8 | // Megafunction Name(s): 9 | // altfp_add_sub 10 | // 11 | // Simulation Library Files(s): 12 | // lpm 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module fpadd ( 35 | aclr, 36 | clk_en, 37 | clock, 38 | dataa, 39 | datab, 40 | result)/* synthesis synthesis_clearbox = 1 */; 41 | 42 | input aclr; 43 | input clk_en; 44 | input clock; 45 | input [31:0] dataa; 46 | input [31:0] datab; 47 | output [31:0] result; 48 | 49 | endmodule 50 | 51 | // ============================================================ 52 | // CNX file retrieval info 53 | // ============================================================ 54 | // Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0" 55 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 56 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 57 | // Retrieval info: PRIVATE: WIDTH_DATA NUMERIC "32" 58 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 59 | // Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO" 60 | // Retrieval info: CONSTANT: DIRECTION STRING "ADD" 61 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 62 | // Retrieval info: CONSTANT: OPTIMIZE STRING "SPEED" 63 | // Retrieval info: CONSTANT: PIPELINE NUMERIC "7" 64 | // Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO" 65 | // Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8" 66 | // Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23" 67 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" 68 | // Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en" 69 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 70 | // Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]" 71 | // Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]" 72 | // Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]" 73 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 74 | // Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0 75 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 76 | // Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 77 | // Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 78 | // Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 79 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd.v TRUE 80 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd.inc TRUE 81 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd.cmp TRUE 82 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd.bsf TRUE 83 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd_inst.v TRUE 84 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpadd_bb.v TRUE 85 | // Retrieval info: LIB_FILE: lpm 86 | -------------------------------------------------------------------------------- /procUnit.sv: -------------------------------------------------------------------------------- 1 | module procUnit 2 | #( 3 | parameter WDATA_ROW_LEN = 16 4 | ) 5 | ( 6 | input clock, 7 | input reset, 8 | 9 | input [31:0] weights[WDATA_ROW_LEN], 10 | 11 | //Config streaming 12 | input [23:0] confin_i, 13 | input confvalid_i, 14 | output [23:0] confout_o, 15 | 16 | //Route connections 17 | //Pipeline stall signal chain 18 | input stall_omux_i, //stall chain input, ignored when psum_output is disabled 19 | //input stall_prev_i, //stall signal from previous chain node, ignored when psum_output is enabled 20 | //output stall_router_o, //stall signal output to next chain node and calculation core 21 | 22 | //Broadcast receiver 23 | input [39:0] broadcastdata_i, 24 | input broadcastvalid_i, 25 | output broadcaststall_o, // flag indicates core is stalled and can't receive new data 26 | 27 | //Psum data routing 28 | input [39:0] psum_i, 29 | input psum_valid_i, 30 | output [39:0] psum_o, 31 | output psum_to_prev_valid_o, 32 | output psum_to_omux_valid_o, 33 | 34 | //Psum data integrity features 35 | input psum_can_send_i, //From previous node, whether we can send psum to that node 36 | output psum_can_accept_o //To subsequent node(s), whether we can accept psum input 37 | 38 | ); 39 | wire [31:0] fifodatain; 40 | wire fifowrite; 41 | 42 | wire fifofull; 43 | wire fifoempty; 44 | wire [31:0] fifodataout; 45 | wire fiforead; 46 | 47 | assign broadcaststall_o = fifofull; 48 | 49 | fifo_32 accfifo( 50 | .aclr(reset), 51 | .clock(clock), 52 | .data(fifodatain), 53 | .rdreq(fiforead), 54 | .wrreq(fifowrite), 55 | .empty(fifoempty), 56 | .full(fifofull), 57 | .q(fifodataout), 58 | .usedw() 59 | ); 60 | 61 | procControl ctrl( 62 | .clock(clock), 63 | .reset(reset), 64 | .confin_i(confin_i), 65 | .confvalid_i(confvalid_i), 66 | .confout_o(confout_o) 67 | ); 68 | 69 | procRouter router( 70 | .clock(clock), 71 | .reset(reset), 72 | //Pipeline stall signal chain 73 | .stall_omux_i(stall_omux_i), //stall chain input, ignored when psum_output is disabled 74 | //.stall_prev_i(stall_prev_i), //stall signal from previous chain node, ignored when psum_output is enabled 75 | //.stall_o(stall_router_o), //stall signal output to next chain node and calculation core 76 | 77 | //Psum data routing 78 | .psum_i(psum_i), 79 | .psum_valid_i(psum_valid_i), 80 | .psum_o(psum_o), 81 | .psum_to_prev_valid_o(psum_to_prev_valid_o), 82 | .psum_to_omux_valid_o(psum_to_omux_valid_o), 83 | 84 | //Psum data integrity features 85 | .psum_can_send_i(psum_can_send_i), //From previous node, whether we can send psum to that node 86 | .psum_can_accept_o(psum_can_accept_o), //To subsequent node(s), whether we can accept psum input 87 | 88 | //Config input 89 | .conf_i(confout_o), 90 | 91 | //Connection to calculation core 92 | 93 | //Acc result FIFO read 94 | .fifo_empty_i(fifoempty), 95 | .fifo_rdreq_o(fiforead), 96 | .fifo_rddata_i(fifodataout) 97 | 98 | ); 99 | 100 | wire accdata_valid; 101 | assign fifowrite = accdata_valid && !fifofull; 102 | 103 | wire [31:0] data = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastdata_i[31:0] : 32'b0; 104 | wire datavalid = broadcastdata_i[39:32] == confout_o[7:0] ? broadcastvalid_i : 1'b0; 105 | 106 | procCore#( 107 | .WDATA_ROW_LEN(WDATA_ROW_LEN) 108 | ) core( 109 | .clock(clock), 110 | .reset(reset), 111 | .conf_i(confout_o), 112 | .weights(weights), 113 | .data_i(data), 114 | .datavalid_i(datavalid), 115 | .stall_i(fifofull), 116 | .accresvalid_o(accdata_valid), 117 | .accres_o(fifodatain) 118 | ); 119 | 120 | 121 | endmodule -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 216 128) 24 | (text "spram_4096x32" (rect 62 0 170 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 112 25 124)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 4 18 53 31)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 88 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8))) 37 | (text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 88 48)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "address[11..0]" (rect 0 0 81 14)(font "Arial" (font_size 8))) 44 | (text "address[11..0]" (rect 4 50 71 63)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 88 64)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 112) 49 | (input) 50 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 51 | (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) 52 | (line (pt 0 112)(pt 80 112)) 53 | ) 54 | (port 55 | (pt 216 32) 56 | (output) 57 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 58 | (text "q[31..0]" (rect 177 18 211 31)(font "Arial" (font_size 8))) 59 | (line (pt 216 32)(pt 136 32)(line_width 3)) 60 | ) 61 | (drawing 62 | (text "32 bits" (rect 109 24 194 159)(font "Arial" )(vertical)) 63 | (text "4096 words" (rect 120 12 214 177)(font "Arial" )(vertical)) 64 | (text "Block type: M144K" (rect 48 114 174 239)(font "Arial" )) 65 | (line (pt 104 24)(pt 136 24)) 66 | (line (pt 136 24)(pt 136 96)) 67 | (line (pt 136 96)(pt 104 96)) 68 | (line (pt 104 96)(pt 104 24)) 69 | (line (pt 118 58)(pt 123 63)) 70 | (line (pt 118 62)(pt 123 57)) 71 | (line (pt 88 27)(pt 96 27)) 72 | (line (pt 96 27)(pt 96 39)) 73 | (line (pt 96 39)(pt 88 39)) 74 | (line (pt 88 39)(pt 88 27)) 75 | (line (pt 88 34)(pt 90 36)) 76 | (line (pt 90 36)(pt 88 38)) 77 | (line (pt 80 36)(pt 88 36)) 78 | (line (pt 96 32)(pt 104 32)(line_width 3)) 79 | (line (pt 88 43)(pt 96 43)) 80 | (line (pt 96 43)(pt 96 55)) 81 | (line (pt 96 55)(pt 88 55)) 82 | (line (pt 88 55)(pt 88 43)) 83 | (line (pt 88 50)(pt 90 52)) 84 | (line (pt 90 52)(pt 88 54)) 85 | (line (pt 80 52)(pt 88 52)) 86 | (line (pt 96 48)(pt 104 48)) 87 | (line (pt 88 59)(pt 96 59)) 88 | (line (pt 96 59)(pt 96 71)) 89 | (line (pt 96 71)(pt 88 71)) 90 | (line (pt 88 71)(pt 88 59)) 91 | (line (pt 88 66)(pt 90 68)) 92 | (line (pt 90 68)(pt 88 70)) 93 | (line (pt 80 68)(pt 88 68)) 94 | (line (pt 96 64)(pt 104 64)(line_width 3)) 95 | (line (pt 80 112)(pt 80 36)) 96 | (line (pt 0 0)(pt 217 0)) 97 | (line (pt 217 0)(pt 217 130)) 98 | (line (pt 0 130)(pt 217 130)) 99 | (line (pt 0 0)(pt 0 130)) 100 | (line (pt 0 0)(pt 0 0)) 101 | (line (pt 0 0)(pt 0 0)) 102 | (line (pt 0 0)(pt 0 0)) 103 | (line (pt 0 0)(pt 0 0)) 104 | ) 105 | ) 106 | -------------------------------------------------------------------------------- /ip/fpmult/fpmult_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTFP_MULT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: ALTFP_MULT 5 | 6 | // ============================================================ 7 | // File Name: fpmult.v 8 | // Megafunction Name(s): 9 | // ALTFP_MULT 10 | // 11 | // Simulation Library Files(s): 12 | // lpm 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module fpmult ( 35 | aclr, 36 | clk_en, 37 | clock, 38 | dataa, 39 | datab, 40 | result)/* synthesis synthesis_clearbox = 1 */; 41 | 42 | input aclr; 43 | input clk_en; 44 | input clock; 45 | input [31:0] dataa; 46 | input [31:0] datab; 47 | output [31:0] result; 48 | 49 | endmodule 50 | 51 | // ============================================================ 52 | // CNX file retrieval info 53 | // ============================================================ 54 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 55 | // Retrieval info: PRIVATE: FPM_FORMAT STRING "Single" 56 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 57 | // Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "YES" 58 | // Retrieval info: CONSTANT: DENORMAL_SUPPORT STRING "NO" 59 | // Retrieval info: CONSTANT: EXCEPTION_HANDLING STRING "NO" 60 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED" 61 | // Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED" 62 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_mult" 63 | // Retrieval info: CONSTANT: PIPELINE NUMERIC "5" 64 | // Retrieval info: CONSTANT: REDUCED_FUNCTIONALITY STRING "NO" 65 | // Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST" 66 | // Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8" 67 | // Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23" 68 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" 69 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 70 | // Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en" 71 | // Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0 72 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 73 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 74 | // Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]" 75 | // Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 76 | // Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]" 77 | // Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 78 | // Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]" 79 | // Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 80 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult.v TRUE FALSE 81 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult.qip TRUE FALSE 82 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult.bsf TRUE TRUE 83 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult_inst.v TRUE TRUE 84 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult_bb.v TRUE TRUE 85 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult.inc TRUE TRUE 86 | // Retrieval info: GEN_FILE: TYPE_NORMAL fpmult.cmp TRUE TRUE 87 | // Retrieval info: LIB_FILE: lpm 88 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_TOOL_NAME "altera_fp_acc_custom" 2 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_TOOL_VERSION "18.0" 3 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_TOOL_ENV "mwpim" 4 | set_global_assignment -library "fpacc" -name MISC_FILE [file join $::quartus(qip_path) "fpacc.cmp"] 5 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_TARGETED_DEVICE_FAMILY "Stratix IV" 6 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_GENERATED_DEVICE_FAMILY "{Stratix IV}" 7 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_QSYS_MODE "UNKNOWN" 8 | set_global_assignment -name SYNTHESIS_ONLY_QIP ON 9 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_NAME "ZnBhY2M=" 10 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0FDQ19DVVNUT00=" 11 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 12 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_INTERNAL "Off" 13 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 14 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_VERSION "MTguMA==" 15 | set_global_assignment -entity "fpacc" -library "fpacc" -name IP_COMPONENT_DESCRIPTION "QW4gYXBwbGljYXRpb24tc3BlY2lmaWMgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IuIEEgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IgdGhhdCBjYW4gYmUgY3VzdG9taXplZCB0byB0aGUgcmVxdWlyZWQgcmFuZ2Ugb2YgaW5wdXQgYW5kIG91dHB1dCB2YWx1ZXMuIFRoZSBhY2N1bXVsYXRvciB3aWxsIGJlIGJ1aWx0IHRvIG9wZXJhdGUgYXQgdGhlIHRhcmdldCBmcmVxdWVuY3kgb24gdGhlIHRhcmdldCBkZXZpY2UgZmFtaWx5Lg==" 16 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_NAME "ZnBhY2NfMDAwMg==" 17 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_DISPLAY_NAME "QUxURVJBX0ZQX0FDQ19DVVNUT00=" 18 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_REPORT_HIERARCHY "Off" 19 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_INTERNAL "Off" 20 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u" 21 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_VERSION "MTguMA==" 22 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_DESCRIPTION "QW4gYXBwbGljYXRpb24tc3BlY2lmaWMgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IuIEEgZmxvYXRpbmcgcG9pbnQgYWNjdW11bGF0b3IgdGhhdCBjYW4gYmUgY3VzdG9taXplZCB0byB0aGUgcmVxdWlyZWQgcmFuZ2Ugb2YgaW5wdXQgYW5kIG91dHB1dCB2YWx1ZXMuIFRoZSBhY2N1bXVsYXRvciB3aWxsIGJlIGJ1aWx0IHRvIG9wZXJhdGUgYXQgdGhlIHRhcmdldCBmcmVxdWVuY3kgb24gdGhlIHRhcmdldCBkZXZpY2UgZmFtaWx5Lg==" 23 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "ZnBfZm9ybWF0::c2luZ2xl::RmxvYXRpbmcgcG9pbnQgZm9ybWF0" 24 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "ZnJlcXVlbmN5::MjAw::VGFyZ2V0IGZyZXF1ZW5jeQ==" 25 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "Z2VuX2VuYWJsZQ==::dHJ1ZQ==::R2VuZXJhdGUgYW4gZW5hYmxlIHBvcnQ=" 26 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "TVNCQQ==::MzI=::TVNCQQ==" 27 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "bWF4TVNCWA==::MTI=::bWF4TVNCWA==" 28 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "TFNCQQ==::LTI2::TFNCQQ==" 29 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==::U3RyYXRpeCBJVg==::c2VsZWN0ZWRfZGV2aWNlX2ZhbWlseQ==" 30 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=::Mg==::c2VsZWN0ZWRfZGV2aWNlX3NwZWVkZ3JhZGU=" 31 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_COMPONENT_PARAMETER "dmFsaWRhdGlvbl9mYWlsZWQ=::ZmFsc2U=::dmFsaWRhdGlvbl9mYWlsZWQ=" 32 | 33 | set_global_assignment -library "fpacc" -name VERILOG_FILE [file join $::quartus(qip_path) "fpacc.v"] 34 | set_global_assignment -library "fpacc" -name VHDL_FILE [file join $::quartus(qip_path) "fpacc/dspba_library_package.vhd"] 35 | set_global_assignment -library "fpacc" -name VHDL_FILE [file join $::quartus(qip_path) "fpacc/dspba_library.vhd"] 36 | set_global_assignment -library "fpacc" -name VHDL_FILE [file join $::quartus(qip_path) "fpacc/fpacc_0002.vhd"] 37 | 38 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_TOOL_NAME "altera_fp_acc_custom" 39 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_TOOL_VERSION "18.0" 40 | set_global_assignment -entity "fpacc_0002" -library "fpacc" -name IP_TOOL_ENV "mwpim" 41 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 256 152) 24 | (text "dpram_16x32" (rect 89 0 181 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 136 25 148)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 4 18 53 31)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 112 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wraddress[3..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) 37 | (text "wraddress[3..0]" (rect 4 34 80 47)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 112 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8))) 44 | (text "wren" (rect 4 50 28 63)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 112 64)) 46 | ) 47 | (port 48 | (pt 0 88) 49 | (input) 50 | (text "rdaddress[3..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) 51 | (text "rdaddress[3..0]" (rect 4 74 76 87)(font "Arial" (font_size 8))) 52 | (line (pt 0 88)(pt 112 88)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 112) 56 | (input) 57 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 58 | (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) 59 | (line (pt 0 112)(pt 104 112)) 60 | ) 61 | (port 62 | (pt 0 128) 63 | (input) 64 | (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) 65 | (text "enable" (rect 4 114 34 127)(font "Arial" (font_size 8))) 66 | (line (pt 0 128)(pt 48 128)) 67 | ) 68 | (port 69 | (pt 256 88) 70 | (output) 71 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 72 | (text "q[31..0]" (rect 217 74 251 87)(font "Arial" (font_size 8))) 73 | (line (pt 256 88)(pt 168 88)(line_width 3)) 74 | ) 75 | (drawing 76 | (text "16 Word(s)" (rect 137 -5 231 177)(font "Arial" )(vertical)) 77 | (text "RAM" (rect 148 -16 229 151)(font "Arial" )(vertical)) 78 | (text "Block Type: M9K" (rect 40 141 150 293)(font "Arial" )) 79 | (line (pt 128 24)(pt 168 24)) 80 | (line (pt 168 24)(pt 168 96)) 81 | (line (pt 168 96)(pt 128 96)) 82 | (line (pt 128 96)(pt 128 24)) 83 | (line (pt 112 27)(pt 120 27)) 84 | (line (pt 120 27)(pt 120 39)) 85 | (line (pt 120 39)(pt 112 39)) 86 | (line (pt 112 39)(pt 112 27)) 87 | (line (pt 112 34)(pt 114 36)) 88 | (line (pt 114 36)(pt 112 38)) 89 | (line (pt 104 36)(pt 112 36)) 90 | (line (pt 120 32)(pt 128 32)(line_width 3)) 91 | (line (pt 112 43)(pt 120 43)) 92 | (line (pt 120 43)(pt 120 55)) 93 | (line (pt 120 55)(pt 112 55)) 94 | (line (pt 112 55)(pt 112 43)) 95 | (line (pt 112 50)(pt 114 52)) 96 | (line (pt 114 52)(pt 112 54)) 97 | (line (pt 104 52)(pt 112 52)) 98 | (line (pt 120 48)(pt 128 48)(line_width 3)) 99 | (line (pt 112 59)(pt 120 59)) 100 | (line (pt 120 59)(pt 120 71)) 101 | (line (pt 120 71)(pt 112 71)) 102 | (line (pt 112 71)(pt 112 59)) 103 | (line (pt 112 66)(pt 114 68)) 104 | (line (pt 114 68)(pt 112 70)) 105 | (line (pt 104 68)(pt 112 68)) 106 | (line (pt 120 64)(pt 128 64)) 107 | (line (pt 112 83)(pt 120 83)) 108 | (line (pt 120 83)(pt 120 95)) 109 | (line (pt 120 95)(pt 112 95)) 110 | (line (pt 112 95)(pt 112 83)) 111 | (line (pt 112 90)(pt 114 92)) 112 | (line (pt 114 92)(pt 112 94)) 113 | (line (pt 104 92)(pt 112 92)) 114 | (line (pt 120 88)(pt 128 88)(line_width 3)) 115 | (line (pt 104 36)(pt 104 113)) 116 | (line (pt 0 0)(pt 257 0)) 117 | (line (pt 257 0)(pt 257 154)) 118 | (line (pt 0 154)(pt 257 154)) 119 | (line (pt 0 0)(pt 0 154)) 120 | (line (pt 0 0)(pt 0 0)) 121 | (line (pt 0 0)(pt 0 0)) 122 | (line (pt 0 0)(pt 0 0)) 123 | (line (pt 0 0)(pt 0 0)) 124 | ) 125 | ) 126 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 256 160) 24 | (text "dpram_256x32" (rect 86 0 186 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 144 25 156)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) 30 | (text "data[31..0]" (rect 4 18 53 31)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 112 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "wraddress[7..0]" (rect 0 0 92 14)(font "Arial" (font_size 8))) 37 | (text "wraddress[7..0]" (rect 4 34 80 47)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 112 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8))) 44 | (text "wren" (rect 4 50 28 63)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 112 64)) 46 | ) 47 | (port 48 | (pt 0 88) 49 | (input) 50 | (text "rdaddress[7..0]" (rect 0 0 87 14)(font "Arial" (font_size 8))) 51 | (text "rdaddress[7..0]" (rect 4 74 76 87)(font "Arial" (font_size 8))) 52 | (line (pt 0 88)(pt 112 88)(line_width 3)) 53 | ) 54 | (port 55 | (pt 0 112) 56 | (input) 57 | (text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8))) 58 | (text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8))) 59 | (line (pt 0 112)(pt 104 112)) 60 | ) 61 | (port 62 | (pt 0 128) 63 | (input) 64 | (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) 65 | (text "enable" (rect 4 114 34 127)(font "Arial" (font_size 8))) 66 | (line (pt 0 128)(pt 48 128)) 67 | ) 68 | (port 69 | (pt 200 160) 70 | (input) 71 | (text "aclr" (rect 0 0 14 21)(font "Arial" (font_size 8))(vertical)) 72 | (text "aclr" (rect 186 139 199 155)(font "Arial" (font_size 8))(vertical)) 73 | (line (pt 200 160)(pt 200 136)) 74 | ) 75 | (port 76 | (pt 256 88) 77 | (output) 78 | (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8))) 79 | (text "q[31..0]" (rect 217 74 251 87)(font "Arial" (font_size 8))) 80 | (line (pt 256 88)(pt 168 88)(line_width 3)) 81 | ) 82 | (drawing 83 | (text "256 Word(s)" (rect 137 -6 233 181)(font "Arial" )(vertical)) 84 | (text "RAM" (rect 148 -16 229 151)(font "Arial" )(vertical)) 85 | (text "Block Type: M9K" (rect 40 141 150 293)(font "Arial" )) 86 | (line (pt 128 24)(pt 168 24)) 87 | (line (pt 168 24)(pt 168 96)) 88 | (line (pt 168 96)(pt 128 96)) 89 | (line (pt 128 96)(pt 128 24)) 90 | (line (pt 112 27)(pt 120 27)) 91 | (line (pt 120 27)(pt 120 39)) 92 | (line (pt 120 39)(pt 112 39)) 93 | (line (pt 112 39)(pt 112 27)) 94 | (line (pt 112 34)(pt 114 36)) 95 | (line (pt 114 36)(pt 112 38)) 96 | (line (pt 104 36)(pt 112 36)) 97 | (line (pt 120 32)(pt 128 32)(line_width 3)) 98 | (line (pt 112 43)(pt 120 43)) 99 | (line (pt 120 43)(pt 120 55)) 100 | (line (pt 120 55)(pt 112 55)) 101 | (line (pt 112 55)(pt 112 43)) 102 | (line (pt 112 50)(pt 114 52)) 103 | (line (pt 114 52)(pt 112 54)) 104 | (line (pt 104 52)(pt 112 52)) 105 | (line (pt 120 48)(pt 128 48)(line_width 3)) 106 | (line (pt 112 59)(pt 120 59)) 107 | (line (pt 120 59)(pt 120 71)) 108 | (line (pt 120 71)(pt 112 71)) 109 | (line (pt 112 71)(pt 112 59)) 110 | (line (pt 112 66)(pt 114 68)) 111 | (line (pt 114 68)(pt 112 70)) 112 | (line (pt 104 68)(pt 112 68)) 113 | (line (pt 120 64)(pt 128 64)) 114 | (line (pt 112 83)(pt 120 83)) 115 | (line (pt 120 83)(pt 120 95)) 116 | (line (pt 120 95)(pt 112 95)) 117 | (line (pt 112 95)(pt 112 83)) 118 | (line (pt 112 90)(pt 114 92)) 119 | (line (pt 114 92)(pt 112 94)) 120 | (line (pt 104 92)(pt 112 92)) 121 | (line (pt 120 88)(pt 128 88)(line_width 3)) 122 | (line (pt 116 95)(pt 116 99)) 123 | (line (pt 104 36)(pt 104 113)) 124 | (line (pt 0 0)(pt 257 0)) 125 | (line (pt 257 0)(pt 257 161)) 126 | (line (pt 0 161)(pt 257 161)) 127 | (line (pt 0 0)(pt 0 161)) 128 | (line (pt 0 0)(pt 0 0)) 129 | (line (pt 0 0)(pt 0 0)) 130 | (line (pt 0 0)(pt 0 0)) 131 | (line (pt 0 0)(pt 0 0)) 132 | ) 133 | ) 134 | -------------------------------------------------------------------------------- /proc_top.sv: -------------------------------------------------------------------------------- 1 | module proc_top 2 | #( 3 | parameter ARRAY_COL_NUM = 16, 4 | parameter ARRAY_ROW_NUM = 4, 5 | parameter WDATA_ROW_LEN = 16 6 | ) 7 | ( 8 | input clock, 9 | input reset, 10 | 11 | //Avalon slave 12 | input [6:2] avs_address_i, 13 | input [31:0] avs_writedata_i, 14 | output [31:0] avs_readdata_o, 15 | input avs_write_i, 16 | output avs_irq_o, 17 | 18 | //Avalon dma master 19 | output [31:0] avm_address_o, 20 | output [31:0] avm_writedata_o, 21 | input [31:0] avm_readdata_i, 22 | output avm_read_o, 23 | output avm_write_o, 24 | input avm_waitreq_i 25 | 26 | ); 27 | 28 | wire [31:0] gp[16]; 29 | wire [31:0] inst; 30 | wire [31:0] conf;//0:interrupt ena 31 | wire inst_val; 32 | wire [31:0] stat;//0:idle 33 | 34 | procRegs regs( 35 | .clock(clock), 36 | .reset(reset), 37 | 38 | .addr_i(avs_address_i), 39 | .wrdata_i(avs_writedata_i), 40 | .rddata_o(avs_readdata_o), 41 | .wren_i(avs_write_i), 42 | 43 | .gp(gp), 44 | .inst(inst), 45 | .conf(conf), 46 | .inst_val(inst_val), 47 | .stat(stat) 48 | ); 49 | 50 | wire reset_req; 51 | wire proc_reset = reset | reset_req; 52 | wire inst_done; 53 | assign avs_irq_o = inst_done & conf[0]; 54 | 55 | wire [31:0] ic_weightrow_writedata[WDATA_ROW_LEN]; 56 | wire ic_weightrow_cs; 57 | 58 | wire [39:0] ic_broadcast_writedata; 59 | wire ic_broadcast_cs; 60 | wire ic_broadcast_waitreq; //broadcast stall request 61 | 62 | wire [39:0] ic_psum_writedata;//psum row output 63 | wire ic_psum_cs; 64 | 65 | wire [23:0] ic_conf_writedata[ARRAY_COL_NUM]; 66 | wire ic_conf_cs; 67 | 68 | wire dma_cs; 69 | wire dma_wr; 70 | assign avm_read_o = dma_cs & ~dma_wr; 71 | assign avm_write_o = dma_cs & dma_wr; 72 | 73 | wire [31:0] sram_readdata; 74 | wire [31:0] sram_writedata; 75 | wire [11:0] sram_address; 76 | wire sram_wren; 77 | wire sram_rden; 78 | 79 | //sram write port 80 | wire [11:0] sres_address; 81 | wire [31:0] sres_writedata; 82 | wire sres_wren; 83 | 84 | procInstSchd 85 | #( 86 | .ARRAY_COL_NUM(ARRAY_COL_NUM), 87 | .ARRAY_ROW_NUM(ARRAY_ROW_NUM), 88 | .WDATA_ROW_LEN(WDATA_ROW_LEN) 89 | ) 90 | instschd( 91 | .clock(clock), 92 | .reset(reset), 93 | 94 | .reset_req_o(reset_req), 95 | .stat_idle_o(stat[0]), 96 | 97 | //Instruction interface 98 | .instruction_i(inst), 99 | .instruction_valid_i(inst_val), 100 | .instruction_done_o(inst_done), 101 | 102 | .gp(gp), 103 | 104 | //Connection between processing array 105 | .icm_weightrow_writedata_o(ic_weightrow_writedata), 106 | .icm_weightrow_cs_o(ic_weightrow_cs), 107 | 108 | .icm_broadcast_writedata_o(ic_broadcast_writedata), 109 | .icm_broadcast_cs_o(ic_broadcast_cs), 110 | .icm_broadcast_waitreq_i(ic_broadcast_waitreq), //broadcast stall request 111 | 112 | .ics_psum_writedata_i(ic_psum_writedata),//psum row output 113 | .ics_psum_cs_i(ic_psum_cs), 114 | 115 | .icm_conf_writedata_o(ic_conf_writedata), 116 | .icm_conf_cs_o(ic_conf_cs), 117 | 118 | //dma interface 119 | .icm_dma_readdata_i(avm_readdata_i), 120 | .icm_dma_writedata_o(avm_writedata_o), 121 | .icm_dma_address_o(avm_address_o), 122 | .icm_dma_cs_o(dma_cs), 123 | .icm_dma_write_o(dma_wr), 124 | .icm_dma_waitreq_i(avm_waitreq_i), 125 | 126 | //sram rw interface 127 | .sram_readdata_i(sram_readdata), 128 | .sram_writedata_o(sram_writedata), 129 | .sram_address_o(sram_address), 130 | .sram_wren_o(sram_wren), 131 | .sram_rden_o(sram_rden), 132 | 133 | //sram write port 134 | .sres_address_o(sres_address), 135 | .sres_writedata_o(sres_writedata), 136 | .sres_wren_o(sres_wren) 137 | ); 138 | 139 | procArray 140 | #( 141 | .ARRAY_COL_NUM(ARRAY_COL_NUM), 142 | .ARRAY_ROW_NUM(ARRAY_ROW_NUM), 143 | .WDATA_ROW_LEN(WDATA_ROW_LEN) 144 | ) 145 | proc( 146 | .clock(clock), 147 | .reset(proc_reset), 148 | 149 | .flush_weight_data_i(), 150 | 151 | //InterConn write-only master: row data output 152 | 153 | .icm_psum_writedata_o(ic_psum_writedata),//psum row output 154 | .icm_psum_cs_o(ic_psum_cs), 155 | 156 | //InterConn write-only slave:broadcast data input 157 | .ics_broadcast_writedata_i(ic_broadcast_writedata), 158 | .ics_broadcast_cs_i(ic_broadcast_cs), 159 | .ics_broadcast_waitreq_o(ic_broadcast_waitreq), //broadcast stall request 160 | 161 | //InterConn write-only slave:weight row data input 162 | .ics_weightrow_writedata_i(ic_weightrow_writedata), 163 | .ics_weightrow_cs_i(ic_weightrow_cs), 164 | 165 | //InterConn write-only slave:pu config data input 166 | .ics_conf_writedata_i(ic_conf_writedata), 167 | .ics_conf_cs_i(ic_conf_cs) 168 | 169 | ); 170 | 171 | dpram_4096x32 dbuf( 172 | .address_a(sram_address), 173 | .address_b(sres_address), 174 | .clock_a(clock), 175 | .clock_b(clock), 176 | .data_a(sram_writedata), 177 | .data_b(sres_writedata), 178 | .wren_a(sram_wren), 179 | .wren_b(sres_wren), 180 | .rden_a(sram_rden), 181 | .rden_b(0), 182 | .q_a(sram_readdata), 183 | .q_b() 184 | ); 185 | 186 | endmodule -------------------------------------------------------------------------------- /procRouter.sv: -------------------------------------------------------------------------------- 1 | /*TODO: Reduce long combinational logic chains*/ 2 | 3 | module procRouter( 4 | input clock, 5 | input reset, 6 | 7 | //Pipeline stall signal chain 8 | input stall_omux_i, //stall chain input, ignored when psum_output is disabled 9 | //output stall_o, //stall signal output to next chain node and calculation core 10 | 11 | //Psum data routing 12 | input [39:0] psum_i, 13 | input psum_valid_i, 14 | output [39:0] psum_o, 15 | output psum_to_prev_valid_o, 16 | output psum_to_omux_valid_o, 17 | 18 | //Psum data integrity features 19 | input psum_can_send_i, //From previous node, whether we can send psum to that node 20 | output psum_can_accept_o, //To subsequent node(s), whether we can accept psum input 21 | 22 | //Config input 23 | input [23:0] conf_i, 24 | 25 | //Connection to calculation core 26 | 27 | //Acc result FIFO read 28 | input fifo_empty_i, 29 | output fifo_rdreq_o, 30 | input [31:0] fifo_rddata_i 31 | ); 32 | wire stall_this_router; 33 | 34 | //config decode 35 | wire conf_enable; 36 | wire conf_psum_input; 37 | wire conf_psum_output; 38 | wire conf_incache; 39 | wire [3:0] conf_weightlen; 40 | wire [7:0] conf_cachelen; 41 | wire [7:0] conf_id; 42 | 43 | assign { 44 | conf_enable, 45 | conf_psum_input, 46 | conf_psum_output, 47 | conf_incache, 48 | conf_weightlen, 49 | conf_cachelen, 50 | conf_id 51 | } = conf_i; 52 | 53 | assign psum_o[39:32] = conf_id; 54 | //FIFO connection 55 | //Delay chain compensates for 1 cycle delay between rdreq and valid data output 56 | reg fifo_rdvaild_delay; 57 | always@(posedge clock or posedge reset) begin 58 | if(reset == 1) 59 | fifo_rdvaild_delay <= 0; 60 | else if(!stall_this_router) 61 | fifo_rdvaild_delay <= fifo_rdreq_o; 62 | end 63 | //In order to deliever the same group of data from fifo and subsequent psum 64 | //to the chain node adder at the same time, we need to buffer input psum for 1 65 | //cycle again, to compensate for 1 cycle delay from fifo 66 | reg [31:0] psum_input_delay; 67 | reg psum_input_valid_delay; 68 | always@(posedge clock or posedge reset) begin 69 | if(reset == 1) begin 70 | psum_input_delay <= 0; 71 | psum_input_valid_delay <= 0; 72 | end 73 | else if(!stall_this_router) begin 74 | psum_input_delay <= psum_i[31:0]; 75 | psum_input_valid_delay <= psum_valid_i; 76 | end 77 | end 78 | //read request management 79 | /* 80 | +---------+----------+------------------+--------------------------------------------------+ 81 | | | | | Read FIFO | 82 | | Psum in | Psum out | Condition +----------+---------------+-----------+-----------+ 83 | | | | | can send | Psum_in valid | not empty | not stall | 84 | +---------+----------+------------------+----------+---------------+-----------+-----------+ 85 | | 0 | 0 | Link end | 1 | 0 | 1 | 1 | 86 | +---------+----------+------------------+----------+---------------+-----------+-----------+ 87 | | 0 | 1 | Link with 1 node | 0 | 0 | 1 | 1 | 88 | +---------+----------+------------------+----------+---------------+-----------+-----------+ 89 | | 1 | 0 | Normal link node | 1 | 1 | 1 | 1 | 90 | +---------+----------+------------------+----------+---------------+-----------+-----------+ 91 | | 1 | 1 | Link head | 0 | 1 | 1 | 1 | 92 | +---------+----------+------------------+----------+---------------+-----------+-----------+ 93 | */ 94 | assign fifo_rdreq_o = (!fifo_empty_i) && (!stall_this_router) &&( 95 | (conf_psum_output || psum_can_send_i) && 96 | ((!conf_psum_input) || psum_valid_i) 97 | ); 98 | 99 | //Add chain 100 | //enable adder when accepts psum input and is enabled 101 | wire addchain_ena = conf_psum_input && !stall_this_router; 102 | wire [31:0] addchain_res; 103 | //Adder cycle: 7 104 | reg [6:0] addchain_res_valid_delay = 0; 105 | always@(posedge clock or posedge reset) begin 106 | if(reset == 1) 107 | addchain_res_valid_delay <= 0; 108 | else if(addchain_ena) 109 | addchain_res_valid_delay <= {addchain_res_valid_delay[5:0],psum_input_valid_delay && fifo_rdvaild_delay}; 110 | end 111 | fpadd add( 112 | .aclr(reset),//input aclr; 113 | .clk_en(addchain_ena),//input clk_en; 114 | .clock(clock),//input clock; 115 | .dataa(fifo_rddata_i),//input [31:0] dataa; 116 | .datab(psum_input_delay),//input [31:0] datab; 117 | .result(addchain_res)//output [31:0] result; 118 | ); 119 | 120 | //Data router 121 | //Psum output routing 122 | assign psum_o[31:0] = conf_psum_input == 1'b1 ? addchain_res : fifo_rddata_i; 123 | wire psum_valid = conf_psum_input == 1'b1 ? addchain_res_valid_delay[6] : fifo_rdvaild_delay; 124 | assign psum_to_prev_valid_o = conf_psum_output == 1'b1 ? 1'b0 : psum_valid; 125 | assign psum_to_omux_valid_o = conf_psum_output == 1'b1 ? psum_valid : 1'b0; 126 | assign psum_can_accept_o = conf_psum_input == 1'b1 ? !((fifo_empty_i || stall_this_router)&& psum_valid_i) : 1'b0; 127 | 128 | //Stall signaling 129 | //Not only previous node stalled but also previous node can't accept psum input 130 | assign stall_this_router = !conf_enable || (conf_psum_output == 1 ? stall_omux_i : !psum_can_send_i); 131 | 132 | //Broadcast filtering 133 | 134 | 135 | endmodule -------------------------------------------------------------------------------- /procRow.sv: -------------------------------------------------------------------------------- 1 | module procRow 2 | #( 3 | parameter PU_ROW_LEN = 16, 4 | parameter WDATA_ROW_LEN = 16 5 | ) 6 | ( 7 | input clock, 8 | input reset, 9 | 10 | //weight data streaming interface 11 | input flush_weight_data_i, 12 | input [31:0] stream_from_prev_weightdata_i[WDATA_ROW_LEN], 13 | input stream_from_global_weightdata_valid_i, 14 | output [31:0] stream_to_next_weightdata_o[WDATA_ROW_LEN], 15 | 16 | //InterConn write-only slave:broadcast data input 17 | input [39:0] ics_broadcast_writedata_i, 18 | input ics_broadcast_cs_i, 19 | output ics_broadcast_waitreq_o, //broadcast stall request 20 | 21 | //InterConn write-only master: row psum data output 22 | output [39:0] icm_psum_writedata_o[PU_ROW_LEN],//psum row output 23 | output icm_psum_cs_o, 24 | output [PU_ROW_LEN - 1:0] icm_psum_wordenable_o,//Flag indicates valid pu words(40 bits) inside psum row output 25 | input icm_psum_waitreq_i, 26 | 27 | //Streaming interface: psum 28 | output [PU_ROW_LEN - 1:0] stream_to_prev_psum_valid_o, 29 | input [PU_ROW_LEN - 1:0] stream_from_next_psum_valid_i, 30 | input [39:0] stream_from_next_psum_data_i[PU_ROW_LEN], 31 | input [PU_ROW_LEN - 1:0] stream_from_prev_psum_can_send_i, 32 | output [PU_ROW_LEN - 1:0] stream_to_next_psum_can_send_o, 33 | 34 | //Streaming interface: config 35 | input stream_from_global_conf_valid_i, 36 | output [23:0] stream_to_next_conf_o[PU_ROW_LEN], 37 | input [23:0] stream_from_prev_conf_i[PU_ROW_LEN] 38 | 39 | //streaming interface: router stall signal chain 40 | //input [PU_ROW_LEN - 1:0] stream_from_prev_router_stall_i, 41 | //output [PU_ROW_LEN - 1:0] stream_to_next_router_stall_o 42 | ); 43 | 44 | 45 | reg [31:0] weightrow[WDATA_ROW_LEN]; 46 | assign stream_to_next_weightdata_o = weightrow; 47 | 48 | generate 49 | //buffer data streaming 50 | begin:wdata_stream_node 51 | always@(posedge clock or posedge flush_weight_data_i) begin 52 | if(flush_weight_data_i) begin 53 | integer flush_wl_body; 54 | for(flush_wl_body = 0; flush_wl_body < 16; flush_wl_body = flush_wl_body + 1) 55 | weightrow[flush_wl_body] <= 0; 56 | end 57 | else if(stream_from_global_weightdata_valid_i) 58 | weightrow <= stream_from_prev_weightdata_i; 59 | end 60 | end 61 | endgenerate 62 | 63 | //Broadcast signals 64 | wire [PU_ROW_LEN - 1:0] brostall_collector_input;//stall signal collector for each pu package in this row 65 | assign ics_broadcast_waitreq_o = |brostall_collector_input; 66 | 67 | //Row io signals 68 | wire [PU_ROW_LEN - 1:0] output_ready_collector_input; //row collector for psum valid signal 69 | wire [PU_ROW_LEN - 1:0] pu_enabled_collector_input; //row collector for psum valid signal 70 | assign icm_psum_cs_o = output_ready_collector_input == pu_enabled_collector_input && pu_enabled_collector_input != 0;//Every single pu inside current row's output is valid 71 | 72 | generate 73 | genvar x_it; 74 | for(x_it = 0; x_it < PU_ROW_LEN; x_it++) begin:pu_package 75 | wire [23:0] conf_data; 76 | assign stream_to_next_conf_o[x_it] = conf_data; 77 | //Psum output 78 | wire [39:0] psum; 79 | wire psum_to_prev_valid; 80 | wire psum_to_omux_valid; 81 | assign output_ready_collector_input[x_it] = psum_to_omux_valid; 82 | assign pu_enabled_collector_input[x_it] = conf_data[23]/*pu enable bit*/; 83 | assign icm_psum_wordenable_o[x_it] = psum_to_omux_valid; 84 | assign icm_psum_writedata_o[x_it] = psum; 85 | assign stream_to_prev_psum_valid_o[x_it] = psum_to_prev_valid; 86 | 87 | //Whether current node's router should stall 88 | wire stall_this_router = psum_to_omux_valid & (!icm_psum_cs_o/*sync all pu in the same row*/ || icm_psum_waitreq_i); 89 | 90 | //processing unit instance 91 | procUnit #( 92 | .WDATA_ROW_LEN(WDATA_ROW_LEN) 93 | ) pu_core( 94 | .clock(clock), 95 | .reset(reset), 96 | 97 | .weights(weightrow), 98 | 99 | //Config streaming 100 | .confin_i(stream_from_prev_conf_i[x_it]), 101 | .confvalid_i(stream_from_global_conf_valid_i), 102 | .confout_o(conf_data), 103 | 104 | //Route connections 105 | //Pipeline stall signal chain 106 | .stall_omux_i(stall_this_router), //stall chain input, ignored when psum_output is disabled 107 | //.stall_prev_i(stream_from_prev_router_stall_i[x_it]), //stall signal from previous chain node, ignored when psum_output is enabled 108 | //.stall_router_o(stream_to_next_router_stall_o[x_it]), //stall signal output to next chain node and calculation core 109 | 110 | //Broadcast receiver 111 | .broadcastdata_i(ics_broadcast_writedata_i), 112 | .broadcastvalid_i(ics_broadcast_cs_i), 113 | .broadcaststall_o(brostall_collector_input[x_it]), // flag indicates core is stalled and can't receive new data 114 | 115 | //Psum data routing 116 | .psum_i(stream_from_next_psum_data_i[x_it]), 117 | .psum_valid_i(stream_from_next_psum_valid_i[x_it]), 118 | .psum_o(psum), 119 | .psum_to_prev_valid_o(psum_to_prev_valid), 120 | .psum_to_omux_valid_o(psum_to_omux_valid), 121 | 122 | //Psum data integrity features 123 | .psum_can_send_i(stream_from_prev_psum_can_send_i[x_it]), //From previous node, whether we can send psum to that node 124 | .psum_can_accept_o(stream_to_next_psum_can_send_o[x_it]) //To subsequent node(s), whether we can accept psum input 125 | 126 | ); 127 | end //pu_package 128 | endgenerate 129 | 130 | endmodule -------------------------------------------------------------------------------- /ip/fpacc/fpacc.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 144 264) 24 | (text "fpacc" (rect 56 -1 78 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 248 20 260)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "clk" (rect 0 0 10 12)(font "Arial" (font_size 8))) 30 | (text "clk" (rect 4 61 22 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 48 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 0 112) 35 | (input) 36 | (text "areset" (rect 0 0 24 12)(font "Arial" (font_size 8))) 37 | (text "areset" (rect 4 101 40 112)(font "Arial" (font_size 8))) 38 | (line (pt 0 112)(pt 48 112)(line_width 1)) 39 | ) 40 | (port 41 | (pt 0 152) 42 | (input) 43 | (text "x[31..0]" (rect 0 0 28 12)(font "Arial" (font_size 8))) 44 | (text "x[31..0]" (rect 4 141 52 152)(font "Arial" (font_size 8))) 45 | (line (pt 0 152)(pt 48 152)(line_width 3)) 46 | ) 47 | (port 48 | (pt 0 192) 49 | (input) 50 | (text "n" (rect 0 0 4 12)(font "Arial" (font_size 8))) 51 | (text "n" (rect 4 181 10 192)(font "Arial" (font_size 8))) 52 | (line (pt 0 192)(pt 48 192)(line_width 1)) 53 | ) 54 | (port 55 | (pt 0 232) 56 | (input) 57 | (text "en" (rect 0 0 9 12)(font "Arial" (font_size 8))) 58 | (text "en" (rect 4 221 16 232)(font "Arial" (font_size 8))) 59 | (line (pt 0 232)(pt 48 232)(line_width 1)) 60 | ) 61 | (port 62 | (pt 144 72) 63 | (output) 64 | (text "r[31..0]" (rect 0 0 27 12)(font "Arial" (font_size 8))) 65 | (text "r[31..0]" (rect 110 61 158 72)(font "Arial" (font_size 8))) 66 | (line (pt 144 72)(pt 96 72)(line_width 3)) 67 | ) 68 | (port 69 | (pt 144 112) 70 | (output) 71 | (text "xo" (rect 0 0 9 12)(font "Arial" (font_size 8))) 72 | (text "xo" (rect 130 101 142 112)(font "Arial" (font_size 8))) 73 | (line (pt 144 112)(pt 96 112)(line_width 1)) 74 | ) 75 | (port 76 | (pt 144 152) 77 | (output) 78 | (text "xu" (rect 0 0 9 12)(font "Arial" (font_size 8))) 79 | (text "xu" (rect 130 141 142 152)(font "Arial" (font_size 8))) 80 | (line (pt 144 152)(pt 96 152)(line_width 1)) 81 | ) 82 | (port 83 | (pt 144 192) 84 | (output) 85 | (text "ao" (rect 0 0 9 12)(font "Arial" (font_size 8))) 86 | (text "ao" (rect 130 181 142 192)(font "Arial" (font_size 8))) 87 | (line (pt 144 192)(pt 96 192)(line_width 1)) 88 | ) 89 | (drawing 90 | (text "clk" (rect 33 43 84 99)(font "Arial" (color 128 0 0)(font_size 9))) 91 | (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) 92 | (text "areset" (rect 12 83 60 179)(font "Arial" (color 128 0 0)(font_size 9))) 93 | (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) 94 | (text "x" (rect 43 123 92 259)(font "Arial" (color 128 0 0)(font_size 9))) 95 | (text "x" (rect 53 147 112 304)(font "Arial" (color 0 0 0))) 96 | (text "n" (rect 42 163 90 339)(font "Arial" (color 128 0 0)(font_size 9))) 97 | (text "n" (rect 53 187 112 384)(font "Arial" (color 0 0 0))) 98 | (text "r" (rect 97 43 200 99)(font "Arial" (color 128 0 0)(font_size 9))) 99 | (text "r" (rect 89 67 184 144)(font "Arial" (color 0 0 0))) 100 | (text "xo" (rect 97 83 206 179)(font "Arial" (color 128 0 0)(font_size 9))) 101 | (text "xo" (rect 83 107 178 224)(font "Arial" (color 0 0 0))) 102 | (text "xu" (rect 97 123 206 259)(font "Arial" (color 128 0 0)(font_size 9))) 103 | (text "xu" (rect 83 147 178 304)(font "Arial" (color 0 0 0))) 104 | (text "ao" (rect 97 163 206 339)(font "Arial" (color 128 0 0)(font_size 9))) 105 | (text "ao" (rect 83 187 178 384)(font "Arial" (color 0 0 0))) 106 | (text "en" (rect 35 203 82 419)(font "Arial" (color 128 0 0)(font_size 9))) 107 | (text "en" (rect 53 227 118 464)(font "Arial" (color 0 0 0))) 108 | (text " altera_fp_acc_custom " (rect 44 248 220 506)(font "Arial" )) 109 | (line (pt 48 32)(pt 96 32)(line_width 1)) 110 | (line (pt 96 32)(pt 96 248)(line_width 1)) 111 | (line (pt 48 248)(pt 96 248)(line_width 1)) 112 | (line (pt 48 32)(pt 48 248)(line_width 1)) 113 | (line (pt 49 52)(pt 49 76)(line_width 1)) 114 | (line (pt 50 52)(pt 50 76)(line_width 1)) 115 | (line (pt 49 92)(pt 49 116)(line_width 1)) 116 | (line (pt 50 92)(pt 50 116)(line_width 1)) 117 | (line (pt 49 132)(pt 49 156)(line_width 1)) 118 | (line (pt 50 132)(pt 50 156)(line_width 1)) 119 | (line (pt 49 172)(pt 49 196)(line_width 1)) 120 | (line (pt 50 172)(pt 50 196)(line_width 1)) 121 | (line (pt 95 52)(pt 95 76)(line_width 1)) 122 | (line (pt 94 52)(pt 94 76)(line_width 1)) 123 | (line (pt 95 92)(pt 95 116)(line_width 1)) 124 | (line (pt 94 92)(pt 94 116)(line_width 1)) 125 | (line (pt 95 132)(pt 95 156)(line_width 1)) 126 | (line (pt 94 132)(pt 94 156)(line_width 1)) 127 | (line (pt 95 172)(pt 95 196)(line_width 1)) 128 | (line (pt 94 172)(pt 94 196)(line_width 1)) 129 | (line (pt 49 212)(pt 49 236)(line_width 1)) 130 | (line (pt 50 212)(pt 50 236)(line_width 1)) 131 | (line (pt 0 0)(pt 144 0)(line_width 1)) 132 | (line (pt 144 0)(pt 144 264)(line_width 1)) 133 | (line (pt 0 264)(pt 144 264)(line_width 1)) 134 | (line (pt 0 0)(pt 0 264)(line_width 1)) 135 | ) 136 | ) 137 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: scfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo_32.v 8 | // Megafunction Name(s): 9 | // scfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module fifo_32 ( 35 | aclr, 36 | clock, 37 | data, 38 | rdreq, 39 | wrreq, 40 | empty, 41 | full, 42 | q, 43 | usedw); 44 | 45 | input aclr; 46 | input clock; 47 | input [31:0] data; 48 | input rdreq; 49 | input wrreq; 50 | output empty; 51 | output full; 52 | output [31:0] q; 53 | output [7:0] usedw; 54 | 55 | endmodule 56 | 57 | // ============================================================ 58 | // CNX file retrieval info 59 | // ============================================================ 60 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 61 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 62 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 63 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 64 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" 65 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 66 | // Retrieval info: PRIVATE: Depth NUMERIC "256" 67 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 68 | // Retrieval info: PRIVATE: Full NUMERIC "1" 69 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 70 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 71 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 72 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 73 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 74 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 75 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 76 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 77 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 78 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 79 | // Retrieval info: PRIVATE: Width NUMERIC "32" 80 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" 81 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 82 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 83 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 84 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 85 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 86 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 87 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "1" 88 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 89 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 90 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 91 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" 94 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 95 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" 96 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" 97 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 98 | // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" 99 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 100 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" 101 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 102 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 103 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 104 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" 105 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 106 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 107 | // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" 108 | // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" 109 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 110 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 111 | // Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]" 112 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 113 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 114 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 116 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 117 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 118 | // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 119 | // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 120 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 121 | // Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.v TRUE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.inc TRUE 124 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.cmp TRUE 125 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.bsf TRUE 126 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32_inst.v TRUE 127 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32_bb.v TRUE 128 | // Retrieval info: LIB_FILE: altera_mf 129 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: spram_4096x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module spram_4096x32 ( 35 | address, 36 | clock, 37 | data, 38 | wren, 39 | q); 40 | 41 | input [11:0] address; 42 | input clock; 43 | input [31:0] data; 44 | input wren; 45 | output [31:0] q; 46 | `ifndef ALTERA_RESERVED_QIS 47 | // synopsys translate_off 48 | `endif 49 | tri1 clock; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_on 52 | `endif 53 | 54 | endmodule 55 | 56 | // ============================================================ 57 | // CNX file retrieval info 58 | // ============================================================ 59 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 60 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 61 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 62 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 63 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 64 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 65 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 66 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 67 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 70 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 71 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 72 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 73 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 74 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 75 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 76 | // Retrieval info: PRIVATE: JTAG_ID STRING "GBUF" 77 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 78 | // Retrieval info: PRIVATE: MIFfilename STRING "" 79 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 80 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "3" 81 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 82 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 83 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 84 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 85 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 86 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 87 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 88 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 89 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 90 | // Retrieval info: PRIVATE: WidthData NUMERIC "32" 91 | // Retrieval info: PRIVATE: rden NUMERIC "0" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 94 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 95 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 96 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=GBUF" 97 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 98 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 99 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 100 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 101 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 102 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 103 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M144K" 104 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 105 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 106 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 107 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 108 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 109 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 110 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 111 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 112 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 113 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 114 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 115 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 116 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 117 | // Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 118 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.v TRUE 119 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.inc TRUE 120 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.cmp TRUE 121 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.bsf TRUE 122 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32_inst.v TRUE 123 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32_bb.v TRUE 124 | // Retrieval info: LIB_FILE: altera_mf 125 | -------------------------------------------------------------------------------- /ProcessingCore.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2018 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition 21 | # Date created = 16:49:34 May 15, 2019 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # ProcessingCore_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Stratix IV" 40 | set_global_assignment -name DEVICE EP4SGX530HH35C2 41 | set_global_assignment -name TOP_LEVEL_ENTITY proc_top 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:49:34 MAY 15, 2019" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" 50 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 51 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 55 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_procarray -section_id eda_simulation 56 | set_global_assignment -name EDA_TEST_BENCH_NAME tb_proccore -section_id eda_simulation 57 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id tb_proccore 58 | set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ps" -section_id tb_proccore 59 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_proccore -section_id tb_proccore 60 | set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON 61 | set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL 62 | set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON 63 | set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON 64 | set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON 65 | set_global_assignment -name SMART_RECOMPILE ON 66 | set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 67 | set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF 68 | set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 69 | set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF 70 | set_global_assignment -name EDA_TEST_BENCH_NAME tb_procarray -section_id eda_simulation 71 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id tb_procarray 72 | set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ps" -section_id tb_procarray 73 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_procarray -section_id tb_procarray 74 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 75 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 76 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 77 | set_global_assignment -name EDA_TEST_BENCH_NAME tb_proctop -section_id eda_simulation 78 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_proctop 79 | set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1 ps" -section_id tb_proctop 80 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME proc_tb -section_id tb_proctop 81 | set_global_assignment -name SYSTEMVERILOG_FILE procRegs.sv 82 | set_global_assignment -name SYSTEMVERILOG_FILE procInstSchd.sv 83 | set_global_assignment -name SYSTEMVERILOG_FILE proc_top.sv 84 | set_global_assignment -name VERILOG_TEST_BENCH_FILE simulation/modelsim/procArray/tb_procarray.sv 85 | set_global_assignment -name SYSTEMVERILOG_FILE procUnit.sv 86 | set_global_assignment -name VERILOG_TEST_BENCH_FILE simulation/modelsim/tb_proccore.sv 87 | set_global_assignment -name SYSTEMVERILOG_FILE procCore.sv 88 | set_global_assignment -name QIP_FILE ip/fpacc/fpacc.qip 89 | set_global_assignment -name SIP_FILE ip/fpacc/fpacc.sip 90 | set_global_assignment -name QIP_FILE ip/fpmult/fpmult.qip 91 | set_global_assignment -name SYSTEMVERILOG_FILE procControl.sv 92 | set_global_assignment -name SYSTEMVERILOG_FILE procRouter.sv 93 | set_global_assignment -name QIP_FILE ip/fpadd/fpadd.qip 94 | set_global_assignment -name QIP_FILE ip/fifo_32/fifo_32.qip 95 | set_global_assignment -name QIP_FILE ip/dpram_16x32/dpram_16x32.qip 96 | set_global_assignment -name SYSTEMVERILOG_FILE procArray.sv 97 | set_global_assignment -name SYSTEMVERILOG_FILE procRow.sv 98 | set_global_assignment -name QIP_FILE ip/dpram_256x32/dpram_256x32.qip 99 | set_global_assignment -name QIP_FILE ip/dpram_4096x32/dpram_4096x32.qip 100 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 101 | set_global_assignment -name EDA_TEST_BENCH_FILE procCore.sv -section_id tb_proccore 102 | set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/procCore/tb_proccore.sv -section_id tb_proccore 103 | set_global_assignment -name EDA_TEST_BENCH_FILE procArray.sv -section_id tb_procarray 104 | set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/procArray/tb_procarray.sv -section_id tb_procarray 105 | set_global_assignment -name EDA_TEST_BENCH_FILE proc_top.sv.bak -section_id tb_proctop 106 | set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/proc_top/proc_tb.sv -section_id tb_proctop -------------------------------------------------------------------------------- /procCore.sv: -------------------------------------------------------------------------------- 1 | //Processing unit calculation core 2 | module procCore 3 | #( 4 | parameter WDATA_ROW_LEN = 16 5 | ) 6 | ( 7 | input clock, 8 | input reset, 9 | 10 | //Configs 11 | input [23:0] conf_i,//Kernel length 12 | 13 | //Kernel(Weight) data 14 | input [31:0] weights[WDATA_ROW_LEN], 15 | 16 | //Input data 17 | input [31:0] data_i, 18 | input datavalid_i, 19 | input stall_i, 20 | 21 | //Test outputs 22 | output accresvalid_o, 23 | output [31:0] accres_o 24 | ); 25 | 26 | //config decode 27 | //config decode 28 | wire conf_enable; 29 | wire conf_psum_input; 30 | wire conf_psum_output; 31 | wire conf_incache; 32 | wire [3:0] conf_weightlen; 33 | wire [7:0] conf_cachelen; 34 | wire [7:0] conf_id; 35 | 36 | assign { 37 | conf_enable, 38 | conf_psum_input, 39 | conf_psum_output, 40 | conf_incache, 41 | conf_weightlen, 42 | conf_cachelen, 43 | conf_id 44 | } = conf_i; 45 | 46 | wire stallpipeline; // Stall the pipeline, mainly triggererd by a full output buffer 47 | assign stallpipeline = stall_i || !conf_enable; 48 | 49 | 50 | //Multiplier 51 | 52 | wire [31:0] mulres; //Multiply result 53 | reg mulen = 0; 54 | 55 | reg [7:0] datawraddr = 0; 56 | reg [7:0] mulbaseaddr = 0; 57 | reg [3:0] muloffsetaddr = 0; 58 | 59 | reg [0:0] mulstate = 0; 60 | always@(posedge clock or posedge reset) begin 61 | if(reset) begin 62 | datawraddr <= 0; 63 | mulbaseaddr <= 0; 64 | muloffsetaddr <= 0; 65 | mulen <= 0; 66 | mulstate <= 0; 67 | end 68 | else if(!stallpipeline) begin 69 | //data cache address calculate 70 | if(datavalid_i) begin 71 | if(!conf_incache) 72 | datawraddr <= datawraddr + 8'b1; 73 | else 74 | datawraddr <= conf_cachelen; 75 | end 76 | 77 | //multiplier state machine 78 | case(mulstate) 79 | default:begin//kickstart 80 | if(datavalid_i) begin 81 | mulen <= 1; 82 | if(conf_incache) begin 83 | mulstate <= 1; 84 | 85 | end 86 | else begin 87 | if(muloffsetaddr >= conf_weightlen - 1) begin 88 | mulstate <= 1; 89 | muloffsetaddr <= 0; 90 | mulbaseaddr <= mulbaseaddr + 8'b1; 91 | end 92 | else begin 93 | muloffsetaddr <= muloffsetaddr + 4'b1; 94 | end 95 | end 96 | end 97 | else begin 98 | mulen <= 0; 99 | end 100 | end 101 | 1:begin//Full accumulation 102 | if(mulbaseaddr + muloffsetaddr != datawraddr) begin 103 | mulen <= 1; 104 | if(muloffsetaddr >= conf_weightlen - 1) begin 105 | muloffsetaddr <= 0; 106 | mulbaseaddr <= mulbaseaddr + 8'b1; 107 | end 108 | else 109 | muloffsetaddr <= muloffsetaddr + 4'b1; 110 | end 111 | else begin 112 | mulen <= 0; 113 | end 114 | 115 | end 116 | endcase 117 | end 118 | end 119 | 120 | wire [31:0] olddata; 121 | reg [31:0] newdata; 122 | reg passthrough; 123 | wire [31:0] data = passthrough?newdata:olddata; 124 | //Buffer to store data input for convolution input data reuse 125 | dpram_256x32 databuf( 126 | .clock (clock), 127 | .aclr(reset), 128 | .data (data_i), 129 | .enable(!stallpipeline), 130 | .rdaddress (mulbaseaddr + muloffsetaddr), 131 | .wraddress (datawraddr), 132 | .wren (datavalid_i & !conf_incache),//lock input while in in-cache mode 133 | .q (olddata) 134 | ); 135 | 136 | //Pass through logic for read during write operation 137 | always@(posedge clock) begin 138 | if(datavalid_i && !conf_incache) begin//if wren is set to 1 139 | newdata <= data_i; 140 | end 141 | 142 | if(datavalid_i && !conf_incache && 143 | (mulbaseaddr + muloffsetaddr) == datawraddr) begin//if read during write 144 | passthrough <= 1; 145 | end 146 | else 147 | passthrough <= 0; 148 | end 149 | 150 | 151 | // 1 cycle delay for sram read operation 152 | reg [3:0] wdrdaddr_delay; 153 | always@(posedge clock or posedge reset) begin 154 | if(reset) 155 | wdrdaddr_delay <= 0; 156 | else if(!stallpipeline) 157 | wdrdaddr_delay <= muloffsetaddr; 158 | end 159 | 160 | fpmult mult( 161 | .aclr(reset), //input aclr; 162 | .clk_en(!stallpipeline), //input clk_en; 163 | .clock(clock), //input clock; 164 | .dataa(data), //input [31:0] dataa; 165 | .datab(weights[wdrdaddr_delay]), //input [31:0] datab; 166 | .result(mulres) //output [31:0] result; 167 | ); 168 | 169 | //6 stage delay line to compensate for the pipeline delay 170 | //Multiplier cycle: 5, sram read delay: 1 171 | reg [4:0] mul_valid_delay; 172 | reg [4:0] mul_first_delay; 173 | reg [4:0] mul_last_delay; 174 | always@(posedge clock or posedge reset) begin 175 | if(reset) begin 176 | mul_valid_delay <= 0; 177 | mul_first_delay <= 0; 178 | mul_last_delay <= 0; 179 | end 180 | else if(!stallpipeline) begin 181 | mul_valid_delay <= {mul_valid_delay[3:0],mulen}; 182 | mul_first_delay <= {mul_first_delay[3:0],wdrdaddr_delay == 0 && mulen}; 183 | mul_last_delay <= {mul_last_delay[3:0],wdrdaddr_delay == conf_weightlen - 1 && mulen}; 184 | end 185 | end 186 | wire mulresvalid = mul_valid_delay[4];//value acquired from delay line 187 | wire mulresfirst = mul_first_delay[4]; 188 | wire mulreslast = mul_last_delay[4]; 189 | 190 | //Accumulator 191 | wire [31:0] accres; //Accumulator result 192 | 193 | //Accumulator output delay cycle:4 194 | reg [3:0] acc_valid_delay; 195 | wire accresvalid = acc_valid_delay[3]; 196 | always@(posedge clock or posedge reset) begin 197 | if(reset) 198 | acc_valid_delay <= 0; 199 | else if(!stallpipeline) 200 | acc_valid_delay <= {acc_valid_delay[2:0], mulreslast}; 201 | 202 | end 203 | 204 | fpacc acc( 205 | .clk(clock), // input wire clk 206 | .areset(reset), // input wire areset 207 | .x(mulresvalid?mulres:0), //input acc num input wire [31:0] x 208 | .n(mulresvalid && mulresfirst), //start new acc input wire n 209 | .r(accres), //accumulation result output wire [31:0] r 210 | .xo(), //input overflow. output wire xo 211 | .xu(), //input underflow. output wire xu 212 | .ao(), //accumulator overflow. output wire ao 213 | .en(!stallpipeline) //enable pipeline input wire [0:0] en 214 | ); 215 | 216 | //Only for test purposes 217 | assign accres_o = accres; 218 | assign accresvalid_o = accresvalid; 219 | 220 | endmodule 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2018 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.2")) 22 | (symbol 23 | (rect 0 0 256 216) 24 | (text "dpram_4096x32" (rect 82 0 190 16)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 200 25 212)(font "Arial" )) 26 | (port 27 | (pt 0 32) 28 | (input) 29 | (text "data_a[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) 30 | (text "data_a[31..0]" (rect 4 18 65 31)(font "Arial" (font_size 8))) 31 | (line (pt 0 32)(pt 112 32)(line_width 3)) 32 | ) 33 | (port 34 | (pt 0 48) 35 | (input) 36 | (text "address_a[11..0]" (rect 0 0 95 14)(font "Arial" (font_size 8))) 37 | (text "address_a[11..0]" (rect 4 34 83 47)(font "Arial" (font_size 8))) 38 | (line (pt 0 48)(pt 112 48)(line_width 3)) 39 | ) 40 | (port 41 | (pt 0 64) 42 | (input) 43 | (text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8))) 44 | (text "wren_a" (rect 4 50 40 63)(font "Arial" (font_size 8))) 45 | (line (pt 0 64)(pt 112 64)) 46 | ) 47 | (port 48 | (pt 0 80) 49 | (input) 50 | (text "rden_a" (rect 0 0 40 14)(font "Arial" (font_size 8))) 51 | (text "rden_a" (rect 4 66 36 79)(font "Arial" (font_size 8))) 52 | (line (pt 0 80)(pt 112 80)) 53 | ) 54 | (port 55 | (pt 0 104) 56 | (input) 57 | (text "data_b[31..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) 58 | (text "data_b[31..0]" (rect 4 90 65 103)(font "Arial" (font_size 8))) 59 | (line (pt 0 104)(pt 112 104)(line_width 3)) 60 | ) 61 | (port 62 | (pt 0 120) 63 | (input) 64 | (text "address_b[11..0]" (rect 0 0 95 14)(font "Arial" (font_size 8))) 65 | (text "address_b[11..0]" (rect 4 106 83 119)(font "Arial" (font_size 8))) 66 | (line (pt 0 120)(pt 112 120)(line_width 3)) 67 | ) 68 | (port 69 | (pt 0 136) 70 | (input) 71 | (text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8))) 72 | (text "wren_b" (rect 4 122 40 135)(font "Arial" (font_size 8))) 73 | (line (pt 0 136)(pt 112 136)) 74 | ) 75 | (port 76 | (pt 0 152) 77 | (input) 78 | (text "rden_b" (rect 0 0 40 14)(font "Arial" (font_size 8))) 79 | (text "rden_b" (rect 4 138 36 151)(font "Arial" (font_size 8))) 80 | (line (pt 0 152)(pt 112 152)) 81 | ) 82 | (port 83 | (pt 0 176) 84 | (input) 85 | (text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8))) 86 | (text "clock_a" (rect 4 162 39 175)(font "Arial" (font_size 8))) 87 | (line (pt 0 176)(pt 92 176)) 88 | ) 89 | (port 90 | (pt 0 192) 91 | (input) 92 | (text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8))) 93 | (text "clock_b" (rect 4 178 39 191)(font "Arial" (font_size 8))) 94 | (line (pt 0 192)(pt 104 192)) 95 | ) 96 | (port 97 | (pt 256 32) 98 | (output) 99 | (text "q_a[31..0]" (rect 0 0 56 14)(font "Arial" (font_size 8))) 100 | (text "q_a[31..0]" (rect 205 18 251 31)(font "Arial" (font_size 8))) 101 | (line (pt 256 32)(pt 168 32)(line_width 3)) 102 | ) 103 | (port 104 | (pt 256 104) 105 | (output) 106 | (text "q_b[31..0]" (rect 0 0 56 14)(font "Arial" (font_size 8))) 107 | (text "q_b[31..0]" (rect 205 90 251 103)(font "Arial" (font_size 8))) 108 | (line (pt 256 104)(pt 168 104)(line_width 3)) 109 | ) 110 | (drawing 111 | (text "4096 Word(s)" (rect 137 59 268 251)(font "Arial" )(vertical)) 112 | (text "RAM" (rect 148 48 261 215)(font "Arial" )(vertical)) 113 | (text "Block Type: M144K" (rect 40 205 160 421)(font "Arial" )) 114 | (line (pt 128 24)(pt 168 24)) 115 | (line (pt 168 24)(pt 168 160)) 116 | (line (pt 168 160)(pt 128 160)) 117 | (line (pt 128 160)(pt 128 24)) 118 | (line (pt 112 27)(pt 120 27)) 119 | (line (pt 120 27)(pt 120 39)) 120 | (line (pt 120 39)(pt 112 39)) 121 | (line (pt 112 39)(pt 112 27)) 122 | (line (pt 112 34)(pt 114 36)) 123 | (line (pt 114 36)(pt 112 38)) 124 | (line (pt 92 36)(pt 112 36)) 125 | (line (pt 120 32)(pt 128 32)(line_width 3)) 126 | (line (pt 112 43)(pt 120 43)) 127 | (line (pt 120 43)(pt 120 55)) 128 | (line (pt 120 55)(pt 112 55)) 129 | (line (pt 112 55)(pt 112 43)) 130 | (line (pt 112 50)(pt 114 52)) 131 | (line (pt 114 52)(pt 112 54)) 132 | (line (pt 92 52)(pt 112 52)) 133 | (line (pt 120 48)(pt 128 48)(line_width 3)) 134 | (line (pt 112 59)(pt 120 59)) 135 | (line (pt 120 59)(pt 120 71)) 136 | (line (pt 120 71)(pt 112 71)) 137 | (line (pt 112 71)(pt 112 59)) 138 | (line (pt 112 66)(pt 114 68)) 139 | (line (pt 114 68)(pt 112 70)) 140 | (line (pt 92 68)(pt 112 68)) 141 | (line (pt 120 64)(pt 128 64)) 142 | (line (pt 112 75)(pt 120 75)) 143 | (line (pt 120 75)(pt 120 87)) 144 | (line (pt 120 87)(pt 112 87)) 145 | (line (pt 112 87)(pt 112 75)) 146 | (line (pt 112 82)(pt 114 84)) 147 | (line (pt 114 84)(pt 112 86)) 148 | (line (pt 92 84)(pt 112 84)) 149 | (line (pt 120 80)(pt 128 80)) 150 | (line (pt 112 99)(pt 120 99)) 151 | (line (pt 120 99)(pt 120 111)) 152 | (line (pt 120 111)(pt 112 111)) 153 | (line (pt 112 111)(pt 112 99)) 154 | (line (pt 112 106)(pt 114 108)) 155 | (line (pt 114 108)(pt 112 110)) 156 | (line (pt 104 108)(pt 112 108)) 157 | (line (pt 120 104)(pt 128 104)(line_width 3)) 158 | (line (pt 112 115)(pt 120 115)) 159 | (line (pt 120 115)(pt 120 127)) 160 | (line (pt 120 127)(pt 112 127)) 161 | (line (pt 112 127)(pt 112 115)) 162 | (line (pt 112 122)(pt 114 124)) 163 | (line (pt 114 124)(pt 112 126)) 164 | (line (pt 104 124)(pt 112 124)) 165 | (line (pt 120 120)(pt 128 120)(line_width 3)) 166 | (line (pt 112 131)(pt 120 131)) 167 | (line (pt 120 131)(pt 120 143)) 168 | (line (pt 120 143)(pt 112 143)) 169 | (line (pt 112 143)(pt 112 131)) 170 | (line (pt 112 138)(pt 114 140)) 171 | (line (pt 114 140)(pt 112 142)) 172 | (line (pt 104 140)(pt 112 140)) 173 | (line (pt 120 136)(pt 128 136)) 174 | (line (pt 112 147)(pt 120 147)) 175 | (line (pt 120 147)(pt 120 159)) 176 | (line (pt 120 159)(pt 112 159)) 177 | (line (pt 112 159)(pt 112 147)) 178 | (line (pt 112 154)(pt 114 156)) 179 | (line (pt 114 156)(pt 112 158)) 180 | (line (pt 104 156)(pt 112 156)) 181 | (line (pt 120 152)(pt 128 152)) 182 | (line (pt 92 36)(pt 92 177)) 183 | (line (pt 104 108)(pt 104 193)) 184 | (line (pt 0 0)(pt 257 0)) 185 | (line (pt 257 0)(pt 257 218)) 186 | (line (pt 0 218)(pt 257 218)) 187 | (line (pt 0 0)(pt 0 218)) 188 | (line (pt 0 0)(pt 0 0)) 189 | (line (pt 0 0)(pt 0 0)) 190 | (line (pt 0 0)(pt 0 0)) 191 | (line (pt 0 0)(pt 0 0)) 192 | ) 193 | ) 194 | -------------------------------------------------------------------------------- /ip/fifo_32/fifo_32.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %FIFO% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: scfifo 5 | 6 | // ============================================================ 7 | // File Name: fifo_32.v 8 | // Megafunction Name(s): 9 | // scfifo 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module fifo_32 ( 40 | aclr, 41 | clock, 42 | data, 43 | rdreq, 44 | wrreq, 45 | empty, 46 | full, 47 | q, 48 | usedw); 49 | 50 | input aclr; 51 | input clock; 52 | input [31:0] data; 53 | input rdreq; 54 | input wrreq; 55 | output empty; 56 | output full; 57 | output [31:0] q; 58 | output [7:0] usedw; 59 | 60 | wire sub_wire0; 61 | wire sub_wire1; 62 | wire [31:0] sub_wire2; 63 | wire [7:0] sub_wire3; 64 | wire empty = sub_wire0; 65 | wire full = sub_wire1; 66 | wire [31:0] q = sub_wire2[31:0]; 67 | wire [7:0] usedw = sub_wire3[7:0]; 68 | 69 | scfifo scfifo_component ( 70 | .aclr (aclr), 71 | .clock (clock), 72 | .data (data), 73 | .rdreq (rdreq), 74 | .wrreq (wrreq), 75 | .empty (sub_wire0), 76 | .full (sub_wire1), 77 | .q (sub_wire2), 78 | .usedw (sub_wire3), 79 | .almost_empty (), 80 | .almost_full (), 81 | .eccstatus (), 82 | .sclr ()); 83 | defparam 84 | scfifo_component.add_ram_output_register = "OFF", 85 | scfifo_component.intended_device_family = "Stratix IV", 86 | scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", 87 | scfifo_component.lpm_numwords = 256, 88 | scfifo_component.lpm_showahead = "OFF", 89 | scfifo_component.lpm_type = "scfifo", 90 | scfifo_component.lpm_width = 32, 91 | scfifo_component.lpm_widthu = 8, 92 | scfifo_component.overflow_checking = "ON", 93 | scfifo_component.underflow_checking = "ON", 94 | scfifo_component.use_eab = "ON"; 95 | 96 | 97 | endmodule 98 | 99 | // ============================================================ 100 | // CNX file retrieval info 101 | // ============================================================ 102 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" 103 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" 104 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0" 105 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" 106 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1" 107 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 108 | // Retrieval info: PRIVATE: Depth NUMERIC "256" 109 | // Retrieval info: PRIVATE: Empty NUMERIC "1" 110 | // Retrieval info: PRIVATE: Full NUMERIC "1" 111 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 112 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" 113 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" 114 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" 115 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" 116 | // Retrieval info: PRIVATE: Optimize NUMERIC "0" 117 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 118 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 119 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" 120 | // Retrieval info: PRIVATE: UsedW NUMERIC "1" 121 | // Retrieval info: PRIVATE: Width NUMERIC "32" 122 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "0" 123 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0" 124 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0" 125 | // Retrieval info: PRIVATE: output_width NUMERIC "32" 126 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1" 127 | // Retrieval info: PRIVATE: rsFull NUMERIC "0" 128 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0" 129 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "1" 130 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0" 131 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0" 132 | // Retrieval info: PRIVATE: wsFull NUMERIC "1" 133 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "0" 134 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 135 | // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" 136 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 137 | // Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K" 138 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256" 139 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" 140 | // Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" 141 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" 142 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8" 143 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" 144 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" 145 | // Retrieval info: CONSTANT: USE_EAB STRING "ON" 146 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" 147 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" 148 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 149 | // Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" 150 | // Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" 151 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 152 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" 153 | // Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]" 154 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" 155 | // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 156 | // Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 157 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 158 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 159 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 160 | // Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 161 | // Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 162 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0 163 | // Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.v TRUE 165 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.inc TRUE 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.cmp TRUE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32.bsf TRUE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32_inst.v TRUE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32_bb.v TRUE 170 | // Retrieval info: LIB_FILE: altera_mf 171 | -------------------------------------------------------------------------------- /ip/spram_4096x32/spram_4096x32.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 1-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: spram_4096x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module spram_4096x32 ( 40 | address, 41 | clock, 42 | data, 43 | wren, 44 | q); 45 | 46 | input [11:0] address; 47 | input clock; 48 | input [31:0] data; 49 | input wren; 50 | output [31:0] q; 51 | `ifndef ALTERA_RESERVED_QIS 52 | // synopsys translate_off 53 | `endif 54 | tri1 clock; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_on 57 | `endif 58 | 59 | wire [31:0] sub_wire0; 60 | wire [31:0] q = sub_wire0[31:0]; 61 | 62 | altsyncram altsyncram_component ( 63 | .address_a (address), 64 | .clock0 (clock), 65 | .data_a (data), 66 | .wren_a (wren), 67 | .q_a (sub_wire0), 68 | .aclr0 (1'b0), 69 | .aclr1 (1'b0), 70 | .address_b (1'b1), 71 | .addressstall_a (1'b0), 72 | .addressstall_b (1'b0), 73 | .byteena_a (1'b1), 74 | .byteena_b (1'b1), 75 | .clock1 (1'b1), 76 | .clocken0 (1'b1), 77 | .clocken1 (1'b1), 78 | .clocken2 (1'b1), 79 | .clocken3 (1'b1), 80 | .data_b (1'b1), 81 | .eccstatus (), 82 | .q_b (), 83 | .rden_a (1'b1), 84 | .rden_b (1'b1), 85 | .wren_b (1'b0)); 86 | defparam 87 | altsyncram_component.clock_enable_input_a = "BYPASS", 88 | altsyncram_component.clock_enable_output_a = "BYPASS", 89 | altsyncram_component.intended_device_family = "Stratix IV", 90 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=GBUF", 91 | altsyncram_component.lpm_type = "altsyncram", 92 | altsyncram_component.numwords_a = 4096, 93 | altsyncram_component.operation_mode = "SINGLE_PORT", 94 | altsyncram_component.outdata_aclr_a = "NONE", 95 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 96 | altsyncram_component.power_up_uninitialized = "FALSE", 97 | altsyncram_component.ram_block_type = "M144K", 98 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 99 | altsyncram_component.widthad_a = 12, 100 | altsyncram_component.width_a = 32, 101 | altsyncram_component.width_byteena_a = 1; 102 | 103 | 104 | endmodule 105 | 106 | // ============================================================ 107 | // CNX file retrieval info 108 | // ============================================================ 109 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 110 | // Retrieval info: PRIVATE: AclrAddr NUMERIC "0" 111 | // Retrieval info: PRIVATE: AclrByte NUMERIC "0" 112 | // Retrieval info: PRIVATE: AclrData NUMERIC "0" 113 | // Retrieval info: PRIVATE: AclrOutput NUMERIC "0" 114 | // Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0" 115 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 116 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 117 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 118 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 119 | // Retrieval info: PRIVATE: Clken NUMERIC "0" 120 | // Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1" 121 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 122 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 123 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 124 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 125 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1" 126 | // Retrieval info: PRIVATE: JTAG_ID STRING "GBUF" 127 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 128 | // Retrieval info: PRIVATE: MIFfilename STRING "" 129 | // Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096" 130 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "3" 131 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 132 | // Retrieval info: PRIVATE: RegAddr NUMERIC "1" 133 | // Retrieval info: PRIVATE: RegData NUMERIC "1" 134 | // Retrieval info: PRIVATE: RegOutput NUMERIC "0" 135 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 136 | // Retrieval info: PRIVATE: SingleClock NUMERIC "1" 137 | // Retrieval info: PRIVATE: UseDQRAM NUMERIC "1" 138 | // Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0" 139 | // Retrieval info: PRIVATE: WidthAddr NUMERIC "12" 140 | // Retrieval info: PRIVATE: WidthData NUMERIC "32" 141 | // Retrieval info: PRIVATE: rden NUMERIC "0" 142 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 143 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 144 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 145 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 146 | // Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=GBUF" 147 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 148 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 149 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT" 150 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 151 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 152 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 153 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M144K" 154 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 155 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 156 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 157 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 158 | // Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]" 159 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 160 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 161 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 162 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren" 163 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0 164 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 165 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 166 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 167 | // Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.v TRUE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.inc TRUE 170 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.cmp TRUE 171 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32.bsf TRUE 172 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32_inst.v TRUE 173 | // Retrieval info: GEN_FILE: TYPE_NORMAL spram_4096x32_bb.v TRUE 174 | // Retrieval info: LIB_FILE: altera_mf 175 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dpram_16x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module dpram_16x32 ( 35 | clock, 36 | data, 37 | enable, 38 | rdaddress, 39 | wraddress, 40 | wren, 41 | q); 42 | 43 | input clock; 44 | input [31:0] data; 45 | input enable; 46 | input [3:0] rdaddress; 47 | input [3:0] wraddress; 48 | input wren; 49 | output [31:0] q; 50 | `ifndef ALTERA_RESERVED_QIS 51 | // synopsys translate_off 52 | `endif 53 | tri1 clock; 54 | tri1 enable; 55 | tri0 wren; 56 | `ifndef ALTERA_RESERVED_QIS 57 | // synopsys translate_on 58 | `endif 59 | 60 | endmodule 61 | 62 | // ============================================================ 63 | // CNX file retrieval info 64 | // ============================================================ 65 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 66 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 67 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 68 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 69 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 70 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 71 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 72 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 73 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 74 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" 75 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 76 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 77 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 78 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 79 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 80 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 83 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 84 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 85 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 86 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 87 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 88 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 89 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 90 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 91 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 92 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 93 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 94 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 95 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" 96 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 97 | // Retrieval info: PRIVATE: MIFfilename STRING "" 98 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 99 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 100 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 101 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 102 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" 103 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 104 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 105 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 106 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 107 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 108 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 109 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 110 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 111 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 112 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 113 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 114 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 115 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 116 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 117 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 118 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 119 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 120 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 121 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: enable NUMERIC "1" 123 | // Retrieval info: PRIVATE: rden NUMERIC "0" 124 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 125 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 126 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 127 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 128 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" 129 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 130 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 131 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 132 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" 133 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" 134 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 135 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 136 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 137 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 138 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" 139 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" 140 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" 141 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" 142 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 143 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 144 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 145 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 146 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 147 | // Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable" 148 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 149 | // Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" 150 | // Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]" 151 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 152 | // Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0 153 | // Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 154 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 155 | // Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0 156 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 157 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 158 | // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 159 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.v TRUE 160 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.inc TRUE 161 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.cmp TRUE 162 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.bsf TRUE 163 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32_inst.v TRUE 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32_bb.v TRUE 165 | // Retrieval info: LIB_FILE: altera_mf 166 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dpram_256x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module dpram_256x32 ( 35 | aclr, 36 | clock, 37 | data, 38 | enable, 39 | rdaddress, 40 | wraddress, 41 | wren, 42 | q); 43 | 44 | input aclr; 45 | input clock; 46 | input [31:0] data; 47 | input enable; 48 | input [7:0] rdaddress; 49 | input [7:0] wraddress; 50 | input wren; 51 | output [31:0] q; 52 | `ifndef ALTERA_RESERVED_QIS 53 | // synopsys translate_off 54 | `endif 55 | tri0 aclr; 56 | tri1 clock; 57 | tri1 enable; 58 | tri0 wren; 59 | `ifndef ALTERA_RESERVED_QIS 60 | // synopsys translate_on 61 | `endif 62 | 63 | endmodule 64 | 65 | // ============================================================ 66 | // CNX file retrieval info 67 | // ============================================================ 68 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 69 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 70 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 71 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 72 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 73 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 74 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 75 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 76 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 77 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" 78 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 79 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 80 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 81 | // Retrieval info: PRIVATE: CLRq NUMERIC "1" 82 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1" 83 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 84 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 85 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 86 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 87 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 88 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 89 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 90 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 91 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 92 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 93 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 94 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 95 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 96 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 97 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 98 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" 99 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 100 | // Retrieval info: PRIVATE: MIFfilename STRING "" 101 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 102 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1" 103 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 104 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 105 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" 106 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 107 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 108 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 109 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 110 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 111 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 112 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 113 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 114 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 115 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 116 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 117 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 118 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 119 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 120 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 121 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 122 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 123 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 125 | // Retrieval info: PRIVATE: enable NUMERIC "1" 126 | // Retrieval info: PRIVATE: rden NUMERIC "0" 127 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 128 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0" 129 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 130 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 131 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" 132 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 133 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 134 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 135 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 136 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" 137 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 138 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0" 139 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 140 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 141 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" 142 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" 143 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 144 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" 145 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 146 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 147 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 148 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 149 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 150 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 151 | // Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable" 152 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 153 | // Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" 154 | // Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" 155 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 156 | // Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0 157 | // Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 158 | // Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 159 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 160 | // Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0 161 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 162 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 163 | // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 164 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.v TRUE 165 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.inc TRUE 166 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.cmp TRUE 167 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.bsf TRUE 168 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_inst.v TRUE 169 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_bb.v TRUE 170 | // Retrieval info: LIB_FILE: altera_mf 171 | -------------------------------------------------------------------------------- /ip/dpram_4096x32/dpram_4096x32_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dpram_4096x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 21 | //Your use of Intel Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Intel Program License 27 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | //the Intel FPGA IP License Agreement, or other applicable license 29 | //agreement, including, without limitation, that your use is for 30 | //the sole purpose of programming logic devices manufactured by 31 | //Intel and sold by Intel or its authorized distributors. Please 32 | //refer to the applicable agreement for further details. 33 | 34 | module dpram_4096x32 ( 35 | address_a, 36 | address_b, 37 | clock_a, 38 | clock_b, 39 | data_a, 40 | data_b, 41 | rden_a, 42 | rden_b, 43 | wren_a, 44 | wren_b, 45 | q_a, 46 | q_b); 47 | 48 | input [11:0] address_a; 49 | input [11:0] address_b; 50 | input clock_a; 51 | input clock_b; 52 | input [31:0] data_a; 53 | input [31:0] data_b; 54 | input rden_a; 55 | input rden_b; 56 | input wren_a; 57 | input wren_b; 58 | output [31:0] q_a; 59 | output [31:0] q_b; 60 | `ifndef ALTERA_RESERVED_QIS 61 | // synopsys translate_off 62 | `endif 63 | tri1 clock_a; 64 | tri1 rden_a; 65 | tri1 rden_b; 66 | tri0 wren_a; 67 | tri0 wren_b; 68 | `ifndef ALTERA_RESERVED_QIS 69 | // synopsys translate_on 70 | `endif 71 | 72 | endmodule 73 | 74 | // ============================================================ 75 | // CNX file retrieval info 76 | // ============================================================ 77 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 78 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 79 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 80 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 81 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 82 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 83 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 84 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 85 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 86 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 87 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 88 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 89 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 91 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 92 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 93 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 94 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 95 | // Retrieval info: PRIVATE: Clock NUMERIC "5" 96 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 97 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 98 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 99 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 100 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 101 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 102 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 103 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 104 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 105 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 106 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 107 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" 108 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 109 | // Retrieval info: PRIVATE: MIFfilename STRING "" 110 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 111 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 112 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 113 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "3" 114 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 115 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 116 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 117 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 118 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 119 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 120 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 121 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 122 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 123 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 124 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 125 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 126 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 127 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 128 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 129 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 130 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 131 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 132 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 133 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 134 | // Retrieval info: PRIVATE: enable NUMERIC "0" 135 | // Retrieval info: PRIVATE: rden NUMERIC "1" 136 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 137 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" 138 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 139 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 140 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 141 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 142 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" 143 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 144 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 145 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096" 146 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096" 147 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 148 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 149 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 150 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 151 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 152 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 153 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M144K" 154 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 155 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 156 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12" 157 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12" 158 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 159 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 160 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 161 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 162 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" 163 | // Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]" 164 | // Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]" 165 | // Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" 166 | // Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" 167 | // Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" 168 | // Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" 169 | // Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" 170 | // Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" 171 | // Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a" 172 | // Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b" 173 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 174 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 175 | // Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0 176 | // Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0 177 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 178 | // Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 179 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 180 | // Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 181 | // Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0 182 | // Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0 183 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 184 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 185 | // Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 186 | // Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 187 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32.v TRUE 188 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32.inc TRUE 189 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32.cmp TRUE 190 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32.bsf TRUE 191 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32_inst.v TRUE 192 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_4096x32_bb.v TRUE 193 | // Retrieval info: LIB_FILE: altera_mf 194 | -------------------------------------------------------------------------------- /ip/dpram_16x32/dpram_16x32.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dpram_16x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module dpram_16x32 ( 40 | clock, 41 | data, 42 | enable, 43 | rdaddress, 44 | wraddress, 45 | wren, 46 | q); 47 | 48 | input clock; 49 | input [31:0] data; 50 | input enable; 51 | input [3:0] rdaddress; 52 | input [3:0] wraddress; 53 | input wren; 54 | output [31:0] q; 55 | `ifndef ALTERA_RESERVED_QIS 56 | // synopsys translate_off 57 | `endif 58 | tri1 clock; 59 | tri1 enable; 60 | tri0 wren; 61 | `ifndef ALTERA_RESERVED_QIS 62 | // synopsys translate_on 63 | `endif 64 | 65 | wire [31:0] sub_wire0; 66 | wire [31:0] q = sub_wire0[31:0]; 67 | 68 | altsyncram altsyncram_component ( 69 | .address_a (wraddress), 70 | .address_b (rdaddress), 71 | .clock0 (clock), 72 | .clocken0 (enable), 73 | .data_a (data), 74 | .wren_a (wren), 75 | .q_b (sub_wire0), 76 | .aclr0 (1'b0), 77 | .aclr1 (1'b0), 78 | .addressstall_a (1'b0), 79 | .addressstall_b (1'b0), 80 | .byteena_a (1'b1), 81 | .byteena_b (1'b1), 82 | .clock1 (1'b1), 83 | .clocken1 (1'b1), 84 | .clocken2 (1'b1), 85 | .clocken3 (1'b1), 86 | .data_b ({32{1'b1}}), 87 | .eccstatus (), 88 | .q_a (), 89 | .rden_a (1'b1), 90 | .rden_b (1'b1), 91 | .wren_b (1'b0)); 92 | defparam 93 | altsyncram_component.address_aclr_b = "NONE", 94 | altsyncram_component.address_reg_b = "CLOCK0", 95 | altsyncram_component.clock_enable_input_a = "NORMAL", 96 | altsyncram_component.clock_enable_input_b = "NORMAL", 97 | altsyncram_component.clock_enable_output_b = "BYPASS", 98 | altsyncram_component.intended_device_family = "Stratix IV", 99 | altsyncram_component.lpm_type = "altsyncram", 100 | altsyncram_component.numwords_a = 16, 101 | altsyncram_component.numwords_b = 16, 102 | altsyncram_component.operation_mode = "DUAL_PORT", 103 | altsyncram_component.outdata_aclr_b = "NONE", 104 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 105 | altsyncram_component.power_up_uninitialized = "FALSE", 106 | altsyncram_component.ram_block_type = "M9K", 107 | altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", 108 | altsyncram_component.widthad_a = 4, 109 | altsyncram_component.widthad_b = 4, 110 | altsyncram_component.width_a = 32, 111 | altsyncram_component.width_b = 32, 112 | altsyncram_component.width_byteena_a = 1; 113 | 114 | 115 | endmodule 116 | 117 | // ============================================================ 118 | // CNX file retrieval info 119 | // ============================================================ 120 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 121 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 122 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 123 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 124 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 125 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 126 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 127 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 128 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 129 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" 130 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 131 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 132 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 133 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 134 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 135 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 136 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 137 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 138 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 139 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 140 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 141 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 142 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 143 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 144 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 145 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 146 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 147 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 148 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 149 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 150 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "512" 151 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 152 | // Retrieval info: PRIVATE: MIFfilename STRING "" 153 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 154 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 155 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 156 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 157 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" 158 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 159 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 160 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 161 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 162 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 163 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 164 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 165 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 166 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 167 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 168 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 169 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 170 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 171 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 172 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 173 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 174 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 175 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 176 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 177 | // Retrieval info: PRIVATE: enable NUMERIC "1" 178 | // Retrieval info: PRIVATE: rden NUMERIC "0" 179 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 180 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE" 181 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 182 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 183 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" 184 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 185 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 186 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 187 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" 188 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" 189 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 190 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 191 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 192 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 193 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" 194 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" 195 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" 196 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" 197 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 198 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 199 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 200 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 201 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 202 | // Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable" 203 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 204 | // Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]" 205 | // Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]" 206 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 207 | // Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0 208 | // Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0 209 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 210 | // Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0 211 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 212 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 213 | // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 214 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.v TRUE 215 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.inc TRUE 216 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.cmp TRUE 217 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32.bsf TRUE 218 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32_inst.v TRUE 219 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_16x32_bb.v TRUE 220 | // Retrieval info: LIB_FILE: altera_mf 221 | -------------------------------------------------------------------------------- /ip/dpram_256x32/dpram_256x32.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: dpram_256x32.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 18.0.0 Build 614 04/24/2018 SJ Standard Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 2018 Intel Corporation. All rights reserved. 22 | //Your use of Intel Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Intel Program License 28 | //Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | //the Intel FPGA IP License Agreement, or other applicable license 30 | //agreement, including, without limitation, that your use is for 31 | //the sole purpose of programming logic devices manufactured by 32 | //Intel and sold by Intel or its authorized distributors. Please 33 | //refer to the applicable agreement for further details. 34 | 35 | 36 | // synopsys translate_off 37 | `timescale 1 ps / 1 ps 38 | // synopsys translate_on 39 | module dpram_256x32 ( 40 | aclr, 41 | clock, 42 | data, 43 | enable, 44 | rdaddress, 45 | wraddress, 46 | wren, 47 | q); 48 | 49 | input aclr; 50 | input clock; 51 | input [31:0] data; 52 | input enable; 53 | input [7:0] rdaddress; 54 | input [7:0] wraddress; 55 | input wren; 56 | output [31:0] q; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_off 59 | `endif 60 | tri0 aclr; 61 | tri1 clock; 62 | tri1 enable; 63 | tri0 wren; 64 | `ifndef ALTERA_RESERVED_QIS 65 | // synopsys translate_on 66 | `endif 67 | 68 | wire [31:0] sub_wire0; 69 | wire [31:0] q = sub_wire0[31:0]; 70 | 71 | altsyncram altsyncram_component ( 72 | .aclr0 (aclr), 73 | .address_a (wraddress), 74 | .address_b (rdaddress), 75 | .clock0 (clock), 76 | .clocken0 (enable), 77 | .data_a (data), 78 | .wren_a (wren), 79 | .q_b (sub_wire0), 80 | .aclr1 (1'b0), 81 | .addressstall_a (1'b0), 82 | .addressstall_b (1'b0), 83 | .byteena_a (1'b1), 84 | .byteena_b (1'b1), 85 | .clock1 (1'b1), 86 | .clocken1 (1'b1), 87 | .clocken2 (1'b1), 88 | .clocken3 (1'b1), 89 | .data_b ({32{1'b1}}), 90 | .eccstatus (), 91 | .q_a (), 92 | .rden_a (1'b1), 93 | .rden_b (1'b1), 94 | .wren_b (1'b0)); 95 | defparam 96 | altsyncram_component.address_aclr_b = "CLEAR0", 97 | altsyncram_component.address_reg_b = "CLOCK0", 98 | altsyncram_component.clock_enable_input_a = "NORMAL", 99 | altsyncram_component.clock_enable_input_b = "NORMAL", 100 | altsyncram_component.clock_enable_output_b = "BYPASS", 101 | altsyncram_component.intended_device_family = "Stratix IV", 102 | altsyncram_component.lpm_type = "altsyncram", 103 | altsyncram_component.numwords_a = 256, 104 | altsyncram_component.numwords_b = 256, 105 | altsyncram_component.operation_mode = "DUAL_PORT", 106 | altsyncram_component.outdata_aclr_b = "CLEAR0", 107 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 108 | altsyncram_component.power_up_uninitialized = "FALSE", 109 | altsyncram_component.ram_block_type = "M9K", 110 | altsyncram_component.read_during_write_mode_mixed_ports = "OLD_DATA", 111 | altsyncram_component.widthad_a = 8, 112 | altsyncram_component.widthad_b = 8, 113 | altsyncram_component.width_a = 32, 114 | altsyncram_component.width_b = 32, 115 | altsyncram_component.width_byteena_a = 1; 116 | 117 | 118 | endmodule 119 | 120 | // ============================================================ 121 | // CNX file retrieval info 122 | // ============================================================ 123 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 124 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 125 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 126 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 127 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0" 128 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 129 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 130 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 131 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1" 132 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1" 133 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1" 134 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1" 135 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 136 | // Retrieval info: PRIVATE: CLRq NUMERIC "1" 137 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "1" 138 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 139 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 140 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 141 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 142 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 143 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 144 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 145 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 146 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0" 147 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B" 148 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 149 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 150 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 151 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 152 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 153 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192" 154 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 155 | // Retrieval info: PRIVATE: MIFfilename STRING "" 156 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2" 157 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1" 158 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 159 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2" 160 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1" 161 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 162 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 163 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 164 | // Retrieval info: PRIVATE: REGq NUMERIC "1" 165 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" 166 | // Retrieval info: PRIVATE: REGrren NUMERIC "1" 167 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 168 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 169 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 170 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 171 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 172 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 173 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 174 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 175 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 176 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 177 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 178 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0" 179 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 180 | // Retrieval info: PRIVATE: enable NUMERIC "1" 181 | // Retrieval info: PRIVATE: rden NUMERIC "0" 182 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 183 | // Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "CLEAR0" 184 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 185 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL" 186 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL" 187 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 188 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV" 189 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 190 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256" 191 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256" 192 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT" 193 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0" 194 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 195 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 196 | // Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K" 197 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA" 198 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8" 199 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8" 200 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 201 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 202 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" 203 | // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" 204 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 205 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]" 206 | // Retrieval info: USED_PORT: enable 0 0 0 0 INPUT VCC "enable" 207 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]" 208 | // Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]" 209 | // Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]" 210 | // Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren" 211 | // Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0 212 | // Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0 213 | // Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0 214 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 215 | // Retrieval info: CONNECT: @clocken0 0 0 0 0 enable 0 0 0 0 216 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0 217 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0 218 | // Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0 219 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.v TRUE 220 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.inc TRUE 221 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.cmp TRUE 222 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32.bsf TRUE 223 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_inst.v TRUE 224 | // Retrieval info: GEN_FILE: TYPE_NORMAL dpram_256x32_bb.v TRUE 225 | // Retrieval info: LIB_FILE: altera_mf 226 | -------------------------------------------------------------------------------- /ip/fpacc/fpacc_sim/cadence/ncsim_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2019 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 18.0 614 win32 2019.05.15.18:19:40 16 | 17 | # ---------------------------------------- 18 | # ncsim - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script provides commands to simulate the following IP detected in 22 | # your Quartus project: 23 | # fpacc 24 | # 25 | # Altera recommends that you source this Quartus-generated IP simulation 26 | # script from your own customized top-level script, and avoid editing this 27 | # generated script. 28 | # 29 | # To write a top-level shell script that compiles Altera simulation libraries 30 | # and the Quartus-generated IP in your project, along with your design and 31 | # testbench files, copy the text from the TOP-LEVEL TEMPLATE section below 32 | # into a new file, e.g. named "ncsim.sh", and modify text as directed. 33 | # 34 | # You can also modify the simulation flow to suit your needs. Set the 35 | # following variables to 1 to disable their corresponding processes: 36 | # - SKIP_FILE_COPY: skip copying ROM/RAM initialization files 37 | # - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library 38 | # - SKIP_COM: skip compiling Quartus-generated IP simulation files 39 | # - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation 40 | # 41 | # ---------------------------------------- 42 | # # TOP-LEVEL TEMPLATE - BEGIN 43 | # # 44 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to 45 | # # construct paths to the files required to simulate the IP in your Quartus 46 | # # project. By default, the IP script assumes that you are launching the 47 | # # simulator from the IP script location. If launching from another 48 | # # location, set QSYS_SIMDIR to the output directory you specified when you 49 | # # generated the IP script, relative to the directory from which you launch 50 | # # the simulator. In this case, you must also copy the generated files 51 | # # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 52 | # # into the location from which you launch the simulator, or incorporate 53 | # # into any existing library setup. 54 | # # 55 | # # Run Quartus-generated IP simulation script once to compile Quartus EDA 56 | # # simulation libraries and Quartus-generated IP simulation files, and copy 57 | # # any ROM/RAM initialization files to the simulation directory. 58 | # # - If necessary, specify any compilation options: 59 | # # USER_DEFINED_COMPILE_OPTIONS 60 | # # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler 61 | # # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler 62 | # # 63 | # source