├── README.md ├── ida-OpenRisc.py ├── openrisc-arch-1.1-rev0.pdf ├── openrisc-arch-1.1-rev0.txt └── parse_doc.py /README.md: -------------------------------------------------------------------------------- 1 | # ida-cpu-OpenRisc 2 | 3 | Quick and dirty IDA Pro cpu for OpenRISC. 4 | 5 | Code generated from the OpenRISC documentation with an ugly script. 6 | 7 | Beta version, beware of bugs. 8 | 9 | # INSTALL 10 | cp ida-OpenRisc.py IDA/procs 11 | 12 | # USE 13 | Choose 'OpenRISC' in "Processor Type" on the loading page. 14 | 15 | # LICENSE 16 | BeerWare 17 | -------------------------------------------------------------------------------- /ida-OpenRisc.py: -------------------------------------------------------------------------------- 1 | from idaapi import * 2 | import copy 3 | 4 | def SIGNEXT(x, b): 5 | m = 1 << (b - 1) 6 | x = x & ((1 << b) - 1) 7 | return (x ^ m) - m 8 | 9 | 10 | class DecodingError(Exception): 11 | pass 12 | 13 | class openrisc_processor_t(processor_t): 14 | id = 0x8000 + 0x5571C 15 | flag = PR_SEGS | PRN_HEX | PR_RNAMESOK | PR_NO_SEGMOVE | PR_USE32 | PR_DEFSEG32 16 | cnbits = 8 17 | dnbits = 8 18 | author = "Deva" 19 | psnames = ["OpenRISC"] 20 | plnames = ["OpenRISC"] 21 | segreg_size = 0 22 | instruc_start = 0 23 | assembler = { 24 | "flag": ASH_HEXF0 | ASD_DECF0 | ASO_OCTF5 | ASB_BINF0 | AS_N2CHR, 25 | "uflag": 0, 26 | "name": "OpenRISC asm", 27 | "origin": ".org", 28 | "end": ".end", 29 | "cmnt": ";", 30 | "ascsep": '"', 31 | "accsep": "'", 32 | "esccodes": "\"'", 33 | "a_ascii": ".ascii", 34 | "a_byte": ".byte", 35 | "a_word": ".word", 36 | "a_bss": "dfs %s", 37 | "a_seg": "seg", 38 | "a_curip": "PC", 39 | "a_public": "", 40 | "a_weak": "", 41 | "a_extrn": ".extern", 42 | "a_comdef": "", 43 | "a_align": ".align", 44 | "lbrace": "(", 45 | "rbrace": ")", 46 | "a_mod": "%", 47 | "a_band": "&", 48 | "a_bor": "|", 49 | "a_xor": "^", 50 | "a_bnot": "~", 51 | "a_shl": "<<", 52 | "a_shr": ">>", 53 | "a_sizeof_fmt": "size %s", 54 | } 55 | 56 | reg_names = regNames = [ 57 | "r0", "r1", "r2", "r3", "r4", 58 | "r5", "r6", "r7", "r8", 59 | "r9", "r10", "r11", "r12", "r13", 60 | "r14", "r15", "r16", "r17", "r18", "r19", "R20", "R21", 61 | "r22", "r23", "r24", "r25", "r26", 62 | "r27", "r28", "r29", "r30", "r31", 63 | #virutal 64 | "CS", "DS" 65 | ] 66 | 67 | instruc = instrs = [{'name': 'l.add', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.add rD,rA,rB'}, 68 | {'name': 'l.addc', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.addc rD,rA,rB'}, 69 | {'name': 'l.addi', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.addi rD,rA,I'}, 70 | {'name': 'l.addic', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.addic rD,rA,I'}, 71 | {'name': 'l.and', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.and rD,rA,rB'}, 72 | {'name': 'l.andi', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.andi rD,rA,K'}, 73 | {'name': 'l.bf', 'feature': CF_USE1, 'cmt': 'l.bf N'}, 74 | {'name': 'l.bnf', 'feature': CF_USE1, 'cmt': 'l.bnf N'}, 75 | {'name': 'l.cmov', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.cmov rD,rA,rB'}, 76 | {'name': 'l.csyn', 'feature': 0, 'cmt': 'l.csync'}, 77 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust1'}, 78 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust2'}, 79 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust3'}, 80 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust4'}, 81 | {'name': 'l.cust5', 'feature': CF_USE1 | CF_USE2 | CF_USE3 | CF_USE4 | CF_USE5, 'cmt': 'l.cust5 rD,rA,rB,L,K'}, 82 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust6'}, 83 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust7'}, 84 | {'name': 'l.cust', 'feature': 0, 'cmt': 'l.cust8'}, 85 | {'name': 'l.div', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.div rD,rA,rB'}, 86 | {'name': 'l.divu', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.divu rD,rA,rB'}, 87 | {'name': 'l.extbs', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.extbs rD,rA'}, 88 | {'name': 'l.extbz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.extbz rD,rA'}, 89 | {'name': 'l.exths', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.exths rD,rA'}, 90 | {'name': 'l.exthz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.exthz rD,rA'}, 91 | {'name': 'l.extws', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.extws rD,rA'}, 92 | {'name': 'l.extwz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.extwz rD,rA'}, 93 | {'name': 'l.ff1', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.ff1 rD,rA,rB'}, 94 | {'name': 'l.fl1', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.fl1 rD,rA,rB'}, 95 | {'name': 'l.j', 'feature': CF_USE1, 'cmt': 'l.j N'}, 96 | {'name': 'l.jal', 'feature': CF_USE1 | CF_CALL, 'cmt': 'l.jal N'}, 97 | {'name': 'l.jalr', 'feature': CF_USE1, 'cmt': 'l.jalr rB'}, 98 | {'name': 'l.jr', 'feature': CF_USE1, 'cmt': 'l.jr rB'}, 99 | {'name': 'l.lbs', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lbs rD,I(rA)'}, 100 | {'name': 'l.lbz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lbz rD,I(rA)'}, 101 | {'name': 'l.ld', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.ld rD,I(rA)'}, 102 | {'name': 'l.lhs', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lhs rD,I(rA)'}, 103 | {'name': 'l.lhz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lhz rD,I(rA)'}, 104 | {'name': 'l.lwa', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lwa rD,I(rA)'}, 105 | {'name': 'l.lws', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lws rD,I(rA)'}, 106 | {'name': 'l.lwz', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.lwz rD,I(rA)'}, 107 | {'name': 'l.mac', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.mac rA,rB'}, 108 | {'name': 'l.maci', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.maci rA,I'}, 109 | {'name': 'l.macrc', 'feature': CF_USE1, 'cmt': 'l.macrc rD'}, 110 | {'name': 'l.macu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.macu rA,rB'}, 111 | {'name': 'l.mfspr', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.mfspr rD,rA,K'}, 112 | {'name': 'l.movhi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.movhi rD,K'}, 113 | {'name': 'l.msb', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.msb rA,rB'}, 114 | {'name': 'l.msbu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.msbu rA,rB'}, 115 | {'name': 'l.msyn', 'feature': 0, 'cmt': 'l.msync'}, 116 | {'name': 'l.mtspr', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.mtspr rA,rB,K'}, 117 | {'name': 'l.mul', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.mul rD,rA,rB'}, 118 | {'name': 'l.muld', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.muld rA,rB'}, 119 | {'name': 'l.muldu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.muldu rA,rB'}, 120 | {'name': 'l.muli', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.muli rD,rA,I'}, 121 | {'name': 'l.mulu', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.mulu rD,rA,rB'}, 122 | {'name': 'l.nop', 'feature': CF_USE1, 'cmt': 'l.nop K'}, 123 | {'name': 'l.or', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.or rD,rA,rB'}, 124 | {'name': 'l.ori', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.ori rD,rA,K'}, 125 | {'name': 'l.psyn', 'feature': 0, 'cmt': 'l.psync'}, 126 | {'name': 'l.rf', 'feature': 0, 'cmt': 'l.rfe'}, 127 | {'name': 'l.ror', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.ror rD,rA,rB'}, 128 | {'name': 'l.rori', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.rori rD,rA,L'}, 129 | {'name': 'l.sb', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sb I(rA),rB'}, 130 | {'name': 'l.sd', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sd I(rA),rB'}, 131 | {'name': 'l.sfeq', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfeq rA,rB'}, 132 | {'name': 'l.sfeqi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfeqi rA,I'}, 133 | {'name': 'l.sfges', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfges rA,rB'}, 134 | {'name': 'l.sfgesi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgesi rA,I'}, 135 | {'name': 'l.sfgeu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgeu rA,rB'}, 136 | {'name': 'l.sfgeui', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgeui rA,I'}, 137 | {'name': 'l.sfgts', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgts rA,rB'}, 138 | {'name': 'l.sfgtsi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgtsi rA,I'}, 139 | {'name': 'l.sfgtu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgtu rA,rB'}, 140 | {'name': 'l.sfgtui', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfgtui rA,I'}, 141 | {'name': 'l.sflesi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sflesi rA,I'}, 142 | {'name': 'l.sfleu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfleu rA,rB'}, 143 | {'name': 'l.sfleui', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfleui rA,I'}, 144 | {'name': 'l.sflts', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sflts rA,rB'}, 145 | {'name': 'l.sfltsi', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfltsi rA,I'}, 146 | {'name': 'l.sfltu', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfltu rA,rB'}, 147 | {'name': 'l.sfltui', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfltui rA,I'}, 148 | {'name': 'l.sfne', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfne rA,rB'}, 149 | {'name': 'l.sfnei', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sfnei rA,I'}, 150 | {'name': 'l.sh', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sh I(rA),rB'}, 151 | {'name': 'l.sll', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.sll rD,rA,rB'}, 152 | {'name': 'l.slli', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.slli rD,rA,L'}, 153 | {'name': 'l.sra', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.sra rD,rA,rB'}, 154 | {'name': 'l.srai', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.srai rD,rA,L'}, 155 | {'name': 'l.srl', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.srl rD,rA,rB'}, 156 | {'name': 'l.srli', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.srli rD,rA,L'}, 157 | {'name': 'l.sub', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.sub rD,rA,rB'}, 158 | {'name': 'l.sw', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.sw I(rA),rB'}, 159 | {'name': 'l.swa', 'feature': CF_USE1 | CF_USE2, 'cmt': 'l.swa I(rA),rB'}, 160 | {'name': 'l.sys', 'feature': CF_USE1, 'cmt': 'l.sys K'}, 161 | {'name': 'l.trap', 'feature': CF_USE1, 'cmt': 'l.trap K'}, 162 | {'name': 'l.xor', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.xor rD,rA,rB'}, 163 | {'name': 'l.xori', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'l.xori rD,rA,I'}, 164 | {'name': 'lf.add.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.add.d rD,rA,rB'}, 165 | {'name': 'lf.add.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.add.s rD,rA,rB'}, 166 | {'name': 'lf.cust1.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.cust1.d rA,rB'}, 167 | {'name': 'lf.cust1.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.cust1.s rA,rB'}, 168 | {'name': 'lf.div.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.div.d rD,rA,rB'}, 169 | {'name': 'lf.div.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.div.s rD,rA,rB'}, 170 | {'name': 'lf.ftoi.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.ftoi.d rD,rA'}, 171 | {'name': 'lf.ftoi.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.ftoi.s rD,rA'}, 172 | {'name': 'lf.itof.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.itof.d rD,rA'}, 173 | {'name': 'lf.itof.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.itof.s rD,rA'}, 174 | {'name': 'lf.madd.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.madd.d rD,rA,rB'}, 175 | {'name': 'lf.madd.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.madd.s rD,rA,rB'}, 176 | {'name': 'lf.mul.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.mul.d rD,rA,rB'}, 177 | {'name': 'lf.mul.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.mul.s rD,rA,rB'}, 178 | {'name': 'lf.rem.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.rem.d rD,rA,rB'}, 179 | {'name': 'lf.rem.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.rem.s rD,rA,rB'}, 180 | {'name': 'lf.sfeq.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfeq.d rA,rB'}, 181 | {'name': 'lf.sfeq.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfeq.s rA,rB'}, 182 | {'name': 'lf.sfge.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfge.d rA,rB'}, 183 | {'name': 'lf.sfge.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfge.s rA,rB'}, 184 | {'name': 'lf.sfgt.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfgt.d rA,rB'}, 185 | {'name': 'lf.sfgt.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfgt.s rA,rB'}, 186 | {'name': 'lf.sfle.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfle.d rA,rB'}, 187 | {'name': 'lf.sfle.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfle.s rA,rB'}, 188 | {'name': 'lf.sflt.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sflt.d rA,rB'}, 189 | {'name': 'lf.sflt.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sflt.s rA,rB'}, 190 | {'name': 'lf.sfne.d', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfne.d rA,rB'}, 191 | {'name': 'lf.sfne.s', 'feature': CF_USE1 | CF_USE2, 'cmt': 'lf.sfne.s rA,rB'}, 192 | {'name': 'lf.sub.d', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.sub.d rD,rA,rB'}, 193 | {'name': 'lf.sub.s', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lf.sub.s rD,rA,rB'}, 194 | {'name': 'lv.add.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.add.b rD,rA,rB'}, 195 | {'name': 'lv.add.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.add.h rD,rA,rB'}, 196 | {'name': 'lv.adds.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.adds.b rD,rA,rB'}, 197 | {'name': 'lv.adds.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.adds.h rD,rA,rB'}, 198 | {'name': 'lv.addu.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.addu.b rD,rA,rB'}, 199 | {'name': 'lv.addu.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.addu.h rD,rA,rB'}, 200 | {'name': 'lv.addus.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.addus.b rD,rA,rB'}, 201 | {'name': 'lv.addus.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.addus.h rD,rA,rB'}, 202 | {'name': 'lv.all_eq.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_eq.b rD,rA,rB'}, 203 | {'name': 'lv.all_eq.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_eq.h rD,rA,rB'}, 204 | {'name': 'lv.all_ge.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_ge.b rD,rA,rB'}, 205 | {'name': 'lv.all_ge.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_ge.h rD,rA,rB'}, 206 | {'name': 'lv.all_gt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_gt.b rD,rA,rB'}, 207 | {'name': 'lv.all_gt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_gt.h rD,rA,rB'}, 208 | {'name': 'lv.all_le.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_le.b rD,rA,rB'}, 209 | {'name': 'lv.all_le.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_le.h rD,rA,rB'}, 210 | {'name': 'lv.all_lt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_lt.b rD,rA,rB'}, 211 | {'name': 'lv.all_lt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_lt.h rD,rA,rB'}, 212 | {'name': 'lv.all_ne.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_ne.b rD,rA,rB'}, 213 | {'name': 'lv.all_ne.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.all_ne.h rD,rA,rB'}, 214 | {'name': 'lv.and', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.and rD,rA,rB'}, 215 | {'name': 'lv.any_eq.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_eq.b rD,rA,rB'}, 216 | {'name': 'lv.any_eq.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_eq.h rD,rA,rB'}, 217 | {'name': 'lv.any_ge.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_ge.b rD,rA,rB'}, 218 | {'name': 'lv.any_ge.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_ge.h rD,rA,rB'}, 219 | {'name': 'lv.any_gt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_gt.b rD,rA,rB'}, 220 | {'name': 'lv.any_gt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_gt.h rD,rA,rB'}, 221 | {'name': 'lv.any_le.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_le.b rD,rA,rB'}, 222 | {'name': 'lv.any_le.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_le.h rD,rA,rB'}, 223 | {'name': 'lv.any_lt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_lt.b rD,rA,rB'}, 224 | {'name': 'lv.any_lt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_lt.h rD,rA,rB'}, 225 | {'name': 'lv.any_ne.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_ne.b rD,rA,rB'}, 226 | {'name': 'lv.any_ne.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.any_ne.h rD,rA,rB'}, 227 | {'name': 'lv.avg.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.avg.b rD,rA,rB'}, 228 | {'name': 'lv.avg.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.avg.h rD,rA,rB'}, 229 | {'name': 'lv.cmp_eq.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_eq.b rD,rA,rB'}, 230 | {'name': 'lv.cmp_eq.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_eq.h rD,rA,rB'}, 231 | {'name': 'lv.cmp_ge.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_ge.b rD,rA,rB'}, 232 | {'name': 'lv.cmp_ge.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_ge.h rD,rA,rB'}, 233 | {'name': 'lv.cmp_gt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_gt.b rD,rA,rB'}, 234 | {'name': 'lv.cmp_gt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_gt.h rD,rA,rB'}, 235 | {'name': 'lv.cmp_le.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_le.b rD,rA,rB'}, 236 | {'name': 'lv.cmp_le.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_le.h rD,rA,rB'}, 237 | {'name': 'lv.cmp_lt.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_lt.b rD,rA,rB'}, 238 | {'name': 'lv.cmp_lt.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_lt.h rD,rA,rB'}, 239 | {'name': 'lv.cmp_ne.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_ne.b rD,rA,rB'}, 240 | {'name': 'lv.cmp_ne.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.cmp_ne.h rD,rA,rB'}, 241 | {'name': 'lv.cust', 'feature': 0, 'cmt': 'lv.cust1'}, 242 | {'name': 'lv.cust', 'feature': 0, 'cmt': 'lv.cust2'}, 243 | {'name': 'lv.cust', 'feature': 0, 'cmt': 'lv.cust3'}, 244 | {'name': 'lv.cust', 'feature': 0, 'cmt': 'lv.cust4'}, 245 | {'name': 'lv.madds.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.madds.h rD,rA,rB'}, 246 | {'name': 'lv.max.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.max.b rD,rA,rB'}, 247 | {'name': 'lv.max.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.max.h rD,rA,rB'}, 248 | {'name': 'lv.merge.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.merge.b rD,rA,rB'}, 249 | {'name': 'lv.merge.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.merge.h rD,rA,rB'}, 250 | {'name': 'lv.min.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.min.b rD,rA,rB'}, 251 | {'name': 'lv.min.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.min.h rD,rA,rB'}, 252 | {'name': 'lv.msubs.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.msubs.h rD,rA,rB'}, 253 | {'name': 'lv.muls.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.muls.h rD,rA,rB'}, 254 | {'name': 'lv.nand', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.nand rD,rA,rB'}, 255 | {'name': 'lv.nor', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.nor rD,rA,rB'}, 256 | {'name': 'lv.or', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.or rD,rA,rB'}, 257 | {'name': 'lv.pack.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.pack.b rD,rA,rB'}, 258 | {'name': 'lv.pack.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.pack.h rD,rA,rB'}, 259 | {'name': 'lv.packs.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.packs.b rD,rA,rB'}, 260 | {'name': 'lv.packs.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.packs.h rD,rA,rB'}, 261 | {'name': 'lv.packus.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.packus.b rD,rA,rB'}, 262 | {'name': 'lv.packus.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.packus.h rD,rA,rB'}, 263 | {'name': 'lv.perm.n', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.perm.n rD,rA,rB'}, 264 | {'name': 'lv.rl.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.rl.b rD,rA,rB'}, 265 | {'name': 'lv.rl.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.rl.h rD,rA,rB'}, 266 | {'name': 'lv.sll', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sll rD,rA,rB'}, 267 | {'name': 'lv.sll.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sll.b rD,rA,rB'}, 268 | {'name': 'lv.sll.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sll.h rD,rA,rB'}, 269 | {'name': 'lv.sra.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sra.b rD,rA,rB'}, 270 | {'name': 'lv.sra.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sra.h rD,rA,rB'}, 271 | {'name': 'lv.srl', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.srl rD,rA,rB'}, 272 | {'name': 'lv.srl.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.srl.b rD,rA,rB'}, 273 | {'name': 'lv.srl.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.srl.h rD,rA,rB'}, 274 | {'name': 'lv.sub.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sub.b rD,rA,rB'}, 275 | {'name': 'lv.sub.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.sub.h rD,rA,rB'}, 276 | {'name': 'lv.subs.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.subs.h rD,rA,rB'}, 277 | {'name': 'lv.subu.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.subu.b rD,rA,rB'}, 278 | {'name': 'lv.subu.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.subu.h rD,rA,rB'}, 279 | {'name': 'lv.subus.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.subus.b rD,rA,rB'}, 280 | {'name': 'lv.subus.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.subus.h rD,rA,rB'}, 281 | {'name': 'lv.unpack.b', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.unpack.b rD,rA,rB'}, 282 | {'name': 'lv.unpack.h', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.unpack.h rD,rA,rB'}, 283 | {'name': 'lv.xor', 'feature': CF_USE1 | CF_USE2 | CF_USE3, 'cmt': 'lv.xor rD,rA,rB'}] 284 | 285 | instruc_end = len(instruc) 286 | 287 | def __init__(self): 288 | processor_t.__init__(self) 289 | self._init_instructions() 290 | self._init_registers() 291 | self.delayed_jmp = dict() 292 | 293 | def _init_instructions(self): 294 | self.inames = {} 295 | for idx, ins in enumerate(self.instrs): 296 | self.inames[ins['name']] = idx 297 | 298 | def _init_registers(self): 299 | self.reg_ids = {} 300 | for i, reg in enumerate(self.reg_names): 301 | self.reg_ids[reg] = i 302 | self.regFirstSreg = self.regCodeSreg = self.reg_ids["CS"] 303 | self.regLastSreg = self.regDataSreg = self.reg_ids["DS"] 304 | 305 | def _read_cmd_dword(self): 306 | ea = self.cmd.ea + self.cmd.size 307 | dword = get_full_long(ea) 308 | self.cmd.size += 4 309 | return dword 310 | 311 | def _ana(self): 312 | cmd = self.cmd 313 | opcode = self._read_cmd_dword() 314 | op_m5_sl16_sr16 = ((opcode & 0x1f0000) >> 16) 315 | op_m16_sl0_sr0 = ((opcode & 0xffff) >> 0) 316 | op_m1_sl16_sr16 = ((opcode & 0x10000) >> 16) 317 | op_m6_sl0_sr0 = ((opcode & 0x3f) >> 0) 318 | op_m4_sl6_sr6 = ((opcode & 0x3c0) >> 6) 319 | op_m8_sl24_sr24 = ((opcode & 0xff000000) >> 24) 320 | op_m4_sl0_sr0 = ((opcode & 0xf) >> 0) 321 | op_m2_sl6_sr6 = ((opcode & 0xc0) >> 6) 322 | op_m8_sl0_sr0 = ((opcode & 0xff) >> 0) 323 | op_m5_sl21_sr21 = ((opcode & 0x3e00000) >> 21) 324 | op_m32_sl0_sr0 = ((opcode & 0xffffffff) >> 0) 325 | op_m17_sl0_sr0 = ((opcode & 0x1ffff) >> 0) 326 | op_m2_sl8_sr8 = ((opcode & 0x300) >> 8) 327 | op_m6_sl5_sr5 = ((opcode & 0x7e0) >> 5) 328 | op_m26_sl0_sr0 = ((opcode & 0x3ffffff) >> 0) 329 | op_m4_sl4_sr4 = ((opcode & 0xf0) >> 4) 330 | op_m11_sl0_sr0 = ((opcode & 0x7ff) >> 0) 331 | op_m5_sl11_sr11 = ((opcode & 0xf800) >> 11) 332 | op_m11_sl21_sr21 = ((opcode & 0xffe00000) >> 21) 333 | op_m5_sl0_sr0 = ((opcode & 0x1f) >> 0) 334 | op_m6_sl26_sr26 = ((opcode & 0xfc000000) >> 26) 335 | op_m5_sl21_sr10 = ((opcode & 0x3e00000) >> 10) 336 | op_m16_sl16_sr16 = ((opcode & 0xffff0000) >> 16) 337 | 338 | if (op_m4_sl0_sr0 == 0x0) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 339 | cmd.itype = self.inames['l.add'] 340 | cmd[0].type = o_reg 341 | cmd[0].reg = op_m5_sl21_sr21 342 | cmd[0].dtyp = dt_word 343 | cmd[1].type = o_reg 344 | cmd[1].reg = op_m5_sl16_sr16 345 | cmd[1].dtyp = dt_word 346 | cmd[2].type = o_reg 347 | cmd[2].reg = op_m5_sl11_sr11 348 | cmd[2].dtyp = dt_word 349 | elif (op_m4_sl0_sr0 == 0x1) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 350 | cmd.itype = self.inames['l.addc'] 351 | cmd[0].type = o_reg 352 | cmd[0].reg = op_m5_sl21_sr21 353 | cmd[0].dtyp = dt_word 354 | cmd[1].type = o_reg 355 | cmd[1].reg = op_m5_sl16_sr16 356 | cmd[1].dtyp = dt_word 357 | cmd[2].type = o_reg 358 | cmd[2].reg = op_m5_sl11_sr11 359 | cmd[2].dtyp = dt_word 360 | elif (op_m6_sl26_sr26 == 0x27): 361 | cmd.itype = self.inames['l.addi'] 362 | cmd[0].type = o_reg 363 | cmd[0].reg = op_m5_sl21_sr21 364 | cmd[0].dtyp = dt_word 365 | cmd[1].type = o_reg 366 | cmd[1].reg = op_m5_sl16_sr16 367 | cmd[1].dtyp = dt_word 368 | cmd[2].type = o_imm 369 | cmd[2].value = SIGNEXT(op_m16_sl0_sr0, 16) 370 | cmd[2].dtyp = dt_word 371 | elif (op_m6_sl26_sr26 == 0x28): 372 | cmd.itype = self.inames['l.addic'] 373 | cmd[0].type = o_reg 374 | cmd[0].reg = op_m5_sl21_sr21 375 | cmd[0].dtyp = dt_word 376 | cmd[1].type = o_reg 377 | cmd[1].reg = op_m5_sl16_sr16 378 | cmd[1].dtyp = dt_word 379 | cmd[2].type = o_imm 380 | cmd[2].value = SIGNEXT(op_m16_sl0_sr0, 16) 381 | cmd[2].dtyp = dt_word 382 | elif (op_m4_sl0_sr0 == 0x3) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 383 | cmd.itype = self.inames['l.and'] 384 | cmd[0].type = o_reg 385 | cmd[0].reg = op_m5_sl21_sr21 386 | cmd[0].dtyp = dt_word 387 | cmd[1].type = o_reg 388 | cmd[1].reg = op_m5_sl16_sr16 389 | cmd[1].dtyp = dt_word 390 | cmd[2].type = o_reg 391 | cmd[2].reg = op_m5_sl11_sr11 392 | cmd[2].dtyp = dt_word 393 | elif (op_m6_sl26_sr26 == 0x29): 394 | cmd.itype = self.inames['l.andi'] 395 | cmd[0].type = o_reg 396 | cmd[0].reg = op_m5_sl21_sr21 397 | cmd[0].dtyp = dt_word 398 | cmd[1].type = o_reg 399 | cmd[1].reg = op_m5_sl16_sr16 400 | cmd[1].dtyp = dt_word 401 | cmd[2].type = o_imm 402 | cmd[2].value = op_m16_sl0_sr0 403 | cmd[2].dtyp = dt_word 404 | elif (op_m6_sl26_sr26 == 0x4): 405 | cmd.itype = self.inames['l.bf'] 406 | cmd[0].type = o_near 407 | cmd[0].addr = cmd.ea + 4*SIGNEXT(op_m26_sl0_sr0, 26) 408 | cmd[0].dtyp = dt_word 409 | elif (op_m6_sl26_sr26 == 0x3): 410 | cmd.itype = self.inames['l.bnf'] 411 | cmd[0].type = o_near 412 | cmd[0].addr = cmd.ea + 4*SIGNEXT(op_m26_sl0_sr0, 26) 413 | cmd[0].dtyp = dt_word 414 | elif (op_m4_sl0_sr0 == 0xe) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 415 | cmd.itype = self.inames['l.cmov'] 416 | cmd[0].type = o_reg 417 | cmd[0].reg = op_m5_sl21_sr21 418 | cmd[0].dtyp = dt_word 419 | cmd[1].type = o_reg 420 | cmd[1].reg = op_m5_sl16_sr16 421 | cmd[1].dtyp = dt_word 422 | cmd[2].type = o_reg 423 | cmd[2].reg = op_m5_sl11_sr11 424 | cmd[2].dtyp = dt_word 425 | elif (op_m32_sl0_sr0 == 0x23000000): 426 | cmd.itype = self.inames['l.csyn'] 427 | elif (op_m6_sl26_sr26 == 0x1c): 428 | cmd.itype = self.inames['l.cust'] 429 | elif (op_m6_sl26_sr26 == 0x1d): 430 | cmd.itype = self.inames['l.cust'] 431 | elif (op_m6_sl26_sr26 == 0x1e): 432 | cmd.itype = self.inames['l.cust'] 433 | elif (op_m6_sl26_sr26 == 0x1f): 434 | cmd.itype = self.inames['l.cust'] 435 | elif (op_m6_sl26_sr26 == 0x3c): 436 | cmd.itype = self.inames['l.cust5'] 437 | cmd[0].type = o_reg 438 | cmd[0].reg = op_m5_sl21_sr21 439 | cmd[0].dtyp = dt_word 440 | cmd[1].type = o_reg 441 | cmd[1].reg = op_m5_sl16_sr16 442 | cmd[1].dtyp = dt_word 443 | cmd[2].type = o_reg 444 | cmd[2].reg = op_m5_sl11_sr11 445 | cmd[2].dtyp = dt_word 446 | cmd[3].type = o_imm 447 | cmd[3].value = op_m6_sl5_sr5 448 | cmd[3].dtyp = dt_word 449 | cmd[4].type = o_imm 450 | cmd[4].value = op_m5_sl0_sr0 451 | cmd[4].dtyp = dt_word 452 | elif (op_m6_sl26_sr26 == 0x3d): 453 | cmd.itype = self.inames['l.cust'] 454 | elif (op_m6_sl26_sr26 == 0x3e): 455 | cmd.itype = self.inames['l.cust'] 456 | elif (op_m6_sl26_sr26 == 0x3f): 457 | cmd.itype = self.inames['l.cust'] 458 | elif (op_m4_sl0_sr0 == 0x9) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 459 | cmd.itype = self.inames['l.div'] 460 | cmd[0].type = o_reg 461 | cmd[0].reg = op_m5_sl21_sr21 462 | cmd[0].dtyp = dt_word 463 | cmd[1].type = o_reg 464 | cmd[1].reg = op_m5_sl16_sr16 465 | cmd[1].dtyp = dt_word 466 | cmd[2].type = o_reg 467 | cmd[2].reg = op_m5_sl11_sr11 468 | cmd[2].dtyp = dt_word 469 | elif (op_m4_sl0_sr0 == 0xa) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 470 | cmd.itype = self.inames['l.divu'] 471 | cmd[0].type = o_reg 472 | cmd[0].reg = op_m5_sl21_sr21 473 | cmd[0].dtyp = dt_word 474 | cmd[1].type = o_reg 475 | cmd[1].reg = op_m5_sl16_sr16 476 | cmd[1].dtyp = dt_word 477 | cmd[2].type = o_reg 478 | cmd[2].reg = op_m5_sl11_sr11 479 | cmd[2].dtyp = dt_word 480 | elif (op_m4_sl0_sr0 == 0xc) and (op_m4_sl6_sr6 == 0x1) and (op_m6_sl26_sr26 == 0x38): 481 | cmd.itype = self.inames['l.extbs'] 482 | cmd[0].type = o_reg 483 | cmd[0].reg = op_m5_sl21_sr21 484 | cmd[0].dtyp = dt_word 485 | cmd[1].type = o_reg 486 | cmd[1].reg = op_m5_sl16_sr16 487 | cmd[1].dtyp = dt_word 488 | elif (op_m4_sl0_sr0 == 0xc) and (op_m4_sl6_sr6 == 0x3) and (op_m6_sl26_sr26 == 0x38): 489 | cmd.itype = self.inames['l.extbz'] 490 | cmd[0].type = o_reg 491 | cmd[0].reg = op_m5_sl21_sr21 492 | cmd[0].dtyp = dt_word 493 | cmd[1].type = o_reg 494 | cmd[1].reg = op_m5_sl16_sr16 495 | cmd[1].dtyp = dt_word 496 | elif (op_m4_sl0_sr0 == 0xc) and (op_m4_sl6_sr6 == 0x0) and (op_m6_sl26_sr26 == 0x38): 497 | cmd.itype = self.inames['l.exths'] 498 | cmd[0].type = o_reg 499 | cmd[0].reg = op_m5_sl21_sr21 500 | cmd[0].dtyp = dt_word 501 | cmd[1].type = o_reg 502 | cmd[1].reg = op_m5_sl16_sr16 503 | cmd[1].dtyp = dt_word 504 | elif (op_m4_sl0_sr0 == 0xc) and (op_m4_sl6_sr6 == 0x2) and (op_m6_sl26_sr26 == 0x38): 505 | cmd.itype = self.inames['l.exthz'] 506 | cmd[0].type = o_reg 507 | cmd[0].reg = op_m5_sl21_sr21 508 | cmd[0].dtyp = dt_word 509 | cmd[1].type = o_reg 510 | cmd[1].reg = op_m5_sl16_sr16 511 | cmd[1].dtyp = dt_word 512 | elif (op_m4_sl0_sr0 == 0xd) and (op_m4_sl6_sr6 == 0x0) and (op_m6_sl26_sr26 == 0x38): 513 | cmd.itype = self.inames['l.extws'] 514 | cmd[0].type = o_reg 515 | cmd[0].reg = op_m5_sl21_sr21 516 | cmd[0].dtyp = dt_word 517 | cmd[1].type = o_reg 518 | cmd[1].reg = op_m5_sl16_sr16 519 | cmd[1].dtyp = dt_word 520 | elif (op_m4_sl0_sr0 == 0xd) and (op_m4_sl6_sr6 == 0x1) and (op_m6_sl26_sr26 == 0x38): 521 | cmd.itype = self.inames['l.extwz'] 522 | cmd[0].type = o_reg 523 | cmd[0].reg = op_m5_sl21_sr21 524 | cmd[0].dtyp = dt_word 525 | cmd[1].type = o_reg 526 | cmd[1].reg = op_m5_sl16_sr16 527 | cmd[1].dtyp = dt_word 528 | elif (op_m4_sl0_sr0 == 0xf) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 529 | cmd.itype = self.inames['l.ff1'] 530 | cmd[0].type = o_reg 531 | cmd[0].reg = op_m5_sl21_sr21 532 | cmd[0].dtyp = dt_word 533 | cmd[1].type = o_reg 534 | cmd[1].reg = op_m5_sl16_sr16 535 | cmd[1].dtyp = dt_word 536 | elif (op_m4_sl0_sr0 == 0xf) and (op_m2_sl8_sr8 == 0x1) and (op_m6_sl26_sr26 == 0x38): 537 | cmd.itype = self.inames['l.fl1'] 538 | cmd[0].type = o_reg 539 | cmd[0].reg = op_m5_sl21_sr21 540 | cmd[0].dtyp = dt_word 541 | cmd[1].type = o_reg 542 | cmd[1].reg = op_m5_sl16_sr16 543 | cmd[1].dtyp = dt_word 544 | elif (op_m6_sl26_sr26 == 0x0): 545 | cmd.itype = self.inames['l.j'] 546 | cmd[0].type = o_near 547 | cmd[0].addr = cmd.ea + 4*SIGNEXT(op_m26_sl0_sr0, 26) 548 | cmd[0].dtyp = dt_word 549 | elif (op_m6_sl26_sr26 == 0x1): 550 | cmd.itype = self.inames['l.jal'] 551 | cmd[0].type = o_near 552 | cmd[0].addr = cmd.ea + 4*SIGNEXT(op_m26_sl0_sr0, 26) 553 | cmd[0].dtyp = dt_word 554 | elif (op_m6_sl26_sr26 == 0x12): 555 | cmd.itype = self.inames['l.jalr'] 556 | cmd[0].type = o_reg 557 | cmd[0].reg = op_m5_sl11_sr11 558 | cmd[0].dtyp = dt_word 559 | elif (op_m6_sl26_sr26 == 0x11): 560 | cmd.itype = self.inames['l.jr'] 561 | cmd[0].type = o_reg 562 | cmd[0].reg = op_m5_sl11_sr11 563 | cmd[0].dtyp = dt_word 564 | elif (op_m6_sl26_sr26 == 0x24): 565 | cmd.itype = self.inames['l.lbs'] 566 | cmd[0].type = o_reg 567 | cmd[0].reg = op_m5_sl21_sr21 568 | cmd[0].dtyp = dt_word 569 | cmd[1].type = o_displ 570 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 571 | cmd[1].reg = op_m5_sl16_sr16 572 | elif (op_m6_sl26_sr26 == 0x23): 573 | cmd.itype = self.inames['l.lbz'] 574 | cmd[0].type = o_reg 575 | cmd[0].reg = op_m5_sl21_sr21 576 | cmd[0].dtyp = dt_word 577 | cmd[1].type = o_displ 578 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 579 | cmd[1].reg = op_m5_sl16_sr16 580 | elif (op_m6_sl26_sr26 == 0x20): 581 | cmd.itype = self.inames['l.ld'] 582 | cmd[0].type = o_reg 583 | cmd[0].reg = op_m5_sl21_sr21 584 | cmd[0].dtyp = dt_word 585 | cmd[1].type = o_displ 586 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 587 | cmd[1].reg = op_m5_sl16_sr16 588 | elif (op_m6_sl26_sr26 == 0x26): 589 | cmd.itype = self.inames['l.lhs'] 590 | cmd[0].type = o_reg 591 | cmd[0].reg = op_m5_sl21_sr21 592 | cmd[0].dtyp = dt_word 593 | cmd[1].type = o_displ 594 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 595 | cmd[1].reg = op_m5_sl16_sr16 596 | elif (op_m6_sl26_sr26 == 0x25): 597 | cmd.itype = self.inames['l.lhz'] 598 | cmd[0].type = o_reg 599 | cmd[0].reg = op_m5_sl21_sr21 600 | cmd[0].dtyp = dt_word 601 | cmd[1].type = o_displ 602 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 603 | cmd[1].reg = op_m5_sl16_sr16 604 | elif (op_m6_sl26_sr26 == 0x1b): 605 | cmd.itype = self.inames['l.lwa'] 606 | cmd[0].type = o_reg 607 | cmd[0].reg = op_m5_sl21_sr21 608 | cmd[0].dtyp = dt_word 609 | cmd[1].type = o_displ 610 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 611 | cmd[1].reg = op_m5_sl16_sr16 612 | elif (op_m6_sl26_sr26 == 0x22): 613 | cmd.itype = self.inames['l.lws'] 614 | cmd[0].type = o_reg 615 | cmd[0].reg = op_m5_sl21_sr21 616 | cmd[0].dtyp = dt_word 617 | cmd[1].type = o_displ 618 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 619 | cmd[1].reg = op_m5_sl16_sr16 620 | elif (op_m6_sl26_sr26 == 0x21): 621 | cmd.itype = self.inames['l.lwz'] 622 | cmd[0].type = o_reg 623 | cmd[0].reg = op_m5_sl21_sr21 624 | cmd[0].dtyp = dt_word 625 | cmd[1].type = o_displ 626 | cmd[1].addr = SIGNEXT(op_m16_sl0_sr0, 16) 627 | cmd[1].reg = op_m5_sl16_sr16 628 | elif (op_m4_sl0_sr0 == 0x1) and (op_m6_sl26_sr26 == 0x31): 629 | cmd.itype = self.inames['l.mac'] 630 | cmd[0].type = o_reg 631 | cmd[0].reg = op_m5_sl16_sr16 632 | cmd[0].dtyp = dt_word 633 | cmd[1].type = o_reg 634 | cmd[1].reg = op_m5_sl11_sr11 635 | cmd[1].dtyp = dt_word 636 | elif (op_m6_sl26_sr26 == 0x13): 637 | cmd.itype = self.inames['l.maci'] 638 | cmd[0].type = o_reg 639 | cmd[0].reg = op_m5_sl16_sr16 640 | cmd[0].dtyp = dt_word 641 | cmd[1].type = o_imm 642 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 643 | cmd[1].dtyp = dt_word 644 | elif (op_m17_sl0_sr0 == 0x10000) and (op_m6_sl26_sr26 == 0x6): 645 | cmd.itype = self.inames['l.macrc'] 646 | cmd[0].type = o_reg 647 | cmd[0].reg = op_m5_sl21_sr21 648 | cmd[0].dtyp = dt_word 649 | elif (op_m4_sl0_sr0 == 0x3) and (op_m6_sl26_sr26 == 0x31): 650 | cmd.itype = self.inames['l.macu'] 651 | cmd[0].type = o_reg 652 | cmd[0].reg = op_m5_sl16_sr16 653 | cmd[0].dtyp = dt_word 654 | cmd[1].type = o_reg 655 | cmd[1].reg = op_m5_sl11_sr11 656 | cmd[1].dtyp = dt_word 657 | elif (op_m6_sl26_sr26 == 0x2d): 658 | cmd.itype = self.inames['l.mfspr'] 659 | cmd[0].type = o_reg 660 | cmd[0].reg = op_m5_sl21_sr21 661 | cmd[0].dtyp = dt_word 662 | cmd[1].type = o_reg 663 | cmd[1].reg = op_m5_sl16_sr16 664 | cmd[1].dtyp = dt_word 665 | cmd[2].type = o_imm 666 | cmd[2].value = op_m16_sl0_sr0 667 | cmd[2].dtyp = dt_word 668 | elif (op_m1_sl16_sr16 == 0x0) and (op_m6_sl26_sr26 == 0x6): 669 | cmd.itype = self.inames['l.movhi'] 670 | cmd[0].type = o_reg 671 | cmd[0].reg = op_m5_sl21_sr21 672 | cmd[0].dtyp = dt_word 673 | cmd[1].type = o_imm 674 | cmd[1].value = op_m16_sl0_sr0 675 | cmd[1].dtyp = dt_word 676 | elif (op_m4_sl0_sr0 == 0x2) and (op_m6_sl26_sr26 == 0x31): 677 | cmd.itype = self.inames['l.msb'] 678 | cmd[0].type = o_reg 679 | cmd[0].reg = op_m5_sl16_sr16 680 | cmd[0].dtyp = dt_word 681 | cmd[1].type = o_reg 682 | cmd[1].reg = op_m5_sl11_sr11 683 | cmd[1].dtyp = dt_word 684 | elif (op_m4_sl0_sr0 == 0x4) and (op_m6_sl26_sr26 == 0x31): 685 | cmd.itype = self.inames['l.msbu'] 686 | cmd[0].type = o_reg 687 | cmd[0].reg = op_m5_sl16_sr16 688 | cmd[0].dtyp = dt_word 689 | cmd[1].type = o_reg 690 | cmd[1].reg = op_m5_sl11_sr11 691 | cmd[1].dtyp = dt_word 692 | elif (op_m32_sl0_sr0 == 0x22000000): 693 | cmd.itype = self.inames['l.msyn'] 694 | elif (op_m6_sl26_sr26 == 0x30): 695 | cmd.itype = self.inames['l.mtspr'] 696 | cmd[0].type = o_imm 697 | cmd[0].value = op_m5_sl21_sr21 698 | cmd[0].dtyp = dt_word 699 | cmd[1].type = o_reg 700 | cmd[1].reg = op_m5_sl16_sr16 701 | cmd[1].dtyp = dt_word 702 | cmd[2].type = o_reg 703 | cmd[2].reg = op_m5_sl11_sr11 704 | cmd[2].dtyp = dt_word 705 | cmd[3].type = o_imm 706 | cmd[3].value = op_m11_sl0_sr0 707 | cmd[3].dtyp = dt_word 708 | elif (op_m4_sl0_sr0 == 0x6) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 709 | cmd.itype = self.inames['l.mul'] 710 | cmd[0].type = o_reg 711 | cmd[0].reg = op_m5_sl21_sr21 712 | cmd[0].dtyp = dt_word 713 | cmd[1].type = o_reg 714 | cmd[1].reg = op_m5_sl16_sr16 715 | cmd[1].dtyp = dt_word 716 | cmd[2].type = o_reg 717 | cmd[2].reg = op_m5_sl11_sr11 718 | cmd[2].dtyp = dt_word 719 | elif (op_m4_sl0_sr0 == 0x7) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 720 | cmd.itype = self.inames['l.muld'] 721 | cmd[0].type = o_reg 722 | cmd[0].reg = op_m5_sl16_sr16 723 | cmd[0].dtyp = dt_word 724 | cmd[1].type = o_reg 725 | cmd[1].reg = op_m5_sl11_sr11 726 | cmd[1].dtyp = dt_word 727 | elif (op_m4_sl0_sr0 == 0xc) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 728 | cmd.itype = self.inames['l.muldu'] 729 | cmd[0].type = o_reg 730 | cmd[0].reg = op_m5_sl16_sr16 731 | cmd[0].dtyp = dt_word 732 | cmd[1].type = o_reg 733 | cmd[1].reg = op_m5_sl11_sr11 734 | cmd[1].dtyp = dt_word 735 | elif (op_m6_sl26_sr26 == 0x2c): 736 | cmd.itype = self.inames['l.muli'] 737 | cmd[0].type = o_reg 738 | cmd[0].reg = op_m5_sl21_sr21 739 | cmd[0].dtyp = dt_word 740 | cmd[1].type = o_reg 741 | cmd[1].reg = op_m5_sl16_sr16 742 | cmd[1].dtyp = dt_word 743 | cmd[2].type = o_imm 744 | cmd[2].value = SIGNEXT(op_m16_sl0_sr0, 16) 745 | cmd[2].dtyp = dt_word 746 | elif (op_m4_sl0_sr0 == 0xb) and (op_m2_sl8_sr8 == 0x3) and (op_m6_sl26_sr26 == 0x38): 747 | cmd.itype = self.inames['l.mulu'] 748 | cmd[0].type = o_reg 749 | cmd[0].reg = op_m5_sl21_sr21 750 | cmd[0].dtyp = dt_word 751 | cmd[1].type = o_reg 752 | cmd[1].reg = op_m5_sl16_sr16 753 | cmd[1].dtyp = dt_word 754 | cmd[2].type = o_reg 755 | cmd[2].reg = op_m5_sl11_sr11 756 | cmd[2].dtyp = dt_word 757 | elif (op_m8_sl24_sr24 == 0x15): 758 | cmd.itype = self.inames['l.nop'] 759 | cmd[0].type = o_imm 760 | cmd[0].value = op_m16_sl0_sr0 761 | cmd[0].dtyp = dt_word 762 | elif (op_m4_sl0_sr0 == 0x4) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 763 | cmd.itype = self.inames['l.or'] 764 | cmd[0].type = o_reg 765 | cmd[0].reg = op_m5_sl21_sr21 766 | cmd[0].dtyp = dt_word 767 | cmd[1].type = o_reg 768 | cmd[1].reg = op_m5_sl16_sr16 769 | cmd[1].dtyp = dt_word 770 | cmd[2].type = o_reg 771 | cmd[2].reg = op_m5_sl11_sr11 772 | cmd[2].dtyp = dt_word 773 | elif (op_m6_sl26_sr26 == 0x2a): 774 | cmd.itype = self.inames['l.ori'] 775 | cmd[0].type = o_reg 776 | cmd[0].reg = op_m5_sl21_sr21 777 | cmd[0].dtyp = dt_word 778 | cmd[1].type = o_reg 779 | cmd[1].reg = op_m5_sl16_sr16 780 | cmd[1].dtyp = dt_word 781 | cmd[2].type = o_imm 782 | cmd[2].value = op_m16_sl0_sr0 783 | cmd[2].dtyp = dt_word 784 | elif (op_m32_sl0_sr0 == 0x22800000): 785 | cmd.itype = self.inames['l.psyn'] 786 | elif (op_m6_sl26_sr26 == 0x9): 787 | cmd.itype = self.inames['l.rf'] 788 | elif (op_m4_sl0_sr0 == 0x8) and (op_m4_sl6_sr6 == 0x3) and (op_m6_sl26_sr26 == 0x38): 789 | cmd.itype = self.inames['l.ror'] 790 | cmd[0].type = o_reg 791 | cmd[0].reg = op_m5_sl21_sr21 792 | cmd[0].dtyp = dt_word 793 | cmd[1].type = o_reg 794 | cmd[1].reg = op_m5_sl16_sr16 795 | cmd[1].dtyp = dt_word 796 | cmd[2].type = o_reg 797 | cmd[2].reg = op_m5_sl11_sr11 798 | cmd[2].dtyp = dt_word 799 | elif (op_m2_sl6_sr6 == 0x3) and (op_m6_sl26_sr26 == 0x2e): 800 | cmd.itype = self.inames['l.rori'] 801 | cmd[0].type = o_reg 802 | cmd[0].reg = op_m5_sl21_sr21 803 | cmd[0].dtyp = dt_word 804 | cmd[1].type = o_reg 805 | cmd[1].reg = op_m5_sl16_sr16 806 | cmd[1].dtyp = dt_word 807 | cmd[2].type = o_imm 808 | cmd[2].value = op_m6_sl0_sr0 809 | cmd[2].dtyp = dt_word 810 | elif (op_m6_sl26_sr26 == 0x36): 811 | cmd.itype = self.inames['l.sb'] 812 | cmd[0].type = o_reg 813 | cmd[0].reg = op_m5_sl11_sr11 814 | cmd[0].dtyp = dt_word 815 | cmd[1].type = o_displ 816 | cmd[1].addr = SIGNEXT(op_m11_sl0_sr0 | op_m5_sl21_sr10, 16) 817 | cmd[1].reg = op_m5_sl16_sr16 818 | elif (op_m6_sl26_sr26 == 0x34): 819 | cmd.itype = self.inames['l.sd'] 820 | cmd[0].type = o_reg 821 | cmd[0].reg = op_m5_sl11_sr11 822 | cmd[0].dtyp = dt_word 823 | cmd[1].type = o_displ 824 | cmd[1].addr = SIGNEXT(op_m11_sl0_sr0 | op_m5_sl21_sr10, 16) 825 | cmd[1].reg = op_m5_sl16_sr16 826 | elif (op_m11_sl21_sr21 == 0x720): 827 | cmd.itype = self.inames['l.sfeq'] 828 | cmd[0].type = o_reg 829 | cmd[0].reg = op_m5_sl16_sr16 830 | cmd[0].dtyp = dt_word 831 | cmd[1].type = o_reg 832 | cmd[1].reg = op_m5_sl11_sr11 833 | cmd[1].dtyp = dt_word 834 | elif (op_m11_sl21_sr21 == 0x5e0): 835 | cmd.itype = self.inames['l.sfeqi'] 836 | cmd[0].type = o_reg 837 | cmd[0].reg = op_m5_sl16_sr16 838 | cmd[0].dtyp = dt_word 839 | cmd[1].type = o_imm 840 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 841 | cmd[1].dtyp = dt_word 842 | elif (op_m11_sl21_sr21 == 0x72b): 843 | cmd.itype = self.inames['l.sfges'] 844 | cmd[0].type = o_reg 845 | cmd[0].reg = op_m5_sl16_sr16 846 | cmd[0].dtyp = dt_word 847 | cmd[1].type = o_reg 848 | cmd[1].reg = op_m5_sl11_sr11 849 | cmd[1].dtyp = dt_word 850 | elif (op_m11_sl21_sr21 == 0x5eb): 851 | cmd.itype = self.inames['l.sfgesi'] 852 | cmd[0].type = o_reg 853 | cmd[0].reg = op_m5_sl16_sr16 854 | cmd[0].dtyp = dt_word 855 | cmd[1].type = o_imm 856 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 857 | cmd[1].dtyp = dt_word 858 | elif (op_m11_sl21_sr21 == 0x723): 859 | cmd.itype = self.inames['l.sfgeu'] 860 | cmd[0].type = o_reg 861 | cmd[0].reg = op_m5_sl16_sr16 862 | cmd[0].dtyp = dt_word 863 | cmd[1].type = o_reg 864 | cmd[1].reg = op_m5_sl11_sr11 865 | cmd[1].dtyp = dt_word 866 | elif (op_m11_sl21_sr21 == 0x5e3): 867 | cmd.itype = self.inames['l.sfgeui'] 868 | cmd[0].type = o_reg 869 | cmd[0].reg = op_m5_sl16_sr16 870 | cmd[0].dtyp = dt_word 871 | cmd[1].type = o_imm 872 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 873 | cmd[1].dtyp = dt_word 874 | elif (op_m11_sl21_sr21 == 0x72a): 875 | cmd.itype = self.inames['l.sfgts'] 876 | cmd[0].type = o_reg 877 | cmd[0].reg = op_m5_sl16_sr16 878 | cmd[0].dtyp = dt_word 879 | cmd[1].type = o_reg 880 | cmd[1].reg = op_m5_sl11_sr11 881 | cmd[1].dtyp = dt_word 882 | elif (op_m11_sl21_sr21 == 0x5ea): 883 | cmd.itype = self.inames['l.sfgtsi'] 884 | cmd[0].type = o_reg 885 | cmd[0].reg = op_m5_sl16_sr16 886 | cmd[0].dtyp = dt_word 887 | cmd[1].type = o_imm 888 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 889 | cmd[1].dtyp = dt_word 890 | elif (op_m11_sl21_sr21 == 0x722): 891 | cmd.itype = self.inames['l.sfgtu'] 892 | cmd[0].type = o_reg 893 | cmd[0].reg = op_m5_sl16_sr16 894 | cmd[0].dtyp = dt_word 895 | cmd[1].type = o_reg 896 | cmd[1].reg = op_m5_sl11_sr11 897 | cmd[1].dtyp = dt_word 898 | elif (op_m11_sl21_sr21 == 0x5e2): 899 | cmd.itype = self.inames['l.sfgtui'] 900 | cmd[0].type = o_reg 901 | cmd[0].reg = op_m5_sl16_sr16 902 | cmd[0].dtyp = dt_word 903 | cmd[1].type = o_imm 904 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 905 | cmd[1].dtyp = dt_word 906 | elif (op_m11_sl21_sr21 == 0x5ed): 907 | cmd.itype = self.inames['l.sflesi'] 908 | cmd[0].type = o_reg 909 | cmd[0].reg = op_m5_sl16_sr16 910 | cmd[0].dtyp = dt_word 911 | cmd[1].type = o_imm 912 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 913 | cmd[1].dtyp = dt_word 914 | elif (op_m11_sl21_sr21 == 0x725): 915 | cmd.itype = self.inames['l.sfleu'] 916 | cmd[0].type = o_reg 917 | cmd[0].reg = op_m5_sl16_sr16 918 | cmd[0].dtyp = dt_word 919 | cmd[1].type = o_reg 920 | cmd[1].reg = op_m5_sl11_sr11 921 | cmd[1].dtyp = dt_word 922 | elif (op_m11_sl21_sr21 == 0x5e5): 923 | cmd.itype = self.inames['l.sfleui'] 924 | cmd[0].type = o_reg 925 | cmd[0].reg = op_m5_sl16_sr16 926 | cmd[0].dtyp = dt_word 927 | cmd[1].type = o_imm 928 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 929 | cmd[1].dtyp = dt_word 930 | elif (op_m11_sl21_sr21 == 0x72c): 931 | cmd.itype = self.inames['l.sflts'] 932 | cmd[0].type = o_reg 933 | cmd[0].reg = op_m5_sl16_sr16 934 | cmd[0].dtyp = dt_word 935 | cmd[1].type = o_reg 936 | cmd[1].reg = op_m5_sl11_sr11 937 | cmd[1].dtyp = dt_word 938 | elif (op_m11_sl21_sr21 == 0x5ec): 939 | cmd.itype = self.inames['l.sfltsi'] 940 | cmd[0].type = o_reg 941 | cmd[0].reg = op_m5_sl16_sr16 942 | cmd[0].dtyp = dt_word 943 | cmd[1].type = o_imm 944 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 945 | cmd[1].dtyp = dt_word 946 | elif (op_m11_sl21_sr21 == 0x724): 947 | cmd.itype = self.inames['l.sfltu'] 948 | cmd[0].type = o_reg 949 | cmd[0].reg = op_m5_sl16_sr16 950 | cmd[0].dtyp = dt_word 951 | cmd[1].type = o_reg 952 | cmd[1].reg = op_m5_sl11_sr11 953 | cmd[1].dtyp = dt_word 954 | elif (op_m11_sl21_sr21 == 0x5e4): 955 | cmd.itype = self.inames['l.sfltui'] 956 | cmd[0].type = o_reg 957 | cmd[0].reg = op_m5_sl16_sr16 958 | cmd[0].dtyp = dt_word 959 | cmd[1].type = o_imm 960 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 961 | cmd[1].dtyp = dt_word 962 | elif (op_m11_sl21_sr21 == 0x721): 963 | cmd.itype = self.inames['l.sfne'] 964 | cmd[0].type = o_reg 965 | cmd[0].reg = op_m5_sl16_sr16 966 | cmd[0].dtyp = dt_word 967 | cmd[1].type = o_reg 968 | cmd[1].reg = op_m5_sl11_sr11 969 | cmd[1].dtyp = dt_word 970 | elif (op_m11_sl21_sr21 == 0x5e1): 971 | cmd.itype = self.inames['l.sfnei'] 972 | cmd[0].type = o_reg 973 | cmd[0].reg = op_m5_sl16_sr16 974 | cmd[0].dtyp = dt_word 975 | cmd[1].type = o_imm 976 | cmd[1].value = SIGNEXT(op_m16_sl0_sr0, 16) 977 | cmd[1].dtyp = dt_word 978 | elif (op_m6_sl26_sr26 == 0x37): 979 | cmd.itype = self.inames['l.sh'] 980 | cmd[0].type = o_reg 981 | cmd[0].reg = op_m5_sl11_sr11 982 | cmd[0].dtyp = dt_word 983 | cmd[1].type = o_displ 984 | cmd[1].addr = SIGNEXT(op_m11_sl0_sr0 | op_m5_sl21_sr10, 16) 985 | cmd[1].reg = op_m5_sl16_sr16 986 | elif (op_m4_sl0_sr0 == 0x8) and (op_m4_sl6_sr6 == 0x0) and (op_m6_sl26_sr26 == 0x38): 987 | cmd.itype = self.inames['l.sll'] 988 | cmd[0].type = o_reg 989 | cmd[0].reg = op_m5_sl21_sr21 990 | cmd[0].dtyp = dt_word 991 | cmd[1].type = o_reg 992 | cmd[1].reg = op_m5_sl16_sr16 993 | cmd[1].dtyp = dt_word 994 | cmd[2].type = o_reg 995 | cmd[2].reg = op_m5_sl11_sr11 996 | cmd[2].dtyp = dt_word 997 | elif (op_m2_sl6_sr6 == 0x0) and (op_m6_sl26_sr26 == 0x2e): 998 | cmd.itype = self.inames['l.slli'] 999 | cmd[0].type = o_reg 1000 | cmd[0].reg = op_m5_sl21_sr21 1001 | cmd[0].dtyp = dt_word 1002 | cmd[1].type = o_reg 1003 | cmd[1].reg = op_m5_sl16_sr16 1004 | cmd[1].dtyp = dt_word 1005 | cmd[2].type = o_imm 1006 | cmd[2].value = op_m6_sl0_sr0 1007 | cmd[2].dtyp = dt_word 1008 | elif (op_m4_sl0_sr0 == 0x8) and (op_m4_sl6_sr6 == 0x2) and (op_m6_sl26_sr26 == 0x38): 1009 | cmd.itype = self.inames['l.sra'] 1010 | cmd[0].type = o_reg 1011 | cmd[0].reg = op_m5_sl21_sr21 1012 | cmd[0].dtyp = dt_word 1013 | cmd[1].type = o_reg 1014 | cmd[1].reg = op_m5_sl16_sr16 1015 | cmd[1].dtyp = dt_word 1016 | cmd[2].type = o_reg 1017 | cmd[2].reg = op_m5_sl11_sr11 1018 | cmd[2].dtyp = dt_word 1019 | elif (op_m2_sl6_sr6 == 0x2) and (op_m6_sl26_sr26 == 0x2e): 1020 | cmd.itype = self.inames['l.srai'] 1021 | cmd[0].type = o_reg 1022 | cmd[0].reg = op_m5_sl21_sr21 1023 | cmd[0].dtyp = dt_word 1024 | cmd[1].type = o_reg 1025 | cmd[1].reg = op_m5_sl16_sr16 1026 | cmd[1].dtyp = dt_word 1027 | cmd[2].type = o_imm 1028 | cmd[2].value = op_m6_sl0_sr0 1029 | cmd[2].dtyp = dt_word 1030 | elif (op_m4_sl0_sr0 == 0x8) and (op_m4_sl6_sr6 == 0x1) and (op_m6_sl26_sr26 == 0x38): 1031 | cmd.itype = self.inames['l.srl'] 1032 | cmd[0].type = o_reg 1033 | cmd[0].reg = op_m5_sl21_sr21 1034 | cmd[0].dtyp = dt_word 1035 | cmd[1].type = o_reg 1036 | cmd[1].reg = op_m5_sl16_sr16 1037 | cmd[1].dtyp = dt_word 1038 | cmd[2].type = o_reg 1039 | cmd[2].reg = op_m5_sl11_sr11 1040 | cmd[2].dtyp = dt_word 1041 | elif (op_m2_sl6_sr6 == 0x1) and (op_m6_sl26_sr26 == 0x2e): 1042 | cmd.itype = self.inames['l.srli'] 1043 | cmd[0].type = o_reg 1044 | cmd[0].reg = op_m5_sl21_sr21 1045 | cmd[0].dtyp = dt_word 1046 | cmd[1].type = o_reg 1047 | cmd[1].reg = op_m5_sl16_sr16 1048 | cmd[1].dtyp = dt_word 1049 | cmd[2].type = o_imm 1050 | cmd[2].value = op_m6_sl0_sr0 1051 | cmd[2].dtyp = dt_word 1052 | elif (op_m4_sl0_sr0 == 0x2) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 1053 | cmd.itype = self.inames['l.sub'] 1054 | cmd[0].type = o_reg 1055 | cmd[0].reg = op_m5_sl21_sr21 1056 | cmd[0].dtyp = dt_word 1057 | cmd[1].type = o_reg 1058 | cmd[1].reg = op_m5_sl16_sr16 1059 | cmd[1].dtyp = dt_word 1060 | cmd[2].type = o_reg 1061 | cmd[2].reg = op_m5_sl11_sr11 1062 | cmd[2].dtyp = dt_word 1063 | elif (op_m6_sl26_sr26 == 0x35): 1064 | cmd.itype = self.inames['l.sw'] 1065 | cmd[0].type = o_displ 1066 | cmd[0].addr = SIGNEXT(op_m11_sl0_sr0 | op_m5_sl21_sr10, 16) 1067 | cmd[0].reg = op_m5_sl16_sr16 1068 | cmd[1].type = o_reg 1069 | cmd[1].reg = op_m5_sl11_sr11 1070 | cmd[1].dtyp = dt_word 1071 | elif (op_m6_sl26_sr26 == 0x33): 1072 | cmd.itype = self.inames['l.swa'] 1073 | cmd[0].type = o_displ 1074 | cmd[0].addr = SIGNEXT(op_m11_sl0_sr0 | op_m5_sl21_sr10, 16) 1075 | cmd[0].reg = op_m5_sl16_sr16 1076 | cmd[1].type = o_reg 1077 | cmd[1].reg = op_m5_sl11_sr11 1078 | cmd[1].dtyp = dt_word 1079 | elif (op_m16_sl16_sr16 == 0x2000): 1080 | cmd.itype = self.inames['l.sys'] 1081 | cmd[0].type = o_imm 1082 | cmd[0].value = op_m16_sl0_sr0 1083 | cmd[0].dtyp = dt_word 1084 | elif (op_m16_sl16_sr16 == 0x2100): 1085 | cmd.itype = self.inames['l.trap'] 1086 | cmd[0].type = o_imm 1087 | cmd[0].value = op_m16_sl0_sr0 1088 | cmd[0].dtyp = dt_word 1089 | elif (op_m4_sl0_sr0 == 0x5) and (op_m2_sl8_sr8 == 0x0) and (op_m6_sl26_sr26 == 0x38): 1090 | cmd.itype = self.inames['l.xor'] 1091 | cmd[0].type = o_reg 1092 | cmd[0].reg = op_m5_sl21_sr21 1093 | cmd[0].dtyp = dt_word 1094 | cmd[1].type = o_reg 1095 | cmd[1].reg = op_m5_sl16_sr16 1096 | cmd[1].dtyp = dt_word 1097 | cmd[2].type = o_reg 1098 | cmd[2].reg = op_m5_sl11_sr11 1099 | cmd[2].dtyp = dt_word 1100 | elif (op_m6_sl26_sr26 == 0x2b): 1101 | cmd.itype = self.inames['l.xori'] 1102 | cmd[0].type = o_reg 1103 | cmd[0].reg = op_m5_sl21_sr21 1104 | cmd[0].dtyp = dt_word 1105 | cmd[1].type = o_reg 1106 | cmd[1].reg = op_m5_sl16_sr16 1107 | cmd[1].dtyp = dt_word 1108 | cmd[2].type = o_imm 1109 | cmd[2].value = SIGNEXT(op_m16_sl0_sr0, 16) 1110 | cmd[2].dtyp = dt_word 1111 | elif (op_m8_sl0_sr0 == 0x10) and (op_m6_sl26_sr26 == 0x32): 1112 | cmd.itype = self.inames['lf.add.d'] 1113 | cmd[0].type = o_reg 1114 | cmd[0].reg = op_m5_sl21_sr21 1115 | cmd[0].dtyp = dt_word 1116 | cmd[1].type = o_reg 1117 | cmd[1].reg = op_m5_sl16_sr16 1118 | cmd[1].dtyp = dt_word 1119 | cmd[2].type = o_reg 1120 | cmd[2].reg = op_m5_sl11_sr11 1121 | cmd[2].dtyp = dt_word 1122 | elif (op_m8_sl0_sr0 == 0x0) and (op_m6_sl26_sr26 == 0x32): 1123 | cmd.itype = self.inames['lf.add.s'] 1124 | cmd[0].type = o_reg 1125 | cmd[0].reg = op_m5_sl21_sr21 1126 | cmd[0].dtyp = dt_word 1127 | cmd[1].type = o_reg 1128 | cmd[1].reg = op_m5_sl16_sr16 1129 | cmd[1].dtyp = dt_word 1130 | cmd[2].type = o_reg 1131 | cmd[2].reg = op_m5_sl11_sr11 1132 | cmd[2].dtyp = dt_word 1133 | elif (op_m4_sl4_sr4 == 0xe) and (op_m6_sl26_sr26 == 0x32): 1134 | cmd.itype = self.inames['lf.cust1.d'] 1135 | cmd[0].type = o_reg 1136 | cmd[0].reg = op_m5_sl16_sr16 1137 | cmd[0].dtyp = dt_word 1138 | cmd[1].type = o_reg 1139 | cmd[1].reg = op_m5_sl11_sr11 1140 | cmd[1].dtyp = dt_word 1141 | elif (op_m4_sl4_sr4 == 0xd) and (op_m6_sl26_sr26 == 0x32): 1142 | cmd.itype = self.inames['lf.cust1.s'] 1143 | cmd[0].type = o_reg 1144 | cmd[0].reg = op_m5_sl16_sr16 1145 | cmd[0].dtyp = dt_word 1146 | cmd[1].type = o_reg 1147 | cmd[1].reg = op_m5_sl11_sr11 1148 | cmd[1].dtyp = dt_word 1149 | elif (op_m8_sl0_sr0 == 0x13) and (op_m6_sl26_sr26 == 0x32): 1150 | cmd.itype = self.inames['lf.div.d'] 1151 | cmd[0].type = o_reg 1152 | cmd[0].reg = op_m5_sl21_sr21 1153 | cmd[0].dtyp = dt_word 1154 | cmd[1].type = o_reg 1155 | cmd[1].reg = op_m5_sl16_sr16 1156 | cmd[1].dtyp = dt_word 1157 | cmd[2].type = o_reg 1158 | cmd[2].reg = op_m5_sl11_sr11 1159 | cmd[2].dtyp = dt_word 1160 | elif (op_m8_sl0_sr0 == 0x3) and (op_m6_sl26_sr26 == 0x32): 1161 | cmd.itype = self.inames['lf.div.s'] 1162 | cmd[0].type = o_reg 1163 | cmd[0].reg = op_m5_sl21_sr21 1164 | cmd[0].dtyp = dt_word 1165 | cmd[1].type = o_reg 1166 | cmd[1].reg = op_m5_sl16_sr16 1167 | cmd[1].dtyp = dt_word 1168 | cmd[2].type = o_reg 1169 | cmd[2].reg = op_m5_sl11_sr11 1170 | cmd[2].dtyp = dt_word 1171 | elif (op_m8_sl0_sr0 == 0x15) and (op_m5_sl11_sr11 == 0x0) and (op_m6_sl26_sr26 == 0x32): 1172 | cmd.itype = self.inames['lf.ftoi.d'] 1173 | cmd[0].type = o_reg 1174 | cmd[0].reg = op_m5_sl21_sr21 1175 | cmd[0].dtyp = dt_word 1176 | cmd[1].type = o_reg 1177 | cmd[1].reg = op_m5_sl16_sr16 1178 | cmd[1].dtyp = dt_word 1179 | elif (op_m8_sl0_sr0 == 0x5) and (op_m5_sl11_sr11 == 0x0) and (op_m6_sl26_sr26 == 0x32): 1180 | cmd.itype = self.inames['lf.ftoi.s'] 1181 | cmd[0].type = o_reg 1182 | cmd[0].reg = op_m5_sl21_sr21 1183 | cmd[0].dtyp = dt_word 1184 | cmd[1].type = o_reg 1185 | cmd[1].reg = op_m5_sl16_sr16 1186 | cmd[1].dtyp = dt_word 1187 | elif (op_m8_sl0_sr0 == 0x14) and (op_m5_sl11_sr11 == 0x0) and (op_m6_sl26_sr26 == 0x32): 1188 | cmd.itype = self.inames['lf.itof.d'] 1189 | cmd[0].type = o_reg 1190 | cmd[0].reg = op_m5_sl21_sr21 1191 | cmd[0].dtyp = dt_word 1192 | cmd[1].type = o_reg 1193 | cmd[1].reg = op_m5_sl16_sr16 1194 | cmd[1].dtyp = dt_word 1195 | elif (op_m8_sl0_sr0 == 0x4) and (op_m5_sl11_sr11 == 0x0) and (op_m6_sl26_sr26 == 0x32): 1196 | cmd.itype = self.inames['lf.itof.s'] 1197 | cmd[0].type = o_reg 1198 | cmd[0].reg = op_m5_sl21_sr21 1199 | cmd[0].dtyp = dt_word 1200 | cmd[1].type = o_reg 1201 | cmd[1].reg = op_m5_sl16_sr16 1202 | cmd[1].dtyp = dt_word 1203 | elif (op_m8_sl0_sr0 == 0x17) and (op_m6_sl26_sr26 == 0x32): 1204 | cmd.itype = self.inames['lf.madd.d'] 1205 | cmd[0].type = o_reg 1206 | cmd[0].reg = op_m5_sl21_sr21 1207 | cmd[0].dtyp = dt_word 1208 | cmd[1].type = o_reg 1209 | cmd[1].reg = op_m5_sl16_sr16 1210 | cmd[1].dtyp = dt_word 1211 | cmd[2].type = o_reg 1212 | cmd[2].reg = op_m5_sl11_sr11 1213 | cmd[2].dtyp = dt_word 1214 | elif (op_m8_sl0_sr0 == 0x7) and (op_m6_sl26_sr26 == 0x32): 1215 | cmd.itype = self.inames['lf.madd.s'] 1216 | cmd[0].type = o_reg 1217 | cmd[0].reg = op_m5_sl21_sr21 1218 | cmd[0].dtyp = dt_word 1219 | cmd[1].type = o_reg 1220 | cmd[1].reg = op_m5_sl16_sr16 1221 | cmd[1].dtyp = dt_word 1222 | cmd[2].type = o_reg 1223 | cmd[2].reg = op_m5_sl11_sr11 1224 | cmd[2].dtyp = dt_word 1225 | elif (op_m8_sl0_sr0 == 0x12) and (op_m6_sl26_sr26 == 0x32): 1226 | cmd.itype = self.inames['lf.mul.d'] 1227 | cmd[0].type = o_reg 1228 | cmd[0].reg = op_m5_sl21_sr21 1229 | cmd[0].dtyp = dt_word 1230 | cmd[1].type = o_reg 1231 | cmd[1].reg = op_m5_sl16_sr16 1232 | cmd[1].dtyp = dt_word 1233 | cmd[2].type = o_reg 1234 | cmd[2].reg = op_m5_sl11_sr11 1235 | cmd[2].dtyp = dt_word 1236 | elif (op_m8_sl0_sr0 == 0x2) and (op_m6_sl26_sr26 == 0x32): 1237 | cmd.itype = self.inames['lf.mul.s'] 1238 | cmd[0].type = o_reg 1239 | cmd[0].reg = op_m5_sl21_sr21 1240 | cmd[0].dtyp = dt_word 1241 | cmd[1].type = o_reg 1242 | cmd[1].reg = op_m5_sl16_sr16 1243 | cmd[1].dtyp = dt_word 1244 | cmd[2].type = o_reg 1245 | cmd[2].reg = op_m5_sl11_sr11 1246 | cmd[2].dtyp = dt_word 1247 | elif (op_m8_sl0_sr0 == 0x16) and (op_m6_sl26_sr26 == 0x32): 1248 | cmd.itype = self.inames['lf.rem.d'] 1249 | cmd[0].type = o_reg 1250 | cmd[0].reg = op_m5_sl21_sr21 1251 | cmd[0].dtyp = dt_word 1252 | cmd[1].type = o_reg 1253 | cmd[1].reg = op_m5_sl16_sr16 1254 | cmd[1].dtyp = dt_word 1255 | cmd[2].type = o_reg 1256 | cmd[2].reg = op_m5_sl11_sr11 1257 | cmd[2].dtyp = dt_word 1258 | elif (op_m8_sl0_sr0 == 0x6) and (op_m6_sl26_sr26 == 0x32): 1259 | cmd.itype = self.inames['lf.rem.s'] 1260 | cmd[0].type = o_reg 1261 | cmd[0].reg = op_m5_sl21_sr21 1262 | cmd[0].dtyp = dt_word 1263 | cmd[1].type = o_reg 1264 | cmd[1].reg = op_m5_sl16_sr16 1265 | cmd[1].dtyp = dt_word 1266 | cmd[2].type = o_reg 1267 | cmd[2].reg = op_m5_sl11_sr11 1268 | cmd[2].dtyp = dt_word 1269 | elif (op_m8_sl0_sr0 == 0x18) and (op_m6_sl26_sr26 == 0x32): 1270 | cmd.itype = self.inames['lf.sfeq.d'] 1271 | cmd[0].type = o_reg 1272 | cmd[0].reg = op_m5_sl16_sr16 1273 | cmd[0].dtyp = dt_word 1274 | cmd[1].type = o_reg 1275 | cmd[1].reg = op_m5_sl11_sr11 1276 | cmd[1].dtyp = dt_word 1277 | elif (op_m8_sl0_sr0 == 0x8) and (op_m6_sl26_sr26 == 0x32): 1278 | cmd.itype = self.inames['lf.sfeq.s'] 1279 | cmd[0].type = o_reg 1280 | cmd[0].reg = op_m5_sl16_sr16 1281 | cmd[0].dtyp = dt_word 1282 | cmd[1].type = o_reg 1283 | cmd[1].reg = op_m5_sl11_sr11 1284 | cmd[1].dtyp = dt_word 1285 | elif (op_m8_sl0_sr0 == 0x1b) and (op_m6_sl26_sr26 == 0x32): 1286 | cmd.itype = self.inames['lf.sfge.d'] 1287 | cmd[0].type = o_reg 1288 | cmd[0].reg = op_m5_sl16_sr16 1289 | cmd[0].dtyp = dt_word 1290 | cmd[1].type = o_reg 1291 | cmd[1].reg = op_m5_sl11_sr11 1292 | cmd[1].dtyp = dt_word 1293 | elif (op_m8_sl0_sr0 == 0xb) and (op_m6_sl26_sr26 == 0x32): 1294 | cmd.itype = self.inames['lf.sfge.s'] 1295 | cmd[0].type = o_reg 1296 | cmd[0].reg = op_m5_sl16_sr16 1297 | cmd[0].dtyp = dt_word 1298 | cmd[1].type = o_reg 1299 | cmd[1].reg = op_m5_sl11_sr11 1300 | cmd[1].dtyp = dt_word 1301 | elif (op_m8_sl0_sr0 == 0x1a) and (op_m6_sl26_sr26 == 0x32): 1302 | cmd.itype = self.inames['lf.sfgt.d'] 1303 | cmd[0].type = o_reg 1304 | cmd[0].reg = op_m5_sl16_sr16 1305 | cmd[0].dtyp = dt_word 1306 | cmd[1].type = o_reg 1307 | cmd[1].reg = op_m5_sl11_sr11 1308 | cmd[1].dtyp = dt_word 1309 | elif (op_m8_sl0_sr0 == 0xa) and (op_m6_sl26_sr26 == 0x32): 1310 | cmd.itype = self.inames['lf.sfgt.s'] 1311 | cmd[0].type = o_reg 1312 | cmd[0].reg = op_m5_sl16_sr16 1313 | cmd[0].dtyp = dt_word 1314 | cmd[1].type = o_reg 1315 | cmd[1].reg = op_m5_sl11_sr11 1316 | cmd[1].dtyp = dt_word 1317 | elif (op_m8_sl0_sr0 == 0x1d) and (op_m6_sl26_sr26 == 0x32): 1318 | cmd.itype = self.inames['lf.sfle.d'] 1319 | cmd[0].type = o_reg 1320 | cmd[0].reg = op_m5_sl16_sr16 1321 | cmd[0].dtyp = dt_word 1322 | cmd[1].type = o_reg 1323 | cmd[1].reg = op_m5_sl11_sr11 1324 | cmd[1].dtyp = dt_word 1325 | elif (op_m8_sl0_sr0 == 0xd) and (op_m6_sl26_sr26 == 0x32): 1326 | cmd.itype = self.inames['lf.sfle.s'] 1327 | cmd[0].type = o_reg 1328 | cmd[0].reg = op_m5_sl16_sr16 1329 | cmd[0].dtyp = dt_word 1330 | cmd[1].type = o_reg 1331 | cmd[1].reg = op_m5_sl11_sr11 1332 | cmd[1].dtyp = dt_word 1333 | elif (op_m8_sl0_sr0 == 0x1c) and (op_m6_sl26_sr26 == 0x32): 1334 | cmd.itype = self.inames['lf.sflt.d'] 1335 | cmd[0].type = o_reg 1336 | cmd[0].reg = op_m5_sl16_sr16 1337 | cmd[0].dtyp = dt_word 1338 | cmd[1].type = o_reg 1339 | cmd[1].reg = op_m5_sl11_sr11 1340 | cmd[1].dtyp = dt_word 1341 | elif (op_m8_sl0_sr0 == 0xc) and (op_m6_sl26_sr26 == 0x32): 1342 | cmd.itype = self.inames['lf.sflt.s'] 1343 | cmd[0].type = o_reg 1344 | cmd[0].reg = op_m5_sl16_sr16 1345 | cmd[0].dtyp = dt_word 1346 | cmd[1].type = o_reg 1347 | cmd[1].reg = op_m5_sl11_sr11 1348 | cmd[1].dtyp = dt_word 1349 | elif (op_m8_sl0_sr0 == 0x19) and (op_m6_sl26_sr26 == 0x32): 1350 | cmd.itype = self.inames['lf.sfne.d'] 1351 | cmd[0].type = o_reg 1352 | cmd[0].reg = op_m5_sl16_sr16 1353 | cmd[0].dtyp = dt_word 1354 | cmd[1].type = o_reg 1355 | cmd[1].reg = op_m5_sl11_sr11 1356 | cmd[1].dtyp = dt_word 1357 | elif (op_m8_sl0_sr0 == 0x9) and (op_m6_sl26_sr26 == 0x32): 1358 | cmd.itype = self.inames['lf.sfne.s'] 1359 | cmd[0].type = o_reg 1360 | cmd[0].reg = op_m5_sl16_sr16 1361 | cmd[0].dtyp = dt_word 1362 | cmd[1].type = o_reg 1363 | cmd[1].reg = op_m5_sl11_sr11 1364 | cmd[1].dtyp = dt_word 1365 | elif (op_m8_sl0_sr0 == 0x11) and (op_m6_sl26_sr26 == 0x32): 1366 | cmd.itype = self.inames['lf.sub.d'] 1367 | cmd[0].type = o_reg 1368 | cmd[0].reg = op_m5_sl21_sr21 1369 | cmd[0].dtyp = dt_word 1370 | cmd[1].type = o_reg 1371 | cmd[1].reg = op_m5_sl16_sr16 1372 | cmd[1].dtyp = dt_word 1373 | cmd[2].type = o_reg 1374 | cmd[2].reg = op_m5_sl11_sr11 1375 | cmd[2].dtyp = dt_word 1376 | elif (op_m8_sl0_sr0 == 0x1) and (op_m6_sl26_sr26 == 0x32): 1377 | cmd.itype = self.inames['lf.sub.s'] 1378 | cmd[0].type = o_reg 1379 | cmd[0].reg = op_m5_sl21_sr21 1380 | cmd[0].dtyp = dt_word 1381 | cmd[1].type = o_reg 1382 | cmd[1].reg = op_m5_sl16_sr16 1383 | cmd[1].dtyp = dt_word 1384 | cmd[2].type = o_reg 1385 | cmd[2].reg = op_m5_sl11_sr11 1386 | cmd[2].dtyp = dt_word 1387 | elif (op_m8_sl0_sr0 == 0x30) and (op_m6_sl26_sr26 == 0xa): 1388 | cmd.itype = self.inames['lv.add.b'] 1389 | cmd[0].type = o_reg 1390 | cmd[0].reg = op_m5_sl21_sr21 1391 | cmd[0].dtyp = dt_word 1392 | cmd[1].type = o_reg 1393 | cmd[1].reg = op_m5_sl16_sr16 1394 | cmd[1].dtyp = dt_word 1395 | cmd[2].type = o_reg 1396 | cmd[2].reg = op_m5_sl11_sr11 1397 | cmd[2].dtyp = dt_word 1398 | elif (op_m8_sl0_sr0 == 0x31) and (op_m6_sl26_sr26 == 0xa): 1399 | cmd.itype = self.inames['lv.add.h'] 1400 | cmd[0].type = o_reg 1401 | cmd[0].reg = op_m5_sl21_sr21 1402 | cmd[0].dtyp = dt_word 1403 | cmd[1].type = o_reg 1404 | cmd[1].reg = op_m5_sl16_sr16 1405 | cmd[1].dtyp = dt_word 1406 | cmd[2].type = o_reg 1407 | cmd[2].reg = op_m5_sl11_sr11 1408 | cmd[2].dtyp = dt_word 1409 | elif (op_m8_sl0_sr0 == 0x32) and (op_m6_sl26_sr26 == 0xa): 1410 | cmd.itype = self.inames['lv.adds.b'] 1411 | cmd[0].type = o_reg 1412 | cmd[0].reg = op_m5_sl21_sr21 1413 | cmd[0].dtyp = dt_word 1414 | cmd[1].type = o_reg 1415 | cmd[1].reg = op_m5_sl16_sr16 1416 | cmd[1].dtyp = dt_word 1417 | cmd[2].type = o_reg 1418 | cmd[2].reg = op_m5_sl11_sr11 1419 | cmd[2].dtyp = dt_word 1420 | elif (op_m8_sl0_sr0 == 0x33) and (op_m6_sl26_sr26 == 0xa): 1421 | cmd.itype = self.inames['lv.adds.h'] 1422 | cmd[0].type = o_reg 1423 | cmd[0].reg = op_m5_sl21_sr21 1424 | cmd[0].dtyp = dt_word 1425 | cmd[1].type = o_reg 1426 | cmd[1].reg = op_m5_sl16_sr16 1427 | cmd[1].dtyp = dt_word 1428 | cmd[2].type = o_reg 1429 | cmd[2].reg = op_m5_sl11_sr11 1430 | cmd[2].dtyp = dt_word 1431 | elif (op_m8_sl0_sr0 == 0x34) and (op_m6_sl26_sr26 == 0xa): 1432 | cmd.itype = self.inames['lv.addu.b'] 1433 | cmd[0].type = o_reg 1434 | cmd[0].reg = op_m5_sl21_sr21 1435 | cmd[0].dtyp = dt_word 1436 | cmd[1].type = o_reg 1437 | cmd[1].reg = op_m5_sl16_sr16 1438 | cmd[1].dtyp = dt_word 1439 | cmd[2].type = o_reg 1440 | cmd[2].reg = op_m5_sl11_sr11 1441 | cmd[2].dtyp = dt_word 1442 | elif (op_m8_sl0_sr0 == 0x35) and (op_m6_sl26_sr26 == 0xa): 1443 | cmd.itype = self.inames['lv.addu.h'] 1444 | cmd[0].type = o_reg 1445 | cmd[0].reg = op_m5_sl21_sr21 1446 | cmd[0].dtyp = dt_word 1447 | cmd[1].type = o_reg 1448 | cmd[1].reg = op_m5_sl16_sr16 1449 | cmd[1].dtyp = dt_word 1450 | cmd[2].type = o_reg 1451 | cmd[2].reg = op_m5_sl11_sr11 1452 | cmd[2].dtyp = dt_word 1453 | elif (op_m8_sl0_sr0 == 0x36) and (op_m6_sl26_sr26 == 0xa): 1454 | cmd.itype = self.inames['lv.addus.b'] 1455 | cmd[0].type = o_reg 1456 | cmd[0].reg = op_m5_sl21_sr21 1457 | cmd[0].dtyp = dt_word 1458 | cmd[1].type = o_reg 1459 | cmd[1].reg = op_m5_sl16_sr16 1460 | cmd[1].dtyp = dt_word 1461 | cmd[2].type = o_reg 1462 | cmd[2].reg = op_m5_sl11_sr11 1463 | cmd[2].dtyp = dt_word 1464 | elif (op_m8_sl0_sr0 == 0x37) and (op_m6_sl26_sr26 == 0xa): 1465 | cmd.itype = self.inames['lv.addus.h'] 1466 | cmd[0].type = o_reg 1467 | cmd[0].reg = op_m5_sl21_sr21 1468 | cmd[0].dtyp = dt_word 1469 | cmd[1].type = o_reg 1470 | cmd[1].reg = op_m5_sl16_sr16 1471 | cmd[1].dtyp = dt_word 1472 | cmd[2].type = o_reg 1473 | cmd[2].reg = op_m5_sl11_sr11 1474 | cmd[2].dtyp = dt_word 1475 | elif (op_m8_sl0_sr0 == 0x10) and (op_m6_sl26_sr26 == 0xa): 1476 | cmd.itype = self.inames['lv.all_eq.b'] 1477 | cmd[0].type = o_reg 1478 | cmd[0].reg = op_m5_sl21_sr21 1479 | cmd[0].dtyp = dt_word 1480 | cmd[1].type = o_reg 1481 | cmd[1].reg = op_m5_sl16_sr16 1482 | cmd[1].dtyp = dt_word 1483 | cmd[2].type = o_reg 1484 | cmd[2].reg = op_m5_sl11_sr11 1485 | cmd[2].dtyp = dt_word 1486 | elif (op_m8_sl0_sr0 == 0x11) and (op_m6_sl26_sr26 == 0xa): 1487 | cmd.itype = self.inames['lv.all_eq.h'] 1488 | cmd[0].type = o_reg 1489 | cmd[0].reg = op_m5_sl21_sr21 1490 | cmd[0].dtyp = dt_word 1491 | cmd[1].type = o_reg 1492 | cmd[1].reg = op_m5_sl16_sr16 1493 | cmd[1].dtyp = dt_word 1494 | cmd[2].type = o_reg 1495 | cmd[2].reg = op_m5_sl11_sr11 1496 | cmd[2].dtyp = dt_word 1497 | elif (op_m8_sl0_sr0 == 0x12) and (op_m6_sl26_sr26 == 0xa): 1498 | cmd.itype = self.inames['lv.all_ge.b'] 1499 | cmd[0].type = o_reg 1500 | cmd[0].reg = op_m5_sl21_sr21 1501 | cmd[0].dtyp = dt_word 1502 | cmd[1].type = o_reg 1503 | cmd[1].reg = op_m5_sl16_sr16 1504 | cmd[1].dtyp = dt_word 1505 | cmd[2].type = o_reg 1506 | cmd[2].reg = op_m5_sl11_sr11 1507 | cmd[2].dtyp = dt_word 1508 | elif (op_m8_sl0_sr0 == 0x13) and (op_m6_sl26_sr26 == 0xa): 1509 | cmd.itype = self.inames['lv.all_ge.h'] 1510 | cmd[0].type = o_reg 1511 | cmd[0].reg = op_m5_sl21_sr21 1512 | cmd[0].dtyp = dt_word 1513 | cmd[1].type = o_reg 1514 | cmd[1].reg = op_m5_sl16_sr16 1515 | cmd[1].dtyp = dt_word 1516 | cmd[2].type = o_reg 1517 | cmd[2].reg = op_m5_sl11_sr11 1518 | cmd[2].dtyp = dt_word 1519 | elif (op_m8_sl0_sr0 == 0x14) and (op_m6_sl26_sr26 == 0xa): 1520 | cmd.itype = self.inames['lv.all_gt.b'] 1521 | cmd[0].type = o_reg 1522 | cmd[0].reg = op_m5_sl21_sr21 1523 | cmd[0].dtyp = dt_word 1524 | cmd[1].type = o_reg 1525 | cmd[1].reg = op_m5_sl16_sr16 1526 | cmd[1].dtyp = dt_word 1527 | cmd[2].type = o_reg 1528 | cmd[2].reg = op_m5_sl11_sr11 1529 | cmd[2].dtyp = dt_word 1530 | elif (op_m8_sl0_sr0 == 0x15) and (op_m6_sl26_sr26 == 0xa): 1531 | cmd.itype = self.inames['lv.all_gt.h'] 1532 | cmd[0].type = o_reg 1533 | cmd[0].reg = op_m5_sl21_sr21 1534 | cmd[0].dtyp = dt_word 1535 | cmd[1].type = o_reg 1536 | cmd[1].reg = op_m5_sl16_sr16 1537 | cmd[1].dtyp = dt_word 1538 | cmd[2].type = o_reg 1539 | cmd[2].reg = op_m5_sl11_sr11 1540 | cmd[2].dtyp = dt_word 1541 | elif (op_m8_sl0_sr0 == 0x16) and (op_m6_sl26_sr26 == 0xa): 1542 | cmd.itype = self.inames['lv.all_le.b'] 1543 | cmd[0].type = o_reg 1544 | cmd[0].reg = op_m5_sl21_sr21 1545 | cmd[0].dtyp = dt_word 1546 | cmd[1].type = o_reg 1547 | cmd[1].reg = op_m5_sl16_sr16 1548 | cmd[1].dtyp = dt_word 1549 | cmd[2].type = o_reg 1550 | cmd[2].reg = op_m5_sl11_sr11 1551 | cmd[2].dtyp = dt_word 1552 | elif (op_m8_sl0_sr0 == 0x17) and (op_m6_sl26_sr26 == 0xa): 1553 | cmd.itype = self.inames['lv.all_le.h'] 1554 | cmd[0].type = o_reg 1555 | cmd[0].reg = op_m5_sl21_sr21 1556 | cmd[0].dtyp = dt_word 1557 | cmd[1].type = o_reg 1558 | cmd[1].reg = op_m5_sl16_sr16 1559 | cmd[1].dtyp = dt_word 1560 | cmd[2].type = o_reg 1561 | cmd[2].reg = op_m5_sl11_sr11 1562 | cmd[2].dtyp = dt_word 1563 | elif (op_m8_sl0_sr0 == 0x18) and (op_m6_sl26_sr26 == 0xa): 1564 | cmd.itype = self.inames['lv.all_lt.b'] 1565 | cmd[0].type = o_reg 1566 | cmd[0].reg = op_m5_sl21_sr21 1567 | cmd[0].dtyp = dt_word 1568 | cmd[1].type = o_reg 1569 | cmd[1].reg = op_m5_sl16_sr16 1570 | cmd[1].dtyp = dt_word 1571 | cmd[2].type = o_reg 1572 | cmd[2].reg = op_m5_sl11_sr11 1573 | cmd[2].dtyp = dt_word 1574 | elif (op_m8_sl0_sr0 == 0x19) and (op_m6_sl26_sr26 == 0xa): 1575 | cmd.itype = self.inames['lv.all_lt.h'] 1576 | cmd[0].type = o_reg 1577 | cmd[0].reg = op_m5_sl21_sr21 1578 | cmd[0].dtyp = dt_word 1579 | cmd[1].type = o_reg 1580 | cmd[1].reg = op_m5_sl16_sr16 1581 | cmd[1].dtyp = dt_word 1582 | cmd[2].type = o_reg 1583 | cmd[2].reg = op_m5_sl11_sr11 1584 | cmd[2].dtyp = dt_word 1585 | elif (op_m8_sl0_sr0 == 0x1a) and (op_m6_sl26_sr26 == 0xa): 1586 | cmd.itype = self.inames['lv.all_ne.b'] 1587 | cmd[0].type = o_reg 1588 | cmd[0].reg = op_m5_sl21_sr21 1589 | cmd[0].dtyp = dt_word 1590 | cmd[1].type = o_reg 1591 | cmd[1].reg = op_m5_sl16_sr16 1592 | cmd[1].dtyp = dt_word 1593 | cmd[2].type = o_reg 1594 | cmd[2].reg = op_m5_sl11_sr11 1595 | cmd[2].dtyp = dt_word 1596 | elif (op_m8_sl0_sr0 == 0x1b) and (op_m6_sl26_sr26 == 0xa): 1597 | cmd.itype = self.inames['lv.all_ne.h'] 1598 | cmd[0].type = o_reg 1599 | cmd[0].reg = op_m5_sl21_sr21 1600 | cmd[0].dtyp = dt_word 1601 | cmd[1].type = o_reg 1602 | cmd[1].reg = op_m5_sl16_sr16 1603 | cmd[1].dtyp = dt_word 1604 | cmd[2].type = o_reg 1605 | cmd[2].reg = op_m5_sl11_sr11 1606 | cmd[2].dtyp = dt_word 1607 | elif (op_m8_sl0_sr0 == 0x38) and (op_m6_sl26_sr26 == 0xa): 1608 | cmd.itype = self.inames['lv.and'] 1609 | cmd[0].type = o_reg 1610 | cmd[0].reg = op_m5_sl21_sr21 1611 | cmd[0].dtyp = dt_word 1612 | cmd[1].type = o_reg 1613 | cmd[1].reg = op_m5_sl16_sr16 1614 | cmd[1].dtyp = dt_word 1615 | cmd[2].type = o_reg 1616 | cmd[2].reg = op_m5_sl11_sr11 1617 | cmd[2].dtyp = dt_word 1618 | elif (op_m8_sl0_sr0 == 0x20) and (op_m6_sl26_sr26 == 0xa): 1619 | cmd.itype = self.inames['lv.any_eq.b'] 1620 | cmd[0].type = o_reg 1621 | cmd[0].reg = op_m5_sl21_sr21 1622 | cmd[0].dtyp = dt_word 1623 | cmd[1].type = o_reg 1624 | cmd[1].reg = op_m5_sl16_sr16 1625 | cmd[1].dtyp = dt_word 1626 | cmd[2].type = o_reg 1627 | cmd[2].reg = op_m5_sl11_sr11 1628 | cmd[2].dtyp = dt_word 1629 | elif (op_m8_sl0_sr0 == 0x21) and (op_m6_sl26_sr26 == 0xa): 1630 | cmd.itype = self.inames['lv.any_eq.h'] 1631 | cmd[0].type = o_reg 1632 | cmd[0].reg = op_m5_sl21_sr21 1633 | cmd[0].dtyp = dt_word 1634 | cmd[1].type = o_reg 1635 | cmd[1].reg = op_m5_sl16_sr16 1636 | cmd[1].dtyp = dt_word 1637 | cmd[2].type = o_reg 1638 | cmd[2].reg = op_m5_sl11_sr11 1639 | cmd[2].dtyp = dt_word 1640 | elif (op_m8_sl0_sr0 == 0x22) and (op_m6_sl26_sr26 == 0xa): 1641 | cmd.itype = self.inames['lv.any_ge.b'] 1642 | cmd[0].type = o_reg 1643 | cmd[0].reg = op_m5_sl21_sr21 1644 | cmd[0].dtyp = dt_word 1645 | cmd[1].type = o_reg 1646 | cmd[1].reg = op_m5_sl16_sr16 1647 | cmd[1].dtyp = dt_word 1648 | cmd[2].type = o_reg 1649 | cmd[2].reg = op_m5_sl11_sr11 1650 | cmd[2].dtyp = dt_word 1651 | elif (op_m8_sl0_sr0 == 0x23) and (op_m6_sl26_sr26 == 0xa): 1652 | cmd.itype = self.inames['lv.any_ge.h'] 1653 | cmd[0].type = o_reg 1654 | cmd[0].reg = op_m5_sl21_sr21 1655 | cmd[0].dtyp = dt_word 1656 | cmd[1].type = o_reg 1657 | cmd[1].reg = op_m5_sl16_sr16 1658 | cmd[1].dtyp = dt_word 1659 | cmd[2].type = o_reg 1660 | cmd[2].reg = op_m5_sl11_sr11 1661 | cmd[2].dtyp = dt_word 1662 | elif (op_m8_sl0_sr0 == 0x24) and (op_m6_sl26_sr26 == 0xa): 1663 | cmd.itype = self.inames['lv.any_gt.b'] 1664 | cmd[0].type = o_reg 1665 | cmd[0].reg = op_m5_sl21_sr21 1666 | cmd[0].dtyp = dt_word 1667 | cmd[1].type = o_reg 1668 | cmd[1].reg = op_m5_sl16_sr16 1669 | cmd[1].dtyp = dt_word 1670 | cmd[2].type = o_reg 1671 | cmd[2].reg = op_m5_sl11_sr11 1672 | cmd[2].dtyp = dt_word 1673 | elif (op_m8_sl0_sr0 == 0x25) and (op_m6_sl26_sr26 == 0xa): 1674 | cmd.itype = self.inames['lv.any_gt.h'] 1675 | cmd[0].type = o_reg 1676 | cmd[0].reg = op_m5_sl21_sr21 1677 | cmd[0].dtyp = dt_word 1678 | cmd[1].type = o_reg 1679 | cmd[1].reg = op_m5_sl16_sr16 1680 | cmd[1].dtyp = dt_word 1681 | cmd[2].type = o_reg 1682 | cmd[2].reg = op_m5_sl11_sr11 1683 | cmd[2].dtyp = dt_word 1684 | elif (op_m8_sl0_sr0 == 0x26) and (op_m6_sl26_sr26 == 0xa): 1685 | cmd.itype = self.inames['lv.any_le.b'] 1686 | cmd[0].type = o_reg 1687 | cmd[0].reg = op_m5_sl21_sr21 1688 | cmd[0].dtyp = dt_word 1689 | cmd[1].type = o_reg 1690 | cmd[1].reg = op_m5_sl16_sr16 1691 | cmd[1].dtyp = dt_word 1692 | cmd[2].type = o_reg 1693 | cmd[2].reg = op_m5_sl11_sr11 1694 | cmd[2].dtyp = dt_word 1695 | elif (op_m8_sl0_sr0 == 0x27) and (op_m6_sl26_sr26 == 0xa): 1696 | cmd.itype = self.inames['lv.any_le.h'] 1697 | cmd[0].type = o_reg 1698 | cmd[0].reg = op_m5_sl21_sr21 1699 | cmd[0].dtyp = dt_word 1700 | cmd[1].type = o_reg 1701 | cmd[1].reg = op_m5_sl16_sr16 1702 | cmd[1].dtyp = dt_word 1703 | cmd[2].type = o_reg 1704 | cmd[2].reg = op_m5_sl11_sr11 1705 | cmd[2].dtyp = dt_word 1706 | elif (op_m8_sl0_sr0 == 0x28) and (op_m6_sl26_sr26 == 0xa): 1707 | cmd.itype = self.inames['lv.any_lt.b'] 1708 | cmd[0].type = o_reg 1709 | cmd[0].reg = op_m5_sl21_sr21 1710 | cmd[0].dtyp = dt_word 1711 | cmd[1].type = o_reg 1712 | cmd[1].reg = op_m5_sl16_sr16 1713 | cmd[1].dtyp = dt_word 1714 | cmd[2].type = o_reg 1715 | cmd[2].reg = op_m5_sl11_sr11 1716 | cmd[2].dtyp = dt_word 1717 | elif (op_m8_sl0_sr0 == 0x29) and (op_m6_sl26_sr26 == 0xa): 1718 | cmd.itype = self.inames['lv.any_lt.h'] 1719 | cmd[0].type = o_reg 1720 | cmd[0].reg = op_m5_sl21_sr21 1721 | cmd[0].dtyp = dt_word 1722 | cmd[1].type = o_reg 1723 | cmd[1].reg = op_m5_sl16_sr16 1724 | cmd[1].dtyp = dt_word 1725 | cmd[2].type = o_reg 1726 | cmd[2].reg = op_m5_sl11_sr11 1727 | cmd[2].dtyp = dt_word 1728 | elif (op_m8_sl0_sr0 == 0x2a) and (op_m6_sl26_sr26 == 0xa): 1729 | cmd.itype = self.inames['lv.any_ne.b'] 1730 | cmd[0].type = o_reg 1731 | cmd[0].reg = op_m5_sl21_sr21 1732 | cmd[0].dtyp = dt_word 1733 | cmd[1].type = o_reg 1734 | cmd[1].reg = op_m5_sl16_sr16 1735 | cmd[1].dtyp = dt_word 1736 | cmd[2].type = o_reg 1737 | cmd[2].reg = op_m5_sl11_sr11 1738 | cmd[2].dtyp = dt_word 1739 | elif (op_m8_sl0_sr0 == 0x2b) and (op_m6_sl26_sr26 == 0xa): 1740 | cmd.itype = self.inames['lv.any_ne.h'] 1741 | cmd[0].type = o_reg 1742 | cmd[0].reg = op_m5_sl21_sr21 1743 | cmd[0].dtyp = dt_word 1744 | cmd[1].type = o_reg 1745 | cmd[1].reg = op_m5_sl16_sr16 1746 | cmd[1].dtyp = dt_word 1747 | cmd[2].type = o_reg 1748 | cmd[2].reg = op_m5_sl11_sr11 1749 | cmd[2].dtyp = dt_word 1750 | elif (op_m8_sl0_sr0 == 0x39) and (op_m6_sl26_sr26 == 0xa): 1751 | cmd.itype = self.inames['lv.avg.b'] 1752 | cmd[0].type = o_reg 1753 | cmd[0].reg = op_m5_sl21_sr21 1754 | cmd[0].dtyp = dt_word 1755 | cmd[1].type = o_reg 1756 | cmd[1].reg = op_m5_sl16_sr16 1757 | cmd[1].dtyp = dt_word 1758 | cmd[2].type = o_reg 1759 | cmd[2].reg = op_m5_sl11_sr11 1760 | cmd[2].dtyp = dt_word 1761 | elif (op_m8_sl0_sr0 == 0x3a) and (op_m6_sl26_sr26 == 0xa): 1762 | cmd.itype = self.inames['lv.avg.h'] 1763 | cmd[0].type = o_reg 1764 | cmd[0].reg = op_m5_sl21_sr21 1765 | cmd[0].dtyp = dt_word 1766 | cmd[1].type = o_reg 1767 | cmd[1].reg = op_m5_sl16_sr16 1768 | cmd[1].dtyp = dt_word 1769 | cmd[2].type = o_reg 1770 | cmd[2].reg = op_m5_sl11_sr11 1771 | cmd[2].dtyp = dt_word 1772 | elif (op_m8_sl0_sr0 == 0x40) and (op_m6_sl26_sr26 == 0xa): 1773 | cmd.itype = self.inames['lv.cmp_eq.b'] 1774 | cmd[0].type = o_reg 1775 | cmd[0].reg = op_m5_sl21_sr21 1776 | cmd[0].dtyp = dt_word 1777 | cmd[1].type = o_reg 1778 | cmd[1].reg = op_m5_sl16_sr16 1779 | cmd[1].dtyp = dt_word 1780 | cmd[2].type = o_reg 1781 | cmd[2].reg = op_m5_sl11_sr11 1782 | cmd[2].dtyp = dt_word 1783 | elif (op_m8_sl0_sr0 == 0x41) and (op_m6_sl26_sr26 == 0xa): 1784 | cmd.itype = self.inames['lv.cmp_eq.h'] 1785 | cmd[0].type = o_reg 1786 | cmd[0].reg = op_m5_sl21_sr21 1787 | cmd[0].dtyp = dt_word 1788 | cmd[1].type = o_reg 1789 | cmd[1].reg = op_m5_sl16_sr16 1790 | cmd[1].dtyp = dt_word 1791 | cmd[2].type = o_reg 1792 | cmd[2].reg = op_m5_sl11_sr11 1793 | cmd[2].dtyp = dt_word 1794 | elif (op_m8_sl0_sr0 == 0x42) and (op_m6_sl26_sr26 == 0xa): 1795 | cmd.itype = self.inames['lv.cmp_ge.b'] 1796 | cmd[0].type = o_reg 1797 | cmd[0].reg = op_m5_sl21_sr21 1798 | cmd[0].dtyp = dt_word 1799 | cmd[1].type = o_reg 1800 | cmd[1].reg = op_m5_sl16_sr16 1801 | cmd[1].dtyp = dt_word 1802 | cmd[2].type = o_reg 1803 | cmd[2].reg = op_m5_sl11_sr11 1804 | cmd[2].dtyp = dt_word 1805 | elif (op_m8_sl0_sr0 == 0x43) and (op_m6_sl26_sr26 == 0xa): 1806 | cmd.itype = self.inames['lv.cmp_ge.h'] 1807 | cmd[0].type = o_reg 1808 | cmd[0].reg = op_m5_sl21_sr21 1809 | cmd[0].dtyp = dt_word 1810 | cmd[1].type = o_reg 1811 | cmd[1].reg = op_m5_sl16_sr16 1812 | cmd[1].dtyp = dt_word 1813 | cmd[2].type = o_reg 1814 | cmd[2].reg = op_m5_sl11_sr11 1815 | cmd[2].dtyp = dt_word 1816 | elif (op_m8_sl0_sr0 == 0x44) and (op_m6_sl26_sr26 == 0xa): 1817 | cmd.itype = self.inames['lv.cmp_gt.b'] 1818 | cmd[0].type = o_reg 1819 | cmd[0].reg = op_m5_sl21_sr21 1820 | cmd[0].dtyp = dt_word 1821 | cmd[1].type = o_reg 1822 | cmd[1].reg = op_m5_sl16_sr16 1823 | cmd[1].dtyp = dt_word 1824 | cmd[2].type = o_reg 1825 | cmd[2].reg = op_m5_sl11_sr11 1826 | cmd[2].dtyp = dt_word 1827 | elif (op_m8_sl0_sr0 == 0x45) and (op_m6_sl26_sr26 == 0xa): 1828 | cmd.itype = self.inames['lv.cmp_gt.h'] 1829 | cmd[0].type = o_reg 1830 | cmd[0].reg = op_m5_sl21_sr21 1831 | cmd[0].dtyp = dt_word 1832 | cmd[1].type = o_reg 1833 | cmd[1].reg = op_m5_sl16_sr16 1834 | cmd[1].dtyp = dt_word 1835 | cmd[2].type = o_reg 1836 | cmd[2].reg = op_m5_sl11_sr11 1837 | cmd[2].dtyp = dt_word 1838 | elif (op_m8_sl0_sr0 == 0x46) and (op_m6_sl26_sr26 == 0xa): 1839 | cmd.itype = self.inames['lv.cmp_le.b'] 1840 | cmd[0].type = o_reg 1841 | cmd[0].reg = op_m5_sl21_sr21 1842 | cmd[0].dtyp = dt_word 1843 | cmd[1].type = o_reg 1844 | cmd[1].reg = op_m5_sl16_sr16 1845 | cmd[1].dtyp = dt_word 1846 | cmd[2].type = o_reg 1847 | cmd[2].reg = op_m5_sl11_sr11 1848 | cmd[2].dtyp = dt_word 1849 | elif (op_m8_sl0_sr0 == 0x47) and (op_m6_sl26_sr26 == 0xa): 1850 | cmd.itype = self.inames['lv.cmp_le.h'] 1851 | cmd[0].type = o_reg 1852 | cmd[0].reg = op_m5_sl21_sr21 1853 | cmd[0].dtyp = dt_word 1854 | cmd[1].type = o_reg 1855 | cmd[1].reg = op_m5_sl16_sr16 1856 | cmd[1].dtyp = dt_word 1857 | cmd[2].type = o_reg 1858 | cmd[2].reg = op_m5_sl11_sr11 1859 | cmd[2].dtyp = dt_word 1860 | elif (op_m8_sl0_sr0 == 0x48) and (op_m6_sl26_sr26 == 0xa): 1861 | cmd.itype = self.inames['lv.cmp_lt.b'] 1862 | cmd[0].type = o_reg 1863 | cmd[0].reg = op_m5_sl21_sr21 1864 | cmd[0].dtyp = dt_word 1865 | cmd[1].type = o_reg 1866 | cmd[1].reg = op_m5_sl16_sr16 1867 | cmd[1].dtyp = dt_word 1868 | cmd[2].type = o_reg 1869 | cmd[2].reg = op_m5_sl11_sr11 1870 | cmd[2].dtyp = dt_word 1871 | elif (op_m8_sl0_sr0 == 0x49) and (op_m6_sl26_sr26 == 0xa): 1872 | cmd.itype = self.inames['lv.cmp_lt.h'] 1873 | cmd[0].type = o_reg 1874 | cmd[0].reg = op_m5_sl21_sr21 1875 | cmd[0].dtyp = dt_word 1876 | cmd[1].type = o_reg 1877 | cmd[1].reg = op_m5_sl16_sr16 1878 | cmd[1].dtyp = dt_word 1879 | cmd[2].type = o_reg 1880 | cmd[2].reg = op_m5_sl11_sr11 1881 | cmd[2].dtyp = dt_word 1882 | elif (op_m8_sl0_sr0 == 0x4a) and (op_m6_sl26_sr26 == 0xa): 1883 | cmd.itype = self.inames['lv.cmp_ne.b'] 1884 | cmd[0].type = o_reg 1885 | cmd[0].reg = op_m5_sl21_sr21 1886 | cmd[0].dtyp = dt_word 1887 | cmd[1].type = o_reg 1888 | cmd[1].reg = op_m5_sl16_sr16 1889 | cmd[1].dtyp = dt_word 1890 | cmd[2].type = o_reg 1891 | cmd[2].reg = op_m5_sl11_sr11 1892 | cmd[2].dtyp = dt_word 1893 | elif (op_m8_sl0_sr0 == 0x4b) and (op_m6_sl26_sr26 == 0xa): 1894 | cmd.itype = self.inames['lv.cmp_ne.h'] 1895 | cmd[0].type = o_reg 1896 | cmd[0].reg = op_m5_sl21_sr21 1897 | cmd[0].dtyp = dt_word 1898 | cmd[1].type = o_reg 1899 | cmd[1].reg = op_m5_sl16_sr16 1900 | cmd[1].dtyp = dt_word 1901 | cmd[2].type = o_reg 1902 | cmd[2].reg = op_m5_sl11_sr11 1903 | cmd[2].dtyp = dt_word 1904 | elif (op_m4_sl4_sr4 == 0xc) and (op_m6_sl26_sr26 == 0xa): 1905 | cmd.itype = self.inames['lv.cust'] 1906 | elif (op_m4_sl4_sr4 == 0xd) and (op_m6_sl26_sr26 == 0xa): 1907 | cmd.itype = self.inames['lv.cust'] 1908 | elif (op_m4_sl4_sr4 == 0xe) and (op_m6_sl26_sr26 == 0xa): 1909 | cmd.itype = self.inames['lv.cust'] 1910 | elif (op_m4_sl4_sr4 == 0xf) and (op_m6_sl26_sr26 == 0xa): 1911 | cmd.itype = self.inames['lv.cust'] 1912 | elif (op_m8_sl0_sr0 == 0x54) and (op_m6_sl26_sr26 == 0xa): 1913 | cmd.itype = self.inames['lv.madds.h'] 1914 | cmd[0].type = o_reg 1915 | cmd[0].reg = op_m5_sl21_sr21 1916 | cmd[0].dtyp = dt_word 1917 | cmd[1].type = o_reg 1918 | cmd[1].reg = op_m5_sl16_sr16 1919 | cmd[1].dtyp = dt_word 1920 | cmd[2].type = o_reg 1921 | cmd[2].reg = op_m5_sl11_sr11 1922 | cmd[2].dtyp = dt_word 1923 | elif (op_m8_sl0_sr0 == 0x55) and (op_m6_sl26_sr26 == 0xa): 1924 | cmd.itype = self.inames['lv.max.b'] 1925 | cmd[0].type = o_reg 1926 | cmd[0].reg = op_m5_sl21_sr21 1927 | cmd[0].dtyp = dt_word 1928 | cmd[1].type = o_reg 1929 | cmd[1].reg = op_m5_sl16_sr16 1930 | cmd[1].dtyp = dt_word 1931 | cmd[2].type = o_reg 1932 | cmd[2].reg = op_m5_sl11_sr11 1933 | cmd[2].dtyp = dt_word 1934 | elif (op_m8_sl0_sr0 == 0x56) and (op_m6_sl26_sr26 == 0xa): 1935 | cmd.itype = self.inames['lv.max.h'] 1936 | cmd[0].type = o_reg 1937 | cmd[0].reg = op_m5_sl21_sr21 1938 | cmd[0].dtyp = dt_word 1939 | cmd[1].type = o_reg 1940 | cmd[1].reg = op_m5_sl16_sr16 1941 | cmd[1].dtyp = dt_word 1942 | cmd[2].type = o_reg 1943 | cmd[2].reg = op_m5_sl11_sr11 1944 | cmd[2].dtyp = dt_word 1945 | elif (op_m8_sl0_sr0 == 0x57) and (op_m6_sl26_sr26 == 0xa): 1946 | cmd.itype = self.inames['lv.merge.b'] 1947 | cmd[0].type = o_reg 1948 | cmd[0].reg = op_m5_sl21_sr21 1949 | cmd[0].dtyp = dt_word 1950 | cmd[1].type = o_reg 1951 | cmd[1].reg = op_m5_sl16_sr16 1952 | cmd[1].dtyp = dt_word 1953 | cmd[2].type = o_reg 1954 | cmd[2].reg = op_m5_sl11_sr11 1955 | cmd[2].dtyp = dt_word 1956 | elif (op_m8_sl0_sr0 == 0x58) and (op_m6_sl26_sr26 == 0xa): 1957 | cmd.itype = self.inames['lv.merge.h'] 1958 | cmd[0].type = o_reg 1959 | cmd[0].reg = op_m5_sl21_sr21 1960 | cmd[0].dtyp = dt_word 1961 | cmd[1].type = o_reg 1962 | cmd[1].reg = op_m5_sl16_sr16 1963 | cmd[1].dtyp = dt_word 1964 | cmd[2].type = o_reg 1965 | cmd[2].reg = op_m5_sl11_sr11 1966 | cmd[2].dtyp = dt_word 1967 | elif (op_m8_sl0_sr0 == 0x59) and (op_m6_sl26_sr26 == 0xa): 1968 | cmd.itype = self.inames['lv.min.b'] 1969 | cmd[0].type = o_reg 1970 | cmd[0].reg = op_m5_sl21_sr21 1971 | cmd[0].dtyp = dt_word 1972 | cmd[1].type = o_reg 1973 | cmd[1].reg = op_m5_sl16_sr16 1974 | cmd[1].dtyp = dt_word 1975 | cmd[2].type = o_reg 1976 | cmd[2].reg = op_m5_sl11_sr11 1977 | cmd[2].dtyp = dt_word 1978 | elif (op_m8_sl0_sr0 == 0x5a) and (op_m6_sl26_sr26 == 0xa): 1979 | cmd.itype = self.inames['lv.min.h'] 1980 | cmd[0].type = o_reg 1981 | cmd[0].reg = op_m5_sl21_sr21 1982 | cmd[0].dtyp = dt_word 1983 | cmd[1].type = o_reg 1984 | cmd[1].reg = op_m5_sl16_sr16 1985 | cmd[1].dtyp = dt_word 1986 | cmd[2].type = o_reg 1987 | cmd[2].reg = op_m5_sl11_sr11 1988 | cmd[2].dtyp = dt_word 1989 | elif (op_m8_sl0_sr0 == 0x5b) and (op_m6_sl26_sr26 == 0xa): 1990 | cmd.itype = self.inames['lv.msubs.h'] 1991 | cmd[0].type = o_reg 1992 | cmd[0].reg = op_m5_sl21_sr21 1993 | cmd[0].dtyp = dt_word 1994 | cmd[1].type = o_reg 1995 | cmd[1].reg = op_m5_sl16_sr16 1996 | cmd[1].dtyp = dt_word 1997 | cmd[2].type = o_reg 1998 | cmd[2].reg = op_m5_sl11_sr11 1999 | cmd[2].dtyp = dt_word 2000 | elif (op_m8_sl0_sr0 == 0x5c) and (op_m6_sl26_sr26 == 0xa): 2001 | cmd.itype = self.inames['lv.muls.h'] 2002 | cmd[0].type = o_reg 2003 | cmd[0].reg = op_m5_sl21_sr21 2004 | cmd[0].dtyp = dt_word 2005 | cmd[1].type = o_reg 2006 | cmd[1].reg = op_m5_sl16_sr16 2007 | cmd[1].dtyp = dt_word 2008 | cmd[2].type = o_reg 2009 | cmd[2].reg = op_m5_sl11_sr11 2010 | cmd[2].dtyp = dt_word 2011 | elif (op_m8_sl0_sr0 == 0x5d) and (op_m6_sl26_sr26 == 0xa): 2012 | cmd.itype = self.inames['lv.nand'] 2013 | cmd[0].type = o_reg 2014 | cmd[0].reg = op_m5_sl21_sr21 2015 | cmd[0].dtyp = dt_word 2016 | cmd[1].type = o_reg 2017 | cmd[1].reg = op_m5_sl16_sr16 2018 | cmd[1].dtyp = dt_word 2019 | cmd[2].type = o_reg 2020 | cmd[2].reg = op_m5_sl11_sr11 2021 | cmd[2].dtyp = dt_word 2022 | elif (op_m8_sl0_sr0 == 0x5e) and (op_m6_sl26_sr26 == 0xa): 2023 | cmd.itype = self.inames['lv.nor'] 2024 | cmd[0].type = o_reg 2025 | cmd[0].reg = op_m5_sl21_sr21 2026 | cmd[0].dtyp = dt_word 2027 | cmd[1].type = o_reg 2028 | cmd[1].reg = op_m5_sl16_sr16 2029 | cmd[1].dtyp = dt_word 2030 | cmd[2].type = o_reg 2031 | cmd[2].reg = op_m5_sl11_sr11 2032 | cmd[2].dtyp = dt_word 2033 | elif (op_m8_sl0_sr0 == 0x5f) and (op_m6_sl26_sr26 == 0xa): 2034 | cmd.itype = self.inames['lv.or'] 2035 | cmd[0].type = o_reg 2036 | cmd[0].reg = op_m5_sl21_sr21 2037 | cmd[0].dtyp = dt_word 2038 | cmd[1].type = o_reg 2039 | cmd[1].reg = op_m5_sl16_sr16 2040 | cmd[1].dtyp = dt_word 2041 | cmd[2].type = o_reg 2042 | cmd[2].reg = op_m5_sl11_sr11 2043 | cmd[2].dtyp = dt_word 2044 | elif (op_m8_sl0_sr0 == 0x60) and (op_m6_sl26_sr26 == 0xa): 2045 | cmd.itype = self.inames['lv.pack.b'] 2046 | cmd[0].type = o_reg 2047 | cmd[0].reg = op_m5_sl21_sr21 2048 | cmd[0].dtyp = dt_word 2049 | cmd[1].type = o_reg 2050 | cmd[1].reg = op_m5_sl16_sr16 2051 | cmd[1].dtyp = dt_word 2052 | cmd[2].type = o_reg 2053 | cmd[2].reg = op_m5_sl11_sr11 2054 | cmd[2].dtyp = dt_word 2055 | elif (op_m8_sl0_sr0 == 0x61) and (op_m6_sl26_sr26 == 0xa): 2056 | cmd.itype = self.inames['lv.pack.h'] 2057 | cmd[0].type = o_reg 2058 | cmd[0].reg = op_m5_sl21_sr21 2059 | cmd[0].dtyp = dt_word 2060 | cmd[1].type = o_reg 2061 | cmd[1].reg = op_m5_sl16_sr16 2062 | cmd[1].dtyp = dt_word 2063 | cmd[2].type = o_reg 2064 | cmd[2].reg = op_m5_sl11_sr11 2065 | cmd[2].dtyp = dt_word 2066 | elif (op_m8_sl0_sr0 == 0x62) and (op_m6_sl26_sr26 == 0xa): 2067 | cmd.itype = self.inames['lv.packs.b'] 2068 | cmd[0].type = o_reg 2069 | cmd[0].reg = op_m5_sl21_sr21 2070 | cmd[0].dtyp = dt_word 2071 | cmd[1].type = o_reg 2072 | cmd[1].reg = op_m5_sl16_sr16 2073 | cmd[1].dtyp = dt_word 2074 | cmd[2].type = o_reg 2075 | cmd[2].reg = op_m5_sl11_sr11 2076 | cmd[2].dtyp = dt_word 2077 | elif (op_m8_sl0_sr0 == 0x63) and (op_m6_sl26_sr26 == 0xa): 2078 | cmd.itype = self.inames['lv.packs.h'] 2079 | cmd[0].type = o_reg 2080 | cmd[0].reg = op_m5_sl21_sr21 2081 | cmd[0].dtyp = dt_word 2082 | cmd[1].type = o_reg 2083 | cmd[1].reg = op_m5_sl16_sr16 2084 | cmd[1].dtyp = dt_word 2085 | cmd[2].type = o_reg 2086 | cmd[2].reg = op_m5_sl11_sr11 2087 | cmd[2].dtyp = dt_word 2088 | elif (op_m8_sl0_sr0 == 0x64) and (op_m6_sl26_sr26 == 0xa): 2089 | cmd.itype = self.inames['lv.packus.b'] 2090 | cmd[0].type = o_reg 2091 | cmd[0].reg = op_m5_sl21_sr21 2092 | cmd[0].dtyp = dt_word 2093 | cmd[1].type = o_reg 2094 | cmd[1].reg = op_m5_sl16_sr16 2095 | cmd[1].dtyp = dt_word 2096 | cmd[2].type = o_reg 2097 | cmd[2].reg = op_m5_sl11_sr11 2098 | cmd[2].dtyp = dt_word 2099 | elif (op_m8_sl0_sr0 == 0x65) and (op_m6_sl26_sr26 == 0xa): 2100 | cmd.itype = self.inames['lv.packus.h'] 2101 | cmd[0].type = o_reg 2102 | cmd[0].reg = op_m5_sl21_sr21 2103 | cmd[0].dtyp = dt_word 2104 | cmd[1].type = o_reg 2105 | cmd[1].reg = op_m5_sl16_sr16 2106 | cmd[1].dtyp = dt_word 2107 | cmd[2].type = o_reg 2108 | cmd[2].reg = op_m5_sl11_sr11 2109 | cmd[2].dtyp = dt_word 2110 | elif (op_m8_sl0_sr0 == 0x66) and (op_m6_sl26_sr26 == 0xa): 2111 | cmd.itype = self.inames['lv.perm.n'] 2112 | cmd[0].type = o_reg 2113 | cmd[0].reg = op_m5_sl21_sr21 2114 | cmd[0].dtyp = dt_word 2115 | cmd[1].type = o_reg 2116 | cmd[1].reg = op_m5_sl16_sr16 2117 | cmd[1].dtyp = dt_word 2118 | cmd[2].type = o_reg 2119 | cmd[2].reg = op_m5_sl11_sr11 2120 | cmd[2].dtyp = dt_word 2121 | elif (op_m8_sl0_sr0 == 0x67) and (op_m6_sl26_sr26 == 0xa): 2122 | cmd.itype = self.inames['lv.rl.b'] 2123 | cmd[0].type = o_reg 2124 | cmd[0].reg = op_m5_sl21_sr21 2125 | cmd[0].dtyp = dt_word 2126 | cmd[1].type = o_reg 2127 | cmd[1].reg = op_m5_sl16_sr16 2128 | cmd[1].dtyp = dt_word 2129 | cmd[2].type = o_reg 2130 | cmd[2].reg = op_m5_sl11_sr11 2131 | cmd[2].dtyp = dt_word 2132 | elif (op_m8_sl0_sr0 == 0x68) and (op_m6_sl26_sr26 == 0xa): 2133 | cmd.itype = self.inames['lv.rl.h'] 2134 | cmd[0].type = o_reg 2135 | cmd[0].reg = op_m5_sl21_sr21 2136 | cmd[0].dtyp = dt_word 2137 | cmd[1].type = o_reg 2138 | cmd[1].reg = op_m5_sl16_sr16 2139 | cmd[1].dtyp = dt_word 2140 | cmd[2].type = o_reg 2141 | cmd[2].reg = op_m5_sl11_sr11 2142 | cmd[2].dtyp = dt_word 2143 | elif (op_m8_sl0_sr0 == 0x6b) and (op_m6_sl26_sr26 == 0xa): 2144 | cmd.itype = self.inames['lv.sll'] 2145 | cmd[0].type = o_reg 2146 | cmd[0].reg = op_m5_sl21_sr21 2147 | cmd[0].dtyp = dt_word 2148 | cmd[1].type = o_reg 2149 | cmd[1].reg = op_m5_sl16_sr16 2150 | cmd[1].dtyp = dt_word 2151 | cmd[2].type = o_reg 2152 | cmd[2].reg = op_m5_sl11_sr11 2153 | cmd[2].dtyp = dt_word 2154 | elif (op_m8_sl0_sr0 == 0x69) and (op_m6_sl26_sr26 == 0xa): 2155 | cmd.itype = self.inames['lv.sll.b'] 2156 | cmd[0].type = o_reg 2157 | cmd[0].reg = op_m5_sl21_sr21 2158 | cmd[0].dtyp = dt_word 2159 | cmd[1].type = o_reg 2160 | cmd[1].reg = op_m5_sl16_sr16 2161 | cmd[1].dtyp = dt_word 2162 | cmd[2].type = o_reg 2163 | cmd[2].reg = op_m5_sl11_sr11 2164 | cmd[2].dtyp = dt_word 2165 | elif (op_m8_sl0_sr0 == 0x6a) and (op_m6_sl26_sr26 == 0xa): 2166 | cmd.itype = self.inames['lv.sll.h'] 2167 | cmd[0].type = o_reg 2168 | cmd[0].reg = op_m5_sl21_sr21 2169 | cmd[0].dtyp = dt_word 2170 | cmd[1].type = o_reg 2171 | cmd[1].reg = op_m5_sl16_sr16 2172 | cmd[1].dtyp = dt_word 2173 | cmd[2].type = o_reg 2174 | cmd[2].reg = op_m5_sl11_sr11 2175 | cmd[2].dtyp = dt_word 2176 | elif (op_m8_sl0_sr0 == 0x6e) and (op_m6_sl26_sr26 == 0xa): 2177 | cmd.itype = self.inames['lv.sra.b'] 2178 | cmd[0].type = o_reg 2179 | cmd[0].reg = op_m5_sl21_sr21 2180 | cmd[0].dtyp = dt_word 2181 | cmd[1].type = o_reg 2182 | cmd[1].reg = op_m5_sl16_sr16 2183 | cmd[1].dtyp = dt_word 2184 | cmd[2].type = o_reg 2185 | cmd[2].reg = op_m5_sl11_sr11 2186 | cmd[2].dtyp = dt_word 2187 | elif (op_m8_sl0_sr0 == 0x6f) and (op_m6_sl26_sr26 == 0xa): 2188 | cmd.itype = self.inames['lv.sra.h'] 2189 | cmd[0].type = o_reg 2190 | cmd[0].reg = op_m5_sl21_sr21 2191 | cmd[0].dtyp = dt_word 2192 | cmd[1].type = o_reg 2193 | cmd[1].reg = op_m5_sl16_sr16 2194 | cmd[1].dtyp = dt_word 2195 | cmd[2].type = o_reg 2196 | cmd[2].reg = op_m5_sl11_sr11 2197 | cmd[2].dtyp = dt_word 2198 | elif (op_m8_sl0_sr0 == 0x70) and (op_m6_sl26_sr26 == 0xa): 2199 | cmd.itype = self.inames['lv.srl'] 2200 | cmd[0].type = o_reg 2201 | cmd[0].reg = op_m5_sl21_sr21 2202 | cmd[0].dtyp = dt_word 2203 | cmd[1].type = o_reg 2204 | cmd[1].reg = op_m5_sl16_sr16 2205 | cmd[1].dtyp = dt_word 2206 | cmd[2].type = o_reg 2207 | cmd[2].reg = op_m5_sl11_sr11 2208 | cmd[2].dtyp = dt_word 2209 | elif (op_m8_sl0_sr0 == 0x6c) and (op_m6_sl26_sr26 == 0xa): 2210 | cmd.itype = self.inames['lv.srl.b'] 2211 | cmd[0].type = o_reg 2212 | cmd[0].reg = op_m5_sl21_sr21 2213 | cmd[0].dtyp = dt_word 2214 | cmd[1].type = o_reg 2215 | cmd[1].reg = op_m5_sl16_sr16 2216 | cmd[1].dtyp = dt_word 2217 | cmd[2].type = o_reg 2218 | cmd[2].reg = op_m5_sl11_sr11 2219 | cmd[2].dtyp = dt_word 2220 | elif (op_m8_sl0_sr0 == 0x6d) and (op_m6_sl26_sr26 == 0xa): 2221 | cmd.itype = self.inames['lv.srl.h'] 2222 | cmd[0].type = o_reg 2223 | cmd[0].reg = op_m5_sl21_sr21 2224 | cmd[0].dtyp = dt_word 2225 | cmd[1].type = o_reg 2226 | cmd[1].reg = op_m5_sl16_sr16 2227 | cmd[1].dtyp = dt_word 2228 | cmd[2].type = o_reg 2229 | cmd[2].reg = op_m5_sl11_sr11 2230 | cmd[2].dtyp = dt_word 2231 | elif (op_m8_sl0_sr0 == 0x71) and (op_m6_sl26_sr26 == 0xa): 2232 | cmd.itype = self.inames['lv.sub.b'] 2233 | cmd[0].type = o_reg 2234 | cmd[0].reg = op_m5_sl21_sr21 2235 | cmd[0].dtyp = dt_word 2236 | cmd[1].type = o_reg 2237 | cmd[1].reg = op_m5_sl16_sr16 2238 | cmd[1].dtyp = dt_word 2239 | cmd[2].type = o_reg 2240 | cmd[2].reg = op_m5_sl11_sr11 2241 | cmd[2].dtyp = dt_word 2242 | elif (op_m8_sl0_sr0 == 0x72) and (op_m6_sl26_sr26 == 0xa): 2243 | cmd.itype = self.inames['lv.sub.h'] 2244 | cmd[0].type = o_reg 2245 | cmd[0].reg = op_m5_sl21_sr21 2246 | cmd[0].dtyp = dt_word 2247 | cmd[1].type = o_reg 2248 | cmd[1].reg = op_m5_sl16_sr16 2249 | cmd[1].dtyp = dt_word 2250 | cmd[2].type = o_reg 2251 | cmd[2].reg = op_m5_sl11_sr11 2252 | cmd[2].dtyp = dt_word 2253 | elif (op_m8_sl0_sr0 == 0x74) and (op_m6_sl26_sr26 == 0xa): 2254 | cmd.itype = self.inames['lv.subs.h'] 2255 | cmd[0].type = o_reg 2256 | cmd[0].reg = op_m5_sl21_sr21 2257 | cmd[0].dtyp = dt_word 2258 | cmd[1].type = o_reg 2259 | cmd[1].reg = op_m5_sl16_sr16 2260 | cmd[1].dtyp = dt_word 2261 | cmd[2].type = o_reg 2262 | cmd[2].reg = op_m5_sl11_sr11 2263 | cmd[2].dtyp = dt_word 2264 | elif (op_m8_sl0_sr0 == 0x75) and (op_m6_sl26_sr26 == 0xa): 2265 | cmd.itype = self.inames['lv.subu.b'] 2266 | cmd[0].type = o_reg 2267 | cmd[0].reg = op_m5_sl21_sr21 2268 | cmd[0].dtyp = dt_word 2269 | cmd[1].type = o_reg 2270 | cmd[1].reg = op_m5_sl16_sr16 2271 | cmd[1].dtyp = dt_word 2272 | cmd[2].type = o_reg 2273 | cmd[2].reg = op_m5_sl11_sr11 2274 | cmd[2].dtyp = dt_word 2275 | elif (op_m8_sl0_sr0 == 0x76) and (op_m6_sl26_sr26 == 0xa): 2276 | cmd.itype = self.inames['lv.subu.h'] 2277 | cmd[0].type = o_reg 2278 | cmd[0].reg = op_m5_sl21_sr21 2279 | cmd[0].dtyp = dt_word 2280 | cmd[1].type = o_reg 2281 | cmd[1].reg = op_m5_sl16_sr16 2282 | cmd[1].dtyp = dt_word 2283 | cmd[2].type = o_reg 2284 | cmd[2].reg = op_m5_sl11_sr11 2285 | cmd[2].dtyp = dt_word 2286 | elif (op_m8_sl0_sr0 == 0x77) and (op_m6_sl26_sr26 == 0xa): 2287 | cmd.itype = self.inames['lv.subus.b'] 2288 | cmd[0].type = o_reg 2289 | cmd[0].reg = op_m5_sl21_sr21 2290 | cmd[0].dtyp = dt_word 2291 | cmd[1].type = o_reg 2292 | cmd[1].reg = op_m5_sl16_sr16 2293 | cmd[1].dtyp = dt_word 2294 | cmd[2].type = o_reg 2295 | cmd[2].reg = op_m5_sl11_sr11 2296 | cmd[2].dtyp = dt_word 2297 | elif (op_m8_sl0_sr0 == 0x78) and (op_m6_sl26_sr26 == 0xa): 2298 | cmd.itype = self.inames['lv.subus.h'] 2299 | cmd[0].type = o_reg 2300 | cmd[0].reg = op_m5_sl21_sr21 2301 | cmd[0].dtyp = dt_word 2302 | cmd[1].type = o_reg 2303 | cmd[1].reg = op_m5_sl16_sr16 2304 | cmd[1].dtyp = dt_word 2305 | cmd[2].type = o_reg 2306 | cmd[2].reg = op_m5_sl11_sr11 2307 | cmd[2].dtyp = dt_word 2308 | elif (op_m8_sl0_sr0 == 0x79) and (op_m6_sl26_sr26 == 0xa): 2309 | cmd.itype = self.inames['lv.unpack.b'] 2310 | cmd[0].type = o_reg 2311 | cmd[0].reg = op_m5_sl21_sr21 2312 | cmd[0].dtyp = dt_word 2313 | cmd[1].type = o_reg 2314 | cmd[1].reg = op_m5_sl16_sr16 2315 | cmd[1].dtyp = dt_word 2316 | cmd[2].type = o_reg 2317 | cmd[2].reg = op_m5_sl11_sr11 2318 | cmd[2].dtyp = dt_word 2319 | elif (op_m8_sl0_sr0 == 0x7a) and (op_m6_sl26_sr26 == 0xa): 2320 | cmd.itype = self.inames['lv.unpack.h'] 2321 | cmd[0].type = o_reg 2322 | cmd[0].reg = op_m5_sl21_sr21 2323 | cmd[0].dtyp = dt_word 2324 | cmd[1].type = o_reg 2325 | cmd[1].reg = op_m5_sl16_sr16 2326 | cmd[1].dtyp = dt_word 2327 | cmd[2].type = o_reg 2328 | cmd[2].reg = op_m5_sl11_sr11 2329 | cmd[2].dtyp = dt_word 2330 | elif (op_m8_sl0_sr0 == 0x7b) and (op_m6_sl26_sr26 == 0xa): 2331 | cmd.itype = self.inames['lv.xor'] 2332 | cmd[0].type = o_reg 2333 | cmd[0].reg = op_m5_sl21_sr21 2334 | cmd[0].dtyp = dt_word 2335 | cmd[1].type = o_reg 2336 | cmd[1].reg = op_m5_sl16_sr16 2337 | cmd[1].dtyp = dt_word 2338 | cmd[2].type = o_reg 2339 | cmd[2].reg = op_m5_sl11_sr11 2340 | cmd[2].dtyp = dt_word 2341 | return cmd.size 2342 | 2343 | def ana(self): 2344 | try: 2345 | return self._ana() 2346 | except DecodingError: 2347 | return 0 2348 | 2349 | def _emu_operand(self, op): 2350 | if op.type == o_mem: 2351 | ua_dodata2(0, op.addr, op.dtyp) 2352 | ua_add_dref(0, op.addr, dr_R) 2353 | elif op.type == o_near: 2354 | if self.cmd.get_canon_feature() & CF_CALL: 2355 | fl = fl_CN 2356 | ua_add_cref(0, op.addr, fl) 2357 | else: 2358 | fl = fl_JN 2359 | self.delayed_jmp[self.cmd.ea+4] = {'addr': op.addr, 'fl': fl} 2360 | 2361 | 2362 | 2363 | 2364 | 2365 | def emu(self): 2366 | cmd = self.cmd 2367 | ft = cmd.get_canon_feature() 2368 | if ft & CF_USE1: 2369 | self._emu_operand(cmd[0]) 2370 | if ft & CF_USE2: 2371 | self._emu_operand(cmd[1]) 2372 | if ft & CF_USE3: 2373 | self._emu_operand(cmd[2]) 2374 | if ft & CF_USE4: 2375 | self._emu_operand(cmd[3]) 2376 | if not ft & CF_STOP: 2377 | ua_add_cref(0, cmd.ea + cmd.size, fl_F) 2378 | 2379 | if self.cmd.ea in self.delayed_jmp: 2380 | ua_add_cref(0, self.delayed_jmp[self.cmd.ea]['addr'], self.delayed_jmp[self.cmd.ea]['fl']) 2381 | 2382 | return True 2383 | 2384 | def outop(self, op): 2385 | 2386 | optype = op.type 2387 | fl = op.specval 2388 | 2389 | if optype == o_reg: 2390 | out_register(self.regNames[op.reg]) 2391 | 2392 | elif optype == o_imm: 2393 | OutValue(op, OOFW_IMM | OOF_SIGNED) 2394 | 2395 | elif optype in [o_near, o_mem]: 2396 | if optype == o_mem and fl == FL_ABSOLUTE: 2397 | out_symbol('&') 2398 | r = out_name_expr(op, op.addr, BADADDR) 2399 | if not r: 2400 | out_tagon(COLOR_ERROR) 2401 | OutLong(op.addr, 16) 2402 | out_tagoff(COLOR_ERROR) 2403 | QueueSet(Q_noName, self.cmd.ea) 2404 | 2405 | elif optype == o_displ: 2406 | # 16-bit index is signed 2407 | OutValue(op, OOF_ADDR | OOFW_8 | OOF_SIGNED) 2408 | out_symbol('(') 2409 | out_register(self.regNames[op.reg]) 2410 | out_symbol(')') 2411 | 2412 | elif optype == o_phrase: 2413 | out_symbol('@') 2414 | out_register(self.regNames[op.reg]) 2415 | else: 2416 | return False 2417 | 2418 | return True 2419 | 2420 | def out(self): 2421 | cmd = self.cmd 2422 | ft = cmd.get_canon_feature() 2423 | buf = init_output_buffer(1024) 2424 | OutMnem(15) 2425 | if ft & CF_USE1: 2426 | out_one_operand(0) 2427 | if ft & CF_USE2: 2428 | OutChar(',') 2429 | OutChar(' ') 2430 | out_one_operand(1) 2431 | if ft & CF_USE3: 2432 | OutChar(',') 2433 | OutChar(' ') 2434 | out_one_operand(2) 2435 | term_output_buffer() 2436 | cvar.gl_comm = 1 2437 | MakeLine(buf) 2438 | 2439 | def PROCESSOR_ENTRY(): 2440 | return openrisc_processor_t() 2441 | -------------------------------------------------------------------------------- /openrisc-arch-1.1-rev0.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xDeva/ida-cpu-OpenRisc/003c3aac7443858e0fb886d760591ef9bdbc891b/openrisc-arch-1.1-rev0.pdf -------------------------------------------------------------------------------- /parse_doc.py: -------------------------------------------------------------------------------- 1 | 2 | def parse_page(): 3 | 4 | f = open('openrisc-arch-1.1-rev0.txt', 'r').read() 5 | d = f.split('OpenRISC 1000 Architecture Manual') 6 | d = filter(lambda x: "opcode" in x, d) 7 | d = map(lambda x: x[x.rfind("Right")+5:x.find("Description")].split('\n'), d) 8 | 9 | inst = list() 10 | 11 | for x in d: 12 | 13 | if len(x) < 4 or x[-4] != 'Format:': 14 | continue 15 | 16 | new_inst = dict() 17 | # name and format 18 | new_inst['format'] = x[-3] 19 | new_inst['name'] = x[-3][:x[-3].find(' ')] 20 | 21 | 22 | # number of bits 23 | bits = filter(lambda x: x[-5:] == " bits" or x[-4:] == " bit" , x) 24 | new_inst['bits'] = map(lambda x: int(x[:x.find(' ')]), bits)[::-1] 25 | 26 | # values 27 | values = filter(lambda x: x in ['A', 'B', 'C', 'D', 'I', 'K', 'L', 'N', 'reserved'] or x[:6] == "opcode", x) 28 | assert(len(values) == len(new_inst['bits'])) 29 | new_inst['values'] = values[::-1] 30 | 31 | inst.append(new_inst) 32 | 33 | return inst 34 | 35 | 36 | def gen_instructions(inst): 37 | inst_str = list() 38 | 39 | for i in inst: 40 | 41 | nb_CF_USE = len(set(filter(lambda x: x in ['A', 'B', 'C', 'D', 'I', 'K', 'L', 'N'] , i['values']))) 42 | 43 | features = " | ".join(['CF_USE%i' % (j+1) for j in range(nb_CF_USE)]) 44 | if not features: 45 | features = "0" 46 | str_ins = "{'name': '%s', 'feature': %s, 'cmt': '%s'}" % (i['name'], features, i['format']) 47 | inst_str.append(str_ins) 48 | 49 | return "["+",\n".join(inst_str)+"]" 50 | 51 | mask_dict = set() 52 | def get_mask_val(bmask, shiftl, shiftr): 53 | global mask_dict 54 | mask_dict.add((bmask, shiftl, shiftr)) 55 | return "op_m%i_sl%i_sr%i" % (bmask, shiftl, shiftr) 56 | 57 | def gen_masks(): 58 | global mask_dict 59 | return "\n".join(map(lambda x: "op_m%i_sl%i_sr%i = ((opcode & 0x%x) >> %i)" % (x[0], x[1], x[2], ((1 << x[0])-1) << x[1], x[2]), mask_dict)) 60 | 61 | def parse_inst(insts): 62 | 63 | for i in insts: 64 | 65 | cur_bit = 0 66 | cond = list() 67 | op = list() 68 | 69 | for j, nb_bit in enumerate(i['bits']): 70 | 71 | cur_op = i['values'][j] 72 | 73 | # immediate 74 | if cur_op in ['I', 'K', 'L']: 75 | # if immediate in two part 76 | if 'I' in i['values'][j+1:]: 77 | # get index of this one 78 | index = i['values'][j+1:].index('I') 79 | # compute start offset 80 | start_off = cur_bit + nb_bit + sum(i['bits'][j+1:j+1+index]) 81 | # compute size of the second part of I 82 | size = i['bits'][index] 83 | 84 | imm = {'type': 'o_imm', 'dtyp': 'dt_word', 'value': 'SIGNEXT(%s | %s, %i)' % (get_mask_val(nb_bit, cur_bit, cur_bit), get_mask_val(size, start_off, start_off-cur_bit-nb_bit), nb_bit+size)} 85 | 86 | # I is ok, we have handled it 87 | i['values'][j+1+index] = "_" 88 | else: 89 | if cur_op in ['K', 'L']: 90 | imm = {'type': 'o_imm', 'dtyp': 'dt_word', 'value': '%s' % (get_mask_val(nb_bit, cur_bit, cur_bit))} 91 | else: 92 | imm = {'type': 'o_imm', 'dtyp': 'dt_word', 'value': 'SIGNEXT(%s, %i)' % (get_mask_val(nb_bit, cur_bit, cur_bit), nb_bit)} 93 | 94 | # if this is a displacement 95 | if 'I(rA)' in i['format']: 96 | regA = i['values'].index('A') 97 | # compute start offset 98 | start_off = sum(i['bits'][:regA]) 99 | size = i['bits'][regA] 100 | 101 | imm = {'type': 'o_displ', 'addr': imm['value'], 'reg': '%s' % (get_mask_val(size, start_off, start_off))} 102 | i['values'][regA] = "_" 103 | 104 | op.append(imm) 105 | 106 | # register 107 | elif cur_op in ['A', 'B', 'C', 'D']: 108 | reg = {'type': 'o_reg', 'dtyp': 'dt_word', 'reg': '%s' % (get_mask_val(nb_bit, cur_bit, cur_bit))} 109 | op.append(reg) 110 | 111 | # near 112 | elif cur_op in ['N']: 113 | near = {'type': 'o_near', 'dtyp': 'dt_word', 'addr': 'cmd.ea + 4*SIGNEXT(%s, %i)' % (get_mask_val(nb_bit, cur_bit, cur_bit), nb_bit)} 114 | op.append(near) 115 | 116 | # opcode value 117 | elif cur_op[:6] == "opcode": 118 | 119 | v = int(cur_op[7:], 16) 120 | cond.append("(%s == 0x%x)" % (get_mask_val(nb_bit, cur_bit, cur_bit), v)) 121 | 122 | # reserved 123 | elif cur_op == "reserved": 124 | pass 125 | 126 | elif cur_op == "_": 127 | # already handled 128 | pass 129 | 130 | else: 131 | # problem 132 | print "problem" 133 | print cur_op 134 | exit(0) 135 | 136 | cur_bit += nb_bit 137 | 138 | 139 | if i['name'] in ['l.sw', 'l.swa']: 140 | i['op'] = op 141 | else: 142 | i['op'] = op[::-1] 143 | 144 | i['cond_str'] = cond 145 | i['itype_str'] = "cmd.itype = self.inames['%s']" % (i['name']) 146 | 147 | return insts 148 | 149 | 150 | def gen_ana(insts): 151 | ana_str = """ 152 | def _ana(self): 153 | cmd = self.cmd 154 | opcode = self._read_cmd_dword() 155 | %s 156 | """ % gen_masks() 157 | 158 | for i in insts: 159 | 160 | cur_i_str = '' 161 | cur_i_str += "elif "+" and ".join(i['cond_str'])+":\n" 162 | cur_i_str += ' '+i['itype_str']+'\n' 163 | for nb, op_dict in enumerate(i['op']): 164 | for _type, _val in op_dict.iteritems(): 165 | cur_i_str += " cmd[%i].%s = %s\n" % (nb, _type, _val) 166 | 167 | 168 | ana_str += cur_i_str 169 | 170 | return ana_str 171 | 172 | 173 | d = parse_page() 174 | d = parse_inst(d) 175 | 176 | print gen_instructions(d) 177 | print gen_ana(d) --------------------------------------------------------------------------------