├── .gitignore ├── CPU-Guide ├── 31连接表.xlsx ├── 54 标注周期和判别.pdf ├── 54指令CPU实验指导书.pdf ├── 54条CPU指令集.pdf ├── 照片 2018-11-18 06 18 55.png ├── 电路图.pdf ├── 连接表.numbers ├── 连接表.xlsx └── 静动态流水线实验指导书.pdf ├── README.md ├── SD-DDR-Cache ├── CPU │ ├── CLZCounter.v │ ├── CP0.v │ ├── CPU.v │ ├── Concatenater.v │ ├── ControlUnit.v │ ├── Extender.v │ ├── InstructionDecoder.v │ ├── LogicArithmetic.v │ ├── LuiSlt.v │ ├── MDU.v │ ├── MUX.v │ ├── ProgramCounterReg.v │ ├── ReadSelect.v │ ├── RegFile.v │ ├── Registers.v │ ├── Regs.v │ ├── Seg.v │ ├── SegOutput.v │ ├── Shifter.v │ ├── Top.v │ └── WriteSelect.v ├── DDR2.v ├── SD.v ├── clk_wiz_0 │ ├── clk_wiz_0.dcp │ ├── clk_wiz_0.v │ ├── clk_wiz_0.veo │ ├── clk_wiz_0.xci │ ├── clk_wiz_0.xdc │ ├── clk_wiz_0.xml │ ├── clk_wiz_0_board.xdc │ ├── clk_wiz_0_clk_wiz.v │ ├── clk_wiz_0_ooc.xdc │ ├── clk_wiz_0_sim_netlist.v │ ├── clk_wiz_0_sim_netlist.vhdl │ ├── clk_wiz_0_stub.v │ ├── clk_wiz_0_stub.vhdl │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ ├── mmcm_pll_drp_func_7s_pll.vh │ ├── mmcm_pll_drp_func_us_mmcm.vh │ ├── mmcm_pll_drp_func_us_pll.vh │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ └── mmcm_pll_drp_func_us_plus_pll.vh ├── ddr2 │ ├── ddr2.dcp │ ├── ddr2.veo │ ├── ddr2.xci │ ├── ddr2.xml │ ├── ddr2 │ │ ├── datasheet.txt │ │ ├── docs │ │ │ └── phy_only_support_readme.txt │ │ ├── example_design │ │ │ ├── log.txt │ │ │ ├── par │ │ │ │ ├── example_top.xdc │ │ │ │ └── readme.txt │ │ │ ├── rtl │ │ │ │ ├── example_top.v │ │ │ │ └── traffic_gen │ │ │ │ │ ├── mig_7series_v4_1_afifo.v │ │ │ │ │ ├── mig_7series_v4_1_cmd_gen.v │ │ │ │ │ ├── mig_7series_v4_1_cmd_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_1_data_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_1_init_mem_pattern_ctr.v │ │ │ │ │ ├── mig_7series_v4_1_memc_flow_vcontrol.v │ │ │ │ │ ├── mig_7series_v4_1_memc_traffic_gen.v │ │ │ │ │ ├── mig_7series_v4_1_rd_data_gen.v │ │ │ │ │ ├── mig_7series_v4_1_read_data_path.v │ │ │ │ │ ├── mig_7series_v4_1_read_posted_fifo.v │ │ │ │ │ ├── mig_7series_v4_1_s7ven_data_gen.v │ │ │ │ │ ├── mig_7series_v4_1_tg_prbs_gen.v │ │ │ │ │ ├── mig_7series_v4_1_tg_status.v │ │ │ │ │ ├── mig_7series_v4_1_traffic_gen_top.v │ │ │ │ │ ├── mig_7series_v4_1_vio_init_pattern_bram.v │ │ │ │ │ ├── mig_7series_v4_1_wr_data_gen.v │ │ │ │ │ └── mig_7series_v4_1_write_data_path.v │ │ │ └── sim │ │ │ │ ├── ddr2_model.v │ │ │ │ ├── ddr2_model_parameters.vh │ │ │ │ ├── ies_run.sh │ │ │ │ ├── readme.txt │ │ │ │ ├── sim.do │ │ │ │ ├── sim_tb_top.v │ │ │ │ ├── vcs_run.sh │ │ │ │ ├── wiredly.v │ │ │ │ ├── xsim_files.prj │ │ │ │ ├── xsim_options.tcl │ │ │ │ └── xsim_run.bat │ │ ├── mig.prj │ │ └── user_design │ │ │ ├── constraints │ │ │ ├── ddr2.xdc │ │ │ └── ddr2_ooc.xdc │ │ │ ├── log.txt │ │ │ └── rtl │ │ │ ├── clocking │ │ │ ├── mig_7series_v4_1_clk_ibuf.v │ │ │ ├── mig_7series_v4_1_infrastructure.v │ │ │ ├── mig_7series_v4_1_iodelay_ctrl.v │ │ │ └── mig_7series_v4_1_tempmon.v │ │ │ ├── controller │ │ │ ├── mig_7series_v4_1_arb_mux.v │ │ │ ├── mig_7series_v4_1_arb_row_col.v │ │ │ ├── mig_7series_v4_1_arb_select.v │ │ │ ├── mig_7series_v4_1_bank_cntrl.v │ │ │ ├── mig_7series_v4_1_bank_common.v │ │ │ ├── mig_7series_v4_1_bank_compare.v │ │ │ ├── mig_7series_v4_1_bank_mach.v │ │ │ ├── mig_7series_v4_1_bank_queue.v │ │ │ ├── mig_7series_v4_1_bank_state.v │ │ │ ├── mig_7series_v4_1_col_mach.v │ │ │ ├── mig_7series_v4_1_mc.v │ │ │ ├── mig_7series_v4_1_rank_cntrl.v │ │ │ ├── mig_7series_v4_1_rank_common.v │ │ │ ├── mig_7series_v4_1_rank_mach.v │ │ │ └── mig_7series_v4_1_round_robin_arb.v │ │ │ ├── ddr2.v │ │ │ ├── ddr2_mig.v │ │ │ ├── ddr2_mig_sim.v │ │ │ ├── ecc │ │ │ ├── mig_7series_v4_1_ecc_buf.v │ │ │ ├── mig_7series_v4_1_ecc_dec_fix.v │ │ │ ├── mig_7series_v4_1_ecc_gen.v │ │ │ ├── mig_7series_v4_1_ecc_merge_enc.v │ │ │ └── mig_7series_v4_1_fi_xor.v │ │ │ ├── ip_top │ │ │ ├── mig_7series_v4_1_mem_intfc.v │ │ │ └── mig_7series_v4_1_memc_ui_top_std.v │ │ │ ├── phy │ │ │ ├── mig_7series_v4_1_ddr_byte_group_io.v │ │ │ ├── mig_7series_v4_1_ddr_byte_lane.v │ │ │ ├── mig_7series_v4_1_ddr_calib_top.v │ │ │ ├── mig_7series_v4_1_ddr_if_post_fifo.v │ │ │ ├── mig_7series_v4_1_ddr_mc_phy.v │ │ │ ├── mig_7series_v4_1_ddr_mc_phy_wrapper.v │ │ │ ├── mig_7series_v4_1_ddr_of_pre_fifo.v │ │ │ ├── mig_7series_v4_1_ddr_phy_4lanes.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ck_addr_cmd_delay.v │ │ │ ├── mig_7series_v4_1_ddr_phy_dqs_found_cal.v │ │ │ ├── mig_7series_v4_1_ddr_phy_dqs_found_cal_hr.v │ │ │ ├── mig_7series_v4_1_ddr_phy_init.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_cntlr.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_data.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_edge.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_lim.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_mux.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_po_cntlr.v │ │ │ ├── mig_7series_v4_1_ddr_phy_ocd_samp.v │ │ │ ├── mig_7series_v4_1_ddr_phy_oclkdelay_cal.v │ │ │ ├── mig_7series_v4_1_ddr_phy_prbs_rdlvl.v │ │ │ ├── mig_7series_v4_1_ddr_phy_rdlvl.v │ │ │ ├── mig_7series_v4_1_ddr_phy_tempmon.v │ │ │ ├── mig_7series_v4_1_ddr_phy_top.v │ │ │ ├── mig_7series_v4_1_ddr_phy_wrcal.v │ │ │ ├── mig_7series_v4_1_ddr_phy_wrlvl.v │ │ │ ├── mig_7series_v4_1_ddr_phy_wrlvl_off_delay.v │ │ │ ├── mig_7series_v4_1_ddr_prbs_gen.v │ │ │ ├── mig_7series_v4_1_poc_cc.v │ │ │ ├── mig_7series_v4_1_poc_edge_store.v │ │ │ ├── mig_7series_v4_1_poc_meta.v │ │ │ ├── mig_7series_v4_1_poc_pd.v │ │ │ ├── mig_7series_v4_1_poc_tap_base.v │ │ │ └── mig_7series_v4_1_poc_top.v │ │ │ └── ui │ │ │ ├── mig_7series_v4_1_ui_cmd.v │ │ │ ├── mig_7series_v4_1_ui_rd_data.v │ │ │ ├── mig_7series_v4_1_ui_top.v │ │ │ └── mig_7series_v4_1_ui_wr_data.v │ ├── ddr2_sim_netlist.v │ ├── ddr2_sim_netlist.vhdl │ ├── ddr2_stub.v │ ├── ddr2_stub.vhdl │ ├── ddr2_xmdf.tcl │ ├── doc │ │ └── mig_7series_v4_1_changelog.txt │ ├── mig_a.prj │ └── xil_txt.in ├── dmem │ ├── dmem.dcp │ ├── dmem.veo │ ├── dmem.vho │ ├── dmem.xci │ ├── dmem.xml │ ├── dmem_ooc.xdc │ ├── dmem_sim_netlist.v │ ├── dmem_sim_netlist.vhdl │ ├── dmem_stub.v │ ├── dmem_stub.vhdl │ ├── doc │ │ └── dist_mem_gen_v8_0_changelog.txt │ ├── hdl │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ ├── sim │ │ └── dmem.v │ ├── simulation │ │ └── dist_mem_gen_v8_0.v │ └── synth │ │ └── dmem.vhd ├── imem │ ├── doc │ │ └── dist_mem_gen_v8_0_changelog.txt │ ├── hdl │ │ └── dist_mem_gen_v8_0_vhsyn_rfs.vhd │ ├── imem.dcp │ ├── imem.mif │ ├── imem.veo │ ├── imem.vho │ ├── imem.xci │ ├── imem.xml │ ├── imem_ooc.xdc │ ├── imem_sim_netlist.v │ ├── imem_sim_netlist.vhdl │ ├── imem_stub.v │ ├── imem_stub.vhdl │ ├── sim │ │ └── imem.v │ ├── simulation │ │ └── dist_mem_gen_v8_0.v │ └── synth │ │ └── imem.vhd ├── s.xdc ├── 写回SD测试代码.asm └── 引导启动代码.asm ├── V1 ├── 7sd.xdc ├── CPU.v ├── Concatenater.v ├── ConfJudger.v ├── ControlUnit.v ├── Extender.v ├── InstructionDecoder.v ├── LogicArithmetic.v ├── LuiSlt.v ├── MyIMEM.v ├── PipeReg.v ├── ProgramCounterReg.v ├── ReadSelect.v ├── RegFile.v ├── Seg.v ├── SegOutput.v ├── Shifter.v ├── StopJudger.v ├── Top.v ├── WriteSelect.v ├── dmem.v └── pipemux.v ├── V2 ├── 7sd.xdc ├── CPU.v ├── Concatenater.v ├── ConfJudger.v ├── ControlUnit.v ├── Extender.v ├── InstructionDecoder.v ├── LogicArithmetic.v ├── LuiSlt.v ├── MyDMEM.v ├── PipeReg.v ├── ProgramCounterReg.v ├── ReadSelect.v ├── RegFile.v ├── Seg.v ├── SegOutput.v ├── Shifter.v ├── StopJudger.v ├── Top.v ├── WriteSelect.v ├── pipemux.v └── tb_Top.v └── mips1.asm /.gitignore: -------------------------------------------------------------------------------- 1 | CPU-Guide/~* 2 | CPU-Guide/IDONOTKNOW 3 | a* 4 | test* 5 | *.vcd 6 | *.jar 7 | *.out -------------------------------------------------------------------------------- /CPU-Guide/31连接表.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/CPU-Guide/31连接表.xlsx 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/SD-DDR-Cache/CPU/CLZCounter.v: -------------------------------------------------------------------------------- 1 | module CLZCounter( 2 | input [31:0]rs_value, 3 | input start, 4 | output busy, 5 | output reg [31:0]result 6 | ); 7 | 8 | /* 9 | * 先使用组合逻辑 10 | * 之后补上状态机 11 | */ 12 | 13 | assign busy = 1'b0; 14 | always @(*) begin 15 | if(rs_value[31:0] == 32'b0) begin 16 | result = 32'd32; 17 | end else if(rs_value[31:0] == 32'b1) begin 18 | result = 32'd31; 19 | end else if(rs_value[31:1] == 31'b1) begin 20 | result = 32'd30; 21 | end else if(rs_value[31:2] == 30'b1) begin 22 | result = 32'd29; 23 | end else if(rs_value[31:3] == 29'b1) begin 24 | result = 32'd28; 25 | end else if(rs_value[31:4] == 28'b1) begin 26 | result = 32'd27; 27 | end else if(rs_value[31:5] == 27'b1) begin 28 | result = 32'd26; 29 | end else if(rs_value[31:6] == 26'b1) begin 30 | result = 32'd25; 31 | end else if(rs_value[31:7] == 25'b1) begin 32 | result = 32'd24; 33 | end else if(rs_value[31:8] == 24'b1) begin 34 | result = 32'd23; 35 | end else if(rs_value[31:9] == 23'b1) begin 36 | result = 32'd22; 37 | end else if(rs_value[31:10] == 22'b1) begin 38 | result = 32'd21; 39 | end else if(rs_value[31:11] == 21'b1) begin 40 | result = 32'd20; 41 | end else if(rs_value[31:12] == 20'b1) begin 42 | result = 32'd19; 43 | end else if(rs_value[31:13] == 19'b1) begin 44 | result = 32'd18; 45 | end else if(rs_value[31:14] == 18'b1) begin 46 | result = 32'd17; 47 | end else if(rs_value[31:15] == 17'b1) begin 48 | result = 32'd16; 49 | end else if(rs_value[31:16] == 16'b1) begin 50 | result = 32'd15; 51 | end else if(rs_value[31:17] == 15'b1) begin 52 | result = 32'd14; 53 | end else if(rs_value[31:18] == 14'b1) begin 54 | result = 32'd13; 55 | end else if(rs_value[31:19] == 13'b1) begin 56 | result = 32'd12; 57 | end else if(rs_value[31:20] == 12'b1) begin 58 | result = 32'd11; 59 | end else if(rs_value[31:21] == 11'b1) begin 60 | result = 32'd10; 61 | end else if(rs_value[31:22] == 10'b1) begin 62 | result = 32'd9; 63 | end else if(rs_value[31:23] == 9'b1) begin 64 | result = 32'd8; 65 | end else if(rs_value[31:24] == 8'b1) begin 66 | result = 32'd7; 67 | end else if(rs_value[31:25] == 7'b1) begin 68 | result = 32'd6; 69 | end else if(rs_value[31:26] == 6'b1) begin 70 | result = 32'd5; 71 | end else if(rs_value[31:27] == 5'b1) begin 72 | result = 32'd4; 73 | end else if(rs_value[31:28] == 4'b1) begin 74 | result = 32'd3; 75 | end else if(rs_value[31:29] == 3'b1) begin 76 | result = 32'd2; 77 | end else if(rs_value[31:30] == 2'b1) begin 78 | result = 32'd1; 79 | end else begin 80 | result = 32'd0; 81 | end 82 | end 83 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/CP0.v: -------------------------------------------------------------------------------- 1 | module CP0( 2 | input clk, 3 | input rst, 4 | input mfc0, 5 | input [4:0]addr, 6 | input mtc0, 7 | input [31:0]data, 8 | input exception, 9 | input eret, 10 | input [31:0]pc, 11 | input [3:0]cause, 12 | output reg [31:0]CP0_out, 13 | output [31:0]status, 14 | output [31:0]epc_out 15 | ); 16 | 17 | reg [31:0]memory[31:0]; 18 | integer i; 19 | initial begin 20 | for(i = 0; i <= 31; i = i + 1) begin 21 | memory[i] = 32'b0; 22 | end 23 | end 24 | 25 | // reg [31:0]status_reg = 32'b0;//12号寄存器 [3:1]分别屏蔽teq, break, systcall 26 | // reg [31:0]cause_reg = 32'b0;//13号寄存器 [6:2]记录异常原因 27 | // reg [31:0]epc_reg = 32'b0;//14号寄存器 存放PC+4 28 | //wire [31:0]status_reg = memory[12]; 29 | //wire [31:0]cause_reg = memory[13]; 30 | //wire [31:0]epc_reg = memory[14]; 31 | 32 | reg exception_valid = 1'b0; 33 | always @(*) begin 34 | if(exception & memory[12][0]) begin 35 | case(cause[3:0]) 36 | 4'b1000: begin //systcall 37 | if(memory[12][1]) begin 38 | exception_valid = 1'b1; 39 | end else begin 40 | exception_valid = 1'b0; 41 | end 42 | end 43 | 4'b1001: begin //break 44 | if(memory[12][2]) begin 45 | exception_valid = 1'b1; 46 | end else begin 47 | exception_valid = 1'b0; 48 | end 49 | end 50 | 4'b1101: begin //teq 51 | if(memory[12][3]) begin 52 | exception_valid = 1'b1; 53 | end else begin 54 | exception_valid = 1'b0; 55 | end 56 | end 57 | default: begin 58 | exception_valid = 1'bx; 59 | end 60 | endcase 61 | end else begin 62 | exception_valid = 1'b0; 63 | end 64 | end 65 | 66 | reg in_exception = 1'b0; 67 | always @(negedge clk or posedge rst) begin 68 | if(rst) begin 69 | memory[12] <= 32'h0000000f; 70 | memory[13] <= 32'b0; 71 | memory[14] <= 32'b0; 72 | in_exception <= 1'b0; 73 | end else begin 74 | if(mtc0) begin 75 | //mtc0有效 76 | // case(addr[4:0]) 77 | // 5'd12: begin //systcall 78 | // status_reg <= data; 79 | // end 80 | // 5'd13: begin //break 81 | // cause_reg <= data; 82 | // end 83 | // 5'd14: begin //teq 84 | // epc_reg <= data; 85 | // end 86 | // default: begin 87 | // status_reg <= status_reg; 88 | // cause_reg <= cause_reg; 89 | // epc_reg <= epc_reg; 90 | // end 91 | // endcase 92 | memory[addr] <= data; 93 | end else begin 94 | if(exception_valid & (~in_exception)) begin 95 | memory[12] <= {memory[12][26:0], 5'b0}; 96 | memory[13] <= {26'b0 ,cause, 2'b0}; 97 | memory[14] <= pc - 32'h4; 98 | in_exception <= 1'b1; 99 | end else if(eret & in_exception) begin 100 | memory[12] <= {5'b0, memory[12][31:5]}; 101 | in_exception <= 1'b0; 102 | end 103 | end 104 | end 105 | end 106 | 107 | always @(*) begin 108 | if(mfc0) begin 109 | // case(addr) 110 | // 5'd12: begin 111 | // CP0_out = status_reg; 112 | // end 113 | // 5'd13: begin 114 | // CP0_out = cause_reg; 115 | // end 116 | // 5'd14: begin 117 | // CP0_out = epc_reg; 118 | // end 119 | // default: begin 120 | // CP0_out = 32'bx; 121 | // end 122 | // endcase 123 | CP0_out = memory[addr]; 124 | end else begin 125 | CP0_out = 32'bx; 126 | end 127 | end 128 | 129 | wire [31:0]cause_ = memory[13]; 130 | assign status = memory[12];//status_reg; 131 | assign epc_out = memory[14];//epc_reg; 132 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/Concatenater.v: -------------------------------------------------------------------------------- 1 | //拼接器 2 | module Concatenater( 3 | input [31:8]DMEM, 4 | input [15:0]rt_value, 5 | input [31:28]PC, 6 | input [25:0]index, 7 | output [31:0]out_8, 8 | output [31:0]out_16, 9 | output [31:0]out_J 10 | ); 11 | assign out_8 = {DMEM[31:8], rt_value[7:0]}; 12 | assign out_16 = {DMEM[31:16], rt_value[15:0]}; 13 | assign out_J = {PC[31:28], index[25:0], 2'b0}; 14 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/Extender.v: -------------------------------------------------------------------------------- 1 | module Extender( 2 | input [15:0]SignExt16_in, 3 | input [15:0]ZeroExt16_in, 4 | input [15:0]SignExt18_in, 5 | input [7:0]SignExt8_in, 6 | input [7:0]ZeroExt8_in, 7 | input [4:0]ZeroExt5_in, 8 | output [31:0]SignExt16_out, 9 | output [31:0]ZeroExt16_out, 10 | output [31:0]SignExt18_out, 11 | output [31:0]SignExt8_out, 12 | output [31:0]ZeroExt8_out, 13 | output [31:0]ZeroExt5_out 14 | ); 15 | assign SignExt16_out = {{16{SignExt16_in[15]}}, SignExt16_in}; 16 | assign ZeroExt16_out = {16'b0, ZeroExt16_in}; 17 | assign SignExt18_out = {{14{SignExt18_in[15]}}, SignExt18_in, 2'b0}; 18 | assign SignExt8_out = {{24{SignExt8_in[7]}}, SignExt8_in}; 19 | assign ZeroExt8_out = {24'b0, ZeroExt8_in}; 20 | assign ZeroExt5_out = {27'b0, ZeroExt5_in}; 21 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/InstructionDecoder.v: -------------------------------------------------------------------------------- 1 | module InstructionDecoder(instruction, op, rs, rt, rd, shamt, func, imm16, index); 2 | input [31:0]instruction; 3 | output [5:0]op; 4 | output [4:0]rs; 5 | output [4:0]rt; 6 | output [4:0]rd; 7 | output [4:0]shamt; 8 | output [5:0]func; 9 | output [15:0]imm16; 10 | output [25:0]index; 11 | 12 | assign op = instruction[31:26]; 13 | assign rs = instruction[25:21]; 14 | assign rt = instruction[20:16]; 15 | assign rd = instruction[15:11]; 16 | assign shamt = instruction[10:6]; 17 | assign func = instruction[5:0]; 18 | assign imm16 = instruction[15:0]; 19 | assign index = instruction[25:0]; 20 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/LogicArithmetic.v: -------------------------------------------------------------------------------- 1 | module LogicArithmetic(a, b, aluc, result); 2 | input [31:0]a; 3 | input [31:0]b; 4 | input [1:0]aluc; 5 | output reg [31:0]result; 6 | 7 | always @(a or b or aluc[1:0]) begin 8 | case(aluc[1:0]) 9 | 2'b00: begin 10 | result = a & b; 11 | end 12 | 2'b01: begin 13 | result = a | b; 14 | end 15 | 2'b10: begin 16 | result = a ^ b; 17 | end 18 | default: begin 19 | result = ~(a | b); 20 | end 21 | endcase 22 | end 23 | endmodule -------------------------------------------------------------------------------- /SD-DDR-Cache/CPU/LuiSlt.v: -------------------------------------------------------------------------------- 1 | module lui_32bits(b, r); 2 | input [15:0]b; 3 | output [31:0]r; 4 | 5 | assign r = {b[15:0], 16'b0}; 6 | endmodule 7 | 8 | module slt_32bits(a, b, aluc, r, is_equal, is_smaller); 9 | input [31:0]a; 10 | input [31:0]b; 11 | input aluc;//1 slt; 0 sltu 12 | output [31:0]r; 13 | output is_equal; 14 | output is_smaller; 15 | 16 | wire [32:0]ar = {1'b0, a}; 17 | wire [32:0]br = {1'b0, b}; 18 | 19 | reg [2:0]compared_result;//分别代表a-b>0 a-b=0 a-b<0 20 | always @(ar or br) begin 21 | if(ar > br) begin 22 | compared_result = 3'b100; 23 | end else if(ar == br) begin 24 | compared_result = 3'b010; 25 | end else begin 26 | compared_result = 3'b001; 27 | end 28 | end //先当无符号数比较 29 | 30 | reg r_low = 1'b0;//表示r的最低位 31 | always @(*) begin 32 | if(aluc == 1'b1) begin//slt 33 | case({a[31], b[31]}) 34 | 2'b00: begin 35 | //a+ b+ 36 | r_low = compared_result[0]; 37 | end 38 | 2'b01: begin 39 | //a+ b- 40 | r_low = 1'b0; 41 | end 42 | 2'b10: begin 43 | //a- b+ 44 | r_low = 1'b1; 45 | end 46 | 2'b11: begin 47 | //a- b- 48 | r_low = compared_result[0]; 49 | end 50 | endcase 51 | end else begin//sltu 52 | r_low = compared_result[0]; 53 | end 54 | end 55 | /*assign r[0] = ((~aluc) & compared_result[0]) 56 | | (aluc & a[31] & (~b[31])) 57 | | (aluc & (~a[31]) & (~b[31]) & compared_result[0]) 58 | | (aluc & a[31] & b[31] & compared_result[2]);*/ 59 | assign r[31:1] = 0; 60 | assign r[0] = r_low; 61 | 62 | assign is_equal = compared_result[1]; 63 | assign is_smaller = compared_result[0]; 64 | endmodule 65 | 66 | module LuiSlt(a, b, aluc, r, is_equal, is_smaller); 67 | input [31:0]a; 68 | input [31:0]b; 69 | input [1:0]aluc; 70 | output reg [31:0]r; 71 | output is_equal;//若a、b相等，则值为1；否则为0 72 | output is_smaller;//a/user_design/rtl/phy" includes the PHY layer 4 | RTL modules. 5 | - The top-level PHY module to be instantiated is ddr_phy_top (ddr_phy_top.v) 6 | - PHY modules can be used in any environment by taking the RTL modules 7 | listed in "phy" folder and PHY layer needs to be connected to 8 | the memory controller. 9 | - Refer to User Guide (UG586) section "Physical Layer Interface (Non-Memory 10 | Controller Design)" for more details on PHY interface signaling, 11 | parameter(s) and timing information. 12 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/log.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/ddr2/ddr2/example_design/log.txt -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/par/example_top.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/ddr2/ddr2/example_design/par/example_top.xdc -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/par/readme.txt: -------------------------------------------------------------------------------- 1 | Files in PAR folder : 2 | 3 | * "example_top.xdc" file is the constraint file for the design. This is used 4 | by Vivado. It has clock constraints, location constraints, IO standards 5 | and false path/SLICE constraints if any. 6 | 7 | * LTX/probe file is required when programming BIT file to FPGA as it contains 8 | the information of debug signals like signal name and position with respect 9 | to ILA/VIO core. The probe file (debug_nets.ltx) is auto generated by 10 | vivado tool and is found in .runs/impl_1/debug_nets.ltx 11 | 12 | 13 | compatible_ucf folder: 14 | 15 | * MIG outputs this folder only when Pin Compatible FPGAs are checked in GUI 16 | (Pin Compatible FPGAs page in GUI). It generates the XDC files for all 17 | the Compatible FPGAs selected in GUI. If you want to switch to any of the 18 | Compatible FPGAs follow the steps mentioned below. 19 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/rtl/traffic_gen/mig_7series_v4_1_data_prbs_gen.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: data_prbs_gen.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $ 56 | // \ \ / \ Date Created: Fri Sep 01 2006 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module is used LFSR to generate random data for memory 62 | // data write or memory data read comparison.The first data is 63 | // seeded by the input prbs_seed_i which is connected to memory address. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1ps/1ps 69 | 70 | module mig_7series_v4_1_data_prbs_gen # 71 | ( 72 | parameter TCQ = 100, 73 | 74 | parameter EYE_TEST = "FALSE", 75 | parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" 76 | parameter SEED_WIDTH = 32 77 | ) 78 | ( 79 | input clk_i, 80 | input clk_en, 81 | input rst_i, 82 | input prbs_seed_init, // when high the prbs_x_seed will be loaded 83 | input [PRBS_WIDTH - 1:0] prbs_seed_i, 84 | 85 | output [PRBS_WIDTH - 1:0] prbs_o // generated address 86 | ); 87 | 88 | reg [PRBS_WIDTH - 1 :0] prbs; 89 | reg [PRBS_WIDTH :1] lfsr_q; 90 | integer i; 91 | 92 | 93 | 94 | always @ (posedge clk_i) 95 | begin 96 | if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up 97 | // if (rst_i ) //reset it to a known good state to prevent it locks up 98 | 99 | begin 100 | lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5; 101 | // lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 102 | 103 | lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ; 104 | end 105 | else if (clk_en) begin 106 | 107 | lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; 108 | lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; 109 | lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; 110 | lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; 111 | 112 | lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; 113 | lfsr_q[2] <= #TCQ lfsr_q[1] ; 114 | lfsr_q[1] <= #TCQ lfsr_q[32]; 115 | 116 | 117 | end 118 | end 119 | 120 | always @ (lfsr_q[PRBS_WIDTH:1]) begin 121 | prbs = lfsr_q[PRBS_WIDTH:1]; 122 | end 123 | 124 | assign prbs_o = prbs; 125 | 126 | endmodule 127 | 128 | 129 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/rtl/traffic_gen/mig_7series_v4_1_tg_status.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version: %version 53 | // \ \ Application: MIG 54 | // / / Filename: tg_status.v 55 | // /___/ /\ Date Last Modified: 56 | // \ \ / \ Date Created: 57 | // \___\/\___\ 58 | // 59 | //Device: Spartan6 60 | //Design Name: DDR/DDR2/DDR3/LPDDR 61 | //Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. 62 | // Error signal will be asserted if the comparsion is not equal. 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | 67 | `timescale 1ps/1ps 68 | 69 | 70 | module mig_7series_v4_1_tg_status #( 71 | parameter TCQ = 100, 72 | 73 | parameter DWIDTH = 32 74 | ) 75 | ( 76 | 77 | 78 | input clk_i , 79 | input rst_i , 80 | input manual_clear_error, 81 | input data_error_i , 82 | input [DWIDTH-1:0] cmp_data_i, 83 | input [DWIDTH-1:0] rd_data_i , 84 | input [31:0] cmp_addr_i , 85 | input [5:0] cmp_bl_i , 86 | input mcb_cmd_full_i , 87 | input mcb_wr_full_i, 88 | input mcb_rd_empty_i, 89 | output reg [64 + (2*DWIDTH - 1):0] error_status, 90 | output error 91 | ); 92 | 93 | reg data_error_r; 94 | reg error_set; 95 | assign error = error_set; 96 | 97 | always @ (posedge clk_i) 98 | data_error_r <= #TCQ data_error_i; 99 | 100 | always @ (posedge clk_i) 101 | begin 102 | 103 | if (rst_i || manual_clear_error) begin 104 | error_status <= #TCQ 'b0; 105 | error_set <= #TCQ 1'b0; 106 | end 107 | else begin 108 | // latch the first error only 109 | if (data_error_i && ~data_error_r && ~error_set ) begin 110 | error_status[31:0] <= #TCQ cmp_addr_i; 111 | error_status[37:32] <= #TCQ cmp_bl_i; 112 | error_status[40] <= #TCQ mcb_cmd_full_i; 113 | error_status[41] <= #TCQ mcb_wr_full_i; 114 | error_status[42] <= #TCQ mcb_rd_empty_i; 115 | error_set <= #TCQ 1'b1; 116 | error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; 117 | error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; 118 | 119 | end 120 | 121 | error_status[39:38] <= #TCQ 'b0; // reserved 122 | error_status[63:43] <= #TCQ 'b0; // reserved 123 | 124 | 125 | end end 126 | 127 | endmodule 128 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/ies_run.sh: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.1 53 | ## \ \ Application : MIG 54 | ## / / Filename : ies_run.sh 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Tue Oct 29 2013 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample ies_run.sh file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | #echo Simulation Tool: IES 71 | 72 | #Compile the required libraries here# 73 | #libraries path# 74 | 75 | #Compile all modules# 76 | ncvlog -work worklib -sv -messages mig_7series*.v > ies_sim.log 77 | ncvlog -sv -work worklib -messages ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2.v >> ies_sim.log 78 | ncvlog -sv -work worklib -messages ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2_mig_sim.v >> ies_sim.log 79 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/clocking/*.v >> ies_sim.log 80 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/controller/*.v >> ies_sim.log 81 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ecc/*.v >> ies_sim.log 82 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ip_top/*.v >> ies_sim.log 83 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/phy/*.v >> ies_sim.log 84 | ncvlog -work worklib -messages -sv ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ui/*.v >> ies_sim.log 85 | 86 | 87 | 88 | ncvlog -sv -work worklib -messages example_top.v >> ies_sim.log 89 | 90 | #Compile files in sim folder (excluding model parameter file)# 91 | #$XILINX variable must be set 92 | ncvlog -work worklib -messages $XILINX_VIVADO/data/verilog/src/glbl.v >> ies_sim.log 93 | ncvlog -work worklib -messages wiredly.v >> ies_sim.log 94 | ncvlog -work worklib -messages sim_tb_top.v >> ies_sim.log 95 | 96 | #Pass the parameters for memory model parameter file# 97 | ncvlog -work worklib -messages -sv +define+x1Gb +define+sg25E +define+x16 ddr2_model.v >> ies_sim.log 98 | 99 | #Simulate the design with sim_tb_top as the top module 100 | ncelab -namemap_mixgen -timescale '1ps/1ps' -vhdlsync -v93 -messages -nettype_port_relax -access +rwc sim_tb_top glbl >> ies_sim.log 101 | ncsim sim_tb_top >> ies_sim.log 102 | #echo done 103 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/sim.do: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.1 53 | ## \ \ Application : MIG 54 | ## / / Filename : sim.do 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Fri Oct 14 2011 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample sim .do file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | vlib work 71 | 72 | #Map the required libraries here# 73 | #vmap unisims_ver 74 | #vmap unisim 75 | #vmap secureip 76 | 77 | #Compile all modules# 78 | vlog -incr mig_7series*.v 79 | vlog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2.v 80 | vlog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2_mig_sim.v 81 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/clocking/*.v 82 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/controller/*.v 83 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ecc/*.v 84 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ip_top/*.v 85 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/phy/*.v 86 | vlog -incr ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ui/*.v 87 | 88 | 89 | 90 | vlog example_top.v 91 | 92 | #Compile files in sim folder (excluding model parameter file)# 93 | #$XILINX variable must be set 94 | vlog -incr $env(XILINX_VIVADO)/data/verilog/src/glbl.v 95 | vlog wiredly.v 96 | vlog sim_tb_top.v 97 | 98 | #Pass the parameters for memory model parameter file# 99 | vlog -incr +define+x1Gb +define+sg25E +define+x16 ddr2_model.v 100 | 101 | #Load the design. Use required libraries.# 102 | vsim -t fs -novopt +notimingchecks -L unisims_ver -L secureip work.sim_tb_top glbl 103 | 104 | onerror {resume} 105 | #Log all the objects in design. These will appear in .wlf file# 106 | #This helps in viewing all signals of the design instead of 107 | #re-running the simulation for viewing the signals. 108 | #Uncomment below line to log all objects in the design. 109 | #log -r /* 110 | 111 | #View sim_tb_top signals in waveform# 112 | add wave sim:/sim_tb_top/* 113 | #Change radix to Hexadecimal# 114 | radix hex 115 | #Supress Numeric Std package and Arith package warnings.# 116 | #For VHDL designs we get some warnings due to unknown values on some signals at startup# 117 | # ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# 118 | #We may also get some Arithmetic packeage warnings because of unknown values on# 119 | #some of the signals that are used in an Arithmetic operation.# 120 | #In order to suppress these warnings, we use following two commands# 121 | set NumericStdNoWarnings 1 122 | set StdArithNoWarnings 1 123 | 124 | # Choose simulation run time by inserting a breakpoint and then run for specified # 125 | # period. For more details, refer to user guide (UG586).# 126 | # Status reporting logic exists both in simulation test bench (sim_tb_top) 127 | # and sim.do file for ModelSim. Any update in simulation run time or time out 128 | # in this file need to be updated in sim_tb_top file as well. 129 | when {/sim_tb_top/init_calib_complete = 1} { 130 | if {[when -label a_100] == ""} { 131 | when -label a_100 { $now = 50 us } { 132 | nowhen a_100 133 | report simulator control 134 | report simulator state 135 | if {[examine /sim_tb_top/tg_compare_error] == 0} { 136 | echo "TEST PASSED" 137 | stop 138 | } 139 | if {[examine /sim_tb_top/tg_compare_error] != 0} { 140 | echo "TEST FAILED: DATA ERROR" 141 | stop 142 | } 143 | } 144 | } 145 | } 146 | 147 | #In case calibration fails to complete, choose the run time and then stop# 148 | when {$now = @1000 us and /sim_tb_top/init_calib_complete != 1} { 149 | echo "TEST FAILED: CALIBRATION DID NOT COMPLETE" 150 | stop 151 | } 152 | 153 | run -all 154 | stop 155 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/vcs_run.sh: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2008 2009 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.1 53 | ## \ \ Application : MIG 54 | ## / / Filename : vcs_run.sh 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:17 $ 56 | ## \ \ / \ Date Created : Tue Oct 29 2013 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Purpose : 61 | ## Sample vcs_run.sh file to compile and simulate memory interface 62 | ## design and run the simulation for specified period of time. 63 | ## Display the waveforms that are listed with "add wave" command. 64 | ## Assumptions : 65 | ## Simulation takes place in \sim folder of MIG output directory. 66 | ## Reference : 67 | ## Revision History : 68 | ############################################################################### 69 | 70 | #echo Simulation Tool: VCS 71 | #Compile the required libraries here# 72 | #libraries path# 73 | 74 | #Compile all modules# 75 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2.v > vcs_sim.log 76 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ddr2_mig_sim.v >> vcs_sim.log 77 | vlogan -sverilog mig_7series*.v >> vcs_sim.log 78 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/clocking/*.v >> vcs_sim.log 79 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/controller/*.v >> vcs_sim.log 80 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ecc/*.v >> vcs_sim.log 81 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ip_top/*.v >> vcs_sim.log 82 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/phy/*.v >> vcs_sim.log 83 | vlogan -sverilog ../ddr2_ex.srcs/sources_1/ip/ddr2/ddr2/user_design/rtl/ui/*.v >> vcs_sim.log 84 | 85 | 86 | 87 | 88 | vlogan -sverilog example_top.v >> vcs_sim.log 89 | 90 | #Compile files in sim folder (excluding model parameter file)# 91 | #$XILINX variable must be set 92 | vlogan $XILINX_VIVADO/data/verilog/src/glbl.v >> vcs_sim.log 93 | vlogan -sverilog wiredly.v >> vcs_sim.log 94 | vlogan -sverilog sim_tb_top.v >> vcs_sim.log 95 | 96 | #Pass the parameters for memory model parameter file# 97 | vlogan -Xcheck_p1800_2009=char -sverilog +define+x1Gb +define+sg25E +define+x16 ddr2_model.v >> vcs_sim.log 98 | 99 | #Simulate the design with sim_tb_top as the top module 100 | vcs -R -debug_pp -lca sim_tb_top glbl >> vcs_sim.log 101 | 102 | #echo done 103 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/wiredly.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : 4.1 53 | // \ \ Application : MIG 54 | // / / Filename : wiredly.v 55 | // /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $ 56 | // \ \ / \ Date Created : Fri Oct 14 2011 57 | // \___\/\___\ 58 | // 59 | // Device : 7Series 60 | // Design Name : DDR2 SDRAM 61 | // Purpose : 62 | // This module provide the definition of a zero ohm component (A, B). 63 | // 64 | // The applications of this component include: 65 | // . Normal operation of a jumper wire (data flowing in both directions) 66 | // This can corrupt data from DRAM to FPGA useful for verifying ECC function. 67 | // 68 | // The component consists of 2 ports: 69 | // . Port A: One side of the pass-through switch 70 | // . Port B: The other side of the pass-through switch 71 | 72 | // The model is sensitive to transactions on all ports. Once a transaction 73 | // is detected, all other transactions are ignored for that simulation time 74 | // (i.e. further transactions in that delta time are ignored). 75 | 76 | // Model Limitations and Restrictions: 77 | // Signals asserted on the ports of the error injector should not have 78 | // transactions occuring in multiple delta times because the model 79 | // is sensitive to transactions on port A, B ONLY ONCE during 80 | // a simulation time. Thus, once fired, a process will 81 | // not refire if there are multiple transactions occuring in delta times. 82 | // This condition may occur in gate level simulations with 83 | // ZERO delays because transactions may occur in multiple delta times. 84 | // 85 | // Reference : 86 | // Revision History : 87 | //***************************************************************************** 88 | 89 | `timescale 1ns / 1ps 90 | 91 | module WireDelay # ( 92 | parameter Delay_g = 0, 93 | parameter Delay_rd = 0, 94 | parameter ERR_INSERT = "OFF" 95 | ) 96 | ( 97 | inout A, 98 | inout B, 99 | input reset, 100 | input phy_init_done 101 | ); 102 | 103 | reg A_r; 104 | reg B_r; 105 | reg B_inv ; 106 | reg line_en; 107 | 108 | reg B_nonX; 109 | 110 | assign A = A_r; 111 | assign B = B_r; 112 | 113 | always @ (*) 114 | begin 115 | if (B === 1'bx) 116 | B_nonX <= $random; 117 | else 118 | B_nonX <= B; 119 | end 120 | 121 | always@(*) 122 | begin 123 | if((B_nonX == 'b1) || (B_nonX == 'b0)) 124 | B_inv <= #0 ~B_nonX ; 125 | else 126 | B_inv <= #0 'bz ; 127 | end 128 | 129 | always @(*) begin 130 | if (!reset) begin 131 | A_r <= 1'bz; 132 | B_r <= 1'bz; 133 | line_en <= 1'b0; 134 | end else begin 135 | if (line_en) begin 136 | B_r <= 1'bz; 137 | if ((ERR_INSERT == "ON") & (phy_init_done)) 138 | A_r <= #Delay_rd B_inv; 139 | else 140 | A_r <= #Delay_rd B_nonX; 141 | end else begin 142 | B_r <= #Delay_g A; 143 | A_r <= 1'bz; 144 | end 145 | end 146 | end 147 | 148 | always @(A or B) begin 149 | if (!reset) begin 150 | line_en <= 1'b0; 151 | end else if (A !== A_r) begin 152 | line_en <= 1'b0; 153 | end else if (B_r !== B) begin 154 | line_en <= 1'b1; 155 | end else begin 156 | line_en <= line_en; 157 | end 158 | end 159 | endmodule 160 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/xsim_options.tcl: -------------------------------------------------------------------------------- 1 | ############################################################################### 2 | ## (c) Copyright 2012 Xilinx, Inc. All rights reserved. 3 | ## 4 | ## This file contains confidential and proprietary information 5 | ## of Xilinx, Inc. and is protected under U.S. and 6 | ## international copyright and other intellectual property 7 | ## laws. 8 | ## 9 | ## DISCLAIMER 10 | ## This disclaimer is not a license and does not grant any 11 | ## rights to the materials distributed herewith. Except as 12 | ## otherwise provided in a valid license issued to you by 13 | ## Xilinx, and to the maximum extent permitted by applicable 14 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | ## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | ## (2) Xilinx shall not be liable (whether in contract or tort, 20 | ## including negligence, or under any other theory of 21 | ## liability) for any loss or damage of any kind or nature 22 | ## related to, arising under or in connection with these 23 | ## materials, including for any direct, or any indirect, 24 | ## special, incidental, or consequential loss or damage 25 | ## (including loss of data, profits, goodwill, or any type of 26 | ## loss or damage suffered as a result of any action brought 27 | ## by a third party) even if such damage or loss was 28 | ## reasonably foreseeable or Xilinx had been advised of the 29 | ## possibility of the same. 30 | ## 31 | ## CRITICAL APPLICATIONS 32 | ## Xilinx products are not designed or intended to be fail- 33 | ## safe, or for use in any application requiring fail-safe 34 | ## performance, such as life-support or safety devices or 35 | ## systems, Class III medical devices, nuclear facilities, 36 | ## applications related to the deployment of airbags, or any 37 | ## other applications that could lead to death, personal 38 | ## injury, or severe property or environmental damage 39 | ## (individually and collectively, "Critical 40 | ## Applications"). Customer assumes the sole risk and 41 | ## liability of any use of Xilinx products in Critical 42 | ## Applications, subject only to applicable laws and 43 | ## regulations governing limitations on product liability. 44 | ## 45 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | ## PART OF THIS FILE AT ALL TIMES. 47 | ## 48 | ############################################################################### 49 | ## ____ ____ 50 | ## / /\/ / 51 | ## /___/ \ / Vendor : Xilinx 52 | ## \ \ \/ Version : 4.1 53 | ## \ \ Application : MIG 54 | ## / / Filename : xsim_options.tcl 55 | ## /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 56 | ## \ \ / \ Date Created : Tue Jun 05 2012 57 | ## \___\/\___\ 58 | ## 59 | ## Device : 7 Series 60 | ## Design Name : DDR2 SDRAM 61 | ## Purpose : To give commands to XSIM Simulator through batch mode 62 | ## Assumptions: 63 | ## - Simulation takes place in \sim folder of MIG output directory 64 | ## Reference : 65 | ## Revision History: 66 | ############################################################################### 67 | 68 | 69 | add_wave -radix hex /sim_tb_top 70 | run 1000 us 71 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/example_design/sim/xsim_run.bat: -------------------------------------------------------------------------------- 1 | ::!/bin/csh -f 2 | ::***************************************************************************** 3 | :: (c) Copyright 2012 Xilinx, Inc. All rights reserved. 4 | :: 5 | :: This file contains confidential and proprietary information 6 | :: of Xilinx, Inc. and is protected under U.S. and 7 | :: international copyright and other intellectual property 8 | :: laws. 9 | :: 10 | :: DISCLAIMER 11 | :: This disclaimer is not a license and does not grant any 12 | :: rights to the materials distributed herewith. Except as 13 | :: otherwise provided in a valid license issued to you by 14 | :: Xilinx, and to the maximum extent permitted by applicable 15 | :: law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | :: WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | :: AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | :: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | :: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | :: (2) Xilinx shall not be liable (whether in contract or tort, 21 | :: including negligence, or under any other theory of 22 | :: liability) for any loss or damage of any kind or nature 23 | :: related to, arising under or in connection with these 24 | :: materials, including for any direct, or any indirect, 25 | :: special, incidental, or consequential loss or damage 26 | :: (including loss of data, profits, goodwill, or any type of 27 | :: loss or damage suffered as a result of any action brought 28 | :: by a third party) even if such damage or loss was 29 | :: reasonably foreseeable or Xilinx had been advised of the 30 | :: possibility of the same. 31 | :: 32 | :: CRITICAL APPLICATIONS 33 | :: Xilinx products are not designed or intended to be fail- 34 | :: safe, or for use in any application requiring fail-safe 35 | :: performance, such as life-support or safety devices or 36 | :: systems, Class III medical devices, nuclear facilities, 37 | :: applications related to the deployment of airbags, or any 38 | :: other applications that could lead to death, personal 39 | :: injury, or severe property or environmental damage 40 | :: (individually and collectively, "Critical 41 | :: Applications"). Customer assumes the sole risk and 42 | :: liability of any use of Xilinx products in Critical 43 | :: Applications, subject only to applicable laws and 44 | :: regulations governing limitations on product liability. 45 | :: 46 | :: THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | :: PART OF THIS FILE AT ALL TIMES. 48 | :: 49 | :: **************************************************************************** 50 | :: ____ ____ 51 | :: / /\/ / 52 | :: /___/ \ / Vendor : Xilinx 53 | :: \ \ \/ Version : 4.1 54 | :: \ \ Application : MIG 55 | :: / / Filename : xsim_run.bat 56 | :: /___/ /\ Date Last Modified : $Date: 2011/06/02 08:31:16 $ 57 | :: \ \ / \ Date Created : Tue Jun 05 2012 58 | :: \___\/\___\ 59 | :: 60 | :: Device : 7 Series 61 | :: Design Name : DDR2 SDRAM 62 | :: Purpose : Batch file to run Simulation through Vivado Simulator 63 | :: Reference : 64 | :: Revision History : 65 | :: **************************************************************************** 66 | 67 | 68 | echo Simulation Tool: Viavdo Simulator 69 | call xelab work.sim_tb_top work.glbl -prj xsim_files.prj -L unisims_ver -L secureip -s xsim_test -debug typical 70 | xsim -g -t xsim_options.tcl -wdb xsim_database.wdb xsim_test 71 | echo done 72 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/constraints/ddr2.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/ddr2/ddr2/user_design/constraints/ddr2.xdc -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/constraints/ddr2_ooc.xdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/ddr2/ddr2/user_design/constraints/ddr2_ooc.xdc -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/log.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/ddr2/ddr2/user_design/log.txt -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/rtl/clocking/mig_7series_v4_1_clk_ibuf.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version:%version 53 | // \ \ Application: MIG 54 | // / / Filename: clk_ibuf.v 55 | // /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $ 56 | // \ \ / \ Date Created:Mon Aug 3 2009 57 | // \___\/\___\ 58 | // 59 | //Device: Virtex-6 60 | //Design Name: DDR3 SDRAM 61 | //Purpose: 62 | // Clock generation/distribution and reset synchronization 63 | //Reference: 64 | //Revision History: 65 | //***************************************************************************** 66 | `timescale 1ns/1ps 67 | 68 | module mig_7series_v4_1_clk_ibuf # 69 | ( 70 | parameter SYSCLK_TYPE = "DIFFERENTIAL", 71 | // input clock type 72 | parameter DIFF_TERM_SYSCLK = "TRUE" 73 | // Differential Termination 74 | ) 75 | ( 76 | // Clock inputs 77 | input sys_clk_p, // System clock diff input 78 | input sys_clk_n, 79 | input sys_clk_i, 80 | output mmcm_clk 81 | ); 82 | 83 | (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */; 84 | 85 | generate 86 | if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk 87 | 88 | //*********************************************************************** 89 | // Differential input clock input buffers 90 | //*********************************************************************** 91 | 92 | IBUFGDS # 93 | ( 94 | .DIFF_TERM (DIFF_TERM_SYSCLK), 95 | .IBUF_LOW_PWR ("FALSE") 96 | ) 97 | u_ibufg_sys_clk 98 | ( 99 | .I (sys_clk_p), 100 | .IB (sys_clk_n), 101 | .O (sys_clk_ibufg) 102 | ); 103 | 104 | end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk 105 | 106 | //*********************************************************************** 107 | // SINGLE_ENDED input clock input buffers 108 | //*********************************************************************** 109 | 110 | IBUFG # 111 | ( 112 | .IBUF_LOW_PWR ("FALSE") 113 | ) 114 | u_ibufg_sys_clk 115 | ( 116 | .I (sys_clk_i), 117 | .O (sys_clk_ibufg) 118 | ); 119 | end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk 120 | 121 | //*********************************************************************** 122 | // System clock is driven from FPGA internal clock (clock from fabric) 123 | //*********************************************************************** 124 | assign sys_clk_ibufg = sys_clk_i; 125 | end 126 | endgenerate 127 | 128 | assign mmcm_clk = sys_clk_ibufg; 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/rtl/ecc/mig_7series_v4_1_ecc_merge_enc.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor : Xilinx 52 | // \ \ \/ Version : %version 53 | // \ \ Application : MIG 54 | // / / Filename : ecc_merge_enc.v 55 | // /___/ /\ Date Last Modified : $date$ 56 | // \ \ / \ Date Created : Tue Jun 30 2009 57 | // \___\/\___\ 58 | // 59 | //Device : 7-Series 60 | //Design Name : DDR3 SDRAM 61 | //Purpose : 62 | //Reference : 63 | //Revision History : 64 | //***************************************************************************** 65 | 66 | `timescale 1ps/1ps 67 | 68 | module mig_7series_v4_1_ecc_merge_enc 69 | #( 70 | parameter TCQ = 100, 71 | parameter PAYLOAD_WIDTH = 64, 72 | parameter CODE_WIDTH = 72, 73 | parameter DATA_BUF_ADDR_WIDTH = 4, 74 | parameter DATA_BUF_OFFSET_WIDTH = 1, 75 | parameter DATA_WIDTH = 64, 76 | parameter DQ_WIDTH = 72, 77 | parameter ECC_WIDTH = 8, 78 | parameter nCK_PER_CLK = 4 79 | ) 80 | ( 81 | /*AUTOARG*/ 82 | // Outputs 83 | mc_wrdata, mc_wrdata_mask, 84 | // Inputs 85 | clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc 86 | ); 87 | 88 | input clk; 89 | input rst; 90 | 91 | input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data; 92 | input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask; 93 | input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data; 94 | 95 | reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r; 96 | reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r; 97 | reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r; 98 | 99 | always @(posedge clk) wr_data_r <= #TCQ wr_data; 100 | always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask; 101 | always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data; 102 | 103 | // Merge new data with memory read data. 104 | wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data; 105 | genvar h; 106 | genvar i; 107 | generate 108 | for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer 109 | for (i=0; i DATA_WIDTH) 116 | assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]= 117 | wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]; 118 | 119 | end 120 | endgenerate 121 | 122 | // Generate ECC and overlay onto mc_wrdata. 123 | input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows; 124 | input [2*nCK_PER_CLK-1:0] raw_not_ecc; 125 | reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r; 126 | always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc; 127 | output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata; 128 | reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c; 129 | genvar j; 130 | integer k; 131 | generate 132 | for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word 133 | always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin 134 | mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] = 135 | {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}}, 136 | merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]}; 137 | for (k=0; k tap ? tap + TAPSPERKCLK[TAPCNTRWIDTH-1:0] - run 89 | : tap - run; 90 | 91 | wire run_end_this = run_end && select0 && select1; 92 | 93 | reg [TAPCNTRWIDTH-1:0] fall_lead_r, fall_trail_r, rise_lead_r, rise_trail_r; 94 | output [TAPCNTRWIDTH-1:0] fall_lead, fall_trail, rise_lead, rise_trail; 95 | assign fall_lead = fall_lead_r; 96 | assign fall_trail = fall_trail_r; 97 | assign rise_lead = rise_lead_r; 98 | assign rise_trail = rise_trail_r; 99 | 100 | wire [TAPCNTRWIDTH-1:0] fall_lead_ns = run_end_this & run_polarity ? tap : fall_lead_r; 101 | wire [TAPCNTRWIDTH-1:0] rise_trail_ns = run_end_this & run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] 102 | : rise_trail_r; 103 | wire [TAPCNTRWIDTH-1:0] rise_lead_ns = run_end_this & ~run_polarity ? tap : rise_lead_r; 104 | wire [TAPCNTRWIDTH-1:0] fall_trail_ns = run_end_this & ~run_polarity ? trailing_edge[TAPCNTRWIDTH-1:0] 105 | : fall_trail_r; 106 | 107 | always @(posedge clk) fall_lead_r <= #TCQ fall_lead_ns; 108 | always @(posedge clk) fall_trail_r <= #TCQ fall_trail_ns; 109 | always @(posedge clk) rise_lead_r <= #TCQ rise_lead_ns; 110 | always @(posedge clk) rise_trail_r <= #TCQ rise_trail_ns; 111 | 112 | endmodule // mig_7series_v4_1_poc_edge_store 113 | 114 | // Local Variables: 115 | // verilog-library-directories:(".") 116 | // verilog-library-extensions:(".v") 117 | // End: 118 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2/user_design/rtl/phy/mig_7series_v4_1_poc_pd.v: -------------------------------------------------------------------------------- 1 | //***************************************************************************** 2 | // (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved. 3 | // 4 | // This file contains confidential and proprietary information 5 | // of Xilinx, Inc. and is protected under U.S. and 6 | // international copyright and other intellectual property 7 | // laws. 8 | // 9 | // DISCLAIMER 10 | // This disclaimer is not a license and does not grant any 11 | // rights to the materials distributed herewith. Except as 12 | // otherwise provided in a valid license issued to you by 13 | // Xilinx, and to the maximum extent permitted by applicable 14 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 15 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 16 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 17 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 18 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 19 | // (2) Xilinx shall not be liable (whether in contract or tort, 20 | // including negligence, or under any other theory of 21 | // liability) for any loss or damage of any kind or nature 22 | // related to, arising under or in connection with these 23 | // materials, including for any direct, or any indirect, 24 | // special, incidental, or consequential loss or damage 25 | // (including loss of data, profits, goodwill, or any type of 26 | // loss or damage suffered as a result of any action brought 27 | // by a third party) even if such damage or loss was 28 | // reasonably foreseeable or Xilinx had been advised of the 29 | // possibility of the same. 30 | // 31 | // CRITICAL APPLICATIONS 32 | // Xilinx products are not designed or intended to be fail- 33 | // safe, or for use in any application requiring fail-safe 34 | // performance, such as life-support or safety devices or 35 | // systems, Class III medical devices, nuclear facilities, 36 | // applications related to the deployment of airbags, or any 37 | // other applications that could lead to death, personal 38 | // injury, or severe property or environmental damage 39 | // (individually and collectively, "Critical 40 | // Applications"). Customer assumes the sole risk and 41 | // liability of any use of Xilinx products in Critical 42 | // Applications, subject only to applicable laws and 43 | // regulations governing limitations on product liability. 44 | // 45 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 46 | // PART OF THIS FILE AT ALL TIMES. 47 | // 48 | //***************************************************************************** 49 | // ____ ____ 50 | // / /\/ / 51 | // /___/ \ / Vendor: Xilinx 52 | // \ \ \/ Version:%version 53 | // \ \ Application: MIG 54 | // / / Filename: mig_7series_v4_1_poc_pd.v 55 | // /___/ /\ Date Last Modified: $$ 56 | // \ \ / \ Date Created:Tue 15 Jan 2014 57 | // \___\/\___\ 58 | // 59 | //Device: Virtex-7 60 | //Design Name: DDR3 SDRAM 61 | //Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff 62 | // prevents any noise that could happen when the phase shift clock is very 63 | // nearly aligned to the fabric clock. 64 | //Reference: 65 | //Revision History: 66 | //***************************************************************************** 67 | 68 | `timescale 1 ps / 1 ps 69 | 70 | module mig_7series_v4_1_poc_pd # 71 | (parameter POC_USE_METASTABLE_SAMP = "FALSE", 72 | parameter SIM_CAL_OPTION = "NONE", 73 | parameter TCQ = 100) 74 | (/*AUTOARG*/ 75 | // Outputs 76 | pd_out, 77 | // Inputs 78 | iddr_rst, clk, kclk, mmcm_ps_clk 79 | ); 80 | 81 | input iddr_rst; 82 | input clk; 83 | input kclk; 84 | input mmcm_ps_clk; 85 | 86 | wire q1; 87 | IDDR # 88 | (.DDR_CLK_EDGE ("OPPOSITE_EDGE"), 89 | .INIT_Q1 (1'b0), 90 | .INIT_Q2 (1'b0), 91 | .SRTYPE ("SYNC")) 92 | u_phase_detector 93 | (.Q1 (q1), 94 | .Q2 (), 95 | .C (mmcm_ps_clk), 96 | .CE (1'b1), 97 | .D (kclk), 98 | .R (iddr_rst), 99 | .S (1'b0)); 100 | 101 | // Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME 102 | 103 | reg pos_edge_samp; 104 | 105 | generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes 106 | always @(posedge clk) pos_edge_samp <= #TCQ q1; 107 | end else begin : eXes 108 | reg q1_delayed; 109 | reg rising_clk_seen; 110 | always @(posedge mmcm_ps_clk) begin 111 | rising_clk_seen <= 1'b0; 112 | q1_delayed <= 1'bx; 113 | end 114 | always @(posedge clk) begin 115 | rising_clk_seen = 1'b1; 116 | if (rising_clk_seen) q1_delayed <= q1; 117 | end 118 | always @(posedge clk) begin 119 | pos_edge_samp <= q1_delayed; 120 | end 121 | end endgenerate 122 | 123 | reg pd_out_r; 124 | always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp; 125 | 126 | output pd_out; 127 | assign pd_out = pd_out_r; 128 | 129 | 130 | endmodule // mic_7series_v4_0_poc_pd 131 | 132 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | // Date : Sun Dec 23 17:23:22 2018 5 | // Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub d:/Git/CPU/project_6/project_6.srcs/sources_1/ip/ddr2/ddr2_stub.v 7 | // Design : ddr2 8 | // Purpose : Stub declaration of top-level module interface 9 | // Device : xc7a100tcsg324-1 10 | // -------------------------------------------------------------------------------- 11 | 12 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 13 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 14 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 15 | module ddr2(ddr2_dq, ddr2_dqs_n, ddr2_dqs_p, ddr2_addr, 16 | ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_ck_p, ddr2_ck_n, ddr2_cke, ddr2_cs_n, ddr2_dm, 17 | ddr2_odt, sys_clk_i, clk_ref_i, app_addr, app_cmd, app_en, app_wdf_data, app_wdf_end, 18 | app_wdf_mask, app_wdf_wren, app_rd_data, app_rd_data_end, app_rd_data_valid, app_rdy, 19 | app_wdf_rdy, app_sr_req, app_ref_req, app_zq_req, app_sr_active, app_ref_ack, app_zq_ack, 20 | ui_clk, ui_clk_sync_rst, init_calib_complete, sys_rst) 21 | /* synthesis syn_black_box black_box_pad_pin="ddr2_dq[15:0],ddr2_dqs_n[1:0],ddr2_dqs_p[1:0],ddr2_addr[12:0],ddr2_ba[2:0],ddr2_ras_n,ddr2_cas_n,ddr2_we_n,ddr2_ck_p[0:0],ddr2_ck_n[0:0],ddr2_cke[0:0],ddr2_cs_n[0:0],ddr2_dm[1:0],ddr2_odt[0:0],sys_clk_i,clk_ref_i,app_addr[26:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,sys_rst" */; 22 | inout [15:0]ddr2_dq; 23 | inout [1:0]ddr2_dqs_n; 24 | inout [1:0]ddr2_dqs_p; 25 | output [12:0]ddr2_addr; 26 | output [2:0]ddr2_ba; 27 | output ddr2_ras_n; 28 | output ddr2_cas_n; 29 | output ddr2_we_n; 30 | output [0:0]ddr2_ck_p; 31 | output [0:0]ddr2_ck_n; 32 | output [0:0]ddr2_cke; 33 | output [0:0]ddr2_cs_n; 34 | output [1:0]ddr2_dm; 35 | output [0:0]ddr2_odt; 36 | input sys_clk_i; 37 | input clk_ref_i; 38 | input [26:0]app_addr; 39 | input [2:0]app_cmd; 40 | input app_en; 41 | input [127:0]app_wdf_data; 42 | input app_wdf_end; 43 | input [15:0]app_wdf_mask; 44 | input app_wdf_wren; 45 | output [127:0]app_rd_data; 46 | output app_rd_data_end; 47 | output app_rd_data_valid; 48 | output app_rdy; 49 | output app_wdf_rdy; 50 | input app_sr_req; 51 | input app_ref_req; 52 | input app_zq_req; 53 | output app_sr_active; 54 | output app_ref_ack; 55 | output app_zq_ack; 56 | output ui_clk; 57 | output ui_clk_sync_rst; 58 | output init_calib_complete; 59 | input sys_rst; 60 | endmodule 61 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/ddr2_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | -- Date : Sun Dec 23 17:23:22 2018 5 | -- Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub d:/Git/CPU/project_6/project_6.srcs/sources_1/ip/ddr2/ddr2_stub.vhdl 7 | -- Design : ddr2 8 | -- Purpose : Stub declaration of top-level module interface 9 | -- Device : xc7a100tcsg324-1 10 | -- -------------------------------------------------------------------------------- 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | 14 | entity ddr2 is 15 | Port ( 16 | ddr2_dq : inout STD_LOGIC_VECTOR ( 15 downto 0 ); 17 | ddr2_dqs_n : inout STD_LOGIC_VECTOR ( 1 downto 0 ); 18 | ddr2_dqs_p : inout STD_LOGIC_VECTOR ( 1 downto 0 ); 19 | ddr2_addr : out STD_LOGIC_VECTOR ( 12 downto 0 ); 20 | ddr2_ba : out STD_LOGIC_VECTOR ( 2 downto 0 ); 21 | ddr2_ras_n : out STD_LOGIC; 22 | ddr2_cas_n : out STD_LOGIC; 23 | ddr2_we_n : out STD_LOGIC; 24 | ddr2_ck_p : out STD_LOGIC_VECTOR ( 0 to 0 ); 25 | ddr2_ck_n : out STD_LOGIC_VECTOR ( 0 to 0 ); 26 | ddr2_cke : out STD_LOGIC_VECTOR ( 0 to 0 ); 27 | ddr2_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 ); 28 | ddr2_dm : out STD_LOGIC_VECTOR ( 1 downto 0 ); 29 | ddr2_odt : out STD_LOGIC_VECTOR ( 0 to 0 ); 30 | sys_clk_i : in STD_LOGIC; 31 | clk_ref_i : in STD_LOGIC; 32 | app_addr : in STD_LOGIC_VECTOR ( 26 downto 0 ); 33 | app_cmd : in STD_LOGIC_VECTOR ( 2 downto 0 ); 34 | app_en : in STD_LOGIC; 35 | app_wdf_data : in STD_LOGIC_VECTOR ( 127 downto 0 ); 36 | app_wdf_end : in STD_LOGIC; 37 | app_wdf_mask : in STD_LOGIC_VECTOR ( 15 downto 0 ); 38 | app_wdf_wren : in STD_LOGIC; 39 | app_rd_data : out STD_LOGIC_VECTOR ( 127 downto 0 ); 40 | app_rd_data_end : out STD_LOGIC; 41 | app_rd_data_valid : out STD_LOGIC; 42 | app_rdy : out STD_LOGIC; 43 | app_wdf_rdy : out STD_LOGIC; 44 | app_sr_req : in STD_LOGIC; 45 | app_ref_req : in STD_LOGIC; 46 | app_zq_req : in STD_LOGIC; 47 | app_sr_active : out STD_LOGIC; 48 | app_ref_ack : out STD_LOGIC; 49 | app_zq_ack : out STD_LOGIC; 50 | ui_clk : out STD_LOGIC; 51 | ui_clk_sync_rst : out STD_LOGIC; 52 | init_calib_complete : out STD_LOGIC; 53 | sys_rst : in STD_LOGIC 54 | ); 55 | 56 | end ddr2; 57 | 58 | architecture stub of ddr2 is 59 | attribute syn_black_box : boolean; 60 | attribute black_box_pad_pin : string; 61 | attribute syn_black_box of stub : architecture is true; 62 | attribute black_box_pad_pin of stub : architecture is "ddr2_dq[15:0],ddr2_dqs_n[1:0],ddr2_dqs_p[1:0],ddr2_addr[12:0],ddr2_ba[2:0],ddr2_ras_n,ddr2_cas_n,ddr2_we_n,ddr2_ck_p[0:0],ddr2_ck_n[0:0],ddr2_cke[0:0],ddr2_cs_n[0:0],ddr2_dm[1:0],ddr2_odt[0:0],sys_clk_i,clk_ref_i,app_addr[26:0],app_cmd[2:0],app_en,app_wdf_data[127:0],app_wdf_end,app_wdf_mask[15:0],app_wdf_wren,app_rd_data[127:0],app_rd_data_end,app_rd_data_valid,app_rdy,app_wdf_rdy,app_sr_req,app_ref_req,app_zq_req,app_sr_active,app_ref_ack,app_zq_ack,ui_clk,ui_clk_sync_rst,init_calib_complete,sys_rst"; 63 | begin 64 | end; 65 | -------------------------------------------------------------------------------- /SD-DDR-Cache/ddr2/xil_txt.in: -------------------------------------------------------------------------------- 1 | SET_FLAG MODE INTERACTIVE 2 | SET_FLAG STANDALONE_MODE TRUE 3 | SET_PREFERENCE ipi_mode no 4 | SET_PREFERENCE is_ip_locked false 5 | SET_PREFERENCE devicefamily artix7 6 | SET_PREFERENCE device xc7a100t 7 | SET_PREFERENCE speedgrade -1 8 | SET_PREFERENCE package csg324 9 | SET_PREFERENCE verilogsim true 10 | SET_PREFERENCE vhdlsim false 11 | SET_PREFERENCE designentry Verilog 12 | SET_PREFERENCE outputdirectory c:/Users/Jake/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10188-DESKTOP-M4S8FPN/coregen/mig_7series_0/_tmp/ 13 | SET_PREFERENCE subworkingdirectory c:/Users/Jake/AppData/Roaming/Xilinx/Vivado/.Xil/Vivado-10188-DESKTOP-M4S8FPN/coregen/mig_7series_0/_tmp/ 14 | SET_PREFERENCE flowvendor Other 15 | SET_PREFERENCE tool vivado 16 | SET_PARAMETER component_name mig_7series_0 17 | SET_PREFERENCE compnamestatus 1 18 | SET_PARAMETER component_name mig_7series_0 19 | SET_PARAMETER data_dir_path d:/Coding/Xilinx/Vivado/2018.2/data/ip/xilinx/mig_7series_v4_1 20 | SET_CORE_NAME Memory Interface Generator (MIG 7 Series) 21 | SET_CORE_VERSION 2.3 22 | SET_CORE_VLNV xilinx.com:ip:mig_7series:2.3 23 | SET_CORE_PATH d:/Coding/Xilinx/Vivado/2018.2/data/ip/xilinx/mig_7series_v4_1 24 | SET_CORE_DATASHEET d:/Coding/Xilinx/Vivado/2018.2/data/ip/xilinx/mig_7series_v4_1/data/docs/ds176_7series_MIS.pdf 25 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/dmem/dmem.dcp -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 50 | // IP Revision: 12 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | dmem your_instance_name ( 58 | .a(a), // input wire [10 : 0] a 59 | .d(d), // input wire [31 : 0] d 60 | .clk(clk), // input wire clk 61 | .we(we), // input wire we 62 | .spo(spo) // output wire [31 : 0] spo 63 | ); 64 | // INST_TAG_END ------ End INSTANTIATION Template --------- 65 | 66 | // You must compile the wrapper file dmem.v when simulating 67 | // the core, dmem. When compiling the wrapper file, be sure to 68 | // reference the Verilog simulation library. 69 | 70 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 50 | -- IP Revision: 12 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT dmem 56 | PORT ( 57 | a : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 58 | d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 59 | clk : IN STD_LOGIC; 60 | we : IN STD_LOGIC; 61 | spo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 62 | ); 63 | END COMPONENT; 64 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 65 | 66 | -- The following code must appear in the VHDL architecture 67 | -- body. Substitute your own instance name and net names. 68 | 69 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 70 | your_instance_name : dmem 71 | PORT MAP ( 72 | a => a, 73 | d => d, 74 | clk => clk, 75 | we => we, 76 | spo => spo 77 | ); 78 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 79 | 80 | -- You must compile the wrapper file dmem.vhd when simulating 81 | -- the core, dmem. When compiling the wrapper file, be sure to 82 | -- reference the VHDL simulation library. 83 | 84 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | ################################################################################ 50 | 51 | # Tx Core Period Constraint. This constraint can be modified, and is 52 | # valid as long as it is met after place and route. 53 | create_clock -name "TS_CLK" -period 20.0 [ get_ports clk ] 54 | 55 | 56 | ################################################################################ 57 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | // Date : Mon Dec 24 19:26:34 2018 5 | // Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub D:/Git/CPU/project_6/project_6.srcs/sources_1/ip/dmem/dmem_stub.v 7 | // Design : dmem 8 | // Purpose : Stub declaration of top-level module interface 9 | // Device : xc7a100tcsg324-1 10 | // -------------------------------------------------------------------------------- 11 | 12 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 13 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 14 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 15 | (* x_core_info = "dist_mem_gen_v8_0_12,Vivado 2018.2" *) 16 | module dmem(a, d, clk, we, spo) 17 | /* synthesis syn_black_box black_box_pad_pin="a[10:0],d[31:0],clk,we,spo[31:0]" */; 18 | input [10:0]a; 19 | input [31:0]d; 20 | input clk; 21 | input we; 22 | output [31:0]spo; 23 | endmodule 24 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/dmem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | -- Date : Mon Dec 24 19:26:34 2018 5 | -- Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub D:/Git/CPU/project_6/project_6.srcs/sources_1/ip/dmem/dmem_stub.vhdl 7 | -- Design : dmem 8 | -- Purpose : Stub declaration of top-level module interface 9 | -- Device : xc7a100tcsg324-1 10 | -- -------------------------------------------------------------------------------- 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | 14 | entity dmem is 15 | Port ( 16 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 17 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 18 | clk : in STD_LOGIC; 19 | we : in STD_LOGIC; 20 | spo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 21 | ); 22 | 23 | end dmem; 24 | 25 | architecture stub of dmem is 26 | attribute syn_black_box : boolean; 27 | attribute black_box_pad_pin : string; 28 | attribute syn_black_box of stub : architecture is true; 29 | attribute black_box_pad_pin of stub : architecture is "a[10:0],d[31:0],clk,we,spo[31:0]"; 30 | attribute x_core_info : string; 31 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_12,Vivado 2018.2"; 32 | begin 33 | end; 34 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/doc/dist_mem_gen_v8_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2018.2: 2 | * Version 8.0 (Rev. 12) 3 | * No changes 4 | 5 | 2018.1: 6 | * Version 8.0 (Rev. 12) 7 | * No changes 8 | 9 | 2017.4: 10 | * Version 8.0 (Rev. 12) 11 | * No changes 12 | 13 | 2017.3: 14 | * Version 8.0 (Rev. 12) 15 | * General: Internal device family change, no functional changes 16 | 17 | 2017.2: 18 | * Version 8.0 (Rev. 11) 19 | * No changes 20 | 21 | 2017.1: 22 | * Version 8.0 (Rev. 11) 23 | * No changes 24 | 25 | 2016.4: 26 | * Version 8.0 (Rev. 11) 27 | * No changes 28 | 29 | 2016.3: 30 | * Version 8.0 (Rev. 11) 31 | * General: Enable support for future devices 32 | 33 | 2016.2: 34 | * Version 8.0 (Rev. 10) 35 | * No changes 36 | 37 | 2016.1: 38 | * Version 8.0 (Rev. 10) 39 | * Delivering only verilog simulation model, Stopped delivery of vhdl simulation model. 40 | 41 | 2015.4.2: 42 | * Version 8.0 (Rev. 9) 43 | * No changes 44 | 45 | 2015.4.1: 46 | * Version 8.0 (Rev. 9) 47 | * No changes 48 | 49 | 2015.4: 50 | * Version 8.0 (Rev. 9) 51 | * No changes 52 | 53 | 2015.3: 54 | * Version 8.0 (Rev. 9) 55 | * Delivering only vhdl simulation model, Stopped delivery of verilog simulation model. 56 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 57 | 58 | 2015.2.1: 59 | * Version 8.0 (Rev. 8) 60 | * No changes 61 | 62 | 2015.2: 63 | * Version 8.0 (Rev. 8) 64 | * No changes 65 | 66 | 2015.1: 67 | * Version 8.0 (Rev. 8) 68 | * Delivering unencrypted simulation files. 69 | * Supported devices and production status are now determined automatically, to simplify support for future devices 70 | 71 | 2014.4.1: 72 | * Version 8.0 (Rev. 7) 73 | * No changes 74 | 75 | 2014.4: 76 | * Version 8.0 (Rev. 7) 77 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 78 | * Internal device family change, no functional changes 79 | 80 | 2014.3: 81 | * Version 8.0 (Rev. 6) 82 | * Reduced warnings in synthesis, no functional changes 83 | 84 | 2014.2: 85 | * Version 8.0 (Rev. 5) 86 | * Repackaged to improve internal automation, no functional changes. 87 | 88 | 2014.1: 89 | * Version 8.0 (Rev. 4) 90 | * Internal device family name change, no functional changes 91 | 92 | 2013.4: 93 | * Version 8.0 (Rev. 3) 94 | * Added support for Ultrascale devices 95 | 96 | 2013.3: 97 | * Version 8.0 (Rev. 2) 98 | * Enhanced support for IP Integrator 99 | * Reduced warnings in synthesis and simulation 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | 102 | 2013.2: 103 | * Version 8.0 (Rev. 1) 104 | * Repackaged to enable internal version management, no functional changes. 105 | 106 | 2013.1: 107 | * Version 8.0 108 | * Native Vivado Release 109 | * Unused port SPRA and its associated parameters removed. 110 | 111 | (c) Copyright 2002 - 2018 Xilinx, Inc. All rights reserved. 112 | 113 | This file contains confidential and proprietary information 114 | of Xilinx, Inc. and is protected under U.S. and 115 | international copyright and other intellectual property 116 | laws. 117 | 118 | DISCLAIMER 119 | This disclaimer is not a license and does not grant any 120 | rights to the materials distributed herewith. Except as 121 | otherwise provided in a valid license issued to you by 122 | Xilinx, and to the maximum extent permitted by applicable 123 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 124 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 125 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 126 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 127 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 128 | (2) Xilinx shall not be liable (whether in contract or tort, 129 | including negligence, or under any other theory of 130 | liability) for any loss or damage of any kind or nature 131 | related to, arising under or in connection with these 132 | materials, including for any direct, or any indirect, 133 | special, incidental, or consequential loss or damage 134 | (including loss of data, profits, goodwill, or any type of 135 | loss or damage suffered as a result of any action brought 136 | by a third party) even if such damage or loss was 137 | reasonably foreseeable or Xilinx had been advised of the 138 | possibility of the same. 139 | 140 | CRITICAL APPLICATIONS 141 | Xilinx products are not designed or intended to be fail- 142 | safe, or for use in any application requiring fail-safe 143 | performance, such as life-support or safety devices or 144 | systems, Class III medical devices, nuclear facilities, 145 | applications related to the deployment of airbags, or any 146 | other applications that could lead to death, personal 147 | injury, or severe property or environmental damage 148 | (individually and collectively, "Critical 149 | Applications"). Customer assumes the sole risk and 150 | liability of any use of Xilinx products in Critical 151 | Applications, subject only to applicable laws and 152 | regulations governing limitations on product liability. 153 | 154 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 155 | PART OF THIS FILE AT ALL TIMES. 156 | -------------------------------------------------------------------------------- /SD-DDR-Cache/dmem/sim/dmem.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 51 | // IP Revision: 12 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module dmem ( 57 | a, 58 | d, 59 | clk, 60 | we, 61 | spo 62 | ); 63 | 64 | input wire [10 : 0] a; 65 | input wire [31 : 0] d; 66 | input wire clk; 67 | input wire we; 68 | output wire [31 : 0] spo; 69 | 70 | dist_mem_gen_v8_0_12 #( 71 | .C_FAMILY("artix7"), 72 | .C_ADDR_WIDTH(11), 73 | .C_DEFAULT_DATA("0"), 74 | .C_DEPTH(2048), 75 | .C_HAS_CLK(1), 76 | .C_HAS_D(1), 77 | .C_HAS_DPO(0), 78 | .C_HAS_DPRA(0), 79 | .C_HAS_I_CE(0), 80 | .C_HAS_QDPO(0), 81 | .C_HAS_QDPO_CE(0), 82 | .C_HAS_QDPO_CLK(0), 83 | .C_HAS_QDPO_RST(0), 84 | .C_HAS_QDPO_SRST(0), 85 | .C_HAS_QSPO(0), 86 | .C_HAS_QSPO_CE(0), 87 | .C_HAS_QSPO_RST(0), 88 | .C_HAS_QSPO_SRST(0), 89 | .C_HAS_SPO(1), 90 | .C_HAS_WE(1), 91 | .C_MEM_INIT_FILE("no_coe_file_loaded"), 92 | .C_ELABORATION_DIR("./"), 93 | .C_MEM_TYPE(1), 94 | .C_PIPELINE_STAGES(0), 95 | .C_QCE_JOINED(0), 96 | .C_QUALIFY_WE(0), 97 | .C_READ_MIF(0), 98 | .C_REG_A_D_INPUTS(0), 99 | .C_REG_DPRA_INPUT(0), 100 | .C_SYNC_ENABLE(1), 101 | .C_WIDTH(32), 102 | .C_PARSER_TYPE(1) 103 | ) inst ( 104 | .a(a), 105 | .d(d), 106 | .dpra(11'B0), 107 | .clk(clk), 108 | .we(we), 109 | .i_ce(1'D1), 110 | .qspo_ce(1'D1), 111 | .qdpo_ce(1'D1), 112 | .qdpo_clk(1'D0), 113 | .qspo_rst(1'D0), 114 | .qdpo_rst(1'D0), 115 | .qspo_srst(1'D0), 116 | .qdpo_srst(1'D0), 117 | .spo(spo), 118 | .dpo(), 119 | .qspo(), 120 | .qdpo() 121 | ); 122 | endmodule 123 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/doc/dist_mem_gen_v8_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2018.2: 2 | * Version 8.0 (Rev. 12) 3 | * No changes 4 | 5 | 2018.1: 6 | * Version 8.0 (Rev. 12) 7 | * No changes 8 | 9 | 2017.4: 10 | * Version 8.0 (Rev. 12) 11 | * No changes 12 | 13 | 2017.3: 14 | * Version 8.0 (Rev. 12) 15 | * General: Internal device family change, no functional changes 16 | 17 | 2017.2: 18 | * Version 8.0 (Rev. 11) 19 | * No changes 20 | 21 | 2017.1: 22 | * Version 8.0 (Rev. 11) 23 | * No changes 24 | 25 | 2016.4: 26 | * Version 8.0 (Rev. 11) 27 | * No changes 28 | 29 | 2016.3: 30 | * Version 8.0 (Rev. 11) 31 | * General: Enable support for future devices 32 | 33 | 2016.2: 34 | * Version 8.0 (Rev. 10) 35 | * No changes 36 | 37 | 2016.1: 38 | * Version 8.0 (Rev. 10) 39 | * Delivering only verilog simulation model, Stopped delivery of vhdl simulation model. 40 | 41 | 2015.4.2: 42 | * Version 8.0 (Rev. 9) 43 | * No changes 44 | 45 | 2015.4.1: 46 | * Version 8.0 (Rev. 9) 47 | * No changes 48 | 49 | 2015.4: 50 | * Version 8.0 (Rev. 9) 51 | * No changes 52 | 53 | 2015.3: 54 | * Version 8.0 (Rev. 9) 55 | * Delivering only vhdl simulation model, Stopped delivery of verilog simulation model. 56 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 57 | 58 | 2015.2.1: 59 | * Version 8.0 (Rev. 8) 60 | * No changes 61 | 62 | 2015.2: 63 | * Version 8.0 (Rev. 8) 64 | * No changes 65 | 66 | 2015.1: 67 | * Version 8.0 (Rev. 8) 68 | * Delivering unencrypted simulation files. 69 | * Supported devices and production status are now determined automatically, to simplify support for future devices 70 | 71 | 2014.4.1: 72 | * Version 8.0 (Rev. 7) 73 | * No changes 74 | 75 | 2014.4: 76 | * Version 8.0 (Rev. 7) 77 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 78 | * Internal device family change, no functional changes 79 | 80 | 2014.3: 81 | * Version 8.0 (Rev. 6) 82 | * Reduced warnings in synthesis, no functional changes 83 | 84 | 2014.2: 85 | * Version 8.0 (Rev. 5) 86 | * Repackaged to improve internal automation, no functional changes. 87 | 88 | 2014.1: 89 | * Version 8.0 (Rev. 4) 90 | * Internal device family name change, no functional changes 91 | 92 | 2013.4: 93 | * Version 8.0 (Rev. 3) 94 | * Added support for Ultrascale devices 95 | 96 | 2013.3: 97 | * Version 8.0 (Rev. 2) 98 | * Enhanced support for IP Integrator 99 | * Reduced warnings in synthesis and simulation 100 | * Added support for Cadence IES and Synopsys VCS simulators 101 | 102 | 2013.2: 103 | * Version 8.0 (Rev. 1) 104 | * Repackaged to enable internal version management, no functional changes. 105 | 106 | 2013.1: 107 | * Version 8.0 108 | * Native Vivado Release 109 | * Unused port SPRA and its associated parameters removed. 110 | 111 | (c) Copyright 2002 - 2018 Xilinx, Inc. All rights reserved. 112 | 113 | This file contains confidential and proprietary information 114 | of Xilinx, Inc. and is protected under U.S. and 115 | international copyright and other intellectual property 116 | laws. 117 | 118 | DISCLAIMER 119 | This disclaimer is not a license and does not grant any 120 | rights to the materials distributed herewith. Except as 121 | otherwise provided in a valid license issued to you by 122 | Xilinx, and to the maximum extent permitted by applicable 123 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 124 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 125 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 126 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 127 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 128 | (2) Xilinx shall not be liable (whether in contract or tort, 129 | including negligence, or under any other theory of 130 | liability) for any loss or damage of any kind or nature 131 | related to, arising under or in connection with these 132 | materials, including for any direct, or any indirect, 133 | special, incidental, or consequential loss or damage 134 | (including loss of data, profits, goodwill, or any type of 135 | loss or damage suffered as a result of any action brought 136 | by a third party) even if such damage or loss was 137 | reasonably foreseeable or Xilinx had been advised of the 138 | possibility of the same. 139 | 140 | CRITICAL APPLICATIONS 141 | Xilinx products are not designed or intended to be fail- 142 | safe, or for use in any application requiring fail-safe 143 | performance, such as life-support or safety devices or 144 | systems, Class III medical devices, nuclear facilities, 145 | applications related to the deployment of airbags, or any 146 | other applications that could lead to death, personal 147 | injury, or severe property or environmental damage 148 | (individually and collectively, "Critical 149 | Applications"). Customer assumes the sole risk and 150 | liability of any use of Xilinx products in Critical 151 | Applications, subject only to applicable laws and 152 | regulations governing limitations on product liability. 153 | 154 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 155 | PART OF THIS FILE AT ALL TIMES. 156 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/0xf3cd/CPU54-Pipeline/a84261a0c7bc36d397169b48ce8bcdd208e8261a/SD-DDR-Cache/imem/imem.dcp -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem.mif: -------------------------------------------------------------------------------- 1 | 00111100000000010001000000000001 2 | 00110100001000010000000000000000 3 | 00000000000000010101000000100000 4 | 00111100000000010000000010011000 5 | 00110100001000011001011010000000 6 | 00000000000000010101100000100000 7 | 00100001011010111111111111111111 8 | 00010101011000001111111111111110 9 | 10001101010000100100000000010100 10 | 10101101010000100100000001010000 11 | 10101101010000100100000001010100 12 | 00010000010000000000000000000001 13 | 00001000000100000000000000010001 14 | 00100000000001010000000000000100 15 | 10101101010001010100000000010000 16 | 10101101010000000100000000010000 17 | 00001000000100000000000000000011 18 | 10101101010000000100000000001100 19 | 00100000000000100000000000000001 20 | 10101101010000100100000000010000 21 | 10001101010000100100000000010100 22 | 10101101010000100100000001010000 23 | 10101101010000100100000001010100 24 | 00110000010000100000000000000001 25 | 00010000010000001111111111111011 26 | 10101101010000000100000000010000 27 | 10001101010000100100000001001000 28 | 10101101010000100100000000011000 29 | 10001101010000110100000001011000 30 | 10101101010000110100000001010000 31 | 10101101010000110100000001010100 32 | 00001000000100000000000000011010 33 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem.veo: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | // IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 50 | // IP Revision: 12 51 | 52 | // The following must be inserted into your Verilog file for this 53 | // core to be instantiated. Change the instance name and port connections 54 | // (in parentheses) to your own signal names. 55 | 56 | //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG 57 | imem your_instance_name ( 58 | .a(a), // input wire [10 : 0] a 59 | .d(d), // input wire [31 : 0] d 60 | .dpra(dpra), // input wire [10 : 0] dpra 61 | .clk(clk), // input wire clk 62 | .we(we), // input wire we 63 | .dpo(dpo) // output wire [31 : 0] dpo 64 | ); 65 | // INST_TAG_END ------ End INSTANTIATION Template --------- 66 | 67 | // You must compile the wrapper file imem.v when simulating 68 | // the core, imem. When compiling the wrapper file, be sure to 69 | // reference the Verilog simulation library. 70 | 71 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem.vho: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 50 | -- IP Revision: 12 51 | 52 | -- The following code must appear in the VHDL architecture header. 53 | 54 | ------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG 55 | COMPONENT imem 56 | PORT ( 57 | a : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 58 | d : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 59 | dpra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); 60 | clk : IN STD_LOGIC; 61 | we : IN STD_LOGIC; 62 | dpo : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 63 | ); 64 | END COMPONENT; 65 | -- COMP_TAG_END ------ End COMPONENT Declaration ------------ 66 | 67 | -- The following code must appear in the VHDL architecture 68 | -- body. Substitute your own instance name and net names. 69 | 70 | ------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG 71 | your_instance_name : imem 72 | PORT MAP ( 73 | a => a, 74 | d => d, 75 | dpra => dpra, 76 | clk => clk, 77 | we => we, 78 | dpo => dpo 79 | ); 80 | -- INST_TAG_END ------ End INSTANTIATION Template --------- 81 | 82 | -- You must compile the wrapper file imem.vhd when simulating 83 | -- the core, imem. When compiling the wrapper file, be sure to 84 | -- reference the VHDL simulation library. 85 | 86 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | ################################################################################ 50 | 51 | # Tx Core Period Constraint. This constraint can be modified, and is 52 | # valid as long as it is met after place and route. 53 | create_clock -name "TS_CLK" -period 20.0 [ get_ports clk ] 54 | 55 | 56 | ################################################################################ 57 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem_stub.v: -------------------------------------------------------------------------------- 1 | // Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | // -------------------------------------------------------------------------------- 3 | // Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | // Date : Mon Dec 24 19:27:09 2018 5 | // Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | // Command : write_verilog -force -mode synth_stub D:/Git/CPU/project_6/project_6.srcs/sources_1/ip/imem/imem_stub.v 7 | // Design : imem 8 | // Purpose : Stub declaration of top-level module interface 9 | // Device : xc7a100tcsg324-1 10 | // -------------------------------------------------------------------------------- 11 | 12 | // This empty module with port declaration file causes synthesis tools to infer a black box for IP. 13 | // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. 14 | // Please paste the declaration into a Verilog source file or add the file as an additional source. 15 | (* x_core_info = "dist_mem_gen_v8_0_12,Vivado 2018.2" *) 16 | module imem(a, d, dpra, clk, we, dpo) 17 | /* synthesis syn_black_box black_box_pad_pin="a[10:0],d[31:0],dpra[10:0],clk,we,dpo[31:0]" */; 18 | input [10:0]a; 19 | input [31:0]d; 20 | input [10:0]dpra; 21 | input clk; 22 | input we; 23 | output [31:0]dpo; 24 | endmodule 25 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/imem_stub.vhdl: -------------------------------------------------------------------------------- 1 | -- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. 2 | -- -------------------------------------------------------------------------------- 3 | -- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018 4 | -- Date : Mon Dec 24 19:27:09 2018 5 | -- Host : DESKTOP-M4S8FPN running 64-bit major release (build 9200) 6 | -- Command : write_vhdl -force -mode synth_stub D:/Git/CPU/project_6/project_6.srcs/sources_1/ip/imem/imem_stub.vhdl 7 | -- Design : imem 8 | -- Purpose : Stub declaration of top-level module interface 9 | -- Device : xc7a100tcsg324-1 10 | -- -------------------------------------------------------------------------------- 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | 14 | entity imem is 15 | Port ( 16 | a : in STD_LOGIC_VECTOR ( 10 downto 0 ); 17 | d : in STD_LOGIC_VECTOR ( 31 downto 0 ); 18 | dpra : in STD_LOGIC_VECTOR ( 10 downto 0 ); 19 | clk : in STD_LOGIC; 20 | we : in STD_LOGIC; 21 | dpo : out STD_LOGIC_VECTOR ( 31 downto 0 ) 22 | ); 23 | 24 | end imem; 25 | 26 | architecture stub of imem is 27 | attribute syn_black_box : boolean; 28 | attribute black_box_pad_pin : string; 29 | attribute syn_black_box of stub : architecture is true; 30 | attribute black_box_pad_pin of stub : architecture is "a[10:0],d[31:0],dpra[10:0],clk,we,dpo[31:0]"; 31 | attribute x_core_info : string; 32 | attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0_12,Vivado 2018.2"; 33 | begin 34 | end; 35 | -------------------------------------------------------------------------------- /SD-DDR-Cache/imem/sim/imem.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2018 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: xilinx.com:ip:dist_mem_gen:8.0 51 | // IP Revision: 12 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module imem ( 57 | a, 58 | d, 59 | dpra, 60 | clk, 61 | we, 62 | dpo 63 | ); 64 | 65 | input wire [10 : 0] a; 66 | input wire [31 : 0] d; 67 | input wire [10 : 0] dpra; 68 | input wire clk; 69 | input wire we; 70 | output wire [31 : 0] dpo; 71 | 72 | dist_mem_gen_v8_0_12 #( 73 | .C_FAMILY("artix7"), 74 | .C_ADDR_WIDTH(11), 75 | .C_DEFAULT_DATA("0"), 76 | .C_DEPTH(2048), 77 | .C_HAS_CLK(1), 78 | .C_HAS_D(1), 79 | .C_HAS_DPO(1), 80 | .C_HAS_DPRA(1), 81 | .C_HAS_I_CE(0), 82 | .C_HAS_QDPO(0), 83 | .C_HAS_QDPO_CE(0), 84 | .C_HAS_QDPO_CLK(0), 85 | .C_HAS_QDPO_RST(0), 86 | .C_HAS_QDPO_SRST(0), 87 | .C_HAS_QSPO(0), 88 | .C_HAS_QSPO_CE(0), 89 | .C_HAS_QSPO_RST(0), 90 | .C_HAS_QSPO_SRST(0), 91 | .C_HAS_SPO(0), 92 | .C_HAS_WE(1), 93 | .C_MEM_INIT_FILE("imem.mif"), 94 | .C_ELABORATION_DIR("./"), 95 | .C_MEM_TYPE(4), 96 | .C_PIPELINE_STAGES(0), 97 | .C_QCE_JOINED(0), 98 | .C_QUALIFY_WE(0), 99 | .C_READ_MIF(1), 100 | .C_REG_A_D_INPUTS(0), 101 | .C_REG_DPRA_INPUT(0), 102 | .C_SYNC_ENABLE(1), 103 | .C_WIDTH(32), 104 | .C_PARSER_TYPE(1) 105 | ) inst ( 106 | .a(a), 107 | .d(d), 108 | .dpra(dpra), 109 | .clk(clk), 110 | .we(we), 111 | .i_ce(1'D1), 112 | .qspo_ce(1'D1), 113 | .qdpo_ce(1'D1), 114 | .qdpo_clk(1'D0), 115 | .qspo_rst(1'D0), 116 | .qdpo_rst(1'D0), 117 | .qspo_srst(1'D0), 118 | .qdpo_srst(1'D0), 119 | .spo(), 120 | .dpo(dpo), 121 | .qspo(), 122 | .qdpo() 123 | ); 124 | endmodule 125 | -------------------------------------------------------------------------------- /SD-DDR-Cache/写回SD测试代码.asm: -------------------------------------------------------------------------------- 1 | # DON'T USE $0 $1 2 | # $10 Keep 0x10010000 3 | addi $10, $0, 0x10010000 4 | wait_SD_init: 5 | 6 | addi $11, $0, 10000000 7 | trap: 8 | addi $11, $11, -1 9 | bne $11, $0, trap 10 | 11 | 12 | lw $2, 0x4014($10) 13 | sw $2, 0x4050($10) 14 | sw $2, 0x4054($10) 15 | 16 | beq $2, $0, nook 17 | 18 | j ok 19 | 20 | nook: 21 | #reset 22 | addi $5, $0, 0x00000004 23 | sw $5, 0x4010($10) 24 | sw $0, 0x4010($10) 25 | 26 | j wait_SD_init 27 | 28 | ok: 29 | sw $0, 0x400C($10) 30 | addi $2, $0, 1 31 | sw $2, 0x4010($10) 32 | 33 | wait_read: 34 | lw $2, 0x4014($10) 35 | sw $2, 0x4050($10) 36 | sw $2, 0x4054($10) 37 | 38 | andi $2, $2, 0x00000001 39 | beq $2, $0, wait_read 40 | 41 | # read ok 42 | sw $0, 0x4010($10) 43 | 44 | addi $2, $0, 0x12345678 45 | sw $2, 0x4050($10) 46 | sw $2, 0x4054($10) 47 | 48 | addi $2, $0, 0x00000080 # sd addr end 49 | addi $3, $0, 0 # sd addr and alse ddr2 buffer addr 50 | addi $11, $0, 1 51 | addi $12, $0, 0x00000003 52 | andi $20, $0, 0 53 | ddr2_pre: 54 | sw $3, 0x4018($10) 55 | lw $4, 0x4058($10) # 32bits from sd 56 | sw $4, 0x401C($10) # save into ddr2 data 57 | sw $3, 0x4020($10) # ddr2 write addr 58 | sw $11, 0x4024($10) 59 | sw $0, 0x4024($10) # write into ddr2 buffer 60 | 61 | andi $5, $3, 0x00000003 62 | beq $5, $12, write_into_ddr2 63 | j end_write_into_ddr2 64 | 65 | write_into_ddr2: 66 | sw $20, 0x4028($10) 67 | addi $6, $0, 2 68 | sw $6, 0x402C($10) 69 | 70 | wait_ddr2_write_end: 71 | lw $7, 0x4030($10) 72 | bne $7, $6, wait_ddr2_write_end 73 | 74 | sw $0, 0x402C($10) 75 | addi $20, $20, 1 76 | 77 | end_write_into_ddr2: 78 | addi $3, $3, 1 79 | 80 | bne $3, $2, ddr2_pre 81 | 82 | addi $2, $0, 0x23456789 83 | sw $2, 0x4050($10) 84 | sw $2, 0x4054($10) 85 | 86 | ddr2_ok: 87 | addi $22, $0, 4 88 | addi $21, $0, 1 89 | addi $20, $0, 0 # inst addr 90 | addi $2, $0, 0 # 00000 - 11111 91 | addi $23, $0, 0x20 92 | 93 | out_ddr: 94 | sw $2, 0x4028($10) 95 | addi $4, $0, 1 96 | sw $4, 0x402C($10) 97 | wait_out_ddr: 98 | lw $5, 0x4030($10) 99 | bne $5, $4, wait_out_ddr 100 | sw $0, 0x402C($10) 101 | # read ok 102 | 103 | addi $3, $0, 0 # 00 - 11 104 | 105 | write_imem: 106 | sw $3, 0x4034($10) 107 | sw $20, 0x4038($10) 108 | sw $21, 0x403C($10) 109 | sw $0, 0x403C($10) 110 | 111 | addi $20, $20, 4 112 | addi $3, $3, 1 113 | bne $3, $22, write_imem 114 | 115 | addi $2, $2, 1 116 | bne $2, $23, out_ddr 117 | 118 | nop 119 | nop 120 | nop 121 | 122 | 123 | read_SW: 124 | lw $2, 0x4048($10) 125 | lw $3, 0x404C($10) 126 | beq $3, $0, read_SW 127 | 128 | addi $4, $0, 0 129 | addi $5, $0, 128 130 | addi $6, $0, 1 131 | 132 | write_SD_buffer: 133 | sw $2, 0x4008($10) # buffer data 134 | sw $4, 0x4000($10) # buffer addr 135 | sw $6, 0x4004($10) # write ena 136 | sw $0, 0x4004($10) 137 | addi $2, $2, 1 138 | addi $4, $4, 1 139 | bne $4, $5, write_SD_buffer 140 | # write buffer end 141 | 142 | addi $2, $0, 1 143 | addi $3, $0, 2 144 | sw $2, 0x400C($10) # SD write addr 145 | sw $3, 0x4010($10) # start SD write 146 | check_SD_write_status: 147 | lw $4, 0x4014($10) 148 | and $4, $4, $3 149 | bne $4, $0, check_SD_write_status 150 | 151 | #SD Write End 152 | 153 | finish_test: 154 | addi $2, $0, 0xA1B2CDEF 155 | sw $2, 0x4050($10) 156 | sw $2, 0x4054($10) 157 | j finish_test -------------------------------------------------------------------------------- /SD-DDR-Cache/引导启动代码.asm: -------------------------------------------------------------------------------- 1 | # DON'T USE $0 $1 2 | # $10 Keep 0x10010000 3 | addi $10, $0, 0x10010000 4 | wait_SD_init: 5 | 6 | addi $11, $0, 10000000 7 | trap: 8 | addi $11, $11, -1 9 | bne $11, $0, trap 10 | 11 | 12 | lw $2, 0x4014($10) 13 | sw $2, 0x4050($10) 14 | sw $2, 0x4054($10) 15 | 16 | beq $2, $0, nook 17 | 18 | j ok 19 | 20 | nook: 21 | #reset 22 | addi $5, $0, 0x00000004 23 | sw $5, 0x4010($10) 24 | sw $0, 0x4010($10) 25 | 26 | j wait_SD_init 27 | 28 | ok: 29 | sw $0, 0x400C($10) 30 | addi $2, $0, 1 31 | sw $2, 0x4010($10) 32 | 33 | wait_read: 34 | lw $2, 0x4014($10) 35 | sw $2, 0x4050($10) 36 | sw $2, 0x4054($10) 37 | 38 | andi $2, $2, 0x00000001 39 | beq $2, $0, wait_read 40 | 41 | # read ok 42 | sw $0, 0x4010($10) 43 | 44 | addi $2, $0, 0x12345678 45 | sw $2, 0x4050($10) 46 | sw $2, 0x4054($10) 47 | 48 | addi $2, $0, 0x00000080 # sd addr end 49 | addi $3, $0, 0 # sd addr and alse ddr2 buffer addr 50 | addi $11, $0, 1 51 | addi $12, $0, 0x00000003 52 | andi $20, $0, 0 53 | ddr2_pre: 54 | sw $3, 0x4018($10) 55 | lw $4, 0x4058($10) # 32bits from sd 56 | sw $4, 0x401C($10) # save into ddr2 data 57 | sw $3, 0x4020($10) # ddr2 write addr 58 | sw $11, 0x4024($10) 59 | sw $0, 0x4024($10) # write into ddr2 buffer 60 | 61 | andi $5, $3, 0x00000003 62 | beq $5, $12, write_into_ddr2 63 | j end_write_into_ddr2 64 | 65 | write_into_ddr2: 66 | sw $20, 0x4028($10) 67 | addi $6, $0, 2 68 | sw $6, 0x402C($10) 69 | 70 | wait_ddr2_write_end: 71 | lw $7, 0x4030($10) 72 | bne $7, $6, wait_ddr2_write_end 73 | 74 | sw $0, 0x402C($10) 75 | addi $20, $20, 1 76 | 77 | end_write_into_ddr2: 78 | addi $3, $3, 1 79 | 80 | bne $3, $2, ddr2_pre 81 | 82 | addi $2, $0, 0x23456789 83 | sw $2, 0x4050($10) 84 | sw $2, 0x4054($10) 85 | 86 | ddr2_ok: 87 | addi $22, $0, 4 88 | addi $21, $0, 1 89 | addi $20, $0, 0 # inst addr 90 | addi $2, $0, 0 # 00000 - 11111 91 | addi $23, $0, 0x20 92 | 93 | out_ddr: 94 | sw $2, 0x4028($10) 95 | addi $4, $0, 1 96 | sw $4, 0x402C($10) 97 | wait_out_ddr: 98 | lw $5, 0x4030($10) 99 | bne $5, $4, wait_out_ddr 100 | sw $0, 0x402C($10) 101 | # read ok 102 | 103 | addi $3, $0, 0 # 00 - 11 104 | 105 | write_imem: 106 | sw $3, 0x4034($10) 107 | sw $20, 0x4038($10) 108 | sw $21, 0x403C($10) 109 | sw $0, 0x403C($10) 110 | 111 | addi $20, $20, 4 112 | addi $3, $3, 1 113 | bne $3, $22, write_imem 114 | 115 | addi $2, $2, 1 116 | bne $2, $23, out_ddr 117 | 118 | nop 119 | nop 120 | nop 121 | -------------------------------------------------------------------------------- /V1/7sd.xdc: -------------------------------------------------------------------------------- 1 | set_property IOSTANDARD LVCMOS33 [get_ports clk_100] 2 | set_property IOSTANDARD LVCMOS33 [get_ports reset] 3 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[7]}] 4 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[6]}] 5 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[5]}] 6 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[4]}] 7 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[3]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[2]}] 9 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[1]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {atog[0]}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[7]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[6]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[5]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[4]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[3]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[2]}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[1]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {seg_cs[0]}] 19 | set_property PACKAGE_PIN E3 [get_ports clk_100] 20 | set_property PACKAGE_PIN J15 [get_ports reset] 21 | set_property PACKAGE_PIN T10 [get_ports {atog[7]}] 22 | set_property PACKAGE_PIN R10 [get_ports {atog[6]}] 23 | set_property PACKAGE_PIN K16 [get_ports {atog[5]}] 24 | set_property PACKAGE_PIN K13 [get_ports {atog[4]}] 25 | set_property PACKAGE_PIN P15 [get_ports {atog[3]}] 26 | set_property PACKAGE_PIN T11 [get_ports {atog[2]}] 27 | set_property PACKAGE_PIN L18 [get_ports {atog[1]}] 28 | set_property PACKAGE_PIN H15 [get_ports {atog[0]}] 29 | set_property PACKAGE_PIN U13 [get_ports {seg_cs[7]}] 30 | set_property PACKAGE_PIN K2 [get_ports {seg_cs[6]}] 31 | set_property PACKAGE_PIN T14 [get_ports {seg_cs[5]}] 32 | set_property PACKAGE_PIN P14 [get_ports {seg_cs[4]}] 33 | set_property PACKAGE_PIN J14 [get_ports {seg_cs[3]}] 34 | set_property PACKAGE_PIN T9 [get_ports {seg_cs[2]}] 35 | set_property PACKAGE_PIN J18 [get_ports {seg_cs[1]}] 36 | set_property PACKAGE_PIN J17 [get_ports {seg_cs[0]}] 37 | -------------------------------------------------------------------------------- /V1/Concatenater.v: -------------------------------------------------------------------------------- 1 | //拼接器 2 | module Concatenater( 3 | input [31:28]PC, 4 | input [25:0]index, 5 | output [31:0]out_J 6 | ); 7 | assign out_J = {PC[31:28], index[25:0], 2'b0}; 8 | endmodule -------------------------------------------------------------------------------- /V1/ConfJudger.v: -------------------------------------------------------------------------------- 1 | module ConfJudger( 2 | input [31:0]if_inst, 3 | input id_rf_we, 4 | input [4:0]id_rf_waddr, 5 | input exe_rf_we, 6 | input [4:0]exe_rf_waddr, 7 | input mem_rf_we, 8 | input [4:0]mem_rf_waddr, 9 | output reg if_stop 10 | ); 11 | wire [5:0]if_op; 12 | wire [4:0]if_rs; 13 | wire [4:0]if_rt; 14 | wire [4:0]if_rd; 15 | wire [4:0]if_shamt; 16 | wire [5:0]if_func; 17 | wire [15:0]if_imm16; 18 | wire [25:0]if_index; 19 | InstructionDecoder IF_ID( 20 | .instruction(if_inst), 21 | .op(if_op), 22 | .rs(if_rs), 23 | .rt(if_rt), 24 | .rd(if_rd), 25 | .shamt(if_shamt), 26 | .func(if_func), 27 | .imm16(if_imm16), 28 | .index(if_index) 29 | ); 30 | 31 | always @(*) begin 32 | if(id_rf_we && id_rf_waddr != 5'b0) begin 33 | if(if_rs == id_rf_waddr) begin 34 | if_stop = 1'b1; 35 | end else if(if_rt == id_rf_waddr) begin 36 | if_stop = 1'b1; 37 | end else begin 38 | if_stop = 1'b0; 39 | end 40 | end else if(exe_rf_we && exe_rf_waddr != 5'b0) begin 41 | if(if_rs == exe_rf_waddr) begin 42 | if_stop = 1'b1; 43 | end else if(if_rt == exe_rf_waddr) begin 44 | if_stop = 1'b1; 45 | end else begin 46 | if_stop = 1'b0; 47 | end 48 | end else if(mem_rf_we && mem_rf_waddr != 5'b0) begin 49 | if(if_rs == mem_rf_waddr) begin 50 | if_stop = 1'b1; 51 | end else if(if_rt == mem_rf_waddr) begin 52 | if_stop = 1'b1; 53 | end else begin 54 | if_stop = 1'b0; 55 | end 56 | end else begin 57 | if_stop = 1'b0; 58 | end 59 | end 60 | endmodule -------------------------------------------------------------------------------- /V1/Extender.v: -------------------------------------------------------------------------------- 1 | module Extender( 2 | input [15:0]imm16, //SignExt16_in, ZeroExt16_in, SignExt18_in, 3 | input [4:0]shamt, //ZeroExt5_in, 4 | output [31:0]ZeroExt5_out, 5 | output [31:0]ZeroExt16_out, 6 | output [31:0]SignExt16_out, 7 | output [31:0]SignExt18_out 8 | ); 9 | assign ZeroExt5_out = {27'b0, shamt}; 10 | assign ZeroExt16_out = {16'b0, imm16}; 11 | assign SignExt16_out = {{16{imm16[15]}}, imm16}; 12 | assign SignExt18_out = {{14{imm16[15]}}, imm16, 2'b0}; 13 | endmodule -------------------------------------------------------------------------------- /V1/InstructionDecoder.v: -------------------------------------------------------------------------------- 1 | module InstructionDecoder(instruction, op, rs, rt, rd, shamt, func, imm16, index); 2 | input [31:0]instruction; 3 | output [5:0]op; 4 | output [4:0]rs; 5 | output [4:0]rt; 6 | output [4:0]rd; 7 | output [4:0]shamt; 8 | output [5:0]func; 9 | output [15:0]imm16; 10 | output [25:0]index; 11 | 12 | assign op = instruction[31:26]; 13 | assign rs = instruction[25:21]; 14 | assign rt = instruction[20:16]; 15 | assign rd = instruction[15:11]; 16 | assign shamt = instruction[10:6]; 17 | assign func = instruction[5:0]; 18 | assign imm16 = instruction[15:0]; 19 | assign index = instruction[25:0]; 20 | endmodule -------------------------------------------------------------------------------- /V1/LogicArithmetic.v: -------------------------------------------------------------------------------- 1 | module LogicArithmetic(a, b, aluc, result); 2 | input [31:0]a; 3 | input [31:0]b; 4 | input [1:0]aluc; 5 | output reg [31:0]result; 6 | 7 | always @(a or b or aluc[1:0]) begin 8 | case(aluc[1:0]) 9 | 2'b00: begin 10 | result = a & b; 11 | end 12 | 2'b01: begin 13 | result = a | b; 14 | end 15 | 2'b10: begin 16 | result = a ^ b; 17 | end 18 | default: begin 19 | result = ~(a | b); 20 | end 21 | endcase 22 | end 23 | endmodule -------------------------------------------------------------------------------- /V1/LuiSlt.v: -------------------------------------------------------------------------------- 1 | module lui_32bits(b, r); 2 | input [15:0]b; 3 | output [31:0]r; 4 | 5 | assign r = {b[15:0], 16'b0}; 6 | endmodule 7 | 8 | module slt_32bits(a, b, aluc, r, is_equal, is_smaller); 9 | input [31:0]a; 10 | input [31:0]b; 11 | input aluc;//1 slt; 0 sltu 12 | output [31:0]r; 13 | output is_equal; 14 | output is_smaller; 15 | 16 | wire [32:0]ar = {1'b0, a}; 17 | wire [32:0]br = {1'b0, b}; 18 | 19 | reg [2:0]compared_result;//分别代表a-b>0 a-b=0 a-b<0 20 | always @(ar or br) begin 21 | if(ar > br) begin 22 | compared_result = 3'b100; 23 | end else if(ar == br) begin 24 | compared_result = 3'b010; 25 | end else begin 26 | compared_result = 3'b001; 27 | end 28 | end //先当无符号数比较 29 | 30 | reg r_low = 1'b0;//表示r的最低位 31 | always @(*) begin 32 | if(aluc == 1'b1) begin//slt 33 | case({a[31], b[31]}) 34 | 2'b00: begin 35 | //a+ b+ 36 | r_low = compared_result[0]; 37 | end 38 | 2'b01: begin 39 | //a+ b- 40 | r_low = 1'b0; 41 | end 42 | 2'b10: begin 43 | //a- b+ 44 | r_low = 1'b1; 45 | end 46 | 2'b11: begin 47 | //a- b- 48 | r_low = compared_result[0]; 49 | end 50 | endcase 51 | end else begin//sltu 52 | r_low = compared_result[0]; 53 | end 54 | end 55 | /*assign r[0] = ((~aluc) & compared_result[0]) 56 | | (aluc & a[31] & (~b[31])) 57 | | (aluc & (~a[31]) & (~b[31]) & compared_result[0]) 58 | | (aluc & a[31] & b[31] & compared_result[2]);*/ 59 | assign r[31:1] = 0; 60 | assign r[0] = r_low; 61 | 62 | assign is_equal = compared_result[1]; 63 | assign is_smaller = compared_result[0]; 64 | endmodule 65 | 66 | module LuiSlt(a, b, aluc, r, is_equal, is_smaller); 67 | input [31:0]a; 68 | input [31:0]b; 69 | input [1:0]aluc; 70 | output reg [31:0]r; 71 | output is_equal;//若a、b相等，则值为1；否则为0 72 | output is_smaller;//a0 a-b=0 a-b<0 20 | always @(ar or br) begin 21 | if(ar > br) begin 22 | compared_result = 3'b100; 23 | end else if(ar == br) begin 24 | compared_result = 3'b010; 25 | end else begin 26 | compared_result = 3'b001; 27 | end 28 | end //先当无符号数比较 29 | 30 | reg r_low = 1'b0;//表示r的最低位 31 | always @(*) begin 32 | if(aluc == 1'b1) begin//slt 33 | case({a[31], b[31]}) 34 | 2'b00: begin 35 | //a+ b+ 36 | r_low = compared_result[0]; 37 | end 38 | 2'b01: begin 39 | //a+ b- 40 | r_low = 1'b0; 41 | end 42 | 2'b10: begin 43 | //a- b+ 44 | r_low = 1'b1; 45 | end 46 | 2'b11: begin 47 | //a- b- 48 | r_low = compared_result[0]; 49 | end 50 | endcase 51 | end else begin//sltu 52 | r_low = compared_result[0]; 53 | end 54 | end 55 | /*assign r[0] = ((~aluc) & compared_result[0]) 56 | | (aluc & a[31] & (~b[31])) 57 | | (aluc & (~a[31]) & (~b[31]) & compared_result[0]) 58 | | (aluc & a[31] & b[31] & compared_result[2]);*/ 59 | assign r[31:1] = 0; 60 | assign r[0] = r_low; 61 | 62 | assign is_equal = compared_result[1]; 63 | assign is_smaller = compared_result[0]; 64 | endmodule 65 | 66 | module LuiSlt(a, b, aluc, r, is_equal, is_smaller); 67 | input [31:0]a; 68 | input [31:0]b; 69 | input [1:0]aluc; 70 | output reg [31:0]r; 71 | output is_equal;//若a、b相等，则值为1；否则为0 72 | output is_smaller;//a