├── .gitignore ├── 2020NSCSCC记录.docx ├── README.md ├── design.pdf ├── rate记录.xlsx ├── src ├── PipelineMIPS-sram │ ├── EX │ │ ├── alu.v │ │ ├── branch_judge.v │ │ ├── div_radix2.v │ │ └── my_mul.v │ ├── ID │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ ├── jump_predict.v │ │ └── regfile.v │ ├── IF │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── MEM │ │ ├── cp0_reg.v │ │ ├── exception.v │ │ ├── hilo_reg.v │ │ └── mem_ctrl.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── d_cache.v │ ├── datapath.v │ ├── hazard.v │ ├── i_cache.v │ ├── main_decoder.v │ ├── mycpu_top.v │ ├── simulation │ │ ├── ohhhh.wcfg │ │ ├── soft_part │ │ │ ├── README.txt │ │ │ ├── funcTest_independent │ │ │ │ ├── ArithmeticTest │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ ├── DataMoveInstTest │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ ├── LogicInstTest │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ ├── Readme.txt │ │ │ │ ├── S_LInstTest │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ ├── ShiftInstTest │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ ├── j_BTest │ │ │ │ │ ├── Test1 │ │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ │ └── obj │ │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ │ └── test.s │ │ │ │ │ └── Test2 │ │ │ │ │ │ ├── inst_rom.S │ │ │ │ │ │ └── obj │ │ │ │ │ │ ├── axi_ram.mif │ │ │ │ │ │ ├── data_ram.coe │ │ │ │ │ │ ├── data_ram.mif │ │ │ │ │ │ ├── inst_ram.coe │ │ │ │ │ │ ├── inst_ram.mif │ │ │ │ │ │ ├── main.bin │ │ │ │ │ │ ├── main.data │ │ │ │ │ │ ├── main.elf │ │ │ │ │ │ └── test.s │ │ │ │ └── test_bench.v │ │ │ └── func_part │ │ │ │ ├── golden_trace_1.txt │ │ │ │ ├── golden_trace_2.txt │ │ │ │ ├── golden_trace_3.txt │ │ │ │ ├── obj_1 │ │ │ │ ├── axi_ram.mif │ │ │ │ ├── data_ram.coe │ │ │ │ ├── data_ram.mif │ │ │ │ ├── inst_ram.coe │ │ │ │ ├── inst_ram.mif │ │ │ │ ├── main.bin │ │ │ │ ├── main.data │ │ │ │ ├── main.elf │ │ │ │ └── test.s │ │ │ │ ├── obj_2 │ │ │ │ ├── axi_ram.mif │ │ │ │ ├── data_ram.coe │ │ │ │ ├── data_ram.mif │ │ │ │ ├── inst_ram.coe │ │ │ │ ├── inst_ram.mif │ │ │ │ ├── main.bin │ │ │ │ ├── main.data │ │ │ │ ├── main.elf │ │ │ │ └── test.s │ │ │ │ └── obj_3 │ │ │ │ ├── axi_ram.mif │ │ │ │ ├── data_ram.coe │ │ │ │ ├── data_ram.mif │ │ │ │ ├── inst_ram.coe │ │ │ │ ├── inst_ram.mif │ │ │ │ ├── main.bin │ │ │ │ ├── main.data │ │ │ │ ├── main.elf │ │ │ │ └── test.s │ │ └── test.s │ └── utils │ │ ├── aludefines.vh │ │ ├── defines.vh │ │ ├── inst_ascii_decoder.v │ │ ├── mux2.v │ │ ├── mux4.v │ │ └── mux8.v ├── PipelineMIPS │ ├── EX │ │ ├── alu.v │ │ ├── branch_judge.v │ │ ├── div_radix2.v │ │ ├── div_self_align.v │ │ └── my_mul.v │ ├── ID │ │ ├── branch_predict.v │ │ ├── imm_ext.v │ │ ├── jump_predict.v │ │ └── regfile.v │ ├── IF │ │ ├── pc_ctrl.v │ │ └── pc_reg.v │ ├── MEM │ │ ├── cp0_reg.v │ │ ├── exception.v │ │ ├── hilo_reg.v │ │ └── mem_ctrl.v │ ├── PIPE │ │ ├── ex_mem.v │ │ ├── id_ex.v │ │ ├── if_id.v │ │ └── mem_wb.v │ ├── alu_decoder.v │ ├── arbitrater.v │ ├── d_cache.v │ ├── datapath.v │ ├── hazard.v │ ├── i_cache.v │ ├── main_decoder.v │ ├── mycpu_top.v │ ├── simulation │ │ └── ohhhh.wcfg │ ├── tlb.v │ └── utils │ │ ├── LLbit.v │ │ ├── aludefines.vh │ │ ├── decoder2x4.v │ │ ├── decoder3x8.v │ │ ├── defines.vh │ │ ├── encoder4x2.v │ │ ├── inst_ascii_decoder.v │ │ ├── mux2.v │ │ ├── mux4.v │ │ └── mux8.v └── basic_pipeline │ ├── EX │ ├── alu.v │ ├── div_radix2.v │ └── my_mul.v │ ├── ID │ ├── branch_predict.v │ ├── imm_ext.v │ └── regfile.v │ ├── IF │ ├── pc_ctrl.v │ └── pc_reg.v │ ├── MEM │ ├── cp0_reg.v │ ├── exception.v │ ├── hilo_reg.v │ ├── mem_ctrl.v │ └── mem_ctrr.v │ ├── PIPE │ ├── ex_mem.v │ ├── id_ex.v │ ├── if_id.v │ └── mem_wb.v │ ├── alu_decoder.v │ ├── d_cache.v │ ├── datapath.v │ ├── hazard.v │ ├── i_cache.v │ ├── main_decoder.v │ ├── mycpu_top.v │ ├── simulation │ ├── mipstest.asm │ ├── mipstest.coe │ ├── testbench_behav.wcfg │ └── top_tb.v │ ├── soc_top.v │ └── utils │ ├── aludefines.vh │ ├── defines.vh │ ├── inst_ascii_decoder.v │ ├── mux2.v │ └── mux4.v ├── todo.txt ├── 待做.txt └── 重庆大学.pptx /.gitignore: -------------------------------------------------------------------------------- 1 | /debug.txt 2 | /lg.txt 3 | /lg.docx 4 | /log.txt -------------------------------------------------------------------------------- /2020NSCSCC记录.docx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/2020NSCSCC记录.docx -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 2020NSCSCC 2 | 3 | PipelineMIPS 4 | 5 | ## 目标 6 | 7 | 设计并实现一个流水线版的MIPS处理器，力求： 8 | 9 | 1. 模块清晰易懂，代码规范 10 | 2. 有较为完善的Cache 11 | 3. 主频达到100MHz 12 | 4. 有TLB支持，便于之后运行操作系统 13 | 14 | ## 设计 15 | 16 | 1. 指令集为MIPS32 Release1子集。初赛(57 条), 决赛(增加上学期跑PMON, linux时添加的指令) 17 | 2. 采用流水线结构（5级或7级） 18 | 3. Cache：一级cache，组相联结构，块大小为多字。 19 | 4. Cache和TLB结合：虚拟索引，物理tag 20 | 5. 分支预测模块 21 | 22 | ## 现有成果 23 | 0. 通过初赛所有测试：功能测试，记忆游戏，性能测试，系统测试；上板通过； 24 | 1. 25 | ||频率|性能得分|IPC比值| 26 | |-----|-----|-----|-----| 27 | |初赛提交版本|85MHz|48.130|| 28 | |初赛后续优化版本|100MHz|55|| 29 | |决赛提交版本(含TLB)|90MHz||28.156| 30 | 31 | 2. 启动并能够运行PMON，并成功运行移植的“猜数”小游戏。 -------------------------------------------------------------------------------- /design.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/design.pdf -------------------------------------------------------------------------------- /rate记录.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/rate记录.xlsx -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/EX/alu.v: -------------------------------------------------------------------------------- 1 | `include "aludefines.vh" 2 | 3 | module alu ( 4 | input wire clk, rst, 5 | input wire flushE, 6 | input wire [31:0] src_aE, src_bE, 7 | input wire [4:0] alu_controlE, 8 | input wire [4:0] sa, 9 | input wire [63:0] hilo, 10 | 11 | output wire div_stallE, 12 | output wire [63:0] alu_outE, 13 | output wire overflowE 14 | ); 15 | wire [63:0] alu_out_div, alu_out_mul; 16 | wire mul_sign; 17 | wire mul_valid; 18 | wire div_sign; 19 | wire div_vaild; 20 | wire ready; 21 | reg [31:0] alu_out_not_mul_div; //拓展成33位，便于判断溢出 22 | reg carry_bit; 23 | 24 | assign alu_outE = ({64{div_vaild}} & alu_out_div) 25 | | ({64{mul_valid}} & alu_out_mul) 26 | | ({64{~mul_valid & ~div_vaild}} & {32'b0, alu_out_not_mul_div}) 27 | | ({64{(alu_controlE == `ALU_MTHI)}} & {src_aE, hilo[31:0]}) 28 | | ({64{(alu_controlE == `ALU_MTLO)}} & {hilo[63:32], src_aE}); 29 | 30 | assign overflowE = (alu_controlE==`ALU_ADD || alu_controlE==`ALU_SUB) & (carry_bit ^ alu_out_not_mul_div[31]); 31 | 32 | // simple 33 | always @(*) begin 34 | carry_bit = 0; 35 | case(alu_controlE) 36 | `ALU_AND: alu_out_not_mul_div = src_aE & src_bE; 37 | `ALU_OR: alu_out_not_mul_div = src_aE | src_bE; 38 | `ALU_NOR: alu_out_not_mul_div =~(src_aE | src_bE); 39 | `ALU_XOR: alu_out_not_mul_div = src_aE ^ src_bE; 40 | 41 | `ALU_ADD: {carry_bit, alu_out_not_mul_div} = {src_aE[31], src_aE} + {src_bE[31], src_bE}; 42 | `ALU_ADDU: alu_out_not_mul_div = src_aE + src_bE; 43 | `ALU_SUB: {carry_bit, alu_out_not_mul_div} = {src_aE[31], src_aE} - {src_bE[31], src_bE}; 44 | `ALU_SUBU: alu_out_not_mul_div = src_aE - src_bE; 45 | 46 | `ALU_SLT: alu_out_not_mul_div = $signed(src_aE) < $signed(src_bE); 47 | `ALU_SLTU: alu_out_not_mul_div = src_aE < src_bE; 48 | 49 | `ALU_SLL: alu_out_not_mul_div = src_bE << src_aE[4:0]; 50 | `ALU_SRL: alu_out_not_mul_div = src_bE >> src_aE[4:0]; 51 | `ALU_SRA: alu_out_not_mul_div = $signed(src_bE) >>> src_aE[4:0]; 52 | 53 | `ALU_SLL_SA: alu_out_not_mul_div = src_bE << sa; 54 | `ALU_SRL_SA: alu_out_not_mul_div = src_bE >> sa; 55 | `ALU_SRA_SA: alu_out_not_mul_div = $signed(src_bE) >>> sa; 56 | 57 | `ALU_LUI: alu_out_not_mul_div = {src_bE[15:0], 16'b0}; 58 | `ALU_DONOTHING: alu_out_not_mul_div = src_aE; 59 | 60 | default: alu_out_not_mul_div = 32'b0; 61 | endcase 62 | end 63 | 64 | //divide 65 | assign div_sign = (alu_controlE == `ALU_SIGNED_DIV); 66 | assign div_vaild = (alu_controlE == `ALU_SIGNED_DIV || alu_controlE == `ALU_UNSIGNED_DIV); 67 | 68 | div_radix2 DIV( 69 | .clk(~clk), 70 | .rst(rst), 71 | .flush(flushE), 72 | .a(src_aE), //divident 73 | .b(src_bE), //divisor 74 | .valid(div_vaild), 75 | .sign(div_sign), //1 signed 76 | 77 | // .ready(ready), 78 | .div_stall(div_stallE), 79 | .result(alu_out_div) 80 | ); 81 | 82 | //multiply 83 | assign mul_sign = (alu_controlE == `ALU_SIGNED_MULT); 84 | assign mul_valid = (alu_controlE == `ALU_SIGNED_MULT) | (alu_controlE == `ALU_UNSIGNED_MULT); 85 | mul_booth2 MUL( 86 | .a(src_aE), 87 | .b(src_bE), 88 | .sign(mul_sign), //1:signed 89 | 90 | .result(alu_out_mul) 91 | ); 92 | 93 | 94 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/EX/branch_judge.v: -------------------------------------------------------------------------------- 1 | module branch_judge ( 2 | input wire [4:0] branch_judge_controlE, 3 | input wire [31:0] src_aE, src_bE, 4 | 5 | output reg actual_takeE 6 | ); 7 | always @(*) begin 8 | case(branch_judge_controlE) 9 | `ALU_EQ: actual_takeE = ~(|(src_aE ^ src_bE)); 10 | `ALU_NEQ: actual_takeE = |(src_aE ^ src_bE); 11 | `ALU_GTZ: actual_takeE = ~src_aE[31] & (|src_aE); 12 | `ALU_GEZ: actual_takeE = ~src_aE[31]; 13 | `ALU_LTZ: actual_takeE = src_aE[31]; 14 | `ALU_LEZ: actual_takeE = src_aE[31] | ~(|src_aE); 15 | default: 16 | actual_takeE = 1'b0; 17 | endcase 18 | end 19 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/EX/div_radix2.v: -------------------------------------------------------------------------------- 1 | //module: div 2 | //description: radix-2 divider 3 | //version: 1.1 4 | 5 | /* 6 | log: 7 | 1.1: 增加了存储输入的逻辑 (不暂停M,W阶段, 数据前推导致输入发生变化) 8 | */ 9 | 10 | module div_radix2( 11 | input clk, 12 | input rst, 13 | input flush, 14 | input [31:0] a, //divident 15 | input [31:0] b, //divisor 16 | input valid, 17 | input sign, //1:signed 18 | 19 | // output reg ready, 20 | output wire div_stall, 21 | output [63:0] result 22 | ); 23 | /* 24 | 1. 先取绝对值，计算出余数和商。再根据被除数、除数符号对结果调整 25 | 2. 计算过程中，由于保证了remainer为正，因此最高位为0，可以用32位存储。而除数需用33位 26 | */ 27 | reg [31:0] a_save, b_save; 28 | reg [63:0] SR; //shift register 29 | reg [32 :0] NEG_DIVISOR; //divisor 2's complement 30 | wire [31:0] REMAINER, QUOTIENT; 31 | assign REMAINER = SR[63:32]; 32 | assign QUOTIENT = SR[31: 0]; 33 | 34 | wire [31:0] divident_abs; 35 | wire [32:0] divisor_abs; 36 | wire [31:0] remainer, quotient; 37 | 38 | assign divident_abs = (sign & a[31]) ? ~a + 1'b1 : a; 39 | //余数符号与被除数相同 40 | assign remainer = (sign & a_save[31]) ? ~REMAINER + 1'b1 : REMAINER; 41 | assign quotient = sign & (a_save[31] ^ b_save[31]) ? ~QUOTIENT + 1'b1 : QUOTIENT; 42 | assign result = {remainer,quotient}; 43 | 44 | wire CO; 45 | wire [32:0] sub_result; 46 | wire [32:0] mux_result; 47 | //sub 48 | assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR; 49 | //mux 50 | assign mux_result = CO ? sub_result : {1'b0,REMAINER}; 51 | 52 | //state machine 53 | reg [5:0] cnt; 54 | reg start_cnt; 55 | always @(posedge clk) begin 56 | if(rst | flush) begin 57 | cnt <= 0; 58 | start_cnt <= 0; 59 | end 60 | else if(!start_cnt & valid) begin 61 | cnt <= 1; 62 | start_cnt <= 1; 63 | //save a,b 64 | a_save <= a; 65 | b_save <= b; 66 | 67 | //Register init 68 | SR[63:0] <= {31'b0,divident_abs,1'b0}; //left shift one bit initially 69 | NEG_DIVISOR <= (sign & b[31]) ? {1'b1,b} : ~{1'b0,b} + 1'b1; //divisor_abs的补码 70 | end 71 | else if(start_cnt) begin 72 | if(cnt==32) begin 73 | cnt <= 0; 74 | start_cnt <= 0; 75 | 76 | //Output result 77 | SR[63:32] <= mux_result[31:0]; 78 | SR[0] <= CO; 79 | end 80 | else begin 81 | cnt <= cnt + 1; 82 | 83 | SR[63:0] <= {mux_result[30:0],SR[31:1],CO,1'b0}; //wsl: write and shift left 84 | end 85 | end 86 | end 87 | 88 | assign div_stall = |cnt; //只有当cnt=0时不暂停 89 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/ID/branch_predict.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | module branch_predict ( 3 | input wire [31:0] instrD, 4 | input wire [31:0] immD, 5 | 6 | output wire branchD, 7 | output wire pred_takeD 8 | ); 9 | 10 | assign branchD = ( ~(|(instrD[31:26] ^`EXE_BRANCHS)) & ~(|(instrD[19:17] ^ 3'b000)) ) 11 | | ~(|(instrD[31:28] ^4'b0001)); //4'b0001 -> beq, bgtz, blez, bne 12 | 13 | assign pred_takeD = branchD & (immD[31]) ? 1'b1 : 1'b0; //向上跳转，向下不跳转 14 | 15 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/ID/imm_ext.v: -------------------------------------------------------------------------------- 1 | module imm_ext( 2 | input wire [15:0] imm, 3 | input wire sign_ext, 4 | output wire [31:0] imm_ext 5 | ); 6 | assign imm_ext = sign_ext ? {{16{imm[15]}}, imm[15:0]}: 7 | {16'b0, imm[15:0]} 8 | ; 9 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/ID/jump_predict.v: -------------------------------------------------------------------------------- 1 | module jump_predict ( 2 | input wire [31:0] instrD, 3 | input wire [31:0] pc_plus4D, 4 | input wire [31:0] rd1D, 5 | input wire reg_write_enE, reg_write_enM, 6 | input wire [4:0] reg_writeE, reg_writeM, 7 | 8 | output wire jumpD, 9 | output wire jump_conflictD, 10 | output wire [31:0] pc_jumpD 11 | ); 12 | wire jr, j; 13 | wire [4:0] rsD; 14 | assign rsD = instrD[25:21]; 15 | assign jr = ~(|instrD[31:26]) & ~(|(instrD[5:1] ^ 5'b00100)); //jr, jalr 16 | assign j = ~(|(instrD[31:27] ^ 5'b00001)); //j, jal 17 | assign jumpD = jr | j; 18 | 19 | assign jump_conflictD = jr && 20 | ((reg_write_enE && rsD == reg_writeE) || 21 | (reg_write_enM && rsD == reg_writeM)); 22 | 23 | wire [31:0] pc_jump_immD; 24 | assign pc_jump_immD = {pc_plus4D[31:28], instrD[25:0], 2'b00}; 25 | 26 | assign pc_jumpD = j ? pc_jump_immD : rd1D; 27 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/ID/regfile.v: -------------------------------------------------------------------------------- 1 | module regfile( 2 | input wire clk, 3 | input wire stallW, 4 | input wire we3, 5 | input wire[4:0] ra1,ra2,wa3, 6 | input wire[31:0] wd3, 7 | output wire[31:0] rd1,rd2 8 | ); 9 | 10 | reg [31:0] rf[31:0]; 11 | 12 | always @(posedge clk) begin 13 | if(we3 & ~stallW) begin 14 | rf[wa3] <= wd3; 15 | end 16 | end 17 | 18 | assign rd1 = (ra1 != 0) ? rf[ra1] : 0; 19 | assign rd2 = (ra2 != 0) ? rf[ra2] : 0; 20 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/IF/pc_ctrl.v: -------------------------------------------------------------------------------- 1 | module pc_ctrl( 2 | input wire branchD, 3 | input wire branchM, 4 | input wire succM, 5 | input wire actual_takeM, 6 | input wire pred_takeD, 7 | 8 | input wire pc_trapM, 9 | input wire jumpD, 10 | input wire jump_conflictD, 11 | input wire jump_conflictE, 12 | 13 | output reg [2:0] pc_sel 14 | ); 15 | always @(*) begin 16 | if(pc_trapM) 17 | pc_sel = 3'b110; 18 | else if(branchM & ~succM & ~actual_takeM) 19 | pc_sel = 3'b101; 20 | else if(branchM & ~succM & actual_takeM) 21 | pc_sel = 3'b100; 22 | else if(jump_conflictE) 23 | pc_sel = 3'b011; 24 | else if(jumpD & ~jump_conflictD) 25 | pc_sel = 3'b010; 26 | else if(branchD & ~branchM & pred_takeD || 27 | branchD & branchM & succM & pred_takeD) 28 | pc_sel = 3'b001; 29 | else 30 | pc_sel = 3'b000; 31 | end 32 | 33 | // assign pc_sel = (branchM & ~succM & actual_takeM) ? 2'b10: 34 | // (branchM & ~succM & ~actual_takeM) ? 2'b11: 35 | // (branchD & ~branchM & pred_takeD || 36 | // branchD & branchM & succM & pred_takeD) ? 2'b01: 37 | // 2'b00; 38 | 39 | // assign pc_sel2[0] = pc_trapM | jumpD & ~jump_conflictD & ~jump_conflictE; 40 | // assign pc_sel2[1] = pc_trapM | jump_conflictE; 41 | 42 | // always @(*) begin 43 | // if(pc_trapM) 44 | // pc_sel2 = 2'b11; 45 | // else if(jump_conflictE) 46 | // pc_sel2 = 2'b10; 47 | // else if(jumpD & ~jump_conflictD) 48 | // pc_sel2 = 2'b01; 49 | // else 50 | // pc_sel2 = 2'b00; 51 | // end 52 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/IF/pc_reg.v: -------------------------------------------------------------------------------- 1 | module pc_reg #(parameter WIDTH=32)( 2 | input wire clk, 3 | input wire stallF, 4 | input wire rst, 5 | input wire [WIDTH-1:0] pc_next, 6 | 7 | output reg [ WIDTH-1:0] pc, 8 | output reg ce 9 | ); 10 | always @(posedge clk) begin 11 | if(rst) begin 12 | ce <= 0; 13 | end 14 | else begin 15 | ce <= 1; 16 | end 17 | end 18 | 19 | always @(posedge clk) begin 20 | if(!ce) begin 21 | pc <= 32'hbfc00000; 22 | // pc <= 32'h0000_0000; 23 | end 24 | else if(~stallF) begin 25 | pc <= pc_next; 26 | end 27 | end 28 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/MEM/exception.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | 3 | module exception( 4 | input rst, 5 | input [5:0] ext_int, 6 | input ri, break, syscall, overflow, addrErrorSw, addrErrorLw, pcError, eretM, 7 | input [31:0] cp0_status, cp0_cause, cp0_epc, 8 | input [31:0] pcM, 9 | input [31:0] alu_outM, 10 | 11 | output [31:0] except_type, 12 | output flush_exception, 13 | output [31:0] pc_exception, 14 | output pc_trap, 15 | output [31:0] badvaddrM 16 | ); 17 | 18 | //INTERUPT 19 | wire int; 20 | // //IE //EXL 21 | assign int = cp0_status[0] && ~cp0_status[1] && ( 22 | //IM //IP 23 | ( |(cp0_status[9:8] & cp0_cause[9:8]) ) || //soft interupt 24 | ( |(cp0_status[15:10] & ext_int) ) //hard interupt 25 | ); 26 | // 全局中断开启,且没有例外在处理,识别软件中断或者硬件中断; 27 | 28 | assign except_type = (int) ? `EXC_TYPE_INT : 29 | (addrErrorLw | pcError) ? `EXC_TYPE_ADEL : 30 | (ri) ? `EXC_TYPE_RI : 31 | (syscall) ? `EXC_TYPE_SYS : 32 | (break) ? `EXC_TYPE_BP : 33 | (addrErrorSw) ? `EXC_TYPE_ADES : 34 | (overflow) ? `EXC_TYPE_OV : 35 | (eretM) ? `EXC_TYPE_ERET : 36 | `EXC_TYPE_NOEXC; 37 | //interupt pc address 38 | assign pc_exception = (except_type == `EXC_TYPE_NOEXC) ? `ZeroWord: 39 | (except_type == `EXC_TYPE_ERET)? cp0_epc : 40 | 32'hbfc0_0380; 41 | assign pc_trap = (except_type == `EXC_TYPE_NOEXC) ? 1'b0: 42 | 1'b1; 43 | assign flush_exception = (except_type == `EXC_TYPE_NOEXC) ? 1'b0: 44 | 1'b1; 45 | assign badvaddrM = (pcError) ? pcM : alu_outM; 46 | 47 | // // 提高性能; 48 | // assign pc_except = (int) | (addrErrorLw | pcError) | (ri) | (break) | (overflow) 49 | // ? 32'hbfc0_0380 50 | // (eretM) ? `ZeroWord : 51 | // cp0_epc ; 52 | 53 | // assign pc_trap = (int) | (addrErrorLw | pcError) | (ri) | (break) | (overflow) | (eretM) 54 | // ? 1'b1 : 1'b0 ; 55 | 56 | // assign flush_except = pc_trap ; 57 | 58 | // assign badvaddrM = (pcError) ? pcM : alu_outM ; 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/MEM/hilo_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "defines.vh" 3 | 4 | module hilo_reg( 5 | input wire clk,rst,we, //both write lo and hi 6 | input wire [31:0] instrM, 7 | 8 | input wire [63:0] hilo_i, 9 | output wire [31:0] hilo_o 10 | ); 11 | wire [63:0] hilo_ii; 12 | reg [63:0] hilo; 13 | always @(posedge clk) begin 14 | if(rst) 15 | hilo <= 0; 16 | else if(we) 17 | hilo <= hilo_i; 18 | else 19 | hilo <= hilo; 20 | end 21 | 22 | // assign hilo_ii = ( {64{~rst & we}} & hilo_i ); 23 | 24 | // 读cp0逻辑； 25 | wire mfhi; 26 | wire mflo; 27 | assign mfhi = ~(|(instrM[31:26] ^ `EXE_R_TYPE)) & ~(|(instrM[5:0] ^ `EXE_MFHI)); 28 | assign mflo = ~(|(instrM[31:26] ^ `EXE_R_TYPE)) & ~(|(instrM[5:0] ^ `EXE_MFLO)); 29 | 30 | assign hilo_o = ({32{mfhi}} & hilo[63:32]) | ({32{mflo}} & hilo[31:0]); 31 | endmodule 32 | 33 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/MEM/mem_ctrl.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | 3 | module mem_ctrl( 4 | input wire [31:0] instrM, 5 | input wire [31:0] addr, 6 | 7 | input wire [31:0] data_wdataM, 8 | output wire [31:0] mem_wdataM, 9 | output wire [3:0] mem_wenM, 10 | 11 | input wire [31:0] mem_rdataM, 12 | output wire [31:0] data_rdataM, 13 | 14 | output wire addr_error_sw, addr_error_lw 15 | ); 16 | wire [3:0] mem_byte_wen; 17 | wire [5:0] op_code; 18 | 19 | wire instr_lw, instr_lh, instr_lb, instr_sw, instr_sh, instr_sb, instr_lhu; 20 | wire addr_W0, addr_B2, addr_B1, addr_B3; 21 | 22 | 23 | assign op_code = instrM[31:26]; 24 | 25 | assign addr_W0 = ~(|(addr[1:0] ^ 2'b00)); 26 | assign addr_B2 = ~(|(addr[1:0] ^ 2'b10)); 27 | assign addr_B1 = ~(|(addr[1:0] ^ 2'b01)); 28 | assign addr_B3 = ~(|(addr[1:0] ^ 2'b11)); 29 | 30 | assign instr_lw = ~(|(op_code ^ `EXE_LW)); 31 | assign instr_lb = ~(|(op_code ^ `EXE_LB)); 32 | assign instr_lh = ~(|(op_code ^ `EXE_LH)); 33 | assign instr_lbu = ~(|(op_code ^ `EXE_LBU)); 34 | assign instr_lhu = ~(|(op_code ^ `EXE_LHU)); 35 | assign instr_sw = ~(|(op_code ^ `EXE_SW)); 36 | assign instr_sh = ~(|(op_code ^ `EXE_SH)); 37 | assign instr_sb = ~(|(op_code ^ `EXE_SB)); 38 | 39 | 40 | assign addr_error_sw = (instr_sw & ~addr_W0) 41 | | ( instr_sh & ~(addr_W0 | addr_B2)); 42 | assign addr_error_lw = (instr_lw & ~addr_W0) 43 | | (( instr_lh | instr_lhu ) & ~(addr_W0 | addr_B2)); 44 | 45 | // wdata and byte_wen 46 | assign mem_wenM = ( {4{( instr_sw & addr_W0 )}} & 4'b1111) 47 | | ( {4{( instr_sh & addr_W0 )}} & 4'b0011) 48 | | ( {4{( instr_sh & addr_B2 )}} & 4'b1100) 49 | | ( {4{( instr_sb & addr_W0 )}} & 4'b0001) 50 | | ( {4{( instr_sb & addr_B1 )}} & 4'b0010) 51 | | ( {4{( instr_sb & addr_B2 )}} & 4'b0100) 52 | | ( {4{( instr_sb & addr_B3 )}} & 4'b1000); 53 | 54 | // rdata 55 | // data ram 按字寻址 56 | assign mem_wdataM = ({ 32{instr_sw}} & data_wdataM) 57 | | ( {32{instr_sh}} & {2{data_wdataM[15:0]} }) 58 | | ( {32{instr_sb}} & {4{data_wdataM[7:0]} }); 59 | // 所以还是取了整个字： 60 | assign data_rdataM = ( {32{instr_lw}} & mem_rdataM) 61 | | ( {32{ instr_lh & addr_W0}} & { {16{mem_rdataM[15]}}, mem_rdataM[15:0] }) 62 | | ( {32{ instr_lh & addr_B2}} & { {16{mem_rdataM[31]}}, mem_rdataM[31:16] }) 63 | | ( {32{ instr_lhu & addr_W0}} & { 16'b0, mem_rdataM[15:0] }) 64 | | ( {32{ instr_lhu & addr_B2}} & { 16'b0, mem_rdataM[31:16] }) 65 | | ( {32{ instr_lb & addr_W0}} & { {24{mem_rdataM[7]}}, mem_rdataM[7:0] }) 66 | | ( {32{ instr_lb & addr_B1}} & { {24{mem_rdataM[15]}}, mem_rdataM[15:8] }) 67 | | ( {32{ instr_lb & addr_B2}} & { {24{mem_rdataM[23]}}, mem_rdataM[23:16] }) 68 | | ( {32{ instr_lb & addr_B3}} & { {24{mem_rdataM[31]}}, mem_rdataM[31:24] }) 69 | | ( {32{ instr_lbu & addr_W0}} & { 24'b0 , mem_rdataM[7:0] }) 70 | | ( {32{ instr_lbu & addr_B1}} & { 24'b0 , mem_rdataM[15:8] }) 71 | | ( {32{ instr_lbu & addr_B2}} & { 24'b0 , mem_rdataM[23:16] }) 72 | | ( {32{ instr_lbu & addr_B3}} & { 24'b0 , mem_rdataM[31:24] }); 73 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/PIPE/ex_mem.v: -------------------------------------------------------------------------------- 1 | module ex_mem ( 2 | input wire clk, rst,flushM, 3 | input wire stallM, 4 | input wire [31:0] pcE, 5 | input wire [63:0] alu_outE, 6 | input wire [31:0] rt_valueE, 7 | input wire [4:0] reg_writeE, 8 | input wire [31:0] instrE, 9 | input wire branchE, 10 | input wire pred_takeE, 11 | input wire [31:0] pc_branchE, 12 | input wire overflowE, 13 | input wire is_in_delayslot_iE, 14 | input wire [4:0] rdE, 15 | input wire actual_takeE, 16 | 17 | 18 | output reg [31:0] pcM, 19 | output reg [31:0] alu_outM, 20 | output reg [31:0] rt_valueM, 21 | output reg [4:0] reg_writeM, 22 | output reg [31:0] instrM, 23 | output reg branchM, 24 | output reg pred_takeM, 25 | output reg [31:0] pc_branchM, 26 | output reg overflowM, 27 | output reg is_in_delayslot_iM, 28 | output reg [4:0] rdM, 29 | output reg actual_takeM 30 | ); 31 | always @(posedge clk) begin 32 | if(rst | flushM) begin 33 | pcM <= 0; 34 | alu_outM <= 0; 35 | rt_valueM <= 0; 36 | reg_writeM <= 0; 37 | instrM <= 0; 38 | branchM <= 0; 39 | pred_takeM <= 0; 40 | pc_branchM <= 0; 41 | overflowM <= 0; 42 | is_in_delayslot_iM <= 0; 43 | rdM <= 0; 44 | actual_takeM <= 0; 45 | end 46 | else if(~stallM) begin 47 | pcM <= pcE ; 48 | alu_outM <= alu_outE[31:0] ; 49 | rt_valueM <= rt_valueE ; 50 | reg_writeM <= reg_writeE ; 51 | instrM <= instrE ; 52 | branchM <= branchE ; 53 | pred_takeM <= pred_takeE ; 54 | pc_branchM <= pc_branchE ; 55 | overflowM <= overflowE ; 56 | is_in_delayslot_iM <= is_in_delayslot_iE ; 57 | rdM <= rdE ; 58 | actual_takeM <= actual_takeE ; 59 | end 60 | end 61 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/PIPE/id_ex.v: -------------------------------------------------------------------------------- 1 | module id_ex ( 2 | input wire clk, rst, 3 | input wire stallE, 4 | input wire flushE, 5 | input wire [31:0] pcD, 6 | input wire [31:0] rd1D, rd2D, 7 | input wire [4:0] rsD, rtD, rdD, 8 | input wire [31:0] immD, 9 | input wire [31:0] pc_plus4D, 10 | input wire [31:0] instrD, 11 | input wire [31:0] pc_branchD, 12 | input wire pred_takeD, 13 | input wire branchD, 14 | input wire jump_conflictD, 15 | input wire [4:0] saD, 16 | input wire is_in_delayslot_iD, 17 | input wire [4:0] alu_controlD, 18 | input wire jumpD, 19 | input wire [4:0] branch_judge_controlD, 20 | 21 | 22 | output reg [31:0] pcE, 23 | output reg [31:0] rd1E, rd2E, 24 | output reg [4:0] rsE, rtE, rdE, 25 | output reg [31:0] immE, 26 | output reg [31:0] pc_plus4E, 27 | output reg [31:0] instrE, 28 | output reg [31:0] pc_branchE, 29 | output reg pred_takeE, 30 | output reg branchE, 31 | output reg jump_conflictE, 32 | output reg [4:0] saE, 33 | output reg is_in_delayslot_iE, 34 | output reg [4:0] alu_controlE, 35 | output reg jumpE, 36 | output reg [4:0] branch_judge_controlE 37 | ); 38 | always @(posedge clk) begin 39 | if(rst | flushE) begin 40 | pcE <= 0 ; 41 | rd1E <= 0 ; 42 | rd2E <= 0 ; 43 | rsE <= 0 ; 44 | rtE <= 0 ; 45 | rdE <= 0 ; 46 | immE <= 0 ; 47 | pc_plus4E <= 0 ; 48 | instrE <= 0 ; 49 | pc_branchE <= 0 ; 50 | pred_takeE <= 0 ; 51 | branchE <= 0 ; 52 | jump_conflictE <= 0 ; 53 | saE <= 0 ; 54 | is_in_delayslot_iE <= 0 ; 55 | alu_controlE <= 0 ; 56 | jumpE <= 0 ; 57 | branch_judge_controlE <= 0 ; 58 | end 59 | else if(~stallE) begin 60 | pcE <= pcD ; 61 | rd1E <= rd1D ; 62 | rd2E <= rd2D ; 63 | rsE <= rsD ; 64 | rtE <= rtD ; 65 | rdE <= rdD ; 66 | immE <= immD ; 67 | pc_plus4E <= pc_plus4D ; 68 | instrE <= instrD ; 69 | pc_branchE <= pc_branchD ; 70 | pred_takeE <= pred_takeD ; 71 | branchE <= branchD ; 72 | jump_conflictE <= jump_conflictD ; 73 | saE <= saD ; 74 | is_in_delayslot_iE <= is_in_delayslot_iD ; 75 | alu_controlE <= alu_controlD ; 76 | jumpE <= jumpD ; 77 | branch_judge_controlE <= branch_judge_controlD; 78 | end 79 | end 80 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/PIPE/if_id.v: -------------------------------------------------------------------------------- 1 | module if_id( 2 | input wire clk, rst, 3 | input wire flushD, 4 | input wire stallD, 5 | input wire [31:0] pcF, 6 | input wire [31:0] pc_plus4F, 7 | 8 | input wire [31:0] instrF, 9 | input wire [31:0] is_in_delayslot_iF, 10 | 11 | 12 | output reg [31:0] pcD, 13 | output reg [31:0] pc_plus4D, 14 | output reg [31:0] instrD, 15 | output reg [31:0] is_in_delayslot_iD 16 | ); 17 | 18 | always @(posedge clk) begin 19 | if(rst | flushD) begin 20 | pcD <= 0 ; 21 | pc_plus4D <= 0 ; 22 | instrD <= 0 ; 23 | is_in_delayslot_iD <= 0 ; 24 | end 25 | else if(~stallD) begin 26 | pcD <= pcF ; 27 | pc_plus4D <= pc_plus4F ; 28 | instrD <= instrF ; 29 | is_in_delayslot_iD <= is_in_delayslot_iF ; 30 | end 31 | end 32 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/PIPE/mem_wb.v: -------------------------------------------------------------------------------- 1 | module mem_wb ( 2 | input wire clk, rst, 3 | input wire stallW, 4 | input wire [31:0] pcM, 5 | input wire [31:0] alu_outM, 6 | input wire [4:0] reg_writeM, 7 | input wire reg_write_enM, 8 | input wire [31:0] mem_rdataM, 9 | input wire [31:0] resultM, 10 | 11 | 12 | output reg [31:0] pcW, 13 | output reg [31:0] alu_outW, 14 | output reg [4:0] reg_writeW, 15 | output reg reg_write_enW, 16 | output reg [31:0] mem_rdataW, 17 | output reg [31:0] resultW 18 | ); 19 | always @(posedge clk) begin 20 | if(rst) begin 21 | pcW <= 0; 22 | alu_outW <= 0; 23 | reg_writeW <= 0; 24 | reg_write_enW <= 0; 25 | mem_rdataW <= 0; 26 | resultW <= 0; 27 | end 28 | else if(~stallW) begin 29 | pcW <= pcM; 30 | alu_outW <= alu_outM; 31 | reg_writeW <= reg_writeM; 32 | reg_write_enW <= reg_write_enM; 33 | mem_rdataW <= mem_rdataM; 34 | resultW <= resultM; 35 | end 36 | end 37 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/alu_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Create Date: 2019/06/21 16:14:50 4 | 5 | `include "aludefines.vh" 6 | `include "defines.vh" 7 | 8 | module alu_decoder( 9 | input wire [31:0] instrD, 10 | 11 | output reg [4:0] alu_controlD, 12 | output reg [4:0] branch_judge_controlD 13 | ); 14 | 15 | wire [5:0] op_code; 16 | wire [4:0] rs, rt; 17 | wire [5:0] funct; 18 | 19 | assign op_code = instrD[31:26]; 20 | assign rs = instrD[25:21]; 21 | assign rt = instrD[20:16]; 22 | assign funct = instrD[5:0]; 23 | 24 | always @* begin 25 | case(op_code) 26 | `EXE_R_TYPE: 27 | case(funct) 28 | //算数和逻辑运算 29 | `EXE_AND: alu_controlD <= `ALU_AND; //1 30 | `EXE_OR: alu_controlD <= `ALU_OR; 31 | `EXE_XOR: alu_controlD <= `ALU_XOR; 32 | `EXE_NOR: alu_controlD <= `ALU_NOR; 33 | 34 | `EXE_ADD: alu_controlD <= `ALU_ADD; //4 35 | `EXE_SUB: alu_controlD <= `ALU_SUB; 36 | `EXE_ADDU: alu_controlD <= `ALU_ADDU; 37 | `EXE_SUBU: alu_controlD <= `ALU_SUBU; 38 | `EXE_SLT: alu_controlD <= `ALU_SLT; 39 | `EXE_SLTU: alu_controlD <= `ALU_SLTU; 40 | //div and mul 41 | `EXE_DIV: alu_controlD <= `ALU_SIGNED_DIV; 42 | `EXE_DIVU: alu_controlD <= `ALU_UNSIGNED_DIV; 43 | `EXE_MULT: alu_controlD <= `ALU_SIGNED_MULT; 44 | `EXE_MULTU: alu_controlD <= `ALU_UNSIGNED_MULT; 45 | 46 | //移位指令 47 | `EXE_SLL: alu_controlD <= `ALU_SLL_SA; //2 48 | `EXE_SRL: alu_controlD <= `ALU_SRL_SA; 49 | `EXE_SRA: alu_controlD <= `ALU_SRA_SA; 50 | `EXE_SLLV: alu_controlD <= `ALU_SLL; 51 | `EXE_SRLV: alu_controlD <= `ALU_SRL; 52 | `EXE_SRAV: alu_controlD <= `ALU_SRA; 53 | 54 | //hilo 55 | `EXE_MTHI: alu_controlD <= `ALU_MTHI; 56 | `EXE_MTLO: alu_controlD <= `ALU_MTLO; 57 | //jump 58 | // `EXE_JR: alu_controlD <= `ALU_DONOTHING; //5 59 | // `EXE_JALR: alu_controlD <= `ALU_DONOTHING; 60 | default: alu_controlD <= `ALU_DONOTHING; 61 | endcase 62 | //I type 63 | `EXE_ADDI: alu_controlD <= `ALU_ADD; 64 | `EXE_ADDIU: alu_controlD <= `ALU_ADDU; 65 | `EXE_SLTI: alu_controlD <= `ALU_SLT; 66 | `EXE_SLTIU: alu_controlD <= `ALU_SLTU; 67 | `EXE_ANDI: alu_controlD <= `ALU_AND; 68 | `EXE_XORI: alu_controlD <= `ALU_XOR; 69 | `EXE_LUI: alu_controlD <= `ALU_LUI; 70 | `EXE_ORI: alu_controlD <= `ALU_OR; 71 | //memory 72 | `EXE_LW, `EXE_LB, `EXE_LBU, `EXE_LH, `EXE_LHU, `EXE_SW, `EXE_SB, `EXE_SH: 73 | alu_controlD <= `ALU_ADDU; 74 | // `EXE_BEQ: 75 | // alu_controlD <= `ALU_EQ; 76 | // `EXE_BGTZ: 77 | // alu_controlD <= `ALU_GTZ; 78 | // `EXE_BLEZ: 79 | // alu_controlD <= `ALU_LEZ; 80 | // `EXE_BNE: 81 | // alu_controlD <= `ALU_NEQ; 82 | // `EXE_BRANCHS: //bltz, bltzal, bgez, bgezal 83 | // case(rt) 84 | // `EXE_BLTZ, `EXE_BLTZAL: 85 | // alu_controlD <= `ALU_LTZ; 86 | // `EXE_BGEZ, `EXE_BGEZAL: 87 | // alu_controlD <= `ALU_GEZ; 88 | // default: 89 | // alu_controlD <= `ALU_DONOTHING; 90 | // endcase 91 | //J type 92 | // `EXE_J: alu_controlD <= `ALU_DONOTHING; 93 | // `EXE_JAL: alu_controlD <= `ALU_DONOTHING; 94 | default: 95 | alu_controlD <= `ALU_DONOTHING; 96 | endcase 97 | end 98 | 99 | // branch_judge控制信号 100 | always @(*) begin 101 | case(op_code) 102 | `EXE_BEQ: 103 | branch_judge_controlD <= `ALU_EQ; 104 | `EXE_BGTZ: 105 | branch_judge_controlD <= `ALU_GTZ; 106 | `EXE_BLEZ: 107 | branch_judge_controlD <= `ALU_LEZ; 108 | `EXE_BNE: 109 | branch_judge_controlD <= `ALU_NEQ; 110 | `EXE_BRANCHS: //bltz, bltzal, bgez, bgezal 111 | case(rt) 112 | `EXE_BLTZ, `EXE_BLTZAL: 113 | branch_judge_controlD <= `ALU_LTZ; 114 | `EXE_BGEZ, `EXE_BGEZAL: 115 | branch_judge_controlD <= `ALU_GEZ; 116 | default: 117 | branch_judge_controlD <= `ALU_DONOTHING; 118 | endcase 119 | default: 120 | branch_judge_controlD <= `ALU_DONOTHING; 121 | endcase 122 | end 123 | endmodule 124 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/d_cache.v: -------------------------------------------------------------------------------- 1 | module d_cache ( 2 | input wire clk, rst, 3 | 4 | input wire data_en , 5 | input wire [31:0] data_addr , 6 | output wire [31:0] data_rdata , 7 | input wire [3:0] data_wen , 8 | input wire [31:0] data_wdata , 9 | output stall , 10 | 11 | output wire data_sram_en, 12 | output wire [3:0] data_sram_wen , 13 | output wire [31:0] data_sram_addr , 14 | output wire [31:0] data_sram_wdata , 15 | input wire [31:0] data_sram_rdata , 16 | input data_sram_data_ok 17 | ); 18 | //stall 19 | assign stall = data_en & ~(|data_wen) & ~data_sram_data_ok; 20 | 21 | assign data_rdata = data_sram_rdata; 22 | 23 | assign data_sram_en = data_en; 24 | assign data_sram_wen = data_wen; 25 | assign data_sram_addr = data_addr; 26 | assign data_sram_wdata = data_wdata; 27 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/hazard.v: -------------------------------------------------------------------------------- 1 | module hazard ( 2 | input wire [31:0] instrE,//no use 3 | input wire [31:0] instrM,//no use 4 | input wire d_cache_stall, 5 | input wire div_stallE, 6 | 7 | input wire flush_jump_confilctE, flush_pred_failedM, flush_exceptionM, 8 | 9 | input wire [4:0] rsE, 10 | input wire [4:0] rtE, 11 | input wire reg_write_enM, 12 | input wire reg_write_enW, 13 | input wire [4:0] reg_writeM, 14 | input wire [4:0] reg_writeW, 15 | 16 | input wire mem_read_enM, 17 | 18 | output wire stallF, stallD, stallE, stallM, stallW, 19 | output wire flushF, flushD, flushE, flushM, flushW, 20 | 21 | output wire [1:0] forward_aE, forward_bE //00-> NONE, 01-> MEM, 10-> WB (LW instr) 22 | ); 23 | assign forward_aE = rsE != 0 && reg_write_enM && (rsE == reg_writeM) ? 2'b01 : 24 | rsE != 0 && reg_write_enW && (rsE == reg_writeW) ? 2'b10 : 25 | 2'b00; 26 | assign forward_bE = reg_write_enM && (rtE == reg_writeM) ? 2'b01 : 27 | reg_write_enW && (rtE == reg_writeW) ? 2'b10 : 28 | 2'b00; 29 | 30 | // reg stall_lw; //add, lw 数据冲突无法仅靠数据前推解决（MEM阶段无法从内存取得数据），需要先暂停形成一个气泡，再前推 31 | //更新1：通过mem_stall来暂停（相当于将MEM分为了两个阶段），故可以在MEM阶段前推 32 | // always @(*) begin 33 | // stall_lw = rst ? 1'b0 : mem_read_enM && ( 34 | // (reg_write_enM && (rsE == reg_writeM)) || 35 | // (reg_write_enM && (rtE == reg_writeM)) 36 | // ); 37 | // end 38 | 39 | assign stallF = ~flush_exceptionM & (d_cache_stall | div_stallE); 40 | assign stallD = d_cache_stall | div_stallE; 41 | assign stallE = d_cache_stall | div_stallE; 42 | assign stallM = d_cache_stall; 43 | assign stallW = d_cache_stall; // 不暂停,会减少jr等指令冲突; 44 | 45 | assign flushF = 1'b0; 46 | assign flushD = flush_exceptionM | flush_pred_failedM | (flush_jump_confilctE & ~d_cache_stall); //EX: jr(冲突), MEM: lw这种情况时，flush_jump_confilctE会导致暂停在D阶段jr的延迟槽指令消失 47 | assign flushE = flush_exceptionM | (flush_pred_failedM & ~div_stallE); //EX: div, MEM: beq, beq预测失败，要flush D和E，但由于div暂停在E，因此只需要flushD就可以了 48 | assign flushM = flush_exceptionM | div_stallE; 49 | assign flushW = 1'b0; 50 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/i_cache.v: -------------------------------------------------------------------------------- 1 | module i_cache ( 2 | input wire clk, rst, 3 | 4 | input wire inst_en , 5 | input wire [31:0] inst_addr , 6 | output wire [31:0] inst_rdata , 7 | 8 | output wire inst_sram_en, 9 | output wire [31:0] inst_sram_addr , 10 | input wire [31:0] inst_sram_rdata 11 | ); 12 | 13 | assign inst_rdata = inst_sram_rdata; 14 | 15 | assign inst_sram_en = inst_en; 16 | assign inst_sram_addr = inst_addr; 17 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/mycpu_top.v: -------------------------------------------------------------------------------- 1 | module mycpu_top ( 2 | input clk,resetn, 3 | input [5:0] ext_int, 4 | 5 | //instr 6 | output inst_sram_en, 7 | output [3:0] inst_sram_wen , 8 | output [31:0] inst_sram_addr , 9 | output [31:0] inst_sram_wdata , 10 | input [31:0] inst_sram_rdata , 11 | 12 | //data 13 | output data_sram_en, 14 | output [3:0] data_sram_wen , 15 | output [31:0] data_sram_addr , 16 | output [31:0] data_sram_wdata , 17 | input [31:0] data_sram_rdata , 18 | input data_sram_data_ok , //sram没有这个信号，只是为了产生stall而编造的 19 | 20 | //debug 21 | output [31:0] debug_wb_pc , 22 | output [3:0] debug_wb_rf_wen , 23 | output [4:0] debug_wb_rf_wnum , 24 | output [31:0] debug_wb_rf_wdata 25 | ); 26 | //datapath传出来的信号 27 | wire inst_en ; 28 | wire [31:0] inst_addr ; 29 | wire [31:0] inst_rdata ; 30 | 31 | wire data_en ; 32 | wire [31:0] data_addr ; 33 | wire [31:0] data_rdata ; 34 | wire [3:0] data_wen ; 35 | wire [31:0] data_wdata ; 36 | wire d_cache_stall ; 37 | 38 | assign inst_sram_wen = 4'b0; 39 | assign inst_sram_wdata = 32'b0; 40 | 41 | datapath datapath( 42 | .clk(clk), .rst(~resetn), 43 | .ext_int(ext_int), 44 | 45 | //inst 46 | .inst_addrF(inst_addr), 47 | .inst_enF(inst_en), 48 | .instrF(inst_rdata), 49 | 50 | //data 51 | .mem_enM(data_en), 52 | .mem_addrM(data_addr), 53 | .mem_rdataM(data_rdata), 54 | .mem_wenM(data_wen), 55 | .mem_wdataM(data_wdata), 56 | .d_cache_stall(d_cache_stall), 57 | 58 | .debug_wb_pc (debug_wb_pc ), 59 | .debug_wb_rf_wen (debug_wb_rf_wen ), 60 | .debug_wb_rf_wnum (debug_wb_rf_wnum ), 61 | .debug_wb_rf_wdata (debug_wb_rf_wdata ) 62 | ); 63 | 64 | i_cache i_cache( 65 | .clk(clk), .rst(~resetn), 66 | 67 | .inst_en(inst_en), 68 | .inst_addr(inst_addr), 69 | .inst_rdata(inst_rdata), 70 | 71 | .inst_sram_en(inst_sram_en), 72 | .inst_sram_addr(inst_sram_addr), 73 | .inst_sram_rdata(inst_sram_rdata) 74 | ); 75 | 76 | wire [31:0] data_sram_addr_temp; 77 | d_cache d_cache( 78 | .clk(clk), .rst(~resetn), 79 | //datapath 80 | .data_en(data_en), 81 | .data_addr(data_addr), 82 | .data_rdata(data_rdata), 83 | .data_wen(data_wen), 84 | .data_wdata(data_wdata), 85 | .stall(d_cache_stall), 86 | //outer 87 | .data_sram_en(data_sram_en), 88 | .data_sram_wen(data_sram_wen), 89 | .data_sram_addr(data_sram_addr_temp), 90 | .data_sram_wdata(data_sram_wdata), 91 | .data_sram_rdata(data_sram_rdata), 92 | .data_sram_data_ok(data_sram_data_ok) 93 | ); 94 | 95 | assign data_sram_addr = data_sram_addr_temp[31:16] == 16'hbfaf ? {3'b0, data_sram_addr_temp[28:0]} : data_sram_addr_temp; 96 | 97 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/README.txt: -------------------------------------------------------------------------------- 1 | 实验要求由实验指导书说明，本文档主要目的是辅助同学测试指令实现的正确性。测试的文件都在soft目录中，soft目录包括：func_full, func_part, funcTest_independent,三个目录。 2 | func_full是所有的57条指令的总测试集，共89个测试点。由于我们的开发板的ram容量不够没有办法一次性的加载到FPGA上测试，所以后面我们拆成了三个部分也就是func_part,此目录提供测试的源代码，调试的时候可以参考(func_full/inst/xxx.S)文件对照。Func_part目录包含三个obj文件： 3 | obj_1(对应funt_full中的第1到47条测试) 4 | obj_2(对应funt_full中的第48到64条测试) 5 | obj_3(对应funt_full中的第65到89条测试) 6 | 前面两个obj不涉及异常指令和特权指令，只是基础的六类的指令的综合测试，具体的每条测试是什么可以自行参考(func_ful/inst/)。使用此文档的测试需要街上sram接口的Soc才行。 7 | funcTest_independent是简单的六类指令的测试，可以提供在接上Soc之前的实现的测试。在自己设计的cpu上加载coe并对比测试就行。 8 | 对于每个阶段都提供一定的测试文件供同学们简单的判断指令执行的正确性。下面对于测试文件进行说明。 9 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .global _start 4 | _start: 5 | 6 | ######### add\addi\addiu\addu\sub\subu ########## 7 | 8 | ori $1,$0,0x8000 # $1 = 0x8000 9 | sll $1,$1,16 # $1 = 0x80000000 10 | ori $1,$1,0x0010 # $1 = 0x80000010 11 | 12 | ori $2,$0,0x8000 # $2 = 0x8000 13 | sll $2,$2,16 # $2 = 0x80000000 14 | ori $2,$2,0x0001 # $2 = 0x80000001 15 | 16 | ori $3,$0,0x0000 # $3 = 0x00000000 17 | addu $3,$2,$1 ## $3 = 0x00000011 18 | ori $3,$0,0x0000 # $3 = 0x00000000 19 | 20 | 21 | sub $3,$1,$3 ## $3 = 0x80000010 22 | subu $3,$3,$2 ## $3 = 0xF 23 | 24 | addi $3,$3,2 ## $3 = 0x11 25 | ori $3,$0,0x0000 # $3 = 0x00000000 26 | addiu $3,$3,0x8000 ## $3 = 0xffff8000 27 | 28 | sll $1,$1,1 29 | add $3,$2,$1 ## $3 = 0x80000021 30 | 31 | ######### slt\sltu\slti\sltiu ########## 32 | 33 | or $1,$0,0xffff # $1 = 0xffff 34 | sll $1,$1,16 # $1 = 0xffff0000 35 | slt $2,$1,$0 ## $2 = 1 36 | sltu $2,$1,$0 ## $2 = 0 37 | slti $2,$1,0x8000 ## $2 = 1 38 | sltiu $2,$1,0x8000 ## $2 = 1 39 | 40 | ######### mult\multu ########## 41 | 42 | ori $1,$0,0xffff 43 | sll $1,$1,16 44 | ori $1,$1,0xfffb # $1 = -5 45 | ori $2,$0,6 # $2 = 6 46 | 47 | mult $1,$2 ## hi = 0xffffffff 48 | ## lo = 0xffffffe2 49 | 50 | multu $1,$2 ## hi = 0x5 51 | ## lo = 0xffffffe2 52 | nop 53 | nop 54 | 55 | ################# div\divu #################### 56 | ori $2,$0,0xffff 57 | sll $2,$2,16 58 | ori $2,$2,0xfff1 ## $2 = -15 59 | ori $3,$0,0x11 ## $3 = 17 60 | 61 | div $zero,$2,$3 ## hi = 0xfffffff1 62 | ## lo = 0x0 63 | divu $zero,$2,$3 ## hi = 0x00000003 64 | ## lo = 0x0f0f0f0e 65 | 66 | div $zero,$3,$2 ## hi = 2 67 | ## lo = 0xffffffff 68 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000011000000000000000 2 | 00000000000000010000110000000000 3 | 00110100001000010000000000010000 4 | 00110100000000101000000000000000 5 | 00000000000000100001010000000000 6 | 00110100010000100000000000000001 7 | 00110100000000110000000000000000 8 | 00000000010000010001100000100001 9 | 00110100000000110000000000000000 10 | 00000000001000110001100000100010 11 | 00000000011000100001100000100011 12 | 00100000011000110000000000000010 13 | 00110100000000110000000000000000 14 | 00100100011000111000000000000000 15 | 00000000000000010000100001000000 16 | 00000000010000010001100000100000 17 | 00110100000000011111111111111111 18 | 00000000000000010000110000000000 19 | 00000000001000000001000000101010 20 | 00000000001000000001000000101011 21 | 00101000001000101000000000000000 22 | 00101100001000101000000000000000 23 | 00110100000000011111111111111111 24 | 00000000000000010000110000000000 25 | 00110100001000011111111111111011 26 | 00110100000000100000000000000110 27 | 00000000001000100000000000011000 28 | 00000000001000100000000000011001 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00110100000000101111111111111111 32 | 00000000000000100001010000000000 33 | 00110100010000101111111111110001 34 | 00110100000000110000000000010001 35 | 00000000010000110000000000011010 36 | 00000000010000110000000000011011 37 | 00000000011000100000000000011010 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000001110 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 34018000 4 | 00010c00 5 | 34210010 6 | 34028000 7 | 00021400 8 | 34420001 9 | 34030000 10 | 00411821 11 | 34030000 12 | 00231822 13 | 00621823 14 | 20630002 15 | 34030000 16 | 24638000 17 | 00010840 18 | 00411820 19 | 3401ffff 20 | 00010c00 21 | 0020102a 22 | 0020102b 23 | 28228000 24 | 2c228000 25 | 3401ffff 26 | 00010c00 27 | 3421fffb 28 | 34020006 29 | 00220018 30 | 00220019 31 | 00000000 32 | 00000000 33 | 3402ffff 34 | 00021400 35 | 3442fff1 36 | 34030011 37 | 0043001a 38 | 0043001b 39 | 0062001a 40 | 00000000 41 | 00000000 42 | 00000000 43 | 0000000e 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000011000000000000000 2 | 00000000000000010000110000000000 3 | 00110100001000010000000000010000 4 | 00110100000000101000000000000000 5 | 00000000000000100001010000000000 6 | 00110100010000100000000000000001 7 | 00110100000000110000000000000000 8 | 00000000010000010001100000100001 9 | 00110100000000110000000000000000 10 | 00000000001000110001100000100010 11 | 00000000011000100001100000100011 12 | 00100000011000110000000000000010 13 | 00110100000000110000000000000000 14 | 00100100011000111000000000000000 15 | 00000000000000010000100001000000 16 | 00000000010000010001100000100000 17 | 00110100000000011111111111111111 18 | 00000000000000010000110000000000 19 | 00000000001000000001000000101010 20 | 00000000001000000001000000101011 21 | 00101000001000101000000000000000 22 | 00101100001000101000000000000000 23 | 00110100000000011111111111111111 24 | 00000000000000010000110000000000 25 | 00110100001000011111111111111011 26 | 00110100000000100000000000000110 27 | 00000000001000100000000000011000 28 | 00000000001000100000000000011001 29 | 00000000000000000000000000000000 30 | 00000000000000000000000000000000 31 | 00110100000000101111111111111111 32 | 00000000000000100001010000000000 33 | 00110100010000101111111111110001 34 | 00110100000000110000000000010001 35 | 00000000010000110000000000011010 36 | 00000000010000110000000000011011 37 | 00000000011000100000000000011010 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000001110 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ArithmeticTest/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .global _start 4 | _start: 5 | lui $1,0x0000 # $1 = 0x00000000 6 | lui $2,0xffff # $2 = 0xffff0000 7 | lui $3,0x0505 # $3 = 0x05050000 8 | lui $4,0x0000 # $4 = 0x00000000 9 | 10 | mthi $0 ## hi = 0x00000000 11 | mthi $2 ## hi = 0xffff0000 12 | mthi $3 ## hi = 0x05050000 13 | mfhi $4 ## $4 = 0x05050000 14 | 15 | mtlo $3 ## lo = 0x05050000 16 | mtlo $2 ## lo = 0xffff0000 17 | mtlo $1 ## lo = 0x00000000 18 | mflo $4 ## $4 = 0x00000000 19 | 20 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000010000000000000000 2 | 00111100000000101111111111111111 3 | 00111100000000110000010100000101 4 | 00111100000001000000000000000000 5 | 00000000000000000000000000010001 6 | 00000000010000000000000000010001 7 | 00000000011000000000000000010001 8 | 00000000000000000010000000010000 9 | 00000000011000000000000000010011 10 | 00000000010000000000000000010011 11 | 00000000001000000000000000010011 12 | 00000000000000000010000000010010 13 | 00000000000000000000000000011110 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3c010000 4 | 3c02ffff 5 | 3c030505 6 | 3c040000 7 | 00000011 8 | 00400011 9 | 00600011 10 | 00002010 11 | 00600013 12 | 00400013 13 | 00200013 14 | 00002012 15 | 0000001e 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000010000000000000000 2 | 00111100000000101111111111111111 3 | 00111100000000110000010100000101 4 | 00111100000001000000000000000000 5 | 00000000000000000000000000010001 6 | 00000000010000000000000000010001 7 | 00000000011000000000000000010001 8 | 00000000000000000010000000010000 9 | 00000000011000000000000000010011 10 | 00000000010000000000000000010011 11 | 00000000001000000000000000010011 12 | 00000000000000000010000000010010 13 | 00000000000000000000000000011110 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/DataMoveInstTest/obj/test.s: -------------------------------------------------------------------------------- 1 | 2 | main.elf: file format elf32-tradlittlemips 3 | main.elf 4 | 5 | 6 | Disassembly of section .text: 7 | 8 | bfc00000 <_ftext>: 9 | /home/ghj/Desktop/func/start.S:11 10 | bfc00000: 3c010000 lui at,0x0 11 | /home/ghj/Desktop/func/start.S:12 12 | bfc00004: 3c02ffff lui v0,0xffff 13 | /home/ghj/Desktop/func/start.S:13 14 | bfc00008: 3c030505 lui v1,0x505 15 | /home/ghj/Desktop/func/start.S:14 16 | bfc0000c: 3c040000 lui a0,0x0 17 | /home/ghj/Desktop/func/start.S:16 18 | bfc00010: 00000011 mthi zero 19 | /home/ghj/Desktop/func/start.S:17 20 | bfc00014: 00400011 mthi v0 21 | /home/ghj/Desktop/func/start.S:18 22 | bfc00018: 00600011 mthi v1 23 | /home/ghj/Desktop/func/start.S:19 24 | bfc0001c: 00002010 mfhi a0 25 | /home/ghj/Desktop/func/start.S:21 26 | bfc00020: 00600013 mtlo v1 27 | /home/ghj/Desktop/func/start.S:22 28 | bfc00024: 00400013 mtlo v0 29 | /home/ghj/Desktop/func/start.S:23 30 | bfc00028: 00200013 mtlo at 31 | /home/ghj/Desktop/func/start.S:24 32 | bfc0002c: 00002012 mflo a0 33 | _ftext(): 34 | bfc00030: 0000001e 0x1e 35 | ... 36 | 37 | Disassembly of section .data: 38 | 39 | 80000000 <__CTOR_LIST__>: 40 | ... 41 | 42 | 80000008 <__CTOR_END__>: 43 | ... 44 | 45 | Disassembly of section .debug_aranges: 46 | 47 | 00000000 <.debug_aranges>: 48 | 0: 0000001c 0x1c 49 | 4: 00000002 srl zero,zero,0x0 50 | 8: 00040000 sll zero,a0,0x0 51 | c: 00000000 nop 52 | 10: bfc00000 0xbfc00000 53 | 14: 00000030 0x30 54 | ... 55 | 56 | Disassembly of section .debug_line: 57 | 58 | 00000000 <.debug_line>: 59 | 0: 0000003e 0x3e 60 | 4: 001e0002 srl zero,s8,0x0 61 | 8: 01010000 0x1010000 62 | c: 000d0efb 0xd0efb 63 | 10: 01010101 0x1010101 64 | 14: 01000000 0x1000000 65 | 18: 00010000 sll zero,at,0x0 66 | 1c: 72617473 0x72617473 67 | 20: 00532e74 0x532e74 68 | 24: 00000000 nop 69 | 28: 00020500 sll zero,v0,0x14 70 | 2c: 03bfc000 0x3bfc000 71 | 30: 4b4b010a c2 0x14b010a 72 | 34: 4b4b4c4b c2 0x14b4c4b 73 | 38: 4b4b4c4b c2 0x14b4c4b 74 | 3c: 0004024b 0x4024b 75 | 40: Address 0x0000000000000040 is out of bounds. 76 | 77 | 78 | Disassembly of section .debug_info: 79 | 80 | 00000000 <.debug_info>: 81 | 0: 00000044 0x44 82 | 4: 00000002 srl zero,zero,0x0 83 | 8: 01040000 0x1040000 84 | c: 00000000 nop 85 | 10: bfc00000 0xbfc00000 86 | 14: bfc00030 0xbfc00030 87 | 18: 72617473 0x72617473 88 | 1c: 00532e74 0x532e74 89 | 20: 6d6f682f 0x6d6f682f 90 | 24: 68672f65 0x68672f65 91 | 28: 65442f6a 0x65442f6a 92 | 2c: 6f746b73 0x6f746b73 93 | 30: 75662f70 jalx 598bdc0 94 | 34: 4700636e c1 0x100636e 95 | 38: 4120554e 0x4120554e 96 | 3c: 2e322053 sltiu s2,s1,8275 97 | 40: 352e3831 ori t6,t1,0x3831 98 | 44: 80010030 lb at,48(zero) 99 | 100 | Disassembly of section .debug_abbrev: 101 | 102 | 00000000 <.debug_abbrev>: 103 | 0: 10001101 b 4408 104 | 4: 12011106 beq s0,at,4420 105 | 8: 1b080301 0x1b080301 106 | c: 13082508 beq t8,t0,9430 107 | 10: 00000005 0x5 108 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .global _start 3 | .set noat 4 | _start: 5 | lui $1,0x0101 ## $1 = 0x01010000 6 | ori $1,$1,0x0101 ## S1 = 0x01010101 7 | ori $2,$1,0x1100 ## $2 = $1 | 0x1100 = 0x01011101 8 | or $1,$1,$2 ## $1 = $1 | $2 = 0x01011101 9 | andi $3,$1,0x00fe ## $3 = $1 & 0x00fe = 0x00000000 10 | and $1,$3,$1 ## $1 = $3 & $1 = 0x00000000 11 | xori $4,$1,0xff00 ## $4 = $1 ^ 0xff00 = 0x0000ff00 12 | xor $1,$4,$1 ## $1 = $4 ^ $1 = 0x0000ff00 13 | nor $1,$4,$1 ## $1 = $4 ~^ $1 = 0xffff00ff nor is "not or" 14 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000010000000100000001 2 | 00110100001000010000000100000001 3 | 00110100001000100001000100000000 4 | 00000000001000100000100000100101 5 | 00110000001000110000000011111110 6 | 00000000011000010000100000100100 7 | 00111000001001001111111100000000 8 | 00000000100000010000100000100110 9 | 00000000100000010000100000100111 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000011110 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3c010101 4 | 34210101 5 | 34221100 6 | 00220825 7 | 302300fe 8 | 00610824 9 | 3824ff00 10 | 00810826 11 | 00810827 12 | 00000000 13 | 00000000 14 | 00000000 15 | 0000001e 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000010000000100000001 2 | 00110100001000010000000100000001 3 | 00110100001000100001000100000000 4 | 00000000001000100000100000100101 5 | 00110000001000110000000011111110 6 | 00000000011000010000100000100100 7 | 00111000001001001111111100000000 8 | 00000000100000010000100000100110 9 | 00000000100000010000100000100111 10 | 00000000000000000000000000000000 11 | 00000000000000000000000000000000 12 | 00000000000000000000000000000000 13 | 00000000000000000000000000011110 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/LogicInstTest/obj/test.s: -------------------------------------------------------------------------------- 1 | 2 | main.elf: file format elf32-tradlittlemips 3 | main.elf 4 | 5 | 6 | Disassembly of section .text: 7 | 8 | bfc00000 <_ftext>: 9 | /home/ghj/Desktop/func/start.S:11 10 | bfc00000: 3c010101 lui at,0x101 11 | /home/ghj/Desktop/func/start.S:12 12 | bfc00004: 34210101 ori at,at,0x101 13 | /home/ghj/Desktop/func/start.S:13 14 | bfc00008: 34221100 ori v0,at,0x1100 15 | /home/ghj/Desktop/func/start.S:14 16 | bfc0000c: 00220825 or at,at,v0 17 | /home/ghj/Desktop/func/start.S:15 18 | bfc00010: 302300fe andi v1,at,0xfe 19 | /home/ghj/Desktop/func/start.S:16 20 | bfc00014: 00610824 and at,v1,at 21 | /home/ghj/Desktop/func/start.S:17 22 | bfc00018: 3824ff00 xori a0,at,0xff00 23 | /home/ghj/Desktop/func/start.S:18 24 | bfc0001c: 00810826 xor at,a0,at 25 | /home/ghj/Desktop/func/start.S:19 26 | bfc00020: 00810827 nor at,a0,at 27 | ... 28 | _ftext(): 29 | bfc00030: 0000001e 0x1e 30 | ... 31 | 32 | Disassembly of section .data: 33 | 34 | 80000000 <__CTOR_LIST__>: 35 | ... 36 | 37 | 80000008 <__CTOR_END__>: 38 | ... 39 | 40 | Disassembly of section .debug_aranges: 41 | 42 | 00000000 <.debug_aranges>: 43 | 0: 0000001c 0x1c 44 | 4: 00000002 srl zero,zero,0x0 45 | 8: 00040000 sll zero,a0,0x0 46 | c: 00000000 nop 47 | 10: bfc00000 0xbfc00000 48 | 14: 00000024 and zero,zero,zero 49 | ... 50 | 51 | Disassembly of section .debug_line: 52 | 53 | 00000000 <.debug_line>: 54 | 0: 0000003b 0x3b 55 | 4: 001e0002 srl zero,s8,0x0 56 | 8: 01010000 0x1010000 57 | c: 000d0efb 0xd0efb 58 | 10: 01010101 0x1010101 59 | 14: 01000000 0x1000000 60 | 18: 00010000 sll zero,at,0x0 61 | 1c: 72617473 0x72617473 62 | 20: 00532e74 0x532e74 63 | 24: 00000000 nop 64 | 28: 00020500 sll zero,v0,0x14 65 | 2c: 03bfc000 0x3bfc000 66 | 30: 4b4b010a c2 0x14b010a 67 | 34: 4b4b4b4b c2 0x14b4b4b 68 | 38: 04024b4b 0x4024b4b 69 | 3c: Address 0x000000000000003c is out of bounds. 70 | 71 | 72 | Disassembly of section .debug_info: 73 | 74 | 00000000 <.debug_info>: 75 | 0: 00000044 0x44 76 | 4: 00000002 srl zero,zero,0x0 77 | 8: 01040000 0x1040000 78 | c: 00000000 nop 79 | 10: bfc00000 0xbfc00000 80 | 14: bfc00024 0xbfc00024 81 | 18: 72617473 0x72617473 82 | 1c: 00532e74 0x532e74 83 | 20: 6d6f682f 0x6d6f682f 84 | 24: 68672f65 0x68672f65 85 | 28: 65442f6a 0x65442f6a 86 | 2c: 6f746b73 0x6f746b73 87 | 30: 75662f70 jalx 598bdc0 88 | 34: 4700636e c1 0x100636e 89 | 38: 4120554e 0x4120554e 90 | 3c: 2e322053 sltiu s2,s1,8275 91 | 40: 352e3831 ori t6,t1,0x3831 92 | 44: 80010030 lb at,48(zero) 93 | 94 | Disassembly of section .debug_abbrev: 95 | 96 | 00000000 <.debug_abbrev>: 97 | 0: 10001101 b 4408 98 | 4: 12011106 beq s0,at,4420 99 | 8: 1b080301 0x1b080301 100 | c: 13082508 beq t8,t0,9430 101 | 10: 00000005 0x5 102 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/Readme.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/Readme.txt -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .set noreorder 4 | .set nomacro 5 | .global _start 6 | _start: 7 | ori $3,$0,0xeeff 8 | sb $3,0x3($0) # [0x3] = 0xff 9 | srl $3,$3,8 10 | sb $3,0x2($0) # [0x2] = 0xee 11 | ori $3,$0,0xccdd 12 | sb $3,0x1($0) # [0x1] = 0xdd 13 | srl $3,$3,8 14 | sb $3,0x0($0) # [0x0] = 0xcc 15 | lb $1,0x3($0) ## $1 = 0xffffffff 16 | lbu $1,0x2($0) ## $1 = 0x000000ee 17 | nop 18 | 19 | ori $3,$0,0xaabb 20 | sh $3,0x4($0) # [0x4] = 0xaa, [0x5] = 0xbb 21 | lhu $1,0x4($0) ## $1 = 0x0000aabb 22 | lh $1,0x4($0) ## $1 = 0xffffaabb 23 | 24 | ori $3,$0,0x8899 25 | sh $3,0x6($0) # [0x6] = 0x88, [0x7] = 0x99 26 | lh $1,0x6($0) ## $1 = 0xffff8899 27 | lhu $1,0x6($0) ## $1 = 0x00008899 28 | 29 | ori $3,$0,0x4455 30 | sll $3,$3,0x10 31 | ori $3,$3,0x6677 32 | sw $3,0x8($0) # [0x8] = 0x44, [0x9]= 0x55, [0xa]= 0x66, [0xb] = 0x77 33 | lw $1,0x8($0) ## $1 = 0x44556677 34 | 35 | _loop: 36 | j _loop 37 | nop 38 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000111110111011111111 2 | 10100000000000110000000000000011 3 | 00000000000000110001101000000010 4 | 10100000000000110000000000000010 5 | 00110100000000111100110011011101 6 | 10100000000000110000000000000001 7 | 00000000000000110001101000000010 8 | 10100000000000110000000000000000 9 | 10000000000000010000000000000011 10 | 10010000000000010000000000000010 11 | 00000000000000000000000000000000 12 | 00110100000000111010101010111011 13 | 10100100000000110000000000000100 14 | 10010100000000010000000000000100 15 | 10000100000000010000000000000100 16 | 00110100000000111000100010011001 17 | 10100100000000110000000000000110 18 | 10000100000000010000000000000110 19 | 10010100000000010000000000000110 20 | 00110100000000110100010001010101 21 | 00000000000000110001110000000000 22 | 00110100011000110110011001110111 23 | 10101100000000110000000000001000 24 | 10001100000000010000000000001000 25 | 00001011111100000000000000011000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000001010 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00000000000000000000000000000000 35 | 00000000000000000000000000000000 36 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3403eeff 4 | a0030003 5 | 00031a02 6 | a0030002 7 | 3403ccdd 8 | a0030001 9 | 00031a02 10 | a0030000 11 | 80010003 12 | 90010002 13 | 00000000 14 | 3403aabb 15 | a4030004 16 | 94010004 17 | 84010004 18 | 34038899 19 | a4030006 20 | 84010006 21 | 94010006 22 | 34034455 23 | 00031c00 24 | 34636677 25 | ac030008 26 | 8c010008 27 | 0bf00018 28 | 00000000 29 | 00000000 30 | 00000000 31 | 0000000a 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000111110111011111111 2 | 10100000000000110000000000000011 3 | 00000000000000110001101000000010 4 | 10100000000000110000000000000010 5 | 00110100000000111100110011011101 6 | 10100000000000110000000000000001 7 | 00000000000000110001101000000010 8 | 10100000000000110000000000000000 9 | 10000000000000010000000000000011 10 | 10010000000000010000000000000010 11 | 00000000000000000000000000000000 12 | 00110100000000111010101010111011 13 | 10100100000000110000000000000100 14 | 10010100000000010000000000000100 15 | 10000100000000010000000000000100 16 | 00110100000000111000100010011001 17 | 10100100000000110000000000000110 18 | 10000100000000010000000000000110 19 | 10010100000000010000000000000110 20 | 00110100000000110100010001010101 21 | 00000000000000110001110000000000 22 | 00110100011000110110011001110111 23 | 10101100000000110000000000001000 24 | 10001100000000010000000000001000 25 | 00001011111100000000000000011000 26 | 00000000000000000000000000000000 27 | 00000000000000000000000000000000 28 | 00000000000000000000000000000000 29 | 00000000000000000000000000001010 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00000000000000000000000000000000 35 | 00000000000000000000000000000000 36 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/S_LInstTest/obj/test.s: -------------------------------------------------------------------------------- 1 | 2 | main.elf: file format elf32-tradlittlemips 3 | main.elf 4 | 5 | 6 | Disassembly of section .text: 7 | 8 | bfc00000 <_ftext>: 9 | /home/ghj/Desktop/func/start.S:12 10 | bfc00000: 3403eeff li v1,0xeeff 11 | /home/ghj/Desktop/func/start.S:13 12 | bfc00004: a0030003 sb v1,3(zero) 13 | /home/ghj/Desktop/func/start.S:14 14 | bfc00008: 00031a02 srl v1,v1,0x8 15 | /home/ghj/Desktop/func/start.S:15 16 | bfc0000c: a0030002 sb v1,2(zero) 17 | /home/ghj/Desktop/func/start.S:16 18 | bfc00010: 3403ccdd li v1,0xccdd 19 | /home/ghj/Desktop/func/start.S:17 20 | bfc00014: a0030001 sb v1,1(zero) 21 | /home/ghj/Desktop/func/start.S:18 22 | bfc00018: 00031a02 srl v1,v1,0x8 23 | /home/ghj/Desktop/func/start.S:19 24 | bfc0001c: a0030000 sb v1,0(zero) 25 | /home/ghj/Desktop/func/start.S:20 26 | bfc00020: 80010003 lb at,3(zero) 27 | /home/ghj/Desktop/func/start.S:21 28 | bfc00024: 90010002 lbu at,2(zero) 29 | /home/ghj/Desktop/func/start.S:22 30 | bfc00028: 00000000 nop 31 | /home/ghj/Desktop/func/start.S:24 32 | bfc0002c: 3403aabb li v1,0xaabb 33 | /home/ghj/Desktop/func/start.S:25 34 | bfc00030: a4030004 sh v1,4(zero) 35 | /home/ghj/Desktop/func/start.S:26 36 | bfc00034: 94010004 lhu at,4(zero) 37 | /home/ghj/Desktop/func/start.S:27 38 | bfc00038: 84010004 lh at,4(zero) 39 | /home/ghj/Desktop/func/start.S:29 40 | bfc0003c: 34038899 li v1,0x8899 41 | /home/ghj/Desktop/func/start.S:30 42 | bfc00040: a4030006 sh v1,6(zero) 43 | /home/ghj/Desktop/func/start.S:31 44 | bfc00044: 84010006 lh at,6(zero) 45 | /home/ghj/Desktop/func/start.S:32 46 | bfc00048: 94010006 lhu at,6(zero) 47 | /home/ghj/Desktop/func/start.S:34 48 | bfc0004c: 34034455 li v1,0x4455 49 | /home/ghj/Desktop/func/start.S:35 50 | bfc00050: 00031c00 sll v1,v1,0x10 51 | /home/ghj/Desktop/func/start.S:36 52 | bfc00054: 34636677 ori v1,v1,0x6677 53 | /home/ghj/Desktop/func/start.S:37 54 | bfc00058: ac030008 sw v1,8(zero) 55 | /home/ghj/Desktop/func/start.S:38 56 | bfc0005c: 8c010008 lw at,8(zero) 57 | 58 | bfc00060 <_loop>: 59 | /home/ghj/Desktop/func/start.S:41 60 | bfc00060: 0bf00018 j bfc00060 <_loop> 61 | /home/ghj/Desktop/func/start.S:42 62 | bfc00064: 00000000 nop 63 | ... 64 | _loop(): 65 | bfc00070: 0000000a 0xa 66 | ... 67 | 68 | Disassembly of section .data: 69 | 70 | 80000000 <__CTOR_LIST__>: 71 | ... 72 | 73 | 80000008 <__CTOR_END__>: 74 | ... 75 | 76 | Disassembly of section .debug_aranges: 77 | 78 | 00000000 <.debug_aranges>: 79 | 0: 0000001c 0x1c 80 | 4: 00000002 srl zero,zero,0x0 81 | 8: 00040000 sll zero,a0,0x0 82 | c: 00000000 nop 83 | 10: bfc00000 0xbfc00000 84 | 14: 00000068 0x68 85 | ... 86 | 87 | Disassembly of section .debug_line: 88 | 89 | 00000000 <.debug_line>: 90 | 0: 0000004c syscall 0x1 91 | 4: 001e0002 srl zero,s8,0x0 92 | 8: 01010000 0x1010000 93 | c: 000d0efb 0xd0efb 94 | 10: 01010101 0x1010101 95 | 14: 01000000 0x1000000 96 | 18: 00010000 sll zero,at,0x0 97 | 1c: 72617473 0x72617473 98 | 20: 00532e74 0x532e74 99 | 24: 00000000 nop 100 | 28: 00020500 sll zero,v0,0x14 101 | 2c: 03bfc000 0x3bfc000 102 | 30: 4b4b010b c2 0x14b010b 103 | 34: 4b4b4b4b c2 0x14b4b4b 104 | 38: 4b4b4b4b c2 0x14b4b4b 105 | 3c: 4b4b4b4c c2 0x14b4b4c 106 | 40: 4b4b4b4c c2 0x14b4b4c 107 | 44: 4b4b4b4c c2 0x14b4b4c 108 | 48: 024b4d4b 0x24b4d4b 109 | 4c: 01010004 sllv zero,at,t0 110 | 111 | Disassembly of section .debug_info: 112 | 113 | 00000000 <.debug_info>: 114 | 0: 00000044 0x44 115 | 4: 00000002 srl zero,zero,0x0 116 | 8: 01040000 0x1040000 117 | c: 00000000 nop 118 | 10: bfc00000 0xbfc00000 119 | 14: bfc00068 0xbfc00068 120 | 18: 72617473 0x72617473 121 | 1c: 00532e74 0x532e74 122 | 20: 6d6f682f 0x6d6f682f 123 | 24: 68672f65 0x68672f65 124 | 28: 65442f6a 0x65442f6a 125 | 2c: 6f746b73 0x6f746b73 126 | 30: 75662f70 jalx 598bdc0 127 | 34: 4700636e c1 0x100636e 128 | 38: 4120554e 0x4120554e 129 | 3c: 2e322053 sltiu s2,s1,8275 130 | 40: 352e3831 ori t6,t1,0x3831 131 | 44: 80010030 lb at,48(zero) 132 | 133 | Disassembly of section .debug_abbrev: 134 | 135 | 00000000 <.debug_abbrev>: 136 | 0: 10001101 b 4408 137 | 4: 12011106 beq s0,at,4420 138 | 8: 1b080301 0x1b080301 139 | c: 13082508 beq t8,t0,9430 140 | 10: 00000005 0x5 141 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .global _start 4 | _start: 5 | lui $2,0x0404 6 | ori $2,$2,0x0404 7 | ori $7,$0,0x7 8 | ori $5,$0,0x5 9 | ori $8,$0,0x8 10 | sll $2,$2,8 ## $2 = 0x40404040 sll 8 = 0x04040400 11 | sllv $2,$2,$7 ## $2 = 0x04040400 sll 7 = 0x02020000 12 | srl $2,$2,8 ## $2 = 0x02020000 srl 8 = 0x00020200 13 | srlv $2,$2,$5 ## $2 = 0x00020200 srl 5 = 0x00001010 14 | nop 15 | sll $2,$2,19 ## $2 = 0x00001010 sll 19 = 0x80800000 16 | sra $2,$2,16 ## $2 = 0x80800000 sra 16 = 0xffff8080 17 | srav $2,$2,$8 ## $2 = 0xffff8080 sra 8 = 0xffffff80 18 | 19 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000100000010000000100 2 | 00110100010000100000010000000100 3 | 00110100000001110000000000000111 4 | 00110100000001010000000000000101 5 | 00110100000010000000000000001000 6 | 00000000000000100001001000000000 7 | 00000000111000100001000000000100 8 | 00000000000000100001001000000010 9 | 00000000101000100001000000000110 10 | 00000000000000000000000000000000 11 | 00000000000000100001010011000000 12 | 00000000000000100001010000000011 13 | 00000001000000100001000000000111 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000110100100 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 3c020404 4 | 34420404 5 | 34070007 6 | 34050005 7 | 34080008 8 | 00021200 9 | 00e21004 10 | 00021202 11 | 00a21006 12 | 00000000 13 | 000214c0 14 | 00021403 15 | 01021007 16 | 00000000 17 | 00000000 18 | 00000000 19 | 000001a4 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00000000 26 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00111100000000100000010000000100 2 | 00110100010000100000010000000100 3 | 00110100000001110000000000000111 4 | 00110100000001010000000000000101 5 | 00110100000010000000000000001000 6 | 00000000000000100001001000000000 7 | 00000000111000100001000000000100 8 | 00000000000000100001001000000010 9 | 00000000101000100001000000000110 10 | 00000000000000000000000000000000 11 | 00000000000000100001010011000000 12 | 00000000000000100001010000000011 13 | 00000001000000100001000000000111 14 | 00000000000000000000000000000000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000000000000000000000110100100 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00000000000000000000000000000000 22 | 00000000000000000000000000000000 23 | 00000000000000000000000000000000 24 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/ShiftInstTest/obj/test.s: -------------------------------------------------------------------------------- 1 | 2 | main.elf: file format elf32-tradlittlemips 3 | main.elf 4 | 5 | 6 | Disassembly of section .text: 7 | 8 | bfc00000 <_ftext>: 9 | /home/ghj/Desktop/func/start.S:13 10 | bfc00000: 3c020404 lui v0,0x404 11 | /home/ghj/Desktop/func/start.S:14 12 | bfc00004: 34420404 ori v0,v0,0x404 13 | /home/ghj/Desktop/func/start.S:15 14 | bfc00008: 34070007 li a3,0x7 15 | /home/ghj/Desktop/func/start.S:16 16 | bfc0000c: 34050005 li a1,0x5 17 | /home/ghj/Desktop/func/start.S:17 18 | bfc00010: 34080008 li t0,0x8 19 | /home/ghj/Desktop/func/start.S:18 20 | bfc00014: 00021200 sll v0,v0,0x8 21 | /home/ghj/Desktop/func/start.S:19 22 | bfc00018: 00e21004 sllv v0,v0,a3 23 | /home/ghj/Desktop/func/start.S:20 24 | bfc0001c: 00021202 srl v0,v0,0x8 25 | /home/ghj/Desktop/func/start.S:21 26 | bfc00020: 00a21006 srlv v0,v0,a1 27 | /home/ghj/Desktop/func/start.S:22 28 | bfc00024: 00000000 nop 29 | /home/ghj/Desktop/func/start.S:23 30 | bfc00028: 000214c0 sll v0,v0,0x13 31 | /home/ghj/Desktop/func/start.S:24 32 | bfc0002c: 00021403 sra v0,v0,0x10 33 | /home/ghj/Desktop/func/start.S:25 34 | bfc00030: 01021007 srav v0,v0,t0 35 | ... 36 | _ftext(): 37 | bfc00040: 000001a4 0x1a4 38 | ... 39 | 40 | Disassembly of section .data: 41 | 42 | 80000000 <__CTOR_LIST__>: 43 | ... 44 | 45 | 80000008 <__CTOR_END__>: 46 | ... 47 | 48 | Disassembly of section .debug_aranges: 49 | 50 | 00000000 <.debug_aranges>: 51 | 0: 0000001c 0x1c 52 | 4: 00000002 srl zero,zero,0x0 53 | 8: 00040000 sll zero,a0,0x0 54 | c: 00000000 nop 55 | 10: bfc00000 0xbfc00000 56 | 14: 00000034 0x34 57 | ... 58 | 59 | Disassembly of section .debug_line: 60 | 61 | 00000000 <.debug_line>: 62 | 0: 0000003f 0x3f 63 | 4: 001e0002 srl zero,s8,0x0 64 | 8: 01010000 0x1010000 65 | c: 000d0efb 0xd0efb 66 | 10: 01010101 0x1010101 67 | 14: 01000000 0x1000000 68 | 18: 00010000 sll zero,at,0x0 69 | 1c: 72617473 0x72617473 70 | 20: 00532e74 0x532e74 71 | 24: 00000000 nop 72 | 28: 00020500 sll zero,v0,0x14 73 | 2c: 03bfc000 0x3bfc000 74 | 30: 4b4b010c c2 0x14b010c 75 | 34: 4b4b4b4b c2 0x14b4b4b 76 | 38: 4b4b4b4b c2 0x14b4b4b 77 | 3c: 04024b4b 0x4024b4b 78 | 40: Address 0x0000000000000040 is out of bounds. 79 | 80 | 81 | Disassembly of section .debug_info: 82 | 83 | 00000000 <.debug_info>: 84 | 0: 00000044 0x44 85 | 4: 00000002 srl zero,zero,0x0 86 | 8: 01040000 0x1040000 87 | c: 00000000 nop 88 | 10: bfc00000 0xbfc00000 89 | 14: bfc00034 0xbfc00034 90 | 18: 72617473 0x72617473 91 | 1c: 00532e74 0x532e74 92 | 20: 6d6f682f 0x6d6f682f 93 | 24: 68672f65 0x68672f65 94 | 28: 65442f6a 0x65442f6a 95 | 2c: 6f746b73 0x6f746b73 96 | 30: 75662f70 jalx 598bdc0 97 | 34: 4700636e c1 0x100636e 98 | 38: 4120554e 0x4120554e 99 | 3c: 2e322053 sltiu s2,s1,8275 100 | 40: 352e3831 ori t6,t1,0x3831 101 | 44: 80010030 lb at,48(zero) 102 | 103 | Disassembly of section .debug_abbrev: 104 | 105 | 00000000 <.debug_abbrev>: 106 | 0: 10001101 b 4408 107 | 4: 12011106 beq s0,at,4420 108 | 8: 1b080301 0x1b080301 109 | c: 13082508 beq t8,t0,9430 110 | 10: 00000005 0x5 111 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .set noreorder 4 | .set nomacro 5 | .global _start 6 | _start: 7 | addiu $1,$0,0x0001 ## $1 = 0x1 8 | j 0x20 9 | addiu $1,$1,0x0001 ## $1 = 0x2 10 | addiu $1,$1,0x1111 11 | addiu $1,$1,0x1100 12 | 13 | .org 0x20 14 | addiu $1,$1,0x0001 ## $1 = 0x3 15 | jal 0x40 16 | nop 17 | addiu $1,$1,0x0001 ## r1 = 0x4 18 | addiu $1,$1,0x0001 ## r1 = 0x5 19 | j 0x60 20 | nop 21 | 22 | .org 0x40 23 | 24 | jalr $2,$31 25 | or $3,$2,$0 ## $3 = 0xb0000048 26 | addiu $1,$1,0x0001 ## $1 = 0x8 27 | addiu $1,$1,0x0001 ## $1 = 0x9 28 | addiu $1,$1,0x0001 ## $1 = 0xa 29 | j 0x80 30 | nop 31 | 32 | .org 0x60 33 | addiu $1,$1,0x0001 ## $1 = 0x6 34 | jr $3 35 | addiu $1,$1,0x0001 ## $1 = 0x7 36 | addiu $1,$1,0x1111 37 | addiu $1,$1,0x1100 38 | 39 | .org 0x80 40 | nop 41 | 42 | _loop: 43 | j _loop 44 | nop 45 | 46 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00100100000000010000000000000001 2 | 00001000000000000000000000001000 3 | 00100100001000010000000000000001 4 | 00100100001000010001000100010001 5 | 00100100001000010001000100000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00100100001000010000000000000001 10 | 00001100000000000000000000010000 11 | 00000000000000000000000000000000 12 | 00100100001000010000000000000001 13 | 00100100001000010000000000000001 14 | 00001000000000000000000000011000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000011111000000001000000001001 18 | 00000000010000000001100000100101 19 | 00100100001000010000000000000001 20 | 00100100001000010000000000000001 21 | 00100100001000010000000000000001 22 | 00001000000000000000000000100000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00100100001000010000000000000001 26 | 00000000011000000000000000001000 27 | 00100100001000010000000000000001 28 | 00100100001000010001000100010001 29 | 00100100001000010001000100000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00001011111100000000000000100001 35 | 00000000000000000000000000000000 36 | 00000000000000000000000000000000 37 | 10000000000000000000000000001110 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 24010001 4 | 08000008 5 | 24210001 6 | 24211111 7 | 24211100 8 | 00000000 9 | 00000000 10 | 00000000 11 | 24210001 12 | 0c000010 13 | 00000000 14 | 24210001 15 | 24210001 16 | 08000018 17 | 00000000 18 | 00000000 19 | 03e01009 20 | 00401825 21 | 24210001 22 | 24210001 23 | 24210001 24 | 08000020 25 | 00000000 26 | 00000000 27 | 24210001 28 | 00600008 29 | 24210001 30 | 24211111 31 | 24211100 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 0bf00021 37 | 00000000 38 | 00000000 39 | 8000000e 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00100100000000010000000000000001 2 | 00001000000000000000000000001000 3 | 00100100001000010000000000000001 4 | 00100100001000010001000100010001 5 | 00100100001000010001000100000000 6 | 00000000000000000000000000000000 7 | 00000000000000000000000000000000 8 | 00000000000000000000000000000000 9 | 00100100001000010000000000000001 10 | 00001100000000000000000000010000 11 | 00000000000000000000000000000000 12 | 00100100001000010000000000000001 13 | 00100100001000010000000000000001 14 | 00001000000000000000000000011000 15 | 00000000000000000000000000000000 16 | 00000000000000000000000000000000 17 | 00000011111000000001000000001001 18 | 00000000010000000001100000100101 19 | 00100100001000010000000000000001 20 | 00100100001000010000000000000001 21 | 00100100001000010000000000000001 22 | 00001000000000000000000000100000 23 | 00000000000000000000000000000000 24 | 00000000000000000000000000000000 25 | 00100100001000010000000000000001 26 | 00000000011000000000000000001000 27 | 00100100001000010000000000000001 28 | 00100100001000010001000100010001 29 | 00100100001000010001000100000000 30 | 00000000000000000000000000000000 31 | 00000000000000000000000000000000 32 | 00000000000000000000000000000000 33 | 00000000000000000000000000000000 34 | 00001011111100000000000000100001 35 | 00000000000000000000000000000000 36 | 00000000000000000000000000000000 37 | 10000000000000000000000000001110 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test1/obj/test.s: -------------------------------------------------------------------------------- 1 | 2 | main.elf: file format elf32-tradlittlemips 3 | main.elf 4 | 5 | 6 | Disassembly of section .text: 7 | 8 | bfc00000 <_ftext>: 9 | /home/ghj/Desktop/func/start.S:12 10 | bfc00000: 24010001 li at,1 11 | /home/ghj/Desktop/func/start.S:13 12 | bfc00004: 08000008 j b0000020 <_gp+0x2fff8020> 13 | /home/ghj/Desktop/func/start.S:14 14 | bfc00008: 24210001 addiu at,at,1 15 | /home/ghj/Desktop/func/start.S:15 16 | bfc0000c: 24211111 addiu at,at,4369 17 | /home/ghj/Desktop/func/start.S:16 18 | bfc00010: 24211100 addiu at,at,4352 19 | ... 20 | /home/ghj/Desktop/func/start.S:19 21 | bfc00020: 24210001 addiu at,at,1 22 | /home/ghj/Desktop/func/start.S:20 23 | bfc00024: 0c000010 jal b0000040 <_gp+0x2fff8040> 24 | /home/ghj/Desktop/func/start.S:21 25 | bfc00028: 00000000 nop 26 | /home/ghj/Desktop/func/start.S:22 27 | bfc0002c: 24210001 addiu at,at,1 28 | /home/ghj/Desktop/func/start.S:23 29 | bfc00030: 24210001 addiu at,at,1 30 | /home/ghj/Desktop/func/start.S:24 31 | bfc00034: 08000018 j b0000060 <_gp+0x2fff8060> 32 | /home/ghj/Desktop/func/start.S:25 33 | bfc00038: 00000000 nop 34 | bfc0003c: 00000000 nop 35 | /home/ghj/Desktop/func/start.S:29 36 | bfc00040: 03e01009 jalr v0,ra 37 | /home/ghj/Desktop/func/start.S:30 38 | bfc00044: 00401825 move v1,v0 39 | /home/ghj/Desktop/func/start.S:31 40 | bfc00048: 24210001 addiu at,at,1 41 | /home/ghj/Desktop/func/start.S:32 42 | bfc0004c: 24210001 addiu at,at,1 43 | /home/ghj/Desktop/func/start.S:33 44 | bfc00050: 24210001 addiu at,at,1 45 | /home/ghj/Desktop/func/start.S:34 46 | bfc00054: 08000020 j b0000080 <_gp+0x2fff8080> 47 | /home/ghj/Desktop/func/start.S:35 48 | bfc00058: 00000000 nop 49 | bfc0005c: 00000000 nop 50 | /home/ghj/Desktop/func/start.S:38 51 | bfc00060: 24210001 addiu at,at,1 52 | /home/ghj/Desktop/func/start.S:39 53 | bfc00064: 00600008 jr v1 54 | /home/ghj/Desktop/func/start.S:40 55 | bfc00068: 24210001 addiu at,at,1 56 | /home/ghj/Desktop/func/start.S:41 57 | bfc0006c: 24211111 addiu at,at,4369 58 | /home/ghj/Desktop/func/start.S:42 59 | bfc00070: 24211100 addiu at,at,4352 60 | ... 61 | 62 | bfc00084 <_loop>: 63 | /home/ghj/Desktop/func/start.S:48 64 | bfc00084: 0bf00021 j bfc00084 <_loop> 65 | /home/ghj/Desktop/func/start.S:49 66 | bfc00088: 00000000 nop 67 | _loop(): 68 | bfc0008c: 00000000 nop 69 | bfc00090: 8000000e lb zero,14(zero) 70 | ... 71 | 72 | Disassembly of section .data: 73 | 74 | 80000000 <__CTOR_LIST__>: 75 | ... 76 | 77 | 80000008 <__CTOR_END__>: 78 | ... 79 | 80 | Disassembly of section .debug_aranges: 81 | 82 | 00000000 <.debug_aranges>: 83 | 0: 0000001c 0x1c 84 | 4: 00000002 srl zero,zero,0x0 85 | 8: 00040000 sll zero,a0,0x0 86 | c: 00000000 nop 87 | 10: bfc00000 0xbfc00000 88 | 14: 0000008c syscall 0x2 89 | ... 90 | 91 | Disassembly of section .debug_line: 92 | 93 | 00000000 <.debug_line>: 94 | 0: 0000004d break 0x0,0x1 95 | 4: 001e0002 srl zero,s8,0x0 96 | 8: 01010000 0x1010000 97 | c: 000d0efb 0xd0efb 98 | 10: 01010101 0x1010101 99 | 14: 01000000 0x1000000 100 | 18: 00010000 sll zero,at,0x0 101 | 1c: 72617473 0x72617473 102 | 20: 00532e74 0x532e74 103 | 24: 00000000 nop 104 | 28: 00020500 sll zero,v0,0x14 105 | 2c: 03bfc000 0x3bfc000 106 | 30: 4b4b010b c2 0x14b010b 107 | 34: 4bf54b4b c2 0x1f54b4b 108 | 38: 4b4b4b4b c2 0x14b4b4b 109 | 3c: 4b4b864b c2 0x14b864b 110 | 40: 4b4b4b4b c2 0x14b4b4b 111 | 44: 4b4b4b85 c2 0x14b4b85 112 | 48: 4b4df54b c2 0x14df54b 113 | 4c: 01000402 0x1000402 114 | 50: Address 0x0000000000000050 is out of bounds. 115 | 116 | 117 | Disassembly of section .debug_info: 118 | 119 | 00000000 <.debug_info>: 120 | 0: 00000044 0x44 121 | 4: 00000002 srl zero,zero,0x0 122 | 8: 01040000 0x1040000 123 | c: 00000000 nop 124 | 10: bfc00000 0xbfc00000 125 | 14: bfc0008c 0xbfc0008c 126 | 18: 72617473 0x72617473 127 | 1c: 00532e74 0x532e74 128 | 20: 6d6f682f 0x6d6f682f 129 | 24: 68672f65 0x68672f65 130 | 28: 65442f6a 0x65442f6a 131 | 2c: 6f746b73 0x6f746b73 132 | 30: 75662f70 jalx 598bdc0 133 | 34: 4700636e c1 0x100636e 134 | 38: 4120554e 0x4120554e 135 | 3c: 2e322053 sltiu s2,s1,8275 136 | 40: 352e3831 ori t6,t1,0x3831 137 | 44: 80010030 lb at,48(zero) 138 | 139 | Disassembly of section .debug_abbrev: 140 | 141 | 00000000 <.debug_abbrev>: 142 | 0: 10001101 b 4408 143 | 4: 12011106 beq s0,at,4420 144 | 8: 1b080301 0x1b080301 145 | c: 13082508 beq t8,t0,9430 146 | 10: 00000005 0x5 147 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/inst_rom.S: -------------------------------------------------------------------------------- 1 | .org 0x0 2 | .set noat 3 | .set noreorder 4 | .set nomacro 5 | .global _start 6 | _start: 7 | ori $3,$0,0x8000 8 | sll $3,16 # $3 = 0x80000000 9 | ori $1,$0,0x0001 ## $1 = 0x1 10 | b sec1 11 | ori $1,$0,0x0002 ## $1 = 0x2 12 | 1: 13 | ori $1,$0,0x1111 14 | ori $1,$0,0x1100 15 | 16 | .org 0x20 17 | sec1: 18 | ori $1,$0,0x0003 ## $1 = 0x3 19 | bal s2 20 | ori $1,$0,0x1100 21 | ori $1,$0,0x1111 22 | bne $1,$0,s3 23 | nop 24 | ori $1,$0,0x1100 25 | ori $1,$0,0x1111 26 | 27 | .org 0x50 28 | s2: 29 | ori $1,$0,0x0004 ## $1 = 0x4 30 | beq $3,$3,s3 31 | or $1,$31,$0 ## $1 = 0x2c 32 | ori $1,$0,0x1111 33 | ori $1,$0,0x1100 34 | 2: 35 | ori $1,$0,0x0007 ## $1 = 0x7 36 | ori $1,$0,0x0008 ## $1 = 0x8 37 | bgtz $1,s4 38 | ori $1,$0,0x0009 ## $1 = 0x9 39 | ori $1,$0,0x1111 40 | ori $1,$0,0x1100 41 | 42 | .org 0x80 43 | s3: 44 | ori $1,$0,0x0005 ## $1 = 0x5 45 | BGEZ $1,2b 46 | ori $1,$0,0x0006 ## $1 = 0x6 47 | ori $1,$0,0x1111 48 | ori $1,$0,0x1100 49 | 50 | .org 0x100 51 | s4: 52 | ori $1,$0,0x000a ## $1 = 0xa 53 | BGEZAL $3,s3 54 | or $1,$0,$31 ## $1 = 0x10c 55 | ori $1,$0,0x000b ## $1 = 0xb 56 | ori $1,$0,0x000c ## $1 = 0xc 57 | ori $1,$0,0x000d ## $1 = 0xd 58 | ori $1,$0,0x000e ## $1 = 0xe 59 | bltz $3,s5 60 | ori $1,$0,0x000f ## $1 = 0xf 61 | ori $1,$0,0x1100 62 | 63 | 64 | .org 0x130 65 | s5: 66 | ori $1,$0,0x0010 ## $1 = 0x10 67 | blez $1,2b 68 | ori $1,$0,0x0011 ## $1 = 0x11 69 | ori $1,$0,0x0012 ## $1 = 0x12 70 | ori $1,$0,0x0013 ## $1 = 0x13 71 | bltzal $3,s6 72 | or $1,$0,$31 ## $1 = 0x14c 73 | ori $1,$0,0x1100 74 | 75 | 76 | .org 0x160 77 | s6: 78 | ori $1,$0,0x0014 ## $1 = 0x14 79 | nop 80 | 81 | 82 | 83 | _loop: 84 | j _loop 85 | nop 86 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/axi_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000111000000000000000 2 | 00000000000000110001110000000000 3 | 00110100000000010000000000000001 4 | 00010000000000000000000000000100 5 | 00110100000000010000000000000010 6 | 00110100000000010001000100010001 7 | 00110100000000010001000100000000 8 | 00000000000000000000000000000000 9 | 00110100000000010000000000000011 10 | 00000100000100010000000000001010 11 | 00110100000000010001000100000000 12 | 00110100000000010001000100010001 13 | 00010100001000000000000000010011 14 | 00000000000000000000000000000000 15 | 00110100000000010001000100000000 16 | 00110100000000010001000100010001 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00110100000000010000000000000100 22 | 00010000011000110000000000001010 23 | 00000011111000000000100000100101 24 | 00110100000000010001000100010001 25 | 00110100000000010001000100000000 26 | 00110100000000010000000000000111 27 | 00110100000000010000000000001000 28 | 00011100001000000000000000100100 29 | 00110100000000010000000000001001 30 | 00110100000000010001000100010001 31 | 00110100000000010001000100000000 32 | 00000000000000000000000000000000 33 | 00110100000000010000000000000101 34 | 00000100001000011111111111110111 35 | 00110100000000010000000000000110 36 | 00110100000000010001000100010001 37 | 00110100000000010001000100000000 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | 00000000000000000000000000000000 49 | 00000000000000000000000000000000 50 | 00000000000000000000000000000000 51 | 00000000000000000000000000000000 52 | 00000000000000000000000000000000 53 | 00000000000000000000000000000000 54 | 00000000000000000000000000000000 55 | 00000000000000000000000000000000 56 | 00000000000000000000000000000000 57 | 00000000000000000000000000000000 58 | 00000000000000000000000000000000 59 | 00000000000000000000000000000000 60 | 00000000000000000000000000000000 61 | 00000000000000000000000000000000 62 | 00000000000000000000000000000000 63 | 00000000000000000000000000000000 64 | 00000000000000000000000000000000 65 | 00110100000000010000000000001010 66 | 00000100011100011111111111011110 67 | 00000000000111110000100000100101 68 | 00110100000000010000000000001011 69 | 00110100000000010000000000001100 70 | 00110100000000010000000000001101 71 | 00110100000000010000000000001110 72 | 00000100011000000000000000000100 73 | 00110100000000010000000000001111 74 | 00110100000000010001000100000000 75 | 00000000000000000000000000000000 76 | 00000000000000000000000000000000 77 | 00110100000000010000000000010000 78 | 00011000001000001111111111001011 79 | 00110100000000010000000000010001 80 | 00110100000000010000000000010010 81 | 00110100000000010000000000010011 82 | 00000100011100000000000000000110 83 | 00000000000111110000100000100101 84 | 00110100000000010001000100000000 85 | 00000000000000000000000000000000 86 | 00000000000000000000000000000000 87 | 00000000000000000000000000000000 88 | 00000000000000000000000000000000 89 | 00110100000000010000000000010100 90 | 00000000000000000000000000000000 91 | 00001011111100000000000001011010 92 | 00000000000000000000000000000000 93 | 10000000000000000000000000001010 94 | 00000000000000000000000000000000 95 | 00000000000000000000000000000000 96 | 00000000000000000000000000000000 97 | 00000000000000000000000000000000 98 | 00000000000000000000000000000000 99 | 00000000000000000000000000000000 100 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/inst_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 34038000 4 | 00031c00 5 | 34010001 6 | 10000004 7 | 34010002 8 | 34011111 9 | 34011100 10 | 00000000 11 | 34010003 12 | 0411000a 13 | 34011100 14 | 34011111 15 | 14200013 16 | 00000000 17 | 34011100 18 | 34011111 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 34010004 24 | 1063000a 25 | 03e00825 26 | 34011111 27 | 34011100 28 | 34010007 29 | 34010008 30 | 1c200024 31 | 34010009 32 | 34011111 33 | 34011100 34 | 00000000 35 | 34010005 36 | 0421fff7 37 | 34010006 38 | 34011111 39 | 34011100 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000000 66 | 00000000 67 | 3401000a 68 | 0471ffde 69 | 001f0825 70 | 3401000b 71 | 3401000c 72 | 3401000d 73 | 3401000e 74 | 04600004 75 | 3401000f 76 | 34011100 77 | 00000000 78 | 00000000 79 | 34010010 80 | 1820ffcb 81 | 34010011 82 | 34010012 83 | 34010013 84 | 04700006 85 | 001f0825 86 | 34011100 87 | 00000000 88 | 00000000 89 | 00000000 90 | 00000000 91 | 34010014 92 | 00000000 93 | 0bf0005a 94 | 00000000 95 | 8000000a 96 | 00000000 97 | 00000000 98 | 00000000 99 | 00000000 100 | 00000000 101 | 00000000 102 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/inst_ram.mif: -------------------------------------------------------------------------------- 1 | 00110100000000111000000000000000 2 | 00000000000000110001110000000000 3 | 00110100000000010000000000000001 4 | 00010000000000000000000000000100 5 | 00110100000000010000000000000010 6 | 00110100000000010001000100010001 7 | 00110100000000010001000100000000 8 | 00000000000000000000000000000000 9 | 00110100000000010000000000000011 10 | 00000100000100010000000000001010 11 | 00110100000000010001000100000000 12 | 00110100000000010001000100010001 13 | 00010100001000000000000000010011 14 | 00000000000000000000000000000000 15 | 00110100000000010001000100000000 16 | 00110100000000010001000100010001 17 | 00000000000000000000000000000000 18 | 00000000000000000000000000000000 19 | 00000000000000000000000000000000 20 | 00000000000000000000000000000000 21 | 00110100000000010000000000000100 22 | 00010000011000110000000000001010 23 | 00000011111000000000100000100101 24 | 00110100000000010001000100010001 25 | 00110100000000010001000100000000 26 | 00110100000000010000000000000111 27 | 00110100000000010000000000001000 28 | 00011100001000000000000000100100 29 | 00110100000000010000000000001001 30 | 00110100000000010001000100010001 31 | 00110100000000010001000100000000 32 | 00000000000000000000000000000000 33 | 00110100000000010000000000000101 34 | 00000100001000011111111111110111 35 | 00110100000000010000000000000110 36 | 00110100000000010001000100010001 37 | 00110100000000010001000100000000 38 | 00000000000000000000000000000000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00000000000000000000000000000000 42 | 00000000000000000000000000000000 43 | 00000000000000000000000000000000 44 | 00000000000000000000000000000000 45 | 00000000000000000000000000000000 46 | 00000000000000000000000000000000 47 | 00000000000000000000000000000000 48 | 00000000000000000000000000000000 49 | 00000000000000000000000000000000 50 | 00000000000000000000000000000000 51 | 00000000000000000000000000000000 52 | 00000000000000000000000000000000 53 | 00000000000000000000000000000000 54 | 00000000000000000000000000000000 55 | 00000000000000000000000000000000 56 | 00000000000000000000000000000000 57 | 00000000000000000000000000000000 58 | 00000000000000000000000000000000 59 | 00000000000000000000000000000000 60 | 00000000000000000000000000000000 61 | 00000000000000000000000000000000 62 | 00000000000000000000000000000000 63 | 00000000000000000000000000000000 64 | 00000000000000000000000000000000 65 | 00110100000000010000000000001010 66 | 00000100011100011111111111011110 67 | 00000000000111110000100000100101 68 | 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00000000000000000000000000000000 95 | 00000000000000000000000000000000 96 | 00000000000000000000000000000000 97 | 00000000000000000000000000000000 98 | 00000000000000000000000000000000 99 | 00000000000000000000000000000000 100 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/j_BTest/Test2/obj/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/funcTest_independent/test_bench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mips_min_tb(); 4 | 5 | reg clock_50; 6 | reg rst; 7 | 8 | initial begin 9 | clock_50 = 1'b0; 10 | forever # 10 clock_50 = ~clock_50; 11 | end 12 | 13 | initial begin 14 | rst = 0; 15 | #200 rst= 1; 16 | #1000 $stop; 17 | end 18 | 19 | /*** 此处调用自己的cpu,如 20 | mycpuTop mips( 21 | .clk(clock_50), 22 | .rst(rst) 23 | ); 24 | ***/ -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_1/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_2/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/data_ram.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/data_ram.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000000000000000000000000000 3 | 00000000000000000000000000000000 4 | 00000000000000000000000000000000 5 | 00000000000000000000000000000000 6 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/main.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/main.bin -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/main.data: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/main.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/src/PipelineMIPS-sram/simulation/soft_part/func_part/obj_3/main.elf -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/aludefines.vh: -------------------------------------------------------------------------------- 1 | //alu defines 2 | `define ALU_AND 5'b0_0000 3 | `define ALU_OR 5'b0_0001 4 | `define ALU_ADD 5'b0_0010 5 | `define ALU_SUB 5'b0_0011 6 | `define ALU_SLT 5'b0_0100 7 | `define ALU_SLL 5'b0_0101 8 | `define ALU_SRL 5'b0_0110 9 | `define ALU_SRA 5'b0_0111 10 | `define ALU_SLTU 5'b0_1000 11 | `define ALU_UNSIGNED_MULT 5'b0_1001 12 | `define ALU_XOR 5'b0_1010 13 | `define ALU_NOR 5'b0_1011 14 | `define ALU_UNSIGNED_DIV 5'b0_1100 15 | `define ALU_SIGNED_MULT 5'b0_1101 16 | `define ALU_SIGNED_DIV 5'b0_1110 17 | `define ALU_LUI 5'b0_1111 18 | `define ALU_ADDU 5'b1_0000 19 | `define ALU_SUBU 5'b1_0001 20 | `define ALU_LEZ 5'b1_0010 21 | `define ALU_GTZ 5'b1_0011 22 | `define ALU_GEZ 5'b1_0100 23 | `define ALU_LTZ 5'b1_0101 24 | `define ALU_SLL_SA 5'b1_0110 25 | `define ALU_SRL_SA 5'b1_0111 26 | `define ALU_SRA_SA 5'b1_1000 27 | `define ALU_EQ 5'b1_1001 28 | `define ALU_NEQ 5'b1_1010 29 | `define ALU_MTHI 5'b1_1011 30 | `define ALU_MTLO 5'b1_1100 31 | // 5'b1_1101 32 | // 5'b1_1110 33 | `define ALU_DONOTHING 5'b1_1111 -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/defines.vh: -------------------------------------------------------------------------------- 1 | 2 | `define EXE_R_TYPE 6'b000000 3 | //logic inst 4 | `define EXE_NOP 6'b000000 5 | `define EXE_AND 6'b100100 6 | `define EXE_OR 6'b100101 7 | `define EXE_XOR 6'b100110 8 | `define EXE_NOR 6'b100111 9 | `define EXE_ANDI 6'b001100 10 | `define EXE_ORI 6'b001101 11 | `define EXE_XORI 6'b001110 12 | `define EXE_LUI 6'b001111 13 | //shift inst 14 | `define EXE_SLL 6'b000000 15 | `define EXE_SLLV 6'b000100 16 | `define EXE_SRL 6'b000010 17 | `define EXE_SRLV 6'b000110 18 | `define EXE_SRA 6'b000011 19 | `define EXE_SRAV 6'b000111 20 | //move inst 21 | `define EXE_MFHI 6'b010000 22 | `define EXE_MTHI 6'b010001 23 | `define EXE_MFLO 6'b010010 24 | `define EXE_MTLO 6'b010011 25 | //算术运算 26 | `define EXE_SLT 6'b101010 27 | `define EXE_SLTU 6'b101011 28 | `define EXE_SLTI 6'b001010 29 | `define EXE_SLTIU 6'b001011 30 | `define EXE_ADD 6'b100000 31 | `define EXE_ADDU 6'b100001 32 | `define EXE_SUB 6'b100010 33 | `define EXE_SUBU 6'b100011 34 | `define EXE_ADDI 6'b001000 35 | `define EXE_ADDIU 6'b001001 36 | 37 | `define EXE_MULT 6'b011000 38 | `define EXE_MULTU 6'b011001 39 | 40 | `define EXE_DIV 6'b011010 41 | `define EXE_DIVU 6'b011011 42 | //jump 43 | `define EXE_J 6'b000010 44 | `define EXE_JAL 6'b000011 45 | `define EXE_JALR 6'b001001 46 | `define EXE_JR 6'b001000 47 | //branch 48 | `define EXE_BEQ 6'b000100 49 | `define EXE_BGTZ 6'b000111 50 | `define EXE_BNE 6'b000101 51 | `define EXE_BLEZ 6'b000110 52 | `define EXE_BRANCHS 6'b000001 // 53 | `define EXE_BLTZ 5'b00000 54 | `define EXE_BLTZAL 5'b10000 55 | `define EXE_BGEZAL 5'b10001 56 | `define EXE_BGEZ 5'b00001 57 | //load/store 58 | `define EXE_LB 6'b100000 59 | `define EXE_LBU 6'b100100 60 | `define EXE_LH 6'b100001 61 | `define EXE_LHU 6'b100101 62 | `define EXE_LL 6'b110000 63 | `define EXE_LW 6'b100011 64 | `define EXE_LWL 6'b100010 65 | `define EXE_LWR 6'b100110 66 | `define EXE_SB 6'b101000 67 | `define EXE_SC 6'b111000 68 | `define EXE_SH 6'b101001 69 | `define EXE_SW 6'b101011 70 | `define EXE_SWL 6'b101010 71 | `define EXE_SWR 6'b101110 72 | //trap 73 | `define EXE_SYSCALL 6'b001100 74 | `define EXE_BREAK 6'b001101 75 | 76 | `define EXE_TEQ 6'b110100 77 | `define EXE_TEQI 5'b01100 78 | `define EXE_TGE 6'b110000 79 | `define EXE_TGEI 5'b01000 80 | `define EXE_TGEIU 5'b01001 81 | `define EXE_TGEU 6'b110001 82 | `define EXE_TLT 6'b110010 83 | `define EXE_TLTI 5'b01010 84 | `define EXE_TLTIU 5'b01011 85 | `define EXE_TLTU 6'b110011 86 | `define EXE_TNE 6'b110110 87 | `define EXE_TNEI 5'b01110 88 | 89 | // `define EXE_ERET 32'b01000010000000000000000000011000 90 | `define EXE_ERET 26'b10000000000000000000011000 91 | `define EXE_ERET_MFTC 6'b010000 92 | 93 | `define EXE_SYNC 6'b001111 94 | `define EXE_PREF 6'b110011 95 | 96 | `define EXE_MTC0 5'b00100 97 | `define EXE_MFC0 5'b00000 98 | 99 | //Exception code 100 | `define EXC_CODE_INT 5'h00 101 | `define EXC_CODE_ADEL 5'h04 102 | `define EXC_CODE_ADES 5'h05 103 | `define EXC_CODE_SYS 5'h08 104 | `define EXC_CODE_BP 5'h09 105 | `define EXC_CODE_RI 5'h0a 106 | `define EXC_CODE_OV 5'h0c 107 | 108 | //Exception type 109 | `define EXC_TYPE_INT 32'h0000_0001 110 | `define EXC_TYPE_ADEL 32'h0000_0004 111 | `define EXC_TYPE_ADES 32'h0000_0005 112 | `define EXC_TYPE_SYS 32'h0000_0008 113 | `define EXC_TYPE_BP 32'h0000_0009 114 | `define EXC_TYPE_RI 32'h0000_000a 115 | `define EXC_TYPE_OV 32'h0000_000c 116 | `define EXC_TYPE_ERET 32'h0000_000e 117 | `define EXC_TYPE_NOEXC 32'h0000_0000 118 | 119 | //CP0 120 | `define CP0_REG_BADVADDR 5'b01000 121 | `define CP0_REG_COUNT 5'b01001 122 | `define CP0_REG_COMPARE 5'b01011 123 | `define CP0_REG_STATUS 5'b01100 124 | `define CP0_REG_CAUSE 5'b01101 125 | `define CP0_REG_EPC 5'b01110 126 | `define CP0_REG_PRID 5'b01111 127 | `define CP0_REG_CONFIG 5'b10000 128 | 129 | `define InterruptAssert 1'b1 130 | `define InterruptNotAssert 1'b0 131 | `define InDelaySlot 1'b1 132 | `define NotInDelaySlot 1'b0 133 | 134 | `define ZeroWord 32'd0 135 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/inst_ascii_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2018/08/06 15:21:16 7 | // Design Name: 8 | // Module Name: instdec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `timescale 1ns / 1ps 23 | 24 | `include "defines.vh" 25 | 26 | 27 | module inst_ascii_decoder( 28 | input wire [31:0] instr, 29 | output reg [44:0] ascii 30 | ); 31 | 32 | always @(*) 33 | begin 34 | ascii<="N-R"; 35 | case(instr[31:26]) 36 | `EXE_NOP: // R-type 37 | begin 38 | case(instr[5:0]) 39 | /* logic instraction */ 40 | `EXE_AND: ascii<= "AND"; 41 | `EXE_OR: ascii<= "OR"; 42 | `EXE_XOR: ascii<= "XOR"; 43 | `EXE_NOR: ascii<= "NOR"; 44 | /* shift instraction */ 45 | `EXE_SLL: ascii<= "SLL"; 46 | `EXE_SRL: ascii<= "SRL"; 47 | `EXE_SRA: ascii<= "SRA"; 48 | `EXE_SLLV: ascii<= "SLLV"; 49 | `EXE_SRLV: ascii<= "SRLV"; 50 | `EXE_SRAV: ascii<= "SRAV"; 51 | /* move instraction */ 52 | `EXE_MFHI: ascii<= "MFHI"; 53 | `EXE_MTHI: ascii<= "MTHI"; 54 | `EXE_MFLO: ascii<= "MFLO"; 55 | `EXE_MTLO: ascii<= "MTLO"; 56 | /* arithemtic instraction */ 57 | `EXE_ADD: ascii<= "ADD"; 58 | `EXE_ADDU: ascii<= "ADDU"; 59 | `EXE_SUB: ascii<= "SUB"; 60 | `EXE_SUBU: ascii<= "SUBU"; 61 | `EXE_SLT: ascii<= "SLT"; 62 | `EXE_SLTU: ascii<= "SLTU"; 63 | 64 | `EXE_MULT: ascii<= "MULT"; 65 | `EXE_MULTU: ascii<= "MULTU"; 66 | `EXE_DIV: ascii<= "DIV"; 67 | `EXE_DIVU: ascii<= "DIVU"; 68 | /* jump instraction */ 69 | `EXE_JR: ascii<= "JR"; 70 | `EXE_JALR: ascii<= "JALR"; 71 | 72 | `EXE_SYSCALL: ascii<= "SYSC"; 73 | `EXE_BREAK: ascii<= "BRE"; 74 | default: ascii<="N-R"; 75 | endcase 76 | end 77 | `EXE_ANDI: ascii<= "ANDI"; 78 | `EXE_XORI: ascii<= "XORI"; 79 | `EXE_LUI: ascii<= "LUI"; 80 | `EXE_ORI: ascii<= "ORI"; 81 | 82 | `EXE_ADDI: ascii<= "ADDI"; 83 | `EXE_ADDIU: ascii<= "ADDIU"; 84 | `EXE_SLTI: ascii<= "SLTI"; 85 | `EXE_SLTIU: ascii<= "SLTIU"; 86 | 87 | `EXE_J: ascii<= "J"; 88 | `EXE_JAL: ascii<= "JAL"; 89 | 90 | `EXE_BEQ: ascii<= "BEQ"; 91 | `EXE_BGTZ: ascii<= "BGTZ"; 92 | `EXE_BLEZ: ascii<= "BLEZ"; 93 | `EXE_BNE: ascii<= "BNE"; 94 | 95 | `EXE_LB: ascii<= "LB"; 96 | `EXE_LBU: ascii<= "LBU"; 97 | `EXE_LH: ascii<= "LH"; 98 | `EXE_LHU: ascii<= "LHU"; 99 | `EXE_LW: ascii<= "LW"; 100 | `EXE_SB: ascii<= "SB"; 101 | `EXE_SH: ascii<= "SH"; 102 | `EXE_SW: ascii<= "SW"; 103 | 6'b000001: begin 104 | case (instr[20:16]) 105 | `EXE_BGEZ: ascii<= "BGEZ"; 106 | `EXE_BGEZAL: ascii<= "BGEZAL"; 107 | `EXE_BLTZ: ascii<= "BLTZ"; 108 | `EXE_BLTZAL: ascii<= "BLTZAL"; 109 | default : ascii<= " "; 110 | endcase 111 | end 112 | 6'b010000: begin 113 | if(instr==`EXE_ERET) begin 114 | ascii<="ERET"; 115 | end else begin 116 | case (instr[25:21]) 117 | 5'b00100: ascii<="MTOC0"; 118 | 5'b00000: ascii<="MFC0"; 119 | endcase 120 | end 121 | end 122 | default: ascii<= "N-R"; 123 | endcase 124 | if(instr==`EXE_ERET) 125 | ascii<= "ERET"; 126 | if(!instr) 127 | ascii<= "NOP"; 128 | end 129 | 130 | endmodule 131 | 132 | -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/mux2.v: -------------------------------------------------------------------------------- 1 | module mux2 #(parameter WIDTH=32) ( 2 | input wire [WIDTH-1:0] x0, x1, 3 | input wire sel, 4 | 5 | output wire [WIDTH-1:0] y 6 | ); 7 | assign y = sel ? x1 : x0; 8 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/mux4.v: -------------------------------------------------------------------------------- 1 | module mux4 #(parameter WIDTH=32) ( 2 | input wire [WIDTH-1:0] x0, x1, x2, x3, 3 | input wire [1:0] sel, 4 | 5 | output wire [WIDTH-1:0] y 6 | ); 7 | assign y = sel[1] ? (sel[0] ? x3: x2): 8 | (sel[0] ? x1: x0); 9 | 10 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS-sram/utils/mux8.v: -------------------------------------------------------------------------------- 1 | module mux8 #(parameter WIDTH=32) ( 2 | input wire [WIDTH-1:0] x7, x6, x5, x4, x3, x2, x1, x0, 3 | input wire [2:0] sel, 4 | 5 | output wire [WIDTH-1:0] y 6 | ); 7 | assign y = sel[2] ? (sel[1] ? (sel[0] ? x7 : x6): 8 | (sel[0] ? x5 : x4)) : 9 | (sel[1] ? (sel[0] ? x3 : x2) : 10 | (sel[0] ? x1 : x0)) 11 | ; 12 | 13 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS/EX/branch_judge.v: -------------------------------------------------------------------------------- 1 | module branch_judge ( 2 | input wire [4:0] branch_judge_controlE, 3 | input wire [31:0] src_aE, src_bE, 4 | 5 | output reg actual_takeE 6 | ); 7 | 8 | always @(*) begin 9 | case(branch_judge_controlE) 10 | `ALU_EQ: actual_takeE = !(src_aE ^ src_bE); 11 | `ALU_NEQ: actual_takeE = |(src_aE ^ src_bE); 12 | `ALU_GTZ: actual_takeE = ~src_aE[31] & (|src_aE); 13 | `ALU_GEZ: actual_takeE = ~src_aE[31]; 14 | `ALU_LTZ: actual_takeE = src_aE[31]; 15 | `ALU_LEZ: actual_takeE = src_aE[31] | ~(|src_aE); 16 | default: 17 | actual_takeE = 1'b0; 18 | endcase 19 | end 20 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS/EX/div_radix2.v: -------------------------------------------------------------------------------- 1 | //module: div 2 | //description: radix-2 divider 3 | //version: 1.4 4 | 5 | /** log: 6 | 1.1: 增加了存储输入的逻辑 (不暂停M,W阶段, 数据前推导致输入发生变化) 7 | 1.2: 增加了flush逻辑，用于发生异常时停止计算除法（1.3: 合并到rst中） 8 | 1.3: 接口增加axi握手逻辑。其中“地址”握手(opn_valid)，认为是单向握手（slave随时都准备好接收输入） 9 | 1.4: rst时将一些reg清0，防止result出现xxx的情况 10 | */ 11 | 12 | module div_radix2( 13 | input wire clk, 14 | input wire rst, 15 | input wire [31:0] a, //divident 16 | input wire [31:0] b, //divisor 17 | input wire sign, //1:signed 18 | 19 | input wire opn_valid, //master操作数准备好 20 | output reg res_valid, //slave计算结果准备好 21 | input wire res_ready, //master可以接收计算结果 22 | output wire [63:0] result 23 | ); 24 | /** 计算过程 25 | 1. 先取绝对值，计算出余数和商。再根据被除数、除数符号对结果调整 26 | 2. 计算过程中，由于保证了remainer为正，因此最高位为0，可以用32位存储。而除数需用33位 27 | */ 28 | 29 | reg [31:0] a_save, b_save; 30 | reg [63:0] SR; //shift register 31 | reg [32 :0] NEG_DIVISOR; //divisor 2's complement 32 | wire [31:0] REMAINER, QUOTIENT; 33 | assign REMAINER = SR[63:32]; 34 | assign QUOTIENT = SR[31: 0]; 35 | 36 | wire [31:0] divident_abs; 37 | wire [32:0] divisor_abs; 38 | wire [31:0] remainer, quotient; 39 | 40 | assign divident_abs = (sign & a[31]) ? ~a + 1'b1 : a; 41 | //余数符号与被除数相同 42 | assign remainer = (sign & a_save[31]) ? ~REMAINER + 1'b1 : REMAINER; 43 | assign quotient = sign & (a_save[31] ^ b_save[31]) ? ~QUOTIENT + 1'b1 : QUOTIENT; 44 | assign result = {remainer,quotient}; 45 | 46 | wire CO; 47 | wire [32:0] sub_result; 48 | wire [32:0] mux_result; 49 | //sub 50 | assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR; 51 | //mux 52 | assign mux_result = CO ? sub_result : {1'b0,REMAINER}; 53 | 54 | //FSM 55 | reg [5:0] cnt; 56 | reg start_cnt; 57 | always @(posedge clk) begin 58 | if(rst) begin 59 | SR <= 0; 60 | a_save <= 0; 61 | b_save <= 0; 62 | 63 | cnt <= 0; 64 | start_cnt <= 1'b0; 65 | end 66 | else if(~start_cnt & opn_valid & ~res_valid) begin 67 | cnt <= 1; 68 | start_cnt <= 1'b1; 69 | //save a,b 70 | a_save <= a; 71 | b_save <= b; 72 | 73 | //Register init 74 | SR[63:0] <= {31'b0,divident_abs,1'b0}; //left shift one bit initially 75 | NEG_DIVISOR <= (sign & b[31]) ? {1'b1,b} : ~{1'b0,b} + 1'b1; //divisor_abs的补码 76 | end 77 | else if(start_cnt) begin 78 | if(cnt[5]) begin //cnt == 32 79 | cnt <= 0; 80 | start_cnt <= 1'b0; 81 | 82 | //Output result 83 | SR[63:32] <= mux_result[31:0]; 84 | SR[0] <= CO; 85 | end 86 | else begin 87 | cnt <= cnt + 1; 88 | 89 | SR[63:0] <= {mux_result[30:0],SR[31:1],CO,1'b0}; //wsl: write and shift left 90 | end 91 | end 92 | end 93 | 94 | wire data_go; 95 | assign data_go = res_valid & res_ready; 96 | always @(posedge clk) begin 97 | res_valid <= rst ? 1'b0 : 98 | cnt[5] ? 1'b1 : 99 | data_go ? 1'b0 : res_valid; 100 | end 101 | endmodule -------------------------------------------------------------------------------- /src/PipelineMIPS/ID/branch_predict.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | module branch_predict ( 3 | input wire clk, rst, 4 | 5 | input wire flushD, 6 | input wire stallD, 7 | 8 | input wire [31:0] instrD, 9 | input wire [31:0] immD, 10 | 11 | input wire [31:0] pcF, 12 | input wire [31:0] pcM, 13 | input wire branchM, 14 | input wire actual_takeM, 15 | 16 | output wire branchD, 17 | output wire branchL_D, 18 | output wire pred_takeD 19 | ); 20 | wire pred_takeF; 21 | reg pred_takeF_r; 22 | wire [5:0] op_code, funct; 23 | wire [4:0] rt; 24 | assign op_code = instrD[31:26]; 25 | assign rs = instrD[25:21]; 26 | assign rt = instrD[20:16]; 27 | assign funct = instrD[5:0]; 28 | assign branchD = ( !(op_code ^ `EXE_REGIMM) & (!(instrD[19:17] ^ 3'b000) | !(instrD[19:17] ^ 3'b001)) ) 29 | | !(op_code[5:2] ^ 4'b0001); //4'b0001 -> beq, bgtz, blez, bne 30 | // 3'b000 -> BLTZ BLTZAL BGEZAL BGEZ 31 | // 3'b001 -> BGEZALL BGEZL BLTZALL BLTZL 32 | assign branchL_D = ( !(op_code ^ `EXE_REGIMM) & !(instrD[19:17] ^ 3'b001) ) | 33 | !(op_code[5:2] ^ 4'b0101); //beql, bgtzl, blezl, bnel 34 | 35 | parameter Strongly_not_taken = 2'b00, Weakly_not_taken = 2'b01, Weakly_taken = 2'b11, Strongly_taken = 2'b10; 36 | parameter PHT_DEPTH = 6; 37 | parameter BHT_DEPTH = 10; 38 | 39 | reg [5:0] BHT [(1< i_cache, 1-> d_cache 84 | 85 | reg [31:0] i_rdata_r, d_rdata_r; 86 | 87 | //ar 88 | assign ar_sel = ~i_arvalid & d_arvalid ? 1'b1 : 1'b0; //优先i_cache 89 | 90 | //r 91 | wire r_sel; //0-> i_cache, 1-> d_cache 92 | assign r_sel = rid[0]; 93 | 94 | //I CACHE 95 | assign i_arready = arready & ~ar_sel; 96 | 97 | assign i_rdata = ~r_sel ? rdata : 32'b0; 98 | assign i_rlast = ~r_sel ? rlast : 1'b0; 99 | assign i_rvalid = ~r_sel ? rvalid : 1'b0; 100 | //D CACHE 101 | assign d_arready = arready & ar_sel; 102 | 103 | assign d_rdata = r_sel ? rdata : 32'b0; 104 | assign d_rlast = r_sel ? rlast : 1'b0; 105 | assign d_rvalid = r_sel ? rvalid : 1'b0; 106 | //AXI 107 | //ar 108 | assign arid = {3'b0, ar_sel}; 109 | assign araddr = ar_sel ? d_araddr : i_araddr; 110 | assign arlen = ar_sel ? d_arlen : i_arlen; 111 | assign arsize = ar_sel ? d_arsize : 2'b10; //读一个字 112 | assign arburst = 2'b10; //Incrementing burst 113 | assign arlock = 2'd0; 114 | assign arcache = 4'd0; 115 | assign arprot = 3'd0; 116 | assign arvalid = ar_sel ? d_arvalid : i_arvalid; 117 | // 118 | //r 119 | assign rready = ~r_sel ? i_rready : d_rready; 120 | // 121 | 122 | //aw 123 | assign awid = 4'd0; 124 | assign awaddr = d_awaddr; 125 | assign awlen = d_awlen; //8*4B 126 | assign awsize = d_awsize; 127 | assign awburst = 2'b10; //Incrementing burst 128 | assign awlock = 2'd0; 129 | assign awcache = 4'd0; 130 | assign awprot = 3'd0; 131 | assign awvalid = d_awvalid; 132 | //w 133 | assign wid = 4'd0; 134 | assign wdata = d_wdata; 135 | // assign wstrb = do_size_r==2'd0 ? 4'b0001<> src_aE[4:0]; 45 | `ALU_SRA: alu_out_not_mul_div <= $signed(src_bE) >>> src_aE[4:0]; 46 | 47 | `ALU_SLL_SA: alu_out_not_mul_div <= src_bE << sa; 48 | `ALU_SRL_SA: alu_out_not_mul_div <= src_bE >> sa; 49 | `ALU_SRA_SA: alu_out_not_mul_div <= $signed(src_bE) >>> sa; 50 | 51 | // `ALU_UNSIGNED_MULT: alu_out_not_mul_div <= {32'b0, src_aE }* {32'b0, src_bE}; 52 | // `ALU_SIGNED_MULT: alu_out_not_mul_div <= $signed(src_aE) * $signed(src_bE); 53 | 54 | `ALU_LUI: alu_out_not_mul_div <= {src_bE[15:0], 16'b0}; 55 | 56 | // `ALU_PC_PLUS8: alu_out_not_mul_div <= {32'b0, src_aE }+ 64'd4; 57 | default: alu_out_not_mul_div <= 32'b0; 58 | endcase 59 | end 60 | 61 | //divide 62 | wire div_sign; 63 | wire vaild; 64 | wire ready; 65 | 66 | assign div_sign = (alu_controlE == `ALU_SIGNED_DIV); 67 | assign div_vaild = (alu_controlE == `ALU_SIGNED_DIV || alu_controlE == `ALU_UNSIGNED_DIV); 68 | 69 | div_radix2 DIV( 70 | .clk(~clk), 71 | .rst(rst), 72 | .a(src_aE), //divident 73 | .b(src_bE), //divisor 74 | .valid(div_vaild), 75 | .div_sign(div_sign), //1 signed 76 | 77 | // .ready(ready), 78 | .div_stall(div_stall), 79 | .result(alu_out_div) 80 | ); 81 | 82 | //multiply 83 | wire mul_sign; 84 | assign mul_sign = (alu_controlE == `ALU_SIGNED_MULT); 85 | assign mul_valid = (alu_controlE == `ALU_SIGNED_MULT) | (alu_controlE == `ALU_UNSIGNED_MULT); 86 | mul_booth2 MUL( 87 | .a(src_aE), 88 | .b(src_bE), 89 | .sign(mul_sign), //1:signed 90 | 91 | .result(alu_out_mul) 92 | ); 93 | 94 | 95 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/EX/div_radix2.v: -------------------------------------------------------------------------------- 1 | //module: div 2 | //description: radix-2 divider 3 | //version: 1.0 4 | 5 | module div_radix2( 6 | input clk, 7 | input rst, 8 | input [31:0] a, //divident 9 | input [31:0] b, //divisor 10 | input valid, 11 | input sign, //1:signed 12 | 13 | // output reg ready, 14 | output wire div_stall, 15 | output [63:0] result 16 | ); 17 | /* 18 | 1. 先取绝对值，计算出余数和商。再根据被除数、除数符号对结果调整 19 | 2. 计算过程中，由于保证了remainer为正，因此最高位为0，可以用32位存储。而除数需用33位 20 | */ 21 | 22 | reg [63:0] SR; //shift register 23 | reg [32 :0] NEG_DIVISOR; //divisor 2's complement 24 | wire [31:0] REMAINER, QUOTIENT; 25 | assign REMAINER = SR[63:32]; 26 | assign QUOTIENT = SR[31: 0]; 27 | 28 | wire [31:0] divident_abs; 29 | wire [32:0] divisor_abs; 30 | wire [31:0] remainer, quotient; 31 | 32 | assign divident_abs = (sign & a[31]) ? ~a + 1'b1 : a; 33 | //余数符号与被除数相同 34 | assign remainer = (sign & a[31]) ? ~REMAINER + 1'b1 : REMAINER; 35 | assign quotient = sign & (a[31] ^ b[31]) ? ~QUOTIENT + 1'b1 : QUOTIENT; 36 | assign result = {remainer,quotient}; 37 | 38 | wire CO; 39 | wire [32:0] sub_result; 40 | wire [32:0] mux_result; 41 | //sub 42 | assign {CO,sub_result} = {1'b0,REMAINER} + NEG_DIVISOR; 43 | //mux 44 | assign mux_result = CO ? sub_result : {1'b0,REMAINER}; 45 | 46 | //state machine 47 | reg [5:0] cnt; 48 | reg start_cnt; 49 | always @(posedge clk, posedge rst) begin 50 | if(rst) begin 51 | cnt <= 0; 52 | start_cnt <= 0; 53 | end 54 | else if(!start_cnt & valid) begin 55 | cnt <= 1; 56 | start_cnt <= 1; 57 | 58 | //Register init 59 | SR[63:0] <= {31'b0,divident_abs,1'b0}; //left shift one bit initially 60 | NEG_DIVISOR <= (sign & b[31]) ? {1'b1,b} : ~{1'b0,b} + 1'b1; //divisor_abs的补码 61 | end 62 | else if(start_cnt) begin 63 | if(cnt==32) begin 64 | cnt <= 0; 65 | start_cnt <= 0; 66 | 67 | //Output result 68 | SR[63:32] <= mux_result[31:0]; 69 | SR[0] <= CO; 70 | end 71 | else begin 72 | cnt <= cnt + 1; 73 | 74 | SR[63:0] <= {mux_result[30:0],SR[31:1],CO,1'b0}; //wsl: write and shift left 75 | end 76 | end 77 | end 78 | 79 | assign div_stall = |cnt; //只有当cnt=0时不暂停 80 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/ID/branch_predict.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | module branch_predict ( 3 | input wire [31:0] instrD, 4 | input wire [31:0] immD, 5 | 6 | output wire branchD, 7 | output wire pred_takeD 8 | ); 9 | // // assign branch_takeD = ; 10 | // wire [31:0] a, b; 11 | // assign a = rd1D; 12 | // assign b = rd2D; 13 | // always @(*) begin 14 | // case(instrD[31:26]) 15 | // `EXE_BEQ: 16 | // branch_takeD <= ( a == b ); 17 | // `EXE_BGTZ: 18 | // branch_takeD <= ( $signed(a) > 0 ); 19 | // `EXE_BLEZ: 20 | // branch_takeD <= ( $signed(a) <= 0 ); 21 | // `EXE_BNE: 22 | // branch_takeD <= ( a != b ); 23 | 24 | // `EXE_BRANCHS: //bltz, bltzal, bgez, bgezal 25 | // case(instrD[20:16]) 26 | // `EXE_BLTZ, `EXE_BLTZAL: 27 | // branch_takeD <= ( $signed(a) < 0 ); 28 | // `EXE_BGEZ, `EXE_BGEZAL: 29 | // branch_takeD <= ( $signed(a) >= 0 ); 30 | // default: 31 | // branch_takeD <= 1'b0; 32 | // endcase 33 | // default: 34 | // branch_takeD <= 1'b0; 35 | // endcase 36 | // end 37 | assign branchD = ( ~(|(instrD[31:26] ^`EXE_BRANCHS)) & ~(|(instrD[19:17] ^ 3'b000)) ) 38 | | ~(|(instrD[31:28] ^4'b0001)); //4'b0001 -> beq, bgtz, blez, bne 39 | 40 | assign pred_takeD = branchD & (immD[31]) ? 1'b1 : 1'b0; //向上跳转，向下不跳转 41 | 42 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/ID/imm_ext.v: -------------------------------------------------------------------------------- 1 | module imm_ext( 2 | input wire [15:0] imm, 3 | input wire sign_ext, 4 | output wire [31:0] imm_ext 5 | ); 6 | assign imm_ext = sign_ext ? {{16{imm[15]}}, imm[15:0]}: 7 | {16'b0, imm[15:0]} 8 | ; 9 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/ID/regfile.v: -------------------------------------------------------------------------------- 1 | module regfile( 2 | input wire clk, 3 | input wire we3, 4 | input wire[4:0] ra1,ra2,wa3, 5 | input wire[31:0] wd3, 6 | output wire[31:0] rd1,rd2 7 | ); 8 | 9 | reg [31:0] rf[31:0]; 10 | 11 | always @(posedge clk) begin 12 | if(we3) begin 13 | rf[wa3] <= wd3; 14 | end 15 | end 16 | 17 | assign rd1 = (ra1 != 0) ? rf[ra1] : 0; 18 | assign rd2 = (ra2 != 0) ? rf[ra2] : 0; 19 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/IF/pc_ctrl.v: -------------------------------------------------------------------------------- 1 | module pc_ctrl( 2 | input wire branchD, 3 | input wire branchM, 4 | input wire succM, 5 | input wire actual_takeM, 6 | input wire pred_takeD, 7 | 8 | output wire [1:0] pc_sel 9 | ); 10 | 11 | 12 | assign pc_sel = (branchM & ~succM & actual_takeM) ? 2'b10: 13 | (branchM & ~succM & ~actual_takeM) ? 2'b11: 14 | (branchD & ~branchM & pred_takeD || 15 | branchD & branchM & succM & pred_takeD) ? 2'b01: 16 | 2'b00; 17 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/IF/pc_reg.v: -------------------------------------------------------------------------------- 1 | module pc_reg #(parameter WIDTH=32)( 2 | input wire clk, 3 | input wire stallF, 4 | input wire rst, 5 | input wire [WIDTH-1:0] pc_next, 6 | 7 | output reg [ WIDTH-1:0] pc, 8 | output reg ce 9 | ); 10 | always @(posedge clk) begin 11 | if(rst) begin 12 | ce <= 0; 13 | end 14 | else begin 15 | ce <= 1; 16 | end 17 | end 18 | 19 | always @(posedge clk) begin 20 | if(!ce) begin 21 | // pc <= 32'hbfc00000; 22 | pc <= 32'h0000_0000; 23 | end 24 | else if(~stallF) begin 25 | pc <= pc_next; 26 | end 27 | end 28 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/MEM/exception.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | 3 | module exception( 4 | input rst, 5 | input [5:0] ext_int, 6 | input ri, break, syscall, overflow, addrErrorSw, addrErrorLw, pcError, eretM, 7 | input [31:0] cp0_status, cp0_cause, cp0_epc, 8 | input [31:0] pcM, 9 | input [31:0] alu_outM, 10 | 11 | output [31:0] except_type, 12 | output flush_except, 13 | output [31:0] pc_except, 14 | output pc_trap, 15 | output [31:0] badvaddrM 16 | ); 17 | 18 | //INTERUPT 19 | wire int; 20 | // //IE //EXL 21 | assign int = cp0_status[0] && ~cp0_status[1] && ( 22 | //IM //IP 23 | ( |(cp0_status[9:8] & cp0_cause[9:8]) ) || //soft interupt 24 | ( |(cp0_status[15:10] & ext_int) ) //hard interupt 25 | ); 26 | // 全局中断开启,且没有例外在处理,识别软件中断或者硬件中断; 27 | 28 | assign except_type = (int) ? `EXC_TYPE_INT : 29 | (addrErrorLw | pcError) ? `EXC_TYPE_ADEL : 30 | (ri) ? `EXC_TYPE_RI : 31 | (syscall) ? `EXC_TYPE_SYS : 32 | (break) ? `EXC_TYPE_BP : 33 | (addrErrorSw) ? `EXC_TYPE_ADES : 34 | (overflow) ? `EXC_TYPE_OV : 35 | (eretM) ? `EXC_TYPE_ERET : 36 | `EXC_TYPE_NOEXC; 37 | //interupt pc address 38 | assign pc_except = (except_type == `EXC_TYPE_NOEXC) ? `ZeroWord: 39 | (except_type == `EXC_TYPE_ERET)? cp0_epc : 40 | 32'hbfc0_0380; 41 | assign pc_trap = (except_type == `EXC_TYPE_NOEXC) ? 1'b0: 42 | 1'b1; 43 | assign flush_except = (except_type == `EXC_TYPE_NOEXC) ? 1'b0: 44 | 1'b1; 45 | assign badvaddrM = (pcError) ? pcM : alu_outM; 46 | 47 | // // 提高性能; 48 | // assign pc_except = (int) | (addrErrorLw | pcError) | (ri) | (break) | (overflow) 49 | // ? 32'hbfc0_0380 50 | // (eretM) ? `ZeroWord : 51 | // cp0_epc ; 52 | 53 | // assign pc_trap = (int) | (addrErrorLw | pcError) | (ri) | (break) | (overflow) | (eretM) 54 | // ? 1'b1 : 1'b0 ; 55 | 56 | // assign flush_except = pc_trap ; 57 | 58 | // assign badvaddrM = (pcError) ? pcM : alu_outM ; 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /src/basic_pipeline/MEM/hilo_reg.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "defines.vh" 3 | 4 | module hilo_reg( 5 | input wire clk,rst,we, //both write lo and hi 6 | input wire [31:0] instrM, 7 | 8 | input wire [63:0] hilo_i, 9 | output reg [63:0] hilo_o 10 | ); 11 | // 方案1 12 | // always @(posedge clk) begin 13 | // if(rst) begin 14 | // hilo_o <= 0; 15 | // end else if (we) begin 16 | // hilo_o <= hilo_i; 17 | // end 18 | // end 19 | 20 | // 方案2 21 | // 少了一级比较 22 | wire [63:0] hilo_ii; 23 | reg [63:0] hilo; 24 | wire [31:0] hilo_o; 25 | always @(posedge clk) begin 26 | if(we) 27 | hilo <= hilo_ii; 28 | else 29 | hilo <= hilo_ii; 30 | end 31 | assign hilo_ii = ( {64{rst}} & 64'd0 ) 32 | ||( {64{~rst & en}} & hilo_i); 33 | wire hi; 34 | wire lo; 35 | assign hi = ~(|(instrM[31:26] ^ `EXE_R_TYPE)) & ~(|(instrM[5:0] ^ `EXE_MFHI)); 36 | assign lo = ~(|(instrM[31:26] ^ `EXE_R_TYPE)) & ~(|(instrM[5:0] ^ `EXE_MFLO)); 37 | 38 | assign hilo_o = ({32{hi}} & hilo[63:32]) | ({32{lo}} & hilo[31:0]); 39 | 40 | // 方案3 41 | // 少了两级比较 42 | // 同时将hilo_o声明为inout变量； 43 | // wire [63:0] hilo_ii; 44 | // always @(posedge clk) begin 45 | // hilo_o <= hilo_ii 46 | // end 47 | // assign hilo_ii = ( {64{rst}} & 64'd0 ) 48 | // ||( {64{~rst & en}} & hilo_i) 49 | // ||( {64{~rst & ~en}} & hilo_o); 50 | 51 | 52 | 53 | endmodule 54 | 55 | -------------------------------------------------------------------------------- /src/basic_pipeline/MEM/mem_ctrl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "defines.vh" 3 | 4 | module mem_ctrl( 5 | input [5:0] op_code, 6 | input [31:0] addr, 7 | input [31:0] write_data, 8 | //mem 4个输入 9 | output reg mem_en, 10 | output reg [3:0] memsel, 11 | output wire [31:0] final_addr, 12 | output reg [31:0] final_wdata, 13 | 14 | output reg addrErrorSw, 15 | output reg addrErrorLw 16 | ); 17 | assign final_addr = addr; 18 | always @(*) begin 19 | //非读写内存指令 20 | addrErrorLw <= 0; 21 | addrErrorSw <= 0; 22 | memsel <= 4'b0000; 23 | mem_en <= 1'b0; 24 | final_wdata <= 32'b0; 25 | case (op_code) 26 | `EXE_SW: begin 27 | if (addr[1:0] == 2'b00) begin 28 | final_wdata <= write_data; 29 | memsel <= 4'b1111; 30 | mem_en <= 1'b1; 31 | addrErrorSw <= 0; 32 | end 33 | else addrErrorSw <= 1; 34 | end 35 | `EXE_SH: begin 36 | final_wdata <= {2{write_data[15:0]}}; 37 | addrErrorSw <= 0; 38 | mem_en <= 1'b1; 39 | case (addr[1:0]) 40 | 2'b10: memsel <= 4'b1100; 41 | 2'b00: memsel <= 4'b0011; 42 | default: addrErrorSw <= 1; 43 | endcase 44 | end 45 | `EXE_SB: begin 46 | final_wdata <= {4{write_data[7:0]}}; 47 | mem_en <= 1'b1; 48 | case (addr[1:0]) 49 | 2'b11: memsel <= 4'b1000; 50 | 2'b10: memsel <= 4'b0100; 51 | 2'b01: memsel <= 4'b0010; 52 | 2'b00: memsel <= 4'b0001; 53 | endcase 54 | end 55 | `EXE_LW: begin 56 | if(addr[1:0] == 2'b00) begin 57 | memsel <= 4'b0000; // 58 | mem_en <= 1'b1; 59 | end 60 | else begin addrErrorLw <= 1; end 61 | end 62 | `EXE_LH, `EXE_LHU: begin 63 | memsel <= 4'b0000; 64 | mem_en <= 1'b1; 65 | if(addr[1:0] == 2'b01 || addr[1:0] == 2'b11) addrErrorLw <= 1; 66 | end 67 | `EXE_LB, `EXE_LBU: begin 68 | memsel <= 4'b0000; 69 | mem_en <= 1'b1; 70 | end 71 | endcase 72 | end 73 | endmodule 74 | -------------------------------------------------------------------------------- /src/basic_pipeline/MEM/mem_ctrr.v: -------------------------------------------------------------------------------- 1 | `include "defines.vh" 2 | 3 | module mem_ctrr( 4 | // 辅助 5 | input wire [31:0] instrM, 6 | input wire [31:0] addr, 7 | 8 | input wire [31:0] data_wdataM, 9 | output wire [31:0] mem_wdataM, 10 | output wire [3:0] mem_byte_wenM, 11 | 12 | input wire [31:0] mem_rdataM, 13 | output wire [31:0] data_rdataM, 14 | 15 | output wire mem_error_enM, 16 | output wire addr_error_sw, addr_error_lw 17 | ); 18 | wire [3:0] mem_byte_wen; 19 | wire [5:0] op_code; 20 | 21 | wire instr_lw, instr_lh, instr_lb, instr_sw, instr_sh, instr_sb, instr_lhu; 22 | wire addr_W, addr_H, addr_H2, addr_B1, addr_B3; 23 | output wire addr_error_sw, addr_error_lw; 24 | 25 | 26 | assign op_code = instrM[31:26]; 27 | 28 | assign addr_W = ~(|(addr[1:0] ^ 2'b00)); 29 | assign addr_H = ~(|(addr[1:0] ^ 2'b00)) || ~(|(addr[1:0] ^ 2'b10)); 30 | assign addr_H2 = ~(|(addr[1:0] ^ 2'b10)); 31 | assign addr_B1 = ~(|(addr[1:0] ^ 2'b01)); 32 | assign addr_B3 = ~(|(addr[1:0] ^ 2'b11)); 33 | 34 | assign instr_lw = ~(|(op_code ^ `EXE_LW)); 35 | assign instr_lb = ~(|(op_code ^ `EXE_LB)) || ~(|(op_code ^ `EXE_LBU)) ; 36 | assign instr_lh = ~(|(op_code ^ `EXE_LH)) || ~(|(op_code ^ `EXE_LHU)) ; 37 | assign instr_lhu = ~(|(op_code ^ `EXE_LHU)) ; 38 | assign instr_sw = ~(|(op_code ^ `EXE_SW)); 39 | assign instr_sh = ~(|(op_code ^ `EXE_SH)); 40 | assign instr_sb = ~(|(op_code ^ `EXE_SB)); 41 | 42 | 43 | assign addr_error_sw = (instr_sw & ~addr_W) 44 | | (instr_sh & ~addr_H); 45 | assign addr_error_lw = (instr_lw & ~addr_W) 46 | | (instr_lh & ~addr_H); 47 | assign mem_error_enM = ~addr_error_lw & ~addr_error_sw; 48 | 49 | 50 | // wdata and byte_wen 51 | assign mem_byte_wenM = ( {4{( instr_sw & addr_W )}} & 4'b1111) 52 | | ( {4{( instr_sh & addr_W )}} & 4'b0011) 53 | | ( {4{( instr_sh & addr_H2 )}} & 4'b1100) 54 | | ( {4{( instr_sb & addr_W )}} & 4'b0001) 55 | | ( {4{( instr_sb & addr_B1 )}} & 4'b0010) 56 | | ( {4{( instr_sb & addr_H2 )}} & 4'b0100) 57 | | ( {4{( instr_sb & addr_B3 )}} & 4'b1000); 58 | 59 | // rdata 60 | // data ram 按字寻址 61 | // 所以还是取了整个字： assign data_rdataM = ( {32{instr_lw}} & mem_rdataM) 62 | assign mem_wdataM = ({ 32{instr_sw}} & data_wdata) 63 | | ( {32{instr_sh}} & {2{data_wdata[15:0]} }) 64 | | ( {32{instr_sb}} & {4{data_wdata[7:0]} }) 65 | | ( {32{ instr_lh & addr_W}} & { {16{mem_rdataM[15]}}, mem_rdataM[15:0] }) 66 | | ( {32{ instr_lh & addr_H2}} & { {16{mem_rdataM[31]}}, mem_rdataM[31:16] }) 67 | | ( {32{ instr_lhu & addr_W}} & { 16'b0, mem_rdataM[15:0] }) 68 | | ( {32{ instr_lhu & addr_H2}} & { 16'b0, mem_rdataM[31:16] }) 69 | | ( {32{ instr_lb & addr_W}} & { {24{mem_rdataM[7]}}, mem_rdataM[7:0] }) 70 | | ( {32{ instr_lb & addr_B1}} & { {24{mem_rdataM[15]}}, mem_rdataM[15:8] }) 71 | | ( {32{ instr_lb & addr_H2}} & { {24{mem_rdataM[23]}}, mem_rdataM[23:16] }) 72 | | ( {32{ instr_lb & addr_B3}} & { {24{mem_rdataM[31]}}, mem_rdataM[31:24] }) 73 | | ( {32{ instr_lbu & addr_W}} & { 24'b0 , mem_rdataM[7:0] }) 74 | | ( {32{ instr_lbu & addr_B1}} & { 24'b0 , mem_rdataM[15:8] }) 75 | | ( {32{ instr_lbu & addr_H2}} & { 24'b0 , mem_rdataM[23:16] }) 76 | | ( {32{ instr_lbu & addr_B3}} & { 24'b0 , mem_rdataM[31:24] }); 77 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/PIPE/ex_mem.v: -------------------------------------------------------------------------------- 1 | module ex_mem ( 2 | input wire clk, rst,flushM, 3 | input wire stallM, 4 | input wire [31:0] pcE, 5 | input wire [63:0] alu_outE, 6 | input wire [31:0] mem_wdataE, 7 | input wire [4:0] reg_writeE, 8 | input wire [31:0] instrE, 9 | input wire branchE, 10 | input wire pred_takeE, 11 | input wire [31:0] pc_branchE, 12 | input wire overflowE, 13 | 14 | 15 | output reg [31:0] pcM, 16 | output reg [31:0] alu_outM, 17 | output reg [31:0] mem_wdataM, 18 | output reg [4:0] reg_writeM, 19 | output reg [31:0] instrM, 20 | output reg branchM, 21 | output reg pred_takeM, 22 | output reg [31:0] pc_branchM, 23 | output reg overflowM 24 | ); 25 | always @(posedge clk) begin 26 | if(rst | flushM) begin 27 | pcM <= 0; 28 | alu_outM <= 0; 29 | mem_wdataM <= 0; 30 | reg_writeM <= 0; 31 | instrM <= 0; 32 | branchM <= 0; 33 | pred_takeM <= 0; 34 | pc_branchM <= 0; 35 | overflowM <= 0; 36 | end 37 | else if(~stallM) begin 38 | pcM <= pcE ; 39 | alu_outM <= alu_outE[31:0] ; 40 | mem_wdataM <= mem_wdataE ; 41 | reg_writeM <= reg_writeE ; 42 | instrM <= instrE ; 43 | branchM <= branchE ; 44 | pred_takeM <= pred_takeE ; 45 | pc_branchM <= pc_branchE ; 46 | overflowM <= overflowE ; 47 | end 48 | end 49 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/PIPE/id_ex.v: -------------------------------------------------------------------------------- 1 | module id_ex ( 2 | input wire clk, rst, 3 | input wire stallE, 4 | input wire flushE, 5 | input wire [31:0] pcD, 6 | input wire [31:0] rd1D, rd2D, 7 | input wire [4:0] rsD, rtD, rdD, 8 | input wire [31:0] immD, 9 | input wire [31:0] pc_plus4D, 10 | input wire [31:0] instrD, 11 | input wire [31:0] pc_branchD, 12 | input wire pred_takeD, 13 | input wire branchD, 14 | input wire jump_conflictD, 15 | 16 | 17 | output reg [31:0] pcE, 18 | output reg [31:0] rd1E, rd2E, 19 | output reg [4:0] rsE, rtE, rdE, 20 | output reg [31:0] immE, 21 | output reg [31:0] pc_plus4E, 22 | output reg [31:0] instrE, 23 | output reg [31:0] pc_branchE, 24 | output reg pred_takeE, 25 | output reg branchE, 26 | output reg jump_conflictE 27 | ); 28 | always @(posedge clk) begin 29 | if(rst | flushE) begin 30 | pcE <= 0; 31 | rd1E <= 0; 32 | rd2E <= 0; 33 | rsE <= 0; 34 | rtE <= 0; 35 | rdE <= 0; 36 | immE <= 0; 37 | pc_plus4E <= 0; 38 | instrE <= 0; 39 | pc_branchE <= 0; 40 | pred_takeE <= 0; 41 | branchE <= 0; 42 | jump_conflictE <= 0; 43 | end 44 | else if(~stallE) begin 45 | pcE <= pcD; 46 | rd1E <= rd1D; 47 | rd2E <= rd2D; 48 | rsE <= rsD; 49 | rtE <= rtD; 50 | rdE <= rdD; 51 | immE <= immD; 52 | pc_plus4E <= pc_plus4D; 53 | instrE <= instrD; 54 | pc_branchE <= pc_branchD; 55 | pred_takeE <= pred_takeD; 56 | branchE <= branchD; 57 | jump_conflictE <= jump_conflictD; 58 | end 59 | end 60 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/PIPE/if_id.v: -------------------------------------------------------------------------------- 1 | module if_id( 2 | input wire clk, rst, 3 | input wire flushD, 4 | input wire stallD, 5 | input wire [31:0] pcF, 6 | input wire [31:0] pc_plus4F, 7 | 8 | input wire [31:0] instrF, 9 | 10 | 11 | output reg [31:0] pcD, 12 | output reg [31:0] pc_plus4D, 13 | output reg [31:0] instrD 14 | ); 15 | 16 | always @(posedge clk) begin 17 | if(rst | flushD) begin 18 | pcD <= 0; 19 | pc_plus4D <= 0; 20 | instrD <= 0; 21 | end 22 | else if(~stallD) begin 23 | pcD <= pcF; 24 | pc_plus4D <= pc_plus4F; 25 | instrD <= instrF; 26 | end 27 | end 28 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/PIPE/mem_wb.v: -------------------------------------------------------------------------------- 1 | module mem_wb ( 2 | input wire clk, rst, 3 | input wire stallW, 4 | input wire [31:0] pcM, 5 | input wire [31:0] alu_outM, 6 | input wire [4:0] reg_writeM, 7 | input wire reg_write_enM, 8 | input wire [31:0] mem_rdataM, 9 | input wire [31:0] resultM, 10 | 11 | 12 | output reg [31:0] pcW, 13 | output reg [31:0] alu_outW, 14 | output reg [4:0] reg_writeW, 15 | output reg reg_write_enW, 16 | output reg [31:0] mem_rdataW, 17 | output reg [31:0] resultW 18 | ); 19 | always @(posedge clk) begin 20 | if(rst) begin 21 | pcW <= 0; 22 | alu_outW <= 0; 23 | reg_writeW <= 0; 24 | reg_write_enW <= 0; 25 | mem_rdataW <= 0; 26 | resultW <= 0; 27 | end 28 | else if(~stallW) begin 29 | pcW <= pcM; 30 | alu_outW <= alu_outM; 31 | reg_writeW <= reg_writeM; 32 | reg_write_enW <= reg_write_enM; 33 | mem_rdataW <= mem_rdataM; 34 | resultW <= resultM; 35 | end 36 | end 37 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/alu_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Create Date: 2019/06/21 16:14:50 4 | 5 | `include "aludefines.vh" 6 | `include "defines.vh" 7 | 8 | module alu_decoder( 9 | input wire clk, rst, 10 | input wire [31:0] instrD, 11 | 12 | output reg [4:0] alu_controlE 13 | ); 14 | 15 | wire [5:0] op_code; 16 | wire [4:0] rs, rt; 17 | wire [5:0] funct; 18 | reg [4:0] alu_control; 19 | 20 | assign op_code = instrD[31:26]; 21 | assign rs = instrD[25:21]; 22 | assign rt = instrD[20:16]; 23 | assign funct = instrD[5:0]; 24 | 25 | always @* begin 26 | case(op_code) 27 | `EXE_R_TYPE: 28 | case(funct) 29 | //算数和逻辑运算 30 | `EXE_AND: alu_control <= `ALU_AND; //1 31 | `EXE_OR: alu_control <= `ALU_OR; 32 | `EXE_XOR: alu_control <= `ALU_XOR; 33 | `EXE_NOR: alu_control <= `ALU_NOR; 34 | 35 | `EXE_ADD: alu_control <= `ALU_ADD; //4 36 | `EXE_SUB: alu_control <= `ALU_SUB; 37 | `EXE_ADDU: alu_control <= `ALU_ADDU; 38 | `EXE_SUBU: alu_control <= `ALU_SUBU; 39 | `EXE_SLT: alu_control <= `ALU_SLT; 40 | `EXE_SLTU: alu_control <= `ALU_SLTU; 41 | //div and mul 42 | `EXE_DIV: alu_control <= `ALU_SIGNED_DIV; 43 | `EXE_DIVU: alu_control <= `ALU_UNSIGNED_DIV; 44 | `EXE_MULT: alu_control <= `ALU_SIGNED_MULT; 45 | `EXE_MULTU: alu_control <= `ALU_UNSIGNED_MULT; 46 | 47 | //移位指令 48 | `EXE_SLL: alu_control <= `ALU_SLL_SA; //2 49 | `EXE_SRL: alu_control <= `ALU_SRL_SA; 50 | `EXE_SRA: alu_control <= `ALU_SRA_SA; 51 | `EXE_SLLV: alu_control <= `ALU_SLL; 52 | `EXE_SRLV: alu_control <= `ALU_SRL; 53 | `EXE_SRAV: alu_control <= `ALU_SRA; 54 | 55 | //hilo 56 | `EXE_MFHI: alu_control <= `ALU_MFHI; //3 57 | `EXE_MFLO: alu_control <= `ALU_MFLO; 58 | `EXE_MTHI: alu_control <= `ALU_MTHI; 59 | `EXE_MTLO: alu_control <= `ALU_MTLO; 60 | //jump 61 | `EXE_JR: alu_control <= `ALU_DONOTHING; //5 62 | // `EXE_JALR: alu_control <= `ALU_PC_PLUS8; 63 | default: alu_control <= `ALU_ADDU; 64 | endcase 65 | //I type 66 | `EXE_ADDI: alu_control <= `ALU_ADD; 67 | `EXE_ADDIU: alu_control <= `ALU_ADDU; 68 | `EXE_SLTI: alu_control <= `ALU_SLT; 69 | `EXE_SLTIU: alu_control <= `ALU_SLTU; 70 | `EXE_ANDI: alu_control <= `ALU_AND; 71 | `EXE_XORI: alu_control <= `ALU_XOR; 72 | `EXE_LUI: alu_control <= `ALU_LUI; 73 | `EXE_ORI: alu_control <= `ALU_OR; 74 | //memory 75 | `EXE_LW, `EXE_LB, `EXE_LBU, `EXE_LH, `EXE_LHU, `EXE_SW, `EXE_SB, `EXE_SH: 76 | alu_control <= `ALU_ADD; 77 | `EXE_BEQ: 78 | alu_control <= `ALU_XNOR; 79 | `EXE_BGTZ: 80 | alu_control <= `ALU_GTZ; 81 | `EXE_BLEZ: 82 | alu_control <= `ALU_LEZ; 83 | `EXE_BNE: 84 | alu_control <= `ALU_XOR; 85 | `EXE_BRANCHS: //bltz, bltzal, bgez, bgezal 86 | case(rt) 87 | `EXE_BLTZ, `EXE_BLTZAL: 88 | alu_control <= `ALU_LTZ; 89 | `EXE_BGEZ, `EXE_BGEZAL: 90 | alu_control <= `ALU_GEZ; 91 | default: 92 | alu_control <= `ALU_DONOTHING; 93 | endcase 94 | //J type 95 | `EXE_J: alu_control <= `ALU_DONOTHING; 96 | // `EXE_JAL: alu_control <= `ALU_PC_PLUS8; 97 | default: 98 | alu_control <= `ALU_DONOTHING; 99 | endcase 100 | end 101 | 102 | // ID-EX flow 103 | always@(posedge clk) begin 104 | alu_controlE <= alu_control; 105 | end 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- /src/basic_pipeline/d_cache.v: -------------------------------------------------------------------------------- 1 | module d_cache ( 2 | input wire clk, rst, 3 | 4 | input wire data_en , 5 | input wire [31:0] data_addr , 6 | output wire [31:0] data_rdata , 7 | input wire [3:0] data_wen , 8 | input wire [31:0] data_wdata , 9 | output stall , 10 | 11 | output wire data_sram_en, 12 | output wire [3:0] data_sram_wen , 13 | output wire [31:0] data_sram_addr , 14 | output wire [31:0] data_sram_wdata , 15 | input wire [31:0] data_sram_rdata , 16 | input data_sram_data_ok 17 | ); 18 | //stall 19 | assign stall = data_en & ~(|data_wen) & ~data_sram_data_ok; 20 | 21 | assign data_rdata = data_sram_rdata; 22 | 23 | assign data_sram_en = data_en; 24 | assign data_sram_wen = data_wen; 25 | assign data_sram_addr = data_addr; 26 | assign data_sram_wdata = data_wdata; 27 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/hazard.v: -------------------------------------------------------------------------------- 1 | module hazard ( 2 | input wire rst, 3 | input wire [31:0] instrE,//no use 4 | input wire [31:0] instrM,//no use 5 | input wire d_cache_stall, 6 | input wire div_stall, 7 | 8 | input wire [4:0] rsE, 9 | input wire [4:0] rtE, 10 | input wire reg_write_enM, 11 | input wire reg_write_enW, 12 | input wire [4:0] reg_writeM, 13 | input wire [4:0] reg_writeW, 14 | 15 | input wire mem_read_enM, 16 | 17 | output wire stallF, stallD, stallE, stallM, stallW, 18 | 19 | output wire [1:0] forward_aE, forward_bE 20 | ); 21 | wire stallF, stallD, stallE, stallM, stallW; 22 | wire flushF, flushD, flushE, flushM; 23 | 24 | wire [1:0] forward_aE, forward_bE; //00-> NONE, 01-> MEM, 10-> WB (LW instr) 25 | 26 | assign forward_aE = rsE != 0 && reg_write_enM && (rsE == reg_writeM) ? 2'b01 : 27 | rsE != 0 && reg_write_enW && (rsE == reg_writeW) ? 2'b10 : 28 | 2'b00; 29 | assign forward_bE = reg_write_enM && (rtE == reg_writeM) ? 2'b01 : 30 | reg_write_enW && (rtE == reg_writeW) ? 2'b10 : 31 | 2'b00; 32 | 33 | // reg stall_lw; //add, lw 数据冲突无法仅靠数据前推解决（MEM阶段无法从内存取得数据），需要先暂停形成一个气泡，再前推 34 | //更新1：通过mem_stall来暂停（相当于将MEM分为了两个阶段），故可以在MEM阶段前推 35 | // always @(*) begin 36 | // stall_lw = rst ? 1'b0 : mem_read_enM && ( 37 | // (reg_write_enM && (rsE == reg_writeM)) || 38 | // (reg_write_enM && (rtE == reg_writeM)) 39 | // ); 40 | // end 41 | 42 | assign stallF = d_cache_stall | div_stall; 43 | assign stallD = d_cache_stall | div_stall; 44 | assign stallE = d_cache_stall | div_stall; 45 | assign stallM = d_cache_stall | div_stall; 46 | assign stallW = d_cache_stall; // 不暂停,会减少jr等指令冲突; 47 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/i_cache.v: -------------------------------------------------------------------------------- 1 | module i_cache ( 2 | input wire clk, rst, 3 | 4 | input wire inst_en , 5 | input wire [31:0] inst_addr , 6 | output wire [31:0] inst_rdata , 7 | 8 | output wire inst_sram_en, 9 | output wire [31:0] inst_sram_addr , 10 | input wire [31:0] inst_sram_rdata 11 | ); 12 | 13 | assign inst_rdata = inst_sram_rdata; 14 | 15 | assign inst_sram_en = inst_en; 16 | assign inst_sram_addr = inst_addr; 17 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/mycpu_top.v: -------------------------------------------------------------------------------- 1 | module mycpu_top ( 2 | input clk,resetn, 3 | input [5:0] ext_int, 4 | 5 | //instr 6 | output inst_sram_en, 7 | output [3:0] inst_sram_wen , 8 | output [31:0] inst_sram_addr , 9 | output [31:0] inst_sram_wdata , 10 | input [31:0] inst_sram_rdata , 11 | 12 | //data 13 | output data_sram_en, 14 | output [3:0] data_sram_wen , 15 | output [31:0] data_sram_addr , 16 | output [31:0] data_sram_wdata , 17 | input [31:0] data_sram_rdata , 18 | input data_sram_data_ok , //sram没有这个信号，只是为了产生stall而编造的 19 | 20 | //debug 21 | output [31:0] debug_wb_pc , 22 | output [3:0] debug_wb_rf_wen , 23 | output [4:0] debug_wb_rf_wnum , 24 | output [31:0] debug_wb_rf_wdata 25 | ); 26 | //datapath传出来的信号 27 | wire inst_en ; 28 | wire [31:0] inst_addr ; 29 | wire [31:0] inst_rdata ; 30 | 31 | wire data_en ; 32 | wire [31:0] data_addr ; 33 | wire [31:0] data_rdata ; 34 | wire [3:0] data_wen ; 35 | wire [31:0] data_wdata ; 36 | wire d_cache_stall ; 37 | 38 | assign inst_sram_wen = 4'b0; 39 | assign inst_sram_wdata = 32'b0; 40 | 41 | datapath datapath( 42 | .clk(clk), .rst(~resetn), 43 | .ext_int(ext_int), 44 | 45 | //inst 46 | .inst_addrF(inst_addr), 47 | .inst_enF(inst_en), 48 | .instrF(inst_rdata), 49 | 50 | //data 51 | .mem_enM(data_en), 52 | .mem_addrM(data_addr), 53 | .mem_rdataM(data_rdata), 54 | .mem_wenM(data_wen), 55 | .mem_wdataM(data_wdata), 56 | .d_cache_stall(d_cache_stall) 57 | ); 58 | 59 | assign debug_wb_pc = datapath.pcW; 60 | assign debug_wb_rf_wen = datapath.reg_write_enW; 61 | assign debug_wb_rf_wnum = datapath.reg_writeW; 62 | assign debug_wb_rf_wdata = datapath.resultW; 63 | 64 | i_cache i_cache( 65 | .clk(clk), .rst(~resetn), 66 | 67 | .inst_en(inst_en), 68 | .inst_addr(inst_addr), 69 | .inst_rdata(inst_rdata), 70 | 71 | .inst_sram_en(inst_sram_en), 72 | .inst_sram_addr(inst_sram_addr), 73 | .inst_sram_rdata(inst_sram_rdata) 74 | ); 75 | 76 | d_cache d_cache( 77 | .clk(clk), .rst(~resetn), 78 | //datapath 79 | .data_en(data_en), 80 | .data_addr(data_addr), 81 | .data_rdata(data_rdata), 82 | .data_wen(data_wen), 83 | .data_wdata(data_wdata), 84 | .stall(d_cache_stall), 85 | //outer 86 | .data_sram_en(data_sram_en), 87 | .data_sram_wen(data_sram_wen), 88 | .data_sram_addr(data_sram_addr), 89 | .data_sram_wdata(data_sram_wdata), 90 | .data_sram_rdata(data_sram_rdata), 91 | .data_sram_data_ok(data_sram_data_ok) 92 | ); 93 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/simulation/mipstest.asm: -------------------------------------------------------------------------------- 1 | .data 2 | a: .word 3 3 | .text 0x0000 4 | main: 5 | addi $2, $0, 5 # initialize $2=5 0 20020005 6 | addi $3, $0, 12 # initialize $3=12 4 2003000c 7 | addi $7, $3,-9 # initialize $7=3 8 2067fff7 8 | or $4, $7, $2 # $4 <= 3 or 5 = 7 c 00e22025 9 | and $5, $3, $4 # $5 <= 12 and 7 = 4 10 00642824 10 | add $5, $5, $4 # $5 = 4 + 7 = 11 14 00a42820 11 | beq $5, $7, end # shouldn't be taken 18 10a7000c 12 | slt $4, $3, $4 # $4 = 12 < 7 = 0 1c 0064202a 13 | beq $4, $0, around # should be taken 20 10800002 14 | nop # empty inst 24 00000000 15 | addi $5, $0, 0 # shouldn't happen 28 20050000 16 | around: 17 | slt $4, $7, $2 # $4 = 3 < 5 = 1 2c 00e2202a 18 | add $7, $4, $5 # $7 = 1 + 11 = 12 30 00853820 19 | sub $7, $7, $2 # $7 = 12 - 5 = 7 34 00e23822 20 | sw $7, 68($3) # [80] = 7 38 ac670044 21 | //sw $0, 0($0) # [0] = 0 ac000000 //测试用 22 | lw $2, 80($0) # $2 = [80] = 7 3c 8c020050 23 | j end # should be taken 40 08000014 24 | nop # empty inst 44 00000000 25 | addi $2, $0, 1 # shouldn't happen 48 20020001 26 | end: 27 | sw $2, 84($0) # write adr 84=7 4c ac020054 -------------------------------------------------------------------------------- /src/basic_pipeline/simulation/mipstest.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 20020005, 4 | 2003000c, 5 | 2067fff7, 6 | 00e22025, 7 | 00642824, 8 | 00a42820, 9 | 10a7000c, 10 | 0064202a, 11 | 10800002, 12 | 00000000, 13 | 20050000, 14 | 00e2202a, 15 | 00853820, 16 | 00e23822, 17 | ac670044, 18 | 8c020050, 19 | 08000013, 20 | 00000000, 21 | 20020001, 22 | ac020054, -------------------------------------------------------------------------------- /src/basic_pipeline/simulation/top_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module testbench(); 4 | reg clk; 5 | reg rst_n; 6 | 7 | wire[31:0] writedata,dataadr; 8 | wire memwrite; 9 | 10 | soc_top soc(rst_n, clk); 11 | 12 | initial begin 13 | rst_n = 0; 14 | #133 rst_n = 1; 15 | end 16 | 17 | always begin 18 | clk <= 1; 19 | #10; 20 | clk <= 0; 21 | #10; 22 | 23 | end 24 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/soc_top.v: -------------------------------------------------------------------------------- 1 | module soc_top 2 | ( 3 | input resetn, 4 | input clk 5 | ); 6 | //debug signals 7 | wire [31:0] debug_wb_pc; 8 | wire [3 :0] debug_wb_rf_wen; 9 | wire [4 :0] debug_wb_rf_wnum; 10 | wire [31:0] debug_wb_rf_wdata; 11 | 12 | //cpu inst sram 13 | wire cpu_inst_en; 14 | wire [3 :0] cpu_inst_wen; 15 | wire [31:0] cpu_inst_addr; 16 | wire [31:0] cpu_inst_wdata; 17 | wire [31:0] cpu_inst_rdata; 18 | //cpu data sram 19 | wire cpu_data_en; 20 | wire [3 :0] cpu_data_wen; 21 | wire [31:0] cpu_data_addr; 22 | wire [31:0] cpu_data_wdata; 23 | wire [31:0] cpu_data_rdata; 24 | reg cpu_data_ok; 25 | 26 | //cpu 27 | mycpu_top cpu( 28 | .clk (clk ), 29 | .resetn (resetn), //low active 30 | .ext_int (6'd0 ), //interrupt,high active 31 | 32 | .inst_sram_en (cpu_inst_en ), 33 | .inst_sram_wen (cpu_inst_wen ), 34 | .inst_sram_addr (cpu_inst_addr ), 35 | .inst_sram_wdata (cpu_inst_wdata), 36 | .inst_sram_rdata (cpu_inst_rdata), 37 | 38 | .data_sram_en (cpu_data_en ), 39 | .data_sram_wen (cpu_data_wen ), 40 | .data_sram_addr (cpu_data_addr ), 41 | .data_sram_wdata (cpu_data_wdata), 42 | .data_sram_rdata (cpu_data_rdata), 43 | .data_sram_data_ok (cpu_data_ok), 44 | 45 | //debug 46 | .debug_wb_pc (debug_wb_pc ), 47 | .debug_wb_rf_wen (debug_wb_rf_wen ), 48 | .debug_wb_rf_wnum (debug_wb_rf_wnum ), 49 | .debug_wb_rf_wdata(debug_wb_rf_wdata) 50 | ); 51 | 52 | //inst ram 53 | inst_ram inst_ram 54 | ( 55 | .clka (~clk ), 56 | // .rsta (~resetn ), 57 | .ena (cpu_inst_en ), 58 | .wea (cpu_inst_wen ), //3:0 59 | .addra (cpu_inst_addr ), //17:0 60 | .dina (cpu_inst_wdata ), //31:0 61 | .douta (cpu_inst_rdata ) //31:0 62 | ); 63 | 64 | //data ram 65 | data_ram data_ram 66 | ( 67 | .clka (clk ), 68 | .ena (cpu_data_en & ~cpu_data_ok ), 69 | .wea (cpu_data_wen ), //3:0 70 | .addra (cpu_data_addr ), //15:0 71 | .dina (cpu_data_wdata ), //31:0 72 | .douta (cpu_data_rdata ) //31:0 73 | ); 74 | 75 | wire read, write; 76 | assign write = | cpu_data_wen; 77 | assign read = cpu_data_en & ~write; 78 | 79 | always @(posedge clk) begin 80 | cpu_data_ok <= read & ~cpu_data_ok ? 1'b1 : 1'b0; 81 | end 82 | endmodule 83 | 84 | -------------------------------------------------------------------------------- /src/basic_pipeline/utils/aludefines.vh: -------------------------------------------------------------------------------- 1 | //alu defines 2 | `define ALU_AND 5'b0_0000 3 | `define ALU_OR 5'b0_0001 4 | `define ALU_ADD 5'b0_0010 5 | `define ALU_SUB 5'b0_0011 6 | `define ALU_SLT 5'b0_0100 7 | `define ALU_SLL 5'b0_0101 8 | `define ALU_SRL 5'b0_0110 9 | `define ALU_SRA 5'b0_0111 10 | `define ALU_SLTU 5'b0_1000 11 | `define ALU_UNSIGNED_MULT 5'b0_1001 12 | `define ALU_XNOR 5'b0_1010 13 | `define ALU_XOR 5'b0_1011 14 | `define ALU_NOR 5'b0_1100 15 | `define ALU_UNSIGNED_DIV 5'b0_1101 16 | `define ALU_SIGNED_MULT 5'b0_1110 17 | `define ALU_SIGNED_DIV 5'b0_1111 18 | `define ALU_LUI 5'b1_0000 19 | `define ALU_MFHI 5'b1_0001 20 | `define ALU_MTHI 5'b1_0010 21 | `define ALU_MFLO 5'b1_0011 22 | `define ALU_MTLO 5'b1_0100 23 | `define ALU_ADDU 5'b1_0101 24 | `define ALU_SUBU 5'b1_0110 25 | `define ALU_LEZ 5'b1_0111 26 | `define ALU_GTZ 5'b1_1000 27 | `define ALU_GEZ 5'b1_1001 28 | `define ALU_LTZ 5'b1_1010 29 | `define ALU_SLL_SA 5'b1_1011 30 | `define ALU_SRL_SA 5'b1_1100 31 | `define ALU_SRA_SA 5'b1_1101 32 | // 5'b1_1110 33 | `define ALU_DONOTHING 5'b1_1111 -------------------------------------------------------------------------------- /src/basic_pipeline/utils/defines.vh: -------------------------------------------------------------------------------- 1 | 2 | `define EXE_R_TYPE 6'b000000 3 | //logic inst 4 | `define EXE_NOP 6'b000000 5 | `define EXE_AND 6'b100100 6 | `define EXE_OR 6'b100101 7 | `define EXE_XOR 6'b100110 8 | `define EXE_NOR 6'b100111 9 | `define EXE_ANDI 6'b001100 10 | `define EXE_ORI 6'b001101 11 | `define EXE_XORI 6'b001110 12 | `define EXE_LUI 6'b001111 13 | //shift inst 14 | `define EXE_SLL 6'b000000 15 | `define EXE_SLLV 6'b000100 16 | `define EXE_SRL 6'b000010 17 | `define EXE_SRLV 6'b000110 18 | `define EXE_SRA 6'b000011 19 | `define EXE_SRAV 6'b000111 20 | //move inst 21 | `define EXE_MFHI 6'b010000 22 | `define EXE_MTHI 6'b010001 23 | `define EXE_MFLO 6'b010010 24 | `define EXE_MTLO 6'b010011 25 | //算术运算 26 | `define EXE_SLT 6'b101010 27 | `define EXE_SLTU 6'b101011 28 | `define EXE_SLTI 6'b001010 29 | `define EXE_SLTIU 6'b001011 30 | `define EXE_ADD 6'b100000 31 | `define EXE_ADDU 6'b100001 32 | `define EXE_SUB 6'b100010 33 | `define EXE_SUBU 6'b100011 34 | `define EXE_ADDI 6'b001000 35 | `define EXE_ADDIU 6'b001001 36 | 37 | `define EXE_MULT 6'b011000 38 | `define EXE_MULTU 6'b011001 39 | 40 | `define EXE_DIV 6'b011010 41 | `define EXE_DIVU 6'b011011 42 | //jump 43 | `define EXE_J 6'b000010 44 | `define EXE_JAL 6'b000011 45 | `define EXE_JALR 6'b001001 46 | `define EXE_JR 6'b001000 47 | //branch 48 | `define EXE_BEQ 6'b000100 49 | `define EXE_BGTZ 6'b000111 50 | `define EXE_BNE 6'b000101 51 | `define EXE_BLEZ 6'b000110 52 | `define EXE_BRANCHS 6'b000001 // 53 | `define EXE_BLTZ 5'b00000 54 | `define EXE_BLTZAL 5'b10000 55 | `define EXE_BGEZAL 5'b10001 56 | `define EXE_BGEZ 5'b00001 57 | //load/store 58 | `define EXE_LB 6'b100000 59 | `define EXE_LBU 6'b100100 60 | `define EXE_LH 6'b100001 61 | `define EXE_LHU 6'b100101 62 | `define EXE_LL 6'b110000 63 | `define EXE_LW 6'b100011 64 | `define EXE_LWL 6'b100010 65 | `define EXE_LWR 6'b100110 66 | `define EXE_SB 6'b101000 67 | `define EXE_SC 6'b111000 68 | `define EXE_SH 6'b101001 69 | `define EXE_SW 6'b101011 70 | `define EXE_SWL 6'b101010 71 | `define EXE_SWR 6'b101110 72 | //trap 73 | `define EXE_SYSCALL 6'b001100 74 | `define EXE_BREAK 6'b001101 75 | 76 | `define EXE_TEQ 6'b110100 77 | `define EXE_TEQI 5'b01100 78 | `define EXE_TGE 6'b110000 79 | `define EXE_TGEI 5'b01000 80 | `define EXE_TGEIU 5'b01001 81 | `define EXE_TGEU 6'b110001 82 | `define EXE_TLT 6'b110010 83 | `define EXE_TLTI 5'b01010 84 | `define EXE_TLTIU 5'b01011 85 | `define EXE_TLTU 6'b110011 86 | `define EXE_TNE 6'b110110 87 | `define EXE_TNEI 5'b01110 88 | 89 | // `define EXE_ERET 32'b01000010000000000000000000011000 90 | `define EXE_ERET 26'b10000000000000000000011000 91 | `define EXE_ERET_MFTC 6'b010000 92 | 93 | `define EXE_SYNC 6'b001111 94 | `define EXE_PREF 6'b110011 95 | 96 | `define EXE_MTC0 5'b00100 97 | `define EXE_MFC0 5'b00000 98 | 99 | //Exception code 100 | `define EXC_CODE_INT 5'h00 101 | `define EXC_CODE_ADEL 5'h04 102 | `define EXC_CODE_ADES 5'h05 103 | `define EXC_CODE_SYS 5'h08 104 | `define EXC_CODE_BP 5'h09 105 | `define EXC_CODE_RI 5'h0a 106 | `define EXC_CODE_OV 5'h0c 107 | 108 | //Exception type 109 | `define EXC_TYPE_INT 32'h0000_0001 110 | `define EXC_TYPE_ADEL 32'h0000_0004 111 | `define EXC_TYPE_ADES 32'h0000_0005 112 | `define EXC_TYPE_SYS 32'h0000_0008 113 | `define EXC_TYPE_BP 32'h0000_0009 114 | `define EXC_TYPE_RI 32'h0000_000a 115 | `define EXC_TYPE_OV 32'h0000_000c 116 | `define EXC_TYPE_ERET 32'h0000_000e 117 | `define EXC_TYPE_NOEXC 32'h0000_0000 118 | 119 | //CP0 120 | `define CP0_REG_BADVADDR 5'b01000 121 | `define CP0_REG_COUNT 5'b01001 122 | `define CP0_REG_COMPARE 5'b01011 123 | `define CP0_REG_STATUS 5'b01100 124 | `define CP0_REG_CAUSE 5'b01101 125 | `define CP0_REG_EPC 5'b01110 126 | `define CP0_REG_PRID 5'b01111 127 | `define CP0_REG_CONFIG 5'b10000 128 | 129 | `define InterruptAssert 1'b1 130 | `define InterruptNotAssert 1'b0 131 | `define InDelaySlot 1'b1 132 | `define NotInDelaySlot 1'b0 133 | 134 | `define ZeroWord 32'd0 135 | -------------------------------------------------------------------------------- /src/basic_pipeline/utils/inst_ascii_decoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2018/08/06 15:21:16 7 | // Design Name: 8 | // Module Name: instdec 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `timescale 1ns / 1ps 23 | 24 | `include "defines.vh" 25 | 26 | 27 | module inst_ascii_decoder( 28 | input wire [31:0] instr, 29 | output reg [39:0] ascii 30 | ); 31 | 32 | always @(*) 33 | begin 34 | ascii<="N-R"; 35 | case(instr[31:26]) 36 | `EXE_NOP: // R-type 37 | begin 38 | case(instr[5:0]) 39 | /* logic instraction */ 40 | `EXE_AND: ascii<= "AND"; 41 | `EXE_OR: ascii<= "OR"; 42 | `EXE_XOR: ascii<= "XOR"; 43 | `EXE_NOR: ascii<= "NOR"; 44 | /* shift instraction */ 45 | `EXE_SLL: ascii<= "SLL"; 46 | `EXE_SRL: ascii<= "SRL"; 47 | `EXE_SRA: ascii<= "SRA"; 48 | `EXE_SLLV: ascii<= "SLLV"; 49 | `EXE_SRLV: ascii<= "SRLV"; 50 | `EXE_SRAV: ascii<= "SRAV"; 51 | /* move instraction */ 52 | `EXE_MFHI: ascii<= "MFHI"; 53 | `EXE_MTHI: ascii<= "MTHI"; 54 | `EXE_MFLO: ascii<= "MFLO"; 55 | `EXE_MTLO: ascii<= "MTLO"; 56 | /* arithemtic instraction */ 57 | `EXE_ADD: ascii<= "ADD"; 58 | `EXE_ADDU: ascii<= "ADDU"; 59 | `EXE_SUB: ascii<= "SUB"; 60 | `EXE_SUBU: ascii<= "SUBU"; 61 | `EXE_SLT: ascii<= "SLT"; 62 | `EXE_SLTU: ascii<= "SLTU"; 63 | 64 | `EXE_MULT: ascii<= "MULT"; 65 | `EXE_MULTU: ascii<= "MULTU"; 66 | `EXE_DIV: ascii<= "DIV"; 67 | `EXE_DIVU: ascii<= "DIVU"; 68 | /* jump instraction */ 69 | `EXE_JR: ascii<= "JR"; 70 | `EXE_JALR: ascii<= "JALR"; 71 | 72 | `EXE_SYSCALL: ascii<= "SYSC"; 73 | `EXE_BREAK: ascii<= "BRE"; 74 | default: ascii<="N-R"; 75 | endcase 76 | end 77 | `EXE_ANDI: ascii<= "ANDI"; 78 | `EXE_XORI: ascii<= "XORI"; 79 | `EXE_LUI: ascii<= "LUI"; 80 | `EXE_ORI: ascii<= "ORI"; 81 | 82 | `EXE_ADDI: ascii<= "ADDI"; 83 | `EXE_ADDIU: ascii<= "ADDIU"; 84 | `EXE_SLTI: ascii<= "SLTI"; 85 | `EXE_SLTIU: ascii<= "SLTIU"; 86 | 87 | `EXE_J: ascii<= "J"; 88 | `EXE_JAL: ascii<= "JAL"; 89 | 90 | `EXE_BEQ: ascii<= "BEQ"; 91 | `EXE_BGTZ: ascii<= "BGTZ"; 92 | `EXE_BLEZ: ascii<= "BLEZ"; 93 | `EXE_BNE: ascii<= "BNE"; 94 | 95 | `EXE_LB: ascii<= "LB"; 96 | `EXE_LBU: ascii<= "LBU"; 97 | `EXE_LH: ascii<= "LH"; 98 | `EXE_LHU: ascii<= "LHU"; 99 | `EXE_LW: ascii<= "LW"; 100 | `EXE_SB: ascii<= "SB"; 101 | `EXE_SH: ascii<= "SH"; 102 | `EXE_SW: ascii<= "SW"; 103 | 6'b000001: begin 104 | case (instr[20:16]) 105 | `EXE_BGEZ: ascii<= "BGEZ"; 106 | `EXE_BGEZAL: ascii<= "BGEZAL"; 107 | `EXE_BLTZ: ascii<= "BLTZ"; 108 | `EXE_BLTZAL: ascii<= "BLTZAL"; 109 | default : ascii<= " "; 110 | endcase 111 | end 112 | 6'b010000: begin 113 | if(instr==`EXE_ERET) begin 114 | ascii<="ERET"; 115 | end else begin 116 | case (instr[25:21]) 117 | 5'b00100: ascii<="MTOC0"; 118 | 5'b00000: ascii<="MFC0"; 119 | endcase 120 | end 121 | end 122 | default: ascii<= "N-R"; 123 | endcase 124 | if(instr==`EXE_ERET) 125 | ascii<= "ERET"; 126 | if(!instr) 127 | ascii<= "NOP"; 128 | end 129 | 130 | endmodule 131 | 132 | -------------------------------------------------------------------------------- /src/basic_pipeline/utils/mux2.v: -------------------------------------------------------------------------------- 1 | module mux2 #(parameter WIDTH=32) ( 2 | input wire [WIDTH-1:0] x0, x1, 3 | input wire sel, 4 | 5 | output wire [WIDTH-1:0] y 6 | ); 7 | assign y = sel ? x1 : x0; 8 | endmodule -------------------------------------------------------------------------------- /src/basic_pipeline/utils/mux4.v: -------------------------------------------------------------------------------- 1 | module mux4 #(parameter WIDTH=32) ( 2 | input wire [WIDTH-1:0] x0, x1, x2, x3, 3 | input wire [1:0] sel, 4 | 5 | output wire [WIDTH-1:0] y 6 | ); 7 | assign y = sel[1] ? (sel[0] ? x3: x2): 8 | (sel[0] ? x1: x0); 9 | 10 | endmodule -------------------------------------------------------------------------------- /todo.txt: -------------------------------------------------------------------------------- 1 | +-- 2 | 完善每个模块； 3 | main_decoder:阻塞赋值与非阻塞赋值的区别； 4 | 大赛允许使用扇出优化吗？ 5 | 6 | +-- 7 | reg_write_en: 8 | R_TYPE: 9 | NON: MTHI, MTLO, JR; 10 | I_TYPE: 11 | 12 | 13 | reg_dst: 14 | -------------------------------------------------------------------------------- /待做.txt: -------------------------------------------------------------------------------- 1 | +-- 2 | 完善每个模块； 3 | main_decoder:阻塞赋值与非阻塞赋值的区别； 4 | 大赛允许使用扇出优化吗？ 5 | 6 | +-- 7 | reg_write_en: 8 | R_TYPE: 9 | NON: MTHI, MTLO, JR; 10 | I_TYPE: 11 | 12 | 13 | reg_dst: 14 | -------------------------------------------------------------------------------- /重庆大学.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/14010007517/2020NSCSCC/012c80caa98d3d1abebb8ba8ab78a93f6d8c5663/重庆大学.pptx --------------------------------------------------------------------------------