├── rjtag_phat
├── main.ucf
├── overall.sym
├── divider_slow.vhd
├── delayer.vhd
├── divider_fast.sym
├── divider_slow.sym
├── hard_reset.sym
├── delayer.sym
├── detect_10.sym
├── reset_proc.sym
├── slower.sym
├── post_proc.sym
├── post_proc.vhd
├── slower.vhd
├── overall.sch
└── rjtag_phat.xise
├── rgh12_phat
├── main.ucf
├── divider.vhd
├── divider.sym
├── reseter.vhd
├── weird.vhd
├── reseter.sym
├── weird.sym
├── delayer.vhd
├── counter.vhd
├── post_proc.vhd
├── counter.sym
├── post_proc.sym
├── slower.sym
├── slower.vhd
├── weird.sch
├── overall.sch
└── rgh12_phat.xise
├── .gitattributes
├── .gitignore
└── rgh2_phat
├── switcher.vhd
├── div3.vhd
├── divider_fast.vhd
├── divider_slow.vhd
├── main.ucf
├── div3.sym
├── divider_slow.sym
├── clk_300_to_200.sym
├── weird.vhd
├── weird.sym
├── delayer.vhd
├── switcher.sym
├── slower.sym
├── delayer.sym
├── post_proc.sym
├── slower.vhd
├── dualnand.sym
├── dualnand.vhd
├── post_proc.vhd
├── weird.sch
├── clk_300_to_200.sch
├── overall.sch
└── rgh2_phat.xise
/rjtag_phat/main.ucf:
--------------------------------------------------------------------------------
1 | NET "CLK" LOC = "H1" | IOSTANDARD = LVCMOS33 | TNM_NET = clk_int;
2 |
3 | NET "DBG" LOC = "M2" | IOSTANDARD = LVCMOS33 ;
4 | NET "POST" LOC = "D13" | IOSTANDARD = LVCMOS18 | SCHMITT_TRIGGER ;
5 | NET "RST" LOC = "G1" | IOSTANDARD = LVCMOS18 ;
6 | NET "SCL" LOC = "H2" | IOSTANDARD = LVCMOS33 ;
7 | NET "SDA" LOC = "J1" | IOSTANDARD = LVCMOS33 ;
--------------------------------------------------------------------------------
/rjtag_phat/overall.sym:
--------------------------------------------------------------------------------
1 |
2 |
3 | BLOCK
4 | 2014-11-22T19:32:19
5 |
6 |
7 |
8 |
9 |
10 |
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/rgh12_phat/main.ucf:
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1 | #petrozpl idea to pass clock through global net
2 | NET "CLK" LOC = "H1" | IOSTANDARD = LVCMOS33;
3 | #used in weird module
4 | NET "GCK" BUFG=CLK | IOSTANDARD = LVCMOS33;
5 |
6 | NET "DBG" LOC = "M2" | IOSTANDARD = LVCMOS33 ;
7 | NET "POST" LOC = "D13" | IOSTANDARD = LVCMOS18 | SCHMITT_TRIGGER;
8 | NET "RST" LOC = "G1" | IOSTANDARD = LVCMOS18 | SLEW=SLOW;
9 | NET "PLL" LOC = "J1" | IOSTANDARD = LVCMOS33 ;
--------------------------------------------------------------------------------
/.gitattributes:
--------------------------------------------------------------------------------
1 | # Auto detect text files and perform LF normalization
2 | * text=auto
3 |
4 | # Custom for Visual Studio
5 | *.cs diff=csharp
6 | *.sln merge=union
7 | *.csproj merge=union
8 | *.vbproj merge=union
9 | *.fsproj merge=union
10 | *.dbproj merge=union
11 |
12 | # Standard to msysgit
13 | *.doc diff=astextplain
14 | *.DOC diff=astextplain
15 | *.docx diff=astextplain
16 | *.DOCX diff=astextplain
17 | *.dot diff=astextplain
18 | *.DOT diff=astextplain
19 | *.pdf diff=astextplain
20 | *.PDF diff=astextplain
21 | *.rtf diff=astextplain
22 | *.RTF diff=astextplain
23 |
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/.gitignore:
--------------------------------------------------------------------------------
1 | *.lso
2 | *.cmd_log
3 | *.spl
4 | *.xreport
5 | *.jhd
6 | *.prj
7 | *.stx
8 | *.gise
9 | *.html
10 | *.schlog
11 | *.xst
12 | *.vho
13 | *.xmsgs
14 | *.ref
15 | *.bld
16 | *.chk
17 | *.cxt
18 | *.gyd
19 | *.log
20 | *.mfd
21 | *.nga
22 | *.ngc
23 | *.ngd
24 | *.ngr
25 | *.pad
26 | *.pnx
27 | *.rpt
28 | *.syr
29 | *.tim
30 | *.tspec
31 | *.vhf
32 | *.vm6
33 | *.xml
34 | *.js
35 | *.htm
36 | *.tmp
37 | *.jpg
38 | *.gif
39 | *.css
40 | *.xrpt
41 | *.csv
42 | rgh2_phat/sch2HdlBatchFile
43 | *.dat
44 | *.phd
45 | *.err
46 | *.xbcd
47 | *.lst
48 | *.projectmgr
49 | rjtag_phat/sch2HdlBatchFile
50 | *.cmd
51 | rgh2_phat/overall.jed
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/rgh2_phat/switcher.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | --used to momentally switch the nands or change the default one
5 | --may be useful to flash the second nand from the another one
6 |
7 | entity switcher is
8 | Port ( SW : in STD_LOGIC;
9 | S1 : in STD_LOGIC;
10 | S2 : in STD_LOGIC;
11 | O1 : out STD_LOGIC;
12 | O2 : out STD_LOGIC);
13 | end switcher;
14 |
15 | architecture arch of switcher is
16 |
17 | begin
18 |
19 | process (SW) is
20 | begin
21 | if(SW = '1') then
22 | O1 <= S1;
23 | O2 <= S2;
24 | else
25 | O1 <= S2;
26 | O2 <= S1;
27 | end if;
28 | end process;
29 | end arch;
30 |
31 |
--------------------------------------------------------------------------------
/rgh2_phat/div3.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- divides the 300mhz clock into 100 mhz
5 | entity div3 is
6 | Port ( CLK : in STD_LOGIC;
7 | CLK3 : out STD_LOGIC);
8 | end div3;
9 |
10 | architecture arch of div3 is
11 | constant div_value : integer := 2;
12 | signal counter: integer range 0 to div_value := 0;
13 | signal new_clk : STD_LOGIC := '0';
14 | begin
15 |
16 | process (CLK, new_clk) is
17 | begin
18 | if CLK'event then
19 | if(counter < div_value) then
20 | counter <= counter + 1;
21 | else
22 | counter <= 0;
23 | new_clk <= not new_clk;
24 | end if;
25 | end if;
26 | CLK3 <= new_clk;
27 | end process;
28 |
29 | end arch;
30 |
31 |
--------------------------------------------------------------------------------
/rgh12_phat/divider.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- used to down the clock from 150 mhz to 50 mhz
5 | entity divider is
6 | Port ( CLK : in STD_LOGIC;
7 | CLK3 : out STD_LOGIC);
8 | end divider;
9 |
10 | architecture arch of divider is
11 | constant div_value : integer := 2;
12 | signal counter: integer range 0 to div_value := 0;
13 | signal new_clk : STD_LOGIC := '0';
14 | begin
15 |
16 | process (CLK, new_clk) is
17 | begin
18 | if CLK'event then
19 | if(counter < div_value) then
20 | counter <= counter + 1;
21 | else
22 | counter <= 0;
23 | new_clk <= not new_clk;
24 | end if;
25 | end if;
26 | CLK3 <= new_clk;
27 | end process;
28 |
29 | end arch;
30 |
31 |
--------------------------------------------------------------------------------
/rgh2_phat/divider_fast.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- divides the 300mhz clock into 7.5 mhz
5 | entity divider_fast is
6 | Port ( CLK : in STD_LOGIC;
7 | CLK2 : out STD_LOGIC);
8 | end divider_fast;
9 |
10 | architecture arch of divider_fast is
11 | constant div_value : integer := 19;
12 | signal counter: integer range 0 to div_value := 0;
13 | signal new_clk : STD_LOGIC := '0';
14 | begin
15 |
16 | process (CLK, new_clk) is
17 | begin
18 | if rising_edge(CLK) then
19 | if(counter < div_value) then
20 | counter <= counter + 1;
21 | else
22 | counter <= 0;
23 | new_clk <= not new_clk;
24 | end if;
25 | end if;
26 | CLK2 <= new_clk;
27 | end process;
28 |
29 | end arch;
30 |
31 |
--------------------------------------------------------------------------------
/rjtag_phat/divider_slow.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- divides the 300mhz clock into 0.75 mhz
5 | entity divider_slow is
6 | Port ( CLK : in STD_LOGIC;
7 | CLK3 : out STD_LOGIC);
8 | end divider_slow;
9 |
10 | architecture arch of divider_slow is
11 | constant div_value : integer := 199;
12 | signal counter: integer range 0 to div_value := 0;
13 | signal new_clk : STD_LOGIC := '0';
14 | begin
15 |
16 | process (CLK, new_clk) is
17 | begin
18 | if rising_edge(CLK) then
19 | if(counter < div_value) then
20 | counter <= counter + 1;
21 | else
22 | counter <= 0;
23 | new_clk <= not new_clk;
24 | end if;
25 | end if;
26 | CLK3 <= new_clk;
27 | end process;
28 |
29 | end arch;
30 |
31 |
--------------------------------------------------------------------------------
/rgh2_phat/divider_slow.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- used to down the clock for i2c and other things
5 | entity divider_slow is
6 | Port ( CLK : in STD_LOGIC;
7 | CLK3 : out STD_LOGIC);
8 | end divider_slow;
9 |
10 | architecture arch of divider_slow is
11 | constant div_value : integer := 187;
12 | signal counter: integer range 0 to div_value := 0;
13 | signal new_clk : STD_LOGIC := '0';
14 | begin
15 |
16 | process (CLK, new_clk) is
17 | begin
18 | if rising_edge(CLK) then
19 | if(counter < div_value) then
20 | counter <= counter + 1;
21 | else
22 | counter <= 0;
23 | new_clk <= not new_clk;
24 | end if;
25 | end if;
26 | CLK3 <= new_clk;
27 | end process;
28 |
29 | end arch;
30 |
31 |
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/rgh2_phat/main.ucf:
--------------------------------------------------------------------------------
1 | NET "CLK" LOC = "H1" | IOSTANDARD = LVCMOS33;
2 | NET "GCK" BUFG=CLK | IOSTANDARD = LVCMOS33;
3 | NET "DBG" LOC = "M2" | IOSTANDARD = LVCMOS33 ;
4 | NET "POST" LOC = "D13" | IOSTANDARD = LVCMOS18 | SCHMITT_TRIGGER;
5 | NET "RST" LOC = "G1" | IOSTANDARD = LVCMOS18 | SLEW=SLOW;
6 | NET "SCL" LOC = "H2" | IOSTANDARD = LVCMOS33 ;
7 | NET "SDA" LOC = "J1" | IOSTANDARD = LVCMOS33 ;
8 | NET "BUT" LOC = "B7" | IOSTANDARD = LVCMOS18 | SCHMITT_TRIGGER; #DIP1 or R10
9 | NET "CES" LOC = "B8" | IOSTANDARD = LVCMOS18 ; #DIP3 or R8
10 | NET "CED" LOC = "A8" | IOSTANDARD = LVCMOS18 ; #DIP4 or R7
11 | NET "SMC" LOC = "C11" | IOSTANDARD = LVCMOS18 ; #DIP8 or R3
12 | #NET "SW" LOC = "A11" | IOSTANDARD = LVCMOS18 | SCHMITT_TRIGGER; #DIP6 or R5
13 | NET "CIN" LOC = "B11" | IOSTANDARD = LVCMOS18 ; #DIP7 or R4
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/rjtag_phat/delayer.vhd:
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1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- this shit saves the 1.5 seconds (only in case of successfull start)
5 |
6 | entity delayer is
7 | Port ( to_slow : in STD_LOGIC;
8 | de_slow : out STD_LOGIC;
9 | CLK3 : in STD_LOGIC); --300/2 / 200 / 2 / 20 / 2 = 9375 hz
10 | end delayer;
11 |
12 | architecture arch of delayer is
13 | signal cnt: integer range 0 to 6000 := 0;
14 | begin
15 | process(to_slow, CLK3) is
16 | begin
17 | if(to_slow = '0') then
18 | de_slow <= '0';
19 | cnt <= 0;
20 | else
21 | if(rising_edge(CLK3) ) then
22 | if (cnt < 6000) then
23 | cnt <= cnt + 1;
24 | end if;
25 | if(cnt > 5700) then
26 | de_slow <= '1';
27 | else
28 | de_slow <= '0';
29 | end if;
30 | end if;
31 | end if;
32 | end process;
33 | end arch;
34 |
35 |
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/rgh2_phat/div3.sym:
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/rgh12_phat/divider.sym:
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/rgh2_phat/divider_slow.sym:
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/rjtag_phat/divider_fast.sym:
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/rjtag_phat/divider_slow.sym:
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/rgh2_phat/clk_300_to_200.sym:
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/rgh12_phat/reseter.vhd:
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1 | -- RGH 1.2 NEW DESIGN
2 | library IEEE;
3 | use IEEE.STD_LOGIC_1164.ALL;
4 |
5 | -- this module does the reset pulse
6 | -- 150mhz precision!
7 |
8 | entity reseter is
9 | Port ( clk : in STD_LOGIC;
10 | to_reset : in STD_LOGIC;
11 | RST : out STD_LOGIC := 'Z');
12 | end reseter;
13 |
14 | architecture arch of reseter is
15 |
16 | signal m_reset : STD_LOGIC := '0';
17 |
18 | constant len : integer := 6;
19 | signal cnt: integer range 0 to len + 1 := len + 1;
20 |
21 | begin
22 | process (clk) is
23 | begin
24 | if rising_edge(clk) then
25 |
26 | if to_reset /= m_reset then
27 | m_reset <= to_reset;
28 | cnt <= 0;
29 | end if;
30 |
31 | if cnt < len then
32 | RST <= '0';
33 | cnt <= cnt + 1;
34 | else if cnt = len then
35 | cnt <= cnt + 1;
36 | RST <= '1';
37 | else
38 | RST <= 'Z';
39 | end if; end if;
40 | end if;
41 | end process;
42 |
43 | end arch;
44 |
45 |
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/rgh2_phat/weird.vhd:
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1 | ----------------------------------------------------------------------------------
2 | -- Company:
3 | -- Engineer:
4 | --
5 | -- Create Date: 21:10:57 02/22/2015
6 | -- Design Name:
7 | -- Module Name: weird - arch
8 | -- Project Name:
9 | -- Target Devices:
10 | -- Tool versions:
11 | -- Description:
12 | --
13 | -- Dependencies:
14 | --
15 | -- Revision:
16 | -- Revision 0.01 - File Created
17 | -- Additional Comments:
18 | --
19 | ----------------------------------------------------------------------------------
20 | library IEEE;
21 | use IEEE.STD_LOGIC_1164.ALL;
22 |
23 | -- Uncomment the following library declaration if using
24 | -- arithmetic functions with Signed or Unsigned values
25 | --use IEEE.NUMERIC_STD.ALL;
26 |
27 | -- Uncomment the following library declaration if instantiating
28 | -- any Xilinx primitives in this code.
29 | --library UNISIM;
30 | --use UNISIM.VComponents.all;
31 |
32 | entity weird is
33 | end weird;
34 |
35 | architecture arch of weird is
36 |
37 | begin
38 |
39 |
40 | end arch;
41 |
42 |
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/rgh12_phat/weird.vhd:
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1 | ----------------------------------------------------------------------------------
2 | -- Company:
3 | -- Engineer:
4 | --
5 | -- Create Date: 21:10:57 02/22/2015
6 | -- Design Name:
7 | -- Module Name: weird - arch
8 | -- Project Name:
9 | -- Target Devices:
10 | -- Tool versions:
11 | -- Description:
12 | --
13 | -- Dependencies:
14 | --
15 | -- Revision:
16 | -- Revision 0.01 - File Created
17 | -- Additional Comments:
18 | --
19 | ----------------------------------------------------------------------------------
20 | library IEEE;
21 | use IEEE.STD_LOGIC_1164.ALL;
22 |
23 | -- Uncomment the following library declaration if using
24 | -- arithmetic functions with Signed or Unsigned values
25 | --use IEEE.NUMERIC_STD.ALL;
26 |
27 | -- Uncomment the following library declaration if instantiating
28 | -- any Xilinx primitives in this code.
29 | --library UNISIM;
30 | --use UNISIM.VComponents.all;
31 |
32 | entity weird is
33 | end weird;
34 |
35 | architecture arch of weird is
36 |
37 | begin
38 |
39 |
40 | end arch;
41 |
42 |
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/rgh12_phat/reseter.sym:
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/rjtag_phat/hard_reset.sym:
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/rjtag_phat/delayer.sym:
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/rjtag_phat/detect_10.sym:
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/rjtag_phat/reset_proc.sym:
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/rgh12_phat/weird.sym:
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/rgh2_phat/weird.sym:
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/rgh12_phat/delayer.vhd:
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1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- this shit saves the 1.5 seconds (only in case of successfull start or special SMC)
5 |
6 | entity delayer is
7 | Port ( in_slow : in STD_LOGIC;
8 | in_do : in STD_LOGIC;
9 | out_slow : out STD_LOGIC;
10 | out_do: out STD_LOGIC;
11 | CLK3 : in STD_LOGIC);
12 | end delayer;
13 |
14 | architecture arch of delayer is
15 | constant del: integer := 685; --max value for jasper is 705, but you should let xbox to stabilize frequency
16 | --min adequate value (slim) is 500-550. use it when xbox doesn't start
17 | signal cnt: integer range 0 to del := 0;
18 | signal old_do : STD_LOGIC;
19 | signal old_do1 : STD_LOGIC;
20 |
21 | begin
22 | process(in_slow, CLK3) is
23 | begin
24 | out_slow <= in_slow;
25 | if(in_slow = '0') then
26 | old_do <= in_do;
27 | old_do1 <= old_do;
28 | out_do <= old_do;
29 | cnt <= 0;
30 | else
31 | if(rising_edge(CLK3) ) then
32 | if (cnt < del) then
33 | cnt <= cnt + 1;
34 | out_do <= old_do1;
35 | else
36 | out_do <= in_do;
37 | old_do <= in_do;
38 | end if;
39 | end if;
40 | end if;
41 | end process;
42 | end arch;
43 |
44 |
--------------------------------------------------------------------------------
/rgh2_phat/delayer.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | -- this shit saves the 1.5 seconds (only in case of successfull start or special SMC)
5 |
6 | entity delayer is
7 | Port ( in_slow : in STD_LOGIC;
8 | in_do : in STD_LOGIC;
9 | out_slow : out STD_LOGIC;
10 | out_do: out STD_LOGIC;
11 | CLK3 : in STD_LOGIC);
12 | end delayer;
13 |
14 | architecture arch of delayer is
15 | constant del: integer := 685; --max value for jasper is 705, but you should let xbox to stabilize frequency
16 | --min adequate value (slim) is 500-550. use it when xbox doesn't start
17 | signal cnt: integer range 0 to del := 0;
18 | signal old_do : STD_LOGIC;
19 | signal old_do1 : STD_LOGIC;
20 |
21 | begin
22 | process(in_slow, CLK3) is
23 | begin
24 | out_slow <= in_slow;
25 | if(in_slow = '0') then
26 | old_do <= in_do;
27 | old_do1 <= old_do;
28 | out_do <= old_do;
29 | cnt <= 0;
30 | else
31 | if(rising_edge(CLK3) ) then
32 | if (cnt < del) then
33 | cnt <= cnt + 1;
34 | out_do <= old_do1;
35 | else
36 | out_do <= in_do;
37 | old_do <= in_do;
38 | end if;
39 | end if;
40 | end if;
41 | end process;
42 | end arch;
43 |
44 |
--------------------------------------------------------------------------------
/rgh12_phat/counter.vhd:
--------------------------------------------------------------------------------
1 | -- RGH 1.2 NEW DESIGN
2 | library IEEE;
3 | use IEEE.STD_LOGIC_1164.ALL;
4 |
5 | -- this module shall count timing for cpu reset
6 | -- also must provide retail compatibility
7 |
8 | entity counter is
9 | Port ( clk_50 : in STD_LOGIC;
10 | to_count : in STD_LOGIC;
11 | callback : in STD_LOGIC;
12 | timeout : out STD_LOGIC := '0';
13 | to_reset : out STD_LOGIC := '0');
14 | end counter;
15 |
16 | architecture arch of counter is
17 |
18 | signal m_reset : STD_LOGIC := '0';
19 | constant timing : integer := 364415; --50 mhz
20 | constant slow_delay : integer := 50000;
21 | constant cnt_width : integer := timing + 1 + slow_delay;
22 | signal cnt: integer range 0 to cnt_width:= 0;
23 |
24 | begin
25 | process (clk_50) is
26 | begin
27 | if rising_edge(clk_50) then
28 | if (to_count = '0' or callback = '0') then
29 | cnt <= 0;
30 | timeout <= '0';
31 | else
32 | if cnt < cnt_width then
33 | cnt <= cnt + 1;
34 | timeout <= '0';
35 | else
36 | timeout <= '1';
37 | end if;
38 |
39 | if cnt = timing then
40 | m_reset <= not m_reset;
41 | end if;
42 | end if;
43 | end if;
44 | end process;
45 |
46 | process (m_reset) is
47 | begin
48 | to_reset <= m_reset;
49 | end process;
50 |
51 | end arch;
52 |
53 |
--------------------------------------------------------------------------------
/rgh12_phat/post_proc.vhd:
--------------------------------------------------------------------------------
1 | -- RGH 1.2 NEW DESIGN
2 | library IEEE;
3 | use IEEE.STD_LOGIC_1164.ALL;
4 |
5 | -- this module counts post signals and tells what to do to other modules
6 |
7 | entity post_proc is
8 | Port ( POSTBIT : in STD_LOGIC;
9 | RST : in STD_LOGIC ;
10 | to_slow : out STD_LOGIC := '0';
11 | DBG : out STD_LOGIC := '0';
12 | to_count : out STD_LOGIC := '0');
13 | end post_proc;
14 |
15 | architecture arch of post_proc is
16 |
17 | constant post_rgh : integer := 24;
18 | constant post_max : integer := 31;
19 | signal postcnt: integer range 0 to post_max := 0;
20 |
21 | begin
22 | process (POSTBIT, RST) is
23 | begin
24 | if POSTBIT'event then
25 | if(RST = '0') then
26 | postcnt <= 0;
27 | else
28 | if(postcnt < post_max) then
29 | postcnt <= postcnt + 1;
30 | end if;
31 | end if;
32 | end if;
33 | end process;
34 |
35 | process (postcnt) is
36 | begin
37 | if postcnt >= post_rgh then
38 | to_count <= '1';
39 | else
40 | to_count <= '0';
41 | end if;
42 |
43 | if postcnt >= post_rgh - 1 and postcnt <= post_rgh + 1 then
44 | to_slow <= '1';
45 | else
46 | to_slow <= '0';
47 | end if;
48 |
49 | if postcnt < post_max then
50 | DBG <= POSTBIT;
51 | else
52 | DBG <= '0';
53 | end if;
54 | end process;
55 | end arch;
56 |
57 |
--------------------------------------------------------------------------------
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/rjtag_phat/post_proc.vhd:
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1 | -- advanced R-JTAG code for x360ace by 15432 ^_^
2 | -- thx to GliGli
3 | library IEEE;
4 | use IEEE.STD_LOGIC_1164.ALL;
5 |
6 | --main module.
7 |
8 | entity post_proc is
9 | Port ( POSTBIT : in STD_LOGIC;
10 | CLK : in STD_LOGIC;
11 | to_slow : out STD_LOGIC := '0';
12 | RST : inout STD_LOGIC := 'Z';
13 | DBG : out STD_LOGIC := '0');
14 | end post_proc;
15 |
16 | architecture arch of post_proc is
17 |
18 | constant R_START: integer := 85352; --jasper: 85352 --falcon 89062 --zephyr 86260
19 | constant T_END: integer := 131071;
20 |
21 | constant R_LEN: integer := 2; --jasper: 2
22 | constant R_FORCE: integer := 10;
23 |
24 | signal cnt : integer range 0 to T_END := 0;
25 |
26 | constant post_max : integer := 20;
27 | signal postcnt: integer range 0 to post_max := 0;
28 | begin
29 | process (POSTBIT) is
30 | begin
31 | if POSTBIT'event then
32 | if(RST = '0') then
33 | postcnt <= 0;
34 | else
35 | if(postcnt < post_max) then
36 | postcnt <= postcnt + 1;
37 | end if;
38 | end if;
39 | end if;
40 | DBG <= POSTBIT; --visual rater? simple!
41 | end process;
42 |
43 | process (clk) is
44 | begin
45 | if CLK'event then --300 mhz precision, yay!
46 | if(postcnt = 15 or (postcnt = 14 and postbit = '1')) then --another magic, post'event is slowpoke
47 | if(cnt < T_END) then
48 | cnt <= cnt + 1;
49 | end if;
50 | else
51 | cnt <= 0;
52 | end if;
53 |
54 | if(cnt >= R_START and cnt < R_START + R_LEN) then
55 | RST <= '0';
56 | else
57 | if(cnt >= R_START + R_LEN and cnt < R_START + R_LEN + R_FORCE) then
58 | RST <= '1';
59 | else
60 | RST <= 'Z';
61 | end if;
62 | end if;
63 | end if;
64 | end process;
65 |
66 | process (postcnt) is
67 | begin
68 | if postcnt = 14 then -- i2c slower. might be 'special'
69 | to_slow <= '1';
70 | else
71 | to_slow <= '0';
72 | end if;
73 | end process;
74 | end arch;
75 |
76 |
--------------------------------------------------------------------------------
/rgh2_phat/slower.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | --stable slowdown by Alibaba
5 | entity slower is
6 | generic (
7 | SDA_SLOW_BITS : STD_LOGIC_VECTOR(0 to 271) := b"10011111111111100000000000000000000111111111111110000000011111111000011111111110000000000000000000011110000000011111100001111000000001111111111110000111111000000000000000011110000000000001111111111000000000000000000000000000011111100000000000000000000000011111111111111001";
8 | SDA_FAST_BITS : STD_LOGIC_VECTOR(0 to 271) := b"10011111111111100000000000000000000111111111111110000000011111111000011111111110000000000000000000011110000000011111100001111000000001111111111110000111111111100000000000000000000000000001111110000000000000000111111110000000011111100000000000000000000000011110000111111001";
9 | SCL_BITS : STD_LOGIC_VECTOR(0 to 271) := b"11001100110011001100110011001100110011000011001100110011001100110011001100110000110011001100110011001100110011001100001100110011001100110011001100110011000011001100110011001100110011001100110000110011001100110011001100110011001100001100110011001100110011001100110011000011"
10 | );
11 | Port ( CLK3 : in STD_LOGIC;
12 | to_slow : in STD_LOGIC;
13 | to_do: in STD_LOGIC;
14 | SCL : out STD_LOGIC := '1';
15 | SDA : out STD_LOGIC := '1');
16 | end slower;
17 |
18 | architecture arch of slower is
19 | signal p_do: STD_LOGIC := '0';
20 | signal i2ccnt: integer range 0 to 271 := 271;
21 | begin
22 |
23 | process(CLK3, i2ccnt) is
24 | begin
25 | if rising_edge(CLK3) then
26 | if i2ccnt /= 271 then
27 | i2ccnt <= i2ccnt + 1;
28 | else
29 | if p_do /= to_do then
30 | p_do <= to_do;
31 | i2ccnt <= 0;
32 | end if;
33 | end if;
34 | end if;
35 |
36 | if ((to_slow = '1') and (SDA_SLOW_BITS(i2ccnt) = '1')) or ((to_slow = '0') and (SDA_FAST_BITS(i2ccnt) = '1')) then
37 | SDA <= 'Z';
38 | else
39 | SDA <= '0';
40 | end if;
41 |
42 | if SCL_BITS(i2ccnt) = '1' then
43 | SCL <= 'Z';
44 | else
45 | SCL <= '0';
46 | end if;
47 |
48 | end process;
49 |
50 | end arch;
51 |
52 |
--------------------------------------------------------------------------------
/rgh2_phat/dualnand.sym:
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/rgh2_phat/dualnand.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 | use IEEE.NUMERIC_STD.ALL;
4 |
5 | --dualnand module
6 |
7 | entity dualnand is
8 | Port ( RST : in STD_LOGIC;
9 | BUT : in STD_LOGIC;
10 | CIN : in STD_LOGIC;
11 | CES : out STD_LOGIC := '1';
12 | CED : out STD_LOGIC := '1';
13 | SMC : out STD_LOGIC := '1';
14 | CLK : in STD_LOGIC;
15 | LED : out STD_LOGIC := '0');
16 | end dualnand;
17 |
18 | architecture arch of dualnand is
19 |
20 | signal counter : integer range 0 to 511 := 0;
21 | signal counter_smc : integer range 0 to 127 := 0;
22 | signal counter_led : unsigned(9 downto 0) := (others => '0');
23 | signal switch : STD_LOGIC := '1';
24 | signal pre_sw : STD_LOGIC := '1';
25 | signal m_CES : STD_LOGIC := '1';
26 | signal m_CED : STD_LOGIC := '0';
27 | begin
28 |
29 | process (m_CES, m_CED) is
30 | begin
31 | if(m_CES = '0') then
32 | CES <= '1';
33 | else
34 | CES <= CIN;
35 | end if;
36 | if(m_CED = '0') then
37 | CED <= '1';
38 | else
39 | CED <= CIN;
40 | end if;
41 | end process;
42 |
43 | process (CLK) is
44 | begin
45 | if rising_edge(CLK) then
46 | pre_sw <= switch;
47 | --button holding processing
48 | if (BUT = '1') then
49 | counter <= 0;
50 | else
51 | if (RST = '0' and counter /= 511 and to_integer(counter_led) = 0) then
52 | counter <= counter + 1;
53 | else
54 | if (RST = '0' and counter = 511) then
55 | counter <= 0;
56 | switch <= not switch;
57 | end if;
58 | end if;
59 | end if;
60 | --blinking processing
61 | if(pre_sw /= switch) then
62 | if(switch = '0') then
63 | m_CED <= '1';
64 | m_CES <= '0';
65 | counter_led <= b"1111111111";
66 | counter_smc <= 127;
67 | else
68 | m_CED <= '0';
69 | m_CES <= '1';
70 | counter_led <= b"0111111111";
71 | counter_smc <= 127;
72 | end if;
73 | end if;
74 | --smc reset to finish the switching
75 | if (counter_smc /= 0) then
76 | counter_smc <= counter_smc - 1;
77 | SMC <= '0';
78 | else
79 | SMC <= '1';
80 | end if;
81 | if (counter_led /= 0) then
82 | counter_led <= counter_led - 1;
83 | end if;
84 |
85 | end if;
86 | LED <= counter_led(8);
87 | end process;
88 |
89 |
90 | end arch;
91 |
92 |
--------------------------------------------------------------------------------
/rgh12_phat/slower.vhd:
--------------------------------------------------------------------------------
1 | -- RGH 1.2 NEW DESIGN
2 | library IEEE;
3 | use IEEE.STD_LOGIC_1164.ALL;
4 |
5 | -- this module do the PLL slowdown
6 | -- also counts the delay
7 | -- VERY complicated module, sorry
8 |
9 | entity slower is
10 | Port ( to_slow : in STD_LOGIC;
11 | timeout : in STD_LOGIC;
12 | to_count : in STD_LOGIC;
13 | clk_50 : in STD_LOGIC ;
14 | PLL : out STD_LOGIC := '0';
15 | callback : out STD_LOGIC := '0');
16 | end slower;
17 |
18 | architecture arch of slower is
19 |
20 | signal delay_val : integer range 0 to 16383 := 0 ;
21 | signal delay_cnt : integer range 0 to 16383 := 0 ;
22 | constant delay_div: integer := 50 ;
23 | signal mode : STD_LOGIC := '0';
24 |
25 | signal m_cbk : STD_LOGIC := '0';
26 | signal m_slo : STD_LOGIC := '0';
27 |
28 | signal clk_1 : STD_LOGIC := '0';
29 | signal divcnt : integer range 0 to 1023 := 0;
30 | begin
31 |
32 |
33 | process (clk_50) is
34 | begin
35 | if rising_edge(clk_50) then
36 | --retail compatibility
37 | if mode = '0' or to_slow = '0' then
38 | m_cbk <= '0';
39 | else
40 | if to_count = '0' and m_slo = '1' then
41 | m_cbk <= '1';
42 | end if;
43 | end if;
44 |
45 | --convert clk to lower frequency
46 | if divcnt < 1023 then
47 | divcnt <= divcnt + 1;
48 | else
49 | divcnt <= 0;
50 | clk_1 <= not clk_1;
51 | end if;
52 | end if;
53 | end process;
54 |
55 | --delay measurement
56 | process (to_slow, to_count, mode) is
57 | begin
58 | if mode = '0' and to_slow = '1' and to_count = '1' then
59 | mode <= '1';
60 | delay_val <= delay_cnt - delay_div;
61 | end if;
62 | end process;
63 |
64 | -- delay count and slowdown control
65 | process (clk_1) is
66 | begin
67 | if rising_edge(clk_1) then
68 | if timeout = '0' and delay_cnt > delay_val then
69 | m_slo <= '1';
70 | else
71 | m_slo <= '0';
72 | end if;
73 |
74 | if to_slow = '0' then
75 | delay_cnt <= 0;
76 | else
77 | if delay_cnt < 16383 then
78 | delay_cnt <= delay_cnt + 1;
79 | end if;
80 | end if;
81 | end if;
82 | end process;
83 |
84 | --output signals
85 | process (m_cbk, m_slo) is
86 | begin
87 | callback <= m_cbk;
88 | if (m_cbk = '1') then
89 | PLL <= m_slo;
90 | else
91 | PLL <= '0';
92 | end if;
93 | end process;
94 |
95 | end arch;
96 |
97 |
--------------------------------------------------------------------------------
/rgh2_phat/post_proc.vhd:
--------------------------------------------------------------------------------
1 | -- advanced RGH2 code for x360ace by 15432 ^_^
2 | -- thx to GliGli
3 | library IEEE;
4 | use IEEE.STD_LOGIC_1164.ALL;
5 |
6 | --main module.
7 |
8 | entity post_proc is
9 | Port ( POSTBIT : in STD_LOGIC;
10 | CLK : in STD_LOGIC;
11 | to_slow : out STD_LOGIC := '0';
12 | to_do : out STD_LOGIC := '0';
13 | RST : inout STD_LOGIC := 'Z';
14 | DBG : out STD_LOGIC := '0');
15 | end post_proc;
16 |
17 | architecture arch of post_proc is
18 |
19 | constant R_LEN : integer := 1; --try to keep it 1, please. bad results? -> change the working frequency!
20 | --alternative cpu reset only. see rjtag schematic
21 |
22 | constant R_END: integer := 27124; --jasper 27124 --falcon 27126 --zephyr 27451/27452
23 | --you can use 300 MHz or 200 MHz, just
24 |
25 | constant T_END: integer := R_END + 2;
26 |
27 | signal cnt : integer range 0 to T_END := 0;
28 |
29 | constant post_rgh : integer := 13; --24 for alt post
30 | constant post_max : integer := post_rgh + 2;
31 |
32 | signal postcnt: integer range 0 to post_rgh + 2 := 0;
33 | begin
34 | process (POSTBIT, RST) is
35 | begin
36 | if POSTBIT'event then
37 | if(RST = '0') then
38 | postcnt <= 0;
39 | else
40 | if(postcnt < post_max) then
41 | postcnt <= postcnt + 1;
42 | end if;
43 | end if;
44 | end if;
45 | --uncomment for alt post
46 | --if(RST = '0') then
47 | --DBG <= '0';
48 | --else
49 | DBG <= POSTBIT; -- not POSTBIT; --for alt post
50 | --end if;
51 | end process;
52 |
53 | process (clk) is
54 | begin
55 | if rising_edge(clk) then --150 MHz
56 | --if CLK'event then --300 MHz / 200 MHz (add 300_to_200 module right before post_proc input)
57 | if(postcnt = post_rgh ) then
58 | if(cnt < T_END) then
59 | cnt <= cnt + 1;
60 | end if;
61 | else
62 | cnt <= 0;
63 | end if;
64 |
65 | if(cnt >= R_END - R_LEN and cnt < R_END) then
66 | RST <= '0';
67 | else
68 | if(cnt = R_END) then --to end the glitch. necessary for phats
69 | RST <= '1';
70 | else
71 | RST <= 'Z';
72 | end if;
73 | end if;
74 | end if;
75 | end process;
76 |
77 | process (postcnt) is
78 | begin
79 | if postcnt = post_rgh - 1 then
80 | to_slow <= '1';
81 | else
82 | to_slow <= '0';
83 | end if;
84 | if(postcnt <= 1 or postcnt = post_rgh - 1) then
85 | to_do <= '1'; --to fix bad falcon behaviour
86 | else
87 | to_do <= '0';
88 | end if;
89 | end process;
90 | end arch;
91 |
92 |
--------------------------------------------------------------------------------
/rjtag_phat/slower.vhd:
--------------------------------------------------------------------------------
1 | library IEEE;
2 | use IEEE.STD_LOGIC_1164.ALL;
3 |
4 | --nothing special. just common i2c slowdown
5 | entity slower is
6 | generic ( -- S >< E0 >< ACK >< CD >< ACK >< 04 >< ACK >< 4E >< ACK >< 08 >< ACK >< 80 >< ACK >< 03 >< ACK >< P
7 | SDA_SLOW_BITS : STD_LOGIC_VECTOR(0 to 255) := b"1001111111110000000000000001111111111111111100000011111100011111111111111000000000000000111000000111111111110001110000001111111110001111111111100000000000011100000000011111111111111000000000000000000000111111111110000000000000000001111111111111111100101111";
8 | SCL_BITS : STD_LOGIC_VECTOR(0 to 255) := b"1100100100100100100100100100001111100001001001001001001001001000011111000010010010010010010010010000111110000100100100100100100100100001111100001001001001001001001001000011111000010010010010010010010010000111110000100100100100100100100100001111100001111111";
9 | -- S >< E0 >< ACK >< CD >< ACK >< 04 >< ACK >< 4E >< ACK >< 80 >< ACK >< 0c >< ACK >< 02 >< ACK >< P
10 | SDA_FAST_BITS : STD_LOGIC_VECTOR(0 to 255) := b"1001111111110000000000000001111111111111111100000011111100011111111111111000000000000000111000000111111111110001110000001111111110001111111111111100000000000000000000011111111111000000000000111111000000111111111110000000000000000001110001111111111100101111"
11 | );
12 | Port ( CLK3 : in STD_LOGIC;
13 | to_slow : in STD_LOGIC;
14 | SCL : out STD_LOGIC := '1';
15 | SDA : out STD_LOGIC := '1');
16 | end slower;
17 |
18 | architecture arch of slower is
19 | signal p_slow: STD_LOGIC := '0';
20 | signal i2ccnt: integer range 0 to 255 := 255;
21 | begin
22 |
23 | process(CLK3) is
24 | begin
25 | if rising_edge(CLK3) then
26 | if i2ccnt /= 255 then
27 | i2ccnt <= i2ccnt + 1;
28 | else
29 | if p_slow /= to_slow then
30 | p_slow <= to_slow;
31 | i2ccnt <= 0;
32 | end if;
33 | end if;
34 | end if;
35 |
36 | if ((p_slow = '1') and (SDA_SLOW_BITS(i2ccnt) = '1')) or ((p_slow = '0') and (SDA_FAST_BITS(i2ccnt) = '1')) then
37 | SDA <= 'Z';
38 | else
39 | SDA <= '0';
40 | end if;
41 |
42 | if SCL_BITS(i2ccnt) = '1' then
43 | SCL <= 'Z';
44 | else
45 | SCL <= '0';
46 | end if;
47 |
48 | end process;
49 |
50 | end arch;
51 |
52 |
--------------------------------------------------------------------------------
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