├── devnotes ├── isteps │ ├── 8_nest_chiplets │ │ ├── .Rhistory │ │ ├── 8_proc_attr_update.md │ │ ├── 2_host_setup_sbe.md │ │ ├── 5_fabric_post_trainadv.md │ │ └── 3_host_cbs_start.md │ ├── 13_dram_training │ │ ├── 05_proc_mcs_skewadjust.md │ │ ├── 01_host_disable_memvolt.md │ │ ├── 07_host_enable_memvolt.md │ │ ├── 03_mem_pll_initf.md │ │ ├── 04_mem_pll_setup.md │ │ └── 02_mem_pll_reset.md │ ├── 14_DRAM_init │ │ └── 4_mss_power_cleanup.md │ ├── 9_EDI_and_obus_init │ │ ├── 3_fabric_pre_trainadv.md │ │ ├── 1_fabric_erepair.md │ │ └── 5_fabric_post_trainadv.md │ ├── 10_activate_PowerBus │ │ └── 12_proc_chiplet_enable_ridi.md │ ├── 6_master_init_discovery │ │ └── 11_host_start_occ_xstop_handler.md │ ├── 11_centaur_init │ │ └── 1_host_prd_hwreconfig.md │ └── 18_establish_system_SMP_and_TOD │ │ └── 12_proc_tod_init.md ├── RAM_addressing.ods ├── scat │ ├── prebuilt-scat │ ├── samples │ │ └── armv6-obmc-linux-gnueabi │ │ │ ├── reported.by │ │ │ └── crosstool.config │ ├── Makefile │ ├── README.md │ └── scat.c ├── poke │ ├── README.md │ ├── mvpd.pk │ └── wof.pk ├── power_control.md ├── scripts │ ├── dump_cme_sram.sh │ ├── awk_program │ ├── awk_program_occ │ ├── rcd_i2c_dump.sh │ ├── dump_occ_sram.sh │ └── dump_seeprom.sh ├── scom_init_plan.md ├── secure_boot_control.md ├── mvpd_generation.md ├── hostboot-attributes.md ├── git-history-research.md ├── hostboot-centaur-init.md ├── device_tree.md ├── tpm_over_lpc.md ├── user_perspective.md ├── pci.md ├── pdfgrep.md ├── hdat.md ├── mvpd_partition_structure.md ├── initial_cpu_state.md ├── hostboot-nest-chiplets.md ├── register_for_SCOM_tests.md ├── isteps_analysis.md ├── tpm_over_i2c.md └── ipmi_sensors.md ├── logs ├── fdt.bin ├── 28.05.2021_talos_ii_device-tree.bin ├── scom_dumps │ ├── istep_20_2_host_load_hdat.log │ ├── istep_10_5_proc_enable_osclite.log │ ├── istep_8_2_host_setup_sbe.log │ ├── istep_10_7_proc_abus_scominit.log │ ├── istep_8_3_host_cbs_start.log │ ├── istep_8_5_host_attnlisten_proc.log │ ├── istep_12_11_host_startprd_dmi.log │ ├── istep_12_12_host_attnlisten_memb.log │ ├── istep_6_6_host_set_ipl_parms.log │ ├── istep_8_6_host_p9_fbc_eff_config.log │ ├── istep_8_8_proc_attr_update.log │ ├── istep_12_5_dmi_erepair.log │ ├── istep_11_10_cen_initf.log │ ├── istep_11_9_cen_arrayinit.log │ ├── istep_11_13_cen_scominits.log │ ├── istep_11_3_cen_pll_initf.log │ ├── istep_11_4_cen_pll_setup.log │ ├── istep_11_12_cen_startclocks.log │ ├── istep_11_8_cen_chiplet_init.log │ ├── istep_12_4_cen_dmi_scominit.log │ ├── istep_11_6_cen_tp_arrayinit.log │ ├── istep_12_13_cen_set_inband_addr.log │ ├── istep_12_9_dmi_post_trainadv.log │ ├── istep_12_10_proc_cen_framelock.log │ ├── istep_21_2_host_verify_hdat.log │ ├── istep_11_11_cen_do_manual_inits.log │ ├── istep_11_2_cen_tp_chiplet_init1.log │ ├── istep_11_5_cen_tp_chiplet_init2.log │ ├── istep_11_7_cen_tp_chiplet_init3.log │ ├── istep_10_14_host_update_redundant_tpm.log │ ├── istep_12_6_dmi_io_dccal.log │ ├── istep_9_6_proc_smp_link_layer.log │ ├── istep_12_7_dmi_pre_trainadv.log │ ├── istep_12_3_proc_dmi_scominit.log │ ├── istep_8_10_proc_xbus_scominit.log │ ├── istep_13_7_host_enable_memvolt.log │ ├── istep_10_8_proc_obus_scominit.log │ ├── istep_14_4_mss_power_cleanup.log │ ├── istep_10_9_proc_npu_scominit.log │ ├── istep_9_4_fabric_io_run_training.log │ ├── istep_12_2_dmi_attr_update.log │ ├── istep_9_2_fabric_io_dccal.log │ ├── istep_12_1_mss_getecid.log │ ├── istep_9_3_fabric_pre_trainadv.log │ ├── istep_9_5_fabric_post_trainadv.log │ ├── istep_10_11_proc_scomoverride_chiplets.log │ ├── istep_12_8_dmi_io_run_training.log │ ├── istep_9_8_host_fbc_eff_config_aggregate.log │ ├── istep_11_1_host_prd_hwreconfig.log │ ├── istep_8_7_host_p9_eff_config_links.log │ ├── istep_13_1_host_disable_memvolt.log │ ├── istep_8_1_host_slave_sbe_config.log │ ├── istep_8_4_proc_check_slave_sbe_seeprom_complete.log │ ├── istep_15_2_proc_set_pba_homer_bar.log │ ├── istep_8_11_proc_xbus_enable_ridi.log │ ├── istep_16_3_host_secure_rng.log │ ├── istep_16_5_host_load_io_ppe.log │ ├── istep_7_5_mss_attr_update.log │ ├── istep_9_1_fabric_erepair.log │ ├── istep_14_7_proc_exit_cache_contained.log │ ├── istep_7_2_mss_volt.log │ ├── istep_13_3_mem_pll_initf.log │ ├── istep_10_13_host_rng_bist.log │ ├── istep_20_1_host_load_payload.log │ ├── istep_18_12_proc_tod_init.log │ ├── istep_10_4_proc_cen_ref_clk_enable.log │ ├── istep_14_2_mss_thermal_init.log │ ├── istep_16_6_host_ipl_complete.log │ ├── istep_14_6_proc_htm_setup.log │ ├── istep_13_4_mem_pll_setup.log │ ├── istep_10_12_proc_chiplet_enable_ridi.log │ ├── istep_8_9_proc_chiplet_fabric_scominit.log │ ├── istep_7_3_mss_freq.log │ ├── istep_13_2_mem_pll_reset.log │ ├── istep_16_1_host_activate_master.log │ └── istep_6_5_host_init_fsi.log ├── tod │ └── description.txt ├── README.md └── pflash.log ├── images ├── cb_bootblock.png ├── cb_menuconfig.png ├── powert_sb_jmp.png ├── mvpd_after_coreboot.png ├── mvpd_after_hostboot.png ├── TPM_connector_schematic.png ├── cb_menuconfig_romstage.png └── ramstage_tests_results.png ├── releases.md └── README.md /devnotes/isteps/8_nest_chiplets/.Rhistory: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /logs/fdt.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/logs/fdt.bin -------------------------------------------------------------------------------- /images/cb_bootblock.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/cb_bootblock.png -------------------------------------------------------------------------------- /images/cb_menuconfig.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/cb_menuconfig.png -------------------------------------------------------------------------------- /images/powert_sb_jmp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/powert_sb_jmp.png -------------------------------------------------------------------------------- /devnotes/RAM_addressing.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/devnotes/RAM_addressing.ods -------------------------------------------------------------------------------- /devnotes/scat/prebuilt-scat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/devnotes/scat/prebuilt-scat -------------------------------------------------------------------------------- /devnotes/scat/samples/armv6-obmc-linux-gnueabi/reported.by: -------------------------------------------------------------------------------- 1 | reporter_name="" 2 | reporter_url="" 3 | reporter_comment="" 4 | -------------------------------------------------------------------------------- /images/mvpd_after_coreboot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/mvpd_after_coreboot.png -------------------------------------------------------------------------------- /images/mvpd_after_hostboot.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/mvpd_after_hostboot.png -------------------------------------------------------------------------------- /images/TPM_connector_schematic.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/TPM_connector_schematic.png -------------------------------------------------------------------------------- /images/cb_menuconfig_romstage.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/cb_menuconfig_romstage.png -------------------------------------------------------------------------------- /images/ramstage_tests_results.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/images/ramstage_tests_results.png -------------------------------------------------------------------------------- /logs/28.05.2021_talos_ii_device-tree.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/logs/28.05.2021_talos_ii_device-tree.bin -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/05_proc_mcs_skewadjust.md: -------------------------------------------------------------------------------- 1 | ## proc_mcs_skewadjust: Update clock mesh deskew (13.5) 2 | 3 | > a) This step is a no-op 4 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_20_2_host_load_hdat.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/3mdeb/openpower-coreboot-docs/HEAD/logs/scom_dumps/istep_20_2_host_load_hdat.log -------------------------------------------------------------------------------- /releases.md: -------------------------------------------------------------------------------- 1 | # This document is a table of content for release documents 2 | * [0.2.0 ramstage](releases/0.2.0.ramstage.md) 3 | * [0.1.0 romstage](releases/0.1.0.romstage.md) 4 | -------------------------------------------------------------------------------- /devnotes/poke/README.md: -------------------------------------------------------------------------------- 1 | This directory provides some data description files for [GNU poke] interactive 2 | binary editor. See comments in them on sample usage. 3 | 4 | [GNU poke]: http://www.jemarch.net/poke 5 | -------------------------------------------------------------------------------- /devnotes/isteps/8_nest_chiplets/8_proc_attr_update.md: -------------------------------------------------------------------------------- 1 | # 8.8 proc_attr_update :Proc ATTR Update 2 | 3 | * Called per processor 4 | * Stub HWP for FW to override attributes programmatically 5 | 6 | ``` 7 | noop 8 | ``` 9 | -------------------------------------------------------------------------------- /devnotes/isteps/14_DRAM_init/4_mss_power_cleanup.md: -------------------------------------------------------------------------------- 1 | ``` 2 | nop 3 | // there is a logic executed for `CONFIG_NVDIMM` but we don't use it 4 | // there is also a logic executed only 5 | // for Cumulus according to the comment in the code 6 | ``` 7 | -------------------------------------------------------------------------------- /logs/tod/description.txt: -------------------------------------------------------------------------------- 1 | bringup_no_tod.txt 2 | contains boot logs without configured TOD and enabled cpu_bringup 3 | tod_bringup.txt 4 | contains boot logs wit configured TOD and enabled cpu_bringup 5 | tod_no_bringup.txt 6 | contains boot logs wit configured TOD and disabled cpu_bringup 7 | -------------------------------------------------------------------------------- /devnotes/isteps/9_EDI_and_obus_init/3_fabric_pre_trainadv.md: -------------------------------------------------------------------------------- 1 | # 9.3 fabric_pre_trainadv: Advanced pre training 2 | ### p9_io_xbus_linktrain.C (called on each OO and X bus target pair) 3 | * Debug routine for IO Characterization 4 | * Nothing in it 5 | ```python 6 | # only debug in here 7 | pass 8 | ``` 9 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_5_proc_enable_osclite.log: -------------------------------------------------------------------------------- 1 | 430.56088|ISTEP 10. 5 - proc_enable_osclite 2 | 430.56601|ERRL|I>Got an error log Msg - Type: 0x00000039 3 | 430.56603|ERRL|I>Flush message received 4 | 430.56605|INITSVC|<>doIstep: step 10, substep 6, task proc_chiplet_scominit 6 | -------------------------------------------------------------------------------- /devnotes/scat/Makefile: -------------------------------------------------------------------------------- 1 | export PATH := $(PWD)/.build/armv6-obmc-linux-gnueabi/buildtools/bin/:$(PATH) 2 | CROSS := armv6-obmc-linux-gnueabi- 3 | 4 | CC := $(CROSS)gcc 5 | STRIP := $(CROSS)strip 6 | CFLAGS := -march=armv6zk -mcpu=arm1176jz-s 7 | 8 | scat: scat.c 9 | $(CC) -o $@ $^ $(CFLAGS) 10 | $(STRIP) -S $@ 11 | 12 | clean: 13 | $(RM) scat 14 | -------------------------------------------------------------------------------- /devnotes/scat/samples/armv6-obmc-linux-gnueabi/crosstool.config: -------------------------------------------------------------------------------- 1 | CT_CONFIG_VERSION="3" 2 | # CT_REMOVE_DOCS is not set 3 | CT_ARCH_ARM=y 4 | CT_ARCH_ARCH="armv6" 5 | CT_ARCH_FLOAT_SW=y 6 | CT_KERNEL_LINUX=y 7 | CT_LINUX_V_4_18=y 8 | # CT_CC_GCC_USE_GRAPHITE is not set 9 | # CT_CC_GCC_USE_LTO is not set 10 | # CT_CC_GCC_SJLJ_EXCEPTIONS is not set 11 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_2_host_setup_sbe.log: -------------------------------------------------------------------------------- 1 | 398.82001|ISTEP 8. 2 - host_setup_sbe 2 | 398.82422|ISTEPS_TRACE|call_host_setup_sbe entry 3 | 398.82492|ISTEPS_TRACE|call_host_setup_sbe exit 4 | 398.82608|ERRL|I>Got an error log Msg - Type: 0x00000039 5 | 398.82610|ERRL|I>Flush message received 6 | 398.82612|INITSVC|<>doIstep: step 8, substep 3, task host_cbs_start 8 | -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/01_host_disable_memvolt.md: -------------------------------------------------------------------------------- 1 | ## host_disable_memvolt: Disable VDDR on Warm Reboots (13.1) 2 | 3 | > a) Power off dram - VDDR and vPP. Must drop VDDR first, then VPP. 4 | > - Turned off here to handle reconfig loop for dimm failure 5 | > - Only really issued if VDDR/VPP is on 6 | 7 | No-op for Nimbus (why IPL list doesn't say so?), enable pins driven by FPGA, not 8 | configurable. 9 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_7_proc_abus_scominit.log: -------------------------------------------------------------------------------- 1 | 430.98053|ISTEP 10. 7 - proc_abus_scominit 2 | 431.00262|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(15 type) returned 0 entries 3 | 431.00450|ERRL|I>Got an error log Msg - Type: 0x00000039 4 | 431.00451|ERRL|I>Flush message received 5 | 431.00453|INITSVC|<>doIstep: step 10, substep 8, task proc_obus_scominit 7 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_3_host_cbs_start.log: -------------------------------------------------------------------------------- 1 | 398.82616|ISTEP 8. 3 - host_cbs_start 2 | 398.83184|ISTEPS_TRACE|call_host_cbs_start entry 3 | 398.83254|ISTEPS_TRACE|call_host_cbs_start exit 4 | 398.83408|ERRL|I>Got an error log Msg - Type: 0x00000039 5 | 398.83410|ERRL|I>Flush message received 6 | 398.83412|INITSVC|<>doIstep: step 8, substep 4, task proc_check_slave_sbe_seeprom_complete 8 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_5_host_attnlisten_proc.log: -------------------------------------------------------------------------------- 1 | 398.91499|ISTEP 8. 5 - host_attnlisten_proc 2 | 398.92622|ISTEPS_TRACE|call_host_attnlisten_proc entry 3 | 398.92624|ISTEPS_TRACE|call_host_attnlisten_proc exit 4 | 398.92961|ERRL|I>Got an error log Msg - Type: 0x00000039 5 | 398.92962|ERRL|I>Flush message received 6 | 398.92964|INITSVC|<>doIstep: step 8, substep 6, task host_p9_fbc_eff_config 8 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_11_host_startprd_dmi.log: -------------------------------------------------------------------------------- 1 | 435.50006|ISTEP 12.11 - host_startprd_dmi 2 | 435.50691|SCOM|doMulticastWorkaround on 00050000 for 50040018 3 | 435.50738|SCOM|doMulticastWorkaround on 00050000 for 50040009 4 | 435.50796|ERRL|I>Got an error log Msg - Type: 0x00000039 5 | 435.50797|ERRL|I>Flush message received 6 | 435.50799|INITSVC|<>doIstep: step 12, substep 12, task host_attnlisten_memb 8 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_12_host_attnlisten_memb.log: -------------------------------------------------------------------------------- 1 | 435.50805|ISTEP 12.12 - host_attnlisten_memb 2 | 435.51510|SCOM|doMulticastWorkaround on 00050000 for 50040018 3 | 435.51558|SCOM|doMulticastWorkaround on 00050000 for 50040009 4 | 435.51617|ERRL|I>Got an error log Msg - Type: 0x00000039 5 | 435.51618|ERRL|I>Flush message received 6 | 435.51619|INITSVC|<>doIstep: step 12, substep 13, task cen_set_inband_addr 8 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_6_6_host_set_ipl_parms.log: -------------------------------------------------------------------------------- 1 | 6.96622|ISTEP 6. 6 - host_set_ipl_parms 2 | 6.97895|ISTEPS_TRACE|host_set_ipl_parms entry 3 | 7.15105|PNOR|>>PnorIpmiDD::_writeFlash(i_addr=0x03CE9000)> 4 | 7.34063|ISTEPS_TRACE|host_set_ipl_parms exit 5 | 7.34144|ERRL|I>Got an error log Msg - Type: 0x00000039 6 | 7.34145|ERRL|I>Flush message received 7 | 7.34147|INITSVC|<>doIstep: step 6, substep 7, task host_discover_targets 9 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_6_host_p9_fbc_eff_config.log: -------------------------------------------------------------------------------- 1 | 398.92969|ISTEP 8. 6 - host_p9_fbc_eff_config 2 | 398.93998|ISTEPS_TRACE|call_host_p9_fbc_eff_config entry 3 | 398.94237|FAPI|p9_fbc_eff_config.C: End 4 | 398.94373|ISTEPS_TRACE|call_host_p9_fbc_eff_config exit 5 | 398.94574|ERRL|I>Got an error log Msg - Type: 0x00000039 6 | 398.94576|ERRL|I>Flush message received 7 | 398.94578|INITSVC|<>doIstep: step 8, substep 7, task host_p9_eff_config_links 9 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_8_proc_attr_update.log: -------------------------------------------------------------------------------- 1 | 399.02898|ISTEP 8. 8 - proc_attr_update 2 | 399.03317|ISTEPS_TRACE|call_proc_attr_update entry 3 | 399.03390|ISTEPS_TRACE|Running p9_attr_update HWP on processor target 00050000 4 | 399.03391|ISTEPS_TRACE|call_proc_attr_update exit 5 | 399.03867|ERRL|I>Got an error log Msg - Type: 0x00000039 6 | 399.03869|ERRL|I>Flush message received 7 | 399.03871|INITSVC|<>doIstep: step 8, substep 9, task proc_chiplet_fabric_scominit 9 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_5_dmi_erepair.log: -------------------------------------------------------------------------------- 1 | 435.32259|ISTEP 12. 5 - dmi_erepair 2 | 435.34296|ISTEPS_TRACE|call_dmi_erepair entry 3 | 435.34522|ISTEPS_TRACE|call_dmi_erepair exit 4 | 435.35621|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.35669|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.35728|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.35729|ERRL|I>Flush message received 8 | 435.35730|INITSVC|<>doIstep: step 12, substep 6, task dmi_io_dccal 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_10_cen_initf.log: -------------------------------------------------------------------------------- 1 | 433.95603|ISTEP 11.10 - cen_initf 2 | 433.96278|ISTEPS_TRACE|call_cen_initf: 0 membufs found 3 | 433.96430|ISTEPS_TRACE|call_cen_initf exit 4 | 433.96693|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.96741|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.96802|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.96803|ERRL|I>Flush message received 8 | 433.96805|INITSVC|<>doIstep: step 11, substep 11, task cen_do_manual_inits 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_9_cen_arrayinit.log: -------------------------------------------------------------------------------- 1 | 433.94507|ISTEP 11. 9 - cen_arrayinit 2 | 433.95197|ISTEPS_TRACE|call_cen_arrayinit: 0 membufs found 3 | 433.95198|ISTEPS_TRACE|call_cen_arrayinit exit 4 | 433.95487|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.95537|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.95595|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.95596|ERRL|I>Flush message received 8 | 433.95598|INITSVC|<>doIstep: step 11, substep 10, task cen_initf 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_13_cen_scominits.log: -------------------------------------------------------------------------------- 1 | 433.99736|ISTEP 11.13 - cen_scominits 2 | 434.00420|ISTEPS_TRACE|call_cen_scominits: 0 membufs found 3 | 434.00421|ISTEPS_TRACE|call_cen_scominits exit 4 | 434.00711|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 434.00762|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 434.00823|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 434.00824|ERRL|I>Flush message received 8 | 434.00826|INITSVC|<>doIstep: step 12, substep 1, task mss_getecid 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_3_cen_pll_initf.log: -------------------------------------------------------------------------------- 1 | 433.82233|ISTEP 11. 3 - cen_pll_initf 2 | 433.82932|ISTEPS_TRACE|call_cen_pll_initf: 0 membufs found 3 | 433.82933|ISTEPS_TRACE|call_cen_pll_initf exit 4 | 433.83217|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.83267|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.83326|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.83327|ERRL|I>Flush message received 8 | 433.83329|INITSVC|<>doIstep: step 11, substep 4, task cen_pll_setup 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_4_cen_pll_setup.log: -------------------------------------------------------------------------------- 1 | 433.83491|ISTEP 11. 4 - cen_pll_setup 2 | 433.85045|ISTEPS_TRACE|call_cen_pll_setup: 0 membufs found 3 | 433.85046|ISTEPS_TRACE|call_cen_pll_setup exit 4 | 433.85320|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.85372|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.85434|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.85435|ERRL|I>Flush message received 8 | 433.85437|INITSVC|<>doIstep: step 11, substep 5, task cen_tp_chiplet_init2 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_12_cen_startclocks.log: -------------------------------------------------------------------------------- 1 | 433.98623|ISTEP 11.12 - cen_startclocks 2 | 433.99320|ISTEPS_TRACE|call_cen_startclocks: 0 membufs found 3 | 433.99321|ISTEPS_TRACE|call_cen_startclocks exit 4 | 433.99618|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.99667|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.99728|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.99729|ERRL|I>Flush message received 8 | 433.99731|INITSVC|<>doIstep: step 11, substep 13, task cen_scominits 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_8_cen_chiplet_init.log: -------------------------------------------------------------------------------- 1 | 433.93145|ISTEP 11. 8 - cen_chiplet_init 2 | 433.94097|ISTEPS_TRACE|call_cen_chiplet_init: 0 membufs found 3 | 433.94098|ISTEPS_TRACE|call_cen_chiplet_init exit 4 | 433.94386|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.94439|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.94499|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.94500|ERRL|I>Flush message received 8 | 433.94502|INITSVC|<>doIstep: step 11, substep 9, task cen_arrayinit 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_4_cen_dmi_scominit.log: -------------------------------------------------------------------------------- 1 | 435.29876|ISTEP 12. 4 - cen_dmi_scominit 2 | 435.30568|ISTEPS_TRACE|call_cen_dmi_scominit: 0 membufs found 3 | 435.31962|ISTEPS_TRACE|call_cen_dmi_scominit exit 4 | 435.32141|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.32190|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.32251|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.32252|ERRL|I>Flush message received 8 | 435.32254|INITSVC|<>doIstep: step 12, substep 5, task dmi_erepair 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_6_cen_tp_arrayinit.log: -------------------------------------------------------------------------------- 1 | 433.88544|ISTEP 11. 6 - cen_tp_arrayinit 2 | 433.89983|ISTEPS_TRACE|call_cen_tp_arrayinit: 0 membufs found 3 | 433.89984|ISTEPS_TRACE|call_cen_tp_arrayinit exit 4 | 433.90434|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.90485|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.90547|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.90548|ERRL|I>Flush message received 8 | 433.90550|INITSVC|<>doIstep: step 11, substep 7, task cen_tp_chiplet_init3 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_13_cen_set_inband_addr.log: -------------------------------------------------------------------------------- 1 | 435.51625|ISTEP 12.13 - cen_set_inband_addr 2 | 435.52688|ISTEPS_TRACE|call_cen_set_inband_addr entry 3 | 435.52689|ISTEPS_TRACE|call_cen_set_inband_addr exit 4 | 435.52971|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.53023|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.53083|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.53084|ERRL|I>Flush message received 8 | 435.53086|INITSVC|<>doIstep: step 13, substep 1, task host_disable_memvolt 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_9_dmi_post_trainadv.log: -------------------------------------------------------------------------------- 1 | 435.46374|ISTEP 12. 9 - dmi_post_trainadv 2 | 435.47806|ISTEPS_TRACE|call_dmi_post_trainadv: 0 DMIs found 3 | 435.47807|ISTEPS_TRACE|call_dmi_post_trainadv exit 4 | 435.48087|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.48140|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.48200|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.48201|ERRL|I>Flush message received 8 | 435.48203|INITSVC|<>doIstep: step 12, substep 10, task proc_cen_framelock 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_10_proc_cen_framelock.log: -------------------------------------------------------------------------------- 1 | 435.48209|ISTEP 12.10 - proc_cen_framelock 2 | 435.49609|ISTEPS_TRACE|call_proc_cen_framelock: 0 DMIs found 3 | 435.49610|ISTEPS_TRACE|call_proc_cen_framelock exit 4 | 435.49888|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.49936|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.49997|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.49998|ERRL|I>Flush message received 8 | 435.50000|INITSVC|<>doIstep: step 12, substep 11, task host_startprd_dmi 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_21_2_host_verify_hdat.log: -------------------------------------------------------------------------------- 1 | 571.41635|ISTEP 21. 2 - host_verify_hdat 2 | 571.39250|IPMI|wd: resetWatchDogTimer 3 | 571.39251|IPMI|rp: queuing sync 18:22 4 | 571.39252|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 571.39257|IPMI|dd: I>write ok 18:22 seq 8c len 0 6 | 571.43651|IPMI|dd: I>read b2h ok 1c:22 seq 8c len 0 cc 0 7 | 571.43767|ERRL|I>Got an error log Msg - Type: 0x00000039 8 | 571.43768|ERRL|I>Flush message received 9 | 571.43770|INITSVC|<>doIstep: step 21, substep 3, task host_start_payload 11 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_11_cen_do_manual_inits.log: -------------------------------------------------------------------------------- 1 | 433.96810|ISTEP 11.11 - cen_do_manual_inits 2 | 433.98203|ISTEPS_TRACE|call_cen_do_manual_inits: 0 membufs found 3 | 433.98204|ISTEPS_TRACE|call_cen_do_manual_inits exit 4 | 433.98502|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.98554|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.98615|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.98616|ERRL|I>Flush message received 8 | 433.98618|INITSVC|<>doIstep: step 11, substep 12, task cen_startclocks 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_2_cen_tp_chiplet_init1.log: -------------------------------------------------------------------------------- 1 | 433.81042|ISTEP 11. 2 - cen_tp_chiplet_init1 2 | 433.81792|ISTEPS_TRACE|call_cen_tp_chiplet_init1: 0 membufs found 3 | 433.81793|ISTEPS_TRACE|call_cen_tp_chiplet_init1 exit 4 | 433.82112|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.82164|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.82224|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.82225|ERRL|I>Flush message received 8 | 433.82227|INITSVC|<>doIstep: step 11, substep 3, task cen_pll_initf 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_5_cen_tp_chiplet_init2.log: -------------------------------------------------------------------------------- 1 | 433.85442|ISTEP 11. 5 - cen_tp_chiplet_init2 2 | 433.87212|ISTEPS_TRACE|call_cen_tp_chiplet_init2: 0 membufs found 3 | 433.87364|ISTEPS_TRACE|call_cen_tp_chiplet_init2 exit 4 | 433.88424|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.88475|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.88536|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.88537|ERRL|I>Flush message received 8 | 433.88539|INITSVC|<>doIstep: step 11, substep 6, task cen_tp_arrayinit 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_7_cen_tp_chiplet_init3.log: -------------------------------------------------------------------------------- 1 | 433.90555|ISTEP 11. 7 - cen_tp_chiplet_init3 2 | 433.91928|ISTEPS_TRACE|call_cen_tp_chiplet_init3: 0 membufs found 3 | 433.92081|ISTEPS_TRACE|call_cen_tp_chiplet_init3 exit 4 | 433.93022|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 433.93073|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 433.93135|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 433.93136|ERRL|I>Flush message received 8 | 433.93138|INITSVC|<>doIstep: step 11, substep 8, task cen_chiplet_init 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_14_host_update_redundant_tpm.log: -------------------------------------------------------------------------------- 1 | 433.46259|ISTEP 10.14 - host_update_redundant_tpm 2 | 433.46944|ISTEPS_TRACE|>>call_host_update_redundant_tpm 3 | 433.46946|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 7 | 433.47839|ERRL|I>Flush message received 8 | 433.47841|INITSVC|<>doIstep: step 11, substep 1, task host_prd_hwreconfig 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_6_dmi_io_dccal.log: -------------------------------------------------------------------------------- 1 | 435.35737|ISTEP 12. 6 - dmi_io_dccal 2 | 435.36337|ISTEPS_TRACE|skipping p9_io_dmi_dccal because not required for current processor model 0x14 3 | 435.36338|ISTEPS_TRACE|call_dmi_io_dccal exit 4 | 435.36713|SCOM|doMulticastWorkaround on 00050000 for 50040018 5 | 435.36762|SCOM|doMulticastWorkaround on 00050000 for 50040009 6 | 435.36823|ERRL|I>Got an error log Msg - Type: 0x00000039 7 | 435.36824|ERRL|I>Flush message received 8 | 435.36825|INITSVC|<>doIstep: step 12, substep 7, task dmi_pre_trainadv 10 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_6_proc_smp_link_layer.log: -------------------------------------------------------------------------------- 1 | 400.66859|ISTEP 9. 6 - proc_smp_link_layer 2 | 400.90233|ISTEPS_TRACE|call_proc_smp_link_layer entry 3 | 400.90304|ISTEPS_TRACE|Running p9_smp_link_layer HWP on processor target 00050000 4 | 400.90606|FAPI|p9_smp_link_layer.C: Start 5 | 400.90608|FAPI|p9_smp_link_layer.C: End 6 | 400.90609|ISTEPS_TRACE|call_proc_smp_link_layer exit 7 | 400.91117|ERRL|I>Got an error log Msg - Type: 0x00000039 8 | 400.91118|ERRL|I>Flush message received 9 | 400.91120|INITSVC|<>doIstep: step 9, substep 7, task proc_fab_iovalid 11 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_7_dmi_pre_trainadv.log: -------------------------------------------------------------------------------- 1 | 435.36831|ISTEP 12. 7 - dmi_pre_trainadv 2 | 435.37431|ISTEPS_TRACE|call_dmi_pre_trainadv entry 3 | 435.37505|ISTEPS_TRACE|call_dmi_pre_trainadv: 0 DMIs found 4 | 435.42249|ISTEPS_TRACE|call_dmi_pre_trainadv exit 5 | 435.42419|SCOM|doMulticastWorkaround on 00050000 for 50040018 6 | 435.42471|SCOM|doMulticastWorkaround on 00050000 for 50040009 7 | 435.42529|ERRL|I>Got an error log Msg - Type: 0x00000039 8 | 435.42530|ERRL|I>Flush message received 9 | 435.42532|INITSVC|<>doIstep: step 12, substep 8, task dmi_io_run_training 11 | -------------------------------------------------------------------------------- /devnotes/power_control.md: -------------------------------------------------------------------------------- 1 | # Talos II power management from BMC console 2 | 3 | ## Power operations 4 | 5 | If you don't need to wait for the end of power operation omit the 6 | `-w` parameter for non-blocking version of the command. 7 | 8 | * To power on the machine use: 9 | ``` 10 | obmcutil -w poweron 11 | ``` 12 | 13 | * To power off the machine use: 14 | ``` 15 | obmcutil -w poweroff 16 | ``` 17 | > Note: It is also possible to use chassisoff version of this command. 18 | 19 | ## Check power and booting status 20 | To check current power status and booting progress use: 21 | ``` 22 | obmcutil status 23 | ``` 24 | 25 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_3_proc_dmi_scominit.log: -------------------------------------------------------------------------------- 1 | 435.27471|ISTEP 12. 3 - proc_dmi_scominit 2 | 435.28149|ISTEPS_TRACE|call_proc_dmi_scominit: 0 DMIs found 3 | 435.29439|MMIO|>>mmioSetup 4 | 435.29513|MMIO|<Got an error log Msg - Type: 0x00000039 9 | 435.29865|ERRL|I>Flush message received 10 | 435.29867|INITSVC|<>doIstep: step 12, substep 4, task cen_dmi_scominit 12 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_10_proc_xbus_scominit.log: -------------------------------------------------------------------------------- 1 | 399.12599|ISTEP 8.10 - proc_xbus_scominit 2 | 399.13028|ISTEPS_TRACE|call_proc_xbus_scominit entry 3 | 399.14426|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 4 | 399.14428|TARG|Get other endpoint target for target HUID 000E0001 5 | 399.14429|TARG|Other endpoint target HUID 000E0004 6 | 399.14431|ISTEPS_TRACE|call_proc_xbus_scominit exit 7 | 399.14871|ERRL|I>Got an error log Msg - Type: 0x00000039 8 | 399.14872|ERRL|I>Flush message received 9 | 399.14874|INITSVC|<>doIstep: step 8, substep 11, task proc_xbus_enable_ridi 11 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_13_7_host_enable_memvolt.log: -------------------------------------------------------------------------------- 1 | 436.46433|ISTEP 13. 7 - host_enable_memvolt 2 | 436.47250|ISTEPS_TRACE|>>call_host_enable_memvolt 3 | 436.48228|HB_VOLT|call_host_enable_vddr no-op because mbox not available or system does not support dynamic voltages 4 | 436.48229|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 8 | 436.48751|ERRL|I>Flush message received 9 | 436.48753|INITSVC|<>doIstep: step 13, substep 8, task mss_scominit 11 | -------------------------------------------------------------------------------- /devnotes/scripts/dump_cme_sram.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # WARNING: SCOM addresses are hardcoded for CME0 of first quad, change if needed 4 | 5 | if [ $# -lt 1 -o $(($1)) -eq 0 ]; then 6 | echo "Usage: $0 OCB_address [size]" 7 | exit 8 | fi 9 | 10 | SIZE=$(($2)) 11 | if [ $SIZE -eq 0 ]; then 12 | SIZE=256 13 | fi 14 | SIZE=$(($SIZE/8)) 15 | 16 | # need to subtract SRAM base 17 | ADDR=`printf "%#x" $((($1 - 0xffff8000) << 32))` 18 | 19 | # enable autoincrementation 20 | pdbg -P pib putscom 0x1001200C 0x8000000000000000 21 | pdbg -P pib putscom 0x1001200D $ADDR 22 | 23 | # read data 24 | while [ $SIZE -ne 0 ]; do 25 | SIZE=$(($SIZE-1)) 26 | pdbg -P pib getscom 0x1001200E 27 | done 28 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_8_proc_obus_scominit.log: -------------------------------------------------------------------------------- 1 | 431.00458|ISTEP 10. 8 - proc_obus_scominit 2 | 431.00934|ISTEPS_TRACE|>>call_proc_obus_scominit entry 3 | 431.00936|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_io_obus_scominit) entry 4 | 431.01011|ISTEPS_TRACE|Target list empty, no targets found. HWP call p9_io_obus_scominit will not be called 5 | 431.01012|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 8 | 431.01643|ERRL|I>Flush message received 9 | 431.01645|INITSVC|<>doIstep: step 10, substep 9, task proc_npu_scominit 11 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_14_4_mss_power_cleanup.log: -------------------------------------------------------------------------------- 1 | 459.75945|ISTEP 14. 4 - mss_power_cleanup 2 | 459.76645|ISTEPS_TRACE|Running mss_power_cleanup HWP on target HUID 00250000 3 | 459.77629|FAPI|p9_mss_power_cleanup.C: Start power_cleanup 4 | 459.77631|FAPI|p9_mss_power_cleanup.C: End power_cleanup 5 | 459.77632|ISTEPS_TRACE|SUCCESS : mss_power_cleanup HWP( ) 6 | 459.78066|SCOM|doMulticastWorkaround on 00050000 for 50040018 7 | 459.78119|SCOM|doMulticastWorkaround on 00050000 for 50040009 8 | 459.78183|ERRL|I>Got an error log Msg - Type: 0x00000039 9 | 459.78184|ERRL|I>Flush message received 10 | 459.78186|INITSVC|<>doIstep: step 14, substep 5, task proc_setup_bars 12 | -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/07_host_enable_memvolt.md: -------------------------------------------------------------------------------- 1 | ## host_enable_memvolt: Enable the VDDR3 Voltage Rail (13.7) 2 | 3 | > a) Bring power to dram rails VDDR and VPP. VPP must be enabled prior to VDDR 4 | > - BMC based systems - this is a no-op 5 | > - Send message to FSP to turn on voltages 6 | > - Message must have accounted for voltage/current tweaking based on number of plugged dimms (Dynamic VID) 7 | > - Pulled from HWPF attributes per voltage rail 8 | > - FSP 9 | > - Trigger voltage ramp to DPSS via I2C 10 | > - Wait for min 200 ms ramp, must be stable 500us after DPSS claims Pgood 11 | > - Wait for ack message from FSP - confirms that voltage is on and ready 12 | -------------------------------------------------------------------------------- /devnotes/scripts/awk_program: -------------------------------------------------------------------------------- 1 | !/^$/ { 2 | c = "grep " substr($0,28,4) " trexhex"; 3 | c | getline x; 4 | close(c); 5 | 6 | trace_type = and( "0x" substr($0,43,1), 3); 7 | #print "Type = " trace_type; 8 | switch (trace_type) { 9 | case 0: 10 | # empty 11 | break; 12 | case 1: 13 | printf (x "\n", "0x" substr($0,32,4)); 14 | break; 15 | case 2: 16 | size = int("0x" substr($0,34,2)); 17 | if (size > 2) { 18 | getline parm_34; 19 | } 20 | getline parm_12; 21 | 22 | printf (x "\n", "0x" substr(parm_12,28,8), "0x" substr(parm_12,36,8), 23 | "0x" substr(parm_34,28,8), "0x" substr(parm_34,36,8)); 24 | break; 25 | default: 26 | print "Unsupported parameter type" 27 | } 28 | } 29 | -------------------------------------------------------------------------------- /logs/README.md: -------------------------------------------------------------------------------- 1 | 2 | # config 3 | This file contains Linux configuration 4 | extracted from /proc/config.gz at skiroot on Talos II 5 | Dumped at 28.06.2021 6 | 7 | # 28.05.2021_talos_ii_device_tree 8 | This file contains device-tree dumped from skiroot 9 | with following HW configuration: 10 | 11 | * Single IBM POWER9 64bit CPU 12 | 13 | * RAM configuration: 14 | MCS0, MCA0 15 | DIMM0: 1Rx4 16GB PC4-2666V-RC2-12-PA0 16 | DIMM1: not installed 17 | MCS0, MCA1 18 | DIMM0: 1Rx8 8GB PC4-2666V-RD1-12 19 | DIMM1: not installed 20 | MCS1, MCA0 21 | DIMM0: 2Rx4 32GB PC4-2666V-RB2-12-MA0 22 | DIMM1: not installed 23 | MCS1, MCA1 24 | DIMM0: 2Rx8 16GB PC4-2666V-RE2-12 25 | DIMM1: not installed 26 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_9_proc_npu_scominit.log: -------------------------------------------------------------------------------- 1 | 431.01649|ISTEP 10. 9 - proc_npu_scominit 2 | 431.02150|ISTEPS_TRACE|>>call_proc_npu_scominit entry 3 | 431.02151|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_npu_scominit) entry 4 | 431.02220|ISTEPS_TRACE|Running p9_npu_scominit HWP on target HUID 00050000 5 | 431.04674|ISTEPS_TRACE|SUCCESS: p9_npu_scominit HWP returned success with target HUID 0x00050000 6 | 431.04675|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 9 | 431.05077|ERRL|I>Flush message received 10 | 431.05079|INITSVC|<>doIstep: step 10, substep 10, task proc_pcie_scominit 12 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_4_fabric_io_run_training.log: -------------------------------------------------------------------------------- 1 | 400.62583|ISTEP 9. 4 - fabric_io_run_training 2 | 400.63091|ISTEPS_TRACE|>>call_fabric_io_run_training entry 3 | 400.63168|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 4 | 400.63169|TARG|Get other endpoint target for target HUID 000E0001 5 | 400.63170|TARG|Other endpoint target HUID 000E0004 6 | 400.63248|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(40 type) returned 0 entries 7 | 400.63250|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 9 | 400.64707|ERRL|I>Flush message received 10 | 400.64709|INITSVC|<>doIstep: step 9, substep 5, task fabric_post_trainadv 12 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_2_dmi_attr_update.log: -------------------------------------------------------------------------------- 1 | 435.23759|ISTEP 12. 2 - dmi_attr_update 2 | 435.24382|IPMI|wd: resetWatchDogTimer 3 | 435.24384|IPMI|rp: queuing sync 18:22 4 | 435.24385|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 435.24390|IPMI|dd: I>write ok 18:22 seq 3b len 0 6 | 435.26888|IPMI|dd: I>read b2h ok 1c:22 seq 3b len 0 cc 0 7 | 435.26969|ISTEPS_TRACE|call_dmi_attr_update: 0 DMIs found 8 | 435.26970|ISTEPS_TRACE|call_dmi_attr_update exit 9 | 435.27353|SCOM|doMulticastWorkaround on 00050000 for 50040018 10 | 435.27402|SCOM|doMulticastWorkaround on 00050000 for 50040009 11 | 435.27461|ERRL|I>Got an error log Msg - Type: 0x00000039 12 | 435.27462|ERRL|I>Flush message received 13 | 435.27464|INITSVC|<>doIstep: step 12, substep 3, task proc_dmi_scominit 15 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_2_fabric_io_dccal.log: -------------------------------------------------------------------------------- 1 | 400.56793|ISTEP 9. 2 - fabric_io_dccal 2 | 400.57562|ISTEPS_TRACE|>>call_fabric_io_dccal entry 3 | 400.57639|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 4 | 400.57640|TARG|Get other endpoint target for target HUID 000E0001 5 | 400.57642|TARG|Other endpoint target HUID 000E0004 6 | 400.57645|ISTEPS_TRACE|Connection bus list is empty. HWP call p9_io_xbus_dccal will not be called. 7 | 400.57722|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(40 type) returned 0 entries 8 | 400.57723|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 10 | 400.59703|ERRL|I>Flush message received 11 | 400.59705|INITSVC|<>doIstep: step 9, substep 3, task fabric_pre_trainadv 13 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_1_mss_getecid.log: -------------------------------------------------------------------------------- 1 | 434.00833|ISTEP 12. 1 - mss_getecid 2 | 434.02158|INITSVC|unloading [libistep11.so] 3 | 434.02173|INITSVC|unloading [libimageprocs.so] 4 | 434.02189|INITSVC|loading [libistep12.so] 5 | 434.23792|INITSVC|loading [libnestmemutils.so] 6 | 434.25377|INITSVC|loading [libisteps_io.so] 7 | 434.26947|INITSVC|loading [libisteps_mss.so] 8 | 435.19434|INITSVC|loading [libexpupd.so] 9 | 435.22310|ISTEPS_TRACE|call_mss_getecid entry 10 | 435.22311|ISTEPS_TRACE|call_mss_getecid exit 11 | 435.23639|SCOM|doMulticastWorkaround on 00050000 for 50040018 12 | 435.23689|SCOM|doMulticastWorkaround on 00050000 for 50040009 13 | 435.23750|ERRL|I>Got an error log Msg - Type: 0x00000039 14 | 435.23751|ERRL|I>Flush message received 15 | 435.23753|INITSVC|<>doIstep: step 12, substep 2, task dmi_attr_update 17 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_3_fabric_pre_trainadv.log: -------------------------------------------------------------------------------- 1 | 400.59710|ISTEP 9. 3 - fabric_pre_trainadv 2 | 400.60875|ISTEPS_TRACE|>>call_fabric_pre_trainadv entry 3 | 400.60955|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 4 | 400.60956|TARG|Get other endpoint target for target HUID 000E0001 5 | 400.60958|TARG|Other endpoint target HUID 000E0004 6 | 400.61417|ISTEPS_TRACE|Connection bus list is empty. HWP call p9_io_xbus_pre_trainadv will not be called. 7 | 400.61494|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(40 type) returned 0 entries 8 | 400.61649|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 10 | 400.62576|ERRL|I>Flush message received 11 | 400.62578|INITSVC|<>doIstep: step 9, substep 4, task fabric_io_run_training 13 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_5_fabric_post_trainadv.log: -------------------------------------------------------------------------------- 1 | 400.64714|ISTEP 9. 5 - fabric_post_trainadv 2 | 400.65836|ISTEPS_TRACE|>>call_fabric_post_trainadv entry 3 | 400.65912|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 4 | 400.65914|TARG|Get other endpoint target for target HUID 000E0001 5 | 400.65915|TARG|Other endpoint target HUID 000E0004 6 | 400.65918|ISTEPS_TRACE|Connection bus list is empty. HWP call p9_io_xbus_post_trainadv will not be called. 7 | 400.65995|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(40 type) returned 0 entries 8 | 400.65997|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 10 | 400.66852|ERRL|I>Flush message received 11 | 400.66854|INITSVC|<>doIstep: step 9, substep 6, task proc_smp_link_layer 13 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_11_proc_scomoverride_chiplets.log: -------------------------------------------------------------------------------- 1 | 433.24687|ISTEP 10.11 - proc_scomoverride_chiplets 2 | 433.26240|IPMI|wd: resetWatchDogTimer 3 | 433.26242|IPMI|rp: queuing sync 18:22 4 | 433.26243|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 433.26248|IPMI|dd: I>write ok 18:22 seq d7 len 0 6 | 433.28406|IPMI|dd: I>read b2h ok 1c:22 seq d7 len 0 cc 0 7 | 433.28411|ISTEPS_TRACE|call_proc_scomoverride_chiplets entry 8 | 433.28481|ISTEPS_TRACE|Running p9_scomoverride_chiplets HWP on processor target 00050000 9 | 433.28633|ISTEPS_TRACE|SUCCESS : proc_scomoverride_chiplets HWP 10 | 433.28635|ISTEPS_TRACE|call_proc_scomoverride_chiplets exit 11 | 433.30245|ERRL|I>Got an error log Msg - Type: 0x00000039 12 | 433.30247|ERRL|I>Flush message received 13 | 433.30249|INITSVC|<>doIstep: step 10, substep 12, task proc_chiplet_enable_ridi 15 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_12_8_dmi_io_run_training.log: -------------------------------------------------------------------------------- 1 | 435.42538|ISTEP 12. 8 - dmi_io_run_training 2 | 435.43931|ISTEPS_TRACE|call_dmi_io_run_training: 1 proc chips found 3 | 435.43933|ISTEPS_TRACE|p9_io_dmi_linktrain HWP target HUID 00050000 4 | 435.44387|FAPI_I|p9_io_dmi_linktrain.C: p9_io_dmi_linktrain: P9 I/O EDI+/EDI DMI Entering 5 | 435.44884|FAPI_I|p9_io_dmi_linktrain.C: p9_io_dmi_linktrain: P9 I/O EDI+/EDI DMI Exiting 6 | 435.45191|ISTEPS_TRACE|SUCCESS : p9_io_dmi_linktrain HWP 7 | 435.45192|ISTEPS_TRACE|call_dmi_io_run_training exit 8 | 435.46257|SCOM|doMulticastWorkaround on 00050000 for 50040018 9 | 435.46307|SCOM|doMulticastWorkaround on 00050000 for 50040009 10 | 435.46366|ERRL|I>Got an error log Msg - Type: 0x00000039 11 | 435.46367|ERRL|I>Flush message received 12 | 435.46369|INITSVC|<>doIstep: step 12, substep 9, task dmi_post_trainadv 14 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_8_host_fbc_eff_config_aggregate.log: -------------------------------------------------------------------------------- 1 | 404.42409|ISTEP 9. 8 - host_fbc_eff_config_aggregate 2 | 404.45094|IPMI|wd: resetWatchDogTimer 3 | 404.45095|IPMI|rp: queuing sync 18:22 4 | 404.45096|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 404.45101|IPMI|dd: I>write ok 18:22 seq 43 len 0 6 | 404.47769|IPMI|dd: I>read b2h ok 1c:22 seq 43 len 0 cc 0 7 | 404.47776|ISTEPS_TRACE|call_host_fbc_eff_config_aggregate entry 8 | 404.49453|FAPI|p9_fbc_smp_utils.C: (PROC): Start 9 | 404.49455|ISTEPS_TRACE|call_host_fbc_eff_config_aggregate exit 10 | 404.50367|SCOM|doMulticastWorkaround on 00050000 for 50040018 11 | 404.50417|SCOM|doMulticastWorkaround on 00050000 for 50040009 12 | 404.50480|ERRL|I>Got an error log Msg - Type: 0x00000039 13 | 404.50481|ERRL|I>Flush message received 14 | 404.50483|INITSVC|<>doIstep: step 10, substep 1, task proc_build_smp 16 | -------------------------------------------------------------------------------- /devnotes/scom_init_plan.md: -------------------------------------------------------------------------------- 1 | # About this document 2 | This document describes plans of implementing SCOM init steps 8.9 and 8.10 3 | 4 | # soc 5 | Here files that are directly responsible for soc 6 | - Add ibm directory 7 | - Add power9 directory 8 | - Add Kconfig specific to POWER9 family 9 | - Add bootblock, and romstage that are responsible for cpu configuration 10 | - Memlayout is already defined in Motherboard section,\ 11 | so it is probably not needed here.\ 12 | Memlayout should be moved to SoC directory 13 | - Add chip.c for cpu structures 14 | - Add Kconfig for all POWER processors 15 | 16 | # Access to scom 17 | According to Christian Geddes, access to SCOM is possible through XSCOM 18 | using offset 0x000603FC00000000\ 19 | [source](https://lists.ozlabs.org/pipermail/openpower-firmware/2020-December/000602.html) 20 | 21 | # Mainboard 22 | - Memory layout 23 | - Bootblock 24 | 25 | # Summary 26 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_11_1_host_prd_hwreconfig.log: -------------------------------------------------------------------------------- 1 | 433.47848|ISTEP 11. 1 - host_prd_hwreconfig 2 | 433.48488|INITSVC|unloading [libistep10.so] 3 | 433.48511|INITSVC|unloading [libisteps_nest.so] 4 | 433.49471|INITSVC|unloading [libisteps_mss.so] 5 | 433.75298|INITSVC|unloading [libsbe.so] 6 | 433.75316|INITSVC|unloading [libnestmemutils.so] 7 | 433.76408|INITSVC|unloading [libimageprocs.so] 8 | 433.76432|INITSVC|loading [libistep11.so] 9 | 433.78297|INITSVC|loading [libimageprocs.so] 10 | 433.80655|ISTEPS_TRACE|>>call_host_prd_hwreconfig 11 | 433.80656|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 15 | 433.81035|ERRL|I>Flush message received 16 | 433.81037|INITSVC|<>doIstep: step 11, substep 2, task cen_tp_chiplet_init1 18 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_7_host_p9_eff_config_links.log: -------------------------------------------------------------------------------- 1 | 398.94585|ISTEP 8. 7 - host_p9_eff_config_links 2 | 398.95019|ISTEPS_TRACE|>>call_host_p9_fbc_eff_config_links entry 3 | 398.97425|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_fbc_eff_config_links) entry 4 | 398.97497|ISTEPS_TRACE|Running p9_fbc_eff_config_links HWP on target HUID 00050000 5 | 398.97966|FAPI|p9_fbc_smp_utils.C: (PROC): Start 6 | 399.01145|TARG|[TARG] >> TARGETING::getPeerTargets 7 | 399.01148|TARG|[TARG] << TARGETING::getPeerTargets 8 | 399.02478|ISTEPS_TRACE|SUCCESS: p9_fbc_eff_config_links HWP returned success with target HUID 0x00050000 9 | 399.02480|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 12 | 399.02891|ERRL|I>Flush message received 13 | 399.02893|INITSVC|<>doIstep: step 8, substep 8, task proc_attr_update 15 | -------------------------------------------------------------------------------- /devnotes/secure_boot_control.md: -------------------------------------------------------------------------------- 1 | # Talos II Secure Boot control 2 | 3 | The `FSI_CP0_CMD` and `FSI_CP1_CMD` are responsible for controlling the secure 4 | boot state. The pin state is probed by SBE at the launch time. High state 5 | (1.1V) disables the Secure Boot while leaving it floating enables it. A simple 6 | electric circuit has been created to remotely control the Secure Boot state. 7 | When Secure Boot is disabled, one may read SCOM registers from BMC level. 8 | 9 | The schematics of the circuit: 10 | 11 | ![](../images/powert_sb_jmp.png) 12 | 13 | > Do not use resistors with high resistance. 10k Ohm resistor were not able to 14 | > pull the voltage up to 1.1V on the FSI_CPX_SMD node. One must use a low 15 | > resistance components to drive the pins with enough current. 16 | 17 | One may simply control the state by driving RTE GPIO411 low or high: 18 | 19 | * `echo 0 > /sys/class/gpio/gpio411/value` - to disable the Secure Boot 20 | * `echo 1 > /sys/class/gpio/gpio411/value` - to enable the Secure Boot 21 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_13_1_host_disable_memvolt.log: -------------------------------------------------------------------------------- 1 | 435.53091|ISTEP 13. 1 - host_disable_memvolt 2 | 435.53759|INITSVC|unloading [libistep12.so] 3 | 435.53781|INITSVC|unloading [libnestmemutils.so] 4 | 435.53795|INITSVC|unloading [libisteps_io.so] 5 | 435.53805|INITSVC|unloading [libisteps_mss.so] 6 | 435.53892|INITSVC|unloading [libexpupd.so] 7 | 435.53902|INITSVC|loading [libistep13.so] 8 | 435.89734|INITSVC|loading [libisteps_mss.so] 9 | 435.90448|INITSVC|loading [libcen.so] 10 | 435.91619|INITSVC|loading [libnestmemutils.so] 11 | 435.93354|ISTEPS_TRACE|>>call_host_disable_memvolt 12 | 435.93356|HB_VOLT|call_host_disable_vddrno-op because mbox not available 13 | 435.93357|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 17 | 435.94420|ERRL|I>Flush message received 18 | 435.94421|INITSVC|<>doIstep: step 13, substep 2, task mem_pll_reset 20 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_1_host_slave_sbe_config.log: -------------------------------------------------------------------------------- 1 | 398.58951|ISTEP 8. 1 - host_slave_sbe_config 2 | 398.60022|INITSVC|unloading [libistep07.so] 3 | 398.61510|INITSVC|unloading [libnestmemutils.so] 4 | 398.61641|INITSVC|unloading [libisteps_mss.so] 5 | 398.71819|INITSVC|unloading [libsbe.so] 6 | 398.73118|INITSVC|unloading [libimageprocs.so] 7 | 398.73479|INITSVC|unloading [libcen.so] 8 | 398.73725|INITSVC|unloading [libnvram.so] 9 | 398.73736|INITSVC|loading [libistep08.so] 10 | 398.75243|INITSVC|loading [libisteps_nest.so] 11 | 398.76824|INITSVC|loading [libsbe.so] 12 | 398.78081|INITSVC|loading [libimageprocs.so] 13 | 398.79780|ISTEPS_TRACE|call_host_slave_sbe_config entry 14 | 398.79781|ISTEPS_TRACE|ATTR_BOOT_FLAGS=00000000 15 | 398.80946|HWAS_I|I>hwas.C: EQ Gard Bit:0x3f EC Gard Bit:0xa6ffffff on proc with HUID: 0x50000 16 | 398.81887|ISTEPS_TRACE|call_host_slave_sbe_config exit 17 | 398.81993|ERRL|I>Got an error log Msg - Type: 0x00000039 18 | 398.81994|ERRL|I>Flush message received 19 | 398.81996|INITSVC|<>doIstep: step 8, substep 2, task host_setup_sbe 21 | -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/03_mem_pll_initf.md: -------------------------------------------------------------------------------- 1 | ## mem_pll_initf: PLL Initfile for MBAs (13.3) 2 | 3 | > a) p9_mem_pll_initf.C (proc chip) 4 | > - This step is a no-op on cumulus 5 | > - This step is a no-op if memory is running in synchronous mode since the MCAs are using the nest PLL, HWP detect 6 | > and exits 7 | > - MCA PLL setup 8 | > - Note that Hostboot doesn't support twiddling bits, Looks up which "bucket" (ring) to use from attributes set 9 | > during mss_freq 10 | > - Then request the SBE to scan ringId with setPulse 11 | > - SBE needs to support 5 RS4 images 12 | > - Data is stored as a ring image in the SBE that is frequency specific 13 | > - 5 different frequencies (1866, 2133, 2400, 2667, EXP) 14 | 15 | ``` 16 | For each functional Proc: 17 | > if ( !ATTR_MC_SYNC_MODE ) 18 | For each functional MCBIST 19 | - fapi2::putRing(mbist, ring_id(depends on RAM freq), RING_MODE_SET_PULSE_NSL) 20 | // FIXME: depending on whether putRing() is used anywhere else, we may implement this as a function or directly 21 | - /src/user/scan/scandd.C:169 sbeScanPerformOp() 22 | ``` 23 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_4_proc_check_slave_sbe_seeprom_complete.log: -------------------------------------------------------------------------------- 1 | 398.83418|ISTEP 8. 4 - proc_check_slave_sbe_seeprom_complete 2 | 398.83869|ISTEPS_TRACE|call_proc_check_slave_sbe_seeprom_complete entry 3 | 398.83937|ISTEPS_TRACE|proc_check_slave_sbe_seeprom_complete: 1 procs in the system. 4 | 398.83939|ISTEPS_TRACE|Master SBE found, HUID 00050000, skipping to look for Slave SBE's. 5 | 398.83941|ISTEPS_TRACE|Running p9_getecid HWP on processor target 00050000 6 | 398.84177|FAPI|p9_getecid.C: Entering ... 7 | 398.88157|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000018000 18E41840A1005180 8 | 398.89484|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000018001 A1044200000068DA 9 | 398.89487|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000018002 0000000000002ED2 10 | 398.89792|FAPI|p9_getecid.C: Exiting ... 11 | 398.89793|ISTEPS_TRACE|SUCCESS : proc_getecid completed ok 12 | 398.89795|ISTEPS_TRACE|call_proc_check_slave_sbe_seeprom_complete exit 13 | 398.91490|ERRL|I>Got an error log Msg - Type: 0x00000039 14 | 398.91491|ERRL|I>Flush message received 15 | 398.91493|INITSVC|<>doIstep: step 8, substep 5, task host_attnlisten_proc 17 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_15_2_proc_set_pba_homer_bar.log: -------------------------------------------------------------------------------- 1 | 472.33472|ISTEP 15. 2 - proc_set_pba_homer_bar 2 | 472.34193|IPMI|wd: resetWatchDogTimer 3 | 472.34194|IPMI|rp: queuing sync 18:22 4 | 472.34195|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 472.34200|IPMI|dd: I>write ok 18:22 seq fb len 0 6 | 472.35956|IPMI|dd: I>read b2h ok 1c:22 seq fb len 0 cc 0 7 | 472.35963|ISTEPS_TRACE|call_proc_set_pba_homer_bar entry 8 | 472.37515|FAPI|p9_pm_set_homer_bar.C: Entering p9_pm_set_homer_bar ... 9 | 472.39691|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005012B00 00000001FD800000 10 | 472.39695|FAPI|p9_pm_pba_bar_config.C: i_pba_bar_size: 0x0000000000000004. Final work_size: 0x0000000000000004 11 | 472.39698|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005012B04 0000000000300000 12 | 472.42036|ISTEPS_TRACE|call_proc_set_pba_homer_bar exit 13 | 472.42229|SCOM|doMulticastWorkaround on 00050000 for 50040018 14 | 472.42282|SCOM|doMulticastWorkaround on 00050000 for 50040009 15 | 472.42347|ERRL|I>Got an error log Msg - Type: 0x00000039 16 | 472.42348|ERRL|I>Flush message received 17 | 472.42350|INITSVC|<>doIstep: step 15, substep 3, task host_establish_ex_chiplet 19 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_11_proc_xbus_enable_ridi.log: -------------------------------------------------------------------------------- 1 | 399.14879|ISTEP 8.11 - proc_xbus_enable_ridi 2 | 399.15322|ISTEPS_TRACE|>>call_proc_xbus_enable_ridi entry 3 | 399.15324|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_xbus_enable_ridi) entry 4 | 399.15393|ISTEPS_TRACE|Running p9_xbus_enable_ridi HWP on target HUID 00050000 5 | 399.16506|FAPI|p9_xbus_enable_ridi.C: Call p9_xbus_enable_ridi_net_ctrl_action_function 6 | 399.16508|FAPI|p9_xbus_enable_ridi.C: Check for chiplet enable 7 | 399.16513|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c6 : 00000000000F0040 A006030100000000 8 | 399.16515|FAPI|p9_xbus_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 9 | 399.16520|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c6 : 00000000000F0042 00001C0000000000 10 | 399.16524|ISTEPS_TRACE|SUCCESS: p9_xbus_enable_ridi HWP returned success with target HUID 0x00050000 11 | 399.16525|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 14 | 399.17621|ERRL|I>Flush message received 15 | 399.17623|INITSVC|<>doIstep: step 8, substep 12, task host_set_voltages 17 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_16_3_host_secure_rng.log: -------------------------------------------------------------------------------- 1 | 480.37443|ISTEP 16. 3 - host_secure_rng 2 | 480.38249|IPMI|wd: resetWatchDogTimer 3 | 480.38250|IPMI|rp: queuing sync 18:22 4 | 480.38251|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 480.38255|IPMI|dd: I>write ok 18:22 seq 18 len 0 6 | 480.39677|IPMI|dd: I>read b2h ok 1c:22 seq 18 len 0 cc 0 7 | 480.39683|ISTEPS_TRACE|call_host_secure_rng entry 8 | 480.43332|FAPI|p9_rng_init_phase2.C: Start 9 | 480.43480|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E0 000040006CF01F41 10 | 480.43639|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E0 000040006CF01F41 11 | 480.43642|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000010005 0808000000000000 12 | 480.43644|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000010005 0848000000000000 13 | 480.43645|FAPI|p9_rng_init_phase2.C: End 14 | 480.43646|ISTEPS_TRACE|call_host_secure_rng exit 15 | 480.41760|SCOM|doMulticastWorkaround on 00050000 for 50040018 16 | 480.41381|SCOM|doMulticastWorkaround on 00050000 for 50040009 17 | 480.41435|ERRL|I>Got an error log Msg - Type: 0x00000039 18 | 480.41436|ERRL|I>Flush message received 19 | 480.41438|INITSVC|<>doIstep: step 16, substep 4, task mss_scrub 21 | -------------------------------------------------------------------------------- /devnotes/isteps/9_EDI_and_obus_init/1_fabric_erepair.md: -------------------------------------------------------------------------------- 1 | # 9.1 fabric_erepair: Restore Fabric Bus eRepair data 2 | ### p9_io_restore_erepair.C(O, X bus target pairs) 3 | 4 | * Restore/preset bad lanes on electrical O and X buses from VPD 5 | (in drawer) 6 | * Applies powerbus repair data from module vpd (#ER keyword in VRML VWML) 7 | * Runtime detected fails that were written to VPD are restored here 8 | * NOOP for Cronus 9 | 10 | ```python 11 | For each lane_to_restore: 12 | if is_rx(lane_to_restore): 13 | # mark lines as disabled 14 | # src/import/chips/p9/procedures/hwp/io/p9_io_xbus_restore_erepair.C:143 15 | if(lane_index < IO_GCR_REG_WIDTH): 16 | EDIP_RX_LANE_BAD_VEC_0_15 |= 0x8000 >> lane_to_restore 17 | else: 18 | EDIP_RX_LANE_BAD_VEC_16_23 |= 0x8000 >> lane_to_restore 19 | 20 | # power down digital and analog recieve lines 21 | # src/import/chips/p9/procedures/hwp/io/p9_io_xbus_pdwn_lanes.C:139 22 | EDIP_RX_LANE_DIG_PDWN[lane_to_restore] = 1 23 | EDIP_RX_LANE_ANA_PDWN[lane_to_restore] = 1 24 | else: 25 | # power down transmit lines 26 | # src/import/chips/p9/procedures/hwp/io/p9_io_xbus_pdwn_lanes.C:209 27 | EDIP_TX_LANE_PDWN[lane_to_restore] = 1 28 | ``` 29 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_16_5_host_load_io_ppe.log: -------------------------------------------------------------------------------- 1 | 481.70067|ISTEP 16. 5 - host_load_io_ppe 2 | 481.70497|ISTEPS_TRACE|host_load_io_ppe entry 3 | 481.72560|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_io_obus_image_build) entry 4 | 481.72561|ISTEPS_TRACE|HCODE addr = 0x0x814c1000 5 | 481.72617|ISTEPS_TRACE|Target list empty, no targets found. HWP call p9_io_obus_image_build will not be called 6 | 481.72618|ISTEPS_TRACE|<>fapiHWPCallWrapper (p9_io_xbus_image_build) entry 8 | 481.72620|ISTEPS_TRACE|HCODE addr = 0x0x814c1000 9 | 481.72670|ISTEPS_TRACE|Running p9_io_xbus_image_build HWP on target HUID 00050000 10 | 481.72672|FAPI_I|p9_io_xbus_image_build.C: Entering p9_io_xbus_image_build. 11 | 481.72673|FAPI_I|p9_io_xbus_image_build.C: Exit p9_io_xbus_image_build. 12 | 481.72675|ISTEPS_TRACE|SUCCESS: p9_io_xbus_image_build HWP returned success with target HUID 0x00050000 13 | 481.72676|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 16 | 481.77334|ERRL|I>Flush message received 17 | 481.77336|INITSVC|<>doIstep: step 16, substep 6, task host_ipl_complete 19 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_7_5_mss_attr_update.log: -------------------------------------------------------------------------------- 1 | 398.42204|ISTEP 7. 5 - mss_attr_update 2 | 398.42620|IPMI|wd: resetWatchDogTimer 3 | 398.42621|IPMI|rp: queuing sync 18:22 4 | 398.42623|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 398.42627|IPMI|dd: I>write ok 18:22 seq f7 len 0 6 | 398.44453|IPMI|dd: I>read b2h ok 1c:22 seq f7 len 0 cc 0 7 | 398.45482|ISTEPS_TRACE|call_mss_attr_update entry 8 | 398.45484|ISTEPS_TRACE|check_proc0_memory_config entry 9 | 398.46964|ISTEPS_TRACE|check_proc0_memory_config: 1 functional dimms behind proc0 00050000 10 | 398.48181|ISTEPS_TRACE|SUCCESS: check_proc0_memory_config 11 | 398.48257|ISTEPS_TRACE|Running p9_mss_attr_update HWP on MCS target HUID 000B0000 12 | 398.49679|FAPI|p9_mss_attr_update.C: pu.mcs:k0:n0:s0:p00:c0 Start p9_mss_attr_update 13 | 398.49686|FAPI|p9_mss_attr_update.C: Start p9_mss_attr_update_lx_mvpd 14 | 398.58250|FAPI|p9_mss_attr_update.C: End p9_mss_attr_update_lx_mvpd 15 | 398.58252|FAPI|p9_mss_attr_update.C: pu.mcs:k0:n0:s0:p00:c0 End p9_mss_attr_update 16 | 398.58253|ISTEPS_TRACE|call_mss_attr_update exit 17 | 398.58941|ERRL|I>Got an error log Msg - Type: 0x00000039 18 | 398.58943|ERRL|I>Flush message received 19 | 398.58945|INITSVC|<>doIstep: step 8, substep 1, task host_slave_sbe_config 21 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_9_1_fabric_erepair.log: -------------------------------------------------------------------------------- 1 | 400.29721|ISTEP 9. 1 - fabric_erepair 2 | 400.30193|IPMI|wd: resetWatchDogTimer 3 | 400.30194|IPMI|rp: queuing sync 18:22 4 | 400.30195|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 400.30200|IPMI|dd: I>write ok 18:22 seq 20 len 0 6 | 400.32367|IPMI|dd: I>read b2h ok 1c:22 seq 20 len 0 cc 0 7 | 400.32369|INITSVC|unloading [libistep08.so] 8 | 400.32395|INITSVC|unloading [libisteps_nest.so] 9 | 400.32413|INITSVC|unloading [libsbe.so] 10 | 400.32429|INITSVC|unloading [libimageprocs.so] 11 | 400.32443|INITSVC|loading [libistep09.so] 12 | 400.33057|INITSVC|loading [libpm.so] 13 | 400.47755|INITSVC|loading [libnestmemutils.so] 14 | 400.50139|INITSVC|loading [libfab_iovalid.so] 15 | 400.50603|INITSVC|loading [libimageprocs.so] 16 | 400.52435|ISTEPS_TRACE|call_fabric_erepair entry 17 | 400.52667|TARG|PbusLinkSvc::collectPbusConnections - getAllChiplets(14 type) returned 1 entries 18 | 400.52668|TARG|Get other endpoint target for target HUID 000E0001 19 | 400.52669|TARG|Other endpoint target HUID 000E0004 20 | 400.52821|ISTEPS_TRACE|call_fabric_erepair exit 21 | 400.56785|ERRL|I>Got an error log Msg - Type: 0x00000039 22 | 400.56786|ERRL|I>Flush message received 23 | 400.56788|INITSVC|<>doIstep: step 9, substep 2, task fabric_io_dccal 25 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_14_7_proc_exit_cache_contained.log: -------------------------------------------------------------------------------- 1 | 460.83634|ISTEP 14. 7 - proc_exit_cache_contained 2 | 460.85399|HWAS_I|I>hwas.C: checkMinimumHardware entry 3 | 460.85400|HWAS_I|I>hwas.C: checkMinimumHardware: i_nodeOrSys 00010000 4 | 460.90161|HWAS_I|I>hwas.C: checkMinimumHardware exit - minimum hardware available 5 | 460.90334|HWAS_I|I>hwas.C: check_for_missing_memory: looking for a proc with grp=0x0 chip=0x0, found 1 procs 6 | 460.90369|HWAS_I|I>hwas.C: check_for_missing_memory: kept PROC_MEM_TO_USE same 0x0 7 | 460.90370|HWAS_I|I>hwas.C: PROC_MEM_TO_USE currentVal=0x0 reComputedVal=0x0 8 | 460.92078|ISTEPS_TRACE|Payload base address is 0x0000000000000000 9 | 460.92216|ISTEPS_TRACE|Memory range : 0-200000000 10 | 460.92217|FAPI|p9_exit_cache_contained.C: Start 11 | 460.92218|FAPI|p9_exit_cache_contained.C: End 12 | 460.92220|ISTEPS_TRACE|SUCCESS : call_proc_exit_cache_contained on all procs 13 | 460.94122|ISTEPS_TRACE|SUCCESS : call_proc_exit_cache_contained - extendVMM 14 | 460.94713|SCOM|doMulticastWorkaround on 00050000 for 50040018 15 | 460.94805|SCOM|doMulticastWorkaround on 00050000 for 50040009 16 | 460.94868|ERRL|I>Got an error log Msg - Type: 0x00000039 17 | 460.94869|ERRL|I>Flush message received 18 | 460.94871|INITSVC|<>doIstep: step 15, substep 1, task host_build_stop_image 20 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_7_2_mss_volt.log: -------------------------------------------------------------------------------- 1 | 395.68572|ISTEP 7. 2 - mss_volt 2 | 395.69008|ISTEPS_TRACE|call_mss_volt entry 3 | 395.70211|ISTEPS_TRACE|set_eff_config_attrs_helper: setting _EFF_CONFIG attributes enter: i_base=0 4 | 395.70215|ISTEPS_TRACE|set_eff_config_attrs_helper: DDR3 _EFF_CONFIG(0, 0): slope=0, intercept=0, max_limit=0 5 | 395.70218|ISTEPS_TRACE|set_eff_config_attrs_helper: DDR4 _EFF_CONFIG(0, 0): slope=0, intercept=0, max_limit=0 6 | 395.70221|ISTEPS_TRACE|set_eff_config_attrs_helper: VPP _EFF_CONFIG(0, 0): slope=0, intercept=0 7 | 395.70224|ISTEPS_TRACE|set_eff_config_attrs_helper: setting _EFF_CONFIG attributes exit 8 | 395.72948|ISTEPS_TRACE|Calling p9_mss_volt on list of 1 MCS targets 9 | 395.74960|FAPI|nimbus_mss_voltage.C: Populating decoder cache for pu.mcs:k0:n0:s0:p00:c0 10 | 395.86992|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 11 | 395.87394|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 12 | 395.94586|FAPI|p9_mss_volt.C: End mss volt 13 | 395.94701|ISTEPS_TRACE|call_mss_volt exit 14 | 395.95037|ERRL|I>Got an error log Msg - Type: 0x00000039 15 | 395.95039|ERRL|I>Flush message received 16 | 395.95041|INITSVC|<>doIstep: step 7, substep 3, task mss_freq 18 | -------------------------------------------------------------------------------- /devnotes/isteps/8_nest_chiplets/2_host_setup_sbe.md: -------------------------------------------------------------------------------- 1 | # 8.2 host_setup_sbe 2 | 3 | ### src/usr/isteps/istep08/call_host_setup_sbe.C 4 | 5 | ```python 6 | for l_cpu_target in l_cpuTargetList: 7 | if l_cpu_target is not l_pMasterProcTarget: 8 | p9_set_fsi_gp_shadow(l_cpu_target) ## described below 9 | ``` 10 | ### src/import/chips/p9/procedures/hwp/perv/p9_set_fsi_gp_shadow.C 11 | 12 | ```python 13 | # PERV_ROOT_CTRLx_COPY is TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.ROOT_CTRLx_COPY 14 | # PERV_PERV_CTRLx_COPY is TP.TPVSB.FSI.W.FSI_MAILBOX.FSXCOMP.FSXLOG.PERV_CTRLx_COPY 15 | def p9_set_fsi_gp_shadow(i_target_chip): 16 | perv_perv_ctrl0_copy = fapi2::getCfamRegister(i_target_chip, PERV_PERV_CTRL0_COPY)) 17 | 18 | # Write the value of FUSED_CORE_MODE into PERV_CTRL0(23) regardless of chip EC the bit is nonfunctional on Nimbus DD1 19 | if fapi2::fapi2::Target().ATTR_FUSED_CORE_MODE 20 | # perv_perv_ctrl0_copy .setBit<23>() 21 | # perv_perv_ctrl0_copy [8] = 1 22 | perv_perv_ctrl0_copy |= (1ULL << (sizeof(perv_perv_ctrl0_copy) * 8 - 1 - 23)) 23 | else 24 | # perv_perv_ctrl0_copy .clearBit<23>() 25 | # perv_perv_ctrl0_copy [8] = 0 26 | perv_perv_ctrl0_copy &= ~(1ULL << (sizeof(perv_perv_ctrl0_copy) * 8 - 1 - 23)) 27 | 28 | putCfamRegister(i_target_chip, PERV_PERV_CTRL0_COPY, perv_perv_ctrl0_copy)) 29 | ``` 30 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_13_3_mem_pll_initf.log: -------------------------------------------------------------------------------- 1 | 436.08292|ISTEP 13. 3 - mem_pll_initf 2 | 436.08896|ISTEPS_TRACE|call_mem_pll_initf entry 3 | 436.08967|ISTEPS_TRACE|Running p9_mem_pll_initf HWP on target HUID 00050000 4 | 436.09953|FAPI|p9_mem_pll_initf.C: Entering ... 5 | 436.12760|SCANDD|>>sbeScanPerformOp(targ=00250000,id=110,mode=00000004) 6 | 436.12766|SBEIO|psudd: Sending Req = 000000000009D301 00000000006E0004 0000000000000000 0000000000000000 to 00050000 7 | 436.13105|INTR|IntrRp::msgHandler() - LSI Interrupt Detected 8 | 436.13108|INTR|IntrRp::msgHandler() lsiIntStatus 0x0004000000000000 9 | 436.13111|INTR|IntrRp::msgHandler() External Interrupt found for pir: 0x0,interrupt type: 13 10 | 436.13133|SBEIO|psudd: SbePsu::msgHandler got MSG_INTR message 11 | 436.13152|INTR|IntrRp::completeInterruptProcessing() Removing pending interrupt for pir: 0x0,interrupt type: 13 12 | 436.13842|SCANDD|<Got an error log Msg - Type: 0x00000039 20 | 436.15227|ERRL|I>Flush message received 21 | 436.15229|INITSVC|<>doIstep: step 13, substep 4, task mem_pll_setup 23 | -------------------------------------------------------------------------------- /devnotes/scat/README.md: -------------------------------------------------------------------------------- 1 | ## cat for obmc-console 2 | 3 | Server of [obmc-console] used by Talos 2 communicates with its client using 4 | Unix socket with abstract address (see `man 7 unix`). BMC doesn't have much 5 | tools installed and it's not clear if there are any for sockets with abstract 6 | addresses, so here's a tiny C program to get the output (socket name is 7 | hard-coded at the moment). 8 | 9 | It's purpose is to collect logs without a tty, so that termination of ssh 10 | connection wouldn't interrupt anything. 11 | 12 | ### Prebuilt binary 13 | 14 | For convenience, binary is provided right here to avoid building toolchain. 15 | 16 | ### Building from sources 17 | 18 | Target system uses armv6 which is not supported by popular prebuilt toolchains 19 | for years, so `crosstool-ng` configuration for building required toolchain is 20 | provided, skip below if you have a suitable one already. 21 | 22 | Prerequisites: 23 | * [crosstool-ng] 24 | * regular build environment with GCC, GNU make and binutils 25 | 26 | Preparation: 27 | ```bash 28 | # build toolchain for armv6 29 | ct-ng armv6-obmc-linux-gnueabi 30 | ct-ng build 31 | ``` 32 | 33 | Build `scat` binary: 34 | ```bash 35 | make 36 | ``` 37 | 38 | With your own toolchain, proceed as usual: 39 | ```bash 40 | CROSS=armv6-linux-gnueabi- make 41 | ``` 42 | 43 | ### Usage 44 | 45 | ``` 46 | $ scp scat root@talos:/tmp 47 | $ ssh root@talos 48 | # /tmp/scat | gzip > /tmp/boot-log & 49 | ``` 50 | 51 | [crosstool-ng]: https://crosstool-ng.github.io/ 52 | [obmc-console]: https://github.com/openbmc/obmc-console 53 | -------------------------------------------------------------------------------- /devnotes/scripts/awk_program_occ: -------------------------------------------------------------------------------- 1 | # Split with 'sed "s/.\{27\}\(.\{8\}\)\(.\{8\}\).*/\1\n\2/"' 2 | # Manual moving may be required around the wrap-around or when size is not 3 | # multiply of 8B. 4 | 5 | !/^$/ { 6 | # Timestamp high 7 | tb = int("0x" $0 "00000000"); 8 | 9 | # Timestamp low 10 | getline; 11 | tb += int("0x" $0); 12 | 13 | # Assume there are no logs at tb = 0, treat it as mark for end of entries 14 | if (tb == 0) exit; 15 | 16 | # u32 TID 17 | getline; 18 | 19 | # u16 len, u16 tag 20 | # Len is size in bytes of args and line number, including implicit entry size "arg" 21 | getline; 22 | len = int("0x" substr($0,0,4)); 23 | 24 | # u32 hash 25 | getline; 26 | c = "grep \"^" $0 "\" trexhex"; 27 | c | getline x; 28 | close(c); 29 | 30 | # u32 line number 31 | getline; 32 | line_num = int("0x" $0); 33 | 34 | # Even with 0 params there is at least entry size 35 | getline parm_0 36 | 37 | if (len >= 4) { 38 | getline parm_1 39 | } 40 | if (len >= 8) { 41 | getline parm_2 42 | } 43 | if (len >= 12) { 44 | getline parm_3 45 | } 46 | if (len >= 16) { 47 | getline parm_4 48 | } 49 | if (len >= 20) { 50 | getline parm_5 51 | } 52 | if (len >= 24) { 53 | getline parm_6 54 | } 55 | if (len >= 28) { 56 | getline parm_7 57 | } 58 | # 5 parameters + one for entry size + two "just in case" 59 | 60 | fmt = "[%16.16x] " substr(x,12) "\n"; 61 | printf (fmt, tb, line_num, "0x" parm_0, "0x" parm_1, 62 | "0x" parm_2, "0x" parm_3, 63 | "0x" parm_4, "0x" parm_5, 64 | "0x" parm_6, "0x" parm_7); 65 | } 66 | -------------------------------------------------------------------------------- /devnotes/mvpd_generation.md: -------------------------------------------------------------------------------- 1 | # MVPD data modification 2 | 3 | ## Test goals 4 | 5 | The main goal of this test is to check if `MVPD` partition is modified 6 | before starting hosboot by e.g. `HBBL` or some other part of software 7 | started by `Hostboot`. 8 | 9 | ## Testing environement 10 | 11 | Original `PNOR` image was aquired by building [op-build](https://github.com/3mdeb/openpower-coreboot-docs/blob/main/devnotes/porting.md#building-openpower-firmware). 12 | 13 | `MVPD` partition was read using `pflash` tool: 14 | ``` 15 | pflash -P MVPD -r 16 | ``` 17 | ## Test results 18 | 19 | The file containing `MVPD` partition after running `coreboot` is available 20 | to download [here](https://cloud.3mdeb.com/index.php/s/jk3cDHwE3M7wdKn). 21 | ![](../images/mvpd_after_coreboot.png) 22 | 23 | The file containing `MVPD` partition after running `Hostboot` is available 24 | to download [here](https://cloud.3mdeb.com/index.php/s/DKrqonZDtF7pftA). 25 | ![](../images/mvpd_after_hostboot.png) 26 | 27 | * After flashing original `PNOR` image, `MVPD` partition 28 | is empty containg only `ECC`. 29 | * After running `Hostboot` on default `PNOR` image, `MVPD` partition 30 | is modified. 31 | * After running `Hostboot` for a second time, `MVPD` is not modified anymore and 32 | equal to image after first `Hostboot` run. 33 | * After running `coreboot` on default `PNOR` image, `MVPD` is not modified 34 | and is still empty. 35 | 36 | ## Conclusion 37 | 38 | When running `coreboot`, `MVPD` is not modified, therefore it must be filled 39 | after starting `Hostboot` by `Hostboot` or some other component 40 | started by `Hostboot`. 41 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_13_host_rng_bist.log: -------------------------------------------------------------------------------- 1 | 433.39779|ISTEP 10.13 - host_rng_bist 2 | 433.41140|ISTEPS_TRACE|call_host_rng_bist entry 3 | 433.41245|ISTEPS_TRACE|Running p9_rng_init_phase1 HWP on processor target 00050000 4 | 433.42275|FAPI|p9_rng_init_phase1.C: Start 5 | 433.42430|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E0 0000000000002000 6 | 433.42433|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E1 0000000000000000 7 | 433.42436|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E2 0000000000000000 8 | 433.42439|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E8 0000000000000000 9 | 433.42442|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E5 0000000000000000 10 | 433.42444|FAPI|p9_rng_init_phase1.C: Configuring Self Test Registers (non P9N DD1) 11 | 433.42447|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E1 4110320320320320 12 | 433.42450|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E2 0400C8033E000000 13 | 433.42454|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E8 F6D60988A0000000 14 | 433.42457|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E5 03D0000000000000 15 | 433.42460|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 00000000020110E0 0000000000002000 16 | 433.42463|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 00000000020110E0 000000006CF01F41 17 | 433.42464|FAPI|p9_rng_init_phase1.C: End 18 | 433.42465|ISTEPS_TRACE|call_host_rng_bist exit 19 | 433.46250|ERRL|I>Got an error log Msg - Type: 0x00000039 20 | 433.46252|ERRL|I>Flush message received 21 | 433.46254|INITSVC|<>doIstep: step 10, substep 14, task host_update_redundant_tpm 23 | -------------------------------------------------------------------------------- /devnotes/hostboot-attributes.md: -------------------------------------------------------------------------------- 1 | Hostboot stores information in a tree made of targets and attributes associated 2 | with them. Below is a short overview. 3 | 4 | # APIs 5 | 6 | * `FAPI_ATTR_*()` macros. 7 | * Methods of `TARGETING::Target` like `getAttr()`, `tryGetAttr()`. 8 | * There might be others. 9 | 10 | # Data sources 11 | 12 | ## Hostboot's code 13 | 14 | There are methods for setting attributes and Hostboot uses them, so potentially 15 | any value can be modified. 16 | 17 | ## talos.xml 18 | 19 | Machine specification like 20 | [talos.xml](https://git.raptorcs.com/git/talos-xml/plain/talos.xml) 21 | contains most of the attributes or at least their default values. 22 | 23 | Mind that defaults can be specified at multiple levels and default closest to 24 | the target in question has the highest priority. 25 | 26 | ## Processed talos.xml 27 | 28 | At some point during the build of Hostboot machine specification is processed by 29 | Perl scripts which reorganize it and fill in values of some attributes (other 30 | things are removed, so resulting content isn't a superset of `talos.xml`). 31 | 32 | Command for generating it: 33 | 34 | ``` 35 | $ cd talos-hostboot/src/usr/targeting/common 36 | $ perl -I. processMrw.pl -x ~/data/talos.xml -o talos-mrw.xml 37 | $ vim talos-mrw.xml 38 | ``` 39 | 40 | Some of the generated attributes: `ATTR_IPMI_SENSORS`. 41 | 42 | ## Attribute-specific get/set methods 43 | 44 | At least `src/include/usr/fapi2/attribute_service.H` contains functions which 45 | are called on use of `FAPI_ATTR_*()` macros for certain attributes. So if you 46 | don't see where attribute's value is set or where its value is used, it might be 47 | generated/consumed by one of those functions. 48 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_20_1_host_load_payload.log: -------------------------------------------------------------------------------- 1 | 483.51010|ISTEP 20. 1 - host_load_payload 2 | 483.51427|INITSVC|unloading [libtod.so] 3 | 483.51434|ISTEPS_TRACE|>> TOD:: TodControls destructor 4 | 483.51435|ISTEPS_TRACE|>> TOD:: TodControls::destroy 5 | 483.51436|ISTEPS_TRACE|>> TOD:: 6 | 483.51437|ISTEPS_TRACE|>> TOD:: TodProc destructor 7 | 483.51437|ISTEPS_TRACE|<< TOD:: TodProc destructor 8 | 483.51438|ISTEPS_TRACE|<< TOD:: 9 | 483.51439|ISTEPS_TRACE|<< TOD:: 10 | 483.51440|ISTEPS_TRACE|>> TOD:: TodControls::destroy 11 | 483.51440|ISTEPS_TRACE|>> TOD:: 12 | 483.51441|ISTEPS_TRACE|>> TOD:: TodProc destructor 13 | 483.51442|ISTEPS_TRACE|<< TOD:: TodProc destructor 14 | 483.51443|ISTEPS_TRACE|<< TOD:: 15 | 483.51443|ISTEPS_TRACE|<< TOD:: 16 | 483.51444|ISTEPS_TRACE|<< TOD:: TodControls destructor 17 | 483.51445|ISTEPS_TRACE|>> TOD:: 18 | 483.51446|ISTEPS_TRACE|>> TOD:: TodControls::destroy 19 | 483.51446|ISTEPS_TRACE|<< TOD:: 20 | 483.51447|ISTEPS_TRACE|>> TOD:: TodControls::destroy 21 | 483.51448|ISTEPS_TRACE|<< TOD:: 22 | 483.51448|ISTEPS_TRACE|<< TOD:: 23 | 483.51457|INITSVC|unloading [libistep18.so] 24 | 483.51470|INITSVC|unloading [libp9_cpuWkup.so] 25 | 483.48205|INITSVC|unloading [libfab_iovalid.so] 26 | 483.51490|INITSVC|loading [libistep20.so] 27 | 483.48521|INITSVC|loading [libxz.so] 28 | 483.54579|INITSVC|loading [libruntime.so] 29 | 483.56019|ISTEPS_TRACE|>>load_pnor_section() 30 | 483.70964|ISTEPS_TRACE|load_pnor_section: is XZ_compressed: 1 31 | 484.05893|ISTEPS_TRACE|load_pnor_section: The PAYLOAD section was decompressed. 32 | 484.05948|ERRL|I>Got an error log Msg - Type: 0x00000039 33 | 484.05949|ERRL|I>Flush message received 34 | 484.05951|INITSVC|<>doIstep: step 20, substep 2, task host_load_hdat 36 | -------------------------------------------------------------------------------- /devnotes/scripts/rcd_i2c_dump.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Script expects I2C register address in $1, see 3.3.3.1 in JESD82-31 for 4 | # mapping between I2C registers and RCD control words. $1 will have its 2 lowest 5 | # bits masked out by RCD, and always 4 consecutive bytes are returned. 6 | 7 | # i2c* tools are mostly usable for EEPROM devices, however RCD is not an EEPROM. 8 | # It can be hacked to work, although it requires much more accesses as we do not 9 | # have enough control, e.g. i2c{s,g}et doesn't support DWord reads so we have to 10 | # use byte reads/writes everywhere. 11 | 12 | # We need to send 32b address even though most of it is ignored. 13 | # 3 - I2C bus number, 0x5a - chip address, next byte - bus command (see 3.3.2) 14 | 15 | i2cset 3 0x5a 0x80 0 -y # 0x80 - begin DWord read sequence, byte by byte 16 | i2cset 3 0x5a 0x00 0 -y 17 | i2cset 3 0x5a 0x00 0 -y 18 | i2cset 3 0x5a 0x40 $1 -y # 0x40 - end 19 | 20 | # 5 bytes are returned: 1 status byte (0x01 expected) followed by 4 register 21 | # values. MSB is sent first. 22 | 23 | STATUS=`i2cget 3 0x5a 0x80 -y` 24 | B3=`i2cget 3 0x5a 0x00 -y` 25 | B2=`i2cget 3 0x5a 0x00 -y` 26 | B1=`i2cget 3 0x5a 0x00 -y` 27 | B0=`i2cget 3 0x5a 0x40 -y` 28 | 29 | echo "Status: $STATUS" 30 | 31 | # Reverse byte order for readability. 32 | echo $B0 $B1 $B2 $B3 33 | 34 | # Below is an example for writing byte value to RCWs. Larger writes should also 35 | # be possible, not tested as changes to other registers may render the platform 36 | # unstable without further DRAM retraining. Use with caution. 37 | # 38 | # i2cset 3 0x5a 0x84 0 -y # 0x.4 - write byte, must be consistent below 39 | # i2cset 3 0x5a 0x04 0 -y 40 | # i2cset 3 0x5a 0x04 0 -y 41 | # i2cset 3 0x5a 0x04 0x0b -y # 0x0b - I2C register holding RC06 and RC07 42 | # i2cset 3 0x5a 0x44 0x0f -y # 0x0f - byte to be written, NOP for both RCWs 43 | -------------------------------------------------------------------------------- /devnotes/scripts/dump_occ_sram.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # Dump and parse SGPE/CME logs: 4 | # - one time preparation (use appropriate file from hcode/output/obj/*/): 5 | # awk -F'\\|\\|' '{printf("%8.8x %s\n", $1, $2)}' trexStringFile > trexhex 6 | # 7 | # - dumping 8 | # ./dump_occ_sram.sh | tac | awk -f awk_program -n | tac 9 | # 10 | # ...except BMC's busybox doesn't have 'tac' and doesn't support 'awk -n', so 11 | # you have to run dump_occ_sram.sh on BMC and the rest on PC. 12 | # 13 | # 14 | # Dump and parse OCC logs: 15 | # - one time preparation: 16 | # awk -F'\\|\\|' '{printf("%8.8x %s:%%d: %s\n", $1, $3, $2)}' occStringFile | \ 17 | # sed "s/%p/%x/g" > trexhex 18 | # 19 | # - dumping 20 | # ./dump_occ_sram.sh 0x1fd8 | \ 21 | # sed "s/.\{27\}\(.\{8\}\)\(.\{8\}\).*/\1\n\2/" | \ 22 | # awk -f awk_program_occ -n 23 | # 24 | # No need for 'tac', OCC's format can be parsed in chronological order. It 25 | # prints timestamps before lines so you can 'cat' all 3 logs together before 26 | # passing it to 'awk' and 'sort' the output. 27 | # Some manual splitting may be required around the wrap-around, especially if 28 | # the entries are not 8B aligned... 29 | 30 | if [ $# -lt 1 -o $(($1)) -eq 0 ]; then 31 | echo "Usage: $0 OCB_address [size]" 32 | exit 33 | fi 34 | 35 | SIZE=$(($2)) 36 | if [ $SIZE -eq 0 ]; then 37 | SIZE=256 38 | fi 39 | SIZE=$(($SIZE/8)) 40 | 41 | ADDR=`printf "%#x" $(($1 << 32))` 42 | 43 | # enable stream mode 44 | pdbg -P pib putscom 0x0006D013 0x0800000000000000 45 | 46 | # disable circular mode = enable linear mode 47 | pdbg -P pib putscom 0x0006D012 0x0400000000000000 48 | 49 | # set OCB address - must be 8B aligned 50 | pdbg -P pib putscom 0x0006D010 $ADDR 51 | 52 | # read data 53 | while [ $SIZE -ne 0 ]; do 54 | SIZE=$(($SIZE-1)) 55 | pdbg -P pib getscom 0x0006D015 56 | done 57 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_18_12_proc_tod_init.log: -------------------------------------------------------------------------------- 1 | 483.25929|ISTEP 18.12 - proc_tod_init 2 | 483.23488|ISTEPS_TRACE|>> TOD:: call_tod_init 3 | 483.23489|ISTEPS_TRACE|>> TOD:: 4 | 483.23490|ISTEPS_TRACE|>> TOD:: isTodRunning 5 | 483.23490|ISTEPS_TRACE|>> TOD:: getConfiguredMdmt 6 | 483.23544|ISTEPS_TRACE|<< TOD:: 7 | 483.23545|ISTEPS_TRACE|<< TOD:: TOD HW State = 0 8 | 483.23545|ISTEPS_TRACE|>> TOD:: 9 | 483.23548|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040030 FFFFFFFFFFFFFFFF 10 | 483.23696|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040013 8000000000000000 11 | 483.26697|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040018 8000000000000000 12 | 483.26699|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040016 8000000000000000 13 | 483.26701|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040021 0000000000003FFC 14 | 483.26704|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040022 8000000000000000 15 | 483.26706|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040015 8000000000000000 16 | 483.26714|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000040024 2800000000000000 17 | 483.26716|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040030 0000000000B00000 18 | 483.26718|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000040030 0000000000000000 19 | 483.26720|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000040032 0000000003F00000 20 | 483.26722|FAPI|p9_tod_init.C: pu:k0:n0:s0:p00 (Depth = 0) 21 | 483.26725|ISTEPS_TRACE|I> TOD:: Successfully completed p9_tod_init. MDMT's HUID is 0x00050000. MDMT Master type : 0x00000001. 22 | 483.26726|ISTEPS_TRACE|<< TOD:: 23 | 483.26727|ISTEPS_TRACE|<< TOD:: 24 | 483.51004|ERRL|I>Got an error log Msg - Type: 0x00000039 25 | 483.51005|ERRL|I>Flush message received 26 | 483.51006|INITSVC|<>doIstep: step 20, substep 1, task host_load_payload 28 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_4_proc_cen_ref_clk_enable.log: -------------------------------------------------------------------------------- 1 | 430.43823|ISTEP 10. 4 - proc_cen_ref_clk_enable 2 | 430.47446|ISTEPS_TRACE|call_proc_cen_ref_clock_enable enter 3 | 430.47447|ISTEPS_TRACE|>>validateSecuritySettings 4 | 430.47448|SECURE|>> traceSecuritySettings(): i_doConsoleTrace=0 5 | 430.47450|SECURE|>> getAllSecurityRegisters: isTargetingLoaded=1 calledByRP=0 6 | 430.47527|SECURE|I> getSecuritySwitch() err_rc:0x0000 huid:0x00050000 reg:0x0000000000000000 7 | 430.47530|SECURE|<< getAllSecurityRegisters(): err rc=0x0, plid=0x0, o_regs.size()=2 8 | 430.47535|SECURE|I> procTgt=0x50000: ProcSecurity::SwitchRegister(0x10005): 0x0000000000000000: SabBit=0, SULBit=0, SDBBit=0, CMFSIBit=0 9 | 430.47539|SECURE|I> procTgt=0x50000: ProcCbsControl::StatusRegister(0x50001): 0x84C0000200000000: SabBit=0, SmdBit=1 10 | 430.47540|SECURE|<< traceSecuritySettings(): err rc=0x0, plid=0x0 11 | 430.47912|FAPI|p9_update_security_ctrl.C: p9_update_security_ctrl : Entering ... 12 | 430.47914|FAPI|p9_update_security_ctrl.C: TPM Deconfig Attribute value : 0x1 13 | 430.53502|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000000010005 0000000000000000 14 | 430.53506|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000000010005 0808000000000000 15 | 430.53508|FAPI|p9_update_security_ctrl.C: p9_update_security_ctrl : Exiting ... 16 | 430.54834|ISTEPS_TRACE|p9_update_security_ctrl successful for proc: 0x50000 tpm: 0x0 17 | 430.54835|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 22 | 430.56081|ERRL|I>Flush message received 23 | 430.56083|INITSVC|<>doIstep: step 10, substep 5, task proc_enable_osclite 25 | -------------------------------------------------------------------------------- /devnotes/scat/scat.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | 10 | #define BUFFER_SIZE 128 11 | 12 | #define SOCKET_NAME "\0obmc-console" 13 | #define SOCKET_NAME_LEN (sizeof(SOCKET_NAME) - 1) 14 | 15 | void signal_noop(int s) 16 | { 17 | } 18 | 19 | int main(int argc, char *argv[]) 20 | { 21 | struct sockaddr_un addr; 22 | int ret; 23 | int sock; 24 | char buffer[BUFFER_SIZE]; 25 | struct sigaction action; 26 | 27 | // Make Ctrl+C cause read() to return EINTR 28 | action.sa_handler = &signal_noop; 29 | sigemptyset(&action.sa_mask); 30 | action.sa_flags = 0; 31 | sigaction(SIGINT, &action, NULL); 32 | 33 | sock = socket(AF_UNIX, SOCK_STREAM, 0); 34 | if (sock == -1) { 35 | perror("socket"); 36 | exit(EXIT_FAILURE); 37 | } 38 | 39 | memset(&addr, 0, sizeof(addr)); 40 | addr.sun_family = AF_UNIX; 41 | memcpy(addr.sun_path, SOCKET_NAME, SOCKET_NAME_LEN); 42 | 43 | ret = connect(sock, 44 | (const struct sockaddr *)&addr, 45 | sizeof(addr) - sizeof(addr.sun_path) + SOCKET_NAME_LEN); 46 | if (ret == -1) { 47 | fprintf(stderr, "Can't connect: %s\n", strerror(errno)); 48 | exit(EXIT_FAILURE); 49 | } 50 | 51 | while (1) { 52 | ret = read(sock, buffer, sizeof(buffer) - 1); 53 | if (ret == 0) 54 | break; 55 | if (ret == -1) { 56 | if (errno == EINTR) { 57 | // Do an async read() to get last portion of data or we won't 58 | // miss anything anyway? 59 | break; 60 | } 61 | 62 | perror("read"); 63 | exit(EXIT_FAILURE); 64 | } 65 | 66 | buffer[ret - 1] = '\0'; 67 | fputs(buffer, stdout); 68 | } 69 | 70 | close(sock); 71 | return EXIT_SUCCESS; 72 | } 73 | -------------------------------------------------------------------------------- /devnotes/isteps/10_activate_PowerBus/12_proc_chiplet_enable_ridi.md: -------------------------------------------------------------------------------- 1 | From "POWER9 IPL flow" document: 2 | 3 | > 10.12 proc_chiplet_enable_ridi : Enable RI/DI chip wide 4 | > a p9_chiplet_enable_ridi.C 5 | > * Drop RI/DI for all chiplets being used (A, O, PCIe, DMI) 6 | > * Any other chip wide RI/DI 7 | 8 | Source files: 9 | 10 | - `src/import/chips/p9/procedures/hwp/perv/p9_chiplet_enable_ridi.C` 11 | - `src/import/chips/p9/procedures/hwp/perv/p9_chiplet_enable_ridi.H` 12 | 13 | Source code: 14 | 15 | ```cpp 16 | /// @brief Drop RI/DI for O, PCIE, MC 17 | /// 18 | /// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target 19 | /// @return FAPI2_RC_SUCCESS if success, else error code. 20 | fapi2::ReturnCode p9_chiplet_enable_ridi(const 21 | fapi2::Target& i_target_chip) 22 | { 23 | for(auto l_target_cplt : i_target_chip.getChildren 24 | (static_cast(fapi2::TARGET_FILTER_ALL_MC | 25 | fapi2::TARGET_FILTER_ALL_PCI | 26 | fapi2::TARGET_FILTER_ALL_OBUS), 27 | fapi2::TARGET_STATE_FUNCTIONAL)) 28 | { 29 | p9_chiplet_enable_ridi_net_ctrl_action_function(l_target_cplt); 30 | } 31 | } 32 | 33 | /// @brief Enable Drivers/Recievers of O, PCIE, MC chiplets 34 | /// 35 | /// @param[in] i_target_chiplet Reference to TARGET_TYPE_PERV target 36 | /// @return FAPI2_RC_SUCCESS if success, else error code. 37 | static fapi2::ReturnCode p9_chiplet_enable_ridi_net_ctrl_action_function( 38 | const fapi2::Target& i_target_chiplet) 39 | { 40 | bool l_read_reg = false; 41 | fapi2::buffer l_data64; 42 | 43 | // Check for chiplet enable 44 | // Getting NET_CTRL0 register value 45 | fapi2::getScom(i_target_chiplet, PERV_NET_CTRL0, l_data64); 46 | l_read_reg = l_data64.getBit<0>(); //l_read_reg = NET_CTRL0.CHIPLET_ENABLE 47 | 48 | if ( l_read_reg ) 49 | { 50 | // Enable Recievers, Drivers DI1 & DI2 51 | // Setting NET_CTRL0 register value 52 | l_data64.flush<0>(); 53 | l_data64.setBit<19>(); //NET_CTRL0.RI_N = 1 54 | l_data64.setBit<20>(); //NET_CTRL0.DI1_N = 1 55 | l_data64.setBit<21>(); //NET_CTRL0.DI2_N = 1 56 | fapi2::putScom(i_target_chiplet, PERV_NET_CTRL0_WOR, l_data64); 57 | } 58 | } 59 | ``` 60 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_14_2_mss_thermal_init.log: -------------------------------------------------------------------------------- 1 | 458.09534|ISTEP 14. 2 - mss_thermal_init 2 | 458.10155|IPMI|wd: resetWatchDogTimer 3 | 458.10156|IPMI|rp: queuing sync 18:22 4 | 458.10158|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 458.10163|IPMI|dd: I>write ok 18:22 seq 40 len 0 6 | 458.11636|IPMI|dd: I>read b2h ok 1c:22 seq 40 len 0 cc 0 7 | 458.11643|ISTEPS_TRACE|call_mss_thermal_init entry 8 | 458.11721|ISTEPS_TRACE|Running p9_mss_thermal_init HWP on target HUID 000B0000 9 | 458.13218|FAPI|p9_mss_thermal_init.C: Start thermal_init 10 | 458.16048|SCAN|TRACE : GETSCOM : pu.mca:k0:n0:s0:p00:c1 : 0000000007010916 0100010010002000 11 | 458.16053|SCAN|TRACE : PUTSCOM : pu.mca:k0:n0:s0:p00:c1 : 0000000007010916 0040004010002000 12 | 458.16058|SCAN|TRACE : GETSCOM : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010811 00C0481800000000 13 | 458.16062|SCAN|TRACE : PUTSCOM : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010811 00C0481800000000 14 | 458.16064|FAPI|p9_mss_thermal_init.C: End thermal_init 15 | 458.16066|ISTEPS_TRACE|SUCCESS : p9_mss_thermal_init HWP() on 0x000B0000 MCS 16 | 458.16135|ISTEPS_TRACE|Running p9_throttle_sync HWP on target HUID 00050000 17 | 458.18371|FAPI|0 18 | 458.18371|FAPI|00 19 | 458.18373|FAPI|501081118000000001800000000 20 | 458.19839|SCAN|TRACE : PUTSCOMMASK : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010811 0000001800000000 0000001800000000 21 | 458.20792|SCAN|TRACE : PUTSCOMMASK : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010815 0000000000000000 0000800000000000 22 | 458.20793|FAPI|5010815FFFF800000000000FFFD800000000000 23 | 458.20800|SCAN|TRACE : PUTSCOMMASK : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010815 FFFD800000000000 FFFF800000000000 24 | 458.20801|FAPI|5010815800000000000000 25 | 458.20808|SCAN|TRACE : PUTSCOMMASK : pu.mcs:k0:n0:s0:p00:c0 : 0000000005010815 0000000000000000 0080000000000000 26 | 458.20811|ISTEPS_TRACE|SUCCESS : p9_throttle_sync HWP on 0x00050000 processor 27 | 458.20812|ISTEPS_TRACE|call_mss_thermal_init exit 28 | 458.32460|SCOM|doMulticastWorkaround on 00050000 for 50040018 29 | 458.32515|SCOM|doMulticastWorkaround on 00050000 for 50040009 30 | 458.32579|ERRL|I>Got an error log Msg - Type: 0x00000039 31 | 458.32580|ERRL|I>Flush message received 32 | 458.32582|INITSVC|<>doIstep: step 14, substep 3, task proc_pcie_config 34 | -------------------------------------------------------------------------------- /devnotes/git-history-research.md: -------------------------------------------------------------------------------- 1 | # hostboot git history lookup 2 | 3 | ## init file compiler 4 | 5 | * source code from 2011: 6 | 7 | https://github.com/open-power/hostboot/blob/0f6e334655d2eb7026e9f992a1b32b6d37915563/src/build/ifcompiler/makefile#L6 8 | 9 | * `ifcompiler/initCompiler.C` history: 10 | 11 | ``` 12 | git lola -- src/build/ifcompiler/initCompiler.C 13 | * 11c80c5abcf2 HWPF: Only support initfile attributes in fapiGetInitFileAttr() 14 | * 0f6e334655d2 SCOM Initfile - Updates based on design doc review with hardware team. 15 | * d034089348a1 Initial SCOM initfile compiler support. 16 | ``` 17 | 18 | * it was later moved to `src/usr/hwpf/ifcompiler/initCompiler.C` 19 | 20 | * the history of `src/usr/hwpf/ifcompiler/initCompiler.C` 21 | 22 | ``` 23 | git lola -- src/usr/hwpf/ifcompiler/initCompiler.C 24 | * 76f1c48130a0 Removing some more old fapi1 and hwp code 25 | * 1ae25b625d12 SW265478: INITPROC: FSP - FAPI updates needed so file versions will appear in th 26 | * ce5d000adc77 Fix uninitialized value in initfile compiler 27 | * aa0446e9d1c2 Change copyright prolog for all files to Apache. 28 | * 5151c0b22f5d SCOM Initfile: Improve error and debug tracing in the initfile compiler error/debug paths. 29 | * 4a47221cbf1a Right justify SCOM data 30 | * 11c80c5abcf2 HWPF: Only support initfile attributes in fapiGetInitFileAttr() 31 | ``` 32 | 33 | * the `initCompiler.C` was completey removed in the 34 | `76f1c48130a060fbe83c851fce2474c17b2df9b2` commit 35 | 36 | * it means that the most recent version is available in the 37 | `3967f43b9478d7e6b58180dd0b331e61412997cd` commit 38 | 39 | * it cannot be compiled because of the missing header 40 | 41 | ``` 42 | CXX initCompiler.C 43 | In file included from ifcompiler/initCompiler.H:47, 44 | from ifcompiler/initCompiler.C:52: 45 | ifcompiler/initRpn.H:55:10: fatal error: fapiHwpInitFileInclude.H: No such file or directory 46 | 55 | #include 47 | | ^~~~~~~~~~~~~~~~~~~~~~~~~~ 48 | compilation terminated. 49 | make[1]: *** [makefile:351: ../../../obj/genfiles/hwp_ifcompiler/initCompiler.host.o] Error 1 50 | make: *** [../../../src/build/mkrules/passes.rules.mk:105: _BUILD/PASSES/GEN/BODY] Error 2 51 | ``` 52 | 53 | * The mentioned header was removed in `4b4772ef8b18f2e9c80795c47b3a5f81b3521c1f` 54 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_16_6_host_ipl_complete.log: -------------------------------------------------------------------------------- 1 | 481.77343|ISTEP 16. 6 - host_ipl_complete 2 | 481.76788|PNOR|>>PnorIpmiDD::_writeFlash(i_addr=0x03CE9000)> 3 | 482.06869|HWAS_I|I>deconfigGard.C: Clear GARD Records by type eb 4 | 482.07020|HWAS_I|I>hwasPlatDeconfigGard.C: Get all GARD Records 5 | 482.08596|HWAS_I|I>hwasPlatDeconfigGard.C: Get returning 0 GARD Records 6 | 482.10599|IPMI|HbVolatileSensor::setHbVolatile(2) 7 | 482.11715|IPMI|We were not able to find a sensor number in the IPMI_SENSORS attribute for sensor_name=0xc21 for target with huid=0x0, skipping call to sendSetSensorReading() 8 | 482.11718|ERRL|E>Error created : PLID=9000000B, RC=250D, Mod=03, Userdata=00000000000000FF 00000C2100000000, Sev=UNRECOVERABLE 9 | 482.11720|ERRL|>>addProcedureCallout(0x55, 0x6) 10 | 482.11723|ISTEPS_TRACE|Failure in notifying BMC to clear hostboot volatile section, RC=250D 11 | 482.13958|UTILTCE|I>utilUseTcesForDmas: FALSE 12 | 482.13960|ISTEPS_TRACE|Initialize the runtime data attributes for HDAT consumption 13 | 482.13961|ISTEPS_TRACE|number of HB Reserved mem sections = 60 14 | 482.13962|ISTEPS_TRACE|number of HBRT sections = 2 15 | 482.15284|ISTEPS_TRACE|Running p9_switch_rec_attn HWP on target HUID 00050000 16 | 482.15286|ISTEPS_TRACE|SUCCESS: p9_switch_rec_attn HWP( ) on target HUID 00050000 17 | 482.15758|TARG|>>AttrRP::_syncAllAttributesToFsp 18 | 482.15760|TARG|>>AttrRP::_sendAttrSyncMsg: i_msgType = 0x00000004, i_sync = 1. 19 | 482.15761|TARG|I>AttrRP: attrSyncTask: Received message of type = 0x00000004. 20 | 482.15762|TARG|I>AttrRP: attrSyncTask: Invoking attribute sync. 21 | 482.15764|TARG|I>_invokeAttrSync: FSP services not available; suppressing attribute sync. 22 | 482.15765|TARG|<Send SYNC_POINT_REACHED msg to Fsp 25 | 482.15768|INITSVC|>>IStepDispatcher::sendSyncPoint 26 | 482.15769|INITSVC|I>sendSyncPoint: Istep mode or no base services, returning 27 | 482.15770|INITSVC|<Got an error log Msg - Type: 0x00000039 30 | 482.17311|ERRL|I>Flush message received 31 | 482.17313|INITSVC|<>doIstep: step 18, substep 11, task proc_tod_setup 33 | -------------------------------------------------------------------------------- /devnotes/hostboot-centaur-init.md: -------------------------------------------------------------------------------- 1 | # Step 11Hostboot Centaur Init 2 | ## 11.1 host_prd_hwreconfig: Hook to handle HW reconfig 3 | 4 | * This step is always called 5 | * Move all Centaurs inband scom back to FSI scom 6 | * Call PRD to allow them to rebuild model to remove non-functional Centaurs 7 | * Protect Centaur from SP operations during initialization 8 | ** Set the CFP Security bit. This will prevent the SP from performing FSI operations to the Centaur while it is being initialized 9 | * Used for HW reconfig path. FWs strategy is to perform the reconfig on ALL functional Centaurs/MCSs in the system. 10 | * The following procedures must be called: 11 | 12 | ### bp9_switch_cfsim.C(proc target) 13 | * Call on all present processors 14 | * Move all Centaur’s inband scom back to FSI scom 15 | 16 | ### p9_enable_reconfig.C (MCS, DMI, MCA/MBuf) 17 | 18 | ### Call on all presentMCStargets 19 | * Enables HW for reconfig loop 20 | * Cumulus/Centaur: 21 | ** Attribute (ATTR_CEN_MSS_INIT_STATE) to each Centaur to track where the Reconfig loop got to 22 | ** Clocks on (can do fir masking) –set after step 11 23 | ** DMI bus up (inject special bit) –set after 24 | *** Turns on special bit that allows the MCS DMI to get errors and not get into a hang condition 25 | *** Mask a bunch of FIRson processor 26 | *** Mask a bunch FIRs on centaur (HWP will check clock state) 27 | *** Injects a fail on the DMI bus (only if DMI bus is alive) 28 | *** Clears IO/MCS FIRs Turns off special bit 29 | * Nimbus 30 | ** Raise the MCU chiplet fences 31 | ** Stop clocks 32 | ** Scan 0 flush the MCU chiplet each and everytime through this loop 33 | ** How do we cleanup the nest portion of the MCS? 34 | 35 | ```cpp 36 | if defined(CONFIG_SECUREBOOT) and not defined(CONFIG_AXONE): 37 | // Send message to secure provider to load the section 38 | msg_q_t spnorQ = msg_q_resolve(SPNORRP_MSG_Q); 39 | msg = malloc(sizeof(msg_t)); 40 | memset(msg, 0, sizeof(msg_t)); 41 | // Load the MEMD section here as the first part of step11, it 42 | // will stay loaded until the end of step14 43 | // 44 | // PNOR::MSG_LOAD_SECTION = 0x02 45 | msg->type = PNOR::MSG_LOAD_SECTION; 46 | msg->data[0] = static_cast(PNOR::MEMD); 47 | // MSG_SENDRECV = 10 48 | syscall(MSG_SENDRECV, spnorQ, msg, NULL) 49 | free(msg); 50 | ``` 51 | -------------------------------------------------------------------------------- /devnotes/isteps/6_master_init_discovery/11_host_start_occ_xstop_handler.md: -------------------------------------------------------------------------------- 1 | ### OCC starting 2 | 3 | * 4 | OCC is started from `SRAM` using 5 | ```cpp 6 | HBOCC::startOCCFromSRAM(masterproc); 7 | ``` 8 | * 9 | Before starting `OCC`, the image is loaded to SRAM by 10 | ```cpp 11 | HBPM::loadPMComplex( 12 | masterproc, 13 | l_homerPhysAddrBase, 14 | l_commonPhysAddr, 15 | HBPM::PM_LOAD, 16 | true); 17 | ``` 18 | * 19 | OCC starting is executed conditionally 20 | if `CONFIG_IPLTIME_CHECKSTOP_ANALYSIS` config is defined. 21 | 22 | This may indicate, that Hostboot can boot blatform correctly 23 | without starting `OCC`. 24 | 25 | * 26 | Before starting `OCC`, checkstop's are configured, 27 | but only if `CONFIG_HANG_ON_MFG_SRC_TERM` config is not defined. 28 | 29 | This may mean, that `OCC` can be started after merely loading 30 | an image to `SRAM`. 31 | 32 | * 33 | According to comment, `loadPMComplex` function repeats in 34 | `istep 21.1` 35 | ``` 36 | //If i_useSRAM is true, then we're in istep 6.11. This address needs 37 | //to be reset here, so that it's recalculated again in istep 21.1 38 | //where this function is called. 39 | ``` 40 | 41 | * 42 | `OCC` data is loaded into `HOMER` structure 43 | ``` 44 | l_errl = loadOCCImageToHomer(i_target, 45 | l_occImgPaddr, 46 | l_occImgVaddr, 47 | i_mode); 48 | ``` 49 | 50 | * 51 | Logic in this part of `Hostboot` doesn't look to be complicated and twisted 52 | as much as usually. 53 | 54 | Not every function is short and simple but the code tries 55 | to keep some logic. 56 | 57 | * 58 | One function with cryptic name was found `makeStart405Instruction()` 59 | 60 | It might be the one responsible for calculating instruction 61 | for starting OCC judging by comment 62 | ```cpp 63 | // ************************************************************ 64 | // Start OCC PPC405 65 | // ************************************************************ 66 | l_errl = makeStart405Instruction(i_proc, &l_start405MainInstr); 67 | ``` 68 | 69 | * 70 | Some `SCOM` access is done using `DeviceWrite()` 71 | what can be confusing a bit during analysis. 72 | -------------------------------------------------------------------------------- /devnotes/isteps/11_centaur_init/1_host_prd_hwreconfig.md: -------------------------------------------------------------------------------- 1 | # Step 11Hostboot Centaur Init 2 | ## 11.1 host_prd_hwreconfig: Hook to handle HW reconfig 3 | 4 | * This step is always called 5 | * Move all Centaur's inband scom back to FSI scom 6 | * Call PRD to allow them to rebuild model to remove non-functional Centaurs 7 | * Protect Centaur from SP operations during initialization 8 | ** Set the CFP Security bit. This will prevent the SP from performing FSI operations to the Centaur while it is being initialized 9 | * Used for HW reconfig path. FW's strategy is to perform the reconfig on ALL functional Centaurs/MCS's in the system. 10 | * The following procedures must be called: 11 | 12 | ### bp9_switch_cfsim.C(proc target) 13 | * Call on all present processors 14 | * Move all Centaur’s inband scom back to FSI scom 15 | 16 | ### p9_enable_reconfig.C (MCS, DMI, MCA/MBuf) 17 | 18 | ### Call on all presentMCStargets 19 | * Enables HW for reconfig loop 20 | * Cumulus/Centaur: 21 | ** Attribute (ATTR_CEN_MSS_INIT_STATE) to each Centaur to track where the Reconfig loop got to 22 | ** Clocks on (can do fir masking) –set after step 11 23 | ** DMI bus up (inject special bit) –set after 24 | *** Turn's on special bit that allows the MCS DMI to get errors and not get into a hang condition 25 | *** Mask a bunch of FIRson processor 26 | *** Mask a bunch FIRs on centaur (HWP will check clock state) 27 | *** Injects a fail on the DMI bus (only if DMI bus is alive) 28 | *** Clears IO/MCS FIRs•Turns off special bit 29 | * Nimbus 30 | ** Raise the MCU chiplet fences 31 | ** Stop clocks 32 | ** Scan 0 flush the MCU chiplet each and everytime through this loop 33 | ** How do we cleanup the nest portion of the MCS? 34 | 35 | ``` 36 | if defined(CONFIG_SECUREBOOT) and not defined(CONFIG_AXONE): 37 | // Send message to secure provider to load the section 38 | msg_q_t spnorQ = msg_q_resolve(SPNORRP_MSG_Q); 39 | msg = malloc(sizeof(msg_t)); 40 | memset(msg, 0, sizeof(msg_t)); 41 | // Load the MEMD section here as the first part of step11, it 42 | // will stay loaded until the end of step14 43 | // 44 | // PNOR::MSG_LOAD_SECTION = 0x02 45 | msg->type = PNOR::MSG_LOAD_SECTION; 46 | msg->data[0] = static_cast(PNOR::MEMD); 47 | // MSG_SENDRECV = 10 48 | syscall(MSG_SENDRECV, spnorQ, msg, NULL) 49 | free(msg); 50 | ``` 51 | -------------------------------------------------------------------------------- /devnotes/isteps/9_EDI_and_obus_init/5_fabric_post_trainadv.md: -------------------------------------------------------------------------------- 1 | # 9.5 fabric_post_trainadv: Advanced post EI/EDI training 2 | ### p9_io_post_trainadv.C(called on each O and X bus target pair) 3 | * Debug routine for IO Characterization 4 | * Nothing in it 5 | 6 | ``` 7 | for each bus: 8 | if typeof(bus) == TYPE_OBUS: 9 | if fapi2::ATTR_MNFG_FLAGS & fapi2::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS != 0: 10 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C:63 11 | # Setup ECC & CRC Masks 12 | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OR = 13 | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE 14 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE 15 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS 16 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS 17 | 18 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C 19 | # Setup Performance Counters 20 | OBUS_LL0_IOOL_PERF_SEL_CONFIG = 21 | 0x1B | (0x14 << 8) | (0x1B << 16) | (0x14 << 24) 22 | 23 | # Setup Performance Counters 24 | OBUS_LL0_IOOL_PERF_TRACE_CONFIG = 25 | 0x02 26 | | (0x02 << 2) 27 | | (0x01 << 8) 28 | | (0x01 << 10) 29 | | (0x01 << 16) 30 | | (0x01 << 18) 31 | | (0x01 << 24) 32 | | (0x01 << 26) 33 | 34 | # Setup Performance Counters 35 | # Make it so there are only 10 or 5 ECC errors allowed per lane or 10 or 5 CRC errors allowed 36 | # per link (reliability test) --- Have a flag to go between 3.5/3.7 settings 37 | # Ex. putscom pu 0901080F 0F000F00000000000 -bor -pall 38 | # Ex. putscom pu 0901080F FF8AFF8AFFFFFFFF -band -pall 39 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C:116 40 | OBUS_LL0_IOOL_OPTICAL_CONFIG |= (0xF << 4) | (0xF << 20) 41 | 42 | OBUS_LL0_IOOL_OPTICAL_CONFIG |= (0x7F << 9) | (0x7F << 25) 43 | if fapi2::ATTR_IO_O_MNFG_ERROR_THRESHOLD == fapi2::ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_CORNER_MODE: 44 | OBUS_LL0_IOOL_OPTICAL_CONFIG &= (5 << 9) | (5 << 25) 45 | elif fapi2::ATTR_IO_O_MNFG_ERROR_THRESHOLD == ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_RELIABILITY_MODE: 46 | OBUS_LL0_IOOL_OPTICAL_CONFIG &= (10 << 9) | (10 << 25) 47 | ``` 48 | -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/04_mem_pll_setup.md: -------------------------------------------------------------------------------- 1 | ## mem_pll_setup: Setup PLL for MBAs (13.4) 2 | 3 | > a) p9_mem_pll_setup.C (proc chip) 4 | > - This step is a no-op on cumulus 5 | > - This step is a no-op if memory is running in synchronous mode since the MCAs are using the nest PLL, HWP detect 6 | > and exits 7 | > - MCA PLL setup 8 | > - Moved PLL out of bypass (just DDR) 9 | > - Performs PLL checking 10 | 11 | ``` 12 | For each functional Proc: 13 | > if ( !ATTR_MC_SYNC_MODE ) 14 | For each functional MC(BIST?): 15 | // Drop PLDY bypass of Progdelay logic 16 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL1 (WAND) // 0x070F0045 17 | [all] 1 18 | [2] CLK_PDLY_BYPASS_EN = 0 19 | 20 | // Drop DCC bypass of DCC logic 21 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL1 (WAND) // 0x070F0045 22 | [all] 1 23 | [1] CLK_DCC_BYPASS_EN = 0 24 | 25 | // Attribute description: "Skip the locking sequence and check for lock of NEST/MEM/XBUS/OBUS/PCI PLLs". 26 | // Can't find where it is set, assuming 0. 27 | > if (ATTR_NEST_MEM_X_O_PCI_BYPASS == 0) 28 | // Drop PLL test enable 29 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WAND) // 0x070F0041 30 | [all] 1 31 | [3] PLL_TEST_EN = 0 32 | 33 | // Drop PLL reset 34 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WAND) // 0x070F0041 35 | [all] 1 36 | [4] PLL_RESET = 0 37 | 38 | delay(5ms) 39 | 40 | // Check PLL lock 41 | TP.TPCHIP.NET.PCBSLMC01.PLL_LOCK_REG // 0x070F0019 42 | assert([0] (reserved) == 1) 43 | 44 | // Drop PLL Bypass 45 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WAND) // 0x070F0041 46 | [all] 1 47 | [5] PLL_BYPASS = 0 48 | 49 | // Set scan ratio to 4:1 50 | TP.TCMC01.MCSLOW.OPCG_ALIGN // 0x07030001 51 | [47-51] SCAN_RATIO = 3 // 4:1 52 | 53 | > end if 54 | 55 | // Reset PCB Slave error register 56 | TP.TPCHIP.NET.PCBSLMC01.ERROR_REG // 0x070F001F 57 | [all] 1 // Write 1 to clear 58 | 59 | // Unmask PLL unlock error in PCB slave 60 | TP.TPCHIP.NET.PCBSLMC01.SLAVE_CONFIG_REG // 0x070F001E 61 | [12] (part of) ERROR_MASK = 0 62 | ``` 63 | -------------------------------------------------------------------------------- /devnotes/isteps/8_nest_chiplets/5_fabric_post_trainadv.md: -------------------------------------------------------------------------------- 1 | # 9.5 fabric_post_trainadv: Advanced post EI/EDI training 2 | 3 | ### p9_io_post_trainadv.C(called on each O and X bus target pair) 4 | * Debug routine for IO Characterization 5 | * Nothing in it 6 | 7 | ``` cpp 8 | for each bus: 9 | if typeof(bus) == TYPE_OBUS: 10 | if fapi2::ATTR_MNFG_FLAGS & fapi2::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS != 0: 11 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C:63 12 | # Setup ECC & CRC Masks 13 | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_OR = 14 | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_SL_ECC_CORRECTABLE 15 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_SL_ECC_CORRECTABLE 16 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK0_TOO_MANY_CRC_ERRORS 17 | | OBUS_LL0_LL0_LL0_PB_IOOL_FIR_MASK_REG_LINK1_TOO_MANY_CRC_ERRORS 18 | 19 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C 20 | # Setup Performance Counters 21 | OBUS_LL0_IOOL_PERF_SEL_CONFIG = 22 | 0x1B | (0x14 << 8) | (0x1B << 16) | (0x14 << 24) 23 | 24 | # Setup Performance Counters 25 | OBUS_LL0_IOOL_PERF_TRACE_CONFIG = 26 | 0x02 27 | | (0x02 << 2) 28 | | (0x01 << 8) 29 | | (0x01 << 10) 30 | | (0x01 << 16) 31 | | (0x01 << 18) 32 | | (0x01 << 24) 33 | | (0x01 << 26) 34 | 35 | # Setup Performance Counters 36 | # Make it so there are only 10 or 5 ECC errors allowed per lane or 10 or 5 CRC errors allowed 37 | # per link (reliability test) --- Have a flag to go between 3.5/3.7 settings 38 | # Ex. putscom pu 0901080F 0F000F00000000000 -bor -pall 39 | # Ex. putscom pu 0901080F FF8AFF8AFFFFFFFF -band -pall 40 | # src/import/chips/p9/procedures/hwp/io/p9_io_obus_post_trainadv.C:116 41 | OBUS_LL0_IOOL_OPTICAL_CONFIG |= (0xF << 4) | (0xF << 20) 42 | 43 | OBUS_LL0_IOOL_OPTICAL_CONFIG |= (0x7F << 9) | (0x7F << 25) 44 | if fapi2::ATTR_IO_O_MNFG_ERROR_THRESHOLD == fapi2::ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_CORNER_MODE: 45 | OBUS_LL0_IOOL_OPTICAL_CONFIG &= (5 << 9) | (5 << 25) 46 | elif fapi2::ATTR_IO_O_MNFG_ERROR_THRESHOLD == ENUM_ATTR_IO_O_MNFG_ERROR_THRESHOLD_RELIABILITY_MODE: 47 | OBUS_LL0_IOOL_OPTICAL_CONFIG &= (10 << 9) | (10 << 25) 48 | ``` 49 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_14_6_proc_htm_setup.log: -------------------------------------------------------------------------------- 1 | 460.52877|ISTEP 14. 6 - proc_htm_setup 2 | 460.53475|IPMI|wd: resetWatchDogTimer 3 | 460.53476|IPMI|rp: queuing sync 18:22 4 | 460.53478|IPMI|rp: W>Got message (0x18:0x22): l_is_pnor: 0 5 | 460.53483|IPMI|dd: I>write ok 18:22 seq 54 len 0 6 | 460.55038|IPMI|dd: I>read b2h ok 1c:22 seq 54 len 0 cc 0 7 | 460.55045|ISTEPS_TRACE|call_proc_htm_setup entry 8 | 460.55263|FAPI|p9_htm_setup.C: Entering p9_htm_setup 9 | 460.57968|FAPI|p9_htm_setup.C: Target pu:k0:n0:s0:p00: HTM setup attributes 10 | 460.57969|FAPI|p9_htm_setup.C: NHTM type: 0 11 | 460.57970|FAPI|p9_htm_setup.C: CHTM type: Core[0] 0 12 | 460.57971|FAPI|p9_htm_setup.C: CHTM type: Core[1] 0 13 | 460.57973|FAPI|p9_htm_setup.C: CHTM type: Core[2] 0 14 | 460.57974|FAPI|p9_htm_setup.C: CHTM type: Core[3] 0 15 | 460.57975|FAPI|p9_htm_setup.C: CHTM type: Core[4] 0 16 | 460.57976|FAPI|p9_htm_setup.C: CHTM type: Core[5] 0 17 | 460.57978|FAPI|p9_htm_setup.C: CHTM type: Core[6] 0 18 | 460.57979|FAPI|p9_htm_setup.C: CHTM type: Core[7] 0 19 | 460.57980|FAPI|p9_htm_setup.C: CHTM type: Core[8] 0 20 | 460.57981|FAPI|p9_htm_setup.C: CHTM type: Core[9] 0 21 | 460.57982|FAPI|p9_htm_setup.C: CHTM type: Core[10] 0 22 | 460.57984|FAPI|p9_htm_setup.C: CHTM type: Core[11] 0 23 | 460.57985|FAPI|p9_htm_setup.C: CHTM type: Core[12] 0 24 | 460.57986|FAPI|p9_htm_setup.C: CHTM type: Core[13] 0 25 | 460.57987|FAPI|p9_htm_setup.C: CHTM type: Core[14] 0 26 | 460.57988|FAPI|p9_htm_setup.C: CHTM type: Core[15] 0 27 | 460.57989|FAPI|p9_htm_setup.C: CHTM type: Core[16] 0 28 | 460.57990|FAPI|p9_htm_setup.C: CHTM type: Core[17] 0 29 | 460.57992|FAPI|p9_htm_setup.C: CHTM type: Core[18] 0 30 | 460.57993|FAPI|p9_htm_setup.C: CHTM type: Core[19] 0 31 | 460.57994|FAPI|p9_htm_setup.C: CHTM type: Core[20] 0 32 | 460.57995|FAPI|p9_htm_setup.C: CHTM type: Core[21] 0 33 | 460.57996|FAPI|p9_htm_setup.C: CHTM type: Core[22] 0 34 | 460.57997|FAPI|p9_htm_setup.C: CHTM type: Core[23] 0 35 | 460.61197|ISTEPS_TRACE|call_proc_htm_setup exit 36 | 460.83502|SCOM|doMulticastWorkaround on 00050000 for 50040018 37 | 460.83558|SCOM|doMulticastWorkaround on 00050000 for 50040009 38 | 460.83623|ERRL|I>Got an error log Msg - Type: 0x00000039 39 | 460.83624|ERRL|I>Flush message received 40 | 460.83626|INITSVC|<>doIstep: step 14, substep 7, task proc_exit_cache_contained 42 | -------------------------------------------------------------------------------- /devnotes/device_tree.md: -------------------------------------------------------------------------------- 1 | ## Naming conventions 2 | 3 | - DT 4 | 5 | Device Tree. 6 | 7 | - FDT 8 | 9 | Flat Device Tree. 10 | 11 | ## Dump from skiboot 12 | 13 | Hostboot prepares HDAT for `skiboot`, which turns it into a DT that we want to 14 | dump here. The idea is to make `skiboot` build FDT, print out its location 15 | and size and then dump it from memory using `pdbg` while `skiboot` is halted. 16 | 17 | ### Patching skiboot 18 | 19 | Find `skiboot` sources in your locally built [talos-op-build](https://scm.raptorcs.com/scm/git/talos-op-build). 20 | It lies in `output/build/skiboot-*/`. Apply the following patch to the sources: 21 | 22 | ```diff 23 | core/init.c | 7 +++++++ 24 | 1 file changed, 7 insertions(+) 25 | 26 | diff --git a/core/init.c b/core/init.c 27 | index 0fe6c168..9da8c3b6 100644 28 | --- a/core/init.c 29 | +++ b/core/init.c 30 | @@ -1015,8 +1015,15 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) 31 | if (parse_hdat(true) < 0) 32 | abort(); 33 | } else if (fdt == NULL) { 34 | + void *tmp_fdt; 35 | + 36 | if (parse_hdat(false) < 0) 37 | abort(); 38 | + 39 | + tmp_fdt = create_dtb(dt_root, false); 40 | + printf("FDT is located at 0x%8p, its size is 0x%08x\n", 41 | + tmp_fdt, fdt_totalsize(tmp_fdt)); 42 | + abort(); 43 | } else { 44 | dt_expand(fdt); 45 | } 46 | ``` 47 | 48 | ### Updating skiboot 49 | 50 | Rebuild flash image: 51 | 52 | ```bash 53 | export KERNEL_BITS=64 54 | . op-build-env 55 | op-build -j7 skiboot-rebuild openpower-pnor-rebuild 56 | ``` 57 | 58 | Possibly extract just the `PAYLOAD` section and update only it (its size is 1 59 | MiB): 60 | ``` 61 | fcp file:output/images/talos.pnor:PAYLOAD - -o 0 -R > PAYLOAD 62 | ``` 63 | 64 | ### Obtaining the dump 65 | 66 | Update flash image, start the machine and wait for it to hang in this state: 67 | 68 | ``` 69 | [ 36.253046600,5] FDT is located at 0x30423a00, it's size is 0x0001728f 70 | [ 36.253141301,0] Aborting! 71 | CPU 0010 Backtrace: 72 | S: 0000000031c83d10 R: 0000000030013840 .backtrace+0x48 73 | S: 0000000031c83db0 R: 000000003001b2c4 ._abort+0x4c 74 | S: 0000000031c83e30 R: 0000000030014c84 .main_cpu_entry+0x13c 75 | S: 0000000031c83f00 R: 0000000030002730 boot_entry+0x1c0 76 | ``` 77 | 78 | Finally, dump DT in binary format (update address and size in the command!): 79 | 80 | ``` 81 | ssh root@talos pdbg -p0 -c1 -t0 getmem 0x30423a00 0x0001728f > hb-skiboot.dtb 82 | # convert to text 83 | dtc -I dtb -O dts < hb-skiboot.dtb > hb-skiboot.dts 84 | ``` 85 | -------------------------------------------------------------------------------- /devnotes/tpm_over_lpc.md: -------------------------------------------------------------------------------- 1 | # TPM connection over LPC interface 2 | 3 | At this point in time, using TPM module over LPC interface was unsuccessful. 4 | 5 | ## TPM support in Hostboot 6 | 7 | Hostboot mentions in one of the comments in code, that two families of 8 | TPM from Nuvoton vendor are supported. 9 | 10 | ``` 11 | Hostboot code only supports Nuvoton 65x and 75x Models at this time 12 | ``` 13 | 14 | This support was not verified yet. 15 | 16 | ## Talos II TPM Connector 17 | 18 | Talos II TPM connector has `LPC`and `I2C` connections.\ 19 | The description is available in the [user guide](https://wiki.raptorcs.com/w/images/e/e3/T2P9D01_users_guide_version_1_0.pdf). 20 | ![](../images/TPM_connector_schematic.png) 21 | 22 | ## TPM over LPC interface 23 | 24 | `OPTIGA™ TPM SLB 9665TT2.0 TPM2.0` was tested over an LPC interface. 25 | 26 | To test the chip, original Hostboot image with [Heads](https://github.com/3mdeb/openpower-coreboot-docs/blob/main/releases/0.3.0.heads.md) 27 | as a payload was flashed into the system. 28 | 29 | Talos II properly booted, however no TPM module was detected by Heads. 30 | 31 | ``` 32 | $ dmesg | grep -i tpm 33 | [ 4.552516] ima: No TPM chip found, activating TPM-bypass! 34 | ``` 35 | 36 | ### START nibble 37 | 38 | The LPC TPM uses the same cycles as I/O cycles which we implement e.g. for 39 | serial port. The only difference is the START nibble. There may exist a register 40 | thast allows to alter a START nibble that is sent on each LPC cycle. 41 | 42 | > TODO: Check if this type of register exists. 43 | 44 | ## Supported TPM connections 45 | 46 | TPM connection is hardware-supperted via LPC and I2C interface. 47 | [Source](https://wiki.raptorcs.com/wiki/User:HLandau/Block_Diagram_Discussion#Minor_CPU_Interfaces) 48 | 49 | * CPU0 LPC [to FlexVer] to BMC, LPC TPM 50 | 51 | ``` 52 | The LPC interface of CPU0 is connected to the BMC. The BMC serves the PNOR flash chip connected to it to CPU0, and CPU0 loads boot firmware from it. A TPM connector is also provided on the board which exposes this bus, and allows a standard TPM to be attached to it. 53 | 54 | A FlexVer module, if fitted, can intermediate this bus and proxy all communications between the CPU and other devices on the LPC bus. This switching is done automatically via analogue components on the mainboard when a FlexVer device is connected. 55 | ``` 56 | * BMC I2C TO I2C TPM 57 | ``` 58 | Runs to the TPM connector. Allows connection of a TPM via I2C instead of LPC. In this case, the connection is via the BMC. 59 | ``` 60 | -------------------------------------------------------------------------------- /devnotes/user_perspective.md: -------------------------------------------------------------------------------- 1 | ## Boot statistics 2 | 3 | ### Hostboot first boot 4 | 5 | - 6 | reboots: 2 7 | - 8 | total boot time to skiboot: more than 148s 9 | - 10 | Testet revision: `raptor-v2.00` 11 | - 12 | Repository: [https://scm.raptorcs.com/scm/git/talos-op-build](https://scm.raptorcs.com/scm/git/talos-op-build) 13 | 14 | [![asciicast](https://asciinema.org/a/vcNPPv4dR6OtWqW52NjzggvQS.svg)](https://asciinema.org/a/vcNPPv4dR6OtWqW52NjzggvQS) 15 | 16 | This boot path is executed only the first time Hostboot is running. 17 | 18 | ### Hostboot normal boot 19 | 20 | - 21 | reboots: 0 22 | - 23 | boot time to skiboot: 44s 24 | - 25 | Testet revision: `raptor-v2.00` 26 | - 27 | Repository: [https://scm.raptorcs.com/scm/git/talos-op-build](https://scm.raptorcs.com/scm/git/talos-op-build) 28 | 29 | [![asciicast](https://asciinema.org/a/mLuoffJDK3Z1hqIUkMAF9Y3Jf.svg)](https://asciinema.org/a/mLuoffJDK3Z1hqIUkMAF9Y3Jf) 30 | 31 | This boot path is executed at every boot except the first one. 32 | Changing system configuration (like the amount of RAM) would probably 33 | make it longer, but not as long as the first boot. 34 | 35 | ### coreboot first and normal boot 36 | 37 | - 38 | reboots: 0 39 | - 40 | boot time to skiboot: 24s 41 | - 42 | Tested revision: `ce64c091228ed8878263263fd7fe700e64557148` 43 | - 44 | Repository: [https://github.com/3mdeb/coreboot](https://github.com/3mdeb/coreboot) 45 | 46 | [![asciicast](https://asciinema.org/a/lqMvLFEPfjR14Eqq8Z5Wwlm77.svg)](https://asciinema.org/a/lqMvLFEPfjR14Eqq8Z5Wwlm77) 47 | 48 | - 49 | reboots: 0 50 | - 51 | boot time to skiboot: 10s 52 | - 53 | Tested revision: `a6a261b8cedfb8a476d3ec5c5ac095e6d373cb18` 54 | - 55 | Repository: [https://github.com/3mdeb/coreboot](https://github.com/3mdeb/coreboot) 56 | 57 | [![asciicast](https://asciinema.org/a/L1HquySbGrlEPgqNYfFKUPDiW.svg)](https://asciinema.org/a/L1HquySbGrlEPgqNYfFKUPDiW) 58 | 59 | > Keep in mind that coreboot uses part of the data 60 | > generated by Hostboot at the time being. 61 | > This and the fact, coreboot doesn't initialize everything yet, 62 | > may affect the boot time in the future. 63 | 64 | ## Boot video recording vs the real situation 65 | 66 | Before coreboot or Hostboot can be started, the BMC must be already running. 67 | The recordings show only the process of starting Hostboot or coreboot. 68 | This means that BMC had to be started before 69 | (it does automatically after plugging in the power), 70 | and it takes a few moments too. 71 | 72 | When the BMC is running, then the main system 73 | can be started through the web browser, 74 | command over ssh or the power button on the computer case 75 | -------------------------------------------------------------------------------- /devnotes/scripts/dump_seeprom.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # Must add new devices to access 64k 4 | echo 24c512 0xa0d4 > /sys/bus/i2c/devices/i2c-0/new_device 5 | echo 24c512 0xa0d5 > /sys/bus/i2c/devices/i2c-0/new_device 6 | echo 24c512 0xa0d6 > /sys/bus/i2c/devices/i2c-0/new_device 7 | echo 24c512 0xa0d7 > /sys/bus/i2c/devices/i2c-0/new_device 8 | 9 | cp /sys/bus/i2c/devices/0-a0d4/eeprom _seeprom0 10 | cp /sys/bus/i2c/devices/0-a0d5/eeprom _seeprom1 11 | cp /sys/bus/i2c/devices/0-a0d6/eeprom _seeprom2 12 | cp /sys/bus/i2c/devices/0-a0d7/eeprom _seeprom3 13 | 14 | echo 0xa0d4 > /sys/bus/i2c/devices/i2c-0/delete_device 15 | echo 0xa0d5 > /sys/bus/i2c/devices/i2c-0/delete_device 16 | echo 0xa0d6 > /sys/bus/i2c/devices/i2c-0/delete_device 17 | echo 0xa0d7 > /sys/bus/i2c/devices/i2c-0/delete_device 18 | 19 | # Each part has a size that is a multiple of 9 bytes (8 data + 1 ECC), rest is 20 | # padded with zeros. 64k % 9 = 7, that is the number of bytes to skip. Not sure 21 | # if globbing keeps the proper order, use explicit file names just in case. 22 | # Also, output file extension must be '.ecc', otherwise 'ecc' tool complains. 23 | ## FIXME: Busybox's 'head' on BMC does not support '-c', find an alternative 24 | head -c-7 -q _seeprom0 _seeprom1 _seeprom2 _seeprom3 > seeprom.bin.ecc 25 | 26 | # Remove temporary files 27 | rm _seeprom? 28 | 29 | ecc -R seeprom.bin.ecc -p -o seeprom.bin 30 | 31 | ## To write it back: 32 | # 33 | #ecc -I seeprom.bin -p -o seeprom.bin.ecc 34 | #split -d -a 1 -b 65529 seeprom.bin.ecc --filter='dd bs=65536 conv=sync of=$FILE' _seeprom 35 | # 36 | #echo 24c512 0xa0d4 > /sys/bus/i2c/devices/i2c-0/new_device 37 | #echo 24c512 0xa0d5 > /sys/bus/i2c/devices/i2c-0/new_device 38 | #echo 24c512 0xa0d6 > /sys/bus/i2c/devices/i2c-0/new_device 39 | #echo 24c512 0xa0d7 > /sys/bus/i2c/devices/i2c-0/new_device 40 | # 41 | ## This is slow, about 10 min per part. We can use bigger block size (blocks of 42 | ## up to 32 bytes were tested), but this saves just a few seconds. 43 | #dd of=/sys/bus/i2c/devices/0-a0d4/eeprom if=_seeprom0 bs=1 44 | #dd of=/sys/bus/i2c/devices/0-a0d5/eeprom if=_seeprom1 bs=1 45 | #dd of=/sys/bus/i2c/devices/0-a0d6/eeprom if=_seeprom2 bs=1 46 | #dd of=/sys/bus/i2c/devices/0-a0d7/eeprom if=_seeprom3 bs=1 47 | # 48 | ## To write HBBL part only (may be different if SEEPROM layout changes!): 49 | ##dd of=/sys/bus/i2c/devices/0-a0d7/eeprom if=_seeprom3 bs=1 skip=$((0x4e1e)) seek=$((0x4e1e)) count=$((0x5a00)) 50 | # 51 | #echo 0xa0d4 > /sys/bus/i2c/devices/i2c-0/delete_device 52 | #echo 0xa0d5 > /sys/bus/i2c/devices/i2c-0/delete_device 53 | #echo 0xa0d6 > /sys/bus/i2c/devices/i2c-0/delete_device 54 | #echo 0xa0d7 > /sys/bus/i2c/devices/i2c-0/delete_device 55 | # 56 | ## Remove temporary files 57 | #rm _seeprom? 58 | -------------------------------------------------------------------------------- /devnotes/pci.md: -------------------------------------------------------------------------------- 1 | ## Specifications 2 | 3 | [POWER9 PCIe Controller (Functional Specification)](https://wiki.raptorcs.com/w/images/a/a5/POWER9_PCIe_controller_v11_27JUL2018_pub.pdf) 4 | 5 | [Power Systems Host Bridge 4 (PHB4) Specification](https://wiki.raptorcs.com/w/images/a/ad/P9_PHB_version1.0_27July2018_pub.pdf) 6 | 7 | ## Terms 8 | 9 | PEC - PCI Express Controller (probably) 10 | 11 | PHB - PCI Express Host Bridge ("PCIe controller integrated into the CPU and 12 | which connects the CPU with a number of PCIe lanes.") 13 | 14 | ## Initialization process 15 | 16 | - istep 10.10 `proc_pcie_scominit` : Apply scom inits to PCIe chiplets 17 | 18 | * `src/usr/isteps/istep10/host_proc_pcie_scominit.C` 19 | * `src/usr/isteps/istep10/host_proc_pcie_scominit.H` 20 | * `src/usr/isteps/istep10/call_proc_pcie_scominit.C` 21 | * `src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.C` 22 | * `src/import/chips/p9/procedures/hwp/nest/p9_pcie_scominit.H` 23 | 24 | Performs PCIE Phase1 init sequence via SCOM calls. 25 | 26 | - istep 10.12 `proc_chiplet_enable_ridi` : Enable RI/DI chip wide (maybe needed) 27 | 28 | * `src/import/chips/p9/procedures/hwp/perv/p9_chiplet_enable_ridi.C` 29 | * `src/import/chips/p9/procedures/hwp/perv/p9_chiplet_enable_ridi.H` 30 | 31 | Updates value of `NET_CTRL0` register. 32 | 33 | - istep 14.3 `proc_pcie_config` : Configure the PHBs 34 | 35 | * `src/import/chips/p9/procedures/hwp/nest/p9_pcie_config.C` 36 | 37 | Performs PCIE Phase2 init sequence. 38 | 39 | - istep 14.5 `proc_setup_bars` : Setup Memory BARs 40 | 41 | Looks like 14.3 does this for PCIe. 42 | 43 | ## Other relevant sources 44 | 45 | * `setup_pcie_work_around_attributes()` in 46 | `src/import/chips/p9/procedures/hwp/perv/p9_getecid.C`. 47 | 48 | ## What's "initfile" that appears sometimes in comments/documentation? 49 | 50 | This seems to be a reference to source files in 51 | `src/import/chips/p9/procedures/hwp/initfiles/` directory. There are also two 52 | `*.initfiles` there. 53 | 54 | ## Hostboot attributes 55 | 56 | At least 30 PCIe-related attributes which are described in 57 | `src/import/chips/p9/procedures/xml/attribute_info/p9_pcie_attributes.xml`: 58 | - 4 targets system 59 | - 1 targets PHB 60 | - 25 target PEC 61 | 62 | Some others are also queried (for example, those related to defect workarounds). 63 | 64 | ## Discovery/enumeration 65 | 66 | Two kinds: PECs and PHBs. 67 | 68 | `src/import/hwpf/fapi2/include/error_info_defs.H`: 69 | ```c 70 | MAX_PEC_PER_PROC = 3, //Nimbus,Cumulus,Axone 71 | MAX_PHB_PER_PROC = 6, //Nimbus,Cumulus,Axone 72 | ``` 73 | 74 | `talos.xml` has: 75 | ```xml 76 | 77 | PROC_PCIE_NUM_PEC 78 | 3 79 | 80 | 81 | PROC_PCIE_NUM_PHB 82 | 6 83 | 84 | ``` 85 | 86 | Probably can assume that all of them are present. 87 | -------------------------------------------------------------------------------- /logs/pflash.log: -------------------------------------------------------------------------------- 1 | Flash info: 2 | ----------- 3 | Name = /dev/mtd6 4 | Total size = 64MB Flags E:ECC, P:PRESERVED, R:READONLY, B:BACKUP 5 | Erase granule = 64KB F:REPROVISION, V:VOLATILE, C:CLEARECC 6 | 7 | TOC@0x00000000 Partitions: 8 | ----------- 9 | ID=00 part 0x00000000..0x00002000 (actual=0x00002000) [----R-----] 10 | ID=01 HBEL 0x00008000..0x0002c000 (actual=0x00024000) [E-----F-C-] 11 | ID=02 GUARD 0x0002c000..0x00031000 (actual=0x00005000) [E--P--F-C-] 12 | ID=03 NVRAM 0x00031000..0x000c1000 (actual=0x00090000) [---P--F---] 13 | ID=04 SECBOOT 0x000c1000..0x000e5000 (actual=0x00024000) [E--P------] 14 | ID=05 DJVPD 0x000e5000..0x0012d000 (actual=0x00048000) [E--P--F-C-] 15 | ID=06 MVPD 0x0012d000..0x001bd000 (actual=0x00090000) [E--P--F-C-] 16 | ID=07 CVPD 0x001bd000..0x00205000 (actual=0x00048000) [E--P--F-C-] 17 | ID=08 HBB 0x00205000..0x00305000 (actual=0x00100000) [EL--R-----] 18 | ID=09 HBD 0x00305000..0x00425000 (actual=0x00120000) [EL--------] 19 | ID=10 HBI 0x00425000..0x019c5000 (actual=0x015a0000) [EL--R-----] 20 | ID=11 SBE 0x019c5000..0x01a81000 (actual=0x000bc000) [ELI-R-----] 21 | ID=12 HCODE 0x01a81000..0x01ba1000 (actual=0x00120000) [EL--R-----] 22 | ID=13 HBRT 0x01ba1000..0x021a1000 (actual=0x00600000) [EL--R-----] 23 | ID=14 PAYLOAD 0x021a1000..0x022a1000 (actual=0x00100000) [-L--R-----] 24 | ID=15 BOOTKERNEL 0x022a1000..0x03821000 (actual=0x01580000) [-L--R-----] 25 | ID=16 OCC 0x03821000..0x03941000 (actual=0x00120000) [EL--R-----] 26 | ID=17 FIRDATA 0x03941000..0x03944000 (actual=0x00003000) [E-----F-C-] 27 | ID=18 VERSION 0x03944000..0x03946000 (actual=0x00002000) [-L--R-----] 28 | ID=19 BMC_INV 0x03968000..0x03971000 (actual=0x00009000) [------F---] 29 | ID=20 HBBL 0x03971000..0x03978000 (actual=0x00007000) [EL--R-----] 30 | ID=21 ATTR_TMP 0x03978000..0x03980000 (actual=0x00008000) [------F---] 31 | ID=22 ATTR_PERM 0x03980000..0x03988000 (actual=0x00008000) [E-----F-C-] 32 | ID=23 IMA_CATALOG 0x03989000..0x039c9000 (actual=0x00040000) [EL--R-----] 33 | ID=24 RINGOVD 0x039c9000..0x039e9000 (actual=0x00020000) [----------] 34 | ID=25 WOFDATA 0x039e9000..0x03ce9000 (actual=0x00300000) [EL--R-----] 35 | ID=26 HB_VOLATILE 0x03ce9000..0x03cee000 (actual=0x00005000) [E-----F-CV] 36 | ID=27 MEMD 0x03cee000..0x03cfc000 (actual=0x0000e000) [EL--R-----] 37 | ID=28 SBKT 0x03d02000..0x03d06000 (actual=0x00004000) [EL--R-----] 38 | ID=29 HDAT 0x03d06000..0x03d0e000 (actual=0x00008000) [EL--R-----] 39 | ID=30 UVISOR 0x03d10000..0x03e10000 (actual=0x00100000) [-L--R-----] 40 | ID=31 BOOTKERNFW 0x03e10000..0x03ff0000 (actual=0x001e0000) [---P------] 41 | ID=32 BACKUP_PART 0x03ff7000..0x03fff000 (actual=0x00000000) [----RB----] 42 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_13_4_mem_pll_setup.log: -------------------------------------------------------------------------------- 1 | 436.15235|ISTEP 13. 4 - mem_pll_setup 2 | 436.15899|ISTEPS_TRACE|call_mem_pll_setup entry 3 | 436.15969|ISTEPS_TRACE|Running p9_mem_pll_setup HWP on target HUID 00050000 4 | 436.18558|FAPI|p9_mem_pll_setup.C: Entering ... 5 | 436.18605|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0045 DFFFFFFFFFFFFFFF 6 | 436.18609|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0045 BFFFFFFFFFFFFFFF 7 | 436.18614|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0041 EFFFFFFFFFFFFFFF 8 | 436.18618|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0041 F7FFFFFFFFFFFFFF 9 | 436.19123|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0019 F000000000000000 10 | 436.19127|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0041 FBFFFFFFFFFFFFFF 11 | 436.19131|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030001 5500000700000020 12 | 436.19135|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030001 5500000700003020 13 | 436.19139|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F001F FFFFFFFFFFFFFFFF 14 | 436.19143|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F001E 037C000000000000 15 | 436.19148|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F001E 0374000000000000 16 | 436.19152|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0045 DFFFFFFFFFFFFFFF 17 | 436.19156|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0045 BFFFFFFFFFFFFFFF 18 | 436.19160|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0041 EFFFFFFFFFFFFFFF 19 | 436.19164|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0041 F7FFFFFFFFFFFFFF 20 | 436.19669|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0019 F000000000000000 21 | 436.19673|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0041 FBFFFFFFFFFFFFFF 22 | 436.19677|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030001 5000000000000020 23 | 436.19681|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030001 5000000000003020 24 | 436.19686|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F001F FFFFFFFFFFFFFFFF 25 | 436.19690|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F001E 037C000000000000 26 | 436.19694|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F001E 0374000000000000 27 | 436.19695|FAPI|p9_mem_pll_setup.C: Exiting ... 28 | 436.19698|ISTEPS_TRACE|SUCCESS running p9_mem_pll_setup HWP on target HUID 00050000 29 | 436.19699|ISTEPS_TRACE|call_mem_pll_setup exit 30 | 436.23039|SCOM|doMulticastWorkaround on 00050000 for 50040018 31 | 436.23088|SCOM|doMulticastWorkaround on 00050000 for 50040009 32 | 436.23148|ERRL|I>Got an error log Msg - Type: 0x00000039 33 | 436.23149|ERRL|I>Flush message received 34 | 436.23151|INITSVC|<>doIstep: step 13, substep 6, task mem_startclocks 36 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_10_12_proc_chiplet_enable_ridi.log: -------------------------------------------------------------------------------- 1 | 433.30254|ISTEP 10.12 - proc_chiplet_enable_ridi 2 | 433.31496|ISTEPS_TRACE|>>call_proc_chiplet_enable_ridi entry 3 | 433.31499|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_chiplet_enable_ridi) entry 4 | 433.31571|ISTEPS_TRACE|Running p9_chiplet_enable_ridi HWP on target HUID 00050000 5 | 433.33012|FAPI|p9_chiplet_enable_ridi.C: Call p9_chiplet_enable_ridi_net_ctrl_action_function 6 | 433.33013|FAPI|p9_chiplet_enable_ridi.C: Check for chiplet enable 7 | 433.33019|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0040 80263F0100000000 8 | 433.33021|FAPI|p9_chiplet_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 9 | 433.33025|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0042 00001C0000000000 10 | 433.33028|FAPI|p9_chiplet_enable_ridi.C: Call p9_chiplet_enable_ridi_net_ctrl_action_function 11 | 433.33030|FAPI|p9_chiplet_enable_ridi.C: Check for chiplet enable 12 | 433.33035|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0040 80263F0100000000 13 | 433.33036|FAPI|p9_chiplet_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 14 | 433.33041|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0042 00001C0000000000 15 | 433.33044|FAPI|p9_chiplet_enable_ridi.C: Call p9_chiplet_enable_ridi_net_ctrl_action_function 16 | 433.33045|FAPI|p9_chiplet_enable_ridi.C: Check for chiplet enable 17 | 433.33050|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c13 : 00000000000F0040 B006030100000000 18 | 433.33052|FAPI|p9_chiplet_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 19 | 433.33056|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c13 : 00000000000F0042 00001C0000000000 20 | 433.33062|FAPI|p9_chiplet_enable_ridi.C: Call p9_chiplet_enable_ridi_net_ctrl_action_function 21 | 433.33064|FAPI|p9_chiplet_enable_ridi.C: Check for chiplet enable 22 | 433.33069|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c14 : 00000000000F0040 B006030100000000 23 | 433.33070|FAPI|p9_chiplet_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 24 | 433.33075|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c14 : 00000000000F0042 00001C0000000000 25 | 433.33078|FAPI|p9_chiplet_enable_ridi.C: Call p9_chiplet_enable_ridi_net_ctrl_action_function 26 | 433.33079|FAPI|p9_chiplet_enable_ridi.C: Check for chiplet enable 27 | 433.33084|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c15 : 00000000000F0040 B006030100000000 28 | 433.33086|FAPI|p9_chiplet_enable_ridi.C: Enable Recievers, Drivers DI1 & DI2 29 | 433.33090|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c15 : 00000000000F0042 00001C0000000000 30 | 433.33094|ISTEPS_TRACE|SUCCESS: p9_chiplet_enable_ridi HWP returned success with target HUID 0x00050000 31 | 433.33095|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 34 | 433.39772|ERRL|I>Flush message received 35 | 433.39774|INITSVC|<>doIstep: step 10, substep 13, task host_rng_bist 37 | -------------------------------------------------------------------------------- /devnotes/pdfgrep.md: -------------------------------------------------------------------------------- 1 | # Grepping through registers PDFs 2 | 3 | ## pdfgrep 4 | 5 | * [homepage](https://pdfgrep.org/) 6 | 7 | * installation 8 | 9 | ``` 10 | sudo apt install pdfgrep 11 | ``` 12 | 13 | ## Basic grep 14 | 15 | ``` 16 | pdfgrep --cache --page-number 800AE8000601143F \ 17 | POWER9_Registers_vol1_version1.1_pub.pdf \ 18 | POWER9_Registers_vol2_version1.2_pub.pdf \ 19 | POWER9_Registers_vol3_version1.2_pub.pdf 20 | ``` 21 | 22 | The result is something like: 23 | 24 | ``` 25 | POWER9_Registers_vol2_version1.2_pub.pdf:191:IOF2.RX.RX0.RXCTL.GLBSM.REGS.RX_GLBSM_CNTL3_EO_PG 0x800AE8000601143F 1128 26 | POWER9_Registers_vol2_version1.2_pub.pdf:1128: Address 800AE8000601143F (SCOM) 27 | ``` 28 | 29 | It provides useful info such as the volmue and page number. 30 | 31 | ## More advanced tries 32 | 33 | We could try to parse required information from the PDF files and create some 34 | kind of database based on that. But there are a few problems 35 | 36 | Some basic tries to parse out all addresses: 37 | 38 | ``` 39 | pdfgrep --cache --no-filename "Address\s+[[:alnum:]]+\s+\(SCOM\)" \ 40 | POWER9_Registers_vol1_version1.1_pub.pdf \ 41 | POWER9_Registers_vol2_version1.2_pub.pdf \ 42 | POWER9_Registers_vol3_version1.2_pub.pdf \ 43 | | tr -d ' ' | sed -e "s/Address//" 44 | ``` 45 | 46 | 11061 were found 47 | 48 | Some basic tries to parse out all mnemonics: 49 | 50 | ``` 51 | pdfgrep --cache --no-filename " Mnemonic\s+[[:alnum:]]+\.[[:alnum:]]" \ 52 | POWER9_Registers_vol1_version1.1_pub.pdf \ 53 | POWER9_Registers_vol2_version1.2_pub.pdf \ 54 | POWER9_Registers_vol3_version1.2_pub.pdf \ 55 | | tr -d ' ' | sed -e "s/Mnemonic//" 56 | ``` 57 | 58 | 11253 were found 59 | 60 | Quick look indicates that it matches 1:1 (N entry in `address` list matches 61 | with N entry in the `mnemonics` list) until around 7-8k entry. 62 | 63 | There are a few exceptions in the PDFs tables which would make the parsing more 64 | complicated (but it still should be feasible). 65 | 66 | For example, some Address fields contains two or more entries like here: 67 | 68 | ``` 69 | 000000000006C42E (SCOM) 70 | 000000000006C52E (SCOM1) 71 | ``` 72 | 73 | Only the first one one would be parsed out this way, as only the first entry in 74 | the table is in the same line with the `Address` string. 75 | 76 | ``` 77 | pdfgrep --cache --page-number 000000000006C42E \ 78 | POWER9_Registers_vol1_version1.1_pub.pdf \ 79 | POWER9_Registers_vol2_version1.2_pub.pdf \ 80 | POWER9_Registers_vol3_version1.2_pub.pdf 81 | 82 | POWER9_Registers_vol1_version1.1_pub.pdf:47:TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OPIT1C14 0x000000000006C42E 293 83 | POWER9_Registers_vol1_version1.1_pub.pdf:293: Address 000000000006C42E (SCOM) 84 | 85 | 86 | pdfgrep --cache --page-number 000000000006C52E \ 87 | POWER9_Registers_vol1_version1.1_pub.pdf \ 88 | POWER9_Registers_vol2_version1.2_pub.pdf \ 89 | POWER9_Registers_vol3_version1.2_pub.pdf 90 | 91 | POWER9_Registers_vol1_version1.1_pub.pdf:293: 000000000006C52E (SCOM1) 92 | ``` 93 | -------------------------------------------------------------------------------- /devnotes/hdat.md: -------------------------------------------------------------------------------- 1 | ## Naming convensions 2 | 3 | - HDAT 4 | 5 | `HDAT` or `Hostboot DATa` is the name used by `Hostboot`. 6 | 7 | Specification is mentioned by the source code, 8 | but accordign to the current knowledge it is not public. 9 | > "6.1.1 System Parameters" of the Hypervisor Interface Data 10 | > Specifications document (aka the "HDAT spec) 11 | 12 | - SPIRA 13 | 14 | `SPIRA` means `SP Interface Root Array` and is the name used by Skiboot 15 | 16 | - SPIRA-S 17 | 18 | `SPIRA-S` most likely refers to `Service processor SPIRA` 19 | 20 | ```cpp 21 | /* The service processor SPIRA-S structure */ 22 | struct spiras *spiras; 23 | ``` 24 | 25 | - SPIRA-H 26 | 27 | `SPIRA-H` most likely refers to `Hypervisor SPIRA` 28 | ```cpp 29 | /* The Hypervisor SPIRA-H Structure */ 30 | __section(".spirah.data") struct spirah spirah = { 31 | ``` 32 | 33 | Hostboot uses this name sometimes to reference the HDAT 34 | > * @brief Write actual architected register detail to HDAT/SPIRAH 35 | 36 | 37 | ## Dump from memory 38 | 39 | - SPIRA-H 40 | - address: 0x30010400 41 | - size: 0x200 42 | ``` 43 | ssh root@talos pdbg -p0 -c1 -t0 getmem 0x30010400 0x200 2>/dev/null > spira-h.bin 44 | ``` 45 | - SPIRA-S 46 | - address: 0x30010000 47 | - size: 0x400 48 | ``` 49 | ssh root@talos pdbg -p0 -c1 -t0 getmem 0x30010000 0x400 2>/dev/null > spira-s.bin 50 | ``` 51 | - SPIRA_HEAP image 52 | 53 | - address: 0x31200000 54 | - size: 0x00800000 55 | ``` 56 | ssh root@talos pdbg -p0 -c1 -t0 getmem 0x31200000 0x800000 2>/dev/null > spira-heap.bin 57 | ``` 58 | 59 | ## Convert to device-tree 60 | 61 | Skiboot includes a tool able to convert HDAT into device-tree. 62 | Source is located in the [hdata/test/hdata_to_dt.c](https://github.com/open-power/skiboot/blob/master/hdata/test/hdata_to_dt.c) file. 63 | 64 | ### Build the tool 65 | 66 | To build the `hdata_to_dt`, execute following command in the root 67 | of the Skiboot repository. 68 | 69 | ``` 70 | make hdata/test/hdata_to_dt 71 | ``` 72 | 73 | This command should create `hdata_to_dt` binary which will be located in the 74 | `hdata/test/hdata_to_dt` file. 75 | 76 | ### Using the tool 77 | 78 | The tool requires `SPIRA` and `Heap images` 79 | 80 | > hdata_to_dt: Converts HDAT dumps to DTB. 81 | > 82 | > Usage: 83 | > hdata 84 | > hdata -s 85 | > Options: 86 | > -v Verbose 87 | > -q Quiet mode 88 | > -b Keep blobs in the output 89 | > 90 | > -8 Force PVR to POWER8 91 | > -8E Force PVR to POWER8E 92 | > -9 Force PVR to POWER9 (nimbus) 93 | > -9P Force PVR to POWER9P (Axone) 94 | > -10 Force PVR to POWER10 95 | > 96 | > When no PVR is specified -8 is assumed 97 | > Pipe to 'dtc -I dtb -O dts' for human readable output 98 | 99 | ``` 100 | hdata/test/hdata_to_dt -9 -s hdata/test/p8-840-spira.spirah hdata/test/op920.wsp.heap 101 | ``` 102 | -------------------------------------------------------------------------------- /devnotes/isteps/18_establish_system_SMP_and_TOD/12_proc_tod_init.md: -------------------------------------------------------------------------------- 1 | ```cpp 2 | void TodSvc::todInit() 3 | { 4 | p9_tod_clear_error_reg(TOD::iv_todConfig[TOD_PRIMARY].iv_mdmt->iv_tod_node_data); 5 | init_tod_node(TOD::iv_todConfig[TOD_PRIMARY].iv_mdmt->iv_tod_node_data); 6 | } 7 | 8 | void p9_tod_clear_error_reg(const tod_topology_node* i_tod_node) 9 | { 10 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_ERROR_REG, 0xFFFFFFFFFFFFFFFF); 11 | } 12 | 13 | void init_tod_node(const tod_topology_node* i_tod_node) 14 | { 15 | // Sequence details are in TOD Workbook section 1.6.3 16 | // Is the current TOD being processed the master drawer master TOD? 17 | if (i_tod_node->i_tod_master && i_tod_node->i_drawer_master) 18 | { 19 | // TOD Step checkers enable - write TOD_TX_TTYPE_2_REG to enable 20 | // TOD STEP checking on all chips 21 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_TX_TTYPE_2_REG, PPC_BIT(PERV_TOD_TX_TTYPE_2_REG_TRIGGER)); 22 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_LOAD_TOD_MOD_REG, PPC_BIT(PERV_TOD_LOAD_TOD_MOD_REG_FSM_TRIGGER)); 23 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_TX_TTYPE_5_REG, PPC_BIT(PERV_TOD_TX_TTYPE_5_REG_TRIGGER)); 24 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_LOAD_TOD_REG, PERV_TOD_LOAD_REG_LOAD_VALUE); 25 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_START_TOD_REG, PPC_BIT(PERV_TOD_START_TOD_REG_FSM_TRIGGER)); 26 | fapi2::putScom(*(i_tod_node->i_target), PERV_TOD_TX_TTYPE_4_REG, PPC_BIT(PERV_TOD_TX_TTYPE_4_REG_TRIGGER)); 27 | } 28 | 29 | uint32_t l_tod_init_pending_count = 0; 30 | while(l_tod_init_pending_count < P9_TOD_UTIL_TIMEOUT_COUNT) 31 | { 32 | uint64_t l_tod_fsm_reg; 33 | fapi2::delay(P9_TOD_UTILS_HW_NS_DELAY, P9_TOD_UTILS_SIM_CYCLE_DELAY); 34 | fapi2::getScom(*(i_tod_node->i_target), PERV_TOD_FSM_REG, l_tod_fsm_reg); 35 | 36 | if (l_tod_fsm_reg & PPC_BIT(PERV_TOD_FSM_REG_IS_RUNNING)) 37 | { 38 | break; 39 | } 40 | ++l_tod_init_pending_count; 41 | } 42 | 43 | fapi2::putScom( 44 | *(i_tod_node->i_target), 45 | PERV_TOD_ERROR_REG, 46 | PPC_BIT(PERV_TOD_ERROR_REG_RX_TTYPE_2) 47 | | PPC_BIT(PERV_TOD_ERROR_REG_RX_TTYPE_4) 48 | | PPC_BIT(PERV_TOD_ERROR_REG_RX_TTYPE_5)); 49 | 50 | fapi2::getScom(*(i_tod_node->i_target), PERV_TOD_ERROR_REG, l_tod_err_reg); 51 | 52 | fapi2::Target l_fapiFailingProcTarget(NULL); 53 | // going to assert, populate pointer prior to exit 54 | if (l_tod_err_reg.getBit() 55 | || l_tod_err_reg.getBit()) 56 | { 57 | *l_fapiFailingProcTarget = *(i_tod_node->i_target); 58 | } 59 | 60 | fapi2::putScom( 61 | *(i_tod_node->i_target), 62 | PERV_TOD_ERROR_MASK_REG, 63 | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_0) 64 | | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_1) 65 | | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_2) 66 | | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_3) 67 | | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_4) 68 | | PPC_BIT(PERV_TOD_ERROR_MASK_REG_RX_TTYPE_5)); 69 | } 70 | ``` 71 | -------------------------------------------------------------------------------- /devnotes/mvpd_partition_structure.md: -------------------------------------------------------------------------------- 1 | # This file describes MVPD partition internal structure 2 | 3 | ## TOC 4 | At the begining of `MVPD` partition `Table Of Content` is placed. 5 | It includes names and addresses of `Records` counting from the begining 6 | of the partition, but not including checksums. 7 | `TOC` can have up to 32 entries, but only 20 are filled by `Hostboot`. 8 | 9 | ```cpp 10 | struct toc_def { 11 | char recordName[4], 12 | record* recordAddress, // Little Endian 13 | // Offset from the beginning of partition. 14 | // Doesn't include checksums. 15 | // Remember to account for that if present 16 | // or remove checksums using ecc tool. 17 | uint16_t unused, 18 | }; 19 | 20 | toc_def TOC[32]; 21 | ``` 22 | 23 | ## Record 24 | Each `Record` includes some kind of address which purpouse is yet unknown, 25 | `RT Keyword` holding 1 byte of data, string name of the record 26 | and an array of `Keywords` which can be as long as 27 | the space before the next `Keyword` beginning. 28 | 29 | Following records are present in `MVPD` after `Hostboot` has filled the partition:\ 30 | `CP00`, `CRP0`, `LRP0`, `LRP1`,\ 31 | `LRP2`, `LRP3`, `LRP4`, `LRP5`,\ 32 | `LWP0`, `LWP1`, `LWP2`, `LWP3`,\ 33 | `LWP4`, `LWP5`, `MER0`, `VER0`,\ 34 | `VINI`, `VMSC`, `VRML`, `VWML`\ 35 | It is unknown if other `Keyword` names could also be present in `MVPD`. 36 | 37 | ```cpp 38 | struct record { 39 | uint16_t address; 40 | keyword RTKeyword( // This Keyword is always present 41 | char recordName[4] // and holds Record name as data. 42 | ); 43 | keyword keywords[]; // Can hold any amount of Keywords. 44 | }; 45 | ``` 46 | 47 | ## Keyword 48 | 49 | There are two possible types of `Keywords`. `Pound` and `Non-Pound` ones. 50 | In each case the structure is a bit different and `Pound Keywords` can be larger. 51 | 52 | Only some defined `Keywords` names are valid. 53 | 54 | Possible `Keyword` names:\ 55 | `20`, `21`, `30`, `31`, `AW`, `CC`,\ 56 | `CE`, `CH`, `CT`, `DD`, `DN`, `DR`,\ 57 | `ED`, `FN`, `HE`, `HW`, `IN`, `IQ`,\ 58 | `L1`, `L2`, `L3`, `L4`, `L5`, `L6`,\ 59 | `L7`, `L8`, `PB`, `PG`, `PK`, `PM`,\ 60 | `PN`, `PR`, `PZ`, `RT`, `SB`, `SN`,\ 61 | `TE`, `VD`, `VZ` 62 | 63 | Possible `Pound Keyword` names:\ 64 | `#G`, `#H`, `#I`, `#M`, `#R`, `#V`, `#W` 65 | 66 | ```cpp 67 | struct keyword { 68 | char keywordName[2]; 69 | uint8_t keywordSize; // Little Endian 70 | // Doesn't include checksums. 71 | char data[keywordSize]; 72 | }; 73 | 74 | struct pound_keyword { 75 | char keywordName[2]; // NOTE must include leading '#' 76 | uint16_t keywordSize; // Little Endian 77 | // Doesn't include checksums. 78 | char data[keywordSize]; 79 | }; 80 | ``` 81 | 82 | ## Ring 83 | 84 | Some of the keywords contain structures called `Ring`. 85 | This structure is compressed usign RS4 algorithm and has a header of 86 | following structure. 87 | ```cpp 88 | struct CompressedScanData { 89 | uint16_t iv_magic; // Always "RS" 90 | uint8_t iv_version; 91 | uint8_t iv_type; 92 | uint16_t iv_size; // Big Endian 93 | // Includes this structure and data after. 94 | // Doesn't include checksums. 95 | RingId_t iv_ringId; // This is used to recognize correct Ring 96 | uint32_t iv_scanAddr; 97 | char data[] 98 | }; 99 | ``` 100 | -------------------------------------------------------------------------------- /devnotes/initial_cpu_state.md: -------------------------------------------------------------------------------- 1 | # CPU state on stage entries 2 | 3 | CPU is expected to work in big endian at all times during coreboot execution. 4 | This decision was made because: 5 | 6 | * this is the endianness in which coreboot execution starts 7 | * `coreboot-sdk` includes libgcc compiled for BE only 8 | * there are CPU load/store instructions with endianness conversion 9 | * some instructions are only available in BE 10 | * it will help to assure that all of coreboot components are designed in 11 | endian-agnostic way - CBFS, FMAP, (de)compression algorithms etc. 12 | 13 | When an OS or a payload starts, it usually executes a [sequence of instructions](https://github.com/torvalds/linux/blob/v5.8/arch/powerpc/boot/ppc_asm.h#L65) 14 | to switch to the target endianness of its choosing. 15 | 16 | ## Bootblock 17 | 18 | The entry state depends on whether bootblock is loaded instead of HBBL (Hostboot 19 | bootloader) or HBB (Hostboot core). 20 | 21 | #### HBBL 22 | 23 | Binary size is limited to 20 kB (ECC not included). HRMOR is set to 130 MB, that 24 | is 2 MB into the L3 cache region (10 MB total). HBBL is loaded to HRMOR + 12 kB, 25 | so the exception vectors (which are very sparse) do not have to be included into 26 | already limited size of HBBL. SBE jumps to HRMOR + 12 kB, no other registers are 27 | set. 28 | 29 | #### HBB 30 | 31 | HRMOR is set to 128 MB (beginning of L3 cache). In current HBBL implementation, 32 | HBB image size is limited to 1 MB with ECC (space in range 128-130 MB is split 33 | in half between ECC and non-ECC image of HBB). HBB can later overwrite memory 34 | used previously by HBBL and ECC image. HBB begins execution at HRMOR, no space 35 | is implicitly reserved for exception vectors. 36 | 37 | ### Common parts 38 | 39 | Except for those 12 kB reserved for exception vectors and consequent change to 40 | the linking address, the state is almost identical for both paths. 41 | 42 | Different HRMOR doesn't impact the linking address, we are using only hypervisor 43 | state with real mode addressing so HRMOR is always added during calculation of 44 | effective addresses. Whenever access to physical address is required (e.g. IO 45 | operations), bit 0 (MSB) is set so HRMOR is ignored. 46 | 47 | There are no guaranteed values in any of the registers, some of them must be set 48 | before we can begin execution of C code. 49 | 50 | ###### Stack 51 | 52 | `r1` is stack register. It must be loaded with a proper value before any C 53 | function is called. 54 | 55 | ###### TOC 56 | 57 | PPC64 reserves one register (`r2`) for a pointer to the table of contents. It is 58 | used to access GOT (global offset data) and SDA (small data area). This value is 59 | set separately for every externally visible function, and is saved in [function descriptor](https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi.html#FUNC-DES). 60 | All descriptors from a file are saved in a separate section called OPD (official 61 | procedure descriptors). When a function name's symbol is loaded into a register 62 | in assembly, it conveniently holds the address of descriptor; when it is used in 63 | a branch instruction, the entry point to the function is used instead. 64 | 65 | ###### BSS 66 | 67 | Bootblock is loaded as a binary (not ELF), which includes BSS. It is already 68 | zeroed so it doesn't require any additional work. If the size of bootblock 69 | becomes a problem, we can exclude this section from the binary and use cache 70 | memory, in that case we would have to zero it in the code. 71 | 72 | ### Hand-off to romstage 73 | 74 | TBD: 75 | * how to properly obtain new `r2`? 76 | -------------------------------------------------------------------------------- /devnotes/isteps/13_dram_training/02_mem_pll_reset.md: -------------------------------------------------------------------------------- 1 | ## mem_pll_reset: Reset PLL for MCAs in async (13.2) 2 | 3 | > a) p9_mem_pll_reset.C (proc chip) 4 | > - This step is a no-op on cumulus as the centaur is already has its PLLs setup in step 11 5 | > - This step is a no-op if memory is running in synchronous mode since the MCAs are using the nest PLL, HWP detect 6 | > and exits 7 | > - If in async mode then this HWP will put the PLL into bypass, reset mode 8 | > - Disable listen_to_sync for MEM chiplet, whenever MEM is not in sync to NEST 9 | 10 | ``` 11 | For each functional Proc: 12 | > if ( !ATTR_MC_SYNC_MODE ) 13 | For each functional MC(BIST?): 14 | // Assert endpoint reset 15 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WOR) // 0x070F0042 16 | [all] 0 17 | [1] PCB_EP_RESET = 1 18 | 19 | // Mask PLL unlock error in PCB slave 20 | TP.TPCHIP.NET.PCBSLMC01.SLAVE_CONFIG_REG // 0x070F001E 21 | [12] (part of) ERROR_MASK = 1 22 | 23 | // Move MC PLL into reset state (3 separate writes, no delays between them) 24 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WOR) // 0x070F0042 25 | [all] 0 26 | [5] PLL_BYPASS = 1 27 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WOR) // 0x070F0042 28 | [all] 0 29 | [4] PLL_RESET = 1 30 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WOR) // 0x070F0042 31 | [all] 0 32 | [3] PLL_TEST_EN = 1 33 | 34 | // Assert MEM PLDY and DCC bypass 35 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL1 (WOR) // 0x070F0046 36 | [all] 0 37 | [1] CLK_DCC_BYPASS_EN = 1 38 | [2] CLK_PDLY_BYPASS_EN = 1 39 | 40 | // Drop endpoint reset 41 | TP.TPCHIP.NET.PCBSLMC01.NET_CTRL0 (WAND) // 0x070F0041 42 | [all] 1 43 | [1] PCB_EP_RESET = 0 44 | 45 | // Disable listen to sync pulse to MC chiplet, when MEM is not in sync to nest 46 | TP.TCMC01.MCSLOW.SYNC_CONFIG // 0x07030000 47 | [4] LISTEN_TO_SYNC_PULSE_DIS = 1 48 | 49 | // Initialize OPCG_ALIGN register 50 | TP.TCMC01.MCSLOW.OPCG_ALIGN // 0x07030001 51 | [all] 0 52 | [0-3] INOP_ALIGN = 5 // 8:1 53 | [12-19] INOP_WAIT = 0 54 | [47-51] SCAN_RATIO = 0 // 1:1 55 | [52-63] OPCG_WAIT_CYCLES = 0x20 56 | 57 | // scan0 flush PLL boundary ring 58 | TP.TCMC01.MCSLOW.CLK_REGION // 0x07030006 59 | [all] 0 60 | [14] CLOCK_REGION_UNIT10 = 1 61 | [48] SEL_THOLD_SL = 1 62 | [49] SEL_THOLD_NSL = 1 63 | [50] SEL_THOLD_ARY = 1 64 | TP.TCMC01.MCSLOW.SCAN_REGION_TYPE // 0x07030005 65 | [all] 0 66 | [14] SCAN_REGION_UNIT10 = 1 67 | [56] SCAN_TYPE_BNDY = 1 68 | TP.TCMC01.MCSLOW.OPCG_REG0 // 0x07030002 69 | [0] RUNN_MODE = 0 70 | // Separate write, but don't have to read again 71 | TP.TCMC01.MCSLOW.OPCG_REG0 // 0x07030002 72 | [2] RUN_SCAN0 = 1 73 | 74 | timeout(200 * 16us): 75 | TP.TCMC01.MCSLOW.CPLT_STAT0 // 0x07000100 76 | if (([8] CC_CTRL_OPCG_DONE_DC) == 1) break 77 | delay(16us) 78 | 79 | // Cleanup 80 | TP.TCMC01.MCSLOW.CLK_REGION // 0x07030006 81 | [all] 0 82 | TP.TCMC01.MCSLOW.SCAN_REGION_TYPE // 0x07030005 83 | [all] 0 84 | ``` 85 | -------------------------------------------------------------------------------- /devnotes/isteps/8_nest_chiplets/3_host_cbs_start.md: -------------------------------------------------------------------------------- 1 | # 8.3 host_cbs_start 2 | 3 | Requires: 4 | * CFAM/FSI (register access and fifo reset) 5 | 6 | `p9_start_cbs` seems to be responsible for powering on second CPU, see comments 7 | at the bottom of `src/include/usr/sbeio/sbe_retry_handler.H` (for 8 | `iv_sbeRestartMethod`). 9 | 10 | ### src/usr/isteps/istep08/call_host_cbs_start.C 11 | 12 | ```python 13 | for l_cpu_target in l_cpuTargetList: 14 | if l_cpu_target is not l_pMasterProcTarget: 15 | sendFifoReset(l_cpu_target) ## described below 16 | p9_start_cbs(l_cpu_target, True) ## described below 17 | ``` 18 | 19 | ### src/usr/sbeio/sbe_scomAccess.C 20 | 21 | ```python 22 | def sendFifoReset(i_target) 23 | SbeFifo::performFifoReset(i_target) ## described below 24 | ``` 25 | 26 | ### src/usr/sbeio/sbe_fifodd.C 27 | 28 | ```python 29 | def performFifoReset(i_target) 30 | # Perform a write to the DNFIFO Reset to cleanup the fifo 31 | uint32_dummy = 0xDEAD 32 | writeFsi(i_target, SBE_FIFO_DNFIFO_RESET, &uint32_dummy) 33 | ``` 34 | 35 | ### src/import/chips/p9/procedures/hwp/perv/p9_start_cbs.C 36 | 37 | ```python 38 | # IO is done via CFAM/FSI 39 | def p9_start_cbs(i_target_chip, i_sbe_start): 40 | temp8_RESET_SKIP = fapi2::FAPI_SYSTEM.ATTR_START_CBS_FIFO_RESET_SKIP 41 | i_target_chip.PERV_SB_MSG = 0 42 | # PERV_CBS_CS.setBit<3>() 43 | # PERV_CBS_CS[28] = 1 44 | i_target_chip.PERV_CBS_CS |= 1<<28 45 | 46 | temp32_PERV_SB_CS = i_target_chip.PERV_SB_CS 47 | 48 | # PERV_SB_CS_START_RESTART_VECTOR0 49 | # temp32_PERV_SB_CS.clearBit<12>() 50 | # temp32_PERV_SB_CS[19] = 0 51 | temp32_PERV_SB_CS &= ~(1<<19) 52 | # PERV_SB_CS_START_RESTART_VECTOR1 53 | # temp32_PERV_SB_CS.clearBit<13>() 54 | # temp32_PERV_SB_CS[18] = 0 55 | temp32_PERV_SB_CS &= ~(1<<18) 56 | 57 | i_target_chip.PERV_SB_CS = temp32_PERV_SB_CS 58 | 59 | # i_target_chip.PERV_CBS_ENVSTAT.getBit<2>() 60 | #l_read_vdn_pgood_status = i_target_chip.PERV_CBS_ENVSTAT[29] 61 | l_read_vdn_pgood_status = (i_target_chip.PERV_CBS_ENVSTAT & (1<<29)) == (1<<29) 62 | assert(l_read_vdn_pgood_status) 63 | 64 | temp32_PERV_CBS_CS = i_target_chip.PERV_CBS_CS 65 | # temp32_PERV_CBS_CS.clearBit<0>() 66 | # temp32_PERV_CBS_CS.clearBit<2>() 67 | 68 | # temp32_PERV_CBS_CS[31] = 0 69 | temp32_PERV_CBS_CS &= ~(1<<31) 70 | # temp32_PERV_CBS_CS[29] = 0 71 | temp32_PERV_CBS_CS &= ~(1<<29) 72 | 73 | i_target_chip.PERV_CBS_CS = temp32_PERV_CBS_CS 74 | 75 | # temp32_PERV_CBS_CS[31] = 1 76 | temp32_PERV_CBS_CS |= 1<<31 77 | i_target_chip.PERV_CBS_CS = temp32_PERV_CBS_CS 78 | 79 | l_timeout = 20 80 | # UNTIL CBS_CS.CBS_CS_INTERNAL_STATE_VECTOR == CBS_IDLE_VALUE 81 | while l_poll_data != 0x002: 82 | temp32_PERV_CBS_CS = i_target_chip.PERV_CBS_CS 83 | # l_poll_data[15-0] = temp32_PERV_CBS_CS[15-0] 84 | l_poll_data = temp32_PERV_CBS_CS & 0xffff 85 | #fapi2::delay(P9_CBS_IDLE_HW_NS_DELAY, P9_CBS_IDLE_SIM_CYCLE_DELAY) 86 | sleep(640000ns) 87 | 88 | if not temp8_RESET_SKIP: 89 | i_target_chip.PERV_FSB_FSB_DOWNFIFO_RESET = 0x80000000 90 | 91 | if i_sbe_start: 92 | #Setting up hreset 93 | # PERV_SB_CS_START_RESTART_VECTOR0 94 | # i_target_chip.PERV_SB_CS[19] = 0 95 | i_target_chip.PERV_SB_CS &= ~(1<<19) 96 | # i_target_chip.PERV_SB_CS[19] = 1 97 | i_target_chip.PERV_SB_CS |= 1<<19 98 | # i_target_chip.PERV_SB_CS[19] = 0 99 | i_target_chip.PERV_SB_CS &= ~(1<<19) 100 | 101 | #l_fsi2pib_status = i_target_chip.PERV_FSI2PIB_STATUS[15] 102 | l_fsi2pib_status = (i_target_chip.PERV_FSI2PIB_STATUS & (1 << 15)) == (1 << 15) 103 | assert(l_fsi2pib_status); 104 | ``` 105 | -------------------------------------------------------------------------------- /devnotes/poke/mvpd.pk: -------------------------------------------------------------------------------- 1 | /* 2 | * GNU Poke pickle for MVPD and V# keywords. 3 | * 4 | * Example usage: 5 | * 6 | * $ poke MVPD.noecc 7 | * (poke) .load mvpd.pk 8 | * (poke) var v = (Mvpd @ 0#B).get_record("LRP0").get_keyword("#V").as_voltage 9 | * (poke) v.buckets[0].sort_power_turbo 10 | * (poke) var b = (Mvpd @ 0#B).get_vbucket 11 | */ 12 | 13 | set_endian(ENDIAN_BIG); 14 | 15 | var MAX_QUADS = 6; 16 | var VOLTAGE_BUCKET_COUNT = 6; 17 | 18 | type VoltageData = struct { 19 | uint16 freq; // MHz 20 | uint16 vdd_voltage; 21 | uint16 idd_current; 22 | uint16 vcs_voltage; 23 | uint16 ics_current; 24 | }; 25 | 26 | /* Single bucket within #V keyword of version 3 */ 27 | type VoltageBucketv3 = struct { 28 | uint8 id; 29 | 30 | VoltageData nominal; 31 | VoltageData powersave; 32 | VoltageData turbo; 33 | VoltageData ultra_turbo; 34 | VoltageData powerbus; 35 | 36 | uint16 sort_power_normal; 37 | uint16 sort_power_turbo; 38 | 39 | uint8[6] reserved; 40 | }; 41 | 42 | type VoltageKwd = struct { 43 | uint8 version : version == 3; 44 | uint8[3] pnp; 45 | VoltageBucketv3[VOLTAGE_BUCKET_COUNT] buckets; 46 | }; 47 | 48 | type VpdKeyword = struct { 49 | char[2] name; 50 | 51 | uint8 size8 if name[0] != '#'; 52 | uint16 size16 if name[0] == '#'; 53 | var size = name[0] == '#' ? size16 : size8 as uint16; 54 | 55 | byte[size] data; 56 | 57 | method get_name = string : { 58 | return catos(name); 59 | } 60 | method get_size = uint16 : { 61 | return size; 62 | } 63 | method as_voltage = VoltageKwd : { 64 | return VoltageKwd @ data'offset; 65 | } 66 | }; 67 | 68 | type MvpdRecord = struct { 69 | uint16 size; 70 | VpdKeyword[] keywords; 71 | 72 | method get_keyword = (string name) VpdKeyword : { 73 | for (k in keywords) 74 | if (k.get_name == name) 75 | return k; 76 | 77 | raise E_inval; 78 | } 79 | }; 80 | 81 | type MvpdTocEntry = struct { 82 | char[4] name; // Name without trailing NUL byte 83 | little uint16 offset; // Offset from the beginning of partition in LE 84 | uint8[2] reserved; // Unused 85 | 86 | method get_name = string : { 87 | return catos(name); 88 | } 89 | 90 | method get_record = MvpdRecord : { 91 | return MvpdRecord @ offset#B; 92 | } 93 | }; 94 | 95 | type Mvpd = struct { 96 | MvpdTocEntry[32] toc; 97 | 98 | method get_record = (string name) MvpdRecord : { 99 | for (e in toc) { 100 | if (e.get_name == name) 101 | return e.get_record; 102 | } 103 | 104 | raise E_inval; 105 | } 106 | 107 | method get_vbucket = VoltageBucketv3 : { 108 | // Handling only the simplest cases here. 109 | 110 | var v = get_record("LRP0").get_keyword("#V").as_voltage; 111 | for (var i = 1; i < MAX_QUADS; ++i) { 112 | var lrp = catos([ 'L', 'R', 'P', ('0' + i) as char ]); 113 | var vv = get_record(lrp).get_keyword("#V").as_voltage; 114 | if (vv != v) { 115 | raise Exception { 116 | code = 255, 117 | msg = "#Vs aren't equal!" 118 | }; 119 | } 120 | } 121 | 122 | var valid = 0; 123 | var bucket = v.buckets[0]; 124 | for (var i = 0; i < VOLTAGE_BUCKET_COUNT; ++i) { 125 | if (v.buckets[i].nominal.freq != 0) { 126 | bucket = v.buckets[i]; 127 | ++valid; 128 | } 129 | } 130 | 131 | if (valid == 0) { 132 | raise Exception { 133 | code = 255, 134 | msg = "No bucket is valid!" 135 | }; 136 | } 137 | 138 | if (valid > 1) { 139 | raise Exception { 140 | code = 255, 141 | msg = "More than one bucket is valid!" 142 | }; 143 | } 144 | 145 | return bucket; 146 | } 147 | }; 148 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # openpower-coreboot-docs 2 | 3 | Documentation related to POWER9 coreboot porting effort. 4 | 5 | ## Introduction 6 | 7 | 3mdeb Embedded Systems Consulting is porting POWER9 architecture with Raptor 8 | Comupting Systems' Talos II and Talos II lite as reference platforms. The 9 | project has been initiated and is sponsored by Insurgo Technologies Libres/Open 10 | Technologies. The development process is open and anyone can join. See 11 | [How to help and contribute](#how-to-help-and-contribute) section. 12 | 13 | If you are interested in released coreboot images, check out the [releases](releases.md). 14 | 15 | To start working on the project, see the [project introduction](devnotes/documentation.md). 16 | 17 | ## Repository overview 18 | 19 | * [devnotes](devnotes/) - various developer notes created during the porting 20 | * [isteps_analysis.md](devnotes/isteps_analysis.md) - file containing 21 | a table of content for analysis of isteps/IPL flow 22 | * [logs](logs/) - a place to put important dumps and logs, which can be linked 23 | in the documents 24 | * [images](images/) - directory containins images linked in the documents 25 | 26 | ## Public documentation 27 | 28 | Various related documentation of OpenPOWER architecture, registers and 29 | programming guides: 30 | 31 | - [OpenPOWER 64bit ELF ABI](http://cdn.openpowerfoundation.org/wp-content/uploads/resources/leabi/leabi-20170510.pdf) 32 | - [OpenPOWER 64bit ELF ABI errata](http://cdn.openpowerfoundation.org/wp-content/uploads/resources/elfv2-1_4-errata-9/elfv2-1_4-errata-20180313.pdf) 33 | - [POWER9 IPL flow](https://wiki.raptorcs.com/w/images/b/bd/IPL-Flow-POWER9.pdf) 34 | - [OpenFSI specification](https://wiki.raptorcs.com/w/images/9/97/OpenFSI-spec-20161212.pdf) 35 | - [POWER9 processor programming model](https://ibm.ent.box.com/s/8qsbki409iq704wx5gvikz8h6fj8ixre) 36 | - [POWER9 Registers vol1](https://ibm.ent.box.com/s/ddcdl3g0otdzyiajhkfe3jjh2oy5p3mt) 37 | - [POWER9 Registers vol2](https://ibm.ent.box.com/s/gcg7o0sgke0cdqqw2z9pc9xc7zgjj1wu) 38 | - [POWER9 Registers vol3](https://ibm.ent.box.com/s/flt3hs6eiwd9glq3yzzff0flnup2j7p0) 39 | - [POWER ISA v3.0B](https://ibm.ent.box.com/s/1hzcwkwf8rbju5h9iyf44wm94amnlcrv) 40 | - [POWER9 processor errata](https://ibm.ent.box.com/s/0ixfserqjzjmt3q6vabotz9arxzs59md) 41 | - [Power9 PCIe Controller](https://ibm.box.com/s/07dfe69jbaavct70a642f0bhrqhlhgze) 42 | - [PHB4 Specification (PCIe related)](https://ibm.ent.box.com/s/jftnfhceul07qjh9jtn91xwjmclabc71) 43 | 44 | Other useful information extracted form documents aboive may be found in 45 | [ppc.md](devnotes/ppc.md). 46 | 47 | Also information about the porting process are included in 48 | [porting.md](devnotes/porting.md). 49 | 50 | ## How to help and contribute 51 | 52 | If you have Talos II or Talos II Lite simply joins forces with us. Everything 53 | is developed in open on 3mdeb's GitHub: 54 | 55 | - [coreboot](https://github.com/3mdeb/coreboot/tree/talos_2_support), use 56 | `talos_2_support` branch as base, create own branch and set up a PR 57 | - [pnor](https://github.com/3mdeb/pnor/tree/coreboot_support), use `coreboot` 58 | branch as a base, create own branch and set up a PR 59 | - [talos-op-build](https://github.com/3mdeb/talos-op-build/tree/coreboot_support), 60 | use `coreboot` branch as a base, create own branch and set up a PR 61 | - [op-docker](https://github.com/3mdeb/op-docker), dockerized environment to 62 | build full PNOR images for Talos II op-build, refer to its 63 | [README](https://github.com/3mdeb/op-docker/blob/main/README.md) to get 64 | details how to use it. Use own branches for `talos-op-build` to test your 65 | changes. Refer to [Implementing op-build support for coreboot](devnotes/porting.md#implementing-op-build-support-for-coreboot) 66 | to get details how to modify op-build to your needs. 67 | 68 | If you need another repo, let us know. 69 | 70 | **Do not have hardware?** No problem, we can arrange remote access to our 71 | development machine. Just [contact us](mailto:contact@3mdeb.com) to get 72 | details. 73 | 74 | **Do not have time to develop?** No problem. If you are knowledgeable about 75 | OpenPOWER and POWER9 architecture, feel free to use your knowledge to support 76 | us (e.g. through PR reviews). 77 | -------------------------------------------------------------------------------- /devnotes/hostboot-nest-chiplets.md: -------------------------------------------------------------------------------- 1 | # Step 8 Hostboot - Nest Chiplets 2 | ## 8.5 host_attnlisten_proc: Start attention poll for P9(s) 3 | * Enable hostboot to start including all processorattentions in its post istep analysis 4 | * Enable OCC to collect FIR data on all processors if master processor checkstops 5 | * From this point on ATTN/PRD will listen (“poll”) for powerbus attentions after each named istep 6 | 7 | ``` 8 | # src/include/usr/initservice/initserviceif.H:166 9 | # spBaseServicesEnabled() 10 | # 11 | # It is not clear where TARGETING::SpFunctions originates from 12 | sys = getTopLevelTarget() 13 | TARGETING::SpFunctions spfuncs 14 | # sys['spfuncs'] originates from 15 | # sys.tryGetAttr(spfuncs) 16 | if sys 17 | and sys['spfuncs'] 18 | and spfuncs.baseServices: 19 | # send_analyzable_procs() 20 | l_chipHuids = [] 21 | 22 | # get all functional Proc targets 23 | l_procsList = getAllChips(TYPE_PROC) 24 | 25 | # now fill in the list with proc huids 26 | for l_cpu_target in l_procList: 27 | l_chipHuids.push_back(TARGETING::get_huid(l_cpu_target)) 28 | 29 | # 30 | # send the message to alert ATTN to start monitoring these chips 31 | # 32 | 33 | msg_t myMsg 34 | # INITSERVICE::ATTN_MONITOR_CHIPID_LIST = 0x40000030 35 | myMsg.type = INITSERVICE::ATTN_MONITOR_CHIPID_LIST 36 | myMsg.data[0] = 0 37 | # Contains the full size of the extra_data field of myMsg 38 | # extra_data includes attn_chipid_msg + list of HUIDs. 39 | # attn_chipid_msg.data is the start of the huid list so 40 | # need to remove that variable's size from the total 41 | myMsg.data[1] = (sizeof(INITSERVICE::attn_chipid_msg) - sizeof(l_data_ptr.data)) 42 | + (sizeof(TARGETING::ATTR_HUID_type) * len(l_chipHuids)) 43 | # MBOX::alocate() 44 | # 45 | # MSGQ_RESOLVE_ROOT - defined in enum, probably compiled as 8 46 | # MSGQ_ROOT_VFS - defined in enum, probably compiled as 0 47 | msg_q_t vfsQ = syscall(MSGQ_RESOLVE_ROOT, MSGQ_ROOT_VFS) 48 | ##################################### 49 | msg_t msq_resolve_message 50 | msq_resolve_message.type = VFS_MSG_RESOLVE_MSGQ 51 | msq_resolve_message.extra_data = name 52 | # MSG_SENDRECV - defined in enum, compiles to 10 probably 53 | syscall(MSG_SENDRECV, vfsQ, msq_resolve_message, NULL) 54 | ##################################### 55 | msg_q_t mboxQ = msq_resolve_message.data[0] 56 | msg_t message_allocate 57 | # MSG_MBOX_ALLOCATE - defined in enum, compiles to 9 probably 58 | message_allocate.type = MSG_MBOX_ALLOCATE 59 | message_allocate.data[0] = i_size 60 | # MSG_SENDRECV - defined in enum, compiles to 10 probably 61 | syscall(MSG_SENDRECV, mboxQ, message_allocate, NULL) 62 | myMsg.extra_data = message_allocate.data[1] 63 | ##################################### 64 | l_data_ptr = myMsg.extra_data 65 | # total chip huid's in list 66 | l_data_ptr.chipIdCount = len(l_chipHuids) 67 | # data length in bytes of the list (sizeof(huid) * Number of huids) 68 | l_data_ptr.size = sizeof(TARGETING::ATTR_HUID_type) * len(l_chipHuids) 69 | # now fill in the list with huids 70 | # copy the memory 71 | l_data_ptr.data = copy(l_chipHuids) 72 | # send message to alert ATTN to start monitoring these chips 73 | # MBOX::sendrecv() 74 | # src/usr/mbox/mailboxsp.C:2327 75 | myMsg.__reserved__async = 1 76 | # MSGQ_RESOLVE_ROOT - defined in enum, compiles to 8 probably 77 | # MSGQ_ROOT_VFS - defined in enum, compiles to 0 probably 78 | msg_q_t vfsQ = syscall(MSGQ_RESOLVE_ROOT, MSGQ_ROOT_VFS) 79 | ##################################### 80 | msg_t msg_q_resolve 81 | # VFS_MSG_RESOLVE_MSGQ - Message to VFS_ROOT to find a message queue 82 | # defined in enum 83 | msg_q_resolve.type = VFS_MSG_RESOLVE_MSGQ 84 | msg_q_resolve.extra_data = "/msg/mbox" 85 | # MSG_SENDRECV - defined in enum 86 | syscall(MSG_SENDRECV, vfsQ, msg_q_resolve, NULL) 87 | ##################################### 88 | msg_t msg 89 | msg.type = MBOX::MSG_SEND 90 | # HWSVRQ = 0x80000008 91 | msg.data[0] = HWSVRQ 92 | msg.extra_data = myMsg # Payload message 93 | syscall(MBOX::MSG_SEND, msg_q_resolve.data[0], msg) 94 | ##################################### 95 | ``` 96 | -------------------------------------------------------------------------------- /devnotes/register_for_SCOM_tests.md: -------------------------------------------------------------------------------- 1 | # About this document 2 | This document presents a proposition of a register used for testing `SCOM` 3 | writing and reading. 4 | 5 | # Proposed registers 6 | 7 | ## TP.TPCHIP.PIB.PCBMS.DEVICE_ID_REG 8 | * SCOM address: 00000000000F000F 9 | * ID readout. 10 | **0:19 RO**: CFAM_CHIPID: This field is also known as cfam_chipid. 11 | **0 RO**: constant = 0b0 12 | **21:31 RO**: VENDOR_ID: The IBM ID is 0x49 13 | **32:35 RO**: constant = 0b0000 14 | **36:38 RW**: SOCKET_ID: Socket position \ 15 | Socket 0x0 is connected to the primary service element. \ 16 | Socket 0x1 is connected to the secondary service element (high end only). 17 | **39 RW**: CHIPPOS_ID: DCM position \ 18 | 0 = SCMs or the first chip on the DCM \ 19 | 1 = The second chip on the DCM (always a slave) 20 | **40 RO**: IO_TP_VSB_CHIP_POS 21 | **41:47 RO**: constant = 0b0000000 22 | **48 ROX**: FUSE_NX_ALLOW_CRYPTO: 1 = NX crypto-functionality is enabled (export regulation). 23 | **49 ROX**: FUSE_VMX_CRYPTO_DIS: 1 = VMX crypto-functionality is disabled (export regulation). 24 | **50 ROX**: FUSE_FP_THROTTLE_EN: 1 = Floating point is throttled (export regulation). 25 | **51 RO**: TP_NP_NVLINK_DISABLE: Indicates that NVLink is disabled. 26 | **52 RO**: FUSE_TOPOLOGY_2CHIP 27 | **53:54 RO**: FUSE_TOPOLOGY_GROUP 28 | **55:63 RO**: constant = 0b000000000 29 | 30 | ## NPU.STCK0.CS.CTL.MISC.CONFIG1 31 | * SCOM address: 0000000005011081 32 | * Future Configuration 1 Register. \ 33 | Currently a reserved register. \ 34 | IDIAL_CONFIG1: Future configuration register. 35 | 36 | ## VA.VA_NORTH.VA_RG.SCF.VAS_PMCNTL 37 | * SCOM address: 0000000003011830 38 | * Performance Monitor Control Register 39 | * This register is used to enable performance counter bits. \ 40 | **0:31 RW** PU_BIT_ENABLES: Each bit of this dial is used to enable 41 | the associated performance counter bit and send it to the PMU. \ 42 | **32:35 RW** PU_CNTL_UNUSED: Unused bits. \ 43 | **36:63 RO** constant = 0b0000000000000000000000000000 44 | 45 | ## TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCHBR 46 | * SCOM address: 000000000006C08F 47 | * OCB_OCI OCB OCC Heartbeat Register 48 | * **0:15 RW** OCB_OCI_OCCHBR_OCC_HEARTBEAT_COUNT: When written, this 49 | field defines the starting value for a counter that increments at about 50 | 1us if OCC_HEARTBEAT_EN = 1 and the counter value is non-zero. \ 51 | If OCC_HEARTBEAT_EN = 0 or the counter value is 0, the counter does 52 | not increment. \ 53 | If OCC_HEARTBEAT_EN = 1 and this counter becomes 0 (either from a written 54 | value or from the counter wrapping) constitutes the loss of the OCC 55 | heartbeat and surfaces an attention through TBD LFIR(TBD). 56 | The pulses used for this field come from a free running pervasive hang 57 | timer pulse (PM_Hang_Pulse) programmed to be ~ 32 ns that has a 58 | 5-bit precounter whose carryout forms a resultant ~ 1us decrement pulse. \ 59 | Upon writing this register with OCC_HEARTBEAT_EN = 1, the precounter is cleared 60 | and will begin counting upon the next PM_Hang_Pulse. This PM_Hang_Pulse might 61 | arrive immediately or a full duration later. With a (215)-1 range and an ~1 us 62 | incrementation time yields a heartbeat range of 1us (+0-32ns) (value 0xFFFF) 63 | to 65.535 ms (+0-32ns) (value 0x0001). The value chosen to be written for 64 | debug purposes only, writing 0x0000 causes an immediate heartbeat_lost 65 | if OCC_HEARTBEAT_EN = 1. Reads return the current value of the counter value.\ 66 | **16 RW** OCB_OCI_OCCHBR_OCC_HEARTBEAT_EN: OCC Heartbeat Timer Enable.\ 67 | **17:63 RO** constant = 0b00000000000000000000000000000000000000000000000 68 | * used in `src/import/chips/p9/procedures/hwp/pm/p9_pm_ocb_init.C:691` 69 | 70 | # Summary 71 | `TP.TPCHIP.PIB.PCBMS.DEVICE_ID_REG` Has non 0, partially known value after boot, so it is great for testing SCOM reads. \ 72 | `NPU.STCK0.CS.CTL.MISC.CONFIG1` According to the documentation it is currently unused, 73 | and can be written to and read from freely. \ 74 | `VA.VA_NORTH.VA_RG.SCF.VAS_PMCNTL` can be used for testing too. 75 | Part of the register can be read and written to freely. 76 | It is used to enable performance counters, 77 | so unpredicted side effects could occur. \ 78 | `TP.TPCHIP.OCC.OCI.OCB.OCB_OCI_OCCHBR` register is also a good fit for testing, 79 | but the value can change at any time. It has to be keept in mind while 80 | testing SCOM access. 81 | -------------------------------------------------------------------------------- /devnotes/isteps_analysis.md: -------------------------------------------------------------------------------- 1 | # Step 8 Hostboot - Nest Chiplets 2 | 3 | * [8.1 host_slave_sbe_config](isteps/8_nest_chiplets/1_host_slave_sbe_config.md) 4 | * [8.2 host_setup_sbe](isteps/8_nest_chiplets/2_host_setup_sbe.md) 5 | * [8.3 host_cbs_start](isteps/8_nest_chiplets/3_host_cbs_start.md) 6 | * [8.4 proc_check_slave_sbe_seeprom_complete: Check Slave SBE Complete](isteps/8_nest_chiplets/4_proc_check_slave_sbe_seeprom_compl.md) 7 | * [8.5 host_attnlisten_proc: Start attention poll for P9(s)](isteps/8_nest_chiplets/5_fabric_post_trainadv.md) 8 | * [8.6 host_p9_fbc_eff_config: Determine Powerbus config](isteps/8_nest_chiplets/6_host_p9_fbc_eff_config.md) 9 | * [8.7 host_p9_eff_config_links: Powerbuslinkconfig](isteps/8_nest_chiplets/7_host_p9_eff_config_links.md) 10 | * [8.8 proc_attr_update: Proc ATTR Update](isteps/8_nest_chiplets/8_proc_attr_update.md) 11 | * [8.9 proc_chiplet_scominit: Scom inits to all chiplets (sans Quad)](isteps/8_nest_chiplets/9_proc_chiplet_scominit.md) 12 | * [8.10 proc_xbus_scominit: Apply scom inits to Xbus](isteps/8_nest_chiplets/10_proc_xbus_scominit.md) 13 | * [8.11 proc_chiplet_enable_ridi: Enable RI/DI for xbus](isteps/8_nest_chiplets/11_proc_chiplet_enable_ridi.md) 14 | * [8.12 host_set_voltages: Enable RI/DI for xbus](isteps/8_nest_chiplets/12_host_set_voltages.md) 15 | 16 | # Step 9 Hostboot - EDI+ and Electrical O-Bus Initialization 17 | * [9.1 fabric_erepair: Restore Fabric Bus eRepair data](isteps/9_EDI_and_obus_init/1_fabric_erepair.md) 18 | * [9.2 fabric_io_dccal: Calibrate Fabric interfaces](isteps/9_EDI_and_obus_init/2_fabric_io_dccal.md) 19 | * [9.3 fabric_pre_trainadv: Advanced pre training](isteps/9_EDI_and_obus_init/3_fabric_pre_trainadv.md) 20 | * [9.4 fabric_io_run_training: Run training on internal buses](isteps/9_EDI_and_obus_init/4_fabric_io_run_training.md) 21 | * [9.5 fabric_post_trainadv: Advanced post EI/EDI training](isteps/9_EDI_and_obus_init/5_fabric_post_trainadv.md) 22 | * [9.6 proc_smp_link_layer: Start SMP link layer](isteps/9_EDI_and_obus_init/6_proc_smp_link_layer.md) 23 | * [9.7 proc_fab_iovalid: Lower functional fences on local SMP](isteps/9_EDI_and_obus_init/7_proc_fab_iovalid.md) 24 | * [9.8 host_fbc_eff_config_aggregate: Pick link(s) for coherency](isteps/9_EDI_and_obus_init/8_host_fbc_eff_config_aggregate.md) 25 | 26 | # Step 11 Hostboot - Centaur Init 27 | * [11.1 host_prd_hwreconfig](isteps/11_centaur_init/1_host_prd_hwreconfig.md) 28 | 29 | # Step 13 Hostboot - DRAM training 30 | * [13.1 host_disable_memvolt.md: Disable VDDR on Warm Reboots](isteps/13_dram_training/01_host_disable_memvolt.md) 31 | * [13.2 mem_pll_reset.md: Reset PLL for MCAs in async](isteps/13_dram_training/02_mem_pll_reset.md) 32 | * [13.3 mem_pll_initf.md: PLL Initfile for MBAs](isteps/13_dram_training/03_mem_pll_initf.md) 33 | * [13.4 mem_pll_setup.md: Setup PLL for MBAs](isteps/13_dram_training/04_mem_pll_setup.md) 34 | * [13.5 proc_mcs_skewadjust.md: Update clock mesh deskew](isteps/13_dram_training/05_proc_mcs_skewadjust.md) 35 | * [13.6 mem_startclocks.md: Start clocks on MBA/MCAs](isteps/13_dram_training/06_mem_startclocks.md) 36 | * [13.7 host_enable_memvolt.md: Enable the VDDR3 Voltage Rail](isteps/13_dram_training/07_host_enable_memvolt.md) 37 | * [13.8 mss_scominit.md: Perform scom inits to MC and PHY](isteps/13_dram_training/08_mss_scominit.md) 38 | * [13.9 mss_ddr_phy_reset.md: Soft reset of DDR PHY macros](isteps/13_dram_training/09_mss_ddr_phy_reset.md) 39 | * [13.10 mss_draminit.md: Dram initialize](isteps/13_dram_training/10_mss_draminit.md) 40 | * [13.11 mss_draminit_training.md: Dram training](isteps/13_dram_training/11_mss_draminit_training.md) 41 | * [13.12 mss_draminit_trainadv.md: Advanced dram training](isteps/13_dram_training/12_mss_draminit_trainadv.md) 42 | * [13.13 mss_draminit_mc.md: Hand off control to MC](isteps/13_dram_training/13_mss_draminit_mc.md) 43 | 44 | # Step 14 Hostboot - DRAM Init 45 | * [14.1 mss_memdiag: Mainstore Pattern Testing](isteps/14_DRAM_init/1_mss_memdiag.md) 46 | * [14.2 mss_thermal_init: Initialize the thermal sensor](isteps/14_DRAM_init/2_mss_thermal_init.md) 47 | * [14.3 proc_pcie_config: Configure the PHBs](isteps/14_DRAM_init/3_proc_pcie_config.md) 48 | * [14.4 mss_power_cleanup: Clean up any MCS/Centaurs](isteps/14_DRAM_init/4_mss_power_cleanup.md) 49 | * [14.5 proc_setup_bars: Setup Memory BARs](isteps/14_DRAM_init/5_proc_setups_bars.md) 50 | 51 | # Step 18 Establish System SMP & TOD 52 | * [18.11 proc_tod_setup](isteps/18_establish_system_SMP_and_TOD/11_proc_tod_setup.md) 53 | * [18.12 proc_tod_init](isteps/18_establish_system_SMP_and_TOD/12_proc_tod_init.md) 54 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_8_9_proc_chiplet_fabric_scominit.log: -------------------------------------------------------------------------------- 1 | 399.03876|ISTEP 8. 9 - proc_chiplet_fabric_scominit 2 | 399.04753|ISTEPS_TRACE|>>call_proc_chiplet_fabric_scominit entry 3 | 399.04755|ISTEPS_TRACE|>>fapiHWPCallWrapper (p9_chiplet_fabric_scominit) entry 4 | 399.04825|ISTEPS_TRACE|Running p9_chiplet_fabric_scominit HWP on target HUID 00050000 5 | 399.05817|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 000000000501180A 00088102A0000040 6 | 399.05820|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 000000000501180A 08087EFEA0000040 7 | 399.05823|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C0A 80088102A0000040 8 | 399.05827|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C0A 88087EFEA0000040 9 | 399.05830|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C26 0000000000000000 10 | 399.05833|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C26 0000000000000000 11 | 399.05836|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C27 0000000000000000 12 | 399.05839|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C27 0000000000000000 13 | 399.05842|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C28 0000000000000000 14 | 399.05845|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C28 0000000000000000 15 | 399.05848|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C29 0000000000000000 16 | 399.05852|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C29 0000000000000000 17 | 399.05855|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C2A 0000000000000000 18 | 399.05973|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C2A 0000000000000000 19 | 399.05977|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C2B 0000000000000000 20 | 399.05980|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005011C2B 0000000000000000 21 | 399.05983|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 000000000501200A 00088102A0000040 22 | 399.05987|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 000000000501200A 08087EFEA0000040 23 | 399.06109|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 000000000501340A 00E2030000E20000 24 | 399.06229|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 000000000501340A 00E20B4000E20840 25 | 399.06232|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 000000000501340B 00E2030000E20000 26 | 399.06235|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 000000000501340B 00E20B4000E20840 27 | 399.06238|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 000000000501340C 00E2030000E20000 28 | 399.06241|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 000000000501340C 00E20B4000E20840 29 | 399.06244|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005013410 403C3C80403C3C00 30 | 399.06247|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005013410 403C3C80403C3C00 31 | 399.06250|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005013411 403C3C80403C3C00 32 | 399.06253|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005013411 403C3C80403C3C00 33 | 399.06256|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005013412 403C3C80403C3C00 34 | 399.06259|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005013412 403C3C80403C3C00 35 | 399.06262|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005013423 F000000000000000 36 | 399.06265|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005013423 1000000000000000 37 | 399.06268|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005013424 0000000000000000 38 | 399.06271|SCAN|TRACE : PUTSCOM : pu:k0:n0:s0:p00 : 0000000005013424 0000000000000000 39 | 399.06307|SCAN|TRACE : GETSCOM : pu:k0:n0:s0:p00 : 0000000005011C00 0006000000000000 40 | 399.06312|SCAN|TRACE : GETSCOM : pu.xbus:k0:n0:s0:p00:c1 : 000000000601180A 00000000000227D0 41 | 399.06317|SCAN|TRACE : PUTSCOM : pu.xbus:k0:n0:s0:p00:c1 : 000000000601180A A80F000F000227D0 42 | 399.06321|SCAN|TRACE : GETSCOM : pu.xbus:k0:n0:s0:p00:c1 : 0000000006011818 0000000000000000 43 | 399.06326|SCAN|TRACE : PUTSCOM : pu.xbus:k0:n0:s0:p00:c1 : 0000000006011818 6FE0000000000000 44 | 399.06330|SCAN|TRACE : GETSCOM : pu.xbus:k0:n0:s0:p00:c1 : 0000000006011819 0000000000000000 45 | 399.06334|SCAN|TRACE : PUTSCOM : pu.xbus:k0:n0:s0:p00:c1 : 0000000006011819 7FE0000000000000 46 | 399.06370|ISTEPS_TRACE|SUCCESS: p9_chiplet_fabric_scominit HWP returned success with target HUID 0x00050000 47 | 399.06372|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 50 | 399.12592|ERRL|I>Flush message received 51 | 399.12594|INITSVC|<>doIstep: step 8, substep 10, task proc_xbus_scominit 53 | -------------------------------------------------------------------------------- /devnotes/poke/wof.pk: -------------------------------------------------------------------------------- 1 | /* 2 | * GNU Poke pickle for WOFDATA section of PNOR. 3 | * 4 | * Example usage: 5 | * 6 | * $ poke 7 | * (poke) .file WOF.noecc 8 | * (poke) .load wof.pk 9 | * (poke) var wof = WOF @ 0x1000#B 10 | * (poke) wof.find_match(4, b.sort_power_turbo, b.turbo.freq) 11 | * 12 | * // v is #V bucket from MVPD 13 | */ 14 | 15 | set_endian(ENDIAN_BIG); 16 | 17 | var MAX_QUADS_PER_CHIP = 6; 18 | var SYSTEM_VFRT_SIZE = 128#B; 19 | 20 | /* Data is provided in 1/24ths granularity with adjustments for integer representation */ 21 | var VFRT_VRATIO_SIZE = 24; 22 | /* 5 steps down from 100% is Fratio_step sizes */ 23 | var VFRT_FRATIO_SIZE = 5; 24 | 25 | /* Header of data within a WOF table */ 26 | type VfrtHdr = struct { 27 | uint16 magic_number = 0x5654H; // "VT" 28 | uint16 reserved; 29 | // bits 4-7 are type: 0 -- "System", 1 -- "Homer" 30 | // bits 0-3 are version: 1 -- 12 row(voltage) X 11 column(freq) 31 | // 2 -- 24 row(Voltage) X 5 column (Freq) 32 | uint8 type_version; 33 | uint8 res_vdnId; // Vdn assumptions 34 | uint8 vddId_QAId; // Vdd assumptions 35 | uint8 rsvd_QAId; // bits 0-2: Quad Active assumptions 36 | }; 37 | 38 | type VfrtEntry = struct { 39 | VfrtHdr hdr; 40 | uint8[VFRT_FRATIO_SIZE * VFRT_VRATIO_SIZE] freq; 41 | 42 | byte[alignto(OFFSET, SYSTEM_VFRT_SIZE)] padding; 43 | }; 44 | 45 | type WOFTableHdr = struct { 46 | uint32 magic_number : magic_number == 0x57465448; // "WFTH" 47 | 48 | uint16 reserved; 49 | uint8 mode; // version 1 = 0; version 2 = 1 or 2; WOF_MODE_* 50 | uint8 version : version == 1; 51 | 52 | uint16 vfrt_block_size; 53 | uint16 vfrt_block_header_size; 54 | uint16 vfrt_data_size; 55 | uint8 quads_active_size; 56 | uint8 core_count; 57 | uint16 vdn_start; // CeffVdn value represented by index 0 (in 0.01%) 58 | uint16 vdn_step; // CeffVdn step value for each CeffVdn index (in 0.01%) 59 | uint16 vdn_size; // Number of CeffVdn indexes 60 | uint16 vdd_start; // CeffVdd value represented by index 0 (in 0.01%) 61 | uint16 vdd_step; // CeffVdd step value for each CeffVdd index (in 0.01%) 62 | uint16 vdd_size; // Number of CeffVdd indexes 63 | uint16 vratio_start; // Vratio value represented by index 0 (in 0.01%) 64 | uint16 vratio_step; // Vratio step value for each CeffVdd index (in 0.01%) 65 | uint16 vratio_size; // Number of Vratio indexes 66 | uint16 fratio_start; // Fratio value represented by index 0 (in 0.01%) 67 | uint16 fratio_step; // Fratio step value for each CeffVdd index (in 0.01%) 68 | uint16 fratio_size; // Number of Fratio indexes 69 | 70 | uint16[8] vdn_percent; // Currently unused 71 | 72 | uint16 socket_power_w; 73 | uint16 nest_frequency_mhz; 74 | uint16 sort_power_freq_mhz; // Either the Nominal or Turbo #V frequency 75 | uint16 rdp_capacity; // Regulator Design Point Capacity (in Amps) 76 | 77 | char[8] wof_table_source_tag; 78 | char[16] package_name; 79 | }; 80 | 81 | type WOFTable = struct { 82 | WOFTableHdr hdr; 83 | VfrtEntry[hdr.vdn_size * hdr.vdd_size * MAX_QUADS_PER_CHIP] entries @ 128#B; 84 | }; 85 | 86 | type WOFEntry = struct { 87 | uint32 offset; // BE offset to section from image start 88 | uint32 size; // BE size of the section 89 | }; 90 | 91 | type WOF = struct { 92 | uint32 magic_number : magic_number == 0x57544948; // "WTIH"; 93 | uint8 version : version == 1; 94 | uint8 entry_count; // Number of entries in section table 95 | uint32 offset; // BE offset to section table from image start 96 | WOFEntry[entry_count] entries @ offset#B; 97 | 98 | method get_table = (int idx) WOFTable : { 99 | var addr = entries'offset - offset#B + entries[idx].offset#B; 100 | return WOFTable @ addr; 101 | } 102 | 103 | method find_match = (uint8 core_count, uint16 socket_power_w, uint16 sort_power_freq_mhz) WOFTable : { 104 | for (var i = 0; i < entries'length; ++i) { 105 | var t = get_table(i); 106 | 107 | printf("WOF Table #%u8d\n", i); 108 | printf(" core_count = %u8d\n", t.hdr.core_count); 109 | printf(" socket_power_w = %u16d\n", t.hdr.socket_power_w); 110 | printf(" sort_power_freq_mhz = %u16d\n", t.hdr.sort_power_freq_mhz); 111 | 112 | if (t.hdr.core_count != core_count) 113 | continue; 114 | if (t.hdr.socket_power_w != socket_power_w) 115 | continue; 116 | if (t.hdr.sort_power_freq_mhz != sort_power_freq_mhz) 117 | continue; 118 | return t; 119 | } 120 | 121 | raise Exception { code = 255, msg = "No suitable WOF table was found!" }; 122 | } 123 | }; 124 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_7_3_mss_freq.log: -------------------------------------------------------------------------------- 1 | 395.95045|ISTEP 7. 3 - mss_freq 2 | 395.95523|ISTEPS_TRACE|p9_mss_freq HWP target HUID 000b0000 3 | 396.00270|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 4 | 396.00319|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 5 | 396.12734|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 6 | 396.12786|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 7 | 396.25427|FAPI|nimbus_mss_freq.C: pu.mca:k0:n0:s0:p00:c1. VPD info - rank count for dimm_0: 1, dimm_1: 0 8 | 396.25429|FAPI|nimbus_mss_freq.C: VPD info - DDR frequency: 1866 MT/s 9 | 396.26992|VPD|>>DvpdFacade::checkForRecordOverride( MEMD, 0x000B0000 ) 10 | 396.26993|VPD|>>IpVpdFacade::getMEMDFromPNOR( 1, 000B0000 ) 11 | 396.26994|VPD|MEMD is at 0x822b3000 12 | 396.27923|VPD|MEMD Header 13 | ~[0x0000] 4f4b4f4b 30312e30 30312e30 00000015 *OKOK01.001.0....* 14 | ~[0x0010] 00013030 30303030 30303030 30303030 *..00000000000000* 15 | 396.31510|VPD|VPD VM = 599A26A0 16 | 396.31512|VPD|Attempting to read MEMD VM keyword from override 17 | 396.31515|VPD|Matching data was found in PNOR at 20. VM: PNOR=5DD846A0, VPD=599A26A0 18 | 396.31516|VPD|< Record MEMD for target 0x000B0000 exists at 0x822b3020 in PNOR 20 | 396.32771|FAPI|nimbus_mss_freq.C: pu.mca:k0:n0:s0:p00:c1. VPD info - rank count for dimm_0: 1, dimm_1: 0 21 | 396.32772|FAPI|nimbus_mss_freq.C: VPD info - DDR frequency: 2133 MT/s 22 | 396.32783|FAPI|nimbus_mss_freq.C: pu.mca:k0:n0:s0:p00:c1. VPD info - rank count for dimm_0: 1, dimm_1: 0 23 | 396.32784|FAPI|nimbus_mss_freq.C: VPD info - DDR frequency: 2400 MT/s 24 | 396.34116|FAPI|nimbus_mss_freq.C: pu.mca:k0:n0:s0:p00:c1. VPD info - rank count for dimm_0: 1, dimm_1: 0 25 | 396.34117|FAPI|nimbus_mss_freq.C: VPD info - DDR frequency: 2666 MT/s 26 | 396.34129|FAPI|sync.H: pu.mcbist:k0:n0:s0:p00:c0 is not in sync mode, skipping the sync mode check 27 | 396.35434|FAPI|mss_freq_scoreboard.H: pu.mca:k0:n0:s0:p00:c1 after processing MRW, max freq is 2666 28 | 396.35442|FAPI|mss_freq_scoreboard.H: pu.mca:k0:n0:s0:p00:c1 after processing VPD, max freq is 2666 29 | 396.35563|FAPI|mss_freq_scoreboard.H: pu.mca:k0:n0:s0:p00:c1 after processing SPD, max freq is 2666 30 | 396.35684|FAPI|gen_mss_freq.H: pu.mcbist:k0:n0:s0:p00:c0 supported freqs: 31 | 396.35686|FAPI|gen_mss_freq.H: pu.mcbist:k0:n0:s0:p00:c0 1866 32 | 396.35687|FAPI|gen_mss_freq.H: pu.mcbist:k0:n0:s0:p00:c0 2133 33 | 396.35689|FAPI|gen_mss_freq.H: pu.mcbist:k0:n0:s0:p00:c0 2400 34 | 396.35691|FAPI|gen_mss_freq.H: pu.mcbist:k0:n0:s0:p00:c0 2666 35 | 396.35854|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 36 | 396.35908|FAPI|spd_factory_pattern.C: Highest valid rev 0x11, Highest valid encoding level 1, encoding level received 1 for dimm:k0:n0:s0:p02 37 | 396.37667|FAPI|spd_decoder_ddr4.H: dimm:k0:n0:s0:p02. CAS latencies supported (bitmap): 0x1FFF8 38 | 396.37674|FAPI|cas_latency.H: Largest tAAmin (ps): 13750, tCKmin (ps): 750, and supported CL bitmap 0x1FFF8 for all modules across pu.mca:k0:n0:s0:p00:c1 39 | 396.37682|FAPI|nimbus_mss_freq.C: Final Chosen CL: 19 for pu.mca:k0:n0:s0:p00:c1 40 | 396.37688|FAPI|gen_mss_freq.H: Final Chosen Frequency: 2666 (pu.mcbist:k0:n0:s0:p00:c0) 41 | 396.40335|FAPI|freq_workarounds.C: pu.mcbist:k0:n0:s0:p00:c0 Checking the MEM to NEST frequency ratio versus the allowed limit 42 | 396.40337|FAPI|freq_workarounds.C: l_ratio = 1.4287245444801715, max_ratio = 1.5 43 | 396.40339|ISTEPS_TRACE|SUCCESS : p9_mss_freq HWP 44 | 396.40341|UTIL|getBootNestFreq::The boot frequency was 1866: Bucket Id = 2 45 | 396.41532|SBE|>>Enter getBootMcSyncMode() 46 | 396.41533|SBE|The MC Sync Bit is 0 47 | 396.41608|ISTEPS_TRACE|START : running mss_freq_system HWP 48 | 396.41610|FAPI|p9_mss_freq_system.C: ----- In p9_mss_freq_system ---- 49 | 396.41617|FAPI|p9_mss_freq_system.C: Retrieved req'd sync mode: 2 and nest freq 1866 50 | 396.41618|FAPI|sync.C: ---- In dimm_speed_pairs ---- 51 | 396.41621|FAPI|p9_mss_freq_system.C: Dimm speed for all MCBISTs are the same : true 52 | 396.41622|FAPI|sync.C: ---- In select_sync_mode ---- 53 | 396.41625|FAPI|p9_mss_freq_system.C: Selected SYNC mode : MC NOT in sync 54 | 396.41628|FAPI|p9_mss_freq_system.C: pu.mcbist:k0:n0:s0:p00:c0: Setting ATTR_MC_SYNC_MODE to 0 55 | 396.41629|ISTEPS_TRACE|SUCCESS : mss_freq_system HWP 56 | 396.41631|ISTEPS_TRACE|call_mss_freq exit 57 | 396.44341|ERRL|I>Got an error log Msg - Type: 0x00000039 58 | 396.44343|ERRL|I>Flush message received 59 | 396.44345|INITSVC|<>doIstep: step 7, substep 4, task mss_eff_config 61 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_13_2_mem_pll_reset.log: -------------------------------------------------------------------------------- 1 | 435.94426|ISTEP 13. 2 - mem_pll_reset 2 | 435.95888|ISTEPS_TRACE|call_mem_pll_reset entry 3 | 435.95960|ISTEPS_TRACE|Running p9_mem_pll_reset HWP on target HUID 00050000 4 | 435.98958|FAPI|p9_mem_pll_reset.C: Entering ... 5 | 436.00276|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0042 4000000000000000 6 | 436.00281|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F001E 0374000000000000 7 | 436.00285|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F001E 037C000000000000 8 | 436.00289|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0042 0400000000000000 9 | 436.00293|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0042 0800000000000000 10 | 436.00297|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0042 1000000000000000 11 | 436.00301|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0046 6000000000000000 12 | 436.00305|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 00000000000F0041 BFFFFFFFFFFFFFFF 13 | 436.00310|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030000 0000000000000000 14 | 436.00314|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030000 0800000000000000 15 | 436.00318|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030001 5000000000000020 16 | 436.00323|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030006 000200000000E000 17 | 436.00328|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030005 0002000000000080 18 | 436.00332|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030002 0000000000000000 19 | 436.00336|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030002 0000000000000000 20 | 436.00340|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030002 2000000000000000 21 | 436.00345|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000000100 0040000000000000 22 | 436.00351|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000000100 0040000000000000 23 | 436.00357|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000000100 00C0000000000000 24 | 436.00362|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030006 0000000000000000 25 | 436.00366|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c7 : 0000000000030005 0000000000000000 26 | 436.00371|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0042 4000000000000000 27 | 436.00376|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F001E 0374000000000000 28 | 436.00380|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F001E 037C000000000000 29 | 436.00384|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0042 0400000000000000 30 | 436.00389|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0042 0800000000000000 31 | 436.00393|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0042 1000000000000000 32 | 436.00398|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0046 6000000000000000 33 | 436.00402|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 00000000000F0041 BFFFFFFFFFFFFFFF 34 | 436.00407|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030000 0000000000000000 35 | 436.00411|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030000 0800000000000000 36 | 436.00416|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030001 5000000000000020 37 | 436.00421|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030006 000200000000E000 38 | 436.00425|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030005 0002000000000080 39 | 436.00430|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030002 0000000000000000 40 | 436.00434|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030002 0000000000000000 41 | 436.00439|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030002 2000000000000000 42 | 436.00444|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000000100 0040000000000000 43 | 436.00450|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000000100 0040000000000000 44 | 436.00458|SCAN|TRACE : GETSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000000100 00C0000000000000 45 | 436.00462|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030006 0000000000000000 46 | 436.00466|SCAN|TRACE : PUTSCOM : pu.perv:k0:n0:s0:p00:c8 : 0000000000030005 0000000000000000 47 | 436.00468|FAPI|p9_mem_pll_reset.C: Exiting ... 48 | 436.00470|ISTEPS_TRACE|SUCCESS running p9_mem_pll_reset HWP on target HUID 00050000 49 | 436.00471|ISTEPS_TRACE|call_mem_pll_reset exit 50 | 436.08168|SCOM|doMulticastWorkaround on 00050000 for 50040018 51 | 436.08219|SCOM|doMulticastWorkaround on 00050000 for 50040009 52 | 436.08281|ERRL|I>Got an error log Msg - Type: 0x00000039 53 | 436.08282|ERRL|I>Flush message received 54 | 436.08284|INITSVC|<>doIstep: step 13, substep 3, task mem_pll_initf 56 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_16_1_host_activate_master.log: -------------------------------------------------------------------------------- 1 | 475.64471|ISTEP 16. 1 - host_activate_master 2 | 475.65236|INITSVC|unloading [libistep15.so] 3 | 475.65255|INITSVC|unloading [libp9_stop_util.so] 4 | 475.65265|INITSVC|unloading [libnestmemutils.so] 5 | 475.65276|INITSVC|unloading [libp9_cpuWkup.so] 6 | 475.65288|INITSVC|unloading [libpm.so] 7 | 475.65349|INITSVC|unloading [libimageprocs.so] 8 | 475.65393|INITSVC|unloading [libisteps_mss.so] 9 | 475.66561|INITSVC|loading [libistep16.so] 10 | 475.67173|INITSVC|loading [libnestmemutils.so] 11 | 475.67186|INITSVC|loading [libp9_cpuWkup.so] 12 | 475.67201|INITSVC|loading [libisteps_mss.so] 13 | 475.68403|INITSVC|loading [libpm.so] 14 | 475.68448|INITSVC|loading [libimageprocs.so] 15 | 475.68463|INITSVC|loading [libisteps_nest.so] 16 | 475.72123|ISTEPS_TRACE|call_host_activate_master entry 17 | 475.74407|TARG|getMasterCore: found 4 cores on master proc,l_masterCore PIR:0x4 18 | 475.74409|TARG|found master core: 0x1, PIR=0x4 : 19 | 475.75025|TARG|EntityPath 20 | ~[0x0000] 50687973 6963616c 3a2f5379 73302f4e *Physical:/Sys0/N* 21 | ~[0x0010] 6f646530 2f50726f 63302f45 51302f45 *ode0/Proc0/EQ0/E* 22 | ~[0x0020] 58302f43 6f726531 *X0/Core1 * 23 | 475.78500|MBOX|I>MailboxSp::_reclaimDmaBfrsFromFsp - Start. DmaBuffer = 24 | ~[0x0000] 00000000 00821000 00000000 f8821000 *................* 25 | ~[0x0010] ffffffff ffffffff 00000000 00000000 *................* 26 | ~[0x0020] 00000000 00000000 00000000 00000000 *................* 27 | ~[0x0030] 00000000 00000000 *........ * 28 | 475.78807|MBOX|I>MBOXSP Ignored request to suspend a disabled mailbox 29 | 475.80598|ISTEPS_TRACE|call_host_activate_master: About to start deadman loop... Target HUID 00050000 30 | 475.83485|SBEIO|psudd: Sending Req = 00000000000AD101 0000000000002904 0000000000000000 0000000000000000 to 00050000 31 | 475.83493|INTR|IntrRp::msgHandler() - LSI Interrupt Detected 32 | 475.83495|INTR|IntrRp::msgHandler() lsiIntStatus 0x0004000000000000 33 | 475.83498|INTR|IntrRp::msgHandler() External Interrupt found for pir: 0x0,interrupt type: 13 34 | 475.83535|SBEIO|psudd: SbePsu::msgHandler got MSG_INTR message 35 | 475.83555|INTR|IntrRp::completeInterruptProcessing() Removing pending interrupt for pir: 0x0,interrupt type: 13 36 | 475.83635|ISTEPS_TRACE|startDeadManLoop SUCCESS 37 | 475.83636|ISTEPS_TRACE|draining interrupt Q 38 | 475.83639|ISTEPS_TRACE|call_host_activated_master: call p9_block_wakeup_intr(SET) Target HUID 00070001 39 | 475.87235|FAPI|p9_block_wakeup_intr.C: > p9_block_wakeup_intr... 40 | 475.87240|SCAN|TRACE : GETSCOM : pu.core:k0:n0:s0:p00:c1 : 00000000200F0106 3822000000000000 41 | 475.87245|SCAN|TRACE : GETSCOM : pu.core:k0:n0:s0:p00:c1 : 00000000200F0100 0011000000000000 42 | 475.87247|FAPI|p9_block_wakeup_intr.C: Set the CPPM PPM Write Override 43 | 475.87251|SCAN|TRACE : PUTSCOM : pu.core:k0:n0:s0:p00:c1 : 00000000200F0108 4000000000000000 44 | 475.87254|FAPI|p9_block_wakeup_intr.C: Setting GPMMR[Block Interrupt Sources] on Core 1 45 | 475.87258|SCAN|TRACE : PUTSCOM : pu.core:k0:n0:s0:p00:c1 : 00000000200F0102 0200000000000000 46 | 475.87260|FAPI|p9_block_wakeup_intr.C: Clear the CPPM PPM Write Override 47 | 475.87264|SCAN|TRACE : PUTSCOM : pu.core:k0:n0:s0:p00:c1 : 00000000200F0107 4000000000000000 48 | 475.87266|FAPI|p9_block_wakeup_intr.C: < p9_block_wakeup_intr... 49 | 475.87267|ISTEPS_TRACE|p9_block_wakeup_intr SUCCESS 50 | 475.87269|ISTEPS_TRACE|call_host_activate_master: put master into winkle... 51 | 476.90689|ISTEPS_TRACE|Returned from Winkle. 52 | 476.90690|INTR|IntrRp::msgHandler() - LSI Interrupt Detected 53 | 476.90691|INTR|IntrRp::msgHandler() lsiIntStatus 0x0004000000000000 54 | 476.90693|INTR|IntrRp::msgHandler() External Interrupt found for pir: 0x0,interrupt type: 13 55 | 476.90693|SBEIO|psudd: Sending Req = 00000000000BD101 0000000000000000 0000000000000000 0000000000000000 to 00050000 56 | 476.90697|SBEIO|psudd: SbePsu::msgHandler got MSG_INTR message 57 | 476.90714|INTR|IntrRp::completeInterruptProcessing() Removing pending interrupt for pir: 0x0,interrupt type: 13 58 | 476.90716|ISTEPS_TRACE|stopDeadmanLoop SUCCESS 59 | 476.90718|ISTEPS_TRACE|Call proc_stop_deadman_timer. Target 00050000 60 | 476.90719|MBOX|I>Mailbox function resumed 61 | 476.92749|ISTEPS_TRACE|>>core_checkstop_helper_hwp 62 | 476.92752|FAPI|p9_core_checkstop_handler.C: Entering ... 63 | 476.92757|SCAN|TRACE : GETSCOM : pu.core:k0:n0:s0:p00:c1 : 0000000020010A46 0000000000000000 64 | 476.92764|SCAN|TRACE : GETSCOM : pu.core:k0:n0:s0:p00:c1 : 0000000020010A47 A854009775100000 65 | 476.92767|SCAN|TRACE : PUTSCOM : pu.core:k0:n0:s0:p00:c1 : 0000000020010A46 0000000000000000 66 | 476.92771|SCAN|TRACE : PUTSCOM : pu.core:k0:n0:s0:p00:c1 : 0000000020010A47 A854009775100000 67 | 476.92772|FAPI|p9_core_checkstop_handler.C: Exiting ... 68 | 476.95461|ISTEPS_TRACE|<>core_checkstop_helper_homer 70 | 476.95526|ISTEPS_TRACE|convertHomerPhysToVirt: phys_addr=0x1FD800000, virt_addr=0x23800000000 71 | 476.95534|ISTEPS_TRACE|<Got an error log Msg - Type: 0x00000039 74 | 476.96005|ERRL|I>Flush message received 75 | 476.96007|INITSVC|<>doIstep: step 16, substep 2, task host_activate_slave_cores 77 | -------------------------------------------------------------------------------- /devnotes/tpm_over_i2c.md: -------------------------------------------------------------------------------- 1 | This document is about TPM chips with I2C interface, their availability, 2 | documentation, drivers and other relevant sources that could help in supporting 3 | I2C TPM on Talos. 4 | 5 | ## Known I2C chips 6 | 7 | * Nuvoton (problematic to buy, if possible at all) 8 | * `NPCT650` 9 | * [Linux driver](https://elixir.bootlin.com/linux/latest/source/drivers/char/tpm/tpm_i2c_nuvoton.c) 10 | * `NPCT750` 11 | * [Linux driver patches](https://github.com/Nuvoton-Israel/tpm_i2c_ptp) 12 | * [in Hostboot](https://github.com/open-power/hostboot/blob/master/src/usr/i2c/tpmdd.C#L1667) 13 | * [in skiboot](https://github.com/open-power/skiboot/blob/master/libstb/drivers/tpm_i2c_nuvoton.c) (650 only?) 14 | 15 | * ST (problematic to buy) 16 | * `ST33TPHF20I2C` (TPM 2.0) 17 | * [product](https://www.st.com/en/secure-mcus/st33tphf20i2c.html) 18 | * [datasheet](https://www.alldatasheet.com/datasheet-pdf/pdf/1179026/STMICROELECTRONICS/ST33TPHF20I2C.html) 19 | * [data brief](https://www.st.com/resource/en/data_brief/st33tphf20i2c.pdf) 20 | * `ST33TPHF2XI2C` (TPM 2.0) 21 | * [product](https://www.st.com/en/secure-mcus/st33tphf2xi2c.html) 22 | * [data brief](https://www.st.com/resource/en/data_brief/st33tphf2xi2c.pdf) 23 | * `ST33TPHF2EI2C` (TPM 1.2 & TPM 2.0) 24 | * [product](https://www.st.com/en/secure-mcus/st33tphf2ei2c.html) 25 | * [data brief](https://www.st.com/resource/en/data_brief/st33tphf2ei2c.pdf) 26 | * `ST33GTPMAI2C` (TPM 2.0) 27 | * [product](https://www.st.com/en/secure-mcus/st33gtpmai2c.html) 28 | * [data brief](https://www.st.com/resource/en/data_brief/st33gtpmai2c.pdf) 29 | * `ST33GTPMII2C` (TPM 2.0) 30 | * [product](https://www.st.com/en/secure-mcus/st33gtpmii2c.html) 31 | * [data brief](https://www.st.com/resource/en/data_brief/st33gtpmii2c.pdf) 32 | * `ST33TPM12I2C` (TPM 1.2) 33 | * [product](https://www.st.com/en/secure-mcus/st33tpm12i2c.html) 34 | * [data brief](https://www.st.com/resource/en/data_brief/st33tpm12i2c.pdf) 35 | * [Linux driver patches](https://github.com/STMicroelectronics/TCG-TPM-I2C-DRV) 36 | * [some other Linux driver upstream](https://elixir.bootlin.com/linux/latest/source/drivers/char/tpm/st33zp24) 37 | 38 | * Atmel (available in multiple stores) 39 | * `AT97SC3205T` (TPM 1.2) 40 | * [datasheet](https://datasheet.datasheetarchive.com/originals/dk/DKDS-15/281773.pdf) 41 | * [store search](https://www.findchips.com/search/AT97SC3205T-H3M4C-00) 42 | * [store](https://eu.mouser.com/c/?q=AT97SC3205T&instock=y) 43 | * [Linux driver](https://elixir.bootlin.com/linux/latest/source/drivers/char/tpm/tpm_i2c_atmel.c) 44 | 45 | * Infineon (available in one store) 46 | * SLB 9645TT1.2 (TPM 1.2) 47 | * [product](https://www.infineon.com/cms/en/product/security-smart-card-solutions/optiga-embedded-security-solutions/optiga-tpm/slb-9645tt1.2/) 48 | * [datasheet](https://www.infineon.com/dgdl/Infineon-Data-sheet-SLB9645_1.2_Rev1.2-DS-v01_02-EN.pdf?fileId=5546d462689a790c016929d1c4074fdf) 49 | * [store](https://www.arrow.com/en/products/slb9645vq12fw13332xuma2/infineon-technologies-ag) 50 | * [Linux driver](https://elixir.bootlin.com/linux/latest/source/drivers/char/tpm/tpm_i2c_infineon.c) 51 | 52 | ## Implementation efforts 53 | 54 | ### coreboot driver 55 | 56 | coreboot already has drivers for two kinds of chips from above: 57 | * [Atmel I2C chips](https://github.com/coreboot/coreboot/blob/master/src/drivers/i2c/tpm/tis_atmel.c) 58 | * [Infineon I2C chips](https://github.com/coreboot/coreboot/blob/master/src/drivers/i2c/tpm/tpm.c) 59 | 60 | Drivers for Nuvoton or ST33 could be derived from Linux sources if needed. 61 | 62 | ### Linux driver 63 | 64 | Drivers for Atmel, Infineon and NPCT650 are in upstream Linux. NPCT750 driver 65 | is available as a set of patches for v5.6 66 | 67 | Driver for ST33 is available as a patch for v5.4.83 68 | 69 | ### coreboot DT 70 | 71 | TPM should be added to device tree in a way compatible with skiboot and Linux. 72 | 73 | ### skiboot driver 74 | 75 | Looks like only `NPCT650` is supported. 76 | 77 | Drivers for other TPMs can be derived from coreboot or Linux drivers. 78 | 79 | ### Existing drivers 80 | 81 | The smallest drivers are for Atmel: coreboot ~100 lines, Linux ~200 lines. 82 | 83 | Drivers for Infineon are ~600 lines in coreboot and ~750 in Linux (coreboot 84 | driver derived from the Linux driver). 85 | 86 | Linux driver for Nuvoton is ~700 lines. 87 | 88 | Linux driver for ST is ~300 lines. 89 | 90 | Drivers like these are copied between projects and adapted, sometimes one device 91 | driver is derived from the other explicitly. This likely means that it won't be 92 | a major task to make a missing driver for chips whose documentation is 93 | available and is clear enough. 94 | 95 | Implementations seem to be centered around transfer functions, which implement 96 | send and receive operations on registers. 97 | 98 | ### Other potentially relevant sources 99 | 100 | [wolfTPM](https://github.com/wolfSSL/wolfTPM) seems to implement drivers in 101 | userspace using I2C devices exposed through `devfs`. 102 | 103 | There are also QEMU patches for 104 | [Atmel I2C TPM AT97SC3204T](https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg04484.html). 105 | 106 | "If you have a TPM security chip which is connected to a regular, non-tcg I2C 107 | master (i.e. most embedded platforms)" (not sure if applicable): 108 | * [old attempt](https://sourceforge.net/p/tpmdd/mailman/tpmdd-devel/thread/1458502483-16887-13-git-send-email-christophe-h.ricard%40st.com/#msg34951208) 109 | * [recent try](https://lkml.org/lkml/2022/4/7/485) 110 | -------------------------------------------------------------------------------- /devnotes/ipmi_sensors.md: -------------------------------------------------------------------------------- 1 | # IPMI sensor types 2 | 3 | Based on [talos.xml](https://git.raptorcs.com/git/talos-xml/plain/talos.xml), 4 | sorted by `reg` of `/bmc/sensors/sensor@...` nodes: 5 | 6 | `reg` | Name in talos.xml | IPMI sensor type | Notes 7 | ---------|------------------------------|------------------|------ 8 | 0x01 | `host_status_sensor` | 0x22 | 9 | 0x02 | `fw_boot_sensor` | 0x0F | 10 | 0x03-0x04| `occ_active_sensor` | 0x07 | One per CPU, only if CPU is installed 11 | 0x05 | not used | | 12 | 0x06-0x07| `cpu_temp_sensor` | 0x01 | One per CPU, only if CPU is installed 13 | 0x08-0x09| `cpu_func_sensor` | 0x07 | One per CPU, only if CPU is installed 14 | 0x0A | `dimm_freq_sensor` | 0xC1 | Only one (does it limit DIMM population rules?) 15 | 0x0B-0x1A| `dimm_func_sensor` | 0x0C | One per DIMM, `reg`s for empty slots are skipped 16 | 0x1B-0x2A| `dimm_temp_sensor` | 0x01 | One per DIMM, `reg`s for empty slots are skipped 17 | 0x2B-0x5A| `cpucore_func_sensor` | 0x07 | One per core, not filled by Hostboot 18 | 0x5B-0x8A| `cpucore_temp_sensor` | 0x01 | One per core, not filled by Hostboot 19 | 0x8B | `boot_count_sensor` | 0xC3 | 20 | 0x8C | `motherboard_fault_sensor` | 0xC7 | 21 | 0x8D | `ref_clk_sensor` | 0xC7 | 22 | 0x8E | `pci_clk_sensor` | 0xC7 | 23 | 0x8F | `tod_clk_sensor` | 0xC7 | 24 | 0x90 | `system_event_sensor` | 0x12 | 25 | 0x91 | `os_boot_sensor` | 0x1F | 26 | 0x92 | `pci_link_sensor` | 0xC4 | 27 | 0x93 | `apss_fault_sensor` | 0xC7 | 28 | 0x94 | `power_cap_sensor` | 0xC2 | 29 | 0x95 | `ps_redundancy_state_sensor` | 0xCA | 30 | 0x96 | `ps_derating_sensor` | 0xC8 | 31 | 0x97 | `power_limit_sensor` | 0xC6 | 32 | 0x98-0x9F| not used | | 33 | 0xA0-0xCF| `cpucore_freq_sensor` | 0xC1 | One per core, not filled by Hostboot 34 | 0xD0-0xFF| not used | | 35 | 36 | # Sensors in Hostboot 37 | 38 | Targets with IPMI sensors have `ATTR_IPMI_SENSORS` attribute. 39 | 40 | `ATTR_IPMI_SENSORS` is a fixed-size array of type `uint16_t[16][2]`. Single 41 | array entry consists of a sensor name and its IPMI number. IPMI number is 42 | just one byte, which makes it easy to read value of the attribute. Entries of 43 | the array are sorted by sensor name and are looked up via binary search. 44 | Unused entries look like `0xFFFF, 0xFF` and are thus located at the end of the 45 | array. 46 | 47 | Sensor name looks like `0xAABB` where `AA` is its major type and `BB` its minor 48 | type. Minor type (also called sub-type) corresponds to entity ID in IPMI 49 | specification. 50 | 51 | From `obj/genfiles/attributeenums.H`: 52 | 53 | ```cpp 54 | /** 55 | * @brief Enumeration defining the offsets into the IPMI_SENSORS array. 56 | */ 57 | enum IPMI_SENSOR_ARRAY 58 | { 59 | IPMI_SENSOR_ARRAY_NAME_OFFSET = 0x00000000, 60 | IPMI_SENSOR_ARRAY_NUMBER_OFFSET = 0x00000001, 61 | }; 62 | 63 | /** 64 | * @brief Enumeration indicating the IPMI sensor name, which will be used 65 | * by hostboot when determining the sensor number to return. The 66 | * sensor name consists of one byte of sensor type plus one byte of 67 | * sub-type, to differentiate similar sensors under the same target. 68 | * Our implementaion uses the IPMI defined entity ID as the sub-type. 69 | */ 70 | enum SENSOR_NAME 71 | { 72 | SENSOR_NAME_PROC_TEMP = 0x00000103, 73 | SENSOR_NAME_DIMM_TEMP = 0x00000120, 74 | SENSOR_NAME_CORE_TEMP = 0x000001D0, 75 | SENSOR_NAME_STATE = 0x00000500, 76 | SENSOR_NAME_MEMBUF_TEMP = 0x000001D1, 77 | SENSOR_NAME_GPU_TEMP = 0x000001D8, 78 | SENSOR_NAME_GPU_MEM_TEMP = 0x000001D9, 79 | SENSOR_NAME_VRM_VDD_TEMP = 0x000001DA, 80 | SENSOR_NAME_GPU_STATE = 0x000017D8, 81 | SENSOR_NAME_PROC_STATE = 0x00000703, 82 | SENSOR_NAME_CORE_STATE = 0x000007D0, 83 | SENSOR_NAME_HOST_AUTO_REBOOT_CONTROL = 0x00000921, 84 | SENSOR_NAME_DIMM_STATE = 0x00000C20, 85 | SENSOR_NAME_HB_VOLATILE = 0x00000C21, 86 | SENSOR_NAME_MEMBUF_STATE = 0x00000CD1, 87 | SENSOR_NAME_FW_BOOT_PROGRESS = 0x00000F22, 88 | SENSOR_NAME_SYSTEM_EVENT = 0x00001201, 89 | SENSOR_NAME_OS_BOOT = 0x00001F23, 90 | SENSOR_NAME_HOST_STATUS = 0x00002223, 91 | SENSOR_NAME_OCC_ACTIVE = 0x000007D2, 92 | SENSOR_NAME_CORE_FREQ = 0x0000C1D0, 93 | SENSOR_NAME_APSS_CHANNEL = 0x0000C2D7, 94 | SENSOR_NAME_PCI_ACTIVE = 0x0000C423, 95 | SENSOR_NAME_REBOOT_COUNT = 0x0000C322, 96 | SENSOR_NAME_FAULT = 0x0000C700, 97 | SENSOR_NAME_BACKPLANE_FAULT = 0x0000C707, 98 | SENSOR_NAME_REF_CLOCK_FAULT = 0x0000C7D4, 99 | SENSOR_NAME_PCI_CLOCK_FAULT = 0x0000C7D5, 100 | SENSOR_NAME_TOD_CLOCK_FAULT = 0x0000C7D6, 101 | SENSOR_NAME_APSS_FAULT = 0x0000C7D7, 102 | SENSOR_NAME_VRM_VDD_FAULT = 0x0000C707, 103 | SENSOR_NAME_DERATING_FACTOR = 0x0000C815, 104 | SENSOR_NAME_REDUNDANT_PS_POLICY = 0x0000CA22, 105 | SENSOR_NAME_TURBO_ALLOWED = 0x0000CB03, 106 | SENSOR_NAME_TPM_REQUIRED = 0x0000CC03, 107 | SENSOR_NAME_PCI_BIFURCATED = 0x0000CD03, 108 | }; 109 | ``` 110 | -------------------------------------------------------------------------------- /logs/scom_dumps/istep_6_5_host_init_fsi.log: -------------------------------------------------------------------------------- 1 | 6.47014|ISTEP 6. 5 - host_init_fsi 2 | 6.47668|INITSVC|loading [libistep06.so] 3 | 6.51423|INITSVC|loading [libsbe.so] 4 | 6.52940|INITSVC|loading [libpm.so] 5 | 6.64288|INITSVC|loading [libnestmemutils.so] 6 | 6.75324|INITSVC|loading [libimageprocs.so] 7 | 6.77520|INITSVC|loading [libp9_cpuWkup.so] 8 | 6.78604|INITSVC|loading [libisteps_nest.so] 9 | 6.81840|IPMI|rp: queuing async 10:30 10 | 6.81846|IPMI|rp: W>Got message (0x10:0x30): l_is_pnor: 0 11 | 6.81854|IPMI|dd: I>write ok 10:30 seq c9 len a 12 | 6.82898|IPMI|dd: I>read b2h ok 14:30 seq c9 len 0 cc 0 13 | 6.84961|FSI|FsiDD::FsiDD()> 14 | 6.84962|FSI|Master=00050000 15 | 6.84964|FSI|FSI::initializeHardware> 16 | 6.84965|FSI|Master = 00050000 : alt=0 17 | 6.84984|FSI|PIB2OPB Status (00050000->00020001) after cleanup = 0000000000000000 18 | 6.85101|FSI|>>FsiDD::initMasterControl> Initializing Master 00050000:H 19 | 6.85716|FSI|FsiDD::initMasterControl> 00050000:H : Slave Detect = 00000000 20 | 6.85953|FSI|>>FsiDD::initMasterControl> Initializing Master 00050000:C 21 | 6.86069|FSI|FsiDD::initMasterControl> 00050000:C : Slave Detect = 00000000 22 | 6.88192|I2C|>>i2cResetActiveMasters(): i2cProcessType=0xF, i_functional=0, i_engineSelect=0xF0 23 | 6.88196|I2C|>>i2cProcessActiveMasters(): Type=0xF Operation=1 Bus Speed=0 Functional=0 engineSelect=0xF0 24 | 6.88209|I2C|I>i2cProcessActiveMasters: I2C Master Procs: 2 25 | 6.88220|I2C|I>i2cProcessActiveMasters: No Membuf chips found! 26 | 6.88221|I2C|I>i2cProcessActiveMasters: I2C Master Membufs: 0 27 | 6.88223|I2C|I>i2cProcessActiveMasters: Reset/Setup tgt=0x50000 engine=1 28 | 6.88227|SECURE|I> getSecuritySwitch() err_rc:0x0000 huid:0xFFFFFFFF reg:0x0000000000000000 29 | 6.88228|SECURE|I> getEnabled() state:0 30 | 6.88232|SECURE|I> getSecuritySwitch() err_rc:0x0000 huid:0x00050000 reg:0x0000000000000000 31 | 6.88234|I2C|I>i2cProcessActiveMasters: reset engine: 1, reset_level=1 32 | 6.88353|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=1, port=0 33 | 6.88479|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=1, port=1 34 | 6.88484|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=1, port=2 35 | 6.88490|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=1, port=3 36 | 6.88505|I2C|I>i2cProcessActiveMasters: Reset/Setup tgt=0x50000 engine=2 37 | 6.88506|I2C|I>i2cProcessActiveMasters: reset engine: 2, reset_level=1 38 | 6.88626|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/0 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 39 | 6.88628|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 40 | 6.88635|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/1 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 41 | 6.88636|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 42 | 6.88643|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/2 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 43 | 6.88645|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 44 | 6.88652|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/3 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 45 | 6.88653|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 46 | 6.88660|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/4 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 47 | 6.88662|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 48 | 6.88669|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/5 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 49 | 6.88670|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 50 | 6.88677|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/6 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 51 | 6.88679|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 52 | 6.88686|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/7 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 53 | 6.88688|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 54 | 6.88695|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/8 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 55 | 6.88696|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 56 | 6.88703|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/9 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 57 | 6.88705|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 58 | 6.88711|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/10 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 59 | 6.88713|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 60 | 6.88720|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/11 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 61 | 6.88722|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 62 | 6.88729|I2C|I>Not doing i2cForceResetAndUnlock() for target=0x00050000: e/p= 2/12 due to P9 diag mode limitations. Disable diag mode on e2 = 1, secure mode enabled = 0 63 | 6.88731|I2C|I>i2cForceResetAndUnlock(): muxSelector=0xFF, muxPath=NULL 64 | 6.88735|I2C|I>i2cProcessActiveMasters: Reset/Setup tgt=0x50000 engine=3 65 | 6.88737|I2C|I>i2cProcessActiveMasters: reset engine: 3, reset_level=1 66 | 6.88740|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=3, port=0 67 | 6.88746|I2C|I>i2cForceResetAndUnlock() - Performing op on engine=3, port=1 68 | 6.88757|I2C|<Got an error log Msg - Type: 0x00000039 71 | 6.96381|ERRL|I>Flush message received 72 | 6.96616|INITSVC|<>doIstep: step 6, substep 6, task host_set_ipl_parms 74 | --------------------------------------------------------------------------------