├── .ccsproject ├── .cproject ├── .gitignore ├── .project ├── BootLoader ├── inc │ └── BootLoader.h └── src │ └── BootLoader.c ├── Flash28335_API_V210 ├── Lib │ └── Flash28335_API_V210.lib └── inc │ ├── Flash2833x_API_Config.h │ └── Flash2833x_API_Library.h ├── bsp ├── inc │ ├── CANA.h │ ├── Flash.h │ └── LED.h └── src │ ├── CANA.c │ ├── Flash.c │ └── LED.c ├── user ├── inc │ └── main.h └── src │ └── main.c └── user_lib ├── asm ├── DSP2833x_ADC_cal.asm ├── DSP2833x_CSMPasswords.asm ├── DSP2833x_CodeStartBranch.asm ├── DSP2833x_DBGIER.asm ├── DSP2833x_DisInt.asm └── DSP2833x_usDelay.asm ├── cmd ├── DSP2833x_Headers_nonBIOS.cmd └── F28335.cmd ├── inc ├── DSP2833x_Adc.h ├── DSP2833x_CpuTimers.h ├── DSP2833x_DMA.h ├── DSP2833x_DefaultIsr.h ├── DSP2833x_DevEmu.h ├── DSP2833x_Device.h ├── DSP2833x_Dma_defines.h ├── DSP2833x_ECan.h ├── DSP2833x_ECap.h ├── DSP2833x_ECap_define.h ├── DSP2833x_EPwm.h ├── DSP2833x_EPwm_defines.h ├── DSP2833x_EQep.h ├── DSP2833x_Examples.h ├── DSP2833x_GlobalPrototypes.h ├── DSP2833x_Gpio.h ├── DSP2833x_I2c.h ├── DSP2833x_I2c_defines.h ├── DSP2833x_Mcbsp.h ├── DSP2833x_PieCtrl.h ├── DSP2833x_PieVect.h ├── DSP2833x_SWPrioritizedIsrLevels.h ├── DSP2833x_Sci.h ├── DSP2833x_Spi.h ├── DSP2833x_SysCtrl.h ├── DSP2833x_XIntrupt.h ├── DSP2833x_Xintf.h ├── DSP28x_Project.h ├── SFO.h ├── SFO_V5.h ├── config.h ├── data.h └── delay.h └── src ├── DSP2833x_CpuTimers.c ├── DSP2833x_DefaultIsr.c ├── DSP2833x_ECan.c ├── DSP2833x_GlobalVariableDefs.c ├── DSP2833x_Gpio.c ├── DSP2833x_MemCopy.c ├── DSP2833x_PieCtrl.c ├── DSP2833x_PieVect.c ├── DSP2833x_Sci.c ├── DSP2833x_Spi.c ├── DSP2833x_SysCtrl.c ├── DSP2833x_Xintf.c └── delay.c /.ccsproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .launches 2 | .settings 3 | Debug 4 | targetConfigs -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | 28335_Boot 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | 11 | 12 | 13 | 14 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 15 | full,incremental, 16 | 17 | 18 | 19 | 20 | 21 | com.ti.ccstudio.core.ccsNature 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.core.ccnature 25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 26 | 27 | 28 | -------------------------------------------------------------------------------- /BootLoader/inc/BootLoader.h: -------------------------------------------------------------------------------- 1 | /* 2 | * BootLoader.h 3 | * 4 | * Created on: 2017年4月19日 5 | * Author: admin 6 | */ 7 | 8 | #ifndef BOOTLOADER_BOOTLOADER_H_ 9 | #define BOOTLOADER_BOOTLOADER_H_ 10 | #include "DSP2833x_Device.h" 11 | #include "DSP2833x_Examples.h" 12 | #include "data.h" 13 | #include "delay.h" 14 | #include "stdint.h" 15 | #include "CANA.h" 16 | #include "Flash.h" 17 | #define DATA_LEN 520 //缓存数组长度 18 | #define READ_MAX 256 //每次读取数据的最大长度,16位数据 19 | #define APP_START_ADDR ((uint32_t)0x310010) 20 | #define APP_Write_START_ADDR ((uint32_t)0x310000) 21 | #define APP_Write_END_ADDR ((uint32_t)0x33FF80) 22 | #define APP_INFO_ADDR ((uint32_t)0x310000) 23 | #define CAN_BL_APP 0xAAAAAA 24 | #define CAN_BL_BOOT 0x555555 25 | #define DEVICE_ADDR 0x134//设备地址 26 | #define CMD_WIDTH 0x04 27 | #define ADDR_WIDTH 0x0C 28 | //----------------------以下宏定义是对芯片型号进行宏定义---------------------------- 29 | #define TMS320F28335 0x01 30 | #define TMS230F2808 0x02 31 | #define STM32F407IGT6 0x03 32 | //--------------------------------------------------------------------------------- 33 | //故障信息列表 34 | #define DEVICE_ADDR_ERROR 0xA0 35 | #define ERASE_ERROR 0xA1 36 | #define WRITE_ERROR 0xA2 37 | #define READ_LEN_ERROR 0xA3 38 | #define MSG_DATA_LEN_ERROR 0xA4 39 | #define FILE_TYPE_ERROR 0xA5 40 | #define CRC_ERROR 0xA6 41 | #define FLASH_ADDR_ERROR 0xA7 42 | #define WRITE_LEN_ERROR 0xA8 43 | //--------------------------------------------------- 44 | #define File_None 0xF0 45 | #define File_bin 0xF1 46 | #define File_hex 0xF2 47 | typedef void (*pFunction)(void); 48 | typedef struct _Device_INFO 49 | { 50 | union 51 | { 52 | unsigned short int all; 53 | struct 54 | { 55 | unsigned short int Device_addr :12; 56 | unsigned short int reserve :4; 57 | } bits; //设备地址 58 | } Device_addr; 59 | union 60 | { 61 | unsigned long int all; 62 | struct 63 | { 64 | unsigned long int FW_type :24; //固件类型 65 | unsigned long int Chip_Value :8; //控制器芯片类型 66 | } bits; 67 | } FW_TYPE; 68 | union 69 | { 70 | unsigned long int all; 71 | struct 72 | { 73 | unsigned long int Version :7; //固件版本 74 | unsigned long int date :5; //日期 75 | unsigned long int month :4; //月 76 | unsigned long int year :16; //年 77 | } bits; 78 | } FW_Version; //固件版本 79 | } Device_INFO; 80 | typedef struct _bootloader_data 81 | { 82 | union 83 | { 84 | u32 all; 85 | struct 86 | { 87 | u16 cmd :CMD_WIDTH; //命令 88 | u16 addr :ADDR_WIDTH; //设备地址 89 | u16 reserve :16; //保留位 90 | } bit; 91 | } ExtId; //扩展帧ID 92 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 93 | unsigned char DLC; //数据长度，可为0到8; 94 | u8 data[8]; 95 | } bootloader_data; 96 | typedef struct _Boot_CMD_LIST 97 | { 98 | //Bootloader相关命令 99 | unsigned char Read; //读取flash数据 100 | unsigned char Erase; //擦出APP储存扇区数据 101 | unsigned char Write; //以多字节形式写数据 102 | unsigned char Check; //检测节点是否在线，同时返回固件信息 103 | unsigned char Excute; //执行固件 104 | unsigned char WriteInfo; //设置多字节写数据相关参数（写起始地址，数据量） 105 | unsigned char SetBaudRate; //设置节点波特率 106 | //节点返回状态,关键 107 | unsigned char CmdFaild; //命令执行失败 108 | unsigned char CmdSuccess; //命令执行成功 109 | 110 | } Boot_CMD_LIST; 111 | extern Boot_CMD_LIST cmd_list; 112 | extern bootloader_data Bootloader_data; 113 | extern Device_INFO DEVICE_INFO; 114 | extern Uint16 app_check[3]; 115 | void __disable_irq(void); 116 | void __enable_irq(void); 117 | void __set_PRIMASK(u8 state); 118 | 119 | unsigned short int CRCcalc16(unsigned char *data, unsigned short int len); 120 | void CAN_BOOT_JumpToApplication(uint32_t Addr); 121 | void CAN_BOOT_ExecutiveCommand(CanRxMsg *pRxMessage); 122 | unsigned short int Check_APP(uint32_t Addr); 123 | #endif /* BOOTLOADER_BOOTLOADER_H_ */ 124 | -------------------------------------------------------------------------------- /Flash28335_API_V210/Lib/Flash28335_API_V210.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/Flash28335_API_V210/Lib/Flash28335_API_V210.lib -------------------------------------------------------------------------------- /Flash28335_API_V210/inc/Flash2833x_API_Config.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: June 22, 2007 13:11:24 $ 3 | //########################################################################### 4 | // 5 | // FILE: Flash2833x_API_Config.h 6 | // 7 | // TITLE: F2833x Flash Algo's - User Settings 8 | // 9 | // NOTE: This file contains user defined settings that 10 | // are used by the F2833x Flash APIs. 11 | // 12 | //########################################################################### 13 | // $TI Release:$ 14 | // $Release Date:$ 15 | //########################################################################### 16 | 17 | #ifndef FLASH2833X_API_CONFIG_H 18 | #define FLASH2833X_API_CONFIG_H 19 | 20 | #ifdef __cplusplus 21 | extern "C" { 22 | #endif 23 | 24 | // Variables that can be configured by the user. 25 | 26 | /*----------------------------------------------------------------------------- 27 | 1. Specify the device. 28 | Define the device to be programmed as "1" (no quotes). 29 | Define all other devices as "0" (no quotes). 30 | -----------------------------------------------------------------------------*/ 31 | 32 | #define FLASH_F28335 1 33 | #define FLASH_F28334 0 34 | #define FLASH_F28332 0 35 | 36 | /*----------------------------------------------------------------------------- 37 | 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. 38 | 39 | Take into account the input clock frequency and the PLL multiplier 40 | that your application will use. 41 | 42 | Use one of the values provided, or define your own. 43 | The trailing L is required tells the compiler to treat 44 | the number as a 64-bit value. 45 | 46 | Only one statement should be uncommented. 47 | 48 | Example: CLKIN is a 30MHz crystal. 49 | 50 | If the application will set PLLCR = 0xA then the CPU clock 51 | will be 150Mhz (SYSCLKOUT = 150MHz). 52 | 53 | In this case, the CPU_RATE will be 6.667L 54 | Uncomment the line: #define CPU_RATE 6.667L 55 | -----------------------------------------------------------------------------*/ 56 | 57 | #define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) 58 | //#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 59 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 60 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 61 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 62 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 63 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 64 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 65 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 66 | 67 | //---------------------------------------------------------------------------- 68 | 69 | 70 | //----------------------------------------------------------------------------- 71 | // **** DO NOT modify the code below this line **** 72 | //----------------------------------------------------------------------------- 73 | #define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20 74 | 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif /* extern "C" */ 79 | 80 | #endif // -- end FLASH2833X_API_CONFIG_H 81 | -------------------------------------------------------------------------------- /Flash28335_API_V210/inc/Flash2833x_API_Library.h: -------------------------------------------------------------------------------- 1 | #ifndef FLASH2833X_API_LIBRARY_H 2 | #define FLASH2833X_API_LIBRARY_H 3 | 4 | #include "Flash2833x_API_Config.h" 5 | 6 | #ifdef __cplusplus 7 | extern "C" { 8 | #endif 9 | 10 | 11 | 12 | /*--------------------------------------------------------------------------- 13 | 28x Datatypes 14 | 15 | For Portability, User Is Recommended To Use Following Data Type Size 16 | Definitions For 16/32/64-Bit Signed/Unsigned Integers and floating point 17 | variables: 18 | ---------------------------------------------------------------------------*/ 19 | 20 | #ifndef DSP28_DATA_TYPES 21 | #define DSP28_DATA_TYPES 22 | typedef int int16; 23 | typedef long int32; 24 | typedef long long int64; 25 | typedef unsigned int Uint16; 26 | typedef unsigned long Uint32; 27 | typedef unsigned long long Uint64; 28 | typedef float float32; 29 | typedef long double float64; 30 | #endif 31 | 32 | /*--------------------------------------------------------------------------- 33 | API Status Messages 34 | 35 | The following status values are returned from the API to the calling 36 | program. These can be used to determine if the API function passed 37 | or failed. 38 | ---------------------------------------------------------------------------*/ 39 | // Operation passed, no errors were flagged 40 | #define STATUS_SUCCESS 0 41 | 42 | // The CSM is preventing the function from performing its operation 43 | #define STATUS_FAIL_CSM_LOCKED 10 44 | 45 | // Device REVID does not match that required by the API 46 | #define STATUS_FAIL_REVID_INVALID 11 47 | 48 | // Invalid address passed to the API 49 | #define STATUS_FAIL_ADDR_INVALID 12 50 | 51 | // Incorrect PARTID 52 | // For example the F2806 API was used on a F2808 device. 53 | #define STATUS_FAIL_INCORRECT_PARTID 13 54 | 55 | // API/Silicon missmatch. An old version of the 56 | // API is being used on silicon it is not valid for 57 | // Please update to the latest API. 58 | #define STATUS_FAIL_API_SILICON_MISMATCH 14 59 | 60 | // ---- Erase Specific errors ---- 61 | #define STATUS_FAIL_NO_SECTOR_SPECIFIED 20 62 | #define STATUS_FAIL_PRECONDITION 21 63 | #define STATUS_FAIL_ERASE 22 64 | #define STATUS_FAIL_COMPACT 23 65 | #define STATUS_FAIL_PRECOMPACT 24 66 | 67 | // ---- Program Specific errors ---- 68 | #define STATUS_FAIL_PROGRAM 30 69 | #define STATUS_FAIL_ZERO_BIT_ERROR 31 70 | 71 | // ---- Verify Specific errors ---- 72 | #define STATUS_FAIL_VERIFY 40 73 | 74 | // Busy is set by each API function before it determines 75 | // a pass or fail condition for that operation. 76 | // The calling function will will not receive this 77 | // status condition back from the API 78 | #define STATUS_BUSY 999 79 | 80 | /*--------------------------------------------------------------------------- 81 | Flash sector mask definitions 82 | 83 | The following macros can be used to form a mask specifying which sectors 84 | will be erased by the erase API function. 85 | 86 | Bit0 = Sector A 87 | Bit1 = Sector B 88 | Bit2 = Sector C 89 | Bit3 = Sector D 90 | Bit4 = Sector E 91 | Bit5 = Sector F 92 | Bit6 = Sector G 93 | Bit7 = Sector H 94 | ---------------------------------------------------------------------------*/ 95 | 96 | #define SECTORA (Uint16)0x0001 97 | #define SECTORB (Uint16)0x0002 98 | #define SECTORC (Uint16)0x0004 99 | #define SECTORD (Uint16)0x0008 100 | #define SECTORE (Uint16)0x0010 101 | #define SECTORF (Uint16)0x0020 102 | #define SECTORG (Uint16)0x0040 103 | #define SECTORH (Uint16)0x0080 104 | 105 | 106 | #if FLASH_F28335 107 | // All sectors on an F28335 - Sectors A - H 108 | #define SECTOR_F28335 (SECTORA|SECTORB|SECTORC|\ 109 | SECTORD|SECTORE|SECTORF|\ 110 | SECTORG|SECTORH) 111 | #endif // -- end FLASH_F28335 112 | 113 | #if FLASH_F28334 114 | // All sectors on an F28334 - Sectors A - H 115 | #define SECTOR_F28334 (SECTORA|SECTORB|SECTORC|\ 116 | SECTORD|SECTORE|SECTORF|\ 117 | SECTORG|SECTORH) 118 | #endif // -- end FLASH_F28334 119 | 120 | #if FLASH_F28332 121 | // All sectors on an F28332 - Sectors A - D 122 | #define SECTOR_F28332 (SECTORA|SECTORB|SECTORC|\ 123 | SECTORD) 124 | #endif // -- end FLASH_F28332 125 | 126 | 127 | /*--------------------------------------------------------------------------- 128 | API Status Structure 129 | 130 | This structure is used to pass debug data back to the calling routine. 131 | Note that the Erase API function has 3 parts: precondition, erase and 132 | and compaction. Erase and compaction failures will not populate 133 | the expected and actual data fields. 134 | ---------------------------------------------------------------------------*/ 135 | 136 | typedef struct { 137 | Uint32 FirstFailAddr; 138 | Uint16 ExpectedData; 139 | Uint16 ActualData; 140 | }FLASH_ST; 141 | 142 | /*--------------------------------------------------------------------------- 143 | Interface Function prototypes 144 | 145 | For each 28x Flash API library, the function names are of the form: 146 | Flash_() 147 | 148 | Where is the device: ie 2808, 2806, 2801 149 | is the operation such as Erase, Program... 150 | 151 | For portability for users who may move between the F2808, F2806 and 152 | F2801, the following macro definitions are supplied. 153 | 154 | Using these macro definitions, the user can use instead make a generic 155 | call: Flash_ and the macro will map the call to the proper 156 | device function 157 | 158 | Note except for the toggle test function, all of the function prototypes 159 | are compatible with F281x devices as well. 160 | ---------------------------------------------------------------------------*/ 161 | 162 | #if FLASH_F28335 163 | #define Flash_Erase(a,b) Flash28335_Erase(a,b) 164 | #define Flash_Program(a,b,c,d) Flash28335_Program(a,b,c,d) 165 | #define Flash_Verify(a,b,c,d) Flash28335_Verify(a,b,c,d) 166 | #define Flash_ToggleTest(a,b) Flash28335_ToggleTest(a,b) 167 | #define Flash_DepRecover() Flash28335_DepRecover() 168 | #define Flash_APIVersionHex() Flash28335_APIVersionHex() 169 | #define Flash_APIVersion() Flash28335_APIVersion() 170 | #endif 171 | 172 | #if FLASH_F28334 173 | #define Flash_Erase(a,b) Flash28334_Erase(a,b) 174 | #define Flash_Program(a,b,c,d) Flash28334_Program(a,b,c,d) 175 | #define Flash_Verify(a,b,c,d) Flash28334_Verify(a,b,c,d) 176 | #define Flash_ToggleTest(a,b) Flash28334_ToggleTest(a,b) 177 | #define Flash_DepRecover() Flash28334_DepRecover() 178 | #define Flash_APIVersionHex() Flash28334_APIVersionHex() 179 | #define Flash_APIVersion() Flash28334_APIVersion() 180 | #endif 181 | 182 | #if FLASH_F28332 183 | #define Flash_Erase(a,b) Flash28332_Erase(a,b) 184 | #define Flash_Program(a,b,c,d) Flash28332_Program(a,b,c,d) 185 | #define Flash_Verify(a,b,c,d) Flash28332_Verify(a,b,c,d) 186 | #define Flash_ToggleTest(a,b) Flash28332_ToggleTest(a,b) 187 | #define Flash_DepRecover() Flash28332_DepRecover() 188 | #define Flash_APIVersionHex() Flash28332_APIVersionHex() 189 | #define Flash_APIVersion() Flash28332_APIVersion() 190 | #endif 191 | 192 | extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat); 193 | extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus); 194 | extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat); 195 | extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask); 196 | extern Uint16 Flash_DepRecover(); 197 | extern float32 Flash_APIVersion(); 198 | extern Uint16 Flash_APIVersionHex(); 199 | 200 | /*--------------------------------------------------------------------------- 201 | Frequency Scale factor: 202 | The calling program must provide this global parameter used 203 | for frequency scaling the algo's. 204 | ----------------------------------------------------------------------------*/ 205 | 206 | extern Uint32 Flash_CPUScaleFactor; 207 | 208 | /*--------------------------------------------------------------------------- 209 | Callback Function Pointer: 210 | A callback function can be specified. This function will be called 211 | at safe times during erase, program and verify. This function can 212 | then be used to service an external watchdog or send a communications 213 | packet. 214 | 215 | Note: 216 | THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. 217 | THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL 218 | DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL 219 | ----------------------------------------------------------------------------*/ 220 | extern void (*Flash_CallbackPtr) (void); 221 | 222 | /*--------------------------------------------------------------------------- 223 | API load/run symbols: 224 | These symbols are defined by the linker during the link. Refer to the 225 | Flash28_API section in the example .cmd file: 226 | 227 | Flash28_API: 228 | { 229 | Flash28335_API_Library.lib(.econst) 230 | Flash28335_API_Library.lib(.text) 231 | } LOAD = FLASH, 232 | RUN = SARAM, 233 | LOAD_START(_Flash28_API_LoadStart), 234 | LOAD_END(_Flash28_API_LoadEnd), 235 | RUN_START(_Flash28_API_RunStart), 236 | PAGE = 0 237 | 238 | These are used to copy the flash API from flash to SARAM 239 | 240 | ----------------------------------------------------------------------------*/ 241 | 242 | extern Uint16 Flash28_API_LoadStart; 243 | extern Uint16 Flash28_API_LoadEnd; 244 | extern Uint16 Flash28_API_RunStart; 245 | 246 | #ifdef __cplusplus 247 | } 248 | #endif /* extern "C" */ 249 | 250 | 251 | #endif // -- end FLASH2833x_API_LIBRARY_H 252 | 253 | // --------- END OF FILE ---------------------------------- 254 | 255 | -------------------------------------------------------------------------------- /bsp/inc/CANA.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CANA.h 3 | * 4 | * Created on: 2017年4月16日 5 | * Author: admin 6 | */ 7 | 8 | #ifndef BSP_INC_CANA_H_ 9 | #define BSP_INC_CANA_H_ 10 | #include "DSP2833x_Device.h" 11 | #include "DSP2833x_Examples.h" 12 | #include "data.h" 13 | #include "delay.h" 14 | #include "stdint.h" 15 | #define USE_CANA 1 16 | #define USE_CANB 0 17 | #define CAN_Id_Standard 0//表示标准帧 18 | #define CAN_Id_Extended 1//表示扩展帧 19 | #define CAN_ID_STD CAN_Id_Standard 20 | #define CAN_ID_EXT CAN_Id_Extended 21 | #define TXCOUNT 100 22 | typedef enum _CAN_Num 23 | { 24 | Null = 0, CANA = 1, CANB = 2, 25 | } CAN_Num; 26 | typedef enum _UPDATE_State 27 | { 28 | NON_CHANGE = 0, UPDATE = 1, 29 | } UPDATE_State; 30 | typedef union 31 | { 32 | unsigned long int all; 33 | struct 34 | { 35 | unsigned short int SA :8; 36 | unsigned short int PS :8; 37 | unsigned short int PF :8; 38 | unsigned short int DP :1; 39 | unsigned short int R :1; 40 | unsigned short int Priority :3; 41 | unsigned short int resved :3; 42 | } bit; 43 | } SAE_ID; 44 | typedef struct _CAN_MSG_byte 45 | { 46 | unsigned char data[8]; 47 | } CAN_MSG_byte; 48 | typedef struct _CAN_MSG_BYTE 49 | { 50 | unsigned char byte0; 51 | unsigned char byte1; 52 | unsigned char byte2; 53 | unsigned char byte3; 54 | unsigned char byte4; 55 | unsigned char byte5; 56 | unsigned char byte6; 57 | unsigned char byte7; 58 | } CAN_MSG_BYTE; 59 | typedef union _CAN_MSG_DATA 60 | { 61 | CAN_MSG_byte msg_byte; 62 | CAN_MSG_BYTE msg_Byte; 63 | } CAN_MSG_DATA; 64 | typedef struct _CanTxMsg 65 | { 66 | union 67 | { 68 | unsigned short int all; 69 | struct 70 | { 71 | unsigned short int StdId :11; 72 | unsigned short int resved :5; 73 | } bit; 74 | } StdId; //标准帧ID 75 | union 76 | { 77 | unsigned long int all; 78 | struct 79 | { 80 | unsigned long int ExtId :29; 81 | unsigned long int resved :3; 82 | } bit; 83 | } ExtId; //扩展帧ID 84 | unsigned char SAE_J1939_Flag; //表示是否使用SAE J1939协议 85 | SAE_ID SAE_J1939_ID; 86 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 87 | unsigned char DLC; //数据长度，可为0到8; 88 | unsigned char MBox_num; //邮箱编号,0-31 89 | unsigned short int Tx_timeout_cnt; 90 | CAN_Num CAN_num; 91 | UPDATE_State tx_update; 92 | CAN_MSG_DATA CAN_Tx_msg_data; /*!< 帧消息内容,共8字节 */ 93 | 94 | } CanTxMsg; 95 | typedef struct _CanRxMsg 96 | { 97 | union 98 | { 99 | unsigned short int all; 100 | struct 101 | { 102 | unsigned short int StdId :11; 103 | unsigned short int resved :5; 104 | } bit; 105 | } StdId; ////标准帧ID,值为0x000到0x7FFF; 106 | union 107 | { 108 | unsigned long int all; 109 | struct 110 | { 111 | unsigned long int ExtId :29; 112 | unsigned long int resved :3; 113 | } bit; 114 | } ExtId; ////扩展帧ID,值为0到0x1FFFFFFF 115 | unsigned char SAE_J1939_Flag; //表示是否使用SAE J1939协议 116 | SAE_ID SAE_J1939_ID; 117 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 118 | unsigned char DLC; //数据长度，可为0到8; 119 | unsigned char MBox_num; //发送所用邮箱编号 120 | unsigned short int Rx_timeout_cnt; 121 | CAN_MSG_DATA CAN_Rx_msg_data; /*!< 帧消息内容,共8字节 */ 122 | CAN_Num CAN_num; 123 | UPDATE_State rx_update; 124 | } CanRxMsg; 125 | typedef struct _CANBus_Baudrate 126 | { 127 | Uint16 BRPREG: 8; // 23:16 Baudrate prescaler register value 128 | Uint16 TSEG2REG: 3; // 2:0 TSEG2 register value 129 | Uint16 TSEG1REG: 4; // 6:3 TSEG1 register value 130 | unsigned short int BaudRate; 131 | }CANBus_Baudrate; 132 | void CAN_GPIO_Config(CAN_Num CAN); 133 | void CAN_Config(CAN_Num CAN,unsigned short int BaudRate); 134 | void CAN_Tx_Msg(CanTxMsg *can_tx_msg); //发送消息 135 | void CAN_Rx_Msg(CanRxMsg *can_rx_msg); //接收消息 136 | #if USE_CANA 137 | static void CANA_RX_Config(void); 138 | #endif 139 | #if USE_CANB 140 | static void CANB_RX_Config(void); 141 | #endif 142 | void CAN_Rx_Config(void); 143 | void CAN_Rx_IT_Concig(void); 144 | int CAN_GetBaudRateNum(unsigned int BaudRate); 145 | __interrupt void Ecana_isr1(void); 146 | extern CanTxMsg can_tx_msg; 147 | extern CanRxMsg can_rx_msg; 148 | extern CANBus_Baudrate CANBus_Baudrate_table[27]; 149 | #endif /* BSP_INC_CANA_H_ */ 150 | -------------------------------------------------------------------------------- /bsp/inc/Flash.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/bsp/inc/Flash.h -------------------------------------------------------------------------------- /bsp/inc/LED.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/bsp/inc/LED.h -------------------------------------------------------------------------------- /bsp/src/Flash.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/bsp/src/Flash.c -------------------------------------------------------------------------------- /bsp/src/LED.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/bsp/src/LED.c -------------------------------------------------------------------------------- /user/inc/main.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/user/inc/main.h -------------------------------------------------------------------------------- /user/src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * main.c 3 | * 4 | * Created on: 2017年4月16日 5 | * Author: admin 6 | */ 7 | /***************************************************************** 8 | *整体的思路是: 9 | * 第一步:样子FLASH的数据写入和擦除; 10 | * 第二步:验证CAN总线接收数据; 11 | * 第三步:根据前面的步骤进行最后综合 12 | * 第一步验证FLASH功能函数基本结束; 13 | * 需要添加两个功能函数:从某个地址写入和从某个地址读出的函数 14 | *****************************************************************/ 15 | #include "main.h" 16 | #include "BootLoader.h" 17 | #include "LED.h" 18 | int main(void) 19 | { 20 | DINT; 21 | DRTM; 22 | InitSysCtrl(); 23 | CAN_GPIO_Config(CANA); 24 | LED_GPIO_Config(); 25 | CsmUnlock(); 26 | InitPieCtrl(); 27 | IER = 0x0000; 28 | IFR = 0x0000; 29 | InitPieVectTable(); 30 | EALLOW; 31 | PieVectTable.TINT0 = &cpu_timer0_isr; 32 | PieVectTable.ECAN1INTA = &Ecana_isr1; 33 | EDIS; 34 | MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); 35 | MemCopy(&Flash28_API_LoadStart, &Flash28_API_LoadEnd,&Flash28_API_RunStart); 36 | InitFlash(); 37 | FlashAPI_Init(); 38 | /* 39 | FLASH_ST Flash_status; 40 | Uint16 status = 0x0001; 41 | status = Flash_Verify((Uint16*)APP_INFO_ADDR,app_check,3,&Flash_status); 42 | if(status == STATUS_SUCCESS) 43 | { 44 | CAN_BOOT_JumpToApplication(APP_START_ADDR); 45 | } 46 | */ 47 | CAN_Config(CANA,500); 48 | CAN_Rx_Config(); 49 | CAN_Rx_IT_Concig(); 50 | //配置LED指示灯 51 | LED_Timer_Config(); 52 | //------------------------------------ 53 | //配置中断 54 | PieCtrlRegs.PIEIER1.bit.INTx7 = 1; 55 | PieCtrlRegs.PIEIER9.bit.INTx6 = 1; //CANA的中断1 56 | IER |= M_INT9; 57 | IER |= M_INT1; 58 | __enable_irq(); 59 | while (1) 60 | { 61 | if(updata_info.time_out_flag == 0) 62 | { 63 | if(can_rx_msg.rx_update == UPDATE) 64 | { 65 | if(CpuTimer0Regs.TCR.bit.TSS == 0) 66 | { 67 | CpuTimer0Regs.TCR.bit.TSS = 1; 68 | } 69 | updata_info.time_out_flag = 0; 70 | can_rx_msg.rx_update = NON_CHANGE; 71 | CAN_BOOT_ExecutiveCommand(&can_rx_msg); 72 | GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; 73 | } 74 | } 75 | else 76 | { 77 | CAN_BOOT_JumpToApplication(APP_START_ADDR); 78 | } 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_ADC_cal.asm: -------------------------------------------------------------------------------- 1 | ;; TI File $Revision: /main/1 $ 2 | ;; Checkin $Date: July 30, 2007 10:29:23 $ 3 | ;;########################################################################### 4 | ;; 5 | ;; FILE: ADC_cal.asm 6 | ;; 7 | ;; TITLE: 2833x Boot Rom ADC Cal routine. 8 | ;; 9 | ;; Functions: 10 | ;; 11 | ;; _ADC_cal - Copies device specific calibration data into ADCREFSEL and ADCOFFTRIM registers 12 | ;; Notes: 13 | ;; 14 | ;;########################################################################### 15 | ;; $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 16 | ;; $Release Date: June 8, 2012 $ 17 | ;;########################################################################### 18 | 19 | .def _ADC_cal 20 | .asg "0x711C", ADCREFSEL_LOC 21 | 22 | ;----------------------------------------------- 23 | ; _ADC_cal 24 | ;----------------------------------------------- 25 | ;----------------------------------------------- 26 | ; This is the ADC cal routine.This routine is programmed into 27 | ; reserved memory by the factory. 0xAAAA and 0xBBBB are place- 28 | ; holders for calibration data. 29 | ;The actual values programmed by TI are device specific. 30 | ; 31 | ; This function assumes that the clocks have been 32 | ; enabled to the ADC module. 33 | ;----------------------------------------------- 34 | 35 | .sect ".adc_cal" 36 | 37 | _ADC_cal 38 | MOVW DP, #ADCREFSEL_LOC >> 6 39 | MOV @28, #0xAAAA ; actual value may not be 0xAAAA 40 | MOV @29, #0xBBBB ; actual value may not be 0xBBBB 41 | LRETR 42 | ;eof ---------- 43 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_CSMPasswords.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/3 $ 2 | ;// Checkin $Date: June 26, 2007 16:41:07 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CSMPasswords.asm 6 | ;// 7 | ;// TITLE: DSP2833x Code Security Module Passwords. 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This file is used to specify password values to 12 | ;// program into the CSM password locations in Flash 13 | ;// at 0x33FFF8 - 0x33FFFF. 14 | ;// 15 | ;// In addition, the reserved locations 0x33FF80 - 0X33fff5 are 16 | ;// all programmed to 0x0000 17 | ;// 18 | ;//########################################################################### 19 | ;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V141 $ 20 | ;// $Release Date: November 6, 2015 $ 21 | ;// $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated - 22 | ;// http://www.ti.com/ ALL RIGHTS RESERVED $ 23 | ;//########################################################################### 24 | 25 | ; The "csmpasswords" section contains the actual CSM passwords that will be 26 | ; linked and programmed into to the CSM password locations (PWL) in flash. 27 | ; These passwords must be known in order to unlock the CSM module. 28 | ; All 0xFFFF's (erased) is the default value for the password locations (PWL). 29 | 30 | ; It is recommended that all passwords be left as 0xFFFF during code 31 | ; development. Passwords of 0xFFFF do not activate code security and dummy 32 | ; reads of the CSM PWL registers is all that is required to unlock the CSM. 33 | ; When code development is complete, modify the passwords to activate the 34 | ; code security module. 35 | 36 | .sect "csmpasswds" 37 | 38 | .int 0xFFFF ;PWL0 (LSW of 128-bit password) 39 | .int 0xFFFF ;PWL1 40 | .int 0xFFFF ;PWL2 41 | .int 0xFFFF ;PWL3 42 | .int 0xFFFF ;PWL4 43 | .int 0xFFFF ;PWL5 44 | .int 0xFFFF ;PWL6 45 | .int 0xFFFF ;PWL7 (MSW of 128-bit password) 46 | 47 | ;---------------------------------------------------------------------- 48 | 49 | ; For code security operation, all addresses between 0x33FF80 and 50 | ; 0X33fff5 cannot be used as program code or data. These locations 51 | ; must be programmed to 0x0000 when the code security password locations 52 | ; (PWL) are programmed. If security is not a concern, then these addresses 53 | ; can be used for code or data. 54 | 55 | ; The section "csm_rsvd" can be used to program these locations to 0x0000. 56 | 57 | .sect "csm_rsvd" 58 | .loop (33FFF5h - 33FF80h + 1) 59 | .int 0x0000 60 | .endloop 61 | 62 | ;//=========================================================================== 63 | ;// End of file. 64 | ;//=========================================================================== 65 | 66 | 67 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:45:55 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_CodeStartBranch.asm 6 | ;// 7 | ;// TITLE: Branch for redirecting code execution after boot. 8 | ;// 9 | ;// For these examples, code_start is the first code that is executed after 10 | ;// exiting the boot ROM code. 11 | ;// 12 | ;// The codestart section in the linker cmd file is used to physically place 13 | ;// this code at the correct memory location. This section should be placed 14 | ;// at the location the BOOT ROM will re-direct the code to. For example, 15 | ;// for boot to FLASH this code will be located at 0x3f7ff6. 16 | ;// 17 | ;// In addition, the example DSP2833x projects are setup such that the codegen 18 | ;// entry point is also set to the code_start label. This is done by linker 19 | ;// option -e in the project build options. When the debugger loads the code, 20 | ;// it will automatically set the PC to the "entry point" address indicated by 21 | ;// the -e linker option. In this case the debugger is simply assigning the PC, 22 | ;// it is not the same as a full reset of the device. 23 | ;// 24 | ;// The compiler may warn that the entry point for the project is other then 25 | ;// _c_init00. _c_init00 is the C environment setup and is run before 26 | ;// main() is entered. The code_start code will re-direct the execution 27 | ;// to _c_init00 and thus there is no worry and this warning can be ignored. 28 | ;// 29 | ;//########################################################################### 30 | ;// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 31 | ;// $Release Date: June 8, 2012 $ 32 | ;//########################################################################### 33 | 34 | 35 | *********************************************************************** 36 | 37 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 38 | 39 | .ref _c_int00 40 | .global code_start 41 | 42 | *********************************************************************** 43 | * Function: codestart section 44 | * 45 | * Description: Branch to code starting point 46 | *********************************************************************** 47 | 48 | .sect "codestart" 49 | 50 | code_start: 51 | .if WD_DISABLE == 1 52 | LB wd_disable ;Branch to watchdog disable code 53 | .else 54 | LB _c_int00 ;Branch to start of boot.asm in RTS library 55 | .endif 56 | 57 | ;end codestart section 58 | 59 | 60 | *********************************************************************** 61 | * Function: wd_disable 62 | * 63 | * Description: Disables the watchdog timer 64 | *********************************************************************** 65 | .if WD_DISABLE == 1 66 | 67 | .text 68 | wd_disable: 69 | SETC OBJMODE ;Set OBJMODE for 28x object code 70 | EALLOW ;Enable EALLOW protected register access 71 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 72 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 73 | EDIS ;Disable EALLOW protected register access 74 | LB _c_int00 ;Branch to start of boot.asm in RTS library 75 | 76 | .endif 77 | 78 | ;end wd_disable 79 | 80 | 81 | 82 | .end 83 | 84 | ;//=========================================================================== 85 | ;// End of file. 86 | ;//=========================================================================== 87 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_DBGIER.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:03 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DBGIER.asm 6 | ;// 7 | ;// TITLE: Set the DBGIER register 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// Function to set the DBGIER register (for realtime emulation). 12 | ;// Function Prototype: void SetDBGIER(Uint16) 13 | ;// Useage: SetDBGIER(value); 14 | ;// Input Parameters: Uint16 value = value to put in DBGIER register. 15 | ;// Return Value: none 16 | ;// 17 | ;//########################################################################### 18 | ;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V141 $ 19 | ;// $Release Date: November 6, 2015 $ 20 | ;// $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated - 21 | ;// http://www.ti.com/ ALL RIGHTS RESERVED $ 22 | ;//########################################################################### 23 | .global _SetDBGIER 24 | .text 25 | 26 | _SetDBGIER: 27 | MOV *SP++,AL 28 | POP DBGIER 29 | LRETR 30 | 31 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_DisInt.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/1 $ 2 | ;// Checkin $Date: August 18, 2006 13:46:09 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_DisInt.asm 6 | ;// 7 | ;// TITLE: Disable and Restore INTM and DBGM 8 | ;// 9 | ;// Function Prototypes: 10 | ;// 11 | ;// Uint16 DSP28x_DisableInt(); 12 | ;// and void DSP28x_RestoreInt(Uint16 Stat0); 13 | ;// 14 | ;// Usage: 15 | ;// 16 | ;// DSP28x_DisableInt() sets both the INTM and DBGM 17 | ;// bits to disable maskable interrupts. Before doing 18 | ;// this, the current value of ST1 is stored on the stack 19 | ;// so that the values can be restored later. The value 20 | ;// of ST1 before the masks are set is returned to the 21 | ;// user in AL. This is then used to restore their state 22 | ;// via the DSP28x_RestoreInt(Uint16 ST1) function. 23 | ;// 24 | ;// Example 25 | ;// 26 | ;// Uint16 StatusReg1 27 | ;// StatusReg1 = DSP28x_DisableInt(); 28 | ;// 29 | ;// ... May also want to disable INTM here 30 | ;// 31 | ;// ... code here 32 | ;// 33 | ;// DSP28x_RestoreInt(StatusReg1); 34 | ;// 35 | ;// ... Restore INTM enable 36 | ;// 37 | ;//########################################################################### 38 | ;// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V141 $ 39 | ;// $Release Date: November 6, 2015 $ 40 | ;// $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated - 41 | ;// http://www.ti.com/ ALL RIGHTS RESERVED $ 42 | ;//########################################################################### 43 | 44 | 45 | 46 | 47 | .def _DSP28x_DisableInt 48 | .def _DSP28x_RestoreInt 49 | 50 | 51 | _DSP28x_DisableInt: 52 | PUSH ST1 53 | SETC INTM,DBGM 54 | MOV AL, *--SP 55 | LRETR 56 | 57 | _DSP28x_RestoreInt: 58 | MOV *SP++, AL 59 | POP ST1 60 | LRETR 61 | 62 | 63 | ;//=========================================================================== 64 | ;// End of file. 65 | ;//=========================================================================== 66 | 67 | 68 | -------------------------------------------------------------------------------- /user_lib/asm/DSP2833x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;// TI File $Revision: /main/4 $ 2 | ;// Checkin $Date: July 30, 2007 10:28:57 $ 3 | ;//########################################################################### 4 | ;// 5 | ;// FILE: DSP2833x_usDelay.asm 6 | ;// 7 | ;// TITLE: Simple delay function 8 | ;// 9 | ;// DESCRIPTION: 10 | ;// 11 | ;// This is a simple delay function that can be used to insert a specified 12 | ;// delay into code. 13 | ;// 14 | ;// This function is only accurate if executed from internal zero-waitstate 15 | ;// SARAM. If it is executed from waitstate memory then the delay will be 16 | ;// longer then specified. 17 | ;// 18 | ;// To use this function: 19 | ;// 20 | ;// 1 - update the CPU clock speed in the DSP2833x_Examples.h 21 | ;// file. For example: 22 | ;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed 23 | ;// or #define CPU_RATE 10.000L // for a 100MHz CPU clock speed 24 | ;// 25 | ;// 2 - Call this function by using the DELAY_US(A) macro 26 | ;// that is defined in the DSP2833x_Examples.h file. This macro 27 | ;// will convert the number of microseconds specified 28 | ;// into a loop count for use with this function. 29 | ;// This count will be based on the CPU frequency you specify. 30 | ;// 31 | ;// 3 - For the most accurate delay 32 | ;// - Execute this function in 0 waitstate RAM. 33 | ;// - Disable interrupts before calling the function 34 | ;// If you do not disable interrupts, then think of 35 | ;// this as an "at least" delay function as the actual 36 | ;// delay may be longer. 37 | ;// 38 | ;// The C assembly call from the DELAY_US(time) macro will 39 | ;// look as follows: 40 | ;// 41 | ;// extern void Delay(long LoopCount); 42 | ;// 43 | ;// MOV AL,#LowLoopCount 44 | ;// MOV AH,#HighLoopCount 45 | ;// LCR _Delay 46 | ;// 47 | ;// Or as follows (if count is less then 16-bits): 48 | ;// 49 | ;// MOV ACC,#LoopCount 50 | ;// LCR _Delay 51 | ;// 52 | ;// 53 | ;//########################################################################### 54 | ;// $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 55 | ;// $Release Date: June 8, 2012 $ 56 | ;//########################################################################### 57 | 58 | .def _DSP28x_usDelay 59 | .sect "ramfuncs" 60 | 61 | .global __DSP28x_usDelay 62 | _DSP28x_usDelay: 63 | SUB ACC,#1 64 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 65 | LRETR 66 | 67 | ;There is a 9/10 cycle overhead and each loop 68 | ;takes five cycles. The LoopCount is given by 69 | ;the following formula: 70 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 71 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 72 | ; The macro DELAY_US(A) performs this calculation for you 73 | ; 74 | ;//=========================================================================== 75 | ;// End of file. 76 | ;//=========================================================================== 77 | -------------------------------------------------------------------------------- /user_lib/cmd/DSP2833x_Headers_nonBIOS.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: DSP2833x_Headers_nonBIOS.cmd 5 | // 6 | // TITLE: DSP2833x Peripheral registers linker command file 7 | // 8 | // DESCRIPTION: 9 | // 10 | // This file is for use in Non-BIOS applications. 11 | // 12 | // Linker command file to place the peripheral structures 13 | // used within the DSP2833x headerfiles into the correct memory 14 | // mapped locations. 15 | // 16 | // This version of the file includes the PieVectorTable structure. 17 | // For BIOS applications, please use the DSP2833x_Headers_BIOS.cmd file 18 | // which does not include the PieVectorTable structure. 19 | // 20 | //########################################################################### 21 | */ 22 | 23 | MEMORY 24 | { 25 | PAGE 0: /* Program Memory */ 26 | 27 | PAGE 1: /* Data Memory */ 28 | 29 | DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ 30 | FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ 31 | CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ 32 | 33 | ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ 34 | 35 | XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ 36 | 37 | CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ 38 | CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ 39 | CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ 40 | 41 | PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ 42 | PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ 43 | 44 | DMA : origin = 0x001000, length = 0x000200 /* DMA registers */ 45 | 46 | MCBSPA : origin = 0x005000, length = 0x000040 /* McBSP-A registers */ 47 | MCBSPB : origin = 0x005040, length = 0x000040 /* McBSP-B registers */ 48 | 49 | ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ 50 | ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ 51 | ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ 52 | ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ 53 | ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ 54 | 55 | ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ 56 | ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ 57 | ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ 58 | ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ 59 | ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ 60 | 61 | EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ 62 | EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ 63 | EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ 64 | EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ 65 | EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ 66 | EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ 67 | 68 | ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ 69 | ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ 70 | ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ 71 | ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ 72 | ECAP5 : origin = 0x006A80, length = 0x000020 /* Enhanced Capture 5 registers */ 73 | ECAP6 : origin = 0x006AA0, length = 0x000020 /* Enhanced Capture 6 registers */ 74 | 75 | EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ 76 | EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ 77 | 78 | GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ 79 | GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ 80 | GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ 81 | 82 | SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ 83 | SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ 84 | SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ 85 | XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ 86 | 87 | ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ 88 | 89 | SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ 90 | 91 | SCIC : origin = 0x007770, length = 0x000010 /* SCI-C registers */ 92 | 93 | I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ 94 | 95 | CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ 96 | 97 | PARTID : origin = 0x380090, length = 0x000001 /* Part ID register location */ 98 | } 99 | 100 | 101 | SECTIONS 102 | { 103 | PieVectTableFile : > PIE_VECT, PAGE = 1 104 | 105 | /*** Peripheral Frame 0 Register Structures ***/ 106 | DevEmuRegsFile : > DEV_EMU, PAGE = 1 107 | FlashRegsFile : > FLASH_REGS, PAGE = 1 108 | CsmRegsFile : > CSM, PAGE = 1 109 | AdcMirrorFile : > ADC_MIRROR, PAGE = 1 110 | XintfRegsFile : > XINTF, PAGE = 1 111 | CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 112 | CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 113 | CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 114 | PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 115 | DmaRegsFile : > DMA, PAGE = 1 116 | 117 | /*** Peripheral Frame 3 Register Structures ***/ 118 | McbspaRegsFile : > MCBSPA, PAGE = 1 119 | McbspbRegsFile : > MCBSPB, PAGE = 1 120 | 121 | /*** Peripheral Frame 1 Register Structures ***/ 122 | ECanaRegsFile : > ECANA, PAGE = 1 123 | ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 124 | ECanaMboxesFile : > ECANA_MBOX PAGE = 1 125 | ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 126 | ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 127 | 128 | ECanbRegsFile : > ECANB, PAGE = 1 129 | ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 130 | ECanbMboxesFile : > ECANB_MBOX PAGE = 1 131 | ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 132 | ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 133 | 134 | EPwm1RegsFile : > EPWM1 PAGE = 1 135 | EPwm2RegsFile : > EPWM2 PAGE = 1 136 | EPwm3RegsFile : > EPWM3 PAGE = 1 137 | EPwm4RegsFile : > EPWM4 PAGE = 1 138 | EPwm5RegsFile : > EPWM5 PAGE = 1 139 | EPwm6RegsFile : > EPWM6 PAGE = 1 140 | 141 | ECap1RegsFile : > ECAP1 PAGE = 1 142 | ECap2RegsFile : > ECAP2 PAGE = 1 143 | ECap3RegsFile : > ECAP3 PAGE = 1 144 | ECap4RegsFile : > ECAP4 PAGE = 1 145 | ECap5RegsFile : > ECAP5 PAGE = 1 146 | ECap6RegsFile : > ECAP6 PAGE = 1 147 | 148 | EQep1RegsFile : > EQEP1 PAGE = 1 149 | EQep2RegsFile : > EQEP2 PAGE = 1 150 | 151 | GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 152 | GpioDataRegsFile : > GPIODAT PAGE = 1 153 | GpioIntRegsFile : > GPIOINT PAGE = 1 154 | 155 | /*** Peripheral Frame 2 Register Structures ***/ 156 | SysCtrlRegsFile : > SYSTEM, PAGE = 1 157 | SpiaRegsFile : > SPIA, PAGE = 1 158 | SciaRegsFile : > SCIA, PAGE = 1 159 | XIntruptRegsFile : > XINTRUPT, PAGE = 1 160 | AdcRegsFile : > ADC, PAGE = 1 161 | ScibRegsFile : > SCIB, PAGE = 1 162 | ScicRegsFile : > SCIC, PAGE = 1 163 | I2caRegsFile : > I2CA, PAGE = 1 164 | 165 | /*** Code Security Module Register Structures ***/ 166 | CsmPwlFile : > CSM_PWL, PAGE = 1 167 | 168 | /*** Device Part ID Register Structures ***/ 169 | PartIdRegsFile : > PARTID, PAGE = 1 170 | 171 | } 172 | 173 | 174 | /* 175 | //=========================================================================== 176 | // End of file. 177 | //=========================================================================== 178 | */ 179 | -------------------------------------------------------------------------------- /user_lib/cmd/F28335.cmd: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | PAGE 0 : /* Program Memory */ 4 | /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ 5 | 6 | ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */ 7 | RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ 8 | RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ 9 | RAML2 : origin = 0x00A000, length = 0x001000 /* on-chip RAM block L2 */ 10 | RAML3 : origin = 0x00B000, length = 0x001000 /* on-chip RAM block L3 */ 11 | ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */ 12 | ZONE7A : origin = 0x0200000, length = 0x00FC00 /* XINTF zone 7 - program space */ 13 | /*-----------------------------------------------------------------------------*/ 14 | FLASHH : origin = 0x300000, length = 0x008000 15 | /*-----------------------------------------------------------------------------*/ 16 | FLASHG : origin = 0x308000, length = 0x008000 17 | FLASHF : origin = 0x310000, length = 0x008000 18 | FLASHE : origin = 0x318000, length = 0x008000 19 | FLASHD : origin = 0x320000, length = 0x008000 20 | FLASHC : origin = 0x328000, length = 0x008000 21 | FLASHB : origin = 0x330000, length = 0x008000 22 | FLASHA : origin = 0x338000, length = 0x007F80 23 | /*-----------------------------------------------------------------------------*/ 24 | CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ 25 | BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ 26 | CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ 27 | OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */ 28 | ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */ 29 | /*----------------------------------------------------------------------------------------*/ 30 | IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */ 31 | IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */ 32 | FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */ 33 | ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */ 34 | RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ 35 | VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ 36 | 37 | PAGE 1 : 38 | 39 | BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */ 40 | RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */ 41 | RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ 42 | RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */ 43 | RAML5 : origin = 0x00D000, length = 0x001000 /* on-chip RAM block L1 */ 44 | RAML6 : origin = 0x00E000, length = 0x001000 /* on-chip RAM block L1 */ 45 | RAML7 : origin = 0x00F000, length = 0x001000 /* on-chip RAM block L1 */ 46 | ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */ 47 | 48 | } 49 | SECTIONS 50 | { 51 | .cinit : > FLASHH PAGE = 0 52 | .pinit : > FLASHH, PAGE = 0 53 | .text : > FLASHH PAGE = 0 54 | codestart : > BEGIN PAGE = 0 55 | Flash28_API: 56 | { 57 | -l Flash28335_API_V210.lib(.econst) 58 | -l Flash28335_API_V210.lib(.text) 59 | } 60 | LOAD = FLASHH, 61 | RUN = RAML0, 62 | LOAD_START(_Flash28_API_LoadStart), 63 | LOAD_END(_Flash28_API_LoadEnd), 64 | RUN_START(_Flash28_API_RunStart), 65 | PAGE = 0 66 | /*----------------------------------------------*/ 67 | ramfuncs : LOAD = FLASHH, 68 | RUN = RAML0, 69 | LOAD_START(_RamfuncsLoadStart), 70 | LOAD_END(_RamfuncsLoadEnd), 71 | RUN_START(_RamfuncsRunStart), 72 | PAGE = 0 73 | 74 | csmpasswds : > CSM_PWL PAGE = 0 75 | csm_rsvd : > CSM_RSVD PAGE = 0 76 | 77 | /* Allocate uninitalized data sections: */ 78 | .stack : > RAMM1 PAGE = 1 79 | .ebss : > RAML4 PAGE = 1 80 | .esysmem : > RAMM1 PAGE = 1 81 | 82 | /* Initalized sections go in Flash */ 83 | /* For SDFlash to program these, they must be allocated to page 0 */ 84 | .econst : > FLASHH PAGE = 0 85 | .switch : > FLASHH PAGE = 0 86 | 87 | /* Allocate IQ math areas: */ 88 | IQmath : > FLASHH PAGE = 0 /* Math Code */ 89 | IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD 90 | 91 | /* Uncomment the section below if calling the IQNexp() or IQexp() 92 | functions from the IQMath.lib library in order to utilize the 93 | relevant IQ Math table in Boot ROM (This saves space and Boot ROM 94 | is 1 wait-state). If this section is not uncommented, IQmathTables2 95 | will be loaded into other memory (SARAM, Flash, etc.) and will take 96 | up space, but 0 wait-state is possible. 97 | */ 98 | /* 99 | IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD 100 | { 101 | 102 | IQmath.lib (IQmathTablesRam) 103 | 104 | } 105 | */ 106 | 107 | FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD 108 | 109 | /* Allocate DMA-accessible RAM sections: */ 110 | DMARAML4 : > RAML4, PAGE = 1 111 | DMARAML5 : > RAML5, PAGE = 1 112 | DMARAML6 : > RAML6, PAGE = 1 113 | DMARAML7 : > RAML7, PAGE = 1 114 | 115 | /* Allocate 0x400 of XINTF Zone 7 to storing data */ 116 | ZONE7DATA : > ZONE7B, PAGE = 1 117 | 118 | /* .reset is a standard section used by the compiler. It contains the */ 119 | /* the address of the start of _c_int00 for C Code. /* 120 | /* When using the boot ROM this section and the CPU vector */ 121 | /* table is not needed. Thus the default type is set here to */ 122 | /* DSECT */ 123 | .reset : > RESET, PAGE = 0, TYPE = DSECT 124 | vectors : > VECTORS PAGE = 0, TYPE = DSECT 125 | 126 | /* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */ 127 | .adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD 128 | 129 | } 130 | 131 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Adc.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Adc.h 4 | // 5 | // TITLE: DSP2833x Device ADC Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_ADC_H 13 | #define DSP2833x_ADC_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | 20 | //--------------------------------------------------------------------------- 21 | // ADC Individual Register Bit Definitions: 22 | 23 | struct ADCTRL1_BITS { // bits description 24 | Uint16 rsvd1:4; // 3:0 reserved 25 | Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode 26 | Uint16 SEQ_OVRD:1; // 5 Sequencer override 27 | Uint16 CONT_RUN:1; // 6 Continuous run 28 | Uint16 CPS:1; // 7 ADC core clock pre-scalar 29 | Uint16 ACQ_PS:4; // 11:8 Acquisition window size 30 | Uint16 SUSMOD:2; // 13:12 Emulation suspend mode 31 | Uint16 RESET:1; // 14 ADC reset 32 | Uint16 rsvd2:1; // 15 reserved 33 | }; 34 | 35 | 36 | union ADCTRL1_REG { 37 | Uint16 all; 38 | struct ADCTRL1_BITS bit; 39 | }; 40 | 41 | 42 | struct ADCTRL2_BITS { // bits description 43 | Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 44 | Uint16 rsvd1:1; // 1 reserved 45 | Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode 46 | Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable 47 | Uint16 rsvd2:1; // 4 reserved 48 | Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 49 | Uint16 RST_SEQ2:1; // 6 Reset SEQ2 50 | Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 51 | Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 52 | Uint16 rsvd3:1; // 9 reserved 53 | Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode 54 | Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable 55 | Uint16 rsvd4:1; // 12 reserved 56 | Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 57 | Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 58 | Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable 59 | }; 60 | 61 | 62 | union ADCTRL2_REG { 63 | Uint16 all; 64 | struct ADCTRL2_BITS bit; 65 | }; 66 | 67 | 68 | struct ADCASEQSR_BITS { // bits description 69 | Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state 70 | Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state 71 | Uint16 rsvd1:1; // 7 reserved 72 | Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status 73 | Uint16 rsvd2:4; // 15:12 reserved 74 | }; 75 | 76 | union ADCASEQSR_REG { 77 | Uint16 all; 78 | struct ADCASEQSR_BITS bit; 79 | }; 80 | 81 | 82 | struct ADCMAXCONV_BITS { // bits description 83 | Uint16 MAX_CONV1:4; // 3:0 Max number of conversions 84 | Uint16 MAX_CONV2:3; // 6:4 Max number of conversions 85 | Uint16 rsvd1:9; // 15:7 reserved 86 | }; 87 | 88 | union ADCMAXCONV_REG { 89 | Uint16 all; 90 | struct ADCMAXCONV_BITS bit; 91 | }; 92 | 93 | 94 | struct ADCCHSELSEQ1_BITS { // bits description 95 | Uint16 CONV00:4; // 3:0 Conversion selection 00 96 | Uint16 CONV01:4; // 7:4 Conversion selection 01 97 | Uint16 CONV02:4; // 11:8 Conversion selection 02 98 | Uint16 CONV03:4; // 15:12 Conversion selection 03 99 | }; 100 | 101 | union ADCCHSELSEQ1_REG{ 102 | Uint16 all; 103 | struct ADCCHSELSEQ1_BITS bit; 104 | }; 105 | 106 | struct ADCCHSELSEQ2_BITS { // bits description 107 | Uint16 CONV04:4; // 3:0 Conversion selection 04 108 | Uint16 CONV05:4; // 7:4 Conversion selection 05 109 | Uint16 CONV06:4; // 11:8 Conversion selection 06 110 | Uint16 CONV07:4; // 15:12 Conversion selection 07 111 | }; 112 | 113 | union ADCCHSELSEQ2_REG{ 114 | Uint16 all; 115 | struct ADCCHSELSEQ2_BITS bit; 116 | }; 117 | 118 | struct ADCCHSELSEQ3_BITS { // bits description 119 | Uint16 CONV08:4; // 3:0 Conversion selection 08 120 | Uint16 CONV09:4; // 7:4 Conversion selection 09 121 | Uint16 CONV10:4; // 11:8 Conversion selection 10 122 | Uint16 CONV11:4; // 15:12 Conversion selection 11 123 | }; 124 | 125 | union ADCCHSELSEQ3_REG{ 126 | Uint16 all; 127 | struct ADCCHSELSEQ3_BITS bit; 128 | }; 129 | 130 | struct ADCCHSELSEQ4_BITS { // bits description 131 | Uint16 CONV12:4; // 3:0 Conversion selection 12 132 | Uint16 CONV13:4; // 7:4 Conversion selection 13 133 | Uint16 CONV14:4; // 11:8 Conversion selection 14 134 | Uint16 CONV15:4; // 15:12 Conversion selection 15 135 | }; 136 | 137 | union ADCCHSELSEQ4_REG { 138 | Uint16 all; 139 | struct ADCCHSELSEQ4_BITS bit; 140 | }; 141 | 142 | struct ADCTRL3_BITS { // bits description 143 | Uint16 SMODE_SEL:1; // 0 Sampling mode select 144 | Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider 145 | Uint16 ADCPWDN:1; // 5 ADC powerdown 146 | Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down 147 | Uint16 rsvd1:8; // 15:8 reserved 148 | }; 149 | 150 | union ADCTRL3_REG { 151 | Uint16 all; 152 | struct ADCTRL3_BITS bit; 153 | }; 154 | 155 | 156 | struct ADCST_BITS { // bits description 157 | Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag 158 | Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag 159 | Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status 160 | Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status 161 | Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear 162 | Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear 163 | Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 164 | Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 165 | Uint16 rsvd1:8; // 15:8 reserved 166 | }; 167 | 168 | 169 | union ADCST_REG { 170 | Uint16 all; 171 | struct ADCST_BITS bit; 172 | }; 173 | 174 | struct ADCREFSEL_BITS { // bits description 175 | Uint16 rsvd1:14; // 13:0 reserved 176 | Uint16 REF_SEL:2; // 15:14 Reference select 177 | }; 178 | union ADCREFSEL_REG { 179 | Uint16 all; 180 | struct ADCREFSEL_BITS bit; 181 | }; 182 | 183 | struct ADCOFFTRIM_BITS{ // bits description 184 | int16 OFFSET_TRIM:9; // 8:0 Offset Trim 185 | Uint16 rsvd1:7; // 15:9 reserved 186 | }; 187 | 188 | union ADCOFFTRIM_REG{ 189 | Uint16 all; 190 | struct ADCOFFTRIM_BITS bit; 191 | }; 192 | struct ADC_REGS { 193 | union ADCTRL1_REG ADCTRL1; // ADC Control 1 194 | union ADCTRL2_REG ADCTRL2; // ADC Control 2 195 | union ADCMAXCONV_REG ADCMAXCONV; // Max conversions 196 | union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 197 | union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 198 | union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 199 | union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 200 | union ADCASEQSR_REG ADCASEQSR; // Autosequence status register 201 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 202 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 203 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 204 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 205 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 206 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 207 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 208 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 209 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 210 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 211 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 212 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 213 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 214 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 215 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 216 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 217 | union ADCTRL3_REG ADCTRL3; // ADC Control 3 218 | union ADCST_REG ADCST; // ADC Status Register 219 | Uint16 rsvd1; 220 | Uint16 rsvd2; 221 | union ADCREFSEL_REG ADCREFSEL; // Reference Select Register 222 | union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register 223 | }; 224 | 225 | 226 | struct ADC_RESULT_MIRROR_REGS 227 | { 228 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 229 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 230 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 231 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 232 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 233 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 234 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 235 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 236 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 237 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 238 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 239 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 240 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 241 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 242 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 243 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 244 | }; 245 | 246 | //--------------------------------------------------------------------------- 247 | // ADC External References & Function Declarations: 248 | // 249 | extern volatile struct ADC_REGS AdcRegs; 250 | extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; 251 | 252 | 253 | #ifdef __cplusplus 254 | } 255 | #endif /* extern "C" */ 256 | 257 | 258 | #endif // end of DSP2833x_ADC_H definition 259 | 260 | //=========================================================================== 261 | // End of file. 262 | //=========================================================================== 263 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_CpuTimers.h 4 | // 5 | // TITLE: DSP2833x CPU 32-bit Timers Register Definitions. 6 | // 7 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 8 | // other realtime operating systems. 9 | // 10 | // Do not use these two timers in your application if you ever plan 11 | // on integrating DSP-BIOS or another realtime OS. 12 | // 13 | // For this reason, comment out the code to manipulate these two timers 14 | // if using DSP-BIOS or another realtime OS. 15 | // 16 | //########################################################################### 17 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 18 | // $Release Date: June 8, 2012 $ 19 | //########################################################################### 20 | 21 | #ifndef DSP2833x_CPU_TIMERS_H 22 | #define DSP2833x_CPU_TIMERS_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | //--------------------------------------------------------------------------- 29 | // CPU Timer Register Bit Definitions: 30 | // 31 | // 32 | // TCR: Control register bit definitions: 33 | struct TCR_BITS { // bits description 34 | Uint16 rsvd1:4; // 3:0 reserved 35 | Uint16 TSS:1; // 4 Timer Start/Stop 36 | Uint16 TRB:1; // 5 Timer reload 37 | Uint16 rsvd2:4; // 9:6 reserved 38 | Uint16 SOFT:1; // 10 Emulation modes 39 | Uint16 FREE:1; // 11 40 | Uint16 rsvd3:2; // 12:13 reserved 41 | Uint16 TIE:1; // 14 Output enable 42 | Uint16 TIF:1; // 15 Interrupt flag 43 | }; 44 | 45 | union TCR_REG { 46 | Uint16 all; 47 | struct TCR_BITS bit; 48 | }; 49 | 50 | // TPR: Pre-scale low bit definitions: 51 | struct TPR_BITS { // bits description 52 | Uint16 TDDR:8; // 7:0 Divide-down low 53 | Uint16 PSC:8; // 15:8 Prescale counter low 54 | }; 55 | 56 | union TPR_REG { 57 | Uint16 all; 58 | struct TPR_BITS bit; 59 | }; 60 | 61 | // TPRH: Pre-scale high bit definitions: 62 | struct TPRH_BITS { // bits description 63 | Uint16 TDDRH:8; // 7:0 Divide-down high 64 | Uint16 PSCH:8; // 15:8 Prescale counter high 65 | }; 66 | 67 | union TPRH_REG { 68 | Uint16 all; 69 | struct TPRH_BITS bit; 70 | }; 71 | 72 | // TIM, TIMH: Timer register definitions: 73 | struct TIM_REG { 74 | Uint16 LSW; 75 | Uint16 MSW; 76 | }; 77 | 78 | union TIM_GROUP { 79 | Uint32 all; 80 | struct TIM_REG half; 81 | }; 82 | 83 | // PRD, PRDH: Period register definitions: 84 | struct PRD_REG { 85 | Uint16 LSW; 86 | Uint16 MSW; 87 | }; 88 | 89 | union PRD_GROUP { 90 | Uint32 all; 91 | struct PRD_REG half; 92 | }; 93 | 94 | //--------------------------------------------------------------------------- 95 | // CPU Timer Register File: 96 | // 97 | struct CPUTIMER_REGS { 98 | union TIM_GROUP TIM; // Timer counter register 99 | union PRD_GROUP PRD; // Period register 100 | union TCR_REG TCR; // Timer control register 101 | Uint16 rsvd1; // reserved 102 | union TPR_REG TPR; // Timer pre-scale low 103 | union TPRH_REG TPRH; // Timer pre-scale high 104 | }; 105 | 106 | //--------------------------------------------------------------------------- 107 | // CPU Timer Support Variables: 108 | // 109 | struct CPUTIMER_VARS { 110 | volatile struct CPUTIMER_REGS *RegsAddr; 111 | Uint32 InterruptCount; 112 | float CPUFreqInMHz; 113 | float PeriodInUSec; 114 | }; 115 | 116 | //--------------------------------------------------------------------------- 117 | // Function prototypes and external definitions: 118 | // 119 | void InitCpuTimers(void); 120 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 121 | 122 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 123 | extern struct CPUTIMER_VARS CpuTimer0; 124 | 125 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS. Comment out CpuTimer1 and CpuTimer2 if using DSP BIOS or other RTOS 126 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 127 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 128 | 129 | extern struct CPUTIMER_VARS CpuTimer1; 130 | extern struct CPUTIMER_VARS CpuTimer2; 131 | 132 | //--------------------------------------------------------------------------- 133 | // Usefull Timer Operations: 134 | // 135 | // Start Timer: 136 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 137 | 138 | // Stop Timer: 139 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 140 | 141 | // Reload Timer With period Value: 142 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 143 | 144 | // Read 32-Bit Timer Value: 145 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 146 | 147 | // Read 32-Bit Period Value: 148 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 149 | 150 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 151 | // Do not use these two timers if you ever plan on integrating 152 | // DSP-BIOS or another realtime OS. 153 | // 154 | // For this reason, comment out the code to manipulate these two timers 155 | // if using DSP-BIOS or another realtime OS. 156 | 157 | // Start Timer: 158 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 159 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 160 | 161 | 162 | // Stop Timer: 163 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 164 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 165 | 166 | // Reload Timer With period Value: 167 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 168 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 169 | 170 | // Read 32-Bit Timer Value: 171 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 172 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 173 | 174 | // Read 32-Bit Period Value: 175 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 176 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 177 | 178 | 179 | #ifdef __cplusplus 180 | } 181 | #endif /* extern "C" */ 182 | 183 | #endif // end of DSP2833x_CPU_TIMERS_H definition 184 | 185 | 186 | //=========================================================================== 187 | // End of file. 188 | //=========================================================================== 189 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_DefaultIsr.h 4 | // 5 | // TITLE: DSP2833x Devices Default Interrupt Service Routines Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_DEFAULT_ISR_H 13 | #define DSP2833x_DEFAULT_ISR_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | 20 | //--------------------------------------------------------------------------- 21 | // Default Interrupt Service Routine Declarations: 22 | // 23 | // The following function prototypes are for the 24 | // default ISR routines used with the default PIE vector table. 25 | // This default vector table is found in the DSP2833x_PieVect.h 26 | // file. 27 | // 28 | 29 | // Non-Peripheral Interrupts: 30 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 31 | interrupt void INT14_ISR(void); // CPU-Timer2 32 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 33 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 34 | interrupt void EMUINT_ISR(void); // Emulation interrupt 35 | interrupt void NMI_ISR(void); // Non-maskable interrupt 36 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 37 | interrupt void USER1_ISR(void); // User Defined trap 1 38 | interrupt void USER2_ISR(void); // User Defined trap 2 39 | interrupt void USER3_ISR(void); // User Defined trap 3 40 | interrupt void USER4_ISR(void); // User Defined trap 4 41 | interrupt void USER5_ISR(void); // User Defined trap 5 42 | interrupt void USER6_ISR(void); // User Defined trap 6 43 | interrupt void USER7_ISR(void); // User Defined trap 7 44 | interrupt void USER8_ISR(void); // User Defined trap 8 45 | interrupt void USER9_ISR(void); // User Defined trap 9 46 | interrupt void USER10_ISR(void); // User Defined trap 10 47 | interrupt void USER11_ISR(void); // User Defined trap 11 48 | interrupt void USER12_ISR(void); // User Defined trap 12 49 | 50 | // Group 1 PIE Interrupt Service Routines: 51 | interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR 52 | interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR 53 | interrupt void XINT1_ISR(void); // External interrupt 1 54 | interrupt void XINT2_ISR(void); // External interrupt 2 55 | interrupt void ADCINT_ISR(void); // ADC 56 | interrupt void TINT0_ISR(void); // Timer 0 57 | interrupt void WAKEINT_ISR(void); // WD 58 | 59 | // Group 2 PIE Interrupt Service Routines: 60 | interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 61 | interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 62 | interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 63 | interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 64 | interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 65 | interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 66 | 67 | // Group 3 PIE Interrupt Service Routines: 68 | interrupt void EPWM1_INT_ISR(void); // EPWM-1 69 | interrupt void EPWM2_INT_ISR(void); // EPWM-2 70 | interrupt void EPWM3_INT_ISR(void); // EPWM-3 71 | interrupt void EPWM4_INT_ISR(void); // EPWM-4 72 | interrupt void EPWM5_INT_ISR(void); // EPWM-5 73 | interrupt void EPWM6_INT_ISR(void); // EPWM-6 74 | 75 | // Group 4 PIE Interrupt Service Routines: 76 | interrupt void ECAP1_INT_ISR(void); // ECAP-1 77 | interrupt void ECAP2_INT_ISR(void); // ECAP-2 78 | interrupt void ECAP3_INT_ISR(void); // ECAP-3 79 | interrupt void ECAP4_INT_ISR(void); // ECAP-4 80 | interrupt void ECAP5_INT_ISR(void); // ECAP-5 81 | interrupt void ECAP6_INT_ISR(void); // ECAP-6 82 | 83 | // Group 5 PIE Interrupt Service Routines: 84 | interrupt void EQEP1_INT_ISR(void); // EQEP-1 85 | interrupt void EQEP2_INT_ISR(void); // EQEP-2 86 | 87 | // Group 6 PIE Interrupt Service Routines: 88 | interrupt void SPIRXINTA_ISR(void); // SPI-A 89 | interrupt void SPITXINTA_ISR(void); // SPI-A 90 | interrupt void MRINTA_ISR(void); // McBSP-A 91 | interrupt void MXINTA_ISR(void); // McBSP-A 92 | interrupt void MRINTB_ISR(void); // McBSP-B 93 | interrupt void MXINTB_ISR(void); // McBSP-B 94 | 95 | // Group 7 PIE Interrupt Service Routines: 96 | interrupt void DINTCH1_ISR(void); // DMA-Channel 1 97 | interrupt void DINTCH2_ISR(void); // DMA-Channel 2 98 | interrupt void DINTCH3_ISR(void); // DMA-Channel 3 99 | interrupt void DINTCH4_ISR(void); // DMA-Channel 4 100 | interrupt void DINTCH5_ISR(void); // DMA-Channel 5 101 | interrupt void DINTCH6_ISR(void); // DMA-Channel 6 102 | 103 | // Group 8 PIE Interrupt Service Routines: 104 | interrupt void I2CINT1A_ISR(void); // I2C-A 105 | interrupt void I2CINT2A_ISR(void); // I2C-A 106 | interrupt void SCIRXINTC_ISR(void); // SCI-C 107 | interrupt void SCITXINTC_ISR(void); // SCI-C 108 | 109 | // Group 9 PIE Interrupt Service Routines: 110 | interrupt void SCIRXINTA_ISR(void); // SCI-A 111 | interrupt void SCITXINTA_ISR(void); // SCI-A 112 | interrupt void SCIRXINTB_ISR(void); // SCI-B 113 | interrupt void SCITXINTB_ISR(void); // SCI-B 114 | interrupt void ECAN0INTA_ISR(void); // eCAN-A 115 | interrupt void ECAN1INTA_ISR(void); // eCAN-A 116 | interrupt void ECAN0INTB_ISR(void); // eCAN-B 117 | interrupt void ECAN1INTB_ISR(void); // eCAN-B 118 | 119 | // Group 10 PIE Interrupt Service Routines: 120 | 121 | // Group 11 PIE Interrupt Service Routines: 122 | 123 | // Group 12 PIE Interrupt Service Routines: 124 | interrupt void XINT3_ISR(void); // External interrupt 3 125 | interrupt void XINT4_ISR(void); // External interrupt 4 126 | interrupt void XINT5_ISR(void); // External interrupt 5 127 | interrupt void XINT6_ISR(void); // External interrupt 6 128 | interrupt void XINT7_ISR(void); // External interrupt 7 129 | interrupt void LVF_ISR(void); // Latched overflow flag 130 | interrupt void LUF_ISR(void); // Latched underflow flag 131 | 132 | // Catch-all for Reserved Locations For testing purposes: 133 | interrupt void PIE_RESERVED(void); // Reserved for test 134 | interrupt void rsvd_ISR(void); // for test 135 | interrupt void INT_NOTUSED_ISR(void); // for unused interrupts 136 | 137 | #ifdef __cplusplus 138 | } 139 | #endif /* extern "C" */ 140 | 141 | #endif // end of DSP2833x_DEFAULT_ISR_H definition 142 | 143 | //=========================================================================== 144 | // End of file. 145 | //=========================================================================== 146 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_DevEmu.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_DevEmu.h 4 | // 5 | // TITLE: DSP2833x Device Emulation Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_DEV_EMU_H 13 | #define DSP2833x_DEV_EMU_H 14 | 15 | #ifdef __cplusplus 16 | extern "C" { 17 | #endif 18 | 19 | //--------------------------------------------------------------------------- 20 | // Device Emulation Register Bit Definitions: 21 | // 22 | // Device Configuration Register Bit Definitions 23 | struct DEVICECNF_BITS { // bits description 24 | Uint16 rsvd1:3; // 2:0 reserved 25 | Uint16 VMAPS:1; // 3 VMAP Status 26 | Uint16 rsvd2:1; // 4 reserved 27 | Uint16 XRSn:1; // 5 XRSn Signal Status 28 | Uint16 rsvd3:10; // 15:6 29 | Uint16 rsvd4:3; // 18:16 30 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 31 | Uint16 rsvd5:7; // 26:20 reserved 32 | Uint16 TRSTN:1; // 27 Status of TRSTn signal 33 | Uint16 rsvd6:4; // 31:28 reserved 34 | }; 35 | 36 | union DEVICECNF_REG { 37 | Uint32 all; 38 | struct DEVICECNF_BITS bit; 39 | }; 40 | 41 | // CLASSID 42 | struct CLASSID_BITS { // bits description 43 | Uint16 CLASSNO:8; // 7:0 Class Number 44 | Uint16 PARTTYPE:8; // 15:8 Part Type 45 | }; 46 | 47 | union CLASSID_REG { 48 | Uint16 all; 49 | struct CLASSID_BITS bit; 50 | }; 51 | 52 | struct DEV_EMU_REGS { 53 | union DEVICECNF_REG DEVICECNF; // device configuration 54 | union CLASSID_REG CLASSID; // Class ID 55 | Uint16 REVID; // Device ID 56 | Uint16 PROTSTART; // Write-Read protection start 57 | Uint16 PROTRANGE; // Write-Read protection range 58 | Uint16 rsvd2[202]; 59 | }; 60 | 61 | // PARTID 62 | struct PARTID_BITS { // bits description 63 | Uint16 PARTNO:8; // 7:0 Part Number 64 | Uint16 PARTTYPE:8; // 15:8 Part Type 65 | }; 66 | 67 | union PARTID_REG { 68 | Uint16 all; 69 | struct PARTID_BITS bit; 70 | }; 71 | 72 | struct PARTID_REGS { 73 | union PARTID_REG PARTID; // Part ID 74 | }; 75 | 76 | 77 | 78 | //--------------------------------------------------------------------------- 79 | // Device Emulation Register References & Function Declarations: 80 | // 81 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 82 | extern volatile struct PARTID_REGS PartIdRegs; 83 | 84 | #ifdef __cplusplus 85 | } 86 | #endif /* extern "C" */ 87 | 88 | #endif // end of DSP2833x_DEV_EMU_H definition 89 | 90 | //=========================================================================== 91 | // End of file. 92 | //=========================================================================== 93 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Device.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Device.h 4 | // 5 | // TITLE: DSP2833x Device Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_DEVICE_H 13 | #define DSP2833x_DEVICE_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | 21 | #define TARGET 1 22 | //--------------------------------------------------------------------------- 23 | // User To Select Target Device: 24 | 25 | #define DSP28_28335 TARGET // Selects '28335/'28235 26 | #define DSP28_28334 0 // Selects '28334/'28234 27 | #define DSP28_28332 0 // Selects '28332/'28232 28 | 29 | 30 | //--------------------------------------------------------------------------- 31 | // Common CPU Definitions: 32 | // 33 | 34 | extern cregister volatile unsigned int IFR; 35 | extern cregister volatile unsigned int IER; 36 | 37 | #define EINT asm(" clrc INTM") 38 | #define DINT asm(" setc INTM") 39 | #define ERTM asm(" clrc DBGM") 40 | #define DRTM asm(" setc DBGM") 41 | #define EALLOW asm(" EALLOW") 42 | #define EDIS asm(" EDIS") 43 | #define ESTOP0 asm(" ESTOP0") 44 | 45 | #define M_INT1 0x0001 46 | #define M_INT2 0x0002 47 | #define M_INT3 0x0004 48 | #define M_INT4 0x0008 49 | #define M_INT5 0x0010 50 | #define M_INT6 0x0020 51 | #define M_INT7 0x0040 52 | #define M_INT8 0x0080 53 | #define M_INT9 0x0100 54 | #define M_INT10 0x0200 55 | #define M_INT11 0x0400 56 | #define M_INT12 0x0800 57 | #define M_INT13 0x1000 58 | #define M_INT14 0x2000 59 | #define M_DLOG 0x4000 60 | #define M_RTOS 0x8000 61 | 62 | #define BIT0 0x0001 63 | #define BIT1 0x0002 64 | #define BIT2 0x0004 65 | #define BIT3 0x0008 66 | #define BIT4 0x0010 67 | #define BIT5 0x0020 68 | #define BIT6 0x0040 69 | #define BIT7 0x0080 70 | #define BIT8 0x0100 71 | #define BIT9 0x0200 72 | #define BIT10 0x0400 73 | #define BIT11 0x0800 74 | #define BIT12 0x1000 75 | #define BIT13 0x2000 76 | #define BIT14 0x4000 77 | #define BIT15 0x8000 78 | 79 | 80 | 81 | //--------------------------------------------------------------------------- 82 | // For Portability, User Is Recommended To Use Following Data Type Size 83 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 84 | // 85 | 86 | #ifndef DSP28_DATA_TYPES 87 | #define DSP28_DATA_TYPES 88 | typedef int int16; 89 | typedef long int32; 90 | typedef long long int64; 91 | typedef unsigned int Uint16; 92 | typedef unsigned long Uint32; 93 | typedef unsigned long long Uint64; 94 | typedef float float32; 95 | typedef long double float64; 96 | #endif 97 | 98 | 99 | //--------------------------------------------------------------------------- 100 | // Include All Peripheral Header Files: 101 | // 102 | 103 | #include "DSP2833x_Adc.h" // ADC Registers 104 | #include "DSP2833x_DevEmu.h" // Device Emulation Registers 105 | #include "DSP2833x_CpuTimers.h" // 32-bit CPU Timers 106 | #include "DSP2833x_ECan.h" // Enhanced eCAN Registers 107 | #include "DSP2833x_ECap.h" // Enhanced Capture 108 | #include "DSP2833x_DMA.h" // DMA Registers 109 | #include "DSP2833x_EPwm.h" // Enhanced PWM 110 | #include "DSP2833x_EQep.h" // Enhanced QEP 111 | #include "DSP2833x_Gpio.h" // General Purpose I/O Registers 112 | #include "DSP2833x_I2c.h" // I2C Registers 113 | #include "DSP2833x_McBSP.h" // McBSP 114 | #include "DSP2833x_PieCtrl.h" // PIE Control Registers 115 | #include "DSP2833x_PieVect.h" // PIE Vector Table 116 | #include "DSP2833x_Spi.h" // SPI Registers 117 | #include "DSP2833x_Sci.h" // SCI Registers 118 | #include "DSP2833x_SysCtrl.h" // System Control/Power Modes 119 | #include "DSP2833x_XIntrupt.h" // External Interrupts 120 | #include "DSP2833x_Xintf.h" // XINTF External Interface 121 | 122 | #if DSP28_28335 123 | #define DSP28_EPWM1 1 124 | #define DSP28_EPWM2 1 125 | #define DSP28_EPWM3 1 126 | #define DSP28_EPWM4 1 127 | #define DSP28_EPWM5 1 128 | #define DSP28_EPWM6 1 129 | #define DSP28_ECAP1 1 130 | #define DSP28_ECAP2 1 131 | #define DSP28_ECAP3 1 132 | #define DSP28_ECAP4 1 133 | #define DSP28_ECAP5 1 134 | #define DSP28_ECAP6 1 135 | #define DSP28_EQEP1 1 136 | #define DSP28_EQEP2 1 137 | #define DSP28_ECANA 1 138 | #define DSP28_ECANB 1 139 | #define DSP28_MCBSPA 1 140 | #define DSP28_MCBSPB 1 141 | #define DSP28_SPIA 1 142 | #define DSP28_SCIA 1 143 | #define DSP28_SCIB 1 144 | #define DSP28_SCIC 1 145 | #define DSP28_I2CA 1 146 | #endif // end DSP28_28335 147 | 148 | #if DSP28_28334 149 | #define DSP28_EPWM1 1 150 | #define DSP28_EPWM2 1 151 | #define DSP28_EPWM3 1 152 | #define DSP28_EPWM4 1 153 | #define DSP28_EPWM5 1 154 | #define DSP28_EPWM6 1 155 | #define DSP28_ECAP1 1 156 | #define DSP28_ECAP2 1 157 | #define DSP28_ECAP3 1 158 | #define DSP28_ECAP4 1 159 | #define DSP28_ECAP5 0 160 | #define DSP28_ECAP6 0 161 | #define DSP28_EQEP1 1 162 | #define DSP28_EQEP2 1 163 | #define DSP28_ECANA 1 164 | #define DSP28_ECANB 1 165 | #define DSP28_MCBSPA 1 166 | #define DSP28_MCBSPB 1 167 | #define DSP28_SPIA 1 168 | #define DSP28_SCIA 1 169 | #define DSP28_SCIB 1 170 | #define DSP28_SCIC 1 171 | #define DSP28_I2CA 1 172 | #endif // end DSP28_28334 173 | 174 | #if DSP28_28332 175 | #define DSP28_EPWM1 1 176 | #define DSP28_EPWM2 1 177 | #define DSP28_EPWM3 1 178 | #define DSP28_EPWM4 1 179 | #define DSP28_EPWM5 1 180 | #define DSP28_EPWM6 1 181 | #define DSP28_ECAP1 1 182 | #define DSP28_ECAP2 1 183 | #define DSP28_ECAP3 1 184 | #define DSP28_ECAP4 1 185 | #define DSP28_ECAP5 0 186 | #define DSP28_ECAP6 0 187 | #define DSP28_EQEP1 1 188 | #define DSP28_EQEP2 1 189 | #define DSP28_ECANA 1 190 | #define DSP28_ECANB 1 191 | #define DSP28_MCBSPA 1 192 | #define DSP28_MCBSPB 0 193 | #define DSP28_SPIA 1 194 | #define DSP28_SCIA 1 195 | #define DSP28_SCIB 1 196 | #define DSP28_SCIC 0 197 | #define DSP28_I2CA 1 198 | #endif // end DSP28_28332 199 | 200 | #ifdef __cplusplus 201 | } 202 | #endif /* extern "C" */ 203 | 204 | #endif // end of DSP2833x_DEVICE_H definition 205 | 206 | 207 | //=========================================================================== 208 | // End of file. 209 | //=========================================================================== 210 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Dma_defines.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Dma_defines.h 4 | // 5 | // TITLE: #defines used in DMA examples 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_DMA_DEFINES_H 13 | #define DSP2833x_DMA_DEFINES_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | // MODE 21 | //========================== 22 | // PERINTSEL bits 23 | #define DMA_SEQ1INT 1 24 | #define DMA_SEQ2INT 2 25 | #define DMA_XINT1 3 26 | #define DMA_XINT2 4 27 | #define DMA_XINT3 5 28 | #define DMA_XINT4 6 29 | #define DMA_XINT5 7 30 | #define DMA_XINT6 8 31 | #define DMA_XINT7 9 32 | #define DMA_XINT13 10 33 | #define DMA_TINT0 11 34 | #define DMA_TINT1 12 35 | #define DMA_TINT2 13 36 | #define DMA_MXEVTA 14 37 | #define DMA_MREVTA 15 38 | #define DMA_MXREVTB 16 39 | #define DMA_MREVTB 17 40 | // OVERINTE bit 41 | #define OVRFLOW_DISABLE 0x0 42 | #define OVEFLOW_ENABLE 0x1 43 | // PERINTE bit 44 | #define PERINT_DISABLE 0x0 45 | #define PERINT_ENABLE 0x1 46 | // CHINTMODE bits 47 | #define CHINT_BEGIN 0x0 48 | #define CHINT_END 0x1 49 | // ONESHOT bits 50 | #define ONESHOT_DISABLE 0x0 51 | #define ONESHOT_ENABLE 0x1 52 | // CONTINOUS bit 53 | #define CONT_DISABLE 0x0 54 | #define CONT_ENABLE 0x1 55 | // SYNCE bit 56 | #define SYNC_DISABLE 0x0 57 | #define SYNC_ENABLE 0x1 58 | // SYNCSEL bit 59 | #define SYNC_SRC 0x0 60 | #define SYNC_DST 0x1 61 | // DATASIZE bit 62 | #define SIXTEEN_BIT 0x0 63 | #define THIRTYTWO_BIT 0x1 64 | // CHINTE bit 65 | #define CHINT_DISABLE 0x0 66 | #define CHINT_ENABLE 0x1 67 | 68 | 69 | 70 | 71 | #ifdef __cplusplus 72 | } 73 | #endif /* extern "C" */ 74 | 75 | #endif // - end of DSP2833x_EPWM_DEFINES_H 76 | 77 | //=========================================================================== 78 | // End of file. 79 | //=========================================================================== 80 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_ECap.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_ECap.h 4 | // 5 | // TITLE: DSP2833x Enhanced Capture Module Register Bit Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_ECAP_H 13 | #define DSP2833x_ECAP_H 14 | #include "DSP2833x_ECap_define.h" 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | //---------------------------------------------------- 21 | // Capture control register 1 bit definitions */ 22 | struct ECCTL1_BITS { // bits description 23 | Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select 24 | Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 25 | Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select 26 | Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 27 | Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select 28 | Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 29 | Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select 30 | Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 31 | Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event 32 | Uint16 PRESCALE:5; // 13:9 Event Filter prescale select 33 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 34 | }; 35 | 36 | union ECCTL1_REG { 37 | Uint16 all; 38 | struct ECCTL1_BITS bit; 39 | }; 40 | 41 | 42 | // In V1.1 the STOPVALUE bit field was changed to 43 | // STOP_WRAP. This correlated to a silicon change from 44 | // F2833x Rev 0 to Rev A. 45 | //---------------------------------------------------- 46 | // Capture control register 2 bit definitions */ 47 | struct ECCTL2_BITS { // bits description 48 | Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot 49 | Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous 50 | Uint16 REARM:1; // 3 One-shot re-arm 51 | Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop 52 | Uint16 SYNCI_EN:1; // 5 Counter sync-in select 53 | Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode 54 | Uint16 SWSYNC:1; // 8 SW forced counter sync 55 | Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select 56 | Uint16 APWMPOL:1; // 10 APWM output polarity select 57 | Uint16 rsvd1:5; // 15:11 58 | }; 59 | 60 | 61 | union ECCTL2_REG { 62 | Uint16 all; 63 | struct ECCTL2_BITS bit; 64 | }; 65 | 66 | 67 | //---------------------------------------------------- 68 | // ECAP interrupt enable register bit definitions */ 69 | struct ECEINT_BITS { // bits description 70 | Uint16 rsvd1:1; // 0 reserved 71 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable 72 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable 73 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable 74 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable 75 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable 76 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable 77 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable 78 | Uint16 rsvd2:8; // 15:8 reserved 79 | }; 80 | 81 | 82 | union ECEINT_REG { 83 | Uint16 all; 84 | struct ECEINT_BITS bit; 85 | }; 86 | 87 | //---------------------------------------------------- 88 | // ECAP interrupt flag register bit definitions */ 89 | struct ECFLG_BITS { // bits description 90 | Uint16 INT:1; // 0 Global Flag 91 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag 92 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag 93 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag 94 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag 95 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag 96 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag 97 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag 98 | Uint16 rsvd2:8; // 15:8 reserved 99 | }; 100 | 101 | 102 | union ECFLG_REG { 103 | Uint16 all; 104 | struct ECFLG_BITS bit; 105 | }; 106 | 107 | 108 | //---------------------------------------------------- 109 | 110 | struct ECAP_REGS { 111 | Uint32 TSCTR; // Time stamp counter 112 | Uint32 CTRPHS; // Counter phase 113 | Uint32 CAP1; // Capture 1 114 | Uint32 CAP2; // Capture 2 115 | Uint32 CAP3; // Capture 3 116 | Uint32 CAP4; // Capture 4 117 | Uint16 rsvd1[8]; // reserved 118 | union ECCTL1_REG ECCTL1; // Capture Control Reg 1 119 | union ECCTL2_REG ECCTL2; // Capture Control Reg 2 120 | union ECEINT_REG ECEINT; // ECAP interrupt enable 121 | union ECFLG_REG ECFLG; // ECAP interrupt flags 122 | union ECFLG_REG ECCLR; // ECAP interrupt clear 123 | union ECEINT_REG ECFRC; // ECAP interrupt force 124 | Uint16 rsvd2[6]; // reserved 125 | }; 126 | 127 | 128 | 129 | 130 | //--------------------------------------------------------------------------- 131 | // GPI/O External References & Function Declarations: 132 | // 133 | extern volatile struct ECAP_REGS ECap1Regs; 134 | extern volatile struct ECAP_REGS ECap2Regs; 135 | extern volatile struct ECAP_REGS ECap3Regs; 136 | extern volatile struct ECAP_REGS ECap4Regs; 137 | extern volatile struct ECAP_REGS ECap5Regs; 138 | extern volatile struct ECAP_REGS ECap6Regs; 139 | 140 | 141 | #ifdef __cplusplus 142 | } 143 | #endif /* extern "C" */ 144 | 145 | #endif // end of DSP2833x_ECAP_H definition 146 | 147 | //=========================================================================== 148 | // End of file. 149 | //=========================================================================== 150 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_ECap_define.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/user_lib/inc/DSP2833x_ECap_define.h -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_EPwm_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: August 18, 2006 13:45:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP2833x_EPwm_defines.h 6 | // 7 | // TITLE: #defines used in ePWM examples examples 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP2833x Header Files V1.01 $ 11 | // $Release Date: September 26, 2007 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP2833x_EPWM_DEFINES_H 15 | #define DSP2833x_EPWM_DEFINES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | // TBCTL (Time-Base Control) 23 | //========================== 24 | // CTRMODE bits 25 | #define TB_COUNT_UP 0x0 26 | #define TB_COUNT_DOWN 0x1 27 | #define TB_COUNT_UPDOWN 0x2 28 | #define TB_FREEZE 0x3 29 | // PHSEN bit 30 | #define TB_DISABLE 0x0 31 | #define TB_ENABLE 0x1 32 | // PRDLD bit 33 | #define TB_SHADOW 0x0 34 | #define TB_IMMEDIATE 0x1 35 | // SYNCOSEL bits 36 | #define TB_SYNC_IN 0x0 37 | #define TB_CTR_ZERO 0x1 38 | #define TB_CTR_CMPB 0x2 39 | #define TB_SYNC_DISABLE 0x3 40 | // HSPCLKDIV and CLKDIV bits 41 | #define TB_DIV1 0x0 42 | #define TB_DIV2 0x1 43 | #define TB_DIV4 0x2 44 | // PHSDIR bit 45 | #define TB_DOWN 0x0 46 | #define TB_UP 0x1 47 | 48 | // CMPCTL (Compare Control) 49 | //========================== 50 | // LOADAMODE and LOADBMODE bits 51 | #define CC_CTR_ZERO 0x0 52 | #define CC_CTR_PRD 0x1 53 | #define CC_CTR_ZERO_PRD 0x2 54 | #define CC_LD_DISABLE 0x3 55 | // SHDWAMODE and SHDWBMODE bits 56 | #define CC_SHADOW 0x0 57 | #define CC_IMMEDIATE 0x1 58 | 59 | // AQCTLA and AQCTLB (Action Qualifier Control) 60 | //============================================= 61 | // ZRO, PRD, CAU, CAD, CBU, CBD bits 62 | #define AQ_NO_ACTION 0x0 63 | #define AQ_CLEAR 0x1 64 | #define AQ_SET 0x2 65 | #define AQ_TOGGLE 0x3 66 | 67 | // DBCTL (Dead-Band Control) 68 | //========================== 69 | // OUT MODE bits 70 | #define DB_DISABLE 0x0 71 | #define DBA_ENABLE 0x1 72 | #define DBB_ENABLE 0x2 73 | #define DB_FULL_ENABLE 0x3 74 | // POLSEL bits 75 | #define DB_ACTV_HI 0x0 76 | #define DB_ACTV_LOC 0x1 77 | #define DB_ACTV_HIC 0x2 78 | #define DB_ACTV_LO 0x3 79 | // IN MODE 80 | #define DBA_ALL 0x0 81 | #define DBB_RED_DBA_FED 0x1 82 | #define DBA_RED_DBB_FED 0x2 83 | #define DBB_ALL 0x3 84 | 85 | // CHPCTL (chopper control) 86 | //========================== 87 | // CHPEN bit 88 | #define CHP_DISABLE 0x0 89 | #define CHP_ENABLE 0x1 90 | // CHPFREQ bits 91 | #define CHP_DIV1 0x0 92 | #define CHP_DIV2 0x1 93 | #define CHP_DIV3 0x2 94 | #define CHP_DIV4 0x3 95 | #define CHP_DIV5 0x4 96 | #define CHP_DIV6 0x5 97 | #define CHP_DIV7 0x6 98 | #define CHP_DIV8 0x7 99 | /**/ 100 | #define TB_CLKDIV1 0x00 101 | #define TB_CLKDIV2 0x01 102 | #define TB_CLKDIV4 0x02 103 | #define TB_CLKDIV8 0x03 104 | #define TB_CLKDIV16 0x04 105 | #define TB_CLKDIV32 0x05 106 | #define TB_CLKDIV64 0x06 107 | #define TB_CLKDIV128 0x07 108 | //HSPCLKDIV and 109 | #define TB_HSPCLKDIV1 0x00 110 | #define TB_HSPCLKDIV2 0x01 111 | #define TB_HSPCLKDIV4 0x02 112 | #define TB_HSPCLKDIV6 0x03 113 | #define TB_HSPCLKDIV8 0x04 114 | #define TB_HSPCLKDIV10 0x05 115 | #define TB_HSPCLKDIV12 0x06 116 | #define TB_HSPCLKDIV14 0x07 117 | // CHPDUTY bits 118 | #define CHP1_8TH 0x0 119 | #define CHP2_8TH 0x1 120 | #define CHP3_8TH 0x2 121 | #define CHP4_8TH 0x3 122 | #define CHP5_8TH 0x4 123 | #define CHP6_8TH 0x5 124 | #define CHP7_8TH 0x6 125 | 126 | // TZSEL (Trip Zone Select) 127 | //========================== 128 | // CBCn and OSHTn bits 129 | #define TZ_DISABLE 0x0 130 | #define TZ_ENABLE 0x1 131 | 132 | // TZCTL (Trip Zone Control) 133 | //========================== 134 | // TZA and TZB bits 135 | #define TZ_HIZ 0x0 136 | #define TZ_FORCE_HI 0x1 137 | #define TZ_FORCE_LO 0x2 138 | #define TZ_NO_CHANGE 0x3 139 | 140 | // ETSEL (Event Trigger Select) 141 | //============================= 142 | #define ET_CTR_ZERO 0x1 143 | #define ET_CTR_PRD 0x2 144 | #define ET_CTRU_CMPA 0x4 145 | #define ET_CTRD_CMPA 0x5 146 | #define ET_CTRU_CMPB 0x6 147 | #define ET_CTRD_CMPB 0x7 148 | 149 | // ETPS (Event Trigger Pre-scale) 150 | //=============================== 151 | // INTPRD, SOCAPRD, SOCBPRD bits 152 | #define ET_DISABLE 0x0 153 | #define ET_1ST 0x1 154 | #define ET_2ND 0x2 155 | #define ET_3RD 0x3 156 | 157 | 158 | //-------------------------------- 159 | // HRPWM (High Resolution PWM) 160 | //================================ 161 | // HRCNFG 162 | #define HR_Disable 0x0 163 | #define HR_REP 0x1 164 | #define HR_FEP 0x2 165 | #define HR_BEP 0x3 166 | 167 | #define HR_CMP 0x0 168 | #define HR_PHS 0x1 169 | 170 | #define HR_CTR_ZERO 0x0 171 | #define HR_CTR_PRD 0x1 172 | 173 | 174 | #ifdef __cplusplus 175 | } 176 | #endif /* extern "C" */ 177 | 178 | #endif // - end of DSP2833x_EPWM_DEFINES_H 179 | 180 | //=========================================================================== 181 | // End of file. 182 | //=========================================================================== 183 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_EQep.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_EQep.h 4 | // 5 | // TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module 6 | // Register Bit Definitions. 7 | // 8 | //########################################################################### 9 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 10 | // $Release Date: June 8, 2012 $ 11 | //########################################################################### 12 | 13 | #ifndef DSP2833x_EQEP_H 14 | #define DSP2833x_EQEP_H 15 | 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | //---------------------------------------------------- 22 | // Capture decoder control register bit definitions */ 23 | struct QDECCTL_BITS { // bits description 24 | Uint16 rsvd1:5; // 4:0 reserved 25 | Uint16 QSP:1; // 5 QEPS input polarity 26 | Uint16 QIP:1; // 6 QEPI input polarity 27 | Uint16 QBP:1; // 7 QEPB input polarity 28 | Uint16 QAP:1; // 8 QEPA input polarity 29 | Uint16 IGATE:1; // 9 Index pulse gating option 30 | Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter 31 | Uint16 XCR:1; // 11 External clock rate 32 | Uint16 SPSEL:1; // 12 Sync output pin select 33 | Uint16 SOEN:1; // 13 Enable position compare sync 34 | Uint16 QSRC:2; // 15:14 Position counter source 35 | }; 36 | 37 | union QDECCTL_REG { 38 | Uint16 all; 39 | struct QDECCTL_BITS bit; 40 | }; 41 | 42 | 43 | //---------------------------------------------------- 44 | // QEP control register bit definitions */ 45 | struct QEPCTL_BITS { // bits description 46 | Uint16 WDE:1; // 0 QEP watchdog enable 47 | Uint16 UTE:1; // 1 QEP unit timer enable 48 | Uint16 QCLM:1; // 2 QEP capture latch mode 49 | Uint16 QPEN:1; // 3 Quadrature position counter enable 50 | Uint16 IEL:2; // 5:4 Index event latch 51 | Uint16 SEL:1; // 6 Strobe event latch 52 | Uint16 SWI:1; // 7 Software init position counter 53 | Uint16 IEI:2; // 9:8 Index event init of position count 54 | Uint16 SEI:2; // 11:10 Strobe event init 55 | Uint16 PCRM:2; // 13:12 Position counter reset 56 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 57 | }; 58 | 59 | union QEPCTL_REG { 60 | Uint16 all; 61 | struct QEPCTL_BITS bit; 62 | }; 63 | 64 | 65 | //---------------------------------------------------- 66 | // Quadrature capture control register bit definitions */ 67 | struct QCAPCTL_BITS { // bits description 68 | Uint16 UPPS:4; // 3:0 Unit position pre-scale 69 | Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale 70 | Uint16 rsvd1:8; // 14:7 reserved 71 | Uint16 CEN:1; // 15 Enable QEP capture 72 | }; 73 | 74 | 75 | union QCAPCTL_REG { 76 | Uint16 all; 77 | struct QCAPCTL_BITS bit; 78 | }; 79 | 80 | 81 | 82 | //---------------------------------------------------- 83 | // Position compare control register bit definitions */ 84 | struct QPOSCTL_BITS { // bits description 85 | Uint16 PCSPW:12; // 11:0 Position compare sync pulse width 86 | Uint16 PCE:1; // 12 Position compare enable/disable 87 | Uint16 PCPOL:1; // 13 Polarity of sync output 88 | Uint16 PCLOAD:1; // 14 Position compare of shadow load 89 | Uint16 PCSHDW:1; // 15 Position compare shadow enable 90 | }; 91 | 92 | union QPOSCTL_REG { 93 | Uint16 all; 94 | struct QPOSCTL_BITS bit; 95 | }; 96 | 97 | //---------------------------------------------------- 98 | // QEP interrupt control register bit definitions */ 99 | struct QEINT_BITS { // bits description 100 | Uint16 rsvd1:1; // 0 reserved 101 | Uint16 PCE:1; // 1 Position counter error 102 | Uint16 QPE:1; // 2 Quadrature phase error 103 | Uint16 QDC:1; // 3 Quadrature dir change 104 | Uint16 WTO:1; // 4 Watchdog timeout 105 | Uint16 PCU:1; // 5 Position counter underflow 106 | Uint16 PCO:1; // 6 Position counter overflow 107 | Uint16 PCR:1; // 7 Position compare ready 108 | Uint16 PCM:1; // 8 Position compare match 109 | Uint16 SEL:1; // 9 Strobe event latch 110 | Uint16 IEL:1; // 10 Event latch 111 | Uint16 UTO:1; // 11 Unit timeout 112 | Uint16 rsvd2:4; // 15:12 reserved 113 | }; 114 | 115 | 116 | union QEINT_REG { 117 | Uint16 all; 118 | struct QEINT_BITS bit; 119 | }; 120 | 121 | 122 | //---------------------------------------------------- 123 | // QEP interrupt status register bit definitions */ 124 | struct QFLG_BITS { // bits description 125 | Uint16 INT:1; // 0 Global interrupt 126 | Uint16 PCE:1; // 1 Position counter error 127 | Uint16 PHE:1; // 2 Quadrature phase error 128 | Uint16 QDC:1; // 3 Quadrature dir change 129 | Uint16 WTO:1; // 4 Watchdog timeout 130 | Uint16 PCU:1; // 5 Position counter underflow 131 | Uint16 PCO:1; // 6 Position counter overflow 132 | Uint16 PCR:1; // 7 Position compare ready 133 | Uint16 PCM:1; // 8 Position compare match 134 | Uint16 SEL:1; // 9 Strobe event latch 135 | Uint16 IEL:1; // 10 Event latch 136 | Uint16 UTO:1; // 11 Unit timeout 137 | Uint16 rsvd2:4; // 15:12 reserved 138 | }; 139 | 140 | 141 | union QFLG_REG { 142 | Uint16 all; 143 | struct QFLG_BITS bit; 144 | }; 145 | 146 | //---------------------------------------------------- 147 | // QEP interrupt force register bit definitions */ 148 | struct QFRC_BITS { // bits description 149 | Uint16 reserved:1; // 0 Reserved 150 | Uint16 PCE:1; // 1 Position counter error 151 | Uint16 PHE:1; // 2 Quadrature phase error 152 | Uint16 QDC:1; // 3 Quadrature dir change 153 | Uint16 WTO:1; // 4 Watchdog timeout 154 | Uint16 PCU:1; // 5 Position counter underflow 155 | Uint16 PCO:1; // 6 Position counter overflow 156 | Uint16 PCR:1; // 7 Position compare ready 157 | Uint16 PCM:1; // 8 Position compare match 158 | Uint16 SEL:1; // 9 Strobe event latch 159 | Uint16 IEL:1; // 10 Event latch 160 | Uint16 UTO:1; // 11 Unit timeout 161 | Uint16 rsvd2:4; // 15:12 reserved 162 | }; 163 | 164 | 165 | union QFRC_REG { 166 | Uint16 all; 167 | struct QFRC_BITS bit; 168 | }; 169 | 170 | // V1.1 Added UPEVNT (bit 7) This reflects changes 171 | // made as of F2833x Rev A devices 172 | //---------------------------------------------------- 173 | // QEP status register bit definitions */ 174 | struct QEPSTS_BITS { // bits description 175 | Uint16 PCEF:1; // 0 Position counter error 176 | Uint16 FIMF:1; // 1 First index marker 177 | Uint16 CDEF:1; // 2 Capture direction error 178 | Uint16 COEF:1; // 3 Capture overflow error 179 | Uint16 QDLF:1; // 4 QEP direction latch 180 | Uint16 QDF:1; // 5 Quadrature direction 181 | Uint16 FIDF:1; // 6 Direction on first index marker 182 | Uint16 UPEVNT:1; // 7 Unit position event flag 183 | Uint16 rsvd1:8; // 15:8 reserved 184 | }; 185 | 186 | union QEPSTS_REG { 187 | Uint16 all; 188 | struct QEPSTS_BITS bit; 189 | }; 190 | 191 | //---------------------------------------------------- 192 | 193 | struct EQEP_REGS { 194 | Uint32 QPOSCNT; // Position counter 195 | Uint32 QPOSINIT; // Position counter init 196 | Uint32 QPOSMAX; // Maximum position count 197 | Uint32 QPOSCMP; // Position compare 198 | Uint32 QPOSILAT; // Index position latch 199 | Uint32 QPOSSLAT; // Strobe position latch 200 | Uint32 QPOSLAT; // Position latch 201 | Uint32 QUTMR; // Unit timer 202 | Uint32 QUPRD; // Unit period 203 | Uint16 QWDTMR; // QEP watchdog timer 204 | Uint16 QWDPRD; // QEP watchdog period 205 | union QDECCTL_REG QDECCTL; // Quadrature decoder control 206 | union QEPCTL_REG QEPCTL; // QEP control 207 | union QCAPCTL_REG QCAPCTL; // Quadrature capture control 208 | union QPOSCTL_REG QPOSCTL; // Position compare control 209 | union QEINT_REG QEINT; // QEP interrupt control 210 | union QFLG_REG QFLG; // QEP interrupt flag 211 | union QFLG_REG QCLR; // QEP interrupt clear 212 | union QFRC_REG QFRC; // QEP interrupt force 213 | union QEPSTS_REG QEPSTS; // QEP status 214 | Uint16 QCTMR; // QEP capture timer 215 | Uint16 QCPRD; // QEP capture period 216 | Uint16 QCTMRLAT; // QEP capture latch 217 | Uint16 QCPRDLAT; // QEP capture period latch 218 | Uint16 rsvd1[30]; // reserved 219 | }; 220 | 221 | 222 | 223 | 224 | //--------------------------------------------------------------------------- 225 | // GPI/O External References & Function Declarations: 226 | // 227 | extern volatile struct EQEP_REGS EQep1Regs; 228 | extern volatile struct EQEP_REGS EQep2Regs; 229 | 230 | 231 | 232 | #ifdef __cplusplus 233 | } 234 | #endif /* extern "C" */ 235 | 236 | #endif // end of DSP2833x_EQEP_H definition 237 | 238 | //=========================================================================== 239 | // End of file. 240 | //=========================================================================== 241 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Examples.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Examples.h 4 | // 5 | // TITLE: DSP2833x Device Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_EXAMPLES_H 13 | #define DSP2833x_EXAMPLES_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | 21 | /*----------------------------------------------------------------------------- 22 | Specify the PLL control register (PLLCR) and divide select (DIVSEL) value. 23 | -----------------------------------------------------------------------------*/ 24 | //#define DSP28_DIVSEL 0 // Enable /4 for SYSCLKOUT 25 | //#define DSP28_DIVSEL 1 // Enable /4 for SYSCKOUT 26 | #define DSP28_DIVSEL 2 // Enable /2 for SYSCLKOUT 27 | //#define DSP28_DIVSEL 3 // Enable /1 for SYSCLKOUT 28 | 29 | #define DSP28_PLLCR 10 30 | //#define DSP28_PLLCR 9 31 | //#define DSP28_PLLCR 8 32 | //#define DSP28_PLLCR 7 33 | //#define DSP28_PLLCR 6 34 | //#define DSP28_PLLCR 5 35 | //#define DSP28_PLLCR 4 36 | //#define DSP28_PLLCR 3 37 | //#define DSP28_PLLCR 2 38 | //#define DSP28_PLLCR 1 39 | //#define DSP28_PLLCR 0 // PLL is bypassed in this mode 40 | //---------------------------------------------------------------------------- 41 | 42 | 43 | /*----------------------------------------------------------------------------- 44 | Specify the clock rate of the CPU (SYSCLKOUT) in nS. 45 | 46 | Take into account the input clock frequency and the PLL multiplier 47 | selected in step 1. 48 | 49 | Use one of the values provided, or define your own. 50 | The trailing L is required tells the compiler to treat 51 | the number as a 64-bit value. 52 | 53 | Only one statement should be uncommented. 54 | 55 | Example 1:150 MHz devices: 56 | CLKIN is a 30MHz crystal. 57 | 58 | In step 1 the user specified PLLCR = 0xA for a 59 | 150Mhz CPU clock (SYSCLKOUT = 150MHz). 60 | 61 | In this case, the CPU_RATE will be 6.667L 62 | Uncomment the line: #define CPU_RATE 6.667L 63 | 64 | Example 2: 100 MHz devices: 65 | CLKIN is a 20MHz crystal. 66 | 67 | In step 1 the user specified PLLCR = 0xA for a 68 | 100Mhz CPU clock (SYSCLKOUT = 100MHz). 69 | 70 | In this case, the CPU_RATE will be 10.000L 71 | Uncomment the line: #define CPU_RATE 10.000L 72 | -----------------------------------------------------------------------------*/ 73 | #define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) 74 | //#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) 75 | //#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) 76 | //#define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 77 | //#define CPU_RATE 12.500L // for a 80MHz CPU clock speed (SYSCLKOUT) 78 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 79 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 80 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 81 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 82 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 83 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 84 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 85 | 86 | //---------------------------------------------------------------------------- 87 | 88 | /*----------------------------------------------------------------------------- 89 | Target device (in DSP2833x_Device.h) determines CPU frequency 90 | (for examples) - either 150 MHz (for 28335 and 28334) or 100 MHz 91 | (for 28332). User does not have to change anything here. 92 | -----------------------------------------------------------------------------*/ 93 | #if DSP28_28332 // DSP28_28332 device only 94 | #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq (20 MHz input freq) 95 | #define CPU_FRQ_150MHZ 0 96 | #else 97 | #define CPU_FRQ_100MHZ 0 // DSP28_28335||DSP28_28334 98 | #define CPU_FRQ_150MHZ 1 // 150 MHz CPU Freq (30 MHz input freq) by DEFAULT 99 | #endif 100 | 101 | 102 | //--------------------------------------------------------------------------- 103 | // Include Example Header Files: 104 | // 105 | 106 | #include "DSP2833x_GlobalPrototypes.h" // Prototypes for global functions within the 107 | // .c files. 108 | 109 | #include "DSP2833x_ePwm_defines.h" // Macros used for PWM examples. 110 | #include "DSP2833x_Dma_defines.h" // Macros used for DMA examples. 111 | #include "DSP2833x_I2C_defines.h" // Macros used for I2C examples. 112 | 113 | #define PARTNO_28335 0xEF 114 | #define PARTNO_28334 0xEE 115 | #define PARTNO_28332 0xED 116 | #define PARTNO_28235 0xE8 117 | #define PARTNO_28234 0xE7 118 | #define PARTNO_28232 0xE6 119 | 120 | 121 | // Include files not used with DSP/BIOS 122 | #ifndef DSP28_BIOS 123 | #include "DSP2833x_DefaultISR.h" 124 | #endif 125 | 126 | 127 | // DO NOT MODIFY THIS LINE. 128 | #define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) 129 | 130 | 131 | #ifdef __cplusplus 132 | } 133 | #endif /* extern "C" */ 134 | 135 | #endif // end of DSP2833x_EXAMPLES_H definition 136 | 137 | 138 | //=========================================================================== 139 | // End of file. 140 | //=========================================================================== 141 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_GlobalPrototypes.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_GlobalPrototypes.h 4 | // 5 | // TITLE: Global prototypes for DSP2833x Examples 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_GLOBALPROTOTYPES_H 13 | #define DSP2833x_GLOBALPROTOTYPES_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | /*---- shared global function prototypes -----------------------------------*/ 21 | extern void InitAdc(void); 22 | 23 | extern void DMAInitialize(void); 24 | // DMA Channel 1 25 | extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 26 | extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); 27 | extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 28 | extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 29 | extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 30 | extern void StartDMACH1(void); 31 | // DMA Channel 2 32 | extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 33 | extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); 34 | extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 35 | extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 36 | extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 37 | extern void StartDMACH2(void); 38 | // DMA Channel 3 39 | extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 40 | extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); 41 | extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 42 | extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 43 | extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 44 | extern void StartDMACH3(void); 45 | // DMA Channel 4 46 | extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 47 | extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); 48 | extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 49 | extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 50 | extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 51 | extern void StartDMACH4(void); 52 | // DMA Channel 5 53 | extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 54 | extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); 55 | extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 56 | extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 57 | extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 58 | extern void StartDMACH5(void); 59 | // DMA Channel 6 60 | extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source); 61 | extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); 62 | extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); 63 | extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, int16 deswstep); 64 | extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, Uint16 cont, Uint16 synce, Uint16 syncsel, Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, Uint16 chinte); 65 | extern void StartDMACH6(void); 66 | 67 | extern void InitPeripherals(void); 68 | #if DSP28_ECANA 69 | extern void InitECan(void); 70 | extern void InitECana(void); 71 | extern void InitECanGpio(void); 72 | extern void InitECanaGpio(void); 73 | #endif // endif DSP28_ECANA 74 | #if DSP28_ECANB 75 | extern void InitECanb(void); 76 | extern void InitECanbGpio(void); 77 | #endif // endif DSP28_ECANB 78 | extern void InitECap(void); 79 | extern void InitECapGpio(void); 80 | extern void InitECap1Gpio(void); 81 | extern void InitECap2Gpio(void); 82 | #if DSP28_ECAP3 83 | extern void InitECap3Gpio(void); 84 | #endif // endif DSP28_ECAP3 85 | #if DSP28_ECAP4 86 | extern void InitECap4Gpio(void); 87 | #endif // endif DSP28_ECAP4 88 | #if DSP28_ECAP5 89 | extern void InitECap5Gpio(void); 90 | #endif // endif DSP28_ECAP5 91 | #if DSP28_ECAP6 92 | extern void InitECap6Gpio(void); 93 | #endif // endif DSP28_ECAP6 94 | extern void InitEPwm(void); 95 | extern void InitEPwmGpio(void); 96 | extern void InitEPwm1Gpio(void); 97 | extern void InitEPwm2Gpio(void); 98 | extern void InitEPwm3Gpio(void); 99 | #if DSP28_EPWM4 100 | extern void InitEPwm4Gpio(void); 101 | #endif // endif DSP28_EPWM4 102 | #if DSP28_EPWM5 103 | extern void InitEPwm5Gpio(void); 104 | #endif // endif DSP28_EPWM5 105 | #if DSP28_EPWM6 106 | extern void InitEPwm6Gpio(void); 107 | #endif // endif DSP28_EPWM6 108 | #if DSP28_EQEP1 109 | extern void InitEQep(void); 110 | extern void InitEQepGpio(void); 111 | extern void InitEQep1Gpio(void); 112 | #endif // if DSP28_EQEP1 113 | #if DSP28_EQEP2 114 | extern void InitEQep2Gpio(void); 115 | #endif // endif DSP28_EQEP2 116 | extern void InitGpio(void); 117 | extern void InitI2CGpio(void); 118 | 119 | extern void InitMcbsp(void); 120 | extern void InitMcbspa(void); 121 | extern void delay_loop(void); 122 | extern void InitMcbspaGpio(void); 123 | extern void InitMcbspa8bit(void); 124 | extern void InitMcbspa12bit(void); 125 | extern void InitMcbspa16bit(void); 126 | extern void InitMcbspa20bit(void); 127 | extern void InitMcbspa24bit(void); 128 | extern void InitMcbspa32bit(void); 129 | #if DSP28_MCBSPB 130 | extern void InitMcbspb(void); 131 | extern void InitMcbspbGpio(void); 132 | extern void InitMcbspb8bit(void); 133 | extern void InitMcbspb12bit(void); 134 | extern void InitMcbspb16bit(void); 135 | extern void InitMcbspb20bit(void); 136 | extern void InitMcbspb24bit(void); 137 | extern void InitMcbspb32bit(void); 138 | #endif // endif DSP28_MCBSPB 139 | 140 | extern void InitPieCtrl(void); 141 | extern void InitPieVectTable(void); 142 | 143 | extern void InitSci(void); 144 | extern void InitSciGpio(void); 145 | extern void InitSciaGpio(void); 146 | #if DSP28_SCIB 147 | extern void InitScibGpio(void); 148 | #endif // endif DSP28_SCIB 149 | #if DSP28_SCIC 150 | extern void InitScicGpio(void); 151 | #endif 152 | extern void InitSpi(void); 153 | extern void InitSpiGpio(void); 154 | extern void InitSpiaGpio(void); 155 | extern void InitSysCtrl(void); 156 | extern void InitTzGpio(void); 157 | extern void InitXIntrupt(void); 158 | extern void XintfInit(void); 159 | extern void InitXintf16Gpio(); 160 | extern void InitXintf32Gpio(); 161 | extern void InitPll(Uint16 pllcr, Uint16 clkindiv); 162 | extern void InitPeripheralClocks(void); 163 | extern void EnableInterrupts(void); 164 | extern void DSP28x_usDelay(Uint32 Count); 165 | extern void ADC_cal (void); 166 | #define KickDog ServiceDog // For compatiblity with previous versions 167 | extern void ServiceDog(void); 168 | extern void DisableDog(void); 169 | extern Uint16 CsmUnlock(void); 170 | 171 | // DSP28_DBGIER.asm 172 | extern void SetDBGIER(Uint16 dbgier); 173 | 174 | // CAUTION 175 | // This function MUST be executed out of RAM. Executing it 176 | // out of OTP/Flash will yield unpredictable results 177 | extern void InitFlash(void); 178 | 179 | 180 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); 181 | 182 | 183 | //--------------------------------------------------------------------------- 184 | // External symbols created by the linker cmd file 185 | // DSP28 examples will use these to relocate code from one LOAD location 186 | // in either Flash or XINTF to a different RUN location in internal 187 | // RAM 188 | extern Uint16 RamfuncsLoadStart; 189 | extern Uint16 RamfuncsLoadEnd; 190 | extern Uint16 RamfuncsRunStart; 191 | 192 | extern Uint16 XintffuncsLoadStart; 193 | extern Uint16 XintffuncsLoadEnd; 194 | extern Uint16 XintffuncsRunStart; 195 | 196 | 197 | #ifdef __cplusplus 198 | } 199 | #endif /* extern "C" */ 200 | 201 | #endif // - end of DSP2833x_GLOBALPROTOTYPES_H 202 | 203 | //=========================================================================== 204 | // End of file. 205 | //=========================================================================== 206 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_I2c.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_I2c.h 4 | // 5 | // TITLE: DSP2833x Enhanced Quadrature Encoder Pulse Module 6 | // Register Bit Definitions. 7 | // 8 | //########################################################################### 9 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 10 | // $Release Date: June 8, 2012 $ 11 | //########################################################################### 12 | 13 | #ifndef DSP2833x_I2C_H 14 | #define DSP2833x_I2C_H 15 | 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | 22 | //---------------------------------------------------- 23 | // I2C interrupt vector register bit definitions */ 24 | struct I2CISRC_BITS { // bits description 25 | Uint16 INTCODE:3; // 2:0 Interrupt code 26 | Uint16 rsvd1:13; // 15:3 reserved 27 | }; 28 | 29 | union I2CISRC_REG { 30 | Uint16 all; 31 | struct I2CISRC_BITS bit; 32 | }; 33 | 34 | //---------------------------------------------------- 35 | // I2C interrupt mask register bit definitions */ 36 | struct I2CIER_BITS { // bits description 37 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 38 | Uint16 NACK:1; // 1 No ack interrupt 39 | Uint16 ARDY:1; // 2 Register access ready interrupt 40 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 41 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 42 | Uint16 SCD:1; // 5 Stop condition detection 43 | Uint16 AAS:1; // 6 Address as slave 44 | Uint16 rsvd:9; // 15:7 reserved 45 | }; 46 | 47 | union I2CIER_REG { 48 | Uint16 all; 49 | struct I2CIER_BITS bit; 50 | }; 51 | 52 | //---------------------------------------------------- 53 | // I2C status register bit definitions */ 54 | struct I2CSTR_BITS { // bits description 55 | Uint16 ARBL:1; // 0 Arbitration lost interrupt 56 | Uint16 NACK:1; // 1 No ack interrupt 57 | Uint16 ARDY:1; // 2 Register access ready interrupt 58 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 59 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 60 | Uint16 SCD:1; // 5 Stop condition detection 61 | Uint16 rsvd1:2; // 7:6 reserved 62 | Uint16 AD0:1; // 8 Address Zero 63 | Uint16 AAS:1; // 9 Address as slave 64 | Uint16 XSMT:1; // 10 XMIT shift empty 65 | Uint16 RSFULL:1; // 11 Recieve shift full 66 | Uint16 BB:1; // 12 Bus busy 67 | Uint16 NACKSNT:1; // 13 A no ack sent 68 | Uint16 SDIR:1; // 14 Slave direction 69 | Uint16 rsvd2:1; // 15 reserved 70 | }; 71 | 72 | union I2CSTR_REG { 73 | Uint16 all; 74 | struct I2CSTR_BITS bit; 75 | }; 76 | 77 | 78 | //---------------------------------------------------- 79 | // I2C mode control register bit definitions */ 80 | struct I2CMDR_BITS { // bits description 81 | Uint16 BC:3; // 2:0 Bit count 82 | Uint16 FDF:1; // 3 Free data format 83 | Uint16 STB:1; // 4 Start byte 84 | Uint16 IRS:1; // 5 I2C Reset not 85 | Uint16 DLB:1; // 6 Digital loopback 86 | Uint16 RM:1; // 7 Repeat mode 87 | Uint16 XA:1; // 8 Expand address 88 | Uint16 TRX:1; // 9 Transmitter/reciever 89 | Uint16 MST:1; // 10 Master/slave 90 | Uint16 STP:1; // 11 Stop condition 91 | Uint16 rsvd1:1; // 12 reserved 92 | Uint16 STT:1; // 13 Start condition 93 | Uint16 FREE:1; // 14 Emulation mode 94 | Uint16 NACKMOD:1; // 15 No Ack mode 95 | }; 96 | 97 | union I2CMDR_REG { 98 | Uint16 all; 99 | struct I2CMDR_BITS bit; 100 | }; 101 | 102 | //---------------------------------------------------- 103 | // I2C pre-scaler register bit definitions */ 104 | struct I2CPSC_BITS { // bits description 105 | Uint16 IPSC:8; // 7:0 pre-scaler 106 | Uint16 rsvd1:8; // 15:8 reserved 107 | }; 108 | 109 | 110 | union I2CPSC_REG { 111 | Uint16 all; 112 | struct I2CPSC_BITS bit; 113 | }; 114 | 115 | 116 | //---------------------------------------------------- 117 | // TX FIFO control register bit definitions */ 118 | struct I2CFFTX_BITS { // bits description 119 | Uint16 TXFFIL:5; // 4:0 FIFO interrupt level 120 | Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable 121 | Uint16 TXFFINTCLR:1; // 6 FIFO clear 122 | Uint16 TXFFINT:1; // 7 FIFO interrupt flag 123 | Uint16 TXFFST:5; // 12:8 FIFO level status 124 | Uint16 TXFFRST:1; // 13 FIFO reset 125 | Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs 126 | Uint16 rsvd1:1; // 15 reserved 127 | 128 | }; 129 | 130 | union I2CFFTX_REG { 131 | Uint16 all; 132 | struct I2CFFTX_BITS bit; 133 | }; 134 | 135 | //---------------------------------------------------- 136 | // RX FIFO control register bit definitions */ 137 | struct I2CFFRX_BITS { // bits description 138 | Uint16 RXFFIL:5; // 4:0 FIFO interrupt level 139 | Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable 140 | Uint16 RXFFINTCLR:1; // 6 FIFO clear 141 | Uint16 RXFFINT:1; // 7 FIFO interrupt flag 142 | Uint16 RXFFST:5; // 12:8 FIFO level 143 | Uint16 RXFFRST:1; // 13 FIFO reset 144 | Uint16 rsvd1:2; // 15:14 reserved 145 | }; 146 | 147 | union I2CFFRX_REG { 148 | Uint16 all; 149 | struct I2CFFRX_BITS bit; 150 | }; 151 | 152 | 153 | //---------------------------------------------------- 154 | 155 | struct I2C_REGS { 156 | Uint16 I2COAR; // Own address register 157 | union I2CIER_REG I2CIER; // Interrupt enable 158 | union I2CSTR_REG I2CSTR; // Interrupt status 159 | Uint16 I2CCLKL; // Clock divider low 160 | Uint16 I2CCLKH; // Clock divider high 161 | Uint16 I2CCNT; // Data count 162 | Uint16 I2CDRR; // Data recieve 163 | Uint16 I2CSAR; // Slave address 164 | Uint16 I2CDXR; // Data transmit 165 | union I2CMDR_REG I2CMDR; // Mode 166 | union I2CISRC_REG I2CISRC; // Interrupt source 167 | Uint16 rsvd1; // reserved 168 | union I2CPSC_REG I2CPSC; // Pre-scaler 169 | Uint16 rsvd2[19]; // reserved 170 | union I2CFFTX_REG I2CFFTX; // Transmit FIFO 171 | union I2CFFRX_REG I2CFFRX; // Recieve FIFO 172 | }; 173 | 174 | 175 | 176 | 177 | //--------------------------------------------------------------------------- 178 | // External References & Function Declarations: 179 | // 180 | extern volatile struct I2C_REGS I2caRegs; 181 | 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif /* extern "C" */ 186 | 187 | #endif // end of DSP2833x_I2C_H definition 188 | 189 | //=========================================================================== 190 | // End of file. 191 | //=========================================================================== 192 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_I2c_defines.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_I2cExample.h 4 | // 5 | // TITLE: 2833x I2C Example Code Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_I2C_DEFINES_H 13 | #define DSP2833x_I2C_DEFINES_H 14 | 15 | //-------------------------------------------- 16 | // Defines 17 | //-------------------------------------------- 18 | 19 | // Error Messages 20 | #define I2C_ERROR 0xFFFF 21 | #define I2C_ARB_LOST_ERROR 0x0001 22 | #define I2C_NACK_ERROR 0x0002 23 | #define I2C_BUS_BUSY_ERROR 0x1000 24 | #define I2C_STP_NOT_READY_ERROR 0x5555 25 | #define I2C_NO_FLAGS 0xAAAA 26 | #define I2C_SUCCESS 0x0000 27 | 28 | // Clear Status Flags 29 | #define I2C_CLR_AL_BIT 0x0001 30 | #define I2C_CLR_NACK_BIT 0x0002 31 | #define I2C_CLR_ARDY_BIT 0x0004 32 | #define I2C_CLR_RRDY_BIT 0x0008 33 | #define I2C_CLR_SCD_BIT 0x0020 34 | 35 | // Interrupt Source Messages 36 | #define I2C_NO_ISRC 0x0000 37 | #define I2C_ARB_ISRC 0x0001 38 | #define I2C_NACK_ISRC 0x0002 39 | #define I2C_ARDY_ISRC 0x0003 40 | #define I2C_RX_ISRC 0x0004 41 | #define I2C_TX_ISRC 0x0005 42 | #define I2C_SCD_ISRC 0x0006 43 | #define I2C_AAS_ISRC 0x0007 44 | 45 | // I2CMSG structure defines 46 | #define I2C_NO_STOP 0 47 | #define I2C_YES_STOP 1 48 | #define I2C_RECEIVE 0 49 | #define I2C_TRANSMIT 1 50 | #define I2C_MAX_BUFFER_SIZE 16 51 | 52 | // I2C Slave State defines 53 | #define I2C_NOTSLAVE 0 54 | #define I2C_ADDR_AS_SLAVE 1 55 | #define I2C_ST_MSG_READY 2 56 | 57 | // I2C Slave Receiver messages defines 58 | #define I2C_SND_MSG1 1 59 | #define I2C_SND_MSG2 2 60 | 61 | // I2C State defines 62 | #define I2C_IDLE 0 63 | #define I2C_SLAVE_RECEIVER 1 64 | #define I2C_SLAVE_TRANSMITTER 2 65 | #define I2C_MASTER_RECEIVER 3 66 | #define I2C_MASTER_TRANSMITTER 4 67 | 68 | // I2C Message Commands for I2CMSG struct 69 | #define I2C_MSGSTAT_INACTIVE 0x0000 70 | #define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 71 | #define I2C_MSGSTAT_WRITE_BUSY 0x0011 72 | #define I2C_MSGSTAT_SEND_NOSTOP 0x0020 73 | #define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 74 | #define I2C_MSGSTAT_RESTART 0x0022 75 | #define I2C_MSGSTAT_READ_BUSY 0x0023 76 | 77 | // Generic defines 78 | #define I2C_TRUE 1 79 | #define I2C_FALSE 0 80 | #define I2C_YES 1 81 | #define I2C_NO 0 82 | #define I2C_DUMMY_BYTE 0 83 | //byte bits defines 84 | #define IIC_byte_1bits 1 85 | #define IIC_byte_2bits 2 86 | #define IIC_byte_3bits 3 87 | #define IIC_byte_4bits 4 88 | #define IIC_byte_5bits 5 89 | #define IIC_byte_6bits 6 90 | #define IIC_byte_7bits 7 91 | #define IIC_byte_8bits 0 92 | //-------------------------------------------- 93 | // Structures 94 | //-------------------------------------------- 95 | 96 | // I2C Message Structure 97 | struct I2CMSG { 98 | Uint16 MsgStatus; // Word stating what state msg is in: 99 | // I2C_MSGCMD_INACTIVE = do not send msg 100 | // I2C_MSGCMD_BUSY = msg start has been sent, 101 | // awaiting stop 102 | // I2C_MSGCMD_SEND_WITHSTOP = command to send 103 | // master trans msg complete with a stop bit 104 | // I2C_MSGCMD_SEND_NOSTOP = command to send 105 | // master trans msg without the stop bit 106 | // I2C_MSGCMD_RESTART = command to send a restart 107 | // as a master receiver with a stop bit 108 | Uint16 SlaveAddress; // I2C address of slave msg is intended for 109 | Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) 110 | Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) 111 | Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) 112 | Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that 113 | // MAX_BUFFER_SIZE can be is 16 due to 114 | // the FIFO's 115 | }; 116 | 117 | 118 | #endif // end of DSP2833x_I2C_DEFINES_H definition 119 | 120 | //=========================================================================== 121 | // End of file. 122 | //=========================================================================== 123 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_PieCtrl.h 4 | // 5 | // TITLE: DSP2833x Device PIE Control Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | 13 | #ifndef DSP2833x_PIE_CTRL_H 14 | #define DSP2833x_PIE_CTRL_H 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | //--------------------------------------------------------------------------- 21 | // PIE Control Register Bit Definitions: 22 | // 23 | // PIECTRL: Register bit definitions: 24 | struct PIECTRL_BITS { // bits description 25 | Uint16 ENPIE:1; // 0 Enable PIE block 26 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 27 | }; 28 | 29 | union PIECTRL_REG { 30 | Uint16 all; 31 | struct PIECTRL_BITS bit; 32 | }; 33 | 34 | // PIEIER: Register bit definitions: 35 | struct PIEIER_BITS { // bits description 36 | Uint16 INTx1:1; // 0 INTx.1 37 | Uint16 INTx2:1; // 1 INTx.2 38 | Uint16 INTx3:1; // 2 INTx.3 39 | Uint16 INTx4:1; // 3 INTx.4 40 | Uint16 INTx5:1; // 4 INTx.5 41 | Uint16 INTx6:1; // 5 INTx.6 42 | Uint16 INTx7:1; // 6 INTx.7 43 | Uint16 INTx8:1; // 7 INTx.8 44 | Uint16 rsvd:8; // 15:8 reserved 45 | }; 46 | 47 | union PIEIER_REG { 48 | Uint16 all; 49 | struct PIEIER_BITS bit; 50 | }; 51 | 52 | // PIEIFR: Register bit definitions: 53 | struct PIEIFR_BITS { // bits description 54 | Uint16 INTx1:1; // 0 INTx.1 55 | Uint16 INTx2:1; // 1 INTx.2 56 | Uint16 INTx3:1; // 2 INTx.3 57 | Uint16 INTx4:1; // 3 INTx.4 58 | Uint16 INTx5:1; // 4 INTx.5 59 | Uint16 INTx6:1; // 5 INTx.6 60 | Uint16 INTx7:1; // 6 INTx.7 61 | Uint16 INTx8:1; // 7 INTx.8 62 | Uint16 rsvd:8; // 15:8 reserved 63 | }; 64 | 65 | union PIEIFR_REG { 66 | Uint16 all; 67 | struct PIEIFR_BITS bit; 68 | }; 69 | 70 | // PIEACK: Register bit definitions: 71 | struct PIEACK_BITS { // bits description 72 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 73 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 74 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 75 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 76 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 77 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 78 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 79 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 80 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 81 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 82 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 83 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 84 | Uint16 rsvd:4; // 15:12 reserved 85 | }; 86 | 87 | union PIEACK_REG { 88 | Uint16 all; 89 | struct PIEACK_BITS bit; 90 | }; 91 | 92 | //--------------------------------------------------------------------------- 93 | // PIE Control Register File: 94 | // 95 | struct PIE_CTRL_REGS { 96 | union PIECTRL_REG PIECTRL; // PIE control register 97 | union PIEACK_REG PIEACK; // PIE acknowledge 98 | union PIEIER_REG PIEIER1; // PIE int1 IER register 99 | union PIEIFR_REG PIEIFR1; // PIE int1 IFR register 100 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 101 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 102 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 103 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 104 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 105 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 106 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 107 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 108 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 109 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 110 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 111 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 112 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 113 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 114 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 115 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 116 | union PIEIER_REG PIEIER10; // PIE int10 IER register 117 | union PIEIFR_REG PIEIFR10; // PIE int10 IFR register 118 | union PIEIER_REG PIEIER11; // PIE int11 IER register 119 | union PIEIFR_REG PIEIFR11; // PIE int11 IFR register 120 | union PIEIER_REG PIEIER12; // PIE int12 IER register 121 | union PIEIFR_REG PIEIFR12; // PIE int12 IFR register 122 | }; 123 | 124 | #define PIEACK_GROUP1 0x0001 125 | #define PIEACK_GROUP2 0x0002 126 | #define PIEACK_GROUP3 0x0004 127 | #define PIEACK_GROUP4 0x0008 128 | #define PIEACK_GROUP5 0x0010 129 | #define PIEACK_GROUP6 0x0020 130 | #define PIEACK_GROUP7 0x0040 131 | #define PIEACK_GROUP8 0x0080 132 | #define PIEACK_GROUP9 0x0100 133 | #define PIEACK_GROUP10 0x0200 134 | #define PIEACK_GROUP11 0x0400 135 | #define PIEACK_GROUP12 0x0800 136 | 137 | //--------------------------------------------------------------------------- 138 | // PIE Control Registers External References & Function Declarations: 139 | // 140 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 141 | 142 | 143 | #ifdef __cplusplus 144 | } 145 | #endif /* extern "C" */ 146 | 147 | #endif // end of DSP2833x_PIE_CTRL_H definition 148 | 149 | //=========================================================================== 150 | // End of file. 151 | //=========================================================================== 152 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_PieVect.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_PieVect.h 4 | // 5 | // TITLE: DSP2833x Devices PIE Vector Table Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_PIE_VECT_H 13 | #define DSP2833x_PIE_VECT_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | 21 | //--------------------------------------------------------------------------- 22 | // PIE Interrupt Vector Table Definition: 23 | // 24 | // Create a user type called PINT (pointer to interrupt): 25 | 26 | typedef interrupt void(*PINT)(void); 27 | 28 | // Define Vector Table: 29 | struct PIE_VECT_TABLE { 30 | 31 | // Reset is never fetched from this table. 32 | // It will always be fetched from 0x3FFFC0 in 33 | // boot ROM 34 | 35 | PINT PIE1_RESERVED; 36 | PINT PIE2_RESERVED; 37 | PINT PIE3_RESERVED; 38 | PINT PIE4_RESERVED; 39 | PINT PIE5_RESERVED; 40 | PINT PIE6_RESERVED; 41 | PINT PIE7_RESERVED; 42 | PINT PIE8_RESERVED; 43 | PINT PIE9_RESERVED; 44 | PINT PIE10_RESERVED; 45 | PINT PIE11_RESERVED; 46 | PINT PIE12_RESERVED; 47 | PINT PIE13_RESERVED; 48 | 49 | // Non-Peripheral Interrupts: 50 | PINT XINT13; // XINT13 / CPU-Timer1 51 | PINT TINT2; // CPU-Timer2 52 | PINT DATALOG; // Datalogging interrupt 53 | PINT RTOSINT; // RTOS interrupt 54 | PINT EMUINT; // Emulation interrupt 55 | PINT XNMI; // Non-maskable interrupt 56 | PINT ILLEGAL; // Illegal operation TRAP 57 | PINT USER1; // User Defined trap 1 58 | PINT USER2; // User Defined trap 2 59 | PINT USER3; // User Defined trap 3 60 | PINT USER4; // User Defined trap 4 61 | PINT USER5; // User Defined trap 5 62 | PINT USER6; // User Defined trap 6 63 | PINT USER7; // User Defined trap 7 64 | PINT USER8; // User Defined trap 8 65 | PINT USER9; // User Defined trap 9 66 | PINT USER10; // User Defined trap 10 67 | PINT USER11; // User Defined trap 11 68 | PINT USER12; // User Defined trap 12 69 | 70 | // Group 1 PIE Peripheral Vectors: 71 | PINT SEQ1INT; 72 | PINT SEQ2INT; 73 | PINT rsvd1_3; 74 | PINT XINT1; 75 | PINT XINT2; 76 | PINT ADCINT; // ADC 77 | PINT TINT0; // Timer 0 78 | PINT WAKEINT; // WD 79 | 80 | // Group 2 PIE Peripheral Vectors: 81 | PINT EPWM1_TZINT; // EPWM-1 82 | PINT EPWM2_TZINT; // EPWM-2 83 | PINT EPWM3_TZINT; // EPWM-3 84 | PINT EPWM4_TZINT; // EPWM-4 85 | PINT EPWM5_TZINT; // EPWM-5 86 | PINT EPWM6_TZINT; // EPWM-6 87 | PINT rsvd2_7; 88 | PINT rsvd2_8; 89 | 90 | // Group 3 PIE Peripheral Vectors: 91 | PINT EPWM1_INT; // EPWM-1 92 | PINT EPWM2_INT; // EPWM-2 93 | PINT EPWM3_INT; // EPWM-3 94 | PINT EPWM4_INT; // EPWM-4 95 | PINT EPWM5_INT; // EPWM-5 96 | PINT EPWM6_INT; // EPWM-6 97 | PINT rsvd3_7; 98 | PINT rsvd3_8; 99 | 100 | // Group 4 PIE Peripheral Vectors: 101 | PINT ECAP1_INT; // ECAP-1 102 | PINT ECAP2_INT; // ECAP-2 103 | PINT ECAP3_INT; // ECAP-3 104 | PINT ECAP4_INT; // ECAP-4 105 | PINT ECAP5_INT; // ECAP-5 106 | PINT ECAP6_INT; // ECAP-6 107 | PINT rsvd4_7; 108 | PINT rsvd4_8; 109 | 110 | // Group 5 PIE Peripheral Vectors: 111 | PINT EQEP1_INT; // EQEP-1 112 | PINT EQEP2_INT; // EQEP-2 113 | PINT rsvd5_3; 114 | PINT rsvd5_4; 115 | PINT rsvd5_5; 116 | PINT rsvd5_6; 117 | PINT rsvd5_7; 118 | PINT rsvd5_8; 119 | 120 | // Group 6 PIE Peripheral Vectors: 121 | PINT SPIRXINTA; // SPI-A 122 | PINT SPITXINTA; // SPI-A 123 | PINT MRINTB; // McBSP-B 124 | PINT MXINTB; // McBSP-B 125 | PINT MRINTA; // McBSP-A 126 | PINT MXINTA; // McBSP-A 127 | PINT rsvd6_7; 128 | PINT rsvd6_8; 129 | 130 | // Group 7 PIE Peripheral Vectors: 131 | PINT DINTCH1; // DMA 132 | PINT DINTCH2; // DMA 133 | PINT DINTCH3; // DMA 134 | PINT DINTCH4; // DMA 135 | PINT DINTCH5; // DMA 136 | PINT DINTCH6; // DMA 137 | PINT rsvd7_7; 138 | PINT rsvd7_8; 139 | 140 | // Group 8 PIE Peripheral Vectors: 141 | PINT I2CINT1A; // I2C-A 142 | PINT I2CINT2A; // I2C-A 143 | PINT rsvd8_3; 144 | PINT rsvd8_4; 145 | PINT SCIRXINTC; // SCI-C 146 | PINT SCITXINTC; // SCI-C 147 | PINT rsvd8_7; 148 | PINT rsvd8_8; 149 | 150 | // Group 9 PIE Peripheral Vectors: 151 | PINT SCIRXINTA; // SCI-A 152 | PINT SCITXINTA; // SCI-A 153 | PINT SCIRXINTB; // SCI-B 154 | PINT SCITXINTB; // SCI-B 155 | PINT ECAN0INTA; // eCAN-A 156 | PINT ECAN1INTA; // eCAN-A 157 | PINT ECAN0INTB; // eCAN-B 158 | PINT ECAN1INTB; // eCAN-B 159 | 160 | // Group 10 PIE Peripheral Vectors: 161 | PINT rsvd10_1; 162 | PINT rsvd10_2; 163 | PINT rsvd10_3; 164 | PINT rsvd10_4; 165 | PINT rsvd10_5; 166 | PINT rsvd10_6; 167 | PINT rsvd10_7; 168 | PINT rsvd10_8; 169 | 170 | // Group 11 PIE Peripheral Vectors: 171 | PINT rsvd11_1; 172 | PINT rsvd11_2; 173 | PINT rsvd11_3; 174 | PINT rsvd11_4; 175 | PINT rsvd11_5; 176 | PINT rsvd11_6; 177 | PINT rsvd11_7; 178 | PINT rsvd11_8; 179 | 180 | // Group 12 PIE Peripheral Vectors: 181 | PINT XINT3; // External interrupt 182 | PINT XINT4; 183 | PINT XINT5; 184 | PINT XINT6; 185 | PINT XINT7; 186 | PINT rsvd12_6; 187 | PINT LVF; // Latched overflow 188 | PINT LUF; // Latched underflow 189 | }; 190 | 191 | //--------------------------------------------------------------------------- 192 | // PIE Interrupt Vector Table External References & Function Declarations: 193 | // 194 | extern struct PIE_VECT_TABLE PieVectTable; 195 | 196 | 197 | #ifdef __cplusplus 198 | } 199 | #endif /* extern "C" */ 200 | 201 | #endif // end of DSP2833x_PIE_VECT_H definition 202 | 203 | //=========================================================================== 204 | // End of file. 205 | //=========================================================================== 206 | 207 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Sci.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Sci.h 4 | // 5 | // TITLE: DSP2833x Device SCI Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_SCI_H 13 | #define DSP2833x_SCI_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | //--------------------------------------------------------------------------- 21 | // SCI Individual Register Bit Definitions 22 | 23 | //---------------------------------------------------------- 24 | // SCICCR communication control register bit definitions: 25 | // 26 | 27 | struct SCICCR_BITS { // bit description 28 | Uint16 SCICHAR:3; // 2:0 Character length control 29 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 30 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 31 | Uint16 PARITYENA:1; // 5 Parity enable 32 | Uint16 PARITY:1; // 6 Even or Odd Parity 33 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 34 | Uint16 rsvd1:8; // 15:8 reserved 35 | }; 36 | 37 | 38 | union SCICCR_REG { 39 | Uint16 all; 40 | struct SCICCR_BITS bit; 41 | }; 42 | 43 | //------------------------------------------- 44 | // SCICTL1 control register 1 bit definitions: 45 | // 46 | 47 | struct SCICTL1_BITS { // bit description 48 | Uint16 RXENA:1; // 0 SCI receiver enable 49 | Uint16 TXENA:1; // 1 SCI transmitter enable 50 | Uint16 SLEEP:1; // 2 SCI sleep 51 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 52 | Uint16 rsvd:1; // 4 reserved 53 | Uint16 SWRESET:1; // 5 Software reset 54 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 55 | Uint16 rsvd1:9; // 15:7 reserved 56 | 57 | }; 58 | 59 | union SCICTL1_REG { 60 | Uint16 all; 61 | struct SCICTL1_BITS bit; 62 | }; 63 | 64 | //--------------------------------------------- 65 | // SCICTL2 control register 2 bit definitions: 66 | // 67 | 68 | struct SCICTL2_BITS { // bit description 69 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 70 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 71 | Uint16 rsvd:4; // 5:2 reserved 72 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 73 | Uint16 TXRDY:1; // 7 Transmitter ready flag 74 | Uint16 rsvd1:8; // 15:8 reserved 75 | 76 | }; 77 | 78 | union SCICTL2_REG { 79 | Uint16 all; 80 | struct SCICTL2_BITS bit; 81 | }; 82 | 83 | //--------------------------------------------------- 84 | // SCIRXST Receiver status register bit definitions: 85 | // 86 | 87 | struct SCIRXST_BITS { // bit description 88 | Uint16 rsvd:1; // 0 reserved 89 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 90 | Uint16 PE:1; // 2 Parity error flag 91 | Uint16 OE:1; // 3 Overrun error flag 92 | Uint16 FE:1; // 4 Framing error flag 93 | Uint16 BRKDT:1; // 5 Break-detect flag 94 | Uint16 RXRDY:1; // 6 Receiver ready flag 95 | Uint16 RXERROR:1; // 7 Receiver error flag 96 | 97 | }; 98 | 99 | union SCIRXST_REG { 100 | Uint16 all; 101 | struct SCIRXST_BITS bit; 102 | }; 103 | 104 | //---------------------------------------------------- 105 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: 106 | // 107 | 108 | struct SCIRXBUF_BITS { // bits description 109 | Uint16 RXDT:8; // 7:0 Receive word 110 | Uint16 rsvd:6; // 13:8 reserved 111 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 112 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 113 | }; 114 | 115 | union SCIRXBUF_REG { 116 | Uint16 all; 117 | struct SCIRXBUF_BITS bit; 118 | }; 119 | 120 | //-------------------------------------------------- 121 | // SCIPRI Priority control register bit definitions: 122 | // 123 | // 124 | 125 | struct SCIPRI_BITS { // bit description 126 | Uint16 rsvd:3; // 2:0 reserved 127 | Uint16 FREE:1; // 3 Free emulation suspend mode 128 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 129 | Uint16 rsvd1:3; // 7:5 reserved 130 | }; 131 | 132 | union SCIPRI_REG { 133 | Uint16 all; 134 | struct SCIPRI_BITS bit; 135 | }; 136 | 137 | //------------------------------------------------- 138 | // SCI FIFO Transmit register bit definitions: 139 | // 140 | // 141 | 142 | struct SCIFFTX_BITS { // bit description 143 | Uint16 TXFFIL:5; // 4:0 Interrupt level 144 | Uint16 TXFFIENA:1; // 5 Interrupt enable 145 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 146 | Uint16 TXFFINT:1; // 7 INT flag 147 | Uint16 TXFFST:5; // 12:8 FIFO status 148 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 149 | Uint16 SCIFFENA:1; // 14 Enhancement enable 150 | Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 151 | 152 | }; 153 | 154 | union SCIFFTX_REG { 155 | Uint16 all; 156 | struct SCIFFTX_BITS bit; 157 | }; 158 | 159 | //------------------------------------------------ 160 | // SCI FIFO recieve register bit definitions: 161 | // 162 | // 163 | 164 | struct SCIFFRX_BITS { // bits description 165 | Uint16 RXFFIL:5; // 4:0 Interrupt level 166 | Uint16 RXFFIENA:1; // 5 Interrupt enable 167 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 168 | Uint16 RXFFINT:1; // 7 INT flag 169 | Uint16 RXFFST:5; // 12:8 FIFO status 170 | Uint16 RXFIFORESET:1; // 13 FIFO reset 171 | Uint16 RXFFOVRCLR:1; // 14 Clear overflow 172 | Uint16 RXFFOVF:1; // 15 FIFO overflow 173 | 174 | }; 175 | 176 | union SCIFFRX_REG { 177 | Uint16 all; 178 | struct SCIFFRX_BITS bit; 179 | }; 180 | 181 | // SCI FIFO control register bit definitions: 182 | struct SCIFFCT_BITS { // bits description 183 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 184 | Uint16 rsvd:5; // 12:8 reserved 185 | Uint16 CDC:1; // 13 Auto baud mode enable 186 | Uint16 ABDCLR:1; // 14 Auto baud clear 187 | Uint16 ABD:1; // 15 Auto baud detect 188 | }; 189 | 190 | union SCIFFCT_REG { 191 | Uint16 all; 192 | struct SCIFFCT_BITS bit; 193 | }; 194 | 195 | //--------------------------------------------------------------------------- 196 | // SCI Register File: 197 | // 198 | struct SCI_REGS { 199 | union SCICCR_REG SCICCR; // Communications control register 200 | union SCICTL1_REG SCICTL1; // Control register 1 201 | Uint16 SCIHBAUD; // Baud rate (high) register 202 | Uint16 SCILBAUD; // Baud rate (low) register 203 | union SCICTL2_REG SCICTL2; // Control register 2 204 | union SCIRXST_REG SCIRXST; // Recieve status register 205 | Uint16 SCIRXEMU; // Recieve emulation buffer register 206 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 207 | Uint16 rsvd1; // reserved 208 | Uint16 SCITXBUF; // Transmit data buffer 209 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 210 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 211 | union SCIFFCT_REG SCIFFCT; // FIFO control register 212 | Uint16 rsvd2; // reserved 213 | Uint16 rsvd3; // reserved 214 | union SCIPRI_REG SCIPRI; // FIFO Priority control 215 | }; 216 | 217 | //--------------------------------------------------------------------------- 218 | // SCI External References & Function Declarations: 219 | // 220 | extern volatile struct SCI_REGS SciaRegs; 221 | extern volatile struct SCI_REGS ScibRegs; 222 | extern volatile struct SCI_REGS ScicRegs; 223 | 224 | #ifdef __cplusplus 225 | } 226 | #endif /* extern "C" */ 227 | 228 | #endif // end of DSP2833x_SCI_H definition 229 | 230 | //=========================================================================== 231 | // End of file. 232 | //=========================================================================== 233 | 234 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Spi.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Spi.h 4 | // 5 | // TITLE: DSP2833x Device SPI Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_SPI_H 13 | #define DSP2833x_SPI_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | 21 | //--------------------------------------------------------------------------- 22 | // SPI Individual Register Bit Definitions: 23 | // 24 | // SPI FIFO Transmit register bit definitions: 25 | struct SPIFFTX_BITS { // bit description 26 | Uint16 TXFFIL:5; // 4:0 Interrupt level 27 | Uint16 TXFFIENA:1; // 5 Interrupt enable 28 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 29 | Uint16 TXFFINT:1; // 7 INT flag 30 | Uint16 TXFFST:5; // 12:8 FIFO status 31 | Uint16 TXFIFO:1; // 13 FIFO reset 32 | Uint16 SPIFFENA:1; // 14 Enhancement enable 33 | Uint16 SPIRST:1; // 15 Reset SPI 34 | }; 35 | 36 | union SPIFFTX_REG { 37 | Uint16 all; 38 | struct SPIFFTX_BITS bit; 39 | }; 40 | 41 | //-------------------------------------------- 42 | // SPI FIFO recieve register bit definitions: 43 | // 44 | // 45 | struct SPIFFRX_BITS { // bits description 46 | Uint16 RXFFIL:5; // 4:0 Interrupt level 47 | Uint16 RXFFIENA:1; // 5 Interrupt enable 48 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 49 | Uint16 RXFFINT:1; // 7 INT flag 50 | Uint16 RXFFST:5; // 12:8 FIFO status 51 | Uint16 RXFIFORESET:1; // 13 FIFO reset 52 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 53 | Uint16 RXFFOVF:1; // 15 FIFO overflow 54 | 55 | }; 56 | 57 | union SPIFFRX_REG { 58 | Uint16 all; 59 | struct SPIFFRX_BITS bit; 60 | }; 61 | 62 | //-------------------------------------------- 63 | // SPI FIFO control register bit definitions: 64 | // 65 | // 66 | struct SPIFFCT_BITS { // bits description 67 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 68 | Uint16 rsvd:8; // 15:8 reserved 69 | }; 70 | 71 | union SPIFFCT_REG { 72 | Uint16 all; 73 | struct SPIFFCT_BITS bit; 74 | }; 75 | 76 | //--------------------------------------------- 77 | // SPI configuration register bit definitions: 78 | // 79 | // 80 | struct SPICCR_BITS { // bits description 81 | Uint16 SPICHAR:4; // 3:0 Character length control 82 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 83 | Uint16 rsvd1:1; // 5 reserved 84 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 85 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 86 | Uint16 rsvd2:8; // 15:8 reserved 87 | }; 88 | 89 | union SPICCR_REG { 90 | Uint16 all; 91 | struct SPICCR_BITS bit; 92 | }; 93 | 94 | //------------------------------------------------- 95 | // SPI operation control register bit definitions: 96 | // 97 | // 98 | struct SPICTL_BITS { // bits description 99 | Uint16 SPIINTENA:1; // 0 Interrupt enable 100 | Uint16 TALK:1; // 1 Master/Slave transmit enable 101 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 102 | Uint16 CLK_PHASE:1; // 3 Clock phase select 103 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 104 | Uint16 rsvd:11; // 15:5 reserved 105 | }; 106 | 107 | union SPICTL_REG { 108 | Uint16 all; 109 | struct SPICTL_BITS bit; 110 | }; 111 | 112 | //-------------------------------------- 113 | // SPI status register bit definitions: 114 | // 115 | // 116 | struct SPISTS_BITS { // bits description 117 | Uint16 rsvd1:5; // 4:0 reserved 118 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 119 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 120 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 121 | Uint16 rsvd2:8; // 15:8 reserved 122 | }; 123 | 124 | union SPISTS_REG { 125 | Uint16 all; 126 | struct SPISTS_BITS bit; 127 | }; 128 | 129 | //------------------------------------------------ 130 | // SPI priority control register bit definitions: 131 | // 132 | // 133 | struct SPIPRI_BITS { // bits description 134 | Uint16 rsvd1:4; // 3:0 reserved 135 | Uint16 FREE:1; // 4 Free emulation mode control 136 | Uint16 SOFT:1; // 5 Soft emulation mode control 137 | Uint16 rsvd2:1; // 6 reserved 138 | Uint16 rsvd3:9; // 15:7 reserved 139 | }; 140 | 141 | union SPIPRI_REG { 142 | Uint16 all; 143 | struct SPIPRI_BITS bit; 144 | }; 145 | 146 | //--------------------------------------------------------------------------- 147 | // SPI Register File: 148 | // 149 | struct SPI_REGS { 150 | union SPICCR_REG SPICCR; // Configuration register 151 | union SPICTL_REG SPICTL; // Operation control register 152 | union SPISTS_REG SPISTS; // Status register 153 | Uint16 rsvd1; // reserved 154 | Uint16 SPIBRR; // Baud Rate 155 | Uint16 rsvd2; // reserved 156 | Uint16 SPIRXEMU; // Emulation buffer 157 | Uint16 SPIRXBUF; // Serial input buffer 158 | Uint16 SPITXBUF; // Serial output buffer 159 | Uint16 SPIDAT; // Serial data 160 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 161 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 162 | union SPIFFCT_REG SPIFFCT; // FIFO control register 163 | Uint16 rsvd3[2]; // reserved 164 | union SPIPRI_REG SPIPRI; // FIFO Priority control 165 | }; 166 | 167 | //--------------------------------------------------------------------------- 168 | // SPI External References & Function Declarations: 169 | // 170 | extern volatile struct SPI_REGS SpiaRegs; 171 | 172 | #ifdef __cplusplus 173 | } 174 | #endif /* extern "C" */ 175 | 176 | #endif // end of DSP2833x_SPI_H definition 177 | 178 | //=========================================================================== 179 | // End of file. 180 | //=========================================================================== 181 | 182 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_XIntrupt.h 4 | // 5 | // TITLE: DSP2833x Device External Interrupt Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_XINTRUPT_H 13 | #define DSP2833x_XINTRUPT_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | //--------------------------------------------------------------------------- 21 | 22 | struct XINTCR_BITS { 23 | Uint16 ENABLE:1; // 0 enable/disable 24 | Uint16 rsvd1:1; // 1 reserved 25 | Uint16 POLARITY:2; // 3:2 pos/neg, both triggered 26 | Uint16 rsvd2:12; //15:4 reserved 27 | }; 28 | 29 | union XINTCR_REG { 30 | Uint16 all; 31 | struct XINTCR_BITS bit; 32 | }; 33 | 34 | struct XNMICR_BITS { 35 | Uint16 ENABLE:1; // 0 enable/disable 36 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to int13 37 | Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered 38 | Uint16 rsvd2:12; // 15:4 reserved 39 | }; 40 | 41 | union XNMICR_REG { 42 | Uint16 all; 43 | struct XNMICR_BITS bit; 44 | }; 45 | 46 | 47 | 48 | 49 | //--------------------------------------------------------------------------- 50 | // External Interrupt Register File: 51 | // 52 | struct XINTRUPT_REGS { 53 | union XINTCR_REG XINT1CR; 54 | union XINTCR_REG XINT2CR; 55 | union XINTCR_REG XINT3CR; 56 | union XINTCR_REG XINT4CR; 57 | union XINTCR_REG XINT5CR; 58 | union XINTCR_REG XINT6CR; 59 | union XINTCR_REG XINT7CR; 60 | union XNMICR_REG XNMICR; 61 | Uint16 XINT1CTR; 62 | Uint16 XINT2CTR; 63 | Uint16 rsvd[5]; 64 | Uint16 XNMICTR; 65 | }; 66 | 67 | //--------------------------------------------------------------------------- 68 | // External Interrupt References & Function Declarations: 69 | // 70 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 71 | 72 | #ifdef __cplusplus 73 | } 74 | #endif /* extern "C" */ 75 | 76 | #endif // end of DSP2833x_XINTF_H definition 77 | 78 | //=========================================================================== 79 | // End of file. 80 | //=========================================================================== 81 | 82 | -------------------------------------------------------------------------------- /user_lib/inc/DSP2833x_Xintf.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Xintf.h 4 | // 5 | // TITLE: DSP2833x Device External Interface Register Definitions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #ifndef DSP2833x_XINTF_H 13 | #define DSP2833x_XINTF_H 14 | 15 | 16 | #ifdef __cplusplus 17 | extern "C" { 18 | #endif 19 | 20 | 21 | // XINTF timing register bit definitions: 22 | struct XTIMING_BITS { // bits description 23 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 24 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 25 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 26 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 27 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 28 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 29 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 30 | Uint16 READYMODE:1; // 15 Ready mode 31 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 32 | Uint16 rsvd1:4; // 21:18 reserved 33 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 34 | Uint16 rsvd3:9; // 31:23 reserved 35 | }; 36 | 37 | union XTIMING_REG { 38 | Uint32 all; 39 | struct XTIMING_BITS bit; 40 | }; 41 | 42 | // XINTF control register bit definitions: 43 | struct XINTCNF2_BITS { // bits description 44 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 45 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 46 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 47 | Uint16 rsvd1:2; // 5:4 reserved 48 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 49 | Uint16 rsvd2:1; // 8 reserved 50 | Uint16 HOLD:1; // 9 Hold enable/disable 51 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 52 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 53 | Uint16 rsvd3:4; // 15:12 reserved 54 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 55 | Uint16 rsvd4:13; // 31:19 reserved 56 | }; 57 | 58 | union XINTCNF2_REG { 59 | Uint32 all; 60 | struct XINTCNF2_BITS bit; 61 | }; 62 | 63 | // XINTF bank switching register bit definitions: 64 | struct XBANK_BITS { // bits description 65 | Uint16 BANK:3; // 2:0 Zone for which banking is enabled 66 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 67 | Uint16 rsvd:10; // 15:6 reserved 68 | }; 69 | 70 | union XBANK_REG { 71 | Uint16 all; 72 | struct XBANK_BITS bit; 73 | }; 74 | 75 | struct XRESET_BITS { 76 | Uint16 XHARDRESET:1; 77 | Uint16 rsvd1:15; 78 | }; 79 | 80 | union XRESET_REG { 81 | Uint16 all; 82 | struct XRESET_BITS bit; 83 | }; 84 | 85 | 86 | //--------------------------------------------------------------------------- 87 | // XINTF Register File: 88 | // 89 | struct XINTF_REGS { 90 | union XTIMING_REG XTIMING0; 91 | Uint32 rsvd1[5]; 92 | union XTIMING_REG XTIMING6; 93 | union XTIMING_REG XTIMING7; 94 | Uint32 rsvd2[2]; 95 | union XINTCNF2_REG XINTCNF2; 96 | Uint32 rsvd3; 97 | union XBANK_REG XBANK; 98 | Uint16 rsvd4; 99 | Uint16 XREVISION; 100 | Uint16 rsvd5[2]; 101 | union XRESET_REG XRESET; 102 | }; 103 | 104 | //--------------------------------------------------------------------------- 105 | // XINTF External References & Function Declarations: 106 | // 107 | extern volatile struct XINTF_REGS XintfRegs; 108 | 109 | 110 | #ifdef __cplusplus 111 | } 112 | #endif /* extern "C" */ 113 | 114 | #endif // end of DSP2833x_XINTF_H definition 115 | 116 | //=========================================================================== 117 | // No more. 118 | //=========================================================================== 119 | -------------------------------------------------------------------------------- /user_lib/inc/DSP28x_Project.h: -------------------------------------------------------------------------------- 1 | 2 | //########################################################################### 3 | // 4 | // FILE: DSP28x_Project.h 5 | // 6 | // TITLE: DSP28x Project Headerfile and Examples Include File 7 | // 8 | //########################################################################### 9 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 10 | // $Release Date: June 8, 2012 $ 11 | //########################################################################### 12 | 13 | #ifndef DSP28x_PROJECT_H 14 | #define DSP28x_PROJECT_H 15 | 16 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 17 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 18 | 19 | #endif // end of DSP28x_PROJECT_H definition 20 | 21 | -------------------------------------------------------------------------------- /user_lib/inc/SFO.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: SFO.H 4 | // 5 | // TITLE: Scale Factor Optimizer Library Interface Header 6 | // 7 | // 8 | //########################################################################### 9 | // 10 | // Ver | dd mmm yyyy | Who | Description of changes 11 | // =====|=============|======|=============================================== 12 | // 0.01| 09 Jan 2004 | TI | New module 13 | //########################################################################### 14 | 15 | 16 | //============================================================================ 17 | // Description: This header provides the function call interface 18 | // for the scale factor optimizer for the 'F2833x. 19 | //============================================================================ 20 | 21 | 22 | //============================================================================ 23 | // Multiple include Guard 24 | //============================================================================ 25 | #ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___ 26 | #define __4090522384024n8273240x3438jx43087401r34ru32r0___ 27 | 28 | //============================================================================ 29 | // C++ namespace 30 | //============================================================================ 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | 36 | //============================================================================ 37 | // Function prototypes for MEP SFO 38 | //============================================================================ 39 | void SFO_MepEn(int nEpwmModule); 40 | void SFO_MepDis(int nEpwmModule); 41 | 42 | //============================================================================ 43 | // Multiple include Guard 44 | //============================================================================ 45 | #endif // End: Multiple include Guard 46 | 47 | //============================================================================ 48 | // C++ namespace 49 | //============================================================================ 50 | #ifdef __cplusplus 51 | } 52 | #endif /* extern "C" */ 53 | -------------------------------------------------------------------------------- /user_lib/inc/SFO_V5.h: -------------------------------------------------------------------------------- 1 | 2 | //########################################################################### 3 | // 4 | // FILE: SFO_V5.H 5 | // 6 | // TITLE: Scale Factor Optimizer Library V5 Interface Header 7 | // 8 | // 9 | //########################################################################### 10 | // 11 | // Ver | dd mmm yyyy | Who | Description of changes 12 | // =====|=============|======|=============================================== 13 | // 0.01| 09 Jan 2004 | TI | New module 14 | // 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels 15 | //########################################################################### 16 | 17 | 18 | //============================================================================ 19 | // Description: This header provides the function call interface 20 | // for the scale factor optimizer V5. For more 21 | // information on the SFO function usage and 22 | // limitations, see the HRPWM Reference Guide 23 | // (spru924) on the TI website. 24 | //============================================================================ 25 | 26 | 27 | //============================================================================ 28 | // Multiple include Guard 29 | //============================================================================ 30 | #ifndef _SFO_V5_H 31 | #define _SFO_V5_H 32 | 33 | //============================================================================ 34 | // C++ namespace 35 | //============================================================================ 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | //============================================================================ 41 | // USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1 42 | //============================================================================ 43 | #define PWM_CH 7 // Equal # of HRPWM channels PLUS 1 44 | // i.e. PWM_CH is 7 for 6 channels, 5 for 4 channels etc. 45 | 46 | //============================================================================ 47 | // Function prototypes for MEP SFO 48 | //============================================================================ 49 | 50 | int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function 51 | int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function 52 | 53 | //============================================================================ 54 | // Useful Defines when Using SFO Functions 55 | //============================================================================ 56 | #define SFO_INCOMPLETE 0 57 | #define SFO_COMPLETE 1 58 | #define SFO_OUTRANGE_ERROR 2 59 | 60 | //============================================================================ 61 | // Multiple include Guard 62 | //============================================================================ 63 | #endif // End: Multiple include Guard 64 | 65 | //============================================================================ 66 | // C++ namespace 67 | //============================================================================ 68 | #ifdef __cplusplus 69 | } 70 | #endif /* extern "C" */ 71 | -------------------------------------------------------------------------------- /user_lib/inc/config.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/28335CAN_Update_Flash/f17ff342156277b4e908612a7638cfc63fed1151/user_lib/inc/config.h -------------------------------------------------------------------------------- /user_lib/inc/data.h: -------------------------------------------------------------------------------- 1 | #ifndef __DATA_H__ 2 | #define __DATA_H__ 3 | #define NULL 0 4 | #define __IO volatile /*!< Defines 'read / write' permissions */ 5 | typedef unsigned short int u16; 6 | typedef unsigned long int u32; 7 | typedef unsigned char u8; 8 | //------------------------- 9 | typedef struct 10 | { 11 | unsigned char bit0 :1; 12 | unsigned char bit1 :1; 13 | unsigned char bit2 :1; 14 | unsigned char bit3 :1; 15 | unsigned char bit4 :1; 16 | unsigned char bit5 :1; 17 | unsigned char bit6 :1; 18 | unsigned char bit7 :1; 19 | } Bits_8s; 20 | typedef struct 21 | { 22 | unsigned char byte0 :4; 23 | unsigned char byte1 :4; 24 | } Byte_8s; 25 | typedef union 26 | { 27 | unsigned char all; 28 | Bits_8s bit; 29 | Byte_8s byte; 30 | } Char_8s; 31 | //------------------------ 32 | typedef struct 33 | { 34 | unsigned char bit0 :1; 35 | unsigned char bit1 :1; 36 | unsigned char bit2 :1; 37 | unsigned char bit3 :1; 38 | unsigned char bit4 :1; 39 | unsigned char bit5 :1; 40 | unsigned char bit6 :1; 41 | unsigned char bit7 :1; 42 | unsigned char bit8 :1; 43 | unsigned char bit9 :1; 44 | unsigned char bit10 :1; 45 | unsigned char bit11 :1; 46 | unsigned char bit12 :1; 47 | unsigned char bit13 :1; 48 | unsigned char bit14 :1; 49 | unsigned char bit15 :1; 50 | } Bits_16s; 51 | typedef struct 52 | { 53 | unsigned char byte0 :4; 54 | unsigned char byte1 :4; 55 | unsigned char byte3 :4; 56 | unsigned char byte4 :4; 57 | } Byte_16s; 58 | typedef union 59 | { 60 | unsigned short int all; 61 | Bits_16s bit; 62 | Byte_16s byte; 63 | } Uint_16s; 64 | //#define u8 unsigned char 65 | //#define u16 unsigned short int 66 | //#define u32 unsigned long int 67 | #endif 68 | -------------------------------------------------------------------------------- /user_lib/inc/delay.h: -------------------------------------------------------------------------------- 1 | #ifndef _DSP_DELAY_H__ 2 | #define _DSP_DELAY_H__ 3 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 4 | #include "DSP2833x_Examples.h" 5 | #include "data.h" 6 | #include "config.h" 7 | void delay_us(unsigned long int nus); 8 | void delay_ms(unsigned long int nms); 9 | void delay_s(unsigned long int ns); 10 | void delay(unsigned long int i); 11 | #endif 12 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_CpuTimers.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_CpuTimers.c 4 | // 5 | // TITLE: CPU 32-bit Timers Initialization & Support Functions. 6 | // 7 | // NOTES: CpuTimer2 is reserved for use with DSP BIOS and 8 | // other realtime operating systems. 9 | // 10 | // Do not use these this timer in your application if you ever plan 11 | // on integrating DSP-BIOS or another realtime OS. 12 | // 13 | //########################################################################### 14 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 15 | // $Release Date: June 8, 2012 $ 16 | //########################################################################### 17 | 18 | #include "DSP2833x_Device.h" // Headerfile Include File 19 | #include "DSP2833x_Examples.h" // Examples Include File 20 | 21 | struct CPUTIMER_VARS CpuTimer0; 22 | 23 | // When using DSP BIOS & other RTOS, comment out CPU Timer 2 code. 24 | struct CPUTIMER_VARS CpuTimer1; 25 | struct CPUTIMER_VARS CpuTimer2; 26 | 27 | //--------------------------------------------------------------------------- 28 | // InitCpuTimers: 29 | //--------------------------------------------------------------------------- 30 | // This function initializes all three CPU timers to a known state. 31 | // 32 | void InitCpuTimers(void) 33 | { 34 | // CPU Timer 0 35 | // Initialize address pointers to respective timer registers: 36 | CpuTimer0.RegsAddr = &CpuTimer0Regs; 37 | // Initialize timer period to maximum: 38 | CpuTimer0Regs.PRD.all = 0xFFFFFFFF; 39 | // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): 40 | CpuTimer0Regs.TPR.all = 0; 41 | CpuTimer0Regs.TPRH.all = 0; 42 | // Make sure timer is stopped: 43 | CpuTimer0Regs.TCR.bit.TSS = 1; 44 | // Reload all counter register with period value: 45 | CpuTimer0Regs.TCR.bit.TRB = 1; 46 | // Reset interrupt counters: 47 | CpuTimer0.InterruptCount = 0; 48 | 49 | 50 | // CpuTimer2 is reserved for DSP BIOS & other RTOS 51 | // Do not use this timer if you ever plan on integrating 52 | // DSP-BIOS or another realtime OS. 53 | 54 | // Initialize address pointers to respective timer registers: 55 | CpuTimer1.RegsAddr = &CpuTimer1Regs; 56 | CpuTimer2.RegsAddr = &CpuTimer2Regs; 57 | // Initialize timer period to maximum: 58 | CpuTimer1Regs.PRD.all = 0xFFFFFFFF; 59 | CpuTimer2Regs.PRD.all = 0xFFFFFFFF; 60 | // Make sure timers are stopped: 61 | CpuTimer1Regs.TCR.bit.TSS = 1; 62 | CpuTimer2Regs.TCR.bit.TSS = 1; 63 | // Reload all counter register with period value: 64 | CpuTimer1Regs.TCR.bit.TRB = 1; 65 | CpuTimer2Regs.TCR.bit.TRB = 1; 66 | // Reset interrupt counters: 67 | CpuTimer1.InterruptCount = 0; 68 | CpuTimer2.InterruptCount = 0; 69 | 70 | } 71 | 72 | //--------------------------------------------------------------------------- 73 | // ConfigCpuTimer: 74 | //--------------------------------------------------------------------------- 75 | // This function initializes the selected timer to the period specified 76 | // by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz" 77 | // and the period in "uSeconds". The timer is held in the stopped state 78 | // after configuration. 79 | // 80 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) 81 | { 82 | Uint32 temp; 83 | 84 | // Initialize timer period: 85 | Timer->CPUFreqInMHz = Freq; 86 | Timer->PeriodInUSec = Period; 87 | temp = (long) (Freq * Period); 88 | Timer->RegsAddr->PRD.all = temp; 89 | 90 | // Set pre-scale counter to divide by 1 (SYSCLKOUT): 91 | Timer->RegsAddr->TPR.all = 0; 92 | Timer->RegsAddr->TPRH.all = 0; 93 | 94 | // Initialize timer control register: 95 | Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer 96 | Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer 97 | Timer->RegsAddr->TCR.bit.SOFT = 1; 98 | Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run 99 | Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt 100 | 101 | // Reset interrupt counter: 102 | Timer->InterruptCount = 0; 103 | } 104 | 105 | //=========================================================================== 106 | // End of file. 107 | //=========================================================================== 108 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_Gpio.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Gpio.c 4 | // 5 | // TITLE: DSP2833x General Purpose I/O Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 13 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 14 | 15 | //--------------------------------------------------------------------------- 16 | // InitGpio: 17 | //--------------------------------------------------------------------------- 18 | // This function initializes the Gpio to a known (default) state. 19 | // 20 | // For more details on configuring GPIO's as peripheral functions, 21 | // refer to the individual peripheral examples and/or GPIO setup example. 22 | void InitGpio(void) 23 | { 24 | EALLOW; 25 | 26 | // Each GPIO pin can be: 27 | // a) a GPIO input/output 28 | // b) peripheral function 1 29 | // c) peripheral function 2 30 | // d) peripheral function 3 31 | // By default, all are GPIO Inputs 32 | GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO0-GPIO15 33 | GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31 34 | GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO39 35 | GpioCtrlRegs.GPBMUX2.all = 0x0000; // GPIO functionality GPIO48-GPIO63 36 | GpioCtrlRegs.GPCMUX1.all = 0x0000; // GPIO functionality GPIO64-GPIO79 37 | GpioCtrlRegs.GPCMUX2.all = 0x0000; // GPIO functionality GPIO80-GPIO95 38 | 39 | GpioCtrlRegs.GPADIR.all = 0x0000; // GPIO0-GPIO31 are inputs 40 | GpioCtrlRegs.GPBDIR.all = 0x0000; // GPIO32-GPIO63 are inputs 41 | GpioCtrlRegs.GPCDIR.all = 0x0000; // GPI064-GPIO95 are inputs 42 | 43 | // Each input can have different qualification 44 | // a) input synchronized to SYSCLKOUT 45 | // b) input qualified by a sampling window 46 | // c) input sent asynchronously (valid for peripheral inputs only) 47 | GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT 48 | GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT 49 | GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO39 Synch to SYSCLKOUT 50 | GpioCtrlRegs.GPBQSEL2.all = 0x0000; // GPIO48-GPIO63 Synch to SYSCLKOUT 51 | 52 | // Pull-ups can be enabled or disabled. 53 | GpioCtrlRegs.GPAPUD.all = 0x0000; // Pullup's enabled GPIO0-GPIO31 54 | GpioCtrlRegs.GPBPUD.all = 0x0000; // Pullup's enabled GPIO32-GPIO63 55 | GpioCtrlRegs.GPCPUD.all = 0x0000; // Pullup's enabled GPIO64-GPIO79 56 | 57 | //GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31 58 | //GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34 59 | //GpioCtrlRegs.GPCPUD.all = 0xFFFF // Pullup's disabled GPIO64-GPIO79 60 | 61 | EDIS; 62 | 63 | } 64 | 65 | //=========================================================================== 66 | // End of file. 67 | //=========================================================================== 68 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_MemCopy.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_MemCopy.c 4 | // 5 | // TITLE: Memory Copy Utility 6 | // 7 | // ASSUMPTIONS: 8 | // 9 | // 10 | // 11 | // DESCRIPTION: 12 | // 13 | // This function will copy the specified memory contents from 14 | // one location to another. 15 | // 16 | // Uint16 *SourceAddr Pointer to the first word to be moved 17 | // SourceAddr < SourceEndAddr 18 | // Uint16* SourceEndAddr Pointer to the last word to be moved 19 | // Uint16* DestAddr Pointer to the first destination word 20 | // 21 | // No checks are made for invalid memory locations or that the 22 | // end address is > then the first start address. 23 | // 24 | // 25 | //########################################################################### 26 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 27 | // $Release Date: June 8, 2012 $ 28 | //########################################################################### 29 | 30 | #include "DSP2833x_Device.h" 31 | 32 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr) 33 | { 34 | while(SourceAddr < SourceEndAddr) 35 | { 36 | *DestAddr++ = *SourceAddr++; 37 | } 38 | return; 39 | } 40 | 41 | //=========================================================================== 42 | // End of file. 43 | //=========================================================================== 44 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_PieCtrl.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_PieCtrl.c 4 | // 5 | // TITLE: DSP2833x Device PIE Control Register Initialization Functions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 13 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 14 | 15 | //--------------------------------------------------------------------------- 16 | // InitPieCtrl: 17 | //--------------------------------------------------------------------------- 18 | // This function initializes the PIE control registers to a known state. 19 | // 20 | void InitPieCtrl(void) 21 | { 22 | // Disable Interrupts at the CPU level: 23 | DINT; 24 | 25 | // Disable the PIE 26 | PieCtrlRegs.PIECTRL.bit.ENPIE = 0; 27 | 28 | // Clear all PIEIER registers: 29 | PieCtrlRegs.PIEIER1.all = 0; 30 | PieCtrlRegs.PIEIER2.all = 0; 31 | PieCtrlRegs.PIEIER3.all = 0; 32 | PieCtrlRegs.PIEIER4.all = 0; 33 | PieCtrlRegs.PIEIER5.all = 0; 34 | PieCtrlRegs.PIEIER6.all = 0; 35 | PieCtrlRegs.PIEIER7.all = 0; 36 | PieCtrlRegs.PIEIER8.all = 0; 37 | PieCtrlRegs.PIEIER9.all = 0; 38 | PieCtrlRegs.PIEIER10.all = 0; 39 | PieCtrlRegs.PIEIER11.all = 0; 40 | PieCtrlRegs.PIEIER12.all = 0; 41 | 42 | // Clear all PIEIFR registers: 43 | PieCtrlRegs.PIEIFR1.all = 0; 44 | PieCtrlRegs.PIEIFR2.all = 0; 45 | PieCtrlRegs.PIEIFR3.all = 0; 46 | PieCtrlRegs.PIEIFR4.all = 0; 47 | PieCtrlRegs.PIEIFR5.all = 0; 48 | PieCtrlRegs.PIEIFR6.all = 0; 49 | PieCtrlRegs.PIEIFR7.all = 0; 50 | PieCtrlRegs.PIEIFR8.all = 0; 51 | PieCtrlRegs.PIEIFR9.all = 0; 52 | PieCtrlRegs.PIEIFR10.all = 0; 53 | PieCtrlRegs.PIEIFR11.all = 0; 54 | PieCtrlRegs.PIEIFR12.all = 0; 55 | 56 | 57 | } 58 | 59 | //--------------------------------------------------------------------------- 60 | // EnableInterrupts: 61 | //--------------------------------------------------------------------------- 62 | // This function enables the PIE module and CPU interrupts 63 | // 64 | void EnableInterrupts() 65 | { 66 | 67 | // Enable the PIE 68 | PieCtrlRegs.PIECTRL.bit.ENPIE = 1; 69 | 70 | // Enables PIE to drive a pulse into the CPU 71 | PieCtrlRegs.PIEACK.all = 0xFFFF; 72 | 73 | // Enable Interrupts at the CPU level 74 | EINT; 75 | 76 | } 77 | 78 | 79 | //=========================================================================== 80 | // End of file. 81 | //=========================================================================== 82 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_PieVect.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_PieVect.c 4 | // 5 | // TITLE: DSP2833x Devices PIE Vector Table Initialization Functions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 13 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 14 | 15 | 16 | const struct PIE_VECT_TABLE PieVectTableInit = { 17 | 18 | PIE_RESERVED, // 0 Reserved space 19 | PIE_RESERVED, // 1 Reserved space 20 | PIE_RESERVED, // 2 Reserved space 21 | PIE_RESERVED, // 3 Reserved space 22 | PIE_RESERVED, // 4 Reserved space 23 | PIE_RESERVED, // 5 Reserved space 24 | PIE_RESERVED, // 6 Reserved space 25 | PIE_RESERVED, // 7 Reserved space 26 | PIE_RESERVED, // 8 Reserved space 27 | PIE_RESERVED, // 9 Reserved space 28 | PIE_RESERVED, // 10 Reserved space 29 | PIE_RESERVED, // 11 Reserved space 30 | PIE_RESERVED, // 12 Reserved space 31 | 32 | 33 | // Non-Peripheral Interrupts 34 | INT13_ISR, // XINT13 or CPU-Timer 1 35 | INT14_ISR, // CPU-Timer2 36 | DATALOG_ISR, // Datalogging interrupt 37 | RTOSINT_ISR, // RTOS interrupt 38 | EMUINT_ISR, // Emulation interrupt 39 | NMI_ISR, // Non-maskable interrupt 40 | ILLEGAL_ISR, // Illegal operation TRAP 41 | USER1_ISR, // User Defined trap 1 42 | USER2_ISR, // User Defined trap 2 43 | USER3_ISR, // User Defined trap 3 44 | USER4_ISR, // User Defined trap 4 45 | USER5_ISR, // User Defined trap 5 46 | USER6_ISR, // User Defined trap 6 47 | USER7_ISR, // User Defined trap 7 48 | USER8_ISR, // User Defined trap 8 49 | USER9_ISR, // User Defined trap 9 50 | USER10_ISR, // User Defined trap 10 51 | USER11_ISR, // User Defined trap 11 52 | USER12_ISR, // User Defined trap 12 53 | 54 | // Group 1 PIE Vectors 55 | SEQ1INT_ISR, // 1.1 ADC 56 | SEQ2INT_ISR, // 1.2 ADC 57 | rsvd_ISR, // 1.3 58 | XINT1_ISR, // 1.4 59 | XINT2_ISR, // 1.5 60 | ADCINT_ISR, // 1.6 ADC 61 | TINT0_ISR, // 1.7 Timer 0 62 | WAKEINT_ISR, // 1.8 WD, Low Power 63 | 64 | // Group 2 PIE Vectors 65 | EPWM1_TZINT_ISR, // 2.1 EPWM-1 Trip Zone 66 | EPWM2_TZINT_ISR, // 2.2 EPWM-2 Trip Zone 67 | EPWM3_TZINT_ISR, // 2.3 EPWM-3 Trip Zone 68 | EPWM4_TZINT_ISR, // 2.4 EPWM-4 Trip Zone 69 | EPWM5_TZINT_ISR, // 2.5 EPWM-5 Trip Zone 70 | EPWM6_TZINT_ISR, // 2.6 EPWM-6 Trip Zone 71 | rsvd_ISR, // 2.7 72 | rsvd_ISR, // 2.8 73 | 74 | // Group 3 PIE Vectors 75 | EPWM1_INT_ISR, // 3.1 EPWM-1 Interrupt 76 | EPWM2_INT_ISR, // 3.2 EPWM-2 Interrupt 77 | EPWM3_INT_ISR, // 3.3 EPWM-3 Interrupt 78 | EPWM4_INT_ISR, // 3.4 EPWM-4 Interrupt 79 | EPWM5_INT_ISR, // 3.5 EPWM-5 Interrupt 80 | EPWM6_INT_ISR, // 3.6 EPWM-6 Interrupt 81 | rsvd_ISR, // 3.7 82 | rsvd_ISR, // 3.8 83 | 84 | // Group 4 PIE Vectors 85 | ECAP1_INT_ISR, // 4.1 ECAP-1 86 | ECAP2_INT_ISR, // 4.2 ECAP-2 87 | ECAP3_INT_ISR, // 4.3 ECAP-3 88 | ECAP4_INT_ISR, // 4.4 ECAP-4 89 | ECAP5_INT_ISR, // 4.5 ECAP-5 90 | ECAP6_INT_ISR, // 4.6 ECAP-6 91 | rsvd_ISR, // 4.7 92 | rsvd_ISR, // 4.8 93 | 94 | // Group 5 PIE Vectors 95 | EQEP1_INT_ISR, // 5.1 EQEP-1 96 | EQEP2_INT_ISR, // 5.2 EQEP-2 97 | rsvd_ISR, // 5.3 98 | rsvd_ISR, // 5.4 99 | rsvd_ISR, // 5.5 100 | rsvd_ISR, // 5.6 101 | rsvd_ISR, // 5.7 102 | rsvd_ISR, // 5.8 103 | 104 | 105 | // Group 6 PIE Vectors 106 | SPIRXINTA_ISR, // 6.1 SPI-A 107 | SPITXINTA_ISR, // 6.2 SPI-A 108 | MRINTA_ISR, // 6.3 McBSP-A 109 | MXINTA_ISR, // 6.4 McBSP-A 110 | MRINTB_ISR, // 6.5 McBSP-B 111 | MXINTB_ISR, // 6.6 McBSP-B 112 | rsvd_ISR, // 6.7 113 | rsvd_ISR, // 6.8 114 | 115 | 116 | // Group 7 PIE Vectors 117 | DINTCH1_ISR, // 7.1 DMA channel 1 118 | DINTCH2_ISR, // 7.2 DMA channel 2 119 | DINTCH3_ISR, // 7.3 DMA channel 3 120 | DINTCH4_ISR, // 7.4 DMA channel 4 121 | DINTCH5_ISR, // 7.5 DMA channel 5 122 | DINTCH6_ISR, // 7.6 DMA channel 6 123 | rsvd_ISR, // 7.7 124 | rsvd_ISR, // 7.8 125 | 126 | // Group 8 PIE Vectors 127 | I2CINT1A_ISR, // 8.1 I2C 128 | I2CINT2A_ISR, // 8.2 I2C 129 | rsvd_ISR, // 8.3 130 | rsvd_ISR, // 8.4 131 | SCIRXINTC_ISR, // 8.5 SCI-C 132 | SCITXINTC_ISR, // 8.6 SCI-C 133 | rsvd_ISR, // 8.7 134 | rsvd_ISR, // 8.8 135 | 136 | // Group 9 PIE Vectors 137 | SCIRXINTA_ISR, // 9.1 SCI-A 138 | SCITXINTA_ISR, // 9.2 SCI-A 139 | SCIRXINTB_ISR, // 9.3 SCI-B 140 | SCITXINTB_ISR, // 9.4 SCI-B 141 | ECAN0INTA_ISR, // 9.5 eCAN-A 142 | ECAN1INTA_ISR, // 9.6 eCAN-A 143 | ECAN0INTB_ISR, // 9.7 eCAN-B 144 | ECAN1INTB_ISR, // 9.8 eCAN-B 145 | 146 | // Group 10 PIE Vectors 147 | rsvd_ISR, // 10.1 148 | rsvd_ISR, // 10.2 149 | rsvd_ISR, // 10.3 150 | rsvd_ISR, // 10.4 151 | rsvd_ISR, // 10.5 152 | rsvd_ISR, // 10.6 153 | rsvd_ISR, // 10.7 154 | rsvd_ISR, // 10.8 155 | 156 | // Group 11 PIE Vectors 157 | rsvd_ISR, // 11.1 158 | rsvd_ISR, // 11.2 159 | rsvd_ISR, // 11.3 160 | rsvd_ISR, // 11.4 161 | rsvd_ISR, // 11.5 162 | rsvd_ISR, // 11.6 163 | rsvd_ISR, // 11.7 164 | rsvd_ISR, // 11.8 165 | 166 | // Group 12 PIE Vectors 167 | XINT3_ISR, // 12.1 168 | XINT4_ISR, // 12.2 169 | XINT5_ISR, // 12.3 170 | XINT6_ISR, // 12.4 171 | XINT7_ISR, // 12.5 172 | rsvd_ISR, // 12.6 173 | LVF_ISR, // 12.7 174 | LUF_ISR, // 12.8 175 | }; 176 | 177 | 178 | //--------------------------------------------------------------------------- 179 | // InitPieVectTable: 180 | //--------------------------------------------------------------------------- 181 | // This function initializes the PIE vector table to a known state. 182 | // This function must be executed after boot time. 183 | // 184 | 185 | void InitPieVectTable(void) 186 | { 187 | int16 i; 188 | Uint32 *Source = (void *) &PieVectTableInit; 189 | Uint32 *Dest = (void *) &PieVectTable; 190 | 191 | EALLOW; 192 | for(i=0; i < 128; i++) 193 | *Dest++ = *Source++; 194 | EDIS; 195 | 196 | // Enable the PIE Vector Table 197 | PieCtrlRegs.PIECTRL.bit.ENPIE = 1; 198 | 199 | } 200 | 201 | //=========================================================================== 202 | // End of file. 203 | //=========================================================================== 204 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_Sci.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Sci.c 4 | // 5 | // TITLE: DSP2833x SCI Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // $TI Release: 2833x/2823x Header Files and Peripheral Examples V133 $ 9 | // $Release Date: June 8, 2012 $ 10 | //########################################################################### 11 | 12 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 13 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 14 | 15 | //--------------------------------------------------------------------------- 16 | // InitSci: 17 | //--------------------------------------------------------------------------- 18 | // This function initializes the SCI(s) to a known state. 19 | // 20 | void InitSci(void) 21 | { 22 | // Initialize SCI-A: 23 | 24 | //tbd... 25 | 26 | 27 | // Initialize SCI-B: 28 | 29 | //tbd... 30 | 31 | // Initialize SCI-C: 32 | 33 | //tbd... 34 | } 35 | 36 | //--------------------------------------------------------------------------- 37 | // Example: InitSciGpio: 38 | //--------------------------------------------------------------------------- 39 | // This function initializes GPIO pins to function as SCI pins 40 | // 41 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 42 | // peripheral functional pins. By default all pins come up as GPIO 43 | // inputs after reset. 44 | // 45 | // Caution: 46 | // Only one GPIO pin should be enabled for SCITXDA/B operation. 47 | // Only one GPIO pin shoudl be enabled for SCIRXDA/B operation. 48 | // Comment out other unwanted lines. 49 | 50 | void InitSciGpio() 51 | { 52 | InitSciaGpio(); 53 | #if DSP28_SCIB 54 | InitScibGpio(); 55 | #endif // if DSP28_SCIB 56 | #if DSP28_SCIC 57 | InitScicGpio(); 58 | #endif // if DSP28_SCIC 59 | } 60 | 61 | void InitSciaGpio() 62 | { 63 | EALLOW; 64 | 65 | /* Enable internal pull-up for the selected pins */ 66 | // Pull-ups can be enabled or disabled disabled by the user. 67 | // This will enable the pullups for the specified pins. 68 | 69 | GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0; // Enable pull-up for GPIO28 (SCIRXDA) 70 | GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0; // Enable pull-up for GPIO29 (SCITXDA) 71 | 72 | /* Set qualification for selected pins to asynch only */ 73 | // Inputs are synchronized to SYSCLKOUT by default. 74 | // This will select asynch (no qualification) for the selected pins. 75 | 76 | GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 3; // Asynch input GPIO28 (SCIRXDA) 77 | 78 | /* Configure SCI-A pins using GPIO regs*/ 79 | // This specifies which of the possible GPIO pins will be SCI functional pins. 80 | 81 | GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1; // Configure GPIO28 for SCIRXDA operation 82 | GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1; // Configure GPIO29 for SCITXDA operation 83 | 84 | EDIS; 85 | } 86 | 87 | #if DSP28_SCIB 88 | void InitScibGpio() 89 | { 90 | EALLOW; 91 | 92 | /* Enable internal pull-up for the selected pins */ 93 | // Pull-ups can be enabled or disabled disabled by the user. 94 | // This will enable the pullups for the specified pins. 95 | // Comment out other unwanted lines. 96 | 97 | // GpioCtrlRegs.GPAPUD.bit.GPIO9 = 0; // Enable pull-up for GPIO9 (SCITXDB) 98 | // GpioCtrlRegs.GPAPUD.bit.GPIO14 = 0; // Enable pull-up for GPIO14 (SCITXDB) 99 | GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up for GPIO18 (SCITXDB) 100 | // GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0; // Enable pull-up for GPIO22 (SCITXDB) 101 | 102 | 103 | // GpioCtrlRegs.GPAPUD.bit.GPIO11 = 0; // Enable pull-up for GPIO11 (SCIRXDB) 104 | // GpioCtrlRegs.GPAPUD.bit.GPIO15 = 0; // Enable pull-up for GPIO15 (SCIRXDB) 105 | GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up for GPIO19 (SCIRXDB) 106 | // GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0; // Enable pull-up for GPIO23 (SCIRXDB) 107 | 108 | /* Set qualification for selected pins to asynch only */ 109 | // This will select asynch (no qualification) for the selected pins. 110 | // Comment out other unwanted lines. 111 | 112 | // GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Asynch input GPIO11 (SCIRXDB) 113 | // GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Asynch input GPIO15 (SCIRXDB) 114 | GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SCIRXDB) 115 | // GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; // Asynch input GPIO23 (SCIRXDB) 116 | 117 | /* Configure SCI-B pins using GPIO regs*/ 118 | // This specifies which of the possible GPIO pins will be SCI functional pins. 119 | // Comment out other unwanted lines. 120 | 121 | // GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 2; // Configure GPIO9 for SCITXDB operation 122 | // GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 2; // Configure GPIO14 for SCITXDB operation 123 | GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; // Configure GPIO18 for SCITXDB operation 124 | // GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 3; // Configure GPIO22 for SCITXDB operation 125 | 126 | // GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 2; // Configure GPIO11 for SCIRXDB operation 127 | // GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 2; // Configure GPIO15 for SCIRXDB operation 128 | GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; // Configure GPIO19 for SCIRXDB operation 129 | // GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 3; // Configure GPIO23 for SCIRXDB operation 130 | 131 | EDIS; 132 | } 133 | #endif // if DSP28_SCIB 134 | 135 | #if DSP28_SCIC 136 | void InitScicGpio() 137 | { 138 | EALLOW; 139 | 140 | /* Enable internal pull-up for the selected pins */ 141 | // Pull-ups can be enabled or disabled disabled by the user. 142 | // This will enable the pullups for the specified pins. 143 | 144 | GpioCtrlRegs.GPBPUD.bit.GPIO62 = 0; // Enable pull-up for GPIO62 (SCIRXDC) 145 | GpioCtrlRegs.GPBPUD.bit.GPIO63 = 0; // Enable pull-up for GPIO63 (SCITXDC) 146 | 147 | /* Set qualification for selected pins to asynch only */ 148 | // Inputs are synchronized to SYSCLKOUT by default. 149 | // This will select asynch (no qualification) for the selected pins. 150 | 151 | GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // Asynch input GPIO62 (SCIRXDC) 152 | 153 | /* Configure SCI-C pins using GPIO regs*/ 154 | // This specifies which of the possible GPIO pins will be SCI functional pins. 155 | 156 | GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 for SCIRXDC operation 157 | GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 for SCITXDC operation 158 | 159 | EDIS; 160 | } 161 | #endif // if DSP28_SCIC 162 | 163 | 164 | //=========================================================================== 165 | // End of file. 166 | //=========================================================================== 167 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_Spi.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Spi.c 4 | // 5 | // TITLE: DSP2833x SPI Initialization & Support Functions. 6 | // 7 | //########################################################################### 8 | // $TI Release: F2833x/F2823x Header Files and Peripheral Examples V141 $ 9 | // $Release Date: November 6, 2015 $ 10 | // $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated - 11 | // http://www.ti.com/ ALL RIGHTS RESERVED $ 12 | //########################################################################### 13 | 14 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 15 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // InitSPI: 19 | //--------------------------------------------------------------------------- 20 | // This function initializes the SPI(s) to a known state. 21 | // 22 | void InitSpi(void) 23 | { 24 | // Initialize SPI-A/B/C/D 25 | 26 | //tbd... 27 | 28 | } 29 | 30 | //--------------------------------------------------------------------------- 31 | // Example: InitSpiGpio: 32 | //--------------------------------------------------------------------------- 33 | // This function initializes GPIO pins to function as SPI pins 34 | // 35 | // Each GPIO pin can be configured as a GPIO pin or up to 3 different 36 | // peripheral functional pins. By default all pins come up as GPIO 37 | // inputs after reset. 38 | // 39 | // Caution: 40 | // For each SPI peripheral 41 | // Only one GPIO pin should be enabled for SPISOMO operation. 42 | // Only one GPIO pin should be enabled for SPISOMI operation. 43 | // Only one GPIO pin should be enabled for SPICLKA operation. 44 | // Only one GPIO pin should be enabled for SPISTEA operation. 45 | // Comment out other unwanted lines. 46 | 47 | void InitSpiGpio() 48 | { 49 | 50 | InitSpiaGpio(); 51 | } 52 | 53 | void InitSpiaGpio() 54 | { 55 | 56 | EALLOW; 57 | /* Enable internal pull-up for the selected pins */ 58 | // Pull-ups can be enabled or disabled by the user. 59 | // This will enable the pullups for the specified pins. 60 | // Comment out other unwanted lines. 61 | 62 | GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) 63 | GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) 64 | GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) 65 | GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) 66 | 67 | 68 | // GpioCtrlRegs.GPBPUD.bit.GPIO54 = 0; // Enable pull-up on GPIO54 (SPISIMOA) 69 | // GpioCtrlRegs.GPBPUD.bit.GPIO55 = 0; // Enable pull-up on GPIO55 (SPISOMIA) 70 | // GpioCtrlRegs.GPBPUD.bit.GPIO56 = 0; // Enable pull-up on GPIO56 (SPICLKA) 71 | // GpioCtrlRegs.GPBPUD.bit.GPIO57 = 0; // Enable pull-up on GPIO57 (SPISTEA) 72 | 73 | /* Set qualification for selected pins to asynch only */ 74 | // This will select asynch (no qualification) for the selected pins. 75 | // Comment out other unwanted lines. 76 | 77 | GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) 78 | GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) 79 | GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) 80 | GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) 81 | 82 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // Asynch input GPIO16 (SPISIMOA) 83 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // Asynch input GPIO17 (SPISOMIA) 84 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // Asynch input GPIO18 (SPICLKA) 85 | // GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // Asynch input GPIO19 (SPISTEA) 86 | 87 | 88 | /* Configure SPI-A pins using GPIO regs*/ 89 | // This specifies which of the possible GPIO pins will be SPI functional pins. 90 | // Comment out other unwanted lines. 91 | 92 | GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA 93 | GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA 94 | GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA 95 | GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA 96 | 97 | // GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as SPISIMOA 98 | // GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as SPISOMIA 99 | // GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as SPICLKA 100 | // GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as SPISTEA 101 | 102 | EDIS; 103 | } 104 | 105 | //=========================================================================== 106 | // End of file. 107 | //=========================================================================== 108 | -------------------------------------------------------------------------------- /user_lib/src/DSP2833x_Xintf.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP2833x_Xintf.c 4 | // 5 | // TITLE: DSP2833x Device External Interface Init & Support Functions. 6 | // 7 | // DESCRIPTION: 8 | // 9 | // Example initialization function for the external interface (XINTF). 10 | // This example configures the XINTF to its default state. For an 11 | // example of how this function being used refer to the 12 | // examples/run_from_xintf project. 13 | // 14 | //########################################################################### 15 | // $TI Release: F2833x/F2823x Header Files and Peripheral Examples V141 $ 16 | // $Release Date: November 6, 2015 $ 17 | // $Copyright: Copyright (C) 2007-2015 Texas Instruments Incorporated - 18 | // http://www.ti.com/ ALL RIGHTS RESERVED $ 19 | //########################################################################### 20 | 21 | #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File 22 | #include "DSP2833x_Examples.h" // DSP2833x Examples Include File 23 | 24 | //--------------------------------------------------------------------------- 25 | // InitXINTF: 26 | //--------------------------------------------------------------------------- 27 | // This function initializes the External Interface the default reset state. 28 | // 29 | // Do not modify the timings of the XINTF while running from the XINTF. Doing 30 | // so can yield unpredictable results 31 | 32 | 33 | void InitXintf(void) 34 | { 35 | // This shows how to write to the XINTF registers. The 36 | // values used here are the default state after reset. 37 | // Different hardware will require a different configuration. 38 | 39 | // For an example of an XINTF configuration used with the 40 | // F28335 eZdsp, refer to the examples/run_from_xintf project. 41 | 42 | // Any changes to XINTF timing should only be made by code 43 | // running outside of the XINTF. 44 | 45 | // All Zones--------------------------------- 46 | // Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT 47 | EALLOW; 48 | XintfRegs.XINTCNF2.bit.XTIMCLK = 1; 49 | // No write buffering 50 | XintfRegs.XINTCNF2.bit.WRBUFF = 0; 51 | // XCLKOUT is enabled 52 | XintfRegs.XINTCNF2.bit.CLKOFF = 0; 53 | // XCLKOUT = XTIMCLK/2 54 | XintfRegs.XINTCNF2.bit.CLKMODE = 1; 55 | 56 | 57 | // Zone 0------------------------------------ 58 | // When using ready, ACTIVE must be 1 or greater 59 | // Lead must always be 1 or greater 60 | // Zone write timing 61 | XintfRegs.XTIMING0.bit.XWRLEAD = 3; 62 | XintfRegs.XTIMING0.bit.XWRACTIVE = 7; 63 | XintfRegs.XTIMING0.bit.XWRTRAIL = 3; 64 | // Zone read timing 65 | XintfRegs.XTIMING0.bit.XRDLEAD = 3; 66 | XintfRegs.XTIMING0.bit.XRDACTIVE = 7; 67 | XintfRegs.XTIMING0.bit.XRDTRAIL = 3; 68 | 69 | // double all Zone read/write lead/active/trail timing 70 | XintfRegs.XTIMING0.bit.X2TIMING = 1; 71 | 72 | // Zone will sample XREADY signal 73 | XintfRegs.XTIMING0.bit.USEREADY = 1; 74 | XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous 75 | 76 | // Size must be either: 77 | // 0,1 = x32 or 78 | // 1,1 = x16 other values are reserved 79 | XintfRegs.XTIMING0.bit.XSIZE = 3; 80 | 81 | // Zone 6------------------------------------ 82 | // When using ready, ACTIVE must be 1 or greater 83 | // Lead must always be 1 or greater 84 | // Zone write timing 85 | XintfRegs.XTIMING6.bit.XWRLEAD = 3; 86 | XintfRegs.XTIMING6.bit.XWRACTIVE = 7; 87 | XintfRegs.XTIMING6.bit.XWRTRAIL = 3; 88 | // Zone read timing 89 | XintfRegs.XTIMING6.bit.XRDLEAD = 3; 90 | XintfRegs.XTIMING6.bit.XRDACTIVE = 7; 91 | XintfRegs.XTIMING6.bit.XRDTRAIL = 3; 92 | 93 | // double all Zone read/write lead/active/trail timing 94 | XintfRegs.XTIMING6.bit.X2TIMING = 1; 95 | 96 | // Zone will sample XREADY signal 97 | XintfRegs.XTIMING6.bit.USEREADY = 1; 98 | XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous 99 | 100 | // Size must be either: 101 | // 0,1 = x32 or 102 | // 1,1 = x16 other values are reserved 103 | XintfRegs.XTIMING6.bit.XSIZE = 3; 104 | 105 | 106 | // Zone 7------------------------------------ 107 | // When using ready, ACTIVE must be 1 or greater 108 | // Lead must always be 1 or greater 109 | // Zone write timing 110 | XintfRegs.XTIMING7.bit.XWRLEAD = 3; 111 | XintfRegs.XTIMING7.bit.XWRACTIVE = 7; 112 | XintfRegs.XTIMING7.bit.XWRTRAIL = 3; 113 | // Zone read timing 114 | XintfRegs.XTIMING7.bit.XRDLEAD = 3; 115 | XintfRegs.XTIMING7.bit.XRDACTIVE = 7; 116 | XintfRegs.XTIMING7.bit.XRDTRAIL = 3; 117 | 118 | // double all Zone read/write lead/active/trail timing 119 | XintfRegs.XTIMING7.bit.X2TIMING = 1; 120 | 121 | // Zone will sample XREADY signal 122 | XintfRegs.XTIMING7.bit.USEREADY = 1; 123 | XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous 124 | 125 | // Size must be either: 126 | // 0,1 = x32 or 127 | // 1,1 = x16 other values are reserved 128 | XintfRegs.XTIMING7.bit.XSIZE = 3; 129 | 130 | // Bank switching 131 | // Assume Zone 7 is slow, so add additional BCYC cycles 132 | // when ever switching from Zone 7 to another Zone. 133 | // This will help avoid bus contention. 134 | XintfRegs.XBANK.bit.BANK = 7; 135 | XintfRegs.XBANK.bit.BCYC = 7; 136 | EDIS; 137 | //Force a pipeline flush to ensure that the write to 138 | //the last register configured occurs before returning. 139 | 140 | InitXintf16Gpio(); 141 | // InitXintf32Gpio(); 142 | 143 | asm(" RPT #7 || NOP"); 144 | 145 | } 146 | 147 | void InitXintf32Gpio() 148 | { 149 | EALLOW; 150 | GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31 151 | GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30 152 | GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29 153 | GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28 154 | GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27 155 | GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26 156 | GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25 157 | GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24 158 | GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23 159 | GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22 160 | GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21 161 | GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20 162 | GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19 163 | GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18 164 | GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17 165 | GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16 166 | 167 | GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input 168 | GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input 169 | GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input 170 | GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input 171 | GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input 172 | GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input 173 | GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input 174 | GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input 175 | GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input 176 | GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input 177 | GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input 178 | GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input 179 | GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input 180 | GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input 181 | GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input 182 | GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input 183 | 184 | 185 | InitXintf16Gpio(); 186 | } 187 | 188 | void InitXintf16Gpio() 189 | { 190 | EALLOW; 191 | GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15 192 | GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14 193 | GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13 194 | GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12 195 | GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11 196 | GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10 197 | GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19 198 | GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8 199 | GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7 200 | GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6 201 | GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5 202 | GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4 203 | GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3 204 | GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2 205 | GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1 206 | GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0 207 | 208 | GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n 209 | GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1 210 | GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2 211 | GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3 212 | GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4 213 | GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5 214 | GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6 215 | GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7 216 | 217 | GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8 218 | GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9 219 | GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10 220 | GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11 221 | GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12 222 | GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13 223 | GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14 224 | GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15 225 | GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16 226 | GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17 227 | GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18 228 | GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 229 | 230 | GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY 231 | GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW 232 | GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0 233 | 234 | GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0 235 | GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7 236 | GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 237 | EDIS; 238 | } 239 | 240 | //=========================================================================== 241 | // No more. 242 | //=========================================================================== 243 | -------------------------------------------------------------------------------- /user_lib/src/delay.c: -------------------------------------------------------------------------------- 1 | #include "delay.h" 2 | void delay_us(unsigned long int nus) 3 | { 4 | while(nus) 5 | { 6 | DELAY_US(1); 7 | nus--; 8 | } 9 | } 10 | void delay_ms(unsigned long int nms) 11 | { 12 | while(nms) 13 | { 14 | DELAY_US(1000); 15 | nms--; 16 | } 17 | } 18 | 19 | void delay_s(unsigned long int ns) 20 | { 21 | while(ns) 22 | { 23 | delay_ms(1000); 24 | ns--; 25 | } 26 | 27 | } 28 | 29 | void delay(unsigned long int i) 30 | { 31 | while(i) 32 | { 33 | i--; 34 | } 35 | } 36 | --------------------------------------------------------------------------------