├── .ccsproject ├── .cproject ├── .gitignore ├── .project ├── 2808_lib ├── asm │ ├── DSP280x_CSMPasswords.asm │ ├── DSP280x_CodeStartBranch.asm │ ├── DSP280x_DBGIER.asm │ ├── DSP280x_DisInt.asm │ └── DSP280x_usDelay.asm ├── cmd │ └── DSP280x_Headers_nonBIOS.cmd ├── inc │ ├── DSP280x_Adc.h │ ├── DSP280x_CpuTimers.h │ ├── DSP280x_DefaultIsr.h │ ├── DSP280x_DevEmu.h │ ├── DSP280x_Device.h │ ├── DSP280x_ECan.h │ ├── DSP280x_ECap.h │ ├── DSP280x_EPwm.h │ ├── DSP280x_EPwm_defines.h │ ├── DSP280x_EQep.h │ ├── DSP280x_Examples.h │ ├── DSP280x_GlobalPrototypes.h │ ├── DSP280x_Gpio.h │ ├── DSP280x_I2c.h │ ├── DSP280x_I2c_defines.h │ ├── DSP280x_PieCtrl.h │ ├── DSP280x_PieVect.h │ ├── DSP280x_SWPrioritizedIsrLevels.h │ ├── DSP280x_Sci.h │ ├── DSP280x_Spi.h │ ├── DSP280x_SysCtrl.h │ ├── DSP280x_XIntrupt.h │ ├── IQmathLib.h │ ├── SFO.h │ ├── SFO_V5.h │ └── data.h ├── lib │ └── IQmath.lib └── src │ └── F2808_V170.lib ├── BootLoader ├── inc │ └── BootLoader.h └── src │ └── BootLoader.c ├── F2808.cmd ├── Flash2808_API_V302 ├── Flash2808_API_V302.lib ├── Flash280x_API_Config.h └── Flash280x_API_Library.h ├── bsp ├── inc │ ├── CANA.h │ ├── Flash.h │ ├── LED.h │ ├── define.h │ ├── delay.h │ └── include.h └── src │ ├── CANA.c │ ├── Flash.c │ ├── LED.c │ └── delay.c └── user ├── inc └── main.h └── src └── main.c /.ccsproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .launches 2 | .settings 3 | Debug 4 | targetConfigs 5 | # Prerequisites 6 | *.d 7 | 8 | # Object files 9 | *.o 10 | *.ko 11 | *.obj 12 | *.elf 13 | 14 | # Linker output 15 | *.ilk 16 | *.map 17 | *.exp 18 | 19 | # Precompiled Headers 20 | *.gch 21 | *.pch 22 | 23 | # Libraries 24 | *.a 25 | *.la 26 | *.lo 27 | 28 | # Shared objects (inc. Windows DLLs) 29 | *.dll 30 | *.so 31 | *.so.* 32 | *.dylib 33 | 34 | # Executables 35 | *.exe 36 | *.out 37 | *.app 38 | *.i*86 39 | *.x86_64 40 | *.hex 41 | 42 | # Debug files 43 | *.dSYM/ 44 | *.su 45 | *.idb 46 | *.pdb 47 | 48 | # Kernel Module Compile Results 49 | *.mod* 50 | .tmp_versions/ 51 | modules.order 52 | Module.symvers 53 | Mkfile.old 54 | dkms.conf 55 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | TMS32F2808_Bootloader 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | 11 | 12 | 13 | 14 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 15 | full,incremental, 16 | 17 | 18 | 19 | 20 | 21 | com.ti.ccstudio.core.ccsNature 22 | org.eclipse.cdt.core.cnature 23 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 24 | org.eclipse.cdt.core.ccnature 25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 26 | 27 | 28 | -------------------------------------------------------------------------------- /2808_lib/asm/DSP280x_CSMPasswords.asm: -------------------------------------------------------------------------------- 1 | Change .set 0 2 | .sect "csmpasswds" 3 | 4 | .if Change == 0 5 | .int 0xFFFF ;PWL0 (LSW of 128-bit password) 6 | .int 0xFFFF ;PWL1 7 | .int 0xFFFF ;PWL2 8 | .int 0xFFFF ;PWL3 9 | .int 0xFFFF ;PWL4 10 | .int 0xFFFF ;PWL5 11 | .int 0xFFFF ;PWL6 12 | .int 0xFFFF ;PWL7 (MSW of 128-bit password) 13 | .endif 14 | .if Change == 1 15 | .int 0x46CA ;PWL0 (LSW of 128-bit password) 16 | .int 0x9CD6 ;PWL1 17 | .int 0xC023 ;PWL2 18 | .int 0xE840 ;PWL3 19 | .int 0x54AB ;PWL4 20 | .int 0x9334 ;PWL5 21 | .int 0x4FF2 ;PWL6 22 | .int 0x285A ;PWL7 (MSW of 128-bit password) 23 | .endif 24 | .sect "csm_rsvd" 25 | .loop (3F7FF5h - 3F7F80h + 1) 26 | .int 0x0000 27 | .endloop 28 | 29 | -------------------------------------------------------------------------------- /2808_lib/asm/DSP280x_CodeStartBranch.asm: -------------------------------------------------------------------------------- 1 | 2 | WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 3 | 4 | .ref _c_int00 5 | .global code_start 6 | 7 | 8 | .sect "codestart" 9 | 10 | code_start: 11 | .if WD_DISABLE == 1 12 | LB wd_disable ;Branch to watchdog disable code 13 | .else 14 | LB _c_int00 ;Branch to start of boot.asm in RTS library 15 | .endif 16 | 17 | .if WD_DISABLE == 1 18 | 19 | .text 20 | wd_disable: 21 | SETC OBJMODE ;Set OBJMODE for 28x object code 22 | EALLOW ;Enable EALLOW protected register access 23 | MOVZ DP, #7029h>>6 ;Set data page for WDCR register 24 | MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD 25 | EDIS ;Disable EALLOW protected register access 26 | LB _c_int00 ;Branch to start of boot.asm in RTS library 27 | 28 | .endif 29 | 30 | 31 | .end 32 | ========================================================================= 33 | -------------------------------------------------------------------------------- /2808_lib/asm/DSP280x_DBGIER.asm: -------------------------------------------------------------------------------- 1 | .text 2 | 3 | _SetDBGIER: 4 | MOV *SP++,AL 5 | POP DBGIER 6 | LRETR 7 | 8 | -------------------------------------------------------------------------------- /2808_lib/asm/DSP280x_DisInt.asm: -------------------------------------------------------------------------------- 1 | .def _DSP28x_DisableInt 2 | .def _DSP28x_RestoreInt 3 | 4 | 5 | _DSP28x_DisableInt: 6 | PUSH ST1 7 | SETC INTM,DBGM 8 | MOV AL, *--SP 9 | LRETR 10 | 11 | _DSP28x_RestoreInt: 12 | MOV *SP++, AL 13 | POP ST1 14 | LRETR 15 | 16 | 17 | ;//=========================================================================== 18 | ;// End of file. 19 | ;//=========================================================================== 20 | 21 | 22 | -------------------------------------------------------------------------------- /2808_lib/asm/DSP280x_usDelay.asm: -------------------------------------------------------------------------------- 1 | .def _DSP28x_usDelay 2 | .sect "ramfuncs" 3 | 4 | .global __DSP28x_usDelay 5 | _DSP28x_usDelay: 6 | SUB ACC,#1 7 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 8 | LRETR 9 | 10 | -------------------------------------------------------------------------------- /2808_lib/cmd/DSP280x_Headers_nonBIOS.cmd: -------------------------------------------------------------------------------- 1 | 2 | MEMORY 3 | { 4 | PAGE 0: /* Program Memory */ 5 | 6 | PAGE 1: /* Data Memory */ 7 | 8 | DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ 9 | FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ 10 | CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ 11 | 12 | ADC_MIRROR : origin = 0x000B00, length = 0x000010 /* ADC Results register mirror */ 13 | 14 | CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ 15 | CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ 16 | CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/ 17 | 18 | PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ 19 | PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ 20 | 21 | ECANA : origin = 0x006000, length = 0x000040 /* eCAN-A control and status registers */ 22 | ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN-A local acceptance masks */ 23 | ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN-A message object time stamps */ 24 | ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN-A object time-out registers */ 25 | ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN-A mailboxes */ 26 | 27 | ECANB : origin = 0x006200, length = 0x000040 /* eCAN-B control and status registers */ 28 | ECANB_LAM : origin = 0x006240, length = 0x000040 /* eCAN-B local acceptance masks */ 29 | ECANB_MOTS : origin = 0x006280, length = 0x000040 /* eCAN-B message object time stamps */ 30 | ECANB_MOTO : origin = 0x0062C0, length = 0x000040 /* eCAN-B object time-out registers */ 31 | ECANB_MBOX : origin = 0x006300, length = 0x000100 /* eCAN-B mailboxes */ 32 | 33 | EPWM1 : origin = 0x006800, length = 0x000022 /* Enhanced PWM 1 registers */ 34 | EPWM2 : origin = 0x006840, length = 0x000022 /* Enhanced PWM 2 registers */ 35 | EPWM3 : origin = 0x006880, length = 0x000022 /* Enhanced PWM 3 registers */ 36 | EPWM4 : origin = 0x0068C0, length = 0x000022 /* Enhanced PWM 4 registers */ 37 | EPWM5 : origin = 0x006900, length = 0x000022 /* Enhanced PWM 5 registers */ 38 | EPWM6 : origin = 0x006940, length = 0x000022 /* Enhanced PWM 6 registers */ 39 | 40 | ECAP1 : origin = 0x006A00, length = 0x000020 /* Enhanced Capture 1 registers */ 41 | ECAP2 : origin = 0x006A20, length = 0x000020 /* Enhanced Capture 2 registers */ 42 | ECAP3 : origin = 0x006A40, length = 0x000020 /* Enhanced Capture 3 registers */ 43 | ECAP4 : origin = 0x006A60, length = 0x000020 /* Enhanced Capture 4 registers */ 44 | 45 | EQEP1 : origin = 0x006B00, length = 0x000040 /* Enhanced QEP 1 registers */ 46 | EQEP2 : origin = 0x006B40, length = 0x000040 /* Enhanced QEP 2 registers */ 47 | 48 | GPIOCTRL : origin = 0x006F80, length = 0x000040 /* GPIO control registers */ 49 | GPIODAT : origin = 0x006FC0, length = 0x000020 /* GPIO data registers */ 50 | GPIOINT : origin = 0x006FE0, length = 0x000020 /* GPIO interrupt/LPM registers */ 51 | 52 | SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ 53 | SPIA : origin = 0x007040, length = 0x000010 /* SPI-A registers */ 54 | SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ 55 | XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ 56 | 57 | ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ 58 | SPIB : origin = 0x007740, length = 0x000010 /* SPI-B registers */ 59 | 60 | SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ 61 | SPIC : origin = 0x007760, length = 0x000010 /* SPI-C registers */ 62 | 63 | SPID : origin = 0x007780, length = 0x000010 /* SPI-D registers */ 64 | 65 | I2CA : origin = 0x007900, length = 0x000040 /* I2C-A registers */ 66 | 67 | CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ 68 | } 69 | 70 | 71 | SECTIONS 72 | { 73 | PieVectTableFile : > PIE_VECT, PAGE = 1 74 | 75 | /*** Peripheral Frame 0 Register Structures ***/ 76 | DevEmuRegsFile : > DEV_EMU, PAGE = 1 77 | FlashRegsFile : > FLASH_REGS, PAGE = 1 78 | CsmRegsFile : > CSM, PAGE = 1 79 | AdcMirrorFile : > ADC_MIRROR, PAGE = 1 80 | CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 81 | CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 82 | CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 83 | PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 84 | 85 | /*** Peripheral Frame 1 Register Structures ***/ 86 | ECanaRegsFile : > ECANA, PAGE = 1 87 | ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 88 | ECanaMboxesFile : > ECANA_MBOX PAGE = 1 89 | ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 90 | ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 91 | 92 | ECanbRegsFile : > ECANB, PAGE = 1 93 | ECanbLAMRegsFile : > ECANB_LAM PAGE = 1 94 | ECanbMboxesFile : > ECANB_MBOX PAGE = 1 95 | ECanbMOTSRegsFile : > ECANB_MOTS PAGE = 1 96 | ECanbMOTORegsFile : > ECANB_MOTO PAGE = 1 97 | 98 | EPwm1RegsFile : > EPWM1 PAGE = 1 99 | EPwm2RegsFile : > EPWM2 PAGE = 1 100 | EPwm3RegsFile : > EPWM3 PAGE = 1 101 | EPwm4RegsFile : > EPWM4 PAGE = 1 102 | EPwm5RegsFile : > EPWM5 PAGE = 1 103 | EPwm6RegsFile : > EPWM6 PAGE = 1 104 | 105 | ECap1RegsFile : > ECAP1 PAGE = 1 106 | ECap2RegsFile : > ECAP2 PAGE = 1 107 | ECap3RegsFile : > ECAP3 PAGE = 1 108 | ECap4RegsFile : > ECAP4 PAGE = 1 109 | 110 | EQep1RegsFile : > EQEP1 PAGE = 1 111 | EQep2RegsFile : > EQEP2 PAGE = 1 112 | 113 | GpioCtrlRegsFile : > GPIOCTRL PAGE = 1 114 | GpioDataRegsFile : > GPIODAT PAGE = 1 115 | GpioIntRegsFile : > GPIOINT PAGE = 1 116 | 117 | /*** Peripheral Frame 2 Register Structures ***/ 118 | SysCtrlRegsFile : > SYSTEM, PAGE = 1 119 | SpiaRegsFile : > SPIA, PAGE = 1 120 | SciaRegsFile : > SCIA, PAGE = 1 121 | XIntruptRegsFile : > XINTRUPT, PAGE = 1 122 | AdcRegsFile : > ADC, PAGE = 1 123 | SpibRegsFile : > SPIB, PAGE = 1 124 | ScibRegsFile : > SCIB, PAGE = 1 125 | SpicRegsFile : > SPIC, PAGE = 1 126 | SpidRegsFile : > SPID, PAGE = 1 127 | I2caRegsFile : > I2CA, PAGE = 1 128 | 129 | /*** Code Security Module Register Structures ***/ 130 | CsmPwlFile : > CSM_PWL, PAGE = 1 131 | } 132 | 133 | 134 | /* 135 | //=========================================================================== 136 | // End of file. 137 | //=========================================================================== 138 | */ 139 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Adc.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: December 2, 2004 13:40:05 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Adc.h 6 | // 7 | // TITLE: DSP280x Device ADC Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_ADC_H 15 | #define DSP280x_ADC_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | 22 | //--------------------------------------------------------------------------- 23 | // ADC Individual Register Bit Definitions: 24 | 25 | struct ADCTRL1_BITS { // bits description 26 | Uint16 rsvd1:4; // 3:0 reserved 27 | Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode 28 | Uint16 SEQ_OVRD:1; // 5 Sequencer override 29 | Uint16 CONT_RUN:1; // 6 Continuous run 30 | Uint16 CPS:1; // 7 ADC core clock pre-scalar 31 | Uint16 ACQ_PS:4; // 11:8 Acquisition window size 32 | Uint16 SUSMOD:2; // 13:12 Emulation suspend mode 33 | Uint16 RESET:1; // 14 ADC reset 34 | Uint16 rsvd2:1; // 15 reserved 35 | }; 36 | 37 | 38 | union ADCTRL1_REG { 39 | Uint16 all; 40 | struct ADCTRL1_BITS bit; 41 | }; 42 | 43 | 44 | struct ADCTRL2_BITS { // bits description 45 | Uint16 EPWM_SOCB_SEQ2:1; // 0 EPWM compare B SOC mask for SEQ2 46 | Uint16 rsvd1:1; // 1 reserved 47 | Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode 48 | Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable 49 | Uint16 rsvd2:1; // 4 reserved 50 | Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 51 | Uint16 RST_SEQ2:1; // 6 Reset SEQ2 52 | Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 53 | Uint16 EPWM_SOCA_SEQ1:1; // 8 EPWM compare B SOC mask for SEQ1 54 | Uint16 rsvd3:1; // 9 reserved 55 | Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode 56 | Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable 57 | Uint16 rsvd4:1; // 12 reserved 58 | Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 59 | Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 60 | Uint16 EPWM_SOCB_SEQ:1; // 15 EPWM compare B SOC enable 61 | }; 62 | 63 | 64 | union ADCTRL2_REG { 65 | Uint16 all; 66 | struct ADCTRL2_BITS bit; 67 | }; 68 | 69 | 70 | struct ADCASEQSR_BITS { // bits description 71 | Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state 72 | Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state 73 | Uint16 rsvd1:1; // 7 reserved 74 | Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status 75 | Uint16 rsvd2:4; // 15:12 reserved 76 | }; 77 | 78 | union ADCASEQSR_REG { 79 | Uint16 all; 80 | struct ADCASEQSR_BITS bit; 81 | }; 82 | 83 | 84 | struct ADCMAXCONV_BITS { // bits description 85 | Uint16 MAX_CONV1:4; // 3:0 Max number of conversions 86 | Uint16 MAX_CONV2:3; // 6:4 Max number of conversions 87 | Uint16 rsvd1:9; // 15:7 reserved 88 | }; 89 | 90 | union ADCMAXCONV_REG { 91 | Uint16 all; 92 | struct ADCMAXCONV_BITS bit; 93 | }; 94 | 95 | 96 | struct ADCCHSELSEQ1_BITS { // bits description 97 | Uint16 CONV00:4; // 3:0 Conversion selection 00 98 | Uint16 CONV01:4; // 7:4 Conversion selection 01 99 | Uint16 CONV02:4; // 11:8 Conversion selection 02 100 | Uint16 CONV03:4; // 15:12 Conversion selection 03 101 | }; 102 | 103 | union ADCCHSELSEQ1_REG{ 104 | Uint16 all; 105 | struct ADCCHSELSEQ1_BITS bit; 106 | }; 107 | 108 | struct ADCCHSELSEQ2_BITS { // bits description 109 | Uint16 CONV04:4; // 3:0 Conversion selection 04 110 | Uint16 CONV05:4; // 7:4 Conversion selection 05 111 | Uint16 CONV06:4; // 11:8 Conversion selection 06 112 | Uint16 CONV07:4; // 15:12 Conversion selection 07 113 | }; 114 | 115 | union ADCCHSELSEQ2_REG{ 116 | Uint16 all; 117 | struct ADCCHSELSEQ2_BITS bit; 118 | }; 119 | 120 | struct ADCCHSELSEQ3_BITS { // bits description 121 | Uint16 CONV08:4; // 3:0 Conversion selection 08 122 | Uint16 CONV09:4; // 7:4 Conversion selection 09 123 | Uint16 CONV10:4; // 11:8 Conversion selection 10 124 | Uint16 CONV11:4; // 15:12 Conversion selection 11 125 | }; 126 | 127 | union ADCCHSELSEQ3_REG{ 128 | Uint16 all; 129 | struct ADCCHSELSEQ3_BITS bit; 130 | }; 131 | 132 | struct ADCCHSELSEQ4_BITS { // bits description 133 | Uint16 CONV12:4; // 3:0 Conversion selection 12 134 | Uint16 CONV13:4; // 7:4 Conversion selection 13 135 | Uint16 CONV14:4; // 11:8 Conversion selection 14 136 | Uint16 CONV15:4; // 15:12 Conversion selection 15 137 | }; 138 | 139 | union ADCCHSELSEQ4_REG { 140 | Uint16 all; 141 | struct ADCCHSELSEQ4_BITS bit; 142 | }; 143 | 144 | struct ADCTRL3_BITS { // bits description 145 | Uint16 SMODE_SEL:1; // 0 Sampling mode select 146 | Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider 147 | Uint16 ADCPWDN:1; // 5 ADC powerdown 148 | Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down 149 | Uint16 rsvd1:8; // 15:8 reserved 150 | }; 151 | 152 | union ADCTRL3_REG { 153 | Uint16 all; 154 | struct ADCTRL3_BITS bit; 155 | }; 156 | 157 | 158 | struct ADCST_BITS { // bits description 159 | Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag 160 | Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag 161 | Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status 162 | Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status 163 | Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear 164 | Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear 165 | Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 166 | Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 167 | Uint16 rsvd1:8; // 15:8 reserved 168 | }; 169 | 170 | 171 | union ADCST_REG { 172 | Uint16 all; 173 | struct ADCST_BITS bit; 174 | }; 175 | 176 | struct ADCREFSEL_BITS { // bits description 177 | Uint16 rsvd1:14; // 13:0 reserved 178 | Uint16 REF_SEL:2; // 15:14 Reference select 179 | }; 180 | union ADCREFSEL_REG { 181 | Uint16 all; 182 | struct ADCREFSEL_BITS bit; 183 | }; 184 | 185 | struct ADCOFFTRIM_BITS{ // bits description 186 | int16 OFFSET_TRIM:9; // 8:0 Offset Trim 187 | Uint16 rsvd1:7; // 15:9 reserved 188 | }; 189 | 190 | union ADCOFFTRIM_REG{ 191 | Uint16 all; 192 | struct ADCOFFTRIM_BITS bit; 193 | }; 194 | struct ADC_REGS { 195 | union ADCTRL1_REG ADCTRL1; // ADC Control 1 196 | union ADCTRL2_REG ADCTRL2; // ADC Control 2 197 | union ADCMAXCONV_REG ADCMAXCONV; // Max conversions 198 | union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 199 | union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 200 | union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 201 | union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 202 | union ADCASEQSR_REG ADCASEQSR; // Autosequence status register 203 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 204 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 205 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 206 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 207 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 208 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 209 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 210 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 211 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 212 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 213 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 214 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 215 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 216 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 217 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 218 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 219 | union ADCTRL3_REG ADCTRL3; // ADC Control 3 220 | union ADCST_REG ADCST; // ADC Status Register 221 | Uint16 rsvd1; 222 | Uint16 rsvd2; 223 | union ADCREFSEL_REG ADCREFSEL; // Reference Select Register 224 | union ADCOFFTRIM_REG ADCOFFTRIM; // Offset Trim Register 225 | }; 226 | 227 | 228 | struct ADC_RESULT_MIRROR_REGS 229 | { 230 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 231 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 232 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 233 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 234 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 235 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 236 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 237 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 238 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 239 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 240 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 241 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 242 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 243 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 244 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 245 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 246 | }; 247 | 248 | //--------------------------------------------------------------------------- 249 | // ADC External References & Function Declarations: 250 | // 251 | extern volatile struct ADC_REGS AdcRegs; 252 | extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror; 253 | 254 | 255 | #ifdef __cplusplus 256 | } 257 | #endif /* extern "C" */ 258 | 259 | 260 | #endif // end of DSP280x_ADC_H definition 261 | 262 | //=========================================================================== 263 | // End of file. 264 | //=========================================================================== 265 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 14, 2009 16:42:57 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_CpuTimers.h 6 | // 7 | // TITLE: DSP280x CPU 32-bit Timers Register Definitions. 8 | // 9 | // NOTES: CpuTimer2 is reserved for use with DSP BIOS and 10 | // other realtime operating systems. 11 | // 12 | // Do not use this timers in your application if you ever plan 13 | // on integrating DSP-BIOS or another realtime OS. 14 | // 15 | //########################################################################### 16 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 17 | // $Release Date: July 27, 2009 $ 18 | //########################################################################### 19 | 20 | #ifndef DSP280x_CPU_TIMERS_H 21 | #define DSP280x_CPU_TIMERS_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | //--------------------------------------------------------------------------- 28 | // CPU Timer Register Bit Definitions: 29 | // 30 | // 31 | // TCR: Control register bit definitions: 32 | struct TCR_BITS { // bits description 33 | Uint16 rsvd1:4; // 3:0 reserved 34 | Uint16 TSS:1; // 4 Timer Start/Stop 35 | Uint16 TRB:1; // 5 Timer reload 36 | Uint16 rsvd2:4; // 9:6 reserved 37 | Uint16 SOFT:1; // 10 Emulation modes 38 | Uint16 FREE:1; // 11 39 | Uint16 rsvd3:2; // 12:13 reserved 40 | Uint16 TIE:1; // 14 Output enable 41 | Uint16 TIF:1; // 15 Interrupt flag 42 | }; 43 | 44 | union TCR_REG { 45 | Uint16 all; 46 | struct TCR_BITS bit; 47 | }; 48 | 49 | // TPR: Pre-scale low bit definitions: 50 | struct TPR_BITS { // bits description 51 | Uint16 TDDR:8; // 7:0 Divide-down low 52 | Uint16 PSC:8; // 15:8 Prescale counter low 53 | }; 54 | 55 | union TPR_REG { 56 | Uint16 all; 57 | struct TPR_BITS bit; 58 | }; 59 | 60 | // TPRH: Pre-scale high bit definitions: 61 | struct TPRH_BITS { // bits description 62 | Uint16 TDDRH:8; // 7:0 Divide-down high 63 | Uint16 PSCH:8; // 15:8 Prescale counter high 64 | }; 65 | 66 | union TPRH_REG { 67 | Uint16 all; 68 | struct TPRH_BITS bit; 69 | }; 70 | 71 | // TIM, TIMH: Timer register definitions: 72 | struct TIM_REG { 73 | Uint16 LSW; 74 | Uint16 MSW; 75 | }; 76 | 77 | union TIM_GROUP { 78 | Uint32 all; 79 | struct TIM_REG half; 80 | }; 81 | 82 | // PRD, PRDH: Period register definitions: 83 | struct PRD_REG { 84 | Uint16 LSW; 85 | Uint16 MSW; 86 | }; 87 | 88 | union PRD_GROUP { 89 | Uint32 all; 90 | struct PRD_REG half; 91 | }; 92 | 93 | //--------------------------------------------------------------------------- 94 | // CPU Timer Register File: 95 | // 96 | struct CPUTIMER_REGS { 97 | union TIM_GROUP TIM; // Timer counter register 98 | union PRD_GROUP PRD; // Period register 99 | union TCR_REG TCR; // Timer control register 100 | Uint16 rsvd1; // reserved 101 | union TPR_REG TPR; // Timer pre-scale low 102 | union TPRH_REG TPRH; // Timer pre-scale high 103 | }; 104 | 105 | //--------------------------------------------------------------------------- 106 | // CPU Timer Support Variables: 107 | // 108 | struct CPUTIMER_VARS { 109 | volatile struct CPUTIMER_REGS *RegsAddr; 110 | Uint32 InterruptCount; 111 | float CPUFreqInMHz; 112 | float PeriodInUSec; 113 | }; 114 | 115 | //--------------------------------------------------------------------------- 116 | // Function prototypes and external definitions: 117 | // 118 | void InitCpuTimers(void); 119 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 120 | 121 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 122 | extern struct CPUTIMER_VARS CpuTimer0; 123 | 124 | // CpuTimer2 is reserved for DSP BIOS & other RTOS 125 | extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 126 | extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 127 | 128 | extern struct CPUTIMER_VARS CpuTimer1; 129 | extern struct CPUTIMER_VARS CpuTimer2; 130 | 131 | //--------------------------------------------------------------------------- 132 | // Usefull Timer Operations: 133 | // 134 | // Start Timer: 135 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 136 | 137 | // Stop Timer: 138 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 139 | 140 | // Reload Timer With period Value: 141 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 142 | 143 | // Read 32-Bit Timer Value: 144 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 145 | 146 | // Read 32-Bit Period Value: 147 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 148 | 149 | // CpuTimer2 is reserved for DSP BIOS & other RTOS 150 | // Do not use this timer if you ever plan on integrating 151 | // DSP-BIOS or another realtime OS. 152 | 153 | // Start Timer: 154 | #define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 155 | #define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 156 | 157 | // Stop Timer: 158 | #define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 159 | #define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 160 | 161 | // Reload Timer With period Value: 162 | #define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 163 | #define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 164 | 165 | // Read 32-Bit Timer Value: 166 | #define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 167 | #define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 168 | 169 | // Read 32-Bit Period Value: 170 | #define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 171 | #define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 172 | 173 | 174 | #ifdef __cplusplus 175 | } 176 | #endif /* extern "C" */ 177 | 178 | #endif // end of DSP280x_CPU_TIMERS_H definition 179 | 180 | 181 | //=========================================================================== 182 | // End of file. 183 | //=========================================================================== 184 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: December 1, 2004 16:21:01 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_DefaultIsr.h 6 | // 7 | // TITLE: DSP280x Devices Default Interrupt Service Routines Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280X_DEFAULT_ISR_H 15 | #define DSP280X_DEFAULT_ISR_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | 22 | //--------------------------------------------------------------------------- 23 | // Default Interrupt Service Routine Declarations: 24 | // 25 | // The following function prototypes are for the 26 | // default ISR routines used with the default PIE vector table. 27 | // This default vector table is found in the DSP280x_PieVect.h 28 | // file. 29 | // 30 | 31 | // Non-Peripheral Interrupts: 32 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 33 | interrupt void INT14_ISR(void); // CPU-Timer2 34 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 35 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 36 | interrupt void EMUINT_ISR(void); // Emulation interrupt 37 | interrupt void NMI_ISR(void); // Non-maskable interrupt 38 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 39 | interrupt void USER1_ISR(void); // User Defined trap 1 40 | interrupt void USER2_ISR(void); // User Defined trap 2 41 | interrupt void USER3_ISR(void); // User Defined trap 3 42 | interrupt void USER4_ISR(void); // User Defined trap 4 43 | interrupt void USER5_ISR(void); // User Defined trap 5 44 | interrupt void USER6_ISR(void); // User Defined trap 6 45 | interrupt void USER7_ISR(void); // User Defined trap 7 46 | interrupt void USER8_ISR(void); // User Defined trap 8 47 | interrupt void USER9_ISR(void); // User Defined trap 9 48 | interrupt void USER10_ISR(void); // User Defined trap 10 49 | interrupt void USER11_ISR(void); // User Defined trap 11 50 | interrupt void USER12_ISR(void); // User Defined trap 12 51 | 52 | // Group 1 PIE Interrupt Service Routines: 53 | interrupt void SEQ1INT_ISR(void); // ADC Sequencer 1 ISR 54 | interrupt void SEQ2INT_ISR(void); // ADC Sequencer 2 ISR 55 | interrupt void XINT1_ISR(void); // External interrupt 1 56 | interrupt void XINT2_ISR(void); // External interrupt 2 57 | interrupt void ADCINT_ISR(void); // ADC 58 | interrupt void TINT0_ISR(void); // Timer 0 59 | interrupt void WAKEINT_ISR(void); // WD 60 | 61 | // Group 2 PIE Interrupt Service Routines: 62 | interrupt void EPWM1_TZINT_ISR(void); // EPWM-1 63 | interrupt void EPWM2_TZINT_ISR(void); // EPWM-2 64 | interrupt void EPWM3_TZINT_ISR(void); // EPWM-3 65 | interrupt void EPWM4_TZINT_ISR(void); // EPWM-4 66 | interrupt void EPWM5_TZINT_ISR(void); // EPWM-5 67 | interrupt void EPWM6_TZINT_ISR(void); // EPWM-6 68 | 69 | // Group 3 PIE Interrupt Service Routines: 70 | interrupt void EPWM1_INT_ISR(void); // EPWM-1 71 | interrupt void EPWM2_INT_ISR(void); // EPWM-2 72 | interrupt void EPWM3_INT_ISR(void); // EPWM-3 73 | interrupt void EPWM4_INT_ISR(void); // EPWM-4 74 | interrupt void EPWM5_INT_ISR(void); // EPWM-5 75 | interrupt void EPWM6_INT_ISR(void); // EPWM-6 76 | 77 | // Group 4 PIE Interrupt Service Routines: 78 | interrupt void ECAP1_INT_ISR(void); // ECAP-1 79 | interrupt void ECAP2_INT_ISR(void); // ECAP-2 80 | interrupt void ECAP3_INT_ISR(void); // ECAP-3 81 | interrupt void ECAP4_INT_ISR(void); // ECAP-4 82 | 83 | // Group 5 PIE Interrupt Service Routines: 84 | interrupt void EQEP1_INT_ISR(void); // EQEP-1 85 | interrupt void EQEP2_INT_ISR(void); // EQEP-2 86 | 87 | // Group 6 PIE Interrupt Service Routines: 88 | interrupt void SPIRXINTA_ISR(void); // SPI-A 89 | interrupt void SPITXINTA_ISR(void); // SPI-A 90 | interrupt void SPIRXINTB_ISR(void); // SPI-B 91 | interrupt void SPITXINTB_ISR(void); // SPI-B 92 | interrupt void SPIRXINTC_ISR(void); // SPI-C 93 | interrupt void SPITXINTC_ISR(void); // SPI-C 94 | interrupt void SPIRXINTD_ISR(void); // SPI-D 95 | interrupt void SPITXINTD_ISR(void); // SPI-D 96 | 97 | // Group 7 PIE Interrupt Service Routines: 98 | 99 | // Group 8 PIE Interrupt Service Routines: 100 | interrupt void I2CINT1A_ISR(void); // I2C-A 101 | interrupt void I2CINT2A_ISR(void); // I2C-A 102 | 103 | // Group 9 PIE Interrupt Service Routines: 104 | interrupt void SCIRXINTA_ISR(void); // SCI-A 105 | interrupt void SCITXINTA_ISR(void); // SCI-A 106 | interrupt void SCIRXINTB_ISR(void); // SCI-B 107 | interrupt void SCITXINTB_ISR(void); // SCI-B 108 | interrupt void ECAN0INTA_ISR(void); // eCAN-A 109 | interrupt void ECAN1INTA_ISR(void); // eCAN-A 110 | interrupt void ECAN0INTB_ISR(void); // eCAN-B 111 | interrupt void ECAN1INTB_ISR(void); // eCAN-B 112 | 113 | // Group 10 PIE Interrupt Service Routines: 114 | 115 | // Group 11 PIE Interrupt Service Routines: 116 | 117 | // Group 12 PIE Interrupt Service Routines: 118 | 119 | // Catch-all for Reserved Locations For testing purposes: 120 | interrupt void PIE_RESERVED(void); // Reserved for test 121 | interrupt void rsvd_ISR(void); // for test 122 | interrupt void INT_NOTUSED_ISR(void); // for unused interrupts 123 | 124 | #ifdef __cplusplus 125 | } 126 | #endif /* extern "C" */ 127 | 128 | #endif // end of DSP280x_DEFAULT_ISR_H definition 129 | 130 | //=========================================================================== 131 | // End of file. 132 | //=========================================================================== 133 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_DevEmu.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: November 16, 2007 13:56:39 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_DevEmu.h 6 | // 7 | // TITLE: DSP280x Device Emulation Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_DEV_EMU_H 15 | #define DSP280x_DEV_EMU_H 16 | 17 | #ifdef __cplusplus 18 | extern "C" { 19 | #endif 20 | 21 | //--------------------------------------------------------------------------- 22 | // Device Emulation Register Bit Definitions: 23 | // 24 | // Device Configuration Register Bit Definitions 25 | struct DEVICECNF_BITS { // bits description 26 | Uint16 rsvd1:3; // 2:0 reserved 27 | Uint16 VMAPS:1; // 3 VMAP Status 28 | Uint16 rsvd2:1; // 4 reserved 29 | Uint16 XRSn:1; // 5 XRSn Signal Status 30 | Uint16 rsvd3:10; // 15:6 31 | Uint16 rsvd4:3; // 18:6 32 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 33 | Uint16 rsvd5:12; // 31:20 reserved 34 | }; 35 | 36 | union DEVICECNF_REG { 37 | Uint32 all; 38 | struct DEVICECNF_BITS bit; 39 | }; 40 | 41 | // PARTID 42 | struct PARTID_BITS { // bits description 43 | Uint16 PARTNO:8; // 7:0 Part Number 44 | Uint16 PARTTYPE:8; // 15:8 Part Type 45 | }; 46 | 47 | union PARTID_REG { 48 | Uint16 all; 49 | struct PARTID_BITS bit; 50 | }; 51 | 52 | struct DEV_EMU_REGS { 53 | union DEVICECNF_REG DEVICECNF; // device configuration 54 | union PARTID_REG PARTID; // Part ID 55 | Uint16 REVID; // Device ID 56 | Uint16 PROTSTART; // Write-Read protection start 57 | Uint16 PROTRANGE; // Write-Read protection range 58 | Uint16 rsvd2[202]; 59 | }; 60 | 61 | //--------------------------------------------------------------------------- 62 | // Device Emulation Register References & Function Declarations: 63 | // 64 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 65 | 66 | #ifdef __cplusplus 67 | } 68 | #endif /* extern "C" */ 69 | 70 | #endif // end of DSP280x_DEV_EMU_H definition 71 | 72 | //=========================================================================== 73 | // End of file. 74 | //=========================================================================== 75 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Device.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/6 $ 2 | // Checkin $Date: December 17, 2007 13:13:48 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Device.h 6 | // 7 | // TITLE: DSP280x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_DEVICE_H 15 | #define DSP280x_DEVICE_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | #define TARGET 1 24 | //--------------------------------------------------------------------------- 25 | // User To Select Target Device: 26 | 27 | #define DSP28_28015 0 28 | #define DSP28_28016 0 29 | #define DSP28_2809 0 30 | #define DSP28_2808 TARGET 31 | #define DSP28_2806 0 32 | #define DSP28_2802 0 33 | #define DSP28_2801 0 34 | 35 | //--------------------------------------------------------------------------- 36 | // Common CPU Definitions: 37 | // 38 | 39 | extern cregister volatile unsigned int IFR; 40 | extern cregister volatile unsigned int IER; 41 | 42 | #define EINT asm(" clrc INTM") 43 | #define DINT asm(" setc INTM") 44 | #define ERTM asm(" clrc DBGM") 45 | #define DRTM asm(" setc DBGM") 46 | #define EALLOW asm(" EALLOW") 47 | #define EDIS asm(" EDIS") 48 | #define ESTOP0 asm(" ESTOP0") 49 | 50 | #define M_INT1 0x0001 51 | #define M_INT2 0x0002 52 | #define M_INT3 0x0004 53 | #define M_INT4 0x0008 54 | #define M_INT5 0x0010 55 | #define M_INT6 0x0020 56 | #define M_INT7 0x0040 57 | #define M_INT8 0x0080 58 | #define M_INT9 0x0100 59 | #define M_INT10 0x0200 60 | #define M_INT11 0x0400 61 | #define M_INT12 0x0800 62 | #define M_INT13 0x1000 63 | #define M_INT14 0x2000 64 | #define M_DLOG 0x4000 65 | #define M_RTOS 0x8000 66 | 67 | #define BIT0 0x0001 68 | #define BIT1 0x0002 69 | #define BIT2 0x0004 70 | #define BIT3 0x0008 71 | #define BIT4 0x0010 72 | #define BIT5 0x0020 73 | #define BIT6 0x0040 74 | #define BIT7 0x0080 75 | #define BIT8 0x0100 76 | #define BIT9 0x0200 77 | #define BIT10 0x0400 78 | #define BIT11 0x0800 79 | #define BIT12 0x1000 80 | #define BIT13 0x2000 81 | #define BIT14 0x4000 82 | #define BIT15 0x8000 83 | 84 | 85 | 86 | //--------------------------------------------------------------------------- 87 | // For Portability, User Is Recommended To Use Following Data Type Size 88 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 89 | // 90 | 91 | #ifndef DSP28_DATA_TYPES 92 | #define DSP28_DATA_TYPES 93 | typedef int int16; 94 | typedef long int32; 95 | typedef long long int64; 96 | typedef unsigned int Uint16; 97 | typedef unsigned long Uint32; 98 | typedef unsigned long long Uint64; 99 | typedef float float32; 100 | typedef long double float64; 101 | #endif 102 | 103 | 104 | //--------------------------------------------------------------------------- 105 | // Include All Peripheral Header Files: 106 | // 107 | 108 | #include "DSP280x_Adc.h" // ADC Registers 109 | #include "DSP280x_DevEmu.h" // Device Emulation Registers 110 | #include "DSP280x_CpuTimers.h" // 32-bit CPU Timers 111 | #include "DSP280x_ECan.h" // Enhanced eCAN Registers 112 | #include "DSP280x_ECap.h" // Enhanced Capture 113 | #include "DSP280x_EPwm.h" // Enhanced PWM 114 | #include "DSP280x_EQep.h" // Enhanced QEP 115 | #include "DSP280x_Gpio.h" // General Purpose I/O Registers 116 | #include "DSP280x_I2c.h" // I2C Registers 117 | #include "DSP280x_PieCtrl.h" // PIE Control Registers 118 | #include "DSP280x_PieVect.h" // PIE Vector Table 119 | #include "DSP280x_Spi.h" // SPI Registers 120 | #include "DSP280x_Sci.h" // SCI Registers 121 | #include "DSP280x_SysCtrl.h" // System Control/Power Modes 122 | #include "DSP280x_XIntrupt.h" // External Interrupts 123 | 124 | #if DSP28_2809 || DSP28_2808 125 | #define DSP28_EPWM1 1 126 | #define DSP28_EPWM2 1 127 | #define DSP28_EPWM3 1 128 | #define DSP28_EPWM4 1 129 | #define DSP28_EPWM5 1 130 | #define DSP28_EPWM6 1 131 | #define DSP28_ECAP1 1 132 | #define DSP28_ECAP2 1 133 | #define DSP28_ECAP3 1 134 | #define DSP28_ECAP4 1 135 | #define DSP28_EQEP1 1 136 | #define DSP28_EQEP2 1 137 | #define DSP28_ECANA 1 138 | #define DSP28_ECANB 1 139 | #define DSP28_SPIA 1 140 | #define DSP28_SPIB 1 141 | #define DSP28_SPIC 1 142 | #define DSP28_SPID 1 143 | #define DSP28_SCIA 1 144 | #define DSP28_SCIB 1 145 | #define DSP28_I2CA 1 146 | #endif // end DSP28_2809 || DSP_2808 147 | 148 | 149 | #if DSP28_2806 150 | #define DSP28_EPWM1 1 151 | #define DSP28_EPWM2 1 152 | #define DSP28_EPWM3 1 153 | #define DSP28_EPWM4 1 154 | #define DSP28_EPWM5 1 155 | #define DSP28_EPWM6 1 156 | #define DSP28_ECAP1 1 157 | #define DSP28_ECAP2 1 158 | #define DSP28_ECAP3 1 159 | #define DSP28_ECAP4 1 160 | #define DSP28_EQEP1 1 161 | #define DSP28_EQEP2 1 162 | #define DSP28_ECANA 1 163 | #define DSP28_ECANB 0 164 | #define DSP28_SPIA 1 165 | #define DSP28_SPIB 1 166 | #define DSP28_SPIC 1 167 | #define DSP28_SPID 1 168 | #define DSP28_SCIA 1 169 | #define DSP28_SCIB 1 170 | #define DSP28_I2CA 1 171 | #endif // end DSP28_2806 172 | 173 | 174 | #if DSP28_2802 || DSP28_2801 175 | #define DSP28_EPWM1 1 176 | #define DSP28_EPWM2 1 177 | #define DSP28_EPWM3 1 178 | #define DSP28_EPWM4 0 179 | #define DSP28_EPWM5 0 180 | #define DSP28_EPWM6 0 181 | #define DSP28_ECAP1 1 182 | #define DSP28_ECAP2 1 183 | #define DSP28_ECAP3 0 184 | #define DSP28_ECAP4 0 185 | #define DSP28_EQEP1 1 186 | #define DSP28_EQEP2 0 187 | #define DSP28_ECANA 1 188 | #define DSP28_ECANB 0 189 | #define DSP28_SPIA 1 190 | #define DSP28_SPIB 1 191 | #define DSP28_SPIC 0 192 | #define DSP28_SPID 0 193 | #define DSP28_SCIA 1 194 | #define DSP28_SCIB 0 195 | #define DSP28_I2CA 1 196 | #endif // end DSP28_2802 || DSP_2801 197 | 198 | 199 | #if DSP28_28016 200 | #define DSP28_EPWM1 1 201 | #define DSP28_EPWM2 1 202 | #define DSP28_EPWM3 1 203 | #define DSP28_EPWM4 1 204 | #define DSP28_EPWM5 0 205 | #define DSP28_EPWM6 0 206 | #define DSP28_ECAP1 1 207 | #define DSP28_ECAP2 1 208 | #define DSP28_ECAP3 0 209 | #define DSP28_ECAP4 0 210 | #define DSP28_EQEP1 0 211 | #define DSP28_EQEP2 0 212 | #define DSP28_ECANA 1 213 | #define DSP28_ECANB 0 214 | #define DSP28_SPIA 1 215 | #define DSP28_SPIB 0 216 | #define DSP28_SPIC 0 217 | #define DSP28_SPID 0 218 | #define DSP28_SCIA 1 219 | #define DSP28_SCIB 0 220 | #define DSP28_I2CA 1 221 | #endif // end DSP28_28016 222 | 223 | #if DSP28_28015 224 | #define DSP28_EPWM1 1 225 | #define DSP28_EPWM2 1 226 | #define DSP28_EPWM3 1 227 | #define DSP28_EPWM4 1 228 | #define DSP28_EPWM5 0 229 | #define DSP28_EPWM6 0 230 | #define DSP28_ECAP1 1 231 | #define DSP28_ECAP2 1 232 | #define DSP28_ECAP3 0 233 | #define DSP28_ECAP4 0 234 | #define DSP28_EQEP1 0 235 | #define DSP28_EQEP2 0 236 | #define DSP28_ECANA 0 237 | #define DSP28_ECANB 0 238 | #define DSP28_SPIA 1 239 | #define DSP28_SPIB 0 240 | #define DSP28_SPIC 0 241 | #define DSP28_SPID 0 242 | #define DSP28_SCIA 1 243 | #define DSP28_SCIB 0 244 | #define DSP28_I2CA 1 245 | #endif // end DSP28_28015 246 | 247 | 248 | 249 | #ifdef __cplusplus 250 | } 251 | #endif /* extern "C" */ 252 | 253 | #endif // end of DSP280x_DEVICE_H definition 254 | 255 | 256 | //=========================================================================== 257 | // End of file. 258 | //=========================================================================== 259 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_ECap.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: April 7, 2005 13:47:28 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_ECap.h 6 | // 7 | // TITLE: DSP280x Enhanced Capture Module Register Bit Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_ECAP_H 15 | #define DSP280x_ECAP_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //---------------------------------------------------- 23 | // Capture control register 1 bit definitions */ 24 | struct ECCTL1_BITS { // bits description 25 | Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select 26 | Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 27 | Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select 28 | Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 29 | Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select 30 | Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 31 | Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select 32 | Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 33 | Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event 34 | Uint16 PRESCALE:5; // 13:9 Event Filter prescale select 35 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 36 | }; 37 | 38 | union ECCTL1_REG { 39 | Uint16 all; 40 | struct ECCTL1_BITS bit; 41 | }; 42 | 43 | 44 | // In V1.1 the STOPVALUE bit field was changed to 45 | // STOP_WRAP. This correlated to a silicon change from 46 | // F280x Rev 0 to Rev A. 47 | //---------------------------------------------------- 48 | // Capture control register 2 bit definitions */ 49 | struct ECCTL2_BITS { // bits description 50 | Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot 51 | Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous 52 | Uint16 REARM:1; // 3 One-shot re-arm 53 | Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop 54 | Uint16 SYNCI_EN:1; // 5 Counter sync-in select 55 | Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode 56 | Uint16 SWSYNC:1; // 8 SW forced counter sync 57 | Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select 58 | Uint16 APWMPOL:1; // 10 APWM output polarity select 59 | Uint16 rsvd1:5; // 15:11 60 | }; 61 | 62 | 63 | union ECCTL2_REG { 64 | Uint16 all; 65 | struct ECCTL2_BITS bit; 66 | }; 67 | 68 | 69 | //---------------------------------------------------- 70 | // ECAP interrupt enable register bit definitions */ 71 | struct ECEINT_BITS { // bits description 72 | Uint16 rsvd1:1; // 0 reserved 73 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable 74 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable 75 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable 76 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable 77 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable 78 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable 79 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable 80 | Uint16 rsvd2:8; // 15:8 reserved 81 | }; 82 | 83 | 84 | union ECEINT_REG { 85 | Uint16 all; 86 | struct ECEINT_BITS bit; 87 | }; 88 | 89 | //---------------------------------------------------- 90 | // ECAP interrupt flag register bit definitions */ 91 | struct ECFLG_BITS { // bits description 92 | Uint16 INT:1; // 0 Global Flag 93 | Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag 94 | Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag 95 | Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag 96 | Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag 97 | Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag 98 | Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Flag 99 | Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Flag 100 | Uint16 rsvd2:8; // 15:8 reserved 101 | }; 102 | 103 | 104 | union ECFLG_REG { 105 | Uint16 all; 106 | struct ECFLG_BITS bit; 107 | }; 108 | 109 | 110 | //---------------------------------------------------- 111 | 112 | struct ECAP_REGS { 113 | Uint32 TSCTR; // Time stamp counter 114 | Uint32 CTRPHS; // Counter phase 115 | Uint32 CAP1; // Capture 1 116 | Uint32 CAP2; // Capture 2 117 | Uint32 CAP3; // Capture 3 118 | Uint32 CAP4; // Capture 4 119 | Uint16 rsvd1[8]; // reserved 120 | union ECCTL1_REG ECCTL1; // Capture Control Reg 1 121 | union ECCTL2_REG ECCTL2; // Capture Control Reg 2 122 | union ECEINT_REG ECEINT; // ECAP interrupt enable 123 | union ECFLG_REG ECFLG; // ECAP interrupt flags 124 | union ECFLG_REG ECCLR; // ECAP interrupt clear 125 | union ECEINT_REG ECFRC; // ECAP interrupt force 126 | Uint16 rsvd2[6]; // reserved 127 | }; 128 | 129 | 130 | 131 | 132 | //--------------------------------------------------------------------------- 133 | // GPI/O External References & Function Declarations: 134 | // 135 | extern volatile struct ECAP_REGS ECap1Regs; 136 | extern volatile struct ECAP_REGS ECap2Regs; 137 | extern volatile struct ECAP_REGS ECap3Regs; 138 | extern volatile struct ECAP_REGS ECap4Regs; 139 | 140 | 141 | 142 | #ifdef __cplusplus 143 | } 144 | #endif /* extern "C" */ 145 | 146 | #endif // end of DSP280x_ECAP_H definition 147 | 148 | //=========================================================================== 149 | // End of file. 150 | //=========================================================================== 151 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_EPwm.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/7 $ 2 | // Checkin $Date: September 9, 2005 13:59:40 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_EPwm.h 6 | // 7 | // TITLE: DSP280x Enhanced PWM Module Register Bit Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_EPWM_H 15 | #define DSP280x_EPWM_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //---------------------------------------------------- 23 | // Time base control register bit definitions */ 24 | struct TBCTL_BITS { // bits description 25 | Uint16 CTRMODE:2; // 1:0 Counter Mode 26 | Uint16 PHSEN:1; // 2 Phase load enable 27 | Uint16 PRDLD:1; // 3 Active period load 28 | Uint16 SYNCOSEL:2; // 5:4 Sync output select 29 | Uint16 SWFSYNC:1; // 6 Software force sync pulse 30 | Uint16 HSPCLKDIV:3; // 9:7 High speed time pre-scale 31 | Uint16 CLKDIV:3; // 12:10 Timebase clock pre-scale 32 | Uint16 PHSDIR:1; // 13 Phase Direction 33 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 34 | }; 35 | 36 | union TBCTL_REG { 37 | Uint16 all; 38 | struct TBCTL_BITS bit; 39 | }; 40 | 41 | //---------------------------------------------------- 42 | // Time base status register bit definitions */ 43 | struct TBSTS_BITS { // bits description 44 | Uint16 CTRDIR:1; // 0 Counter direction status 45 | Uint16 SYNCI:1; // 1 External input sync status 46 | Uint16 CTRMAX:1; // 2 Counter max latched status 47 | Uint16 rsvd1:13; // 15:3 reserved 48 | }; 49 | 50 | union TBSTS_REG { 51 | Uint16 all; 52 | struct TBSTS_BITS bit; 53 | }; 54 | 55 | //---------------------------------------------------- 56 | // Compare control register bit definitions */ 57 | struct CMPCTL_BITS { // bits description 58 | Uint16 LOADAMODE:2; // 0:1 Active compare A 59 | Uint16 LOADBMODE:2; // 3:2 Active compare B 60 | Uint16 SHDWAMODE:1; // 4 Compare A block operating mode 61 | Uint16 rsvd1:1; // 5 reserved 62 | Uint16 SHDWBMODE:1; // 6 Compare B block operating mode 63 | Uint16 rsvd2:1; // 7 reserved 64 | Uint16 SHDWAFULL:1; // 8 Compare A Shadow registers full Status 65 | Uint16 SHDWBFULL:1; // 9 Compare B Shadow registers full Status 66 | Uint16 rsvd3:6; // 15:10 reserved 67 | }; 68 | 69 | 70 | union CMPCTL_REG { 71 | Uint16 all; 72 | struct CMPCTL_BITS bit; 73 | }; 74 | 75 | //---------------------------------------------------- 76 | // Action qualifier register bit definitions */ 77 | struct AQCTL_BITS { // bits description 78 | Uint16 ZRO:2; // 1:0 Action Counter = Zero 79 | Uint16 PRD:2; // 3:2 Action Counter = Period 80 | Uint16 CAU:2; // 5:4 Action Counter = Compare A up 81 | Uint16 CAD:2; // 7:6 Action Counter = Compare A down 82 | Uint16 CBU:2; // 9:8 Action Counter = Compare B up 83 | Uint16 CBD:2; // 11:10 Action Counter = Compare B down 84 | Uint16 rsvd:4; // 15:12 reserved 85 | }; 86 | 87 | union AQCTL_REG { 88 | Uint16 all; 89 | struct AQCTL_BITS bit; 90 | }; 91 | 92 | //---------------------------------------------------- 93 | // Action qualifier SW force register bit definitions */ 94 | struct AQSFRC_BITS { // bits description 95 | Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A invoked 96 | Uint16 OTSFA:1; // 2 One-time SW Force A output 97 | Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B invoked 98 | Uint16 OTSFB:1; // 5 One-time SW Force A output 99 | Uint16 RLDCSF:2; // 7:6 Reload from Shadow options 100 | Uint16 rsvd1:8; // 15:8 reserved 101 | }; 102 | 103 | union AQSFRC_REG { 104 | Uint16 all; 105 | struct AQSFRC_BITS bit; 106 | }; 107 | 108 | //---------------------------------------------------- 109 | // Action qualifier continuous SW force register bit definitions */ 110 | struct AQCSFRC_BITS { // bits description 111 | Uint16 CSFA:2; // 1:0 Continuous Software Force on output A 112 | Uint16 CSFB:2; // 3:2 Continuous Software Force on output B 113 | Uint16 rsvd1:12; // 15:4 reserved 114 | }; 115 | 116 | union AQCSFRC_REG { 117 | Uint16 all; 118 | struct AQCSFRC_BITS bit; 119 | }; 120 | 121 | 122 | // As of version 1.1 123 | // Changed the MODE bit-field to OUT_MODE 124 | // Added the bit-field IN_MODE 125 | // This corresponds to changes in silicon as of F280x devices 126 | // Rev A silicon. 127 | //---------------------------------------------------- 128 | // Dead-band generator control register bit definitions 129 | struct DBCTL_BITS { // bits description 130 | Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control 131 | Uint16 POLSEL:2; // 3:2 Polarity Select Control 132 | Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control 133 | Uint16 rsvd1:10; // 15:4 reserved 134 | }; 135 | 136 | union DBCTL_REG { 137 | Uint16 all; 138 | struct DBCTL_BITS bit; 139 | }; 140 | 141 | 142 | //---------------------------------------------------- 143 | // Trip zone select register bit definitions 144 | struct TZSEL_BITS { // bits description 145 | Uint16 CBC1:1; // 0 TZ1 CBC select 146 | Uint16 CBC2:1; // 1 TZ2 CBC select 147 | Uint16 CBC3:1; // 2 TZ3 CBC select 148 | Uint16 CBC4:1; // 3 TZ4 CBC select 149 | Uint16 CBC5:1; // 4 TZ5 CBC select 150 | Uint16 CBC6:1; // 5 TZ6 CBC select 151 | Uint16 rsvd1:2; // 7:6 reserved 152 | Uint16 OSHT1:1; // 8 One-shot TZ1 select 153 | Uint16 OSHT2:1; // 9 One-shot TZ2 select 154 | Uint16 OSHT3:1; // 10 One-shot TZ3 select 155 | Uint16 OSHT4:1; // 11 One-shot TZ4 select 156 | Uint16 OSHT5:1; // 12 One-shot TZ5 select 157 | Uint16 OSHT6:1; // 13 One-shot TZ6 select 158 | Uint16 rsvd2:2; // 15:14 reserved 159 | }; 160 | 161 | union TZSEL_REG { 162 | Uint16 all; 163 | struct TZSEL_BITS bit; 164 | }; 165 | 166 | 167 | //---------------------------------------------------- 168 | // Trip zone control register bit definitions */ 169 | struct TZCTL_BITS { // bits description 170 | Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA 171 | Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB 172 | Uint16 rsvd:12; // 15:4 reserved 173 | }; 174 | 175 | union TZCTL_REG { 176 | Uint16 all; 177 | struct TZCTL_BITS bit; 178 | }; 179 | 180 | 181 | //---------------------------------------------------- 182 | // Trip zone control register bit definitions */ 183 | struct TZEINT_BITS { // bits description 184 | Uint16 rsvd1:1; // 0 reserved 185 | Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable 186 | Uint16 OST:1; // 2 Trip Zones One Shot Int Enable 187 | Uint16 rsvd2:13; // 15:3 reserved 188 | }; 189 | 190 | 191 | union TZEINT_REG { 192 | Uint16 all; 193 | struct TZEINT_BITS bit; 194 | }; 195 | 196 | 197 | //---------------------------------------------------- 198 | // Trip zone flag register bit definitions */ 199 | struct TZFLG_BITS { // bits description 200 | Uint16 INT:1; // 0 Global status 201 | Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int 202 | Uint16 OST:1; // 2 Trip Zones One Shot Int 203 | Uint16 rsvd2:13; // 15:3 reserved 204 | }; 205 | 206 | union TZFLG_REG { 207 | Uint16 all; 208 | struct TZFLG_BITS bit; 209 | }; 210 | 211 | //---------------------------------------------------- 212 | // Trip zone flag clear register bit definitions */ 213 | struct TZCLR_BITS { // bits description 214 | Uint16 INT:1; // 0 Global status 215 | Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int 216 | Uint16 OST:1; // 2 Trip Zones One Shot Int 217 | Uint16 rsvd2:13; // 15:3 reserved 218 | }; 219 | 220 | union TZCLR_REG { 221 | Uint16 all; 222 | struct TZCLR_BITS bit; 223 | }; 224 | 225 | //---------------------------------------------------- 226 | // Trip zone flag force register bit definitions */ 227 | struct TZFRC_BITS { // bits description 228 | Uint16 rsvd1:1; // 0 reserved 229 | Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int 230 | Uint16 OST:1; // 2 Trip Zones One Shot Int 231 | Uint16 rsvd2:13; // 15:3 reserved 232 | }; 233 | 234 | union TZFRC_REG { 235 | Uint16 all; 236 | struct TZFRC_BITS bit; 237 | }; 238 | 239 | //---------------------------------------------------- 240 | // Event trigger select register bit definitions */ 241 | struct ETSEL_BITS { // bits description 242 | Uint16 INTSEL:3; // 2:0 EPWMxINTn Select 243 | Uint16 INTEN:1; // 3 EPWMxINTn Enable 244 | Uint16 rsvd1:4; // 7:4 reserved 245 | Uint16 SOCASEL:3; // 10:8 Start of conversion A Select 246 | Uint16 SOCAEN:1; // 11 Start of conversion A Enable 247 | Uint16 SOCBSEL:3; // 14:12 Start of conversion B Select 248 | Uint16 SOCBEN:1; // 15 Start of conversion B Enable 249 | }; 250 | 251 | union ETSEL_REG { 252 | Uint16 all; 253 | struct ETSEL_BITS bit; 254 | }; 255 | 256 | 257 | //---------------------------------------------------- 258 | // Event trigger pre-scale register bit definitions */ 259 | struct ETPS_BITS { // bits description 260 | Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select 261 | Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register 262 | Uint16 rsvd1:4; // 7:4 reserved 263 | Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select 264 | Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register 265 | Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select 266 | Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter Register 267 | }; 268 | 269 | union ETPS_REG { 270 | Uint16 all; 271 | struct ETPS_BITS bit; 272 | }; 273 | 274 | //---------------------------------------------------- 275 | // Event trigger Flag register bit definitions */ 276 | struct ETFLG_BITS { // bits description 277 | Uint16 INT:1; // 0 EPWMxINTn Flag 278 | Uint16 rsvd1:1; // 1 reserved 279 | Uint16 SOCA:1; // 2 EPWMxSOCA Flag 280 | Uint16 SOCB:1; // 3 EPWMxSOCB Flag 281 | Uint16 rsvd2:12; // 15:4 reserved 282 | }; 283 | 284 | union ETFLG_REG { 285 | Uint16 all; 286 | struct ETFLG_BITS bit; 287 | }; 288 | 289 | 290 | //---------------------------------------------------- 291 | // Event trigger Clear register bit definitions */ 292 | struct ETCLR_BITS { // bits description 293 | Uint16 INT:1; // 0 EPWMxINTn Clear 294 | Uint16 rsvd1:1; // 1 reserved 295 | Uint16 SOCA:1; // 2 EPWMxSOCA Clear 296 | Uint16 SOCB:1; // 3 EPWMxSOCB Clear 297 | Uint16 rsvd2:12; // 15:4 reserved 298 | }; 299 | 300 | union ETCLR_REG { 301 | Uint16 all; 302 | struct ETCLR_BITS bit; 303 | }; 304 | 305 | //---------------------------------------------------- 306 | // Event trigger Force register bit definitions */ 307 | struct ETFRC_BITS { // bits description 308 | Uint16 INT:1; // 0 EPWMxINTn Force 309 | Uint16 rsvd1:1; // 1 reserved 310 | Uint16 SOCA:1; // 2 EPWMxSOCA Force 311 | Uint16 SOCB:1; // 3 EPWMxSOCB Force 312 | Uint16 rsvd2:12; // 15:4 reserved 313 | }; 314 | 315 | union ETFRC_REG { 316 | Uint16 all; 317 | struct ETFRC_BITS bit; 318 | }; 319 | //---------------------------------------------------- 320 | // PWM chopper control register bit definitions */ 321 | struct PCCTL_BITS { // bits description 322 | Uint16 CHPEN:1; // 0 PWM chopping enable 323 | Uint16 OSHTWTH:4; // 4:1 One-shot pulse width 324 | Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency 325 | Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle 326 | Uint16 rsvd1:5; // 15:11 reserved 327 | }; 328 | 329 | 330 | union PCCTL_REG { 331 | Uint16 all; 332 | struct PCCTL_BITS bit; 333 | }; 334 | 335 | struct HRCNFG_BITS { // bits description 336 | Uint16 EDGMODE:2; // 1:0 Edge Mode select Bits 337 | Uint16 CTLMODE:1; // 2 Control mode Select Bit 338 | Uint16 HRLOAD:1; // 3 Shadow mode Select Bit 339 | Uint16 rsvd1:12; // 15:4 reserved 340 | }; 341 | 342 | union HRCNFG_REG { 343 | Uint16 all; 344 | struct HRCNFG_BITS bit; 345 | }; 346 | 347 | 348 | struct TBPHS_HRPWM_REG { // bits description 349 | Uint16 TBPHSHR; // 15:0 Extension register for HRPWM Phase (8 bits) 350 | Uint16 TBPHS; // 31:16 Phase offset register 351 | }; 352 | 353 | union TBPHS_HRPWM_GROUP { 354 | Uint32 all; 355 | struct TBPHS_HRPWM_REG half; 356 | }; 357 | 358 | struct CMPA_HRPWM_REG { // bits description 359 | Uint16 CMPAHR; // 15:0 Extension register for HRPWM compare (8 bits) 360 | Uint16 CMPA; // 31:16 Compare A reg 361 | }; 362 | 363 | union CMPA_HRPWM_GROUP { 364 | Uint32 all; 365 | struct CMPA_HRPWM_REG half; 366 | }; 367 | 368 | 369 | struct EPWM_REGS { 370 | union TBCTL_REG TBCTL; // 371 | union TBSTS_REG TBSTS; // 372 | union TBPHS_HRPWM_GROUP TBPHS; // Union of TBPHS:TBPHSHR 373 | Uint16 TBCTR; // Counter 374 | Uint16 TBPRD; // Period register set 375 | Uint16 rsvd1; // 376 | union CMPCTL_REG CMPCTL; // Compare control 377 | union CMPA_HRPWM_GROUP CMPA; // Union of CMPA:CMPAHR 378 | Uint16 CMPB; // Compare B reg 379 | union AQCTL_REG AQCTLA; // Action qual output A 380 | union AQCTL_REG AQCTLB; // Action qual output B 381 | union AQSFRC_REG AQSFRC; // Action qual SW force 382 | union AQCSFRC_REG AQCSFRC; // Action qualifier continuous SW force 383 | union DBCTL_REG DBCTL; // Dead-band control 384 | Uint16 DBRED; // Dead-band rising edge delay 385 | Uint16 DBFED; // Dead-band falling edge delay 386 | union TZSEL_REG TZSEL; // Trip zone select 387 | Uint16 rsvd2; 388 | union TZCTL_REG TZCTL; // Trip zone control 389 | union TZEINT_REG TZEINT; // Trip zone interrupt enable 390 | union TZFLG_REG TZFLG; // Trip zone interrupt flags 391 | union TZCLR_REG TZCLR; // Trip zone clear 392 | union TZFRC_REG TZFRC; // Trip zone force interrupt 393 | union ETSEL_REG ETSEL; // Event trigger selection 394 | union ETPS_REG ETPS; // Event trigger pre-scaler 395 | union ETFLG_REG ETFLG; // Event trigger flags 396 | union ETCLR_REG ETCLR; // Event trigger clear 397 | union ETFRC_REG ETFRC; // Event trigger force 398 | union PCCTL_REG PCCTL; // PWM chopper control 399 | Uint16 rsvd3; // 400 | union HRCNFG_REG HRCNFG; // HRPWM Config Reg 401 | }; 402 | 403 | 404 | 405 | //--------------------------------------------------------------------------- 406 | // External References & Function Declarations: 407 | // 408 | extern volatile struct EPWM_REGS EPwm1Regs; 409 | extern volatile struct EPWM_REGS EPwm2Regs; 410 | extern volatile struct EPWM_REGS EPwm3Regs; 411 | extern volatile struct EPWM_REGS EPwm4Regs; 412 | extern volatile struct EPWM_REGS EPwm5Regs; 413 | extern volatile struct EPWM_REGS EPwm6Regs; 414 | 415 | #ifdef __cplusplus 416 | } 417 | #endif /* extern "C" */ 418 | 419 | #endif // end of DSP280x_EPWM_H definition 420 | 421 | //=========================================================================== 422 | // End of file. 423 | //=========================================================================== 424 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_EPwm_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: April 8, 2005 15:29:44 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280X_EPwm_defines.h 6 | // 7 | // TITLE: #defines used in ePWM examples examples 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280X_EPWM_DEFINES_H 15 | #define DSP280X_EPWM_DEFINES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | // TBCTL (Time-Base Control) 23 | //========================== 24 | // CTRMODE bits 25 | #define TB_COUNT_UP 0x0 26 | #define TB_COUNT_DOWN 0x1 27 | #define TB_COUNT_UPDOWN 0x2 28 | #define TB_FREEZE 0x3 29 | // PHSEN bit 30 | #define TB_DISABLE 0x0 31 | #define TB_ENABLE 0x1 32 | // PRDLD bit 33 | #define TB_SHADOW 0x0 34 | #define TB_IMMEDIATE 0x1 35 | // SYNCOSEL bits 36 | #define TB_SYNC_IN 0x0 37 | #define TB_CTR_ZERO 0x1 38 | #define TB_CTR_CMPB 0x2 39 | #define TB_SYNC_DISABLE 0x3 40 | // HSPCLKDIV and CLKDIV bits 41 | #define TB_DIV1 0x0 42 | #define TB_DIV2 0x1 43 | #define TB_DIV4 0x2 44 | // PHSDIR bit 45 | #define TB_DOWN 0x0 46 | #define TB_UP 0x1 47 | 48 | // CMPCTL (Compare Control) 49 | //========================== 50 | // LOADAMODE and LOADBMODE bits 51 | #define CC_CTR_ZERO 0x0 52 | #define CC_CTR_PRD 0x1 53 | #define CC_CTR_ZERO_PRD 0x2 54 | #define CC_LD_DISABLE 0x3 55 | // SHDWAMODE and SHDWBMODE bits 56 | #define CC_SHADOW 0x0 57 | #define CC_IMMEDIATE 0x1 58 | 59 | // AQCTLA and AQCTLB (Action Qualifier Control) 60 | //============================================= 61 | // ZRO, PRD, CAU, CAD, CBU, CBD bits 62 | #define AQ_NO_ACTION 0x0 63 | #define AQ_CLEAR 0x1 64 | #define AQ_SET 0x2 65 | #define AQ_TOGGLE 0x3 66 | 67 | // DBCTL (Dead-Band Control) 68 | //========================== 69 | // OUT MODE bits 70 | #define DB_DISABLE 0x0 71 | #define DBA_ENABLE 0x1 72 | #define DBB_ENABLE 0x2 73 | #define DB_FULL_ENABLE 0x3 74 | // POLSEL bits 75 | #define DB_ACTV_HI 0x0 76 | #define DB_ACTV_LOC 0x1 77 | #define DB_ACTV_HIC 0x2 78 | #define DB_ACTV_LO 0x3 79 | // IN MODE 80 | #define DBA_ALL 0x0 81 | #define DBB_RED_DBA_FED 0x1 82 | #define DBA_RED_DBB_FED 0x2 83 | #define DBB_ALL 0x3 84 | 85 | // CHPCTL (chopper control) 86 | //========================== 87 | // CHPEN bit 88 | #define CHP_DISABLE 0x0 89 | #define CHP_ENABLE 0x1 90 | // CHPFREQ bits 91 | #define CHP_DIV1 0x0 92 | #define CHP_DIV2 0x1 93 | #define CHP_DIV3 0x2 94 | #define CHP_DIV4 0x3 95 | #define CHP_DIV5 0x4 96 | #define CHP_DIV6 0x5 97 | #define CHP_DIV7 0x6 98 | #define CHP_DIV8 0x7 99 | // CHPDUTY bits 100 | #define CHP1_8TH 0x0 101 | #define CHP2_8TH 0x1 102 | #define CHP3_8TH 0x2 103 | #define CHP4_8TH 0x3 104 | #define CHP5_8TH 0x4 105 | #define CHP6_8TH 0x5 106 | #define CHP7_8TH 0x6 107 | 108 | // TZSEL (Trip Zone Select) 109 | //========================== 110 | // CBCn and OSHTn bits 111 | #define TZ_DISABLE 0x0 112 | #define TZ_ENABLE 0x1 113 | 114 | // TZCTL (Trip Zone Control) 115 | //========================== 116 | // TZA and TZB bits 117 | #define TZ_HIZ 0x0 118 | #define TZ_FORCE_HI 0x1 119 | #define TZ_FORCE_LO 0x2 120 | #define TZ_NO_CHANGE 0x3 121 | 122 | // ETSEL (Event Trigger Select) 123 | //============================= 124 | #define ET_CTR_ZERO 0x1 125 | #define ET_CTR_PRD 0x2 126 | #define ET_CTRU_CMPA 0x4 127 | #define ET_CTRD_CMPA 0x5 128 | #define ET_CTRU_CMPB 0x6 129 | #define ET_CTRD_CMPB 0x7 130 | 131 | // ETPS (Event Trigger Pre-scale) 132 | //=============================== 133 | // INTPRD, SOCAPRD, SOCBPRD bits 134 | #define ET_DISABLE 0x0 135 | #define ET_1ST 0x1 136 | #define ET_2ND 0x2 137 | #define ET_3RD 0x3 138 | 139 | 140 | //-------------------------------- 141 | // HRPWM (High Resolution PWM) 142 | //================================ 143 | // HRCNFG 144 | #define HR_Disable 0x0 145 | #define HR_REP 0x1 146 | #define HR_FEP 0x2 147 | #define HR_BEP 0x3 148 | 149 | #define HR_CMP 0x0 150 | #define HR_PHS 0x1 151 | 152 | #define HR_CTR_ZERO 0x0 153 | #define HR_CTR_PRD 0x1 154 | 155 | 156 | #ifdef __cplusplus 157 | } 158 | #endif /* extern "C" */ 159 | 160 | #endif // - end of DSP280X_EPWM_DEFINES_H 161 | 162 | //=========================================================================== 163 | // End of file. 164 | //=========================================================================== 165 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_EQep.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: April 8, 2005 12:39:38 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_EQep.h 6 | // 7 | // TITLE: DSP280x Enhanced Quadrature Encoder Pulse Module 8 | // Register Bit Definitions. 9 | // 10 | //########################################################################### 11 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 12 | // $Release Date: July 27, 2009 $ 13 | //########################################################################### 14 | 15 | #ifndef DSP280x_EQEP_H 16 | #define DSP280x_EQEP_H 17 | 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | //---------------------------------------------------- 24 | // Capture decoder control register bit definitions */ 25 | struct QDECCTL_BITS { // bits description 26 | Uint16 rsvd1:5; // 4:0 reserved 27 | Uint16 QSP:1; // 5 QEPS input polarity 28 | Uint16 QIP:1; // 6 QEPI input polarity 29 | Uint16 QBP:1; // 7 QEPB input polarity 30 | Uint16 QAP:1; // 8 QEPA input polarity 31 | Uint16 IGATE:1; // 9 Index pulse gating option 32 | Uint16 SWAP:1; // 10 CLK/DIR signal source for Position Counter 33 | Uint16 XCR:1; // 11 External clock rate 34 | Uint16 SPSEL:1; // 12 Sync output pin select 35 | Uint16 SOEN:1; // 13 Enable position compare sync 36 | Uint16 QSRC:2; // 15:14 Position counter source 37 | }; 38 | 39 | union QDECCTL_REG { 40 | Uint16 all; 41 | struct QDECCTL_BITS bit; 42 | }; 43 | 44 | 45 | //---------------------------------------------------- 46 | // QEP control register bit definitions */ 47 | struct QEPCTL_BITS { // bits description 48 | Uint16 WDE:1; // 0 QEP watchdog enable 49 | Uint16 UTE:1; // 1 QEP unit timer enable 50 | Uint16 QCLM:1; // 2 QEP capture latch mode 51 | Uint16 QPEN:1; // 3 Quadrature position counter enable 52 | Uint16 IEL:2; // 5:4 Index event latch 53 | Uint16 SEL:1; // 6 Strobe event latch 54 | Uint16 SWI:1; // 7 Software init position counter 55 | Uint16 IEI:2; // 9:8 Index event init of position count 56 | Uint16 SEI:2; // 11:10 Strobe event init 57 | Uint16 PCRM:2; // 13:12 Position counter reset 58 | Uint16 FREE_SOFT:2; // 15:14 Emulation mode 59 | }; 60 | 61 | union QEPCTL_REG { 62 | Uint16 all; 63 | struct QEPCTL_BITS bit; 64 | }; 65 | 66 | 67 | //---------------------------------------------------- 68 | // Quadrature capture control register bit definitions */ 69 | struct QCAPCTL_BITS { // bits description 70 | Uint16 UPPS:4; // 3:0 Unit position pre-scale 71 | Uint16 CCPS:3; // 6:4 QEP capture timer pre-scale 72 | Uint16 rsvd1:8; // 14:7 reserved 73 | Uint16 CEN:1; // 15 Enable QEP capture 74 | }; 75 | 76 | 77 | union QCAPCTL_REG { 78 | Uint16 all; 79 | struct QCAPCTL_BITS bit; 80 | }; 81 | 82 | 83 | 84 | //---------------------------------------------------- 85 | // Position compare control register bit definitions */ 86 | struct QPOSCTL_BITS { // bits description 87 | Uint16 PCSPW:12; // 11:0 Position compare sync pulse width 88 | Uint16 PCE:1; // 12 Position compare enable/disable 89 | Uint16 PCPOL:1; // 13 Polarity of sync output 90 | Uint16 PCLOAD:1; // 14 Position compare of shadow load 91 | Uint16 PCSHDW:1; // 15 Position compare shadow enable 92 | }; 93 | 94 | union QPOSCTL_REG { 95 | Uint16 all; 96 | struct QPOSCTL_BITS bit; 97 | }; 98 | 99 | //---------------------------------------------------- 100 | // QEP interrupt control register bit definitions */ 101 | struct QEINT_BITS { // bits description 102 | Uint16 rsvd1:1; // 0 reserved 103 | Uint16 PCE:1; // 1 Position counter error 104 | Uint16 QPE:1; // 2 Quadrature phase error 105 | Uint16 QDC:1; // 3 Quadrature dir change 106 | Uint16 WTO:1; // 4 Watchdog timeout 107 | Uint16 PCU:1; // 5 Position counter underflow 108 | Uint16 PCO:1; // 6 Position counter overflow 109 | Uint16 PCR:1; // 7 Position compare ready 110 | Uint16 PCM:1; // 8 Position compare match 111 | Uint16 SEL:1; // 9 Strobe event latch 112 | Uint16 IEL:1; // 10 Event latch 113 | Uint16 UTO:1; // 11 Unit timeout 114 | Uint16 rsvd2:4; // 15:12 reserved 115 | }; 116 | 117 | 118 | union QEINT_REG { 119 | Uint16 all; 120 | struct QEINT_BITS bit; 121 | }; 122 | 123 | 124 | //---------------------------------------------------- 125 | // QEP interrupt status register bit definitions */ 126 | struct QFLG_BITS { // bits description 127 | Uint16 INT:1; // 0 Global interrupt 128 | Uint16 PCE:1; // 1 Position counter error 129 | Uint16 PHE:1; // 2 Quadrature phase error 130 | Uint16 QDC:1; // 3 Quadrature dir change 131 | Uint16 WTO:1; // 4 Watchdog timeout 132 | Uint16 PCU:1; // 5 Position counter underflow 133 | Uint16 PCO:1; // 6 Position counter overflow 134 | Uint16 PCR:1; // 7 Position compare ready 135 | Uint16 PCM:1; // 8 Position compare match 136 | Uint16 SEL:1; // 9 Strobe event latch 137 | Uint16 IEL:1; // 10 Event latch 138 | Uint16 UTO:1; // 11 Unit timeout 139 | Uint16 rsvd2:4; // 15:12 reserved 140 | }; 141 | 142 | 143 | union QFLG_REG { 144 | Uint16 all; 145 | struct QFLG_BITS bit; 146 | }; 147 | 148 | //---------------------------------------------------- 149 | // QEP interrupt force register bit definitions */ 150 | struct QFRC_BITS { // bits description 151 | Uint16 reserved:1; // 0 Reserved 152 | Uint16 PCE:1; // 1 Position counter error 153 | Uint16 PHE:1; // 2 Quadrature phase error 154 | Uint16 QDC:1; // 3 Quadrature dir change 155 | Uint16 WTO:1; // 4 Watchdog timeout 156 | Uint16 PCU:1; // 5 Position counter underflow 157 | Uint16 PCO:1; // 6 Position counter overflow 158 | Uint16 PCR:1; // 7 Position compare ready 159 | Uint16 PCM:1; // 8 Position compare match 160 | Uint16 SEL:1; // 9 Strobe event latch 161 | Uint16 IEL:1; // 10 Event latch 162 | Uint16 UTO:1; // 11 Unit timeout 163 | Uint16 rsvd2:4; // 15:12 reserved 164 | }; 165 | 166 | 167 | union QFRC_REG { 168 | Uint16 all; 169 | struct QFRC_BITS bit; 170 | }; 171 | 172 | // V1.1 Added UPEVNT (bit 7) This reflects changes 173 | // made as of F280x Rev A devices 174 | //---------------------------------------------------- 175 | // QEP status register bit definitions */ 176 | struct QEPSTS_BITS { // bits description 177 | Uint16 PCEF:1; // 0 Position counter error 178 | Uint16 FIMF:1; // 1 First index marker 179 | Uint16 CDEF:1; // 2 Capture direction error 180 | Uint16 COEF:1; // 3 Capture overflow error 181 | Uint16 QDLF:1; // 4 QEP direction latch 182 | Uint16 QDF:1; // 5 Quadrature direction 183 | Uint16 FIDF:1; // 6 Direction on first index marker 184 | Uint16 UPEVNT:1; // 7 Unit position event flag 185 | Uint16 rsvd1:8; // 15:8 reserved 186 | }; 187 | 188 | union QEPSTS_REG { 189 | Uint16 all; 190 | struct QEPSTS_BITS bit; 191 | }; 192 | 193 | //---------------------------------------------------- 194 | 195 | struct EQEP_REGS { 196 | Uint32 QPOSCNT; // Position counter 197 | Uint32 QPOSINIT; // Position counter init 198 | Uint32 QPOSMAX; // Maximum position count 199 | Uint32 QPOSCMP; // Position compare 200 | Uint32 QPOSILAT; // Index position latch 201 | Uint32 QPOSSLAT; // Strobe position latch 202 | Uint32 QPOSLAT; // Position latch 203 | Uint32 QUTMR; // Unit timer 204 | Uint32 QUPRD; // Unit period 205 | Uint16 QWDTMR; // QEP watchdog timer 206 | Uint16 QWDPRD; // QEP watchdog period 207 | union QDECCTL_REG QDECCTL; // Quadrature decoder control 208 | union QEPCTL_REG QEPCTL; // QEP control 209 | union QCAPCTL_REG QCAPCTL; // Quadrature capture control 210 | union QPOSCTL_REG QPOSCTL; // Position compare control 211 | union QEINT_REG QEINT; // QEP interrupt control 212 | union QFLG_REG QFLG; // QEP interrupt flag 213 | union QFLG_REG QCLR; // QEP interrupt clear 214 | union QFRC_REG QFRC; // QEP interrupt force 215 | union QEPSTS_REG QEPSTS; // QEP status 216 | Uint16 QCTMR; // QEP capture timer 217 | Uint16 QCPRD; // QEP capture period 218 | Uint16 QCTMRLAT; // QEP capture latch 219 | Uint16 QCPRDLAT; // QEP capture period latch 220 | Uint16 rsvd1[30]; // reserved 221 | }; 222 | 223 | 224 | 225 | 226 | //--------------------------------------------------------------------------- 227 | // GPI/O External References & Function Declarations: 228 | // 229 | extern volatile struct EQEP_REGS EQep1Regs; 230 | extern volatile struct EQEP_REGS EQep2Regs; 231 | 232 | 233 | 234 | #ifdef __cplusplus 235 | } 236 | #endif /* extern "C" */ 237 | 238 | #endif // end of DSP280x_EQEP_H definition 239 | 240 | //=========================================================================== 241 | // End of file. 242 | //=========================================================================== 243 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Examples.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/8 $ 2 | // Checkin $Date: April 4, 2007 17:18:30 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Examples.h 6 | // 7 | // TITLE: DSP280x Device Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280X_EXAMPLES_H 15 | #define DSP280X_EXAMPLES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | /*----------------------------------------------------------------------------- 24 | Specify the PLL control register (PLLCR) and clock in divide (CLKINDIV) value. 25 | 26 | if CLKINDIV = 0: SYSCLKOUT = (OSCCLK * PLLCR)/2 27 | if CLKINDIV = 1: SYSCLKOUT = (OSCCLK * PLLCR) 28 | -----------------------------------------------------------------------------*/ 29 | #define DSP28_CLKINDIV 0 // Enable /2 for SYSCLKOUT 30 | //#define DSP28_CLKINDIV 1 // Disable /2 for SYSCKOUT 31 | 32 | #define DSP28_PLLCR 10 33 | //#define DSP28_PLLCR 9 34 | //#define DSP28_PLLCR 8 35 | //#define DSP28_PLLCR 7 36 | //#define DSP28_PLLCR 6 // Uncomment for 60 MHz devices [60 MHz = (20MHz * 6)/2] 37 | //#define DSP28_PLLCR 5 38 | //#define DSP28_PLLCR 4 39 | //#define DSP28_PLLCR 3 40 | //#define DSP28_PLLCR 2 41 | //#define DSP28_PLLCR 1 42 | //#define DSP28_PLLCR 0 // PLL is bypassed in this mode 43 | //---------------------------------------------------------------------------- 44 | 45 | 46 | /*----------------------------------------------------------------------------- 47 | Specify the clock rate of the CPU (SYSCLKOUT) in nS. 48 | 49 | Take into account the input clock frequency and the PLL multiplier 50 | selected in step 1. 51 | 52 | Use one of the values provided, or define your own. 53 | The trailing L is required tells the compiler to treat 54 | the number as a 64-bit value. 55 | 56 | Only one statement should be uncommented. 57 | 58 | Example: CLKIN is a 20MHz crystal. 59 | 60 | In step 1 the user specified PLLCR = 0xA for a 61 | 100Mhz CPU clock (SYSCLKOUT = 100MHz). 62 | 63 | In this case, the CPU_RATE will be 10.000L 64 | Uncomment the line: #define CPU_RATE 10.000L 65 | 66 | For a 60 MHz CPU clock (SYSCLKOUT = 60MHz), user 67 | specified PLLCR = 0x06 in step 1. 68 | 69 | In this case, the CPU_RATE will be 16.667L 70 | Uncomment the line: #define CPU_RATE 16.667L 71 | -----------------------------------------------------------------------------*/ 72 | 73 | #define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 74 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 75 | //#define CPU_RATE 16.667L // for a 60MHz CPU clock speed (SYSCLKOUT) 76 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 77 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 78 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 79 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 80 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 81 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 82 | 83 | //---------------------------------------------------------------------------- 84 | 85 | /*----------------------------------------------------------------------------- 86 | Specify the SYSCLKOUT max frequency for examples - either 60 MHz 87 | (for 60 MHz devices only) or 100 MHz (for all other devices - this is 88 | the default SYSCLKOUT frequency for all examples). 89 | 90 | Doing so will allow the debugger to compile Example code which is dependent 91 | upon CPU frequency for that frequency. 92 | 93 | Example: CLKIN is a 20MHz crystal. 94 | In step 1 the user specified PLLCR = 0xA for a 100 MHz 95 | CPU clock (SYSCLKOUT = 100MHz). 96 | 97 | Then #define CPU_FRQ_100MHZ is set as 1 (default) and 98 | #define CPU_FRQ_60MHZ is set as 0 (default). 99 | 100 | If PLLCR = 0x06 in step 1, then: 101 | #define CPU_FRQ_100MHZ is set as 0 and 102 | #define CPU_FRQ_60MHZ is set as 1. 103 | -----------------------------------------------------------------------------*/ 104 | 105 | #define CPU_FRQ_100MHZ 1 // 100 Mhz CPU Freq - default, 1 for 100 MHz devices 106 | #define CPU_FRQ_60MHZ 0 // 60 MHz CPU Freq - 1 for 60 MHz devices 107 | 108 | //--------------------------------------------------------------------------- 109 | // Include Example Header Files: 110 | // 111 | 112 | #include "DSP280x_GlobalPrototypes.h" // Prototypes for global functions within the 113 | // .c files. 114 | 115 | #include "DSP280x_ePwm_defines.h" // Macros used for PWM examples. 116 | #include "DSP280x_I2C_defines.h" // Macros used for I2C examples. 117 | 118 | #define PARTNO_28016 0x14 119 | #define PARTNO_28015 0x1C 120 | #define PARTNO_2809 0xFE 121 | #define PARTNO_2808 0x3C 122 | #define PARTNO_2806 0x34 123 | #define PARTNO_2802 0x24 124 | #define PARTNO_2801 0x2C 125 | 126 | // Include files not used with DSP/BIOS 127 | #ifndef DSP28_BIOS 128 | #include "DSP280x_DefaultISR.h" 129 | #endif 130 | 131 | 132 | // DO NOT MODIFY THIS LINE. 133 | #define DELAY_US(A) DSP28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) 134 | 135 | 136 | #ifdef __cplusplus 137 | } 138 | #endif /* extern "C" */ 139 | 140 | #endif // end of DSP280x_EXAMPLES_H definition 141 | 142 | 143 | //=========================================================================== 144 | // End of file. 145 | //=========================================================================== 146 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_GlobalPrototypes.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/7 $ 2 | // Checkin $Date: April 5, 2007 15:14:19 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_GlobalPrototypes.h 6 | // 7 | // TITLE: Global prototypes for DSP280x Examples 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280X_GLOBALPROTOTYPES_H 15 | #define DSP280X_GLOBALPROTOTYPES_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | /*---- shared global function prototypes -----------------------------------*/ 23 | extern void InitAdc(void); 24 | extern void InitPeripherals(void); 25 | #if DSP28_ECANA 26 | extern void InitECan(void); 27 | extern void InitECana(void); 28 | extern void InitECanGpio(void); 29 | extern void InitECanaGpio(void); 30 | #endif // endif DSP28_ECANA 31 | #if DSP28_ECANB 32 | extern void InitECanb(void); 33 | extern void InitECanbGpio(void); 34 | #endif // endif DSP28_ECANB 35 | extern void InitECap(void); 36 | extern void InitECapGpio(void); 37 | extern void InitECap1Gpio(void); 38 | extern void InitECap2Gpio(void); 39 | #if DSP28_ECAP3 40 | extern void InitECap3Gpio(void); 41 | #endif // endif DSP28_ECAP3 42 | #if DSP28_ECAP4 43 | extern void InitECap4Gpio(void); 44 | #endif // endif DSP28_ECAP4 45 | extern void InitEPwm(void); 46 | extern void InitEPwmGpio(void); 47 | extern void InitEPwm1Gpio(void); 48 | extern void InitEPwm2Gpio(void); 49 | extern void InitEPwm3Gpio(void); 50 | #if DSP28_EPWM4 51 | extern void InitEPwm4Gpio(void); 52 | #endif // endif DSP28_EPWM4 53 | #if DSP28_EPWM5 54 | extern void InitEPwm5Gpio(void); 55 | #endif // endif DSP28_EPWM5 56 | #if DSP28_EPWM6 57 | extern void InitEPwm6Gpio(void); 58 | #endif // endif DSP28_EPWM6 59 | #if DSP28_EQEP1 60 | extern void InitEQep(void); 61 | extern void InitEQepGpio(void); 62 | extern void InitEQep1Gpio(void); 63 | #endif // if DSP28_EQEP1 64 | #if DSP28_EQEP2 65 | extern void InitEQep2Gpio(void); 66 | #endif // endif DSP28_EQEP2 67 | extern void InitGpio(void); 68 | extern void InitI2CGpio(void); 69 | extern void InitPieCtrl(void); 70 | extern void InitPieVectTable(void); 71 | extern void InitSci(void); 72 | extern void InitSciGpio(void); 73 | extern void InitSciaGpio(void); 74 | #if DSP28_SCIB 75 | extern void InitScibGpio(void); 76 | #endif // endif DSP28_SCIB 77 | extern void InitSpi(void); 78 | extern void InitSpiGpio(void); 79 | extern void InitSpiaGpio(void); 80 | #if DSP28_SPIB 81 | extern void InitSpibGpio(void); 82 | #endif // endif DSP28_SPIB 83 | #if DSP28_SPIC 84 | extern void InitSpicGpio(void); 85 | #endif // endif DSP28_SPIC 86 | #if DSP28_SPID 87 | extern void InitSpidGpio(void); 88 | #endif // endif DSP28_SPID 89 | extern void InitSysCtrl(void); 90 | extern void InitTzGpio(void); 91 | extern void InitXIntrupt(void); 92 | extern void InitPll(Uint16 pllcr, Uint16 clkindiv); 93 | extern void InitPeripheralClocks(void); 94 | extern void EnableInterrupts(void); 95 | extern void DSP28x_usDelay(Uint32 Count); 96 | #define KickDog ServiceDog // For compatiblity with previous versions 97 | extern void ServiceDog(void); 98 | extern void DisableDog(void); 99 | extern Uint16 CsmUnlock(void); 100 | 101 | // DSP28_DBGIER.asm 102 | extern void SetDBGIER(Uint16 dbgier); 103 | 104 | 105 | 106 | 107 | // CAUTION 108 | // This function MUST be executed out of RAM. Executing it 109 | // out of OTP/Flash will yield unpredictable results 110 | extern void InitFlash(void); 111 | 112 | 113 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); 114 | 115 | 116 | //--------------------------------------------------------------------------- 117 | // External symbols created by the linker cmd file 118 | // DSP28 examples will use these to relocate code from one LOAD location 119 | // in either Flash or XINTF to a different RUN location in internal 120 | // RAM 121 | extern Uint16 RamfuncsLoadStart; 122 | extern Uint16 RamfuncsLoadEnd; 123 | extern Uint16 RamfuncsRunStart; 124 | 125 | #ifdef __cplusplus 126 | } 127 | #endif /* extern "C" */ 128 | 129 | #endif // - end of DSP280X_GLOBALPROTOTYPES_H 130 | 131 | //=========================================================================== 132 | // End of file. 133 | //=========================================================================== 134 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Gpio.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 9, 2009 10:16:33 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Gpio.h 6 | // 7 | // TITLE: DSP280x General Purpose I/O Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_GPIO_H 15 | #define DSP280x_GPIO_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //---------------------------------------------------- 23 | // GPIO A control register bit definitions */ 24 | struct GPACTRL_BITS { // bits description 25 | Uint16 QUALPRD0:8; // 7:0 Qual period 26 | Uint16 QUALPRD1:8; // 15:8 Qual period 27 | Uint16 QUALPRD2:8; // 23:16 Qual period 28 | Uint16 QUALPRD3:8; // 31:24 Qual period 29 | }; 30 | 31 | union GPACTRL_REG { 32 | Uint32 all; 33 | struct GPACTRL_BITS bit; 34 | }; 35 | 36 | //---------------------------------------------------- 37 | // GPIO B control register bit definitions */ 38 | struct GPBCTRL_BITS { // bits description 39 | Uint16 QUALPRD0:8; // 7:0 Qual period 40 | Uint16 rsvd1:8; // 15:8 reserved 41 | Uint16 rsvd2:16; // 31:16 reserved 42 | }; 43 | 44 | union GPBCTRL_REG { 45 | Uint32 all; 46 | struct GPBCTRL_BITS bit; 47 | }; 48 | 49 | //---------------------------------------------------- 50 | // GPIO A Qual/MUX select register bit definitions */ 51 | struct GPA1_BITS { // bits description 52 | Uint16 GPIO0:2; // 1:0 GPIO0 53 | Uint16 GPIO1:2; // 3:2 GPIO1 54 | Uint16 GPIO2:2; // 5:4 GPIO2 55 | Uint16 GPIO3:2; // 7:6 GPIO3 56 | Uint16 GPIO4:2; // 9:8 GPIO4 57 | Uint16 GPIO5:2; // 11:10 GPIO5 58 | Uint16 GPIO6:2; // 13:12 GPIO6 59 | Uint16 GPIO7:2; // 15:14 GPIO7 60 | Uint16 GPIO8:2; // 17:16 GPIO8 61 | Uint16 GPIO9:2; // 19:18 GPIO9 62 | Uint16 GPIO10:2; // 21:20 GPIO10 63 | Uint16 GPIO11:2; // 23:22 GPIO11 64 | Uint16 GPIO12:2; // 25:24 GPIO12 65 | Uint16 GPIO13:2; // 27:26 GPIO13 66 | Uint16 GPIO14:2; // 29:28 GPIO14 67 | Uint16 GPIO15:2; // 31:30 GPIO15 68 | }; 69 | 70 | 71 | struct GPA2_BITS { // bits description 72 | Uint16 GPIO16:2; // 1:0 GPIO16 73 | Uint16 GPIO17:2; // 3:2 GPIO17 74 | Uint16 GPIO18:2; // 5:4 GPIO18 75 | Uint16 GPIO19:2; // 7:6 GPIO19 76 | Uint16 GPIO20:2; // 9:8 GPIO20 77 | Uint16 GPIO21:2; // 11:10 GPIO21 78 | Uint16 GPIO22:2; // 13:12 GPIO22 79 | Uint16 GPIO23:2; // 15:14 GPIO23 80 | Uint16 GPIO24:2; // 17:16 GPIO24 81 | Uint16 GPIO25:2; // 19:18 GPIO25 82 | Uint16 GPIO26:2; // 21:20 GPIO26 83 | Uint16 GPIO27:2; // 23:22 GPIO27 84 | Uint16 GPIO28:2; // 25:24 GPIO28 85 | Uint16 GPIO29:2; // 27:26 GPIO29 86 | Uint16 GPIO30:2; // 29:28 GPIO30 87 | Uint16 GPIO31:2; // 31:30 GPIO31 88 | }; 89 | 90 | struct GPB1_BITS { // bits description 91 | Uint16 GPIO32:2; // 1:0 GPIO32 92 | Uint16 GPIO33:2; // 3:2 GPIO33 93 | Uint16 GPIO34:2; // 5:4 GPIO34 94 | Uint16 rsvd1:2; // 7:6 reserved 95 | Uint16 rsvd2:8; // 15:8 reserved 96 | Uint16 rsvd3:16; // 31:16 reserved 97 | }; 98 | 99 | struct GPB2_BITS { // bits description 100 | Uint16 rsvd1:16; // 15:0 reserved 101 | Uint16 rsvd2:16; // 31:16 reserved 102 | }; 103 | 104 | 105 | 106 | union GPA1_REG { 107 | Uint32 all; 108 | struct GPA1_BITS bit; 109 | }; 110 | 111 | union GPA2_REG { 112 | Uint32 all; 113 | struct GPA2_BITS bit; 114 | }; 115 | 116 | union GPB1_REG { 117 | Uint32 all; 118 | struct GPB1_BITS bit; 119 | }; 120 | 121 | union GPB2_REG { 122 | Uint32 all; 123 | struct GPB2_BITS bit; 124 | }; 125 | 126 | 127 | //---------------------------------------------------- 128 | // GPIO A DIR/TOGGLE/SET/CLEAR register bit definitions */ 129 | struct GPADAT_BITS { // bits description 130 | Uint16 GPIO0:1; // 0 GPIO0 131 | Uint16 GPIO1:1; // 1 GPIO1 132 | Uint16 GPIO2:1; // 2 GPIO2 133 | Uint16 GPIO3:1; // 3 GPIO3 134 | Uint16 GPIO4:1; // 4 GPIO4 135 | Uint16 GPIO5:1; // 5 GPIO5 136 | Uint16 GPIO6:1; // 6 GPIO6 137 | Uint16 GPIO7:1; // 7 GPIO7 138 | Uint16 GPIO8:1; // 8 GPIO8 139 | Uint16 GPIO9:1; // 9 GPIO9 140 | Uint16 GPIO10:1; // 10 GPIO10 141 | Uint16 GPIO11:1; // 11 GPIO11 142 | Uint16 GPIO12:1; // 12 GPIO12 143 | Uint16 GPIO13:1; // 13 GPIO13 144 | Uint16 GPIO14:1; // 14 GPIO14 145 | Uint16 GPIO15:1; // 15 GPIO15 146 | Uint16 GPIO16:1; // 16 GPIO16 147 | Uint16 GPIO17:1; // 17 GPIO17 148 | Uint16 GPIO18:1; // 18 GPIO18 149 | Uint16 GPIO19:1; // 19 GPIO19 150 | Uint16 GPIO20:1; // 20 GPIO20 151 | Uint16 GPIO21:1; // 21 GPIO21 152 | Uint16 GPIO22:1; // 22 GPIO22 153 | Uint16 GPIO23:1; // 23 GPIO23 154 | Uint16 GPIO24:1; // 24 GPIO24 155 | Uint16 GPIO25:1; // 25 GPIO25 156 | Uint16 GPIO26:1; // 26 GPIO26 157 | Uint16 GPIO27:1; // 27 GPIO27 158 | Uint16 GPIO28:1; // 28 GPIO28 159 | Uint16 GPIO29:1; // 29 GPIO29 160 | Uint16 GPIO30:1; // 30 GPIO30 161 | Uint16 GPIO31:1; // 31 GPIO31 162 | }; 163 | 164 | struct GPBDAT_BITS { // bits description 165 | Uint16 GPIO32:1; // 0 GPIO32 166 | Uint16 GPIO33:1; // 1 GPIO33 167 | Uint16 GPIO34:1; // 2 GPIO34 168 | Uint16 rsvd1:13; // 15:3 reserved 169 | Uint16 rsvd2:16; // 31:16 reserved 170 | }; 171 | 172 | union GPADAT_REG { 173 | Uint32 all; 174 | struct GPADAT_BITS bit; 175 | }; 176 | 177 | union GPBDAT_REG { 178 | Uint32 all; 179 | struct GPBDAT_BITS bit; 180 | }; 181 | 182 | 183 | // GPIO35 is an internal pin that is not pinned out 184 | // for HALT low power mode, enable the internal pull-up 185 | // to avoid extran current draw from this pin. 186 | 187 | struct GPBPUD_BITS { // bits description 188 | Uint16 GPIO32:1; // 0 GPIO32 189 | Uint16 GPIO33:1; // 1 GPIO33 190 | Uint16 GPIO34:1; // 2 GPIO34 191 | Uint16 GPIO35:1; // 3 GPIO35 192 | Uint16 rsvd1:12; // 15:4 reserved 193 | Uint16 rsvd2:16; // 31:16 reserved 194 | }; 195 | 196 | union GPBPUD_REG { 197 | Uint32 all; 198 | struct GPBPUD_BITS bit; 199 | }; 200 | 201 | 202 | 203 | 204 | //---------------------------------------------------- 205 | // GPIO XINT1/XINT2/XNMI select register bit definitions */ 206 | struct GPIOXINT_BITS { // bits description 207 | Uint16 GPIOSEL:5; // 4:0 Select GPIO interrupt input source 208 | Uint16 rsvd1:11; // 15:5 reserved 209 | }; 210 | 211 | union GPIOXINT_REG { 212 | Uint16 all; 213 | struct GPIOXINT_BITS bit; 214 | }; 215 | 216 | 217 | struct GPIO_CTRL_REGS { 218 | union GPACTRL_REG GPACTRL; // GPIO A Control Register (GPIO0 to 31) 219 | union GPA1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) 220 | union GPA2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) 221 | union GPA1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) 222 | union GPA2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) 223 | union GPADAT_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) 224 | union GPADAT_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) 225 | Uint32 rsvd1; 226 | union GPBCTRL_REG GPBCTRL; // GPIO B Control Register (GPIO32 to 63) 227 | union GPB1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) 228 | union GPB2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) 229 | union GPB1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) 230 | union GPB2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) 231 | union GPBDAT_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) 232 | union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) 233 | Uint16 rsvd2[33]; 234 | }; 235 | 236 | struct GPIO_DATA_REGS { 237 | union GPADAT_REG GPADAT; // GPIO Data Register (GPIO0 to 31) 238 | union GPADAT_REG GPASET; // GPIO Data Set Register (GPIO0 to 31) 239 | union GPADAT_REG GPACLEAR; // GPIO Data Clear Register (GPIO0 to 31) 240 | union GPADAT_REG GPATOGGLE; // GPIO Data Toggle Register (GPIO0 to 31) 241 | union GPBDAT_REG GPBDAT; // GPIO Data Register (GPIO32 to 63) 242 | union GPBDAT_REG GPBSET; // GPIO Data Set Register (GPIO32 to 63) 243 | union GPBDAT_REG GPBCLEAR; // GPIO Data Clear Register (GPIO32 to 63) 244 | union GPBDAT_REG GPBTOGGLE; // GPIO Data Toggle Register (GPIO32 to 63) 245 | Uint16 rsvd1[16]; 246 | }; 247 | 248 | struct GPIO_INT_REGS { 249 | union GPIOXINT_REG GPIOXINT1SEL; // XINT1 GPIO Input Selection 250 | union GPIOXINT_REG GPIOXINT2SEL; // XINT2 GPIO Input Selection 251 | union GPIOXINT_REG GPIOXNMISEL; // XNMI_XINT13 GPIO Input Selection 252 | Uint16 rsvd2[5]; 253 | union GPADAT_REG GPIOLPMSEL; // Low power modes GP I/O input select 254 | }; 255 | 256 | 257 | //--------------------------------------------------------------------------- 258 | // GPI/O External References & Function Declarations: 259 | // 260 | extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; 261 | extern volatile struct GPIO_DATA_REGS GpioDataRegs; 262 | extern volatile struct GPIO_INT_REGS GpioIntRegs; 263 | 264 | #ifdef __cplusplus 265 | } 266 | #endif /* extern "C" */ 267 | 268 | #endif // end of DSP280x_GPIO_H definition 269 | 270 | //=========================================================================== 271 | // End of file. 272 | //=========================================================================== 273 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_I2c.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: December 2, 2004 13:43:02 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_I2c.h 6 | // 7 | // TITLE: DSP280x Enhanced Quadrature Encoder Pulse Module 8 | // Register Bit Definitions. 9 | // 10 | //########################################################################### 11 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 12 | // $Release Date: July 27, 2009 $ 13 | //########################################################################### 14 | 15 | #ifndef DSP280x_I2C_H 16 | #define DSP280x_I2C_H 17 | 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | 24 | //---------------------------------------------------- 25 | // I2C interrupt vector register bit definitions */ 26 | struct I2CISRC_BITS { // bits description 27 | Uint16 INTCODE:3; // 2:0 Interrupt code 28 | Uint16 rsvd1:13; // 15:3 reserved 29 | }; 30 | 31 | union I2CISRC_REG { 32 | Uint16 all; 33 | struct I2CISRC_BITS bit; 34 | }; 35 | 36 | //---------------------------------------------------- 37 | // I2C interrupt mask register bit definitions */ 38 | struct I2CIER_BITS { // bits description 39 | Uint16 AL:1; // 0 Arbitration lost interrupt 40 | Uint16 NACK:1; // 1 No ack interrupt 41 | Uint16 ARDY:1; // 2 Register access ready interrupt 42 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 43 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 44 | Uint16 SCD:1; // 5 Stop condition detection 45 | Uint16 AAS:1; // 6 Address as slave 46 | Uint16 rsvd:9; // 15:7 reserved 47 | }; 48 | 49 | union I2CIER_REG { 50 | Uint16 all; 51 | struct I2CIER_BITS bit; 52 | }; 53 | 54 | //---------------------------------------------------- 55 | // I2C status register bit definitions */ 56 | struct I2CSTR_BITS { // bits description 57 | Uint16 AL:1; // 0 Arbitration lost interrupt 58 | Uint16 NACK:1; // 1 No ack interrupt 59 | Uint16 ARDY:1; // 2 Register access ready interrupt 60 | Uint16 RRDY:1; // 3 Recieve data ready interrupt 61 | Uint16 XRDY:1; // 4 Transmit data ready interrupt 62 | Uint16 SCD:1; // 5 Stop condition detection 63 | Uint16 rsvd1:2; // 7:6 reserved 64 | Uint16 AD0:1; // 8 Address Zero 65 | Uint16 AAS:1; // 9 Address as slave 66 | Uint16 XSMT:1; // 10 XMIT shift empty 67 | Uint16 RSFULL:1; // 11 Recieve shift full 68 | Uint16 BB:1; // 12 Bus busy 69 | Uint16 NACKSNT:1; // 13 A no ack sent 70 | Uint16 SDIR:1; // 14 Slave direction 71 | Uint16 rsvd2:1; // 15 reserved 72 | }; 73 | 74 | union I2CSTR_REG { 75 | Uint16 all; 76 | struct I2CSTR_BITS bit; 77 | }; 78 | 79 | 80 | //---------------------------------------------------- 81 | // I2C mode control register bit definitions */ 82 | struct I2CMDR_BITS { // bits description 83 | Uint16 BC:3; // 2:0 Bit count 84 | Uint16 FDF:1; // 3 Free data format 85 | Uint16 STB:1; // 4 Start byte 86 | Uint16 IRS:1; // 5 I2C Reset not 87 | Uint16 DLB:1; // 6 Digital loopback 88 | Uint16 RM:1; // 7 Repeat mode 89 | Uint16 XA:1; // 8 Expand address 90 | Uint16 TRX:1; // 9 Transmitter/reciever 91 | Uint16 MST:1; // 10 Master/slave 92 | Uint16 STP:1; // 11 Stop condition 93 | Uint16 rsvd1:1; // 12 reserved 94 | Uint16 STT:1; // 13 Start condition 95 | Uint16 FREE:1; // 14 Emulation mode 96 | Uint16 NACKMOD:1; // 15 No Ack mode 97 | }; 98 | 99 | union I2CMDR_REG { 100 | Uint16 all; 101 | struct I2CMDR_BITS bit; 102 | }; 103 | 104 | //---------------------------------------------------- 105 | // I2C pre-scaler register bit definitions */ 106 | struct I2CPSC_BITS { // bits description 107 | Uint16 IPSC:8; // 7:0 pre-scaler 108 | Uint16 rsvd1:8; // 15:8 reserved 109 | }; 110 | 111 | 112 | union I2CPSC_REG { 113 | Uint16 all; 114 | struct I2CPSC_BITS bit; 115 | }; 116 | 117 | 118 | //---------------------------------------------------- 119 | // TX FIFO control register bit definitions */ 120 | struct I2CFFTX_BITS { // bits description 121 | Uint16 TXFFIL:5; // 4:0 FIFO interrupt level 122 | Uint16 TXFFIENA:1; // 5 FIFO interrupt enable/disable 123 | Uint16 TXFFINTCLR:1; // 6 FIFO clear 124 | Uint16 TXFFINT:1; // 7 FIFO interrupt flag 125 | Uint16 TXFFST:5; // 12:8 FIFO level status 126 | Uint16 TXFFRST:1; // 13 FIFO reset 127 | Uint16 I2CFFEN:1; // 14 enable/disable TX & RX FIFOs 128 | Uint16 rsvd1:1; // 15 reserved 129 | 130 | }; 131 | 132 | union I2CFFTX_REG { 133 | Uint16 all; 134 | struct I2CFFTX_BITS bit; 135 | }; 136 | 137 | //---------------------------------------------------- 138 | // RX FIFO control register bit definitions */ 139 | struct I2CFFRX_BITS { // bits description 140 | Uint16 RXFFIL:5; // 4:0 FIFO interrupt level 141 | Uint16 RXFFIENA:1; // 5 FIFO interrupt enable/disable 142 | Uint16 RXFFINTCLR:1; // 6 FIFO clear 143 | Uint16 RXFFINT:1; // 7 FIFO interrupt flag 144 | Uint16 RXFFST:5; // 12:8 FIFO level 145 | Uint16 RXFFRST:1; // 13 FIFO reset 146 | Uint16 rsvd1:2; // 15:14 reserved 147 | }; 148 | 149 | union I2CFFRX_REG { 150 | Uint16 all; 151 | struct I2CFFRX_BITS bit; 152 | }; 153 | 154 | 155 | //---------------------------------------------------- 156 | 157 | struct I2C_REGS { 158 | Uint16 I2COAR; // Own address register 159 | union I2CIER_REG I2CIER; // Interrupt enable 160 | union I2CSTR_REG I2CSTR; // Interrupt status 161 | Uint16 I2CCLKL; // Clock divider low 162 | Uint16 I2CCLKH; // Clock divider high 163 | Uint16 I2CCNT; // Data count 164 | Uint16 I2CDRR; // Data recieve 165 | Uint16 I2CSAR; // Slave address 166 | Uint16 I2CDXR; // Data transmit 167 | union I2CMDR_REG I2CMDR; // Mode 168 | union I2CISRC_REG I2CISRC; // Interrupt source 169 | Uint16 rsvd1; // reserved 170 | union I2CPSC_REG I2CPSC; // Pre-scaler 171 | Uint16 rsvd2[19]; // reserved 172 | union I2CFFTX_REG I2CFFTX; // Transmit FIFO 173 | union I2CFFRX_REG I2CFFRX; // Recieve FIFO 174 | }; 175 | 176 | 177 | 178 | 179 | //--------------------------------------------------------------------------- 180 | // External References & Function Declarations: 181 | // 182 | extern volatile struct I2C_REGS I2caRegs; 183 | 184 | 185 | #ifdef __cplusplus 186 | } 187 | #endif /* extern "C" */ 188 | 189 | #endif // end of DSP280x_I2C_H definition 190 | 191 | //=========================================================================== 192 | // End of file. 193 | //=========================================================================== 194 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_I2c_defines.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: July 9, 2009 10:13:47 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_I2cExample.h 6 | // 7 | // TITLE: 280x I2C Example Code Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280X_I2C_DEFINES_H 15 | #define DSP280X_I2C_DEFINES_H 16 | 17 | //-------------------------------------------- 18 | // Defines 19 | //-------------------------------------------- 20 | 21 | // Error Messages 22 | #define I2C_ERROR 0xFFFF 23 | #define I2C_ARB_LOST_ERROR 0x0001 24 | #define I2C_NACK_ERROR 0x0002 25 | #define I2C_BUS_BUSY_ERROR 0x1000 26 | #define I2C_STP_NOT_READY_ERROR 0x5555 27 | #define I2C_NO_FLAGS 0xAAAA 28 | #define I2C_SUCCESS 0x0000 29 | 30 | // Clear Status Flags 31 | #define I2C_CLR_AL_BIT 0x0001 32 | #define I2C_CLR_NACK_BIT 0x0002 33 | #define I2C_CLR_ARDY_BIT 0x0004 34 | #define I2C_CLR_RRDY_BIT 0x0008 35 | #define I2C_CLR_SCD_BIT 0x0020 36 | 37 | // Interrupt Source Messages 38 | #define I2C_NO_ISRC 0x0000 39 | #define I2C_ARB_ISRC 0x0001 40 | #define I2C_NACK_ISRC 0x0002 41 | #define I2C_ARDY_ISRC 0x0003 42 | #define I2C_RX_ISRC 0x0004 43 | #define I2C_TX_ISRC 0x0005 44 | #define I2C_SCD_ISRC 0x0006 45 | #define I2C_AAS_ISRC 0x0007 46 | 47 | // I2CMSG structure defines 48 | #define I2C_NO_STOP 0 49 | #define I2C_YES_STOP 1 50 | #define I2C_RECEIVE 0 51 | #define I2C_TRANSMIT 1 52 | #define I2C_MAX_BUFFER_SIZE 16 53 | 54 | // I2C Slave State defines 55 | #define I2C_NOTSLAVE 0 56 | #define I2C_ADDR_AS_SLAVE 1 57 | #define I2C_ST_MSG_READY 2 58 | 59 | // I2C Slave Receiver messages defines 60 | #define I2C_SND_MSG1 1 61 | #define I2C_SND_MSG2 2 62 | 63 | // I2C State defines 64 | #define I2C_IDLE 0 65 | #define I2C_SLAVE_RECEIVER 1 66 | #define I2C_SLAVE_TRANSMITTER 2 67 | #define I2C_MASTER_RECEIVER 3 68 | #define I2C_MASTER_TRANSMITTER 4 69 | 70 | // I2C Message Commands for I2CMSG struct 71 | #define I2C_MSGSTAT_INACTIVE 0x0000 72 | #define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 73 | #define I2C_MSGSTAT_WRITE_BUSY 0x0011 74 | #define I2C_MSGSTAT_SEND_NOSTOP 0x0020 75 | #define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 76 | #define I2C_MSGSTAT_RESTART 0x0022 77 | #define I2C_MSGSTAT_READ_BUSY 0x0023 78 | 79 | // Generic defines 80 | #define I2C_TRUE 1 81 | #define I2C_FALSE 0 82 | #define I2C_YES 1 83 | #define I2C_NO 0 84 | #define I2C_DUMMY_BYTE 0 85 | 86 | 87 | //-------------------------------------------- 88 | // Structures 89 | //-------------------------------------------- 90 | 91 | // I2C Message Structure 92 | struct I2CMSG { 93 | Uint16 MsgStatus; // Word stating what state msg is in: 94 | // I2C_MSGCMD_INACTIVE = do not send msg 95 | // I2C_MSGCMD_BUSY = msg start has been sent, 96 | // awaiting stop 97 | // I2C_MSGCMD_SEND_WITHSTOP = command to send 98 | // master trans msg complete with a stop bit 99 | // I2C_MSGCMD_SEND_NOSTOP = command to send 100 | // master trans msg without the stop bit 101 | // I2C_MSGCMD_RESTART = command to send a restart 102 | // as a master receiver with a stop bit 103 | Uint16 SlaveAddress; // I2C address of slave msg is intended for 104 | Uint16 NumOfBytes; // Num of valid bytes in (or to be put in MsgBuffer) 105 | Uint16 MemoryHighAddr; // EEPROM address of data associated with msg (high byte) 106 | Uint16 MemoryLowAddr; // EEPROM address of data associated with msg (low byte) 107 | Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that 108 | // MAX_BUFFER_SIZE can be is 16 due to 109 | // the FIFO's 110 | }; 111 | 112 | 113 | #endif // end of DSP280X_I2C_DEFINES_H definition 114 | 115 | //=========================================================================== 116 | // End of file. 117 | //=========================================================================== 118 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/2 $ 2 | // Checkin $Date: August 2, 2006 14:35:45 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_PieCtrl.h 6 | // 7 | // TITLE: DSP280x Device PIE Control Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | 15 | #ifndef DSP280x_PIE_CTRL_H 16 | #define DSP280x_PIE_CTRL_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | // PIE Control Register Bit Definitions: 24 | // 25 | // PIECTRL: Register bit definitions: 26 | struct PIECTRL_BITS { // bits description 27 | Uint16 ENPIE:1; // 0 Enable PIE block 28 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 29 | }; 30 | 31 | union PIECTRL_REG { 32 | Uint16 all; 33 | struct PIECTRL_BITS bit; 34 | }; 35 | 36 | // PIEIER: Register bit definitions: 37 | struct PIEIER_BITS { // bits description 38 | Uint16 INTx1:1; // 0 INTx.1 39 | Uint16 INTx2:1; // 1 INTx.2 40 | Uint16 INTx3:1; // 2 INTx.3 41 | Uint16 INTx4:1; // 3 INTx.4 42 | Uint16 INTx5:1; // 4 INTx.5 43 | Uint16 INTx6:1; // 5 INTx.6 44 | Uint16 INTx7:1; // 6 INTx.7 45 | Uint16 INTx8:1; // 7 INTx.8 46 | Uint16 rsvd:8; // 15:8 reserved 47 | }; 48 | 49 | union PIEIER_REG { 50 | Uint16 all; 51 | struct PIEIER_BITS bit; 52 | }; 53 | 54 | // PIEIFR: Register bit definitions: 55 | struct PIEIFR_BITS { // bits description 56 | Uint16 INTx1:1; // 0 INTx.1 57 | Uint16 INTx2:1; // 1 INTx.2 58 | Uint16 INTx3:1; // 2 INTx.3 59 | Uint16 INTx4:1; // 3 INTx.4 60 | Uint16 INTx5:1; // 4 INTx.5 61 | Uint16 INTx6:1; // 5 INTx.6 62 | Uint16 INTx7:1; // 6 INTx.7 63 | Uint16 INTx8:1; // 7 INTx.8 64 | Uint16 rsvd:8; // 15:8 reserved 65 | }; 66 | 67 | union PIEIFR_REG { 68 | Uint16 all; 69 | struct PIEIFR_BITS bit; 70 | }; 71 | 72 | // PIEACK: Register bit definitions: 73 | struct PIEACK_BITS { // bits description 74 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 75 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 76 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 77 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 78 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 79 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 80 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 81 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 82 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 83 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 84 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 85 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 86 | Uint16 rsvd:4; // 15:12 reserved 87 | }; 88 | 89 | union PIEACK_REG { 90 | Uint16 all; 91 | struct PIEACK_BITS bit; 92 | }; 93 | 94 | //--------------------------------------------------------------------------- 95 | // PIE Control Register File: 96 | // 97 | struct PIE_CTRL_REGS { 98 | union PIECTRL_REG PIECTRL; // PIE control register 99 | union PIEACK_REG PIEACK; // PIE acknowledge 100 | union PIEIER_REG PIEIER1; // PIE INT1 IER register 101 | union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register 102 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 103 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 104 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 105 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 106 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 107 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 108 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 109 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 110 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 111 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 112 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 113 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 114 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 115 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 116 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 117 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 118 | union PIEIER_REG PIEIER10; // PIE INT10 IER register 119 | union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register 120 | union PIEIER_REG PIEIER11; // PIE INT11 IER register 121 | union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register 122 | union PIEIER_REG PIEIER12; // PIE INT12 IER register 123 | union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register 124 | }; 125 | 126 | #define PIEACK_GROUP1 0x0001 127 | #define PIEACK_GROUP2 0x0002 128 | #define PIEACK_GROUP3 0x0004 129 | #define PIEACK_GROUP4 0x0008 130 | #define PIEACK_GROUP5 0x0010 131 | #define PIEACK_GROUP6 0x0020 132 | #define PIEACK_GROUP7 0x0040 133 | #define PIEACK_GROUP8 0x0080 134 | #define PIEACK_GROUP9 0x0100 135 | #define PIEACK_GROUP10 0x0200 136 | #define PIEACK_GROUP11 0x0400 137 | #define PIEACK_GROUP12 0x0800 138 | 139 | //--------------------------------------------------------------------------- 140 | // PIE Control Registers External References & Function Declarations: 141 | // 142 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 143 | 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif /* extern "C" */ 148 | 149 | #endif // end of DSP280x_PIE_CTRL_H definition 150 | 151 | //=========================================================================== 152 | // End of file. 153 | //=========================================================================== 154 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_PieVect.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: December 1, 2004 12:31:56 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_PieVect.h 6 | // 7 | // TITLE: DSP280x Devices PIE Vector Table Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_PIE_VECT_H 15 | #define DSP280x_PIE_VECT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // PIE Interrupt Vector Table Definition: 25 | // 26 | // Create a user type called PINT (pointer to interrupt): 27 | 28 | typedef interrupt void(*PINT)(void); 29 | 30 | // Define Vector Table: 31 | struct PIE_VECT_TABLE { 32 | 33 | // Reset is never fetched from this table. 34 | // It will always be fetched from 0x3FFFC0 in 35 | // boot ROM 36 | 37 | PINT PIE1_RESERVED; 38 | PINT PIE2_RESERVED; 39 | PINT PIE3_RESERVED; 40 | PINT PIE4_RESERVED; 41 | PINT PIE5_RESERVED; 42 | PINT PIE6_RESERVED; 43 | PINT PIE7_RESERVED; 44 | PINT PIE8_RESERVED; 45 | PINT PIE9_RESERVED; 46 | PINT PIE10_RESERVED; 47 | PINT PIE11_RESERVED; 48 | PINT PIE12_RESERVED; 49 | PINT PIE13_RESERVED; 50 | 51 | // Non-Peripheral Interrupts: 52 | PINT XINT13; // XINT13 53 | PINT TINT2; // CPU-Timer2 54 | PINT DATALOG; // Datalogging interrupt 55 | PINT RTOSINT; // RTOS interrupt 56 | PINT EMUINT; // Emulation interrupt 57 | PINT XNMI; // Non-maskable interrupt 58 | PINT ILLEGAL; // Illegal operation TRAP 59 | PINT USER1; // User Defined trap 1 60 | PINT USER2; // User Defined trap 2 61 | PINT USER3; // User Defined trap 3 62 | PINT USER4; // User Defined trap 4 63 | PINT USER5; // User Defined trap 5 64 | PINT USER6; // User Defined trap 6 65 | PINT USER7; // User Defined trap 7 66 | PINT USER8; // User Defined trap 8 67 | PINT USER9; // User Defined trap 9 68 | PINT USER10; // User Defined trap 10 69 | PINT USER11; // User Defined trap 11 70 | PINT USER12; // User Defined trap 12 71 | 72 | // Group 1 PIE Peripheral Vectors: 73 | PINT SEQ1INT; 74 | PINT SEQ2INT; 75 | PINT rsvd1_3; 76 | PINT XINT1; 77 | PINT XINT2; 78 | PINT ADCINT; // ADC 79 | PINT TINT0; // Timer 0 80 | PINT WAKEINT; // WD 81 | 82 | // Group 2 PIE Peripheral Vectors: 83 | PINT EPWM1_TZINT; // EPWM-1 84 | PINT EPWM2_TZINT; // EPWM-2 85 | PINT EPWM3_TZINT; // EPWM-3 86 | PINT EPWM4_TZINT; // EPWM-4 87 | PINT EPWM5_TZINT; // EPWM-5 88 | PINT EPWM6_TZINT; // EPWM-6 89 | PINT rsvd2_7; 90 | PINT rsvd2_8; 91 | 92 | // Group 3 PIE Peripheral Vectors: 93 | PINT EPWM1_INT; // EPWM-1 94 | PINT EPWM2_INT; // EPWM-2 95 | PINT EPWM3_INT; // EPWM-3 96 | PINT EPWM4_INT; // EPWM-4 97 | PINT EPWM5_INT; // EPWM-5 98 | PINT EPWM6_INT; // EPWM-6 99 | PINT rsvd3_7; 100 | PINT rsvd3_8; 101 | 102 | // Group 4 PIE Peripheral Vectors: 103 | PINT ECAP1_INT; // ECAP-1 104 | PINT ECAP2_INT; // ECAP-2 105 | PINT ECAP3_INT; // ECAP-3 106 | PINT ECAP4_INT; // ECAP-4 107 | PINT rsvd4_5; 108 | PINT rsvd4_6; 109 | PINT rsvd4_7; 110 | PINT rsvd4_8; 111 | 112 | // Group 5 PIE Peripheral Vectors: 113 | PINT EQEP1_INT; // EQEP-1 114 | PINT EQEP2_INT; // EQEP-2 115 | PINT rsvd5_3; 116 | PINT rsvd5_4; 117 | PINT rsvd5_5; 118 | PINT rsvd5_6; 119 | PINT rsvd5_7; 120 | PINT rsvd5_8; 121 | 122 | // Group 6 PIE Peripheral Vectors: 123 | PINT SPIRXINTA; // SPI-A 124 | PINT SPITXINTA; // SPI-A 125 | PINT SPIRXINTB; // SPI-B 126 | PINT SPITXINTB; // SPI-B 127 | PINT SPIRXINTC; // SPI-C 128 | PINT SPITXINTC; // SPI-C 129 | PINT SPIRXINTD; // SPI-D 130 | PINT SPITXINTD; // SPI-D 131 | 132 | // Group 7 PIE Peripheral Vectors: 133 | PINT rsvd7_1; 134 | PINT rsvd7_2; 135 | PINT rsvd7_3; 136 | PINT rsvd7_4; 137 | PINT rsvd7_5; 138 | PINT rsvd7_6; 139 | PINT rsvd7_7; 140 | PINT rsvd7_8; 141 | 142 | // Group 8 PIE Peripheral Vectors: 143 | PINT I2CINT1A; // I2C-A 144 | PINT I2CINT2A; // I2C-A 145 | PINT rsvd8_3; 146 | PINT rsvd8_4; 147 | PINT rsvd8_5; 148 | PINT rsvd8_6; 149 | PINT rsvd8_7; 150 | PINT rsvd8_8; 151 | 152 | // Group 9 PIE Peripheral Vectors: 153 | PINT SCIRXINTA; // SCI-A 154 | PINT SCITXINTA; // SCI-A 155 | PINT SCIRXINTB; // SCI-B 156 | PINT SCITXINTB; // SCI-B 157 | PINT ECAN0INTA; // eCAN-A 158 | PINT ECAN1INTA; // eCAN-A 159 | PINT ECAN0INTB; // eCAN-B 160 | PINT ECAN1INTB; // eCAN-B 161 | 162 | // Group 10 PIE Peripheral Vectors: 163 | PINT rsvd10_1; 164 | PINT rsvd10_2; 165 | PINT rsvd10_3; 166 | PINT rsvd10_4; 167 | PINT rsvd10_5; 168 | PINT rsvd10_6; 169 | PINT rsvd10_7; 170 | PINT rsvd10_8; 171 | 172 | // Group 11 PIE Peripheral Vectors: 173 | PINT rsvd11_1; 174 | PINT rsvd11_2; 175 | PINT rsvd11_3; 176 | PINT rsvd11_4; 177 | PINT rsvd11_5; 178 | PINT rsvd11_6; 179 | PINT rsvd11_7; 180 | PINT rsvd11_8; 181 | 182 | // Group 12 PIE Peripheral Vectors: 183 | PINT rsvd12_1; 184 | PINT rsvd12_2; 185 | PINT rsvd12_3; 186 | PINT rsvd12_4; 187 | PINT rsvd12_5; 188 | PINT rsvd12_6; 189 | PINT rsvd12_7; 190 | PINT rsvd12_8; 191 | }; 192 | 193 | //--------------------------------------------------------------------------- 194 | // PIE Interrupt Vector Table External References & Function Declarations: 195 | // 196 | extern struct PIE_VECT_TABLE PieVectTable; 197 | 198 | 199 | #ifdef __cplusplus 200 | } 201 | #endif /* extern "C" */ 202 | 203 | #endif // end of DSP280x_PIE_VECT_H definition 204 | 205 | //=========================================================================== 206 | // End of file. 207 | //=========================================================================== 208 | 209 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Sci.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: December 1, 2004 12:31:58 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Sci.h 6 | // 7 | // TITLE: DSP280x Device SCI Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_SCI_H 15 | #define DSP280x_SCI_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | // SCI Individual Register Bit Definitions 24 | 25 | //---------------------------------------------------------- 26 | // SCICCR communication control register bit definitions: 27 | // 28 | 29 | struct SCICCR_BITS { // bit description 30 | Uint16 SCICHAR:3; // 2:0 Character length control 31 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 32 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 33 | Uint16 PARITYENA:1; // 5 Parity enable 34 | Uint16 PARITY:1; // 6 Even or Odd Parity 35 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 36 | Uint16 rsvd1:8; // 15:8 reserved 37 | }; 38 | 39 | 40 | union SCICCR_REG { 41 | Uint16 all; 42 | struct SCICCR_BITS bit; 43 | }; 44 | 45 | //------------------------------------------- 46 | // SCICTL1 control register 1 bit definitions: 47 | // 48 | 49 | struct SCICTL1_BITS { // bit description 50 | Uint16 RXENA:1; // 0 SCI receiver enable 51 | Uint16 TXENA:1; // 1 SCI transmitter enable 52 | Uint16 SLEEP:1; // 2 SCI sleep 53 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 54 | Uint16 rsvd:1; // 4 reserved 55 | Uint16 SWRESET:1; // 5 Software reset 56 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 57 | Uint16 rsvd1:9; // 15:7 reserved 58 | 59 | }; 60 | 61 | union SCICTL1_REG { 62 | Uint16 all; 63 | struct SCICTL1_BITS bit; 64 | }; 65 | 66 | //--------------------------------------------- 67 | // SCICTL2 control register 2 bit definitions: 68 | // 69 | 70 | struct SCICTL2_BITS { // bit description 71 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 72 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 73 | Uint16 rsvd:4; // 5:2 reserved 74 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 75 | Uint16 TXRDY:1; // 7 Transmitter ready flag 76 | Uint16 rsvd1:8; // 15:8 reserved 77 | 78 | }; 79 | 80 | union SCICTL2_REG { 81 | Uint16 all; 82 | struct SCICTL2_BITS bit; 83 | }; 84 | 85 | //--------------------------------------------------- 86 | // SCIRXST Receiver status register bit definitions: 87 | // 88 | 89 | struct SCIRXST_BITS { // bit description 90 | Uint16 rsvd:1; // 0 reserved 91 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 92 | Uint16 PE:1; // 2 Parity error flag 93 | Uint16 OE:1; // 3 Overrun error flag 94 | Uint16 FE:1; // 4 Framing error flag 95 | Uint16 BRKDT:1; // 5 Break-detect flag 96 | Uint16 RXRDY:1; // 6 Receiver ready flag 97 | Uint16 RXERROR:1; // 7 Receiver error flag 98 | 99 | }; 100 | 101 | union SCIRXST_REG { 102 | Uint16 all; 103 | struct SCIRXST_BITS bit; 104 | }; 105 | 106 | //---------------------------------------------------- 107 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: 108 | // 109 | 110 | struct SCIRXBUF_BITS { // bits description 111 | Uint16 RXDT:8; // 7:0 Receive word 112 | Uint16 rsvd:6; // 13:8 reserved 113 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 114 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 115 | }; 116 | 117 | union SCIRXBUF_REG { 118 | Uint16 all; 119 | struct SCIRXBUF_BITS bit; 120 | }; 121 | 122 | //-------------------------------------------------- 123 | // SCIPRI Priority control register bit definitions: 124 | // 125 | // 126 | 127 | struct SCIPRI_BITS { // bit description 128 | Uint16 rsvd:3; // 2:0 reserved 129 | Uint16 FREE:1; // 3 Free emulation suspend mode 130 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 131 | Uint16 rsvd1:3; // 7:5 reserved 132 | }; 133 | 134 | union SCIPRI_REG { 135 | Uint16 all; 136 | struct SCIPRI_BITS bit; 137 | }; 138 | 139 | //------------------------------------------------- 140 | // SCI FIFO Transmit register bit definitions: 141 | // 142 | // 143 | 144 | struct SCIFFTX_BITS { // bit description 145 | Uint16 TXFFIL:5; // 4:0 Interrupt level 146 | Uint16 TXFFIENA:1; // 5 Interrupt enable 147 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 148 | Uint16 TXFFINT:1; // 7 INT flag 149 | Uint16 TXFFST:5; // 12:8 FIFO status 150 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 151 | Uint16 SCIFFENA:1; // 14 Enhancement enable 152 | Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 153 | 154 | }; 155 | 156 | union SCIFFTX_REG { 157 | Uint16 all; 158 | struct SCIFFTX_BITS bit; 159 | }; 160 | 161 | //------------------------------------------------ 162 | // SCI FIFO recieve register bit definitions: 163 | // 164 | // 165 | 166 | struct SCIFFRX_BITS { // bits description 167 | Uint16 RXFFIL:5; // 4:0 Interrupt level 168 | Uint16 RXFFIENA:1; // 5 Interrupt enable 169 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 170 | Uint16 RXFFINT:1; // 7 INT flag 171 | Uint16 RXFFST:5; // 12:8 FIFO status 172 | Uint16 RXFIFORESET:1; // 13 FIFO reset 173 | Uint16 RXFFOVRCLR:1; // 14 Clear overflow 174 | Uint16 RXFFOVF:1; // 15 FIFO overflow 175 | 176 | }; 177 | 178 | union SCIFFRX_REG { 179 | Uint16 all; 180 | struct SCIFFRX_BITS bit; 181 | }; 182 | 183 | // SCI FIFO control register bit definitions: 184 | struct SCIFFCT_BITS { // bits description 185 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 186 | Uint16 rsvd:5; // 12:8 reserved 187 | Uint16 CDC:1; // 13 Auto baud mode enable 188 | Uint16 ABDCLR:1; // 14 Auto baud clear 189 | Uint16 ABD:1; // 15 Auto baud detect 190 | }; 191 | 192 | union SCIFFCT_REG { 193 | Uint16 all; 194 | struct SCIFFCT_BITS bit; 195 | }; 196 | 197 | //--------------------------------------------------------------------------- 198 | // SCI Register File: 199 | // 200 | struct SCI_REGS { 201 | union SCICCR_REG SCICCR; // Communications control register 202 | union SCICTL1_REG SCICTL1; // Control register 1 203 | Uint16 SCIHBAUD; // Baud rate (high) register 204 | Uint16 SCILBAUD; // Baud rate (low) register 205 | union SCICTL2_REG SCICTL2; // Control register 2 206 | union SCIRXST_REG SCIRXST; // Recieve status register 207 | Uint16 SCIRXEMU; // Recieve emulation buffer register 208 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 209 | Uint16 rsvd1; // reserved 210 | Uint16 SCITXBUF; // Transmit data buffer 211 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 212 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 213 | union SCIFFCT_REG SCIFFCT; // FIFO control register 214 | Uint16 rsvd2; // reserved 215 | Uint16 rsvd3; // reserved 216 | union SCIPRI_REG SCIPRI; // FIFO Priority control 217 | }; 218 | 219 | //--------------------------------------------------------------------------- 220 | // SCI External References & Function Declarations: 221 | // 222 | extern volatile struct SCI_REGS SciaRegs; 223 | extern volatile struct SCI_REGS ScibRegs; 224 | 225 | #ifdef __cplusplus 226 | } 227 | #endif /* extern "C" */ 228 | 229 | #endif // end of DSP280x_SCI_H definition 230 | 231 | //=========================================================================== 232 | // End of file. 233 | //=========================================================================== 234 | 235 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_Spi.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/3 $ 2 | // Checkin $Date: July 9, 2009 10:10:25 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_Spi.h 6 | // 7 | // TITLE: DSP280x Device SPI Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_SPI_H 15 | #define DSP280x_SPI_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // SPI Individual Register Bit Definitions: 25 | // 26 | // SPI FIFO Transmit register bit definitions: 27 | struct SPIFFTX_BITS { // bit description 28 | Uint16 TXFFIL:5; // 4:0 Interrupt level 29 | Uint16 TXFFIENA:1; // 5 Interrupt enable 30 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 31 | Uint16 TXFFINT:1; // 7 INT flag 32 | Uint16 TXFFST:5; // 12:8 FIFO status 33 | Uint16 TXFIFO:1; // 13 FIFO reset 34 | Uint16 SPIFFENA:1; // 14 Enhancement enable 35 | Uint16 SPIRST:1; // 15 Reset SPI 36 | }; 37 | 38 | union SPIFFTX_REG { 39 | Uint16 all; 40 | struct SPIFFTX_BITS bit; 41 | }; 42 | 43 | //-------------------------------------------- 44 | // SPI FIFO recieve register bit definitions: 45 | // 46 | // 47 | struct SPIFFRX_BITS { // bits description 48 | Uint16 RXFFIL:5; // 4:0 Interrupt level 49 | Uint16 RXFFIENA:1; // 5 Interrupt enable 50 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 51 | Uint16 RXFFINT:1; // 7 INT flag 52 | Uint16 RXFFST:5; // 12:8 FIFO status 53 | Uint16 RXFIFORESET:1; // 13 FIFO reset 54 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 55 | Uint16 RXFFOVF:1; // 15 FIFO overflow 56 | 57 | }; 58 | 59 | union SPIFFRX_REG { 60 | Uint16 all; 61 | struct SPIFFRX_BITS bit; 62 | }; 63 | 64 | //-------------------------------------------- 65 | // SPI FIFO control register bit definitions: 66 | // 67 | // 68 | struct SPIFFCT_BITS { // bits description 69 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 70 | Uint16 rsvd:8; // 15:8 reserved 71 | }; 72 | 73 | union SPIFFCT_REG { 74 | Uint16 all; 75 | struct SPIFFCT_BITS bit; 76 | }; 77 | 78 | //--------------------------------------------- 79 | // SPI configuration register bit definitions: 80 | // 81 | // 82 | struct SPICCR_BITS { // bits description 83 | Uint16 SPICHAR:4; // 3:0 Character length control 84 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 85 | Uint16 rsvd1:1; // 5 reserved 86 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 87 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 88 | Uint16 rsvd2:8; // 15:8 reserved 89 | }; 90 | 91 | union SPICCR_REG { 92 | Uint16 all; 93 | struct SPICCR_BITS bit; 94 | }; 95 | 96 | //------------------------------------------------- 97 | // SPI operation control register bit definitions: 98 | // 99 | // 100 | struct SPICTL_BITS { // bits description 101 | Uint16 SPIINTENA:1; // 0 Interrupt enable 102 | Uint16 TALK:1; // 1 Master/Slave transmit enable 103 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 104 | Uint16 CLK_PHASE:1; // 3 Clock phase select 105 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 106 | Uint16 rsvd:11; // 15:5 reserved 107 | }; 108 | 109 | union SPICTL_REG { 110 | Uint16 all; 111 | struct SPICTL_BITS bit; 112 | }; 113 | 114 | //-------------------------------------- 115 | // SPI status register bit definitions: 116 | // 117 | // 118 | struct SPISTS_BITS { // bits description 119 | Uint16 rsvd1:5; // 4:0 reserved 120 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 121 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 122 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 123 | Uint16 rsvd2:8; // 15:8 reserved 124 | }; 125 | 126 | union SPISTS_REG { 127 | Uint16 all; 128 | struct SPISTS_BITS bit; 129 | }; 130 | 131 | //------------------------------------------------ 132 | // SPI priority control register bit definitions: 133 | // 134 | // 135 | struct SPIPRI_BITS { // bits description 136 | Uint16 rsvd1:4; // 3:0 reserved 137 | Uint16 FREE:1; // 4 Free emulation mode control 138 | Uint16 SOFT:1; // 5 Soft emulation mode control 139 | Uint16 rsvd2:1; // 6 reserved 140 | Uint16 rsvd3:9; // 15:7 reserved 141 | }; 142 | 143 | union SPIPRI_REG { 144 | Uint16 all; 145 | struct SPIPRI_BITS bit; 146 | }; 147 | 148 | //--------------------------------------------------------------------------- 149 | // SPI Register File: 150 | // 151 | struct SPI_REGS { 152 | union SPICCR_REG SPICCR; // Configuration register 153 | union SPICTL_REG SPICTL; // Operation control register 154 | union SPISTS_REG SPISTS; // Status register 155 | Uint16 rsvd1; // reserved 156 | Uint16 SPIBRR; // Baud Rate 157 | Uint16 rsvd2; // reserved 158 | Uint16 SPIRXEMU; // Emulation buffer 159 | Uint16 SPIRXBUF; // Serial input buffer 160 | Uint16 SPITXBUF; // Serial output buffer 161 | Uint16 SPIDAT; // Serial data 162 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 163 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 164 | union SPIFFCT_REG SPIFFCT; // FIFO control register 165 | Uint16 rsvd3[2]; // reserved 166 | union SPIPRI_REG SPIPRI; // FIFO Priority control 167 | }; 168 | 169 | //--------------------------------------------------------------------------- 170 | // SPI External References & Function Declarations: 171 | // 172 | extern volatile struct SPI_REGS SpiaRegs; 173 | extern volatile struct SPI_REGS SpibRegs; 174 | extern volatile struct SPI_REGS SpicRegs; 175 | extern volatile struct SPI_REGS SpidRegs; 176 | 177 | #ifdef __cplusplus 178 | } 179 | #endif /* extern "C" */ 180 | 181 | #endif // end of DSP280x_SPI_H definition 182 | 183 | //=========================================================================== 184 | // End of file. 185 | //=========================================================================== 186 | 187 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_SysCtrl.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/4 $ 2 | // Checkin $Date: July 2, 2007 09:24:03 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_SysCtrl.h 6 | // 7 | // TITLE: DSP280x Device System Control Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_SYS_CTRL_H 15 | #define DSP280x_SYS_CTRL_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // System Control Individual Register Bit Definitions: 25 | // 26 | 27 | // XCLKOUT Control 28 | struct XCLK_BITS { // bits description 29 | Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Ratio 30 | Uint16 XCLKOUTDAT:1; // 2 reserved for TI use only 31 | Uint16 X1DAT:1; // 3 reserved for TI use only 32 | Uint16 XCLKINDAT:1; // 4 reserved for TI use only 33 | Uint16 rsvd1:3; // 7:5 reserved 34 | Uint16 X1CNT:4; // 11:8 reserved for TI use only 35 | Uint16 XCLKINCNT:4; // 15:12 reserved for TI use only 36 | }; 37 | 38 | union XCLK_REG { 39 | Uint16 all; 40 | struct XCLK_BITS bit; 41 | }; 42 | 43 | // PLL Status Register 44 | struct PLLSTS_BITS { // bits description 45 | Uint16 PLLLOCKS:1; // 0 PLL lock status 46 | Uint16 CLKINDIV:1; // 1 CLKIN div by 2 47 | Uint16 PLLOFF:1; // 2 PLL off bit 48 | Uint16 MCLKSTS:1; // 3 Missing clock status bit 49 | Uint16 MCLKCLR:1; // 4 Missing clock clear bit 50 | Uint16 OSCOFF:1; // 5 Oscillator clock off 51 | Uint16 MCLKOFF:1; // 6 Missing clock detect 52 | Uint16 rsvd2:9; // 15:7 reserved 53 | }; 54 | 55 | union PLLSTS_REG { 56 | Uint16 all; 57 | struct PLLSTS_BITS bit; 58 | }; 59 | 60 | // High speed peripheral clock register bit definitions: 61 | struct HISPCP_BITS { // bits description 62 | Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT 63 | Uint16 rsvd1:13; // 15:3 reserved 64 | }; 65 | 66 | union HISPCP_REG { 67 | Uint16 all; 68 | struct HISPCP_BITS bit; 69 | }; 70 | 71 | // Low speed peripheral clock register bit definitions: 72 | struct LOSPCP_BITS { // bits description 73 | Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT 74 | Uint16 rsvd1:13; // 15:3 reserved 75 | }; 76 | 77 | union LOSPCP_REG { 78 | Uint16 all; 79 | struct LOSPCP_BITS bit; 80 | }; 81 | 82 | // Peripheral clock control register 0 bit definitions: 83 | struct PCLKCR0_BITS { // bits description 84 | Uint16 rsvd1:2; // 1:0 reserved 85 | Uint16 TBCLKSYNC:1; // 2 EWPM Module TBCLK enable/sync 86 | Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC 87 | Uint16 I2CAENCLK:1; // 4 Enable SYSCLKOUT to I2C-A 88 | Uint16 rsvd2:1; // 5 reserved 89 | Uint16 SPICENCLK:1; // 6 Enable low speed clk to SPI-C 90 | Uint16 SPIDENCLK:1; // 7 Enable low speed clk to SPI-D 91 | Uint16 SPIAENCLK:1; // 8 Enable low speed clk to SPI-A 92 | Uint16 SPIBENCLK:1; // 9 Enable low speed clk to SPI-B 93 | Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A 94 | Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B 95 | Uint16 rsvd3:2; // 13:12 reserved 96 | Uint16 ECANAENCLK:1; // 14 Enable system clk to eCAN-A 97 | Uint16 ECANBENCLK:1; // 15 Enable system clk to eCAN-B 98 | }; 99 | 100 | union PCLKCR0_REG { 101 | Uint16 all; 102 | struct PCLKCR0_BITS bit; 103 | }; 104 | 105 | // Peripheral clock control register 1 bit definitions: 106 | struct PCLKCR1_BITS { // bits description 107 | Uint16 EPWM1ENCLK:1; // 0 Enable SYSCLKOUT to EPWM1 108 | Uint16 EPWM2ENCLK:1; // 1 Enable SYSCLKOUT to EPWM2 109 | Uint16 EPWM3ENCLK:1; // 2 Enable SYSCLKOUT to EPWM3 110 | Uint16 EPWM4ENCLK:1; // 3 Enable SYSCLKOUT to EPWM4 111 | Uint16 EPWM5ENCLK:1; // 4 Enable SYSCLKOUT to EPWM5 112 | Uint16 EPWM6ENCLK:1; // 5 Enable SYSCLKOUT to EPWM6 113 | Uint16 rsvd1:2; // 7:6 reserved 114 | Uint16 ECAP1ENCLK:1; // 8 Enable SYSCLKOUT to ECAP1 115 | Uint16 ECAP2ENCLK:1; // 9 Enable SYSCLKOUT to ECAP2 116 | Uint16 ECAP3ENCLK:1; // 10 Enable SYSCLKOUT to ECAP3 117 | Uint16 ECAP4ENCLK:1; // 11 Enable SYSCLKOUT to ECAP4 118 | Uint16 rsvd2:2; // 13:12 reserved 119 | Uint16 EQEP1ENCLK:1; // 11 Enable SYSCLKOUT to EQEP1 120 | Uint16 EQEP2ENCLK:1; // 11 Enable SYSCLKOUT to EQEP2 121 | }; 122 | 123 | union PCLKCR1_REG { 124 | Uint16 all; 125 | struct PCLKCR1_BITS bit; 126 | }; 127 | 128 | 129 | // PLL control register bit definitions: 130 | struct PLLCR_BITS { // bits description 131 | Uint16 DIV:4; // 3:0 Set clock ratio for the PLL 132 | Uint16 rsvd1:12; // 15:4 reserved 133 | }; 134 | 135 | union PLLCR_REG { 136 | Uint16 all; 137 | struct PLLCR_BITS bit; 138 | }; 139 | 140 | // Low Power Mode 0 control register bit definitions: 141 | struct LPMCR0_BITS { // bits description 142 | Uint16 LPM:2; // 1:0 Set the low power mode 143 | Uint16 QUALSTDBY:6; // 7:2 Qualification 144 | Uint16 rsvd1:7; // 14:8 reserved 145 | Uint16 WDINTE:1; // 15 Enables WD to wake the device from STANDBY 146 | }; 147 | 148 | union LPMCR0_REG { 149 | Uint16 all; 150 | struct LPMCR0_BITS bit; 151 | }; 152 | 153 | //--------------------------------------------------------------------------- 154 | // System Control Register File: 155 | // 156 | struct SYS_CTRL_REGS { 157 | union XCLK_REG XCLK; // 0 158 | union PLLSTS_REG PLLSTS; // 1 159 | Uint16 rsvd1[8]; // 2-9 160 | union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler 161 | union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler 162 | union PCLKCR0_REG PCLKCR0; // 12: Peripheral clock control register 163 | union PCLKCR1_REG PCLKCR1; // 13: Peripheral clock control register 164 | union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 165 | Uint16 rsvd2; // 15: reserved 166 | Uint16 rsvd3; // 16: reserved 167 | union PLLCR_REG PLLCR; // 17: PLL control register 168 | // No bit definitions are defined for SCSR because 169 | // a read-modify-write instruction can clear the WDOVERRIDE bit 170 | Uint16 SCSR; // 18: System control and status register 171 | Uint16 WDCNTR; // 19: WD counter register 172 | Uint16 rsvd4; // 20 173 | Uint16 WDKEY; // 21: WD reset key register 174 | Uint16 rsvd5[3]; // 22-24 175 | // No bit definitions are defined for WDCR because 176 | // the proper value must be written to the WDCHK field 177 | // whenever writing to this register. 178 | Uint16 WDCR; // 25: WD timer control register 179 | Uint16 rsvd6[6]; // 26-31 180 | }; 181 | 182 | 183 | /* --------------------------------------------------- */ 184 | /* CSM Registers */ 185 | /* */ 186 | /* ----------------------------------------------------*/ 187 | 188 | /* CSM Status & Control register bit definitions */ 189 | struct CSMSCR_BITS { // bit description 190 | Uint16 SECURE:1; // 0 Secure flag 191 | Uint16 rsvd1:14; // 14-1 reserved 192 | Uint16 FORCESEC:1; // 15 Force Secure control bit 193 | 194 | }; 195 | 196 | /* Allow access to the bit fields or entire register */ 197 | union CSMSCR_REG { 198 | Uint16 all; 199 | struct CSMSCR_BITS bit; 200 | }; 201 | 202 | /* CSM Register File */ 203 | struct CSM_REGS { 204 | Uint16 KEY0; // KEY reg bits 15-0 205 | Uint16 KEY1; // KEY reg bits 31-16 206 | Uint16 KEY2; // KEY reg bits 47-32 207 | Uint16 KEY3; // KEY reg bits 63-48 208 | Uint16 KEY4; // KEY reg bits 79-64 209 | Uint16 KEY5; // KEY reg bits 95-80 210 | Uint16 KEY6; // KEY reg bits 111-96 211 | Uint16 KEY7; // KEY reg bits 127-112 212 | Uint16 rsvd1; // reserved 213 | Uint16 rsvd2; // reserved 214 | Uint16 rsvd3; // reserved 215 | Uint16 rsvd4; // reserved 216 | Uint16 rsvd5; // reserved 217 | Uint16 rsvd6; // reserved 218 | Uint16 rsvd7; // reserved 219 | union CSMSCR_REG CSMSCR; // CSM Status & Control register 220 | }; 221 | 222 | /* Password locations */ 223 | struct CSM_PWL { 224 | Uint16 PSWD0; // PSWD bits 15-0 225 | Uint16 PSWD1; // PSWD bits 31-16 226 | Uint16 PSWD2; // PSWD bits 47-32 227 | Uint16 PSWD3; // PSWD bits 63-48 228 | Uint16 PSWD4; // PSWD bits 79-64 229 | Uint16 PSWD5; // PSWD bits 95-80 230 | Uint16 PSWD6; // PSWD bits 111-96 231 | Uint16 PSWD7; // PSWD bits 127-112 232 | }; 233 | 234 | 235 | 236 | /* Flash Registers */ 237 | 238 | #define FLASH_SLEEP 0x0000; 239 | #define FLASH_STANDBY 0x0001; 240 | #define FLASH_ACTIVE 0x0003; 241 | 242 | 243 | /* Flash Option Register bit definitions */ 244 | struct FOPT_BITS { // bit description 245 | Uint16 ENPIPE:1; // 0 Enable Pipeline Mode 246 | Uint16 rsvd:15; // 1-15 reserved 247 | }; 248 | 249 | /* Allow access to the bit fields or entire register */ 250 | union FOPT_REG { 251 | Uint16 all; 252 | struct FOPT_BITS bit; 253 | }; 254 | 255 | /* Flash Power Modes Register bit definitions */ 256 | struct FPWR_BITS { // bit description 257 | Uint16 PWR:2; // 0-1 Power Mode bits 258 | Uint16 rsvd:14; // 2-15 reserved 259 | }; 260 | 261 | /* Allow access to the bit fields or entire register */ 262 | union FPWR_REG { 263 | Uint16 all; 264 | struct FPWR_BITS bit; 265 | }; 266 | 267 | 268 | /* Flash Status Register bit definitions */ 269 | struct FSTATUS_BITS { // bit description 270 | Uint16 PWRS:2; // 0-1 Power Mode Status bits 271 | Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits 272 | Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits 273 | Uint16 rsvd1:4; // 4-7 reserved 274 | Uint16 V3STAT:1; // 8 VDD3V Status Latch bit 275 | Uint16 rsvd2:7; // 9-15 reserved 276 | }; 277 | 278 | /* Allow access to the bit fields or entire register */ 279 | union FSTATUS_REG { 280 | Uint16 all; 281 | struct FSTATUS_BITS bit; 282 | }; 283 | 284 | /* Flash Sleep to Standby Wait Counter Register bit definitions */ 285 | struct FSTDBYWAIT_BITS { // bit description 286 | Uint16 STDBYWAIT:9; // 0-8 Bank/Pump Sleep to Standby Wait Count bits 287 | Uint16 rsvd:7; // 9-15 reserved 288 | }; 289 | 290 | /* Allow access to the bit fields or entire register */ 291 | union FSTDBYWAIT_REG { 292 | Uint16 all; 293 | struct FSTDBYWAIT_BITS bit; 294 | }; 295 | 296 | /* Flash Standby to Active Wait Counter Register bit definitions */ 297 | struct FACTIVEWAIT_BITS { // bit description 298 | Uint16 ACTIVEWAIT:9; // 0-8 Bank/Pump Standby to Active Wait Count bits 299 | Uint16 rsvd:7; // 9-15 reserved 300 | }; 301 | 302 | /* Allow access to the bit fields or entire register */ 303 | union FACTIVEWAIT_REG { 304 | Uint16 all; 305 | struct FACTIVEWAIT_BITS bit; 306 | }; 307 | 308 | /* Bank Read Access Wait State Register bit definitions */ 309 | struct FBANKWAIT_BITS { // bit description 310 | Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits 311 | Uint16 rsvd1:4; // 4-7 reserved 312 | Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits 313 | Uint16 rsvd2:4; // 12-15 reserved 314 | }; 315 | 316 | /* Allow access to the bit fields or entire register */ 317 | union FBANKWAIT_REG { 318 | Uint16 all; 319 | struct FBANKWAIT_BITS bit; 320 | }; 321 | 322 | /* OTP Read Access Wait State Register bit definitions */ 323 | struct FOTPWAIT_BITS { // bit description 324 | Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits 325 | Uint16 rsvd:11; // 5-15 reserved 326 | }; 327 | 328 | /* Allow access to the bit fields or entire register */ 329 | union FOTPWAIT_REG { 330 | Uint16 all; 331 | struct FOTPWAIT_BITS bit; 332 | }; 333 | 334 | 335 | struct FLASH_REGS { 336 | union FOPT_REG FOPT; // Option Register 337 | Uint16 rsvd1; // reserved 338 | union FPWR_REG FPWR; // Power Modes Register 339 | union FSTATUS_REG FSTATUS; // Status Register 340 | union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register 341 | union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register 342 | union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register 343 | union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register 344 | }; 345 | 346 | //--------------------------------------------------------------------------- 347 | // System Control External References & Function Declarations: 348 | // 349 | extern volatile struct SYS_CTRL_REGS SysCtrlRegs; 350 | extern volatile struct CSM_REGS CsmRegs; 351 | extern volatile struct CSM_PWL CsmPwl; 352 | extern volatile struct FLASH_REGS FlashRegs; 353 | 354 | 355 | #ifdef __cplusplus 356 | } 357 | #endif /* extern "C" */ 358 | 359 | #endif // end of DSP280x_SYS_CTRL_H definition 360 | 361 | //=========================================================================== 362 | // End of file. 363 | //=========================================================================== 364 | 365 | -------------------------------------------------------------------------------- /2808_lib/inc/DSP280x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/1 $ 2 | // Checkin $Date: December 1, 2004 12:32:06 $ 3 | //########################################################################### 4 | // 5 | // FILE: DSP280x_XIntrupt.h 6 | // 7 | // TITLE: DSP280x Device External Interrupt Register Definitions. 8 | // 9 | //########################################################################### 10 | // $TI Release: DSP280x C/C++ Header Files V1.70 $ 11 | // $Release Date: July 27, 2009 $ 12 | //########################################################################### 13 | 14 | #ifndef DSP280x_XINTRUPT_H 15 | #define DSP280x_XINTRUPT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | 24 | struct XINTCR_BITS { 25 | Uint16 ENABLE:1; // 0 enable/disable 26 | Uint16 rsvd1:1; // 1 reserved 27 | Uint16 POLARITY:2; // 3:2 pos/neg, both triggered 28 | Uint16 rsvd2:12; //15:4 reserved 29 | }; 30 | 31 | union XINTCR_REG { 32 | Uint16 all; 33 | struct XINTCR_BITS bit; 34 | }; 35 | 36 | struct XNMICR_BITS { 37 | Uint16 ENABLE:1; // 0 enable/disable 38 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to INT13 39 | Uint16 POLARITY:2; // 3:2 pos/neg, or both triggered 40 | Uint16 rsvd2:12; // 15:4 reserved 41 | }; 42 | 43 | union XNMICR_REG { 44 | Uint16 all; 45 | struct XNMICR_BITS bit; 46 | }; 47 | 48 | 49 | 50 | 51 | //--------------------------------------------------------------------------- 52 | // External Interrupt Register File: 53 | // 54 | struct XINTRUPT_REGS { 55 | union XINTCR_REG XINT1CR; 56 | union XINTCR_REG XINT2CR; 57 | Uint16 rsvd1[5]; 58 | union XNMICR_REG XNMICR; 59 | Uint16 XINT1CTR; 60 | Uint16 XINT2CTR; 61 | Uint16 rsvd[5]; 62 | Uint16 XNMICTR; 63 | }; 64 | 65 | //--------------------------------------------------------------------------- 66 | // External Interrupt References & Function Declarations: 67 | // 68 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif /* extern "C" */ 73 | 74 | #endif // end of DSP280x_XINTF_H definition 75 | 76 | //=========================================================================== 77 | // End of file. 78 | //=========================================================================== 79 | 80 | -------------------------------------------------------------------------------- /2808_lib/inc/SFO.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: SFO.H 4 | // 5 | // TITLE: Scale Factor Optimizer Library Interface Header 6 | // 7 | // 8 | //########################################################################### 9 | // 10 | // Ver | dd mmm yyyy | Who | Description of changes 11 | // =====|=============|======|=============================================== 12 | // 0.01| 09 Jan 2004 | TI | New module 13 | //########################################################################### 14 | 15 | 16 | //============================================================================ 17 | // Description: This header provides the function call interface 18 | // for the scale factor optimizer for the 'F280x. 19 | //============================================================================ 20 | 21 | 22 | //============================================================================ 23 | // Multiple include Guard 24 | //============================================================================ 25 | #ifndef __4090522384024n8273240x3438jx43087401r34ru32r0___ 26 | #define __4090522384024n8273240x3438jx43087401r34ru32r0___ 27 | 28 | //============================================================================ 29 | // C++ namespace 30 | //============================================================================ 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | 36 | //============================================================================ 37 | // Function prototypes for MEP SFO 38 | //============================================================================ 39 | void SFO_MepEn(int nEpwmModule); 40 | void SFO_MepDis(int nEpwmModule); 41 | 42 | //============================================================================ 43 | // Multiple include Guard 44 | //============================================================================ 45 | #endif // End: Multiple include Guard 46 | 47 | //============================================================================ 48 | // C++ namespace 49 | //============================================================================ 50 | #ifdef __cplusplus 51 | } 52 | #endif /* extern "C" */ 53 | -------------------------------------------------------------------------------- /2808_lib/inc/SFO_V5.h: -------------------------------------------------------------------------------- 1 | 2 | //########################################################################### 3 | // 4 | // FILE: SFO_V5.H 5 | // 6 | // TITLE: Scale Factor Optimizer Library V5 Interface Header 7 | // 8 | // 9 | //########################################################################### 10 | // 11 | // Ver | dd mmm yyyy | Who | Description of changes 12 | // =====|=============|======|=============================================== 13 | // 0.01| 09 Jan 2004 | TI | New module 14 | // 0.02| 22 Jun 2007 | TI | New version (V5) with support for more channels 15 | //########################################################################### 16 | 17 | 18 | //============================================================================ 19 | // Description: This header provides the function call interface 20 | // for the scale factor optimizer V5. For more 21 | // information on the SFO function usage and 22 | // limitations, see the HRPWM Reference Guide 23 | // (spru924) on the TI website. 24 | //============================================================================ 25 | 26 | 27 | //============================================================================ 28 | // Multiple include Guard 29 | //============================================================================ 30 | #ifndef _SFO_V5_H 31 | #define _SFO_V5_H 32 | 33 | //============================================================================ 34 | // C++ namespace 35 | //============================================================================ 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | //============================================================================ 41 | // USER MUST UPDATE THIS CONSTANT FOR NUMBER OF HRPWM CHANNELS USED + 1 42 | //============================================================================ 43 | #define PWM_CH 5 // Equal # of HRPWM channels PLUS 1 44 | // i.e. PWM_CH is 5 for 4 channels, 4 for 3 channels, etc. 45 | //============================================================================ 46 | // Function prototypes for MEP SFO 47 | //============================================================================ 48 | 49 | int SFO_MepEn_V5(int nEpwmModule); // MEP-Enable V5 Calibration Function 50 | int SFO_MepDis_V5(int nEpwmModule); // MEP-Disable V5 Calibration Function 51 | 52 | //============================================================================ 53 | // Useful Defines when Using SFO Functions 54 | //============================================================================ 55 | #define SFO_INCOMPLETE 0 56 | #define SFO_COMPLETE 1 57 | #define SFO_OUTRANGE_ERROR 2 58 | 59 | //============================================================================ 60 | // Multiple include Guard 61 | //============================================================================ 62 | #endif // End: Multiple include Guard 63 | 64 | //============================================================================ 65 | // C++ namespace 66 | //============================================================================ 67 | #ifdef __cplusplus 68 | } 69 | #endif /* extern "C" */ 70 | -------------------------------------------------------------------------------- /2808_lib/inc/data.h: -------------------------------------------------------------------------------- 1 | #ifndef __DATA_H__ 2 | #define __DATA_H__ 3 | #define NULL 0 4 | #define __IO volatile /*!< Defines 'read / write' permissions */ 5 | //typedef unsigned short int u16; 6 | //typedef unsigned long int u32; 7 | //typedef unsigned char u8; 8 | //------------------------- 9 | typedef struct 10 | { 11 | unsigned char bit0 :1; 12 | unsigned char bit1 :1; 13 | unsigned char bit2 :1; 14 | unsigned char bit3 :1; 15 | unsigned char bit4 :1; 16 | unsigned char bit5 :1; 17 | unsigned char bit6 :1; 18 | unsigned char bit7 :1; 19 | } Bits_8s; 20 | typedef struct 21 | { 22 | unsigned char byte0 :4; 23 | unsigned char byte1 :4; 24 | } Byte_8s; 25 | typedef union 26 | { 27 | unsigned char all; 28 | Bits_8s bit; 29 | Byte_8s byte; 30 | } Char_8s; 31 | //------------------------ 32 | typedef struct 33 | { 34 | unsigned char bit0 :1; 35 | unsigned char bit1 :1; 36 | unsigned char bit2 :1; 37 | unsigned char bit3 :1; 38 | unsigned char bit4 :1; 39 | unsigned char bit5 :1; 40 | unsigned char bit6 :1; 41 | unsigned char bit7 :1; 42 | unsigned char bit8 :1; 43 | unsigned char bit9 :1; 44 | unsigned char bit10 :1; 45 | unsigned char bit11 :1; 46 | unsigned char bit12 :1; 47 | unsigned char bit13 :1; 48 | unsigned char bit14 :1; 49 | unsigned char bit15 :1; 50 | } Bits_16s; 51 | typedef struct 52 | { 53 | unsigned char byte0 :4; 54 | unsigned char byte1 :4; 55 | unsigned char byte3 :4; 56 | unsigned char byte4 :4; 57 | } Byte_16s; 58 | typedef union 59 | { 60 | unsigned short int all; 61 | Bits_16s bit; 62 | Byte_16s byte; 63 | } Uint_16s; 64 | //#define u8 unsigned char 65 | //#define u16 unsigned short int 66 | //#define u32 unsigned long int 67 | #endif 68 | -------------------------------------------------------------------------------- /2808_lib/lib/IQmath.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/TMS32F2808_Bootloader/a82685a34ccb07d1a4613b8aa18b84a508c202a9/2808_lib/lib/IQmath.lib -------------------------------------------------------------------------------- /2808_lib/src/F2808_V170.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/TMS32F2808_Bootloader/a82685a34ccb07d1a4613b8aa18b84a508c202a9/2808_lib/src/F2808_V170.lib -------------------------------------------------------------------------------- /BootLoader/inc/BootLoader.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:BootLoader.h 3 | *日期:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef BOOTLOADER_BOOTLOADER_H_ 7 | #define BOOTLOADER_BOOTLOADER_H_ 8 | #include "include.h" 9 | #include "data.h" 10 | #include "delay.h" 11 | #include "stdint.h" 12 | #include "CANA.h" 13 | #include "Flash.h" 14 | #define DATA_LEN 520 //缓存数组长度 15 | #define READ_MAX 256 //每次读取数据的最大长度,16位数据 16 | #define APP_INFO_ADDR ((uint32_t)0x3E8000) 17 | #define APP_START_ADDR ((uint32_t)0x3E8010) 18 | #define APP_Write_END_ADDR ((uint32_t)0x3F4000) 19 | #define APP_Write_START_ADDR ((uint32_t)0x3E8000) 20 | #define CAN_BL_APP 0xAAAAAA 21 | #define CAN_BL_BOOT 0x555555 22 | #define DEVICE_ADDR 0x12D//设备地址 23 | #define CMD_WIDTH 0x04 24 | #define ADDR_WIDTH 0x0C 25 | //----------------------以下宏定义是对芯片型号进行宏定义---------------------------- 26 | #define TMS320F28335 0x01 27 | #define TMS230F2808 0x02 28 | #define STM32F407IGT6 0x03 29 | //--------------------------------------------------------------------------------- 30 | //故障信息列表 31 | #define DEVICE_ADDR_ERROR 0xA0 //设备地址错误 32 | #define ERASE_ERROR 0xA1 //擦除错误 33 | #define WRITE_ERROR 0xA2 //写入数据错误 34 | #define READ_LEN_ERROR 0xA3 //读取数据长度错误 35 | #define MSG_DATA_LEN_ERROR 0xA4 //消息长度错误 36 | #define FILE_TYPE_ERROR 0xA5 //烧写文件类型错误 37 | #define CRC_ERROR 0xA6 //CRC校验错误 38 | #define FLASH_ADDR_ERROR 0xA7 //FALSH地址错误 39 | #define WRITE_LEN_ERROR 0xA8 //写入数据长度错误 40 | //--------------------------------------------------- 41 | //-----------烧写文件类型宏定义---------------------- 42 | /**************************************************** 43 | * 当前DSP芯片和STM32系列芯片支持bin文件和hex文件烧写,但是STM32芯片仅仅支持keil生成的hex文件,IAR测试有问题具体无法确认 44 | ****************************************************/ 45 | #define File_None 0xF0 //烧写文件类型未知 46 | #define File_bin 0xF1 //烧写文件为bin文件 47 | #define File_hex 0xF2 //烧写文件为hex文件, 48 | typedef void (*pFunction)(void); 49 | typedef struct _Device_INFO 50 | { 51 | union 52 | { 53 | unsigned short int all; 54 | struct 55 | { 56 | unsigned short int Device_addr :12; 57 | unsigned short int reserve :4; 58 | } bits; //设备地址 59 | } Device_addr; 60 | union 61 | { 62 | unsigned long int all; 63 | struct 64 | { 65 | unsigned long int FW_type :24; //固件类型 66 | unsigned long int Chip_Value :8; //控制器芯片类型 67 | } bits; 68 | } FW_TYPE; 69 | union 70 | { 71 | unsigned long int all; 72 | struct 73 | { 74 | unsigned long int Version :7; //固件版本 75 | unsigned long int date :5; //日期 76 | unsigned long int month :4; //月 77 | unsigned long int year :16; //年 78 | } bits; 79 | } FW_Version; //固件版本 80 | unsigned short int Sector_size;//FLASH扇区大小,仅仅针对DSP芯片有效, 81 | } Device_INFO; 82 | typedef struct _bootloader_data 83 | { 84 | union 85 | { 86 | u32 all; 87 | struct 88 | { 89 | u16 cmd :CMD_WIDTH; //命令 90 | u16 addr :ADDR_WIDTH; //设备地址 91 | u16 reserve :16; //保留位 92 | } bit; 93 | } ExtId; //扩展帧ID 94 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 95 | unsigned char DLC; //数据长度，可为0到8; 96 | u8 data[8]; 97 | } bootloader_data; 98 | typedef struct _Boot_CMD_LIST 99 | { 100 | //Bootloader相关命令 101 | unsigned char Read; //读取flash数据 102 | unsigned char Erase; //擦出APP储存扇区数据 103 | unsigned char Write; //以多字节形式写数据 104 | unsigned char Check; //检测节点是否在线，同时返回固件信息 105 | unsigned char Excute; //执行固件 106 | unsigned char WriteInfo; //设置多字节写数据相关参数（写起始地址，数据量） 107 | unsigned char SetBaudRate; //设置节点波特率 108 | //节点返回状态,关键 109 | unsigned char CmdFaild; //命令执行失败 110 | unsigned char CmdSuccess; //命令执行成功 111 | 112 | } Boot_CMD_LIST; 113 | extern Boot_CMD_LIST cmd_list; 114 | extern bootloader_data Bootloader_data; 115 | extern Device_INFO DEVICE_INFO; 116 | extern Uint16 app_check[2]; 117 | void __disable_irq(void); 118 | void __enable_irq(void); 119 | void __set_PRIMASK(u8 state); 120 | 121 | unsigned short int CRCcalc16(unsigned char *data, unsigned short int len); 122 | void CAN_BOOT_JumpToApplication(uint32_t Addr); 123 | void CAN_BOOT_ExecutiveCommand(CanRxMsg *pRxMessage); 124 | unsigned short int Check_APP(uint32_t Addr); 125 | #endif /* BOOTLOADER_BOOTLOADER_H_ */ 126 | -------------------------------------------------------------------------------- /F2808.cmd: -------------------------------------------------------------------------------- 1 | MEMORY 2 | { 3 | PAGE 0: /* Program Memory */ 4 | /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */ 5 | 6 | RAML0 : origin = 0x008000, length = 0x001000 /* on-chip RAM block L0 */ 7 | OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */ 8 | /* 9 | FLASHD : origin = 0x3E8000, length = 0x004000 10 | FLASHC : origin = 0x3EC000, length = 0x004000 11 | FLASHB : origin = 0x3F0000, length = 0x004000 12 | */ 13 | FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */ 14 | CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */ 15 | BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */ 16 | CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */ 17 | 18 | ROM : origin = 0x3FF000, length = 0x000FC0 /* Boot ROM */ 19 | RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */ 20 | VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */ 21 | 22 | PAGE 1 : /* Data Memory */ 23 | /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */ 24 | /* Registers remain on PAGE1 */ 25 | 26 | RAMM0 : origin = 0x000000, length = 0x000400 /* on-chip RAM block M0 */ 27 | BOOT_RSVD : origin = 0x000400, length = 0x000080 /* Part of M1, BOOT rom will use this for stack */ 28 | RAMM1 : origin = 0x000480, length = 0x000380 /* on-chip RAM block M1 */ 29 | RAML1 : origin = 0x009000, length = 0x001000 /* on-chip RAM block L1 */ 30 | RAMH0 : origin = 0x3FA000, length = 0x002000 /* on-chip RAM block H0 */ 31 | } 32 | 33 | /* Allocate sections to memory blocks. 34 | Note: 35 | codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code 36 | execution when booting to flash 37 | ramfuncs user defined section to store functions that will be copied from Flash into RAM 38 | */ 39 | 40 | SECTIONS 41 | { 42 | 43 | /* Allocate program areas: */ 44 | .cinit : > FLASHA PAGE = 0 45 | .pinit : > FLASHA, PAGE = 0 46 | .text : > FLASHA PAGE = 0 47 | codestart : > BEGIN PAGE = 0 48 | Flash28_API: 49 | { 50 | -l Flash2808_API_V302.lib(.econst) 51 | -l Flash2808_API_V302.lib(.text) 52 | } 53 | LOAD = FLASHA 54 | RUN = RAML0 55 | LOAD_START(_Flash28_API_LoadStart) 56 | LOAD_END (_Flash28_API_LoadEnd) 57 | RUN_START (_Flash28_API_RunStart) 58 | PAGE=0 59 | ramfuncs : LOAD = FLASHA, 60 | RUN = RAML0, 61 | LOAD_START(_RamfuncsLoadStart), 62 | LOAD_END(_RamfuncsLoadEnd), 63 | RUN_START(_RamfuncsRunStart), 64 | PAGE = 0 65 | 66 | csmpasswds : > CSM_PWL PAGE = 0 67 | csm_rsvd : > CSM_RSVD PAGE = 0 68 | 69 | /* Allocate uninitalized data sections: */ 70 | .stack : > RAMM0 PAGE = 1 71 | .ebss : > RAML1 PAGE = 1 72 | .esysmem : > RAMH0 PAGE = 1 73 | 74 | /* Initalized sections go in Flash */ 75 | /* For SDFlash to program these, they must be allocated to page 0 */ 76 | .econst : > FLASHA PAGE = 0 77 | .switch : > FLASHA PAGE = 0 78 | 79 | /* Allocate IQ math areas: */ 80 | IQmath : > FLASHA PAGE = 0 /* Math Code */ 81 | IQmathTables : > ROM PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */ 82 | 83 | /* .reset is a standard section used by the compiler. It contains the */ 84 | /* the address of the start of _c_int00 for C Code. /* 85 | /* When using the boot ROM this section and the CPU vector */ 86 | /* table is not needed. Thus the default type is set here to */ 87 | /* DSECT */ 88 | .reset : > RESET, PAGE = 0, TYPE = DSECT 89 | vectors : > VECTORS PAGE = 0, TYPE = DSECT 90 | 91 | } 92 | 93 | -------------------------------------------------------------------------------- /Flash2808_API_V302/Flash2808_API_V302.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/596142041/TMS32F2808_Bootloader/a82685a34ccb07d1a4613b8aa18b84a508c202a9/Flash2808_API_V302/Flash2808_API_V302.lib -------------------------------------------------------------------------------- /Flash2808_API_V302/Flash280x_API_Config.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/8 $ 2 | // Checkin $Date: December 13, 2005 08:47:30 $ 3 | //########################################################################### 4 | // 5 | // FILE: Flash280x_API_Config.h 6 | // 7 | // TITLE: F280x Flash Algo's - User Settings 8 | // 9 | // NOTE: This file contains user defined settings that 10 | // are used by the F280x Flash APIs. 11 | // 12 | //########################################################################### 13 | // $TI Release:$ 14 | // $Release Date:$ 15 | //########################################################################### 16 | 17 | #ifndef FLASH280X_API_CONFIG_H 18 | #define FLASH280X_API_CONFIG_H 19 | 20 | #ifdef __cplusplus 21 | extern "C" { 22 | #endif 23 | 24 | // Variables that can be configured by the user. 25 | 26 | /*----------------------------------------------------------------------------- 27 | 1. Specify the device. 28 | Define the device to be programmed as "1" (no quotes). 29 | Define all other devices as "0" (no quotes). 30 | -----------------------------------------------------------------------------*/ 31 | 32 | #define FLASH_F2808 1 33 | #define FLASH_F2806 0 34 | #define FLASH_F2802 0 35 | #define FLASH_F2801 0 36 | 37 | /*----------------------------------------------------------------------------- 38 | 2. Specify the clock rate of the CPU (SYSCLKOUT) in nS. 39 | 40 | Take into account the input clock frequency and the PLL multiplier 41 | that your application will use. 42 | 43 | Use one of the values provided, or define your own. 44 | The trailing L is required tells the compiler to treat 45 | the number as a 64-bit value. 46 | 47 | Only one statement should be uncommented. 48 | 49 | Example: CLKIN is a 20MHz crystal. 50 | 51 | If the application will set PLLCR = 0xA then the CPU clock 52 | will be 100Mhz (SYSCLKOUT = 100MHz). 53 | 54 | In this case, the CPU_RATE will be 10.000L 55 | Uncomment the line: #define CPU_RATE 10.000L 56 | -----------------------------------------------------------------------------*/ 57 | 58 | #define CPU_RATE 10.000L // for a 100MHz CPU clock speed (SYSCLKOUT) 59 | //#define CPU_RATE 13.330L // for a 75MHz CPU clock speed (SYSCLKOUT) 60 | //#define CPU_RATE 20.000L // for a 50MHz CPU clock speed (SYSCLKOUT) 61 | //#define CPU_RATE 33.333L // for a 30MHz CPU clock speed (SYSCLKOUT) 62 | //#define CPU_RATE 41.667L // for a 24MHz CPU clock speed (SYSCLKOUT) 63 | //#define CPU_RATE 50.000L // for a 20MHz CPU clock speed (SYSCLKOUT) 64 | //#define CPU_RATE 66.667L // for a 15MHz CPU clock speed (SYSCLKOUT) 65 | //#define CPU_RATE 100.000L // for a 10MHz CPU clock speed (SYSCLKOUT) 66 | 67 | //---------------------------------------------------------------------------- 68 | 69 | 70 | //----------------------------------------------------------------------------- 71 | // **** DO NOT modify the code below this line **** 72 | //----------------------------------------------------------------------------- 73 | #define SCALE_FACTOR 1048576.0L*( (200L/CPU_RATE) ) // IQ20 74 | 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif /* extern "C" */ 79 | 80 | #endif // -- end FLASH280X_API_CONFIG_H 81 | -------------------------------------------------------------------------------- /Flash2808_API_V302/Flash280x_API_Library.h: -------------------------------------------------------------------------------- 1 | // TI File $Revision: /main/11 $ 2 | // Checkin $Date: December 13, 2005 08:44:46 $ 3 | //########################################################################### 4 | // 5 | // FILE: Flash280x_API_Library.h 6 | // 7 | // TITLE: F280x Flash Algo's main include file 8 | // 9 | // DESCRIPTION: 10 | // 11 | // This file should be included in any project that uses any of the 12 | // the F280x flash APIs. 13 | // 14 | //########################################################################### 15 | // $TI Release:$ 16 | // $Release Date:$ 17 | //########################################################################### 18 | 19 | #ifndef FLASH280X_API_LIBRARY_H 20 | #define FLASH280X_API_LIBRARY_H 21 | 22 | #include "Flash280x_API_Config.h" 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | 29 | 30 | /*--------------------------------------------------------------------------- 31 | 28x Datatypes 32 | 33 | For Portability, User Is Recommended To Use Following Data Type Size 34 | Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 35 | ---------------------------------------------------------------------------*/ 36 | 37 | #ifndef DSP28_DATA_TYPES 38 | #define DSP28_DATA_TYPES 39 | typedef int int16; 40 | typedef long int32; 41 | typedef unsigned int Uint16; 42 | typedef unsigned long Uint32; 43 | typedef float float32; 44 | typedef long double float64; 45 | #endif 46 | 47 | /*--------------------------------------------------------------------------- 48 | API Status Messages 49 | 50 | The following status values are returned from the API to the calling 51 | program. These can be used to determine if the API function passed 52 | or failed. 53 | ---------------------------------------------------------------------------*/ 54 | // Operation passed, no errors were flagged 55 | #define STATUS_SUCCESS 0 56 | 57 | // The CSM is preventing the function from performing its operation 58 | #define STATUS_FAIL_CSM_LOCKED 10 59 | 60 | // Device REVID does not match that required by the API 61 | #define STATUS_FAIL_REVID_INVALID 11 62 | 63 | // Invalid address passed to the API 64 | #define STATUS_FAIL_ADDR_INVALID 12 65 | 66 | // Incorrect PARTID 67 | // For example the F2806 API was used on a F2808 device. 68 | #define STATUS_FAIL_INCORRECT_PARTID 13 69 | 70 | // API/Silicon missmatch. An old version of the 71 | // API is being used on silicon it is not valid for 72 | // Please update to the latest API. 73 | #define STATUS_FAIL_API_SILICON_MISMATCH 14 74 | 75 | // ---- Erase Specific errors ---- 76 | #define STATUS_FAIL_NO_SECTOR_SPECIFIED 20 77 | #define STATUS_FAIL_PRECONDITION 21 78 | #define STATUS_FAIL_ERASE 22 79 | #define STATUS_FAIL_COMPACT 23 80 | #define STATUS_FAIL_PRECOMPACT 24 81 | 82 | // ---- Program Specific errors ---- 83 | #define STATUS_FAIL_PROGRAM 30 84 | #define STATUS_FAIL_ZERO_BIT_ERROR 31 85 | 86 | // ---- Verify Specific errors ---- 87 | #define STATUS_FAIL_VERIFY 40 88 | 89 | // Busy is set by each API function before it determines 90 | // a pass or fail condition for that operation. 91 | // The calling function will will not receive this 92 | // status condition back from the API 93 | #define STATUS_BUSY 999 94 | 95 | /*--------------------------------------------------------------------------- 96 | Flash sector mask definitions 97 | 98 | The following macros can be used to form a mask specifying which sectors 99 | will be erased by the erase API function. 100 | 101 | Bit0 = Sector A 102 | Bit1 = Sector B 103 | Bit2 = Sector C 104 | Bit3 = Sector D 105 | ---------------------------------------------------------------------------*/ 106 | 107 | #define SECTORA (Uint16)0x0001 108 | #define SECTORB (Uint16)0x0002 109 | #define SECTORC (Uint16)0x0004 110 | #define SECTORD (Uint16)0x0008 111 | 112 | 113 | #if FLASH_F2808 114 | // All sectors on an F2808 - Sectors A - D 115 | #define SECTOR_F2808 (SECTORA|SECTORB|SECTORC|\ 116 | SECTORD) 117 | #endif // -- end FLASH_F2808 118 | 119 | #if FLASH_F2806 120 | // All sectors on an F2806 - Sectors A - D 121 | #define SECTOR_F2806 (SECTORA|SECTORB|SECTORC|\ 122 | SECTORD) 123 | #endif // -- end FLASH_F2806 124 | 125 | #if FLASH_F2802 126 | // All sectors on an F2802 - Sectors A - D 127 | #define SECTOR_F2802 (SECTORA|SECTORB|SECTORC|\ 128 | SECTORD) 129 | #endif // -- end FLASH_F2802 130 | 131 | #if FLASH_F2801 132 | // All sectors on an F2801 - Sectors A - D 133 | #define SECTOR_F2801 (SECTORA|SECTORB|SECTORC|\ 134 | SECTORD) 135 | #endif // -- end FLASH_F2801 136 | 137 | /*--------------------------------------------------------------------------- 138 | API Status Structure 139 | 140 | This structure is used to pass debug data back to the calling routine. 141 | Note that the Erase API function has 3 parts: precondition, erase and 142 | and compaction. Erase and compaction failures will not populate 143 | the expected and actual data fields. 144 | ---------------------------------------------------------------------------*/ 145 | 146 | typedef struct { 147 | Uint32 FirstFailAddr; 148 | Uint16 ExpectedData; 149 | Uint16 ActualData; 150 | }FLASH_ST; 151 | 152 | /*--------------------------------------------------------------------------- 153 | Interface Function prototypes 154 | 155 | For each 28x Flash API library, the function names are of the form: 156 | Flash_() 157 | 158 | Where is the device: ie 2808, 2806, 2801 159 | is the operation such as Erase, Program... 160 | 161 | For portability for users who may move between the F2808, F2806 and 162 | F2801, the following macro definitions are supplied. 163 | 164 | Using these macro definitions, the user can use instead make a generic 165 | call: Flash_ and the macro will map the call to the proper 166 | device function 167 | 168 | Note except for the toggle test function, all of the function prototypes 169 | are compatible with F281x devices as well. 170 | ---------------------------------------------------------------------------*/ 171 | 172 | #if FLASH_F2801 173 | #define Flash_Erase(a,b) Flash2801_Erase(a,b) 174 | #define Flash_Program(a,b,c,d) Flash2801_Program(a,b,c,d) 175 | #define Flash_Verify(a,b,c,d) Flash2801_Verify(a,b,c,d) 176 | #define Flash_ToggleTest(a,b) Flash2801_ToggleTest(a,b) 177 | #define Flash_DepRecover() Flash2801_DepRecover() 178 | #define Flash_APIVersionHex() Flash2801_APIVersionHex() 179 | #define Flash_APIVersion() Flash2801_APIVersion() 180 | 181 | #elif FLASH_F2802 182 | #define Flash_Erase(a,b) Flash2802_Erase(a,b) 183 | #define Flash_Program(a,b,c,d) Flash2802_Program(a,b,c,d) 184 | #define Flash_Verify(a,b,c,d) Flash2802_Verify(a,b,c,d) 185 | #define Flash_ToggleTest(a,b) Flash2802_ToggleTest(a,b) 186 | #define Flash_DepRecover() Flash2802_DepRecover() 187 | #define Flash_APIVersionHex() Flash2802_APIVersionHex() 188 | #define Flash_APIVersion() Flash2802_APIVersion() 189 | 190 | #elif FLASH_F2806 191 | #define Flash_Erase(a,b) Flash2806_Erase(a,b) 192 | #define Flash_Program(a,b,c,d) Flash2806_Program(a,b,c,d) 193 | #define Flash_Verify(a,b,c,d) Flash2806_Verify(a,b,c,d) 194 | #define Flash_ToggleTest(a,b) Flash2806_ToggleTest(a,b) 195 | #define Flash_DepRecover() Flash2806_DepRecover() 196 | #define Flash_APIVersionHex() Flash2806_APIVersionHex() 197 | #define Flash_APIVersion() Flash2806_APIVersion() 198 | 199 | #elif FLASH_F2808 200 | #define Flash_Erase(a,b) Flash2808_Erase(a,b) 201 | #define Flash_Program(a,b,c,d) Flash2808_Program(a,b,c,d) 202 | #define Flash_Verify(a,b,c,d) Flash2808_Verify(a,b,c,d) 203 | #define Flash_ToggleTest(a,b) Flash2808_ToggleTest(a,b) 204 | #define Flash_DepRecover() Flash2808_DepRecover() 205 | #define Flash_APIVersionHex() Flash2808_APIVersionHex() 206 | #define Flash_APIVersion() Flash2808_APIVersion() 207 | #endif 208 | 209 | extern Uint16 Flash_Erase(Uint16 SectorMask, FLASH_ST *FEraseStat); 210 | extern Uint16 Flash_Program(Uint16 *FlashAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FProgStatus); 211 | extern Uint16 Flash_Verify(Uint16 *StartAddr, Uint16 *BufAddr, Uint32 Length, FLASH_ST *FVerifyStat); 212 | extern void Flash_ToggleTest(volatile Uint32 *ToggleReg, Uint32 Mask); 213 | extern Uint16 Flash_DepRecover(); 214 | extern float32 Flash_APIVersion(); 215 | extern Uint16 Flash_APIVersionHex(); 216 | 217 | /*--------------------------------------------------------------------------- 218 | Frequency Scale factor: 219 | The calling program must provide this global parameter used 220 | for frequency scaling the algo's. 221 | ----------------------------------------------------------------------------*/ 222 | 223 | extern Uint32 Flash_CPUScaleFactor; 224 | 225 | /*--------------------------------------------------------------------------- 226 | Callback Function Pointer: 227 | A callback function can be specified. This function will be called 228 | at safe times during erase, program and verify. This function can 229 | then be used to service an external watchdog or send a communications 230 | packet. 231 | 232 | Note: 233 | THE FLASH AND OTP ARE NOT AVAILABLE DURING THIS FUNCTION CALL. 234 | THE FLASH/OTP CANNOT BE READ NOR CAN CODE EXECUTE FROM IT DURING THIS CALL 235 | DO NOT CALL ANY OF THE THE FLASH API FUNCTIONS DURING THIS CALL 236 | ----------------------------------------------------------------------------*/ 237 | extern void (*Flash_CallbackPtr) (void); 238 | 239 | /*--------------------------------------------------------------------------- 240 | API load/run symbols: 241 | These symbols are defined by the linker during the link. Refer to the 242 | Flash28_API section in the example .cmd file: 243 | 244 | Flash28_API: 245 | { 246 | Flash2808_API_Library.lib(.econst) 247 | Flash2808_API_Library.lib(.text) 248 | } LOAD = FLASH, 249 | RUN = SARAM, 250 | LOAD_START(_Flash28_API_LoadStart), 251 | LOAD_END(_Flash28_API_LoadEnd), 252 | RUN_START(_Flash28_API_RunStart), 253 | PAGE = 0 254 | 255 | These are used to copy the flash API from flash to SARAM 256 | 257 | ----------------------------------------------------------------------------*/ 258 | 259 | extern Uint16 Flash28_API_LoadStart; 260 | extern Uint16 Flash28_API_LoadEnd; 261 | extern Uint16 Flash28_API_RunStart; 262 | 263 | #ifdef __cplusplus 264 | } 265 | #endif /* extern "C" */ 266 | 267 | 268 | #endif // -- end FLASH2812_API_LIBRARY_H 269 | 270 | // --------- END OF FILE ---------------------------------- 271 | 272 | -------------------------------------------------------------------------------- /bsp/inc/CANA.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:CANA.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef BSP_INC_CANA_H_ 7 | #define BSP_INC_CANA_H_ 8 | #include "include.h" 9 | #include "data.h" 10 | #include "stdint.h" 11 | #define USE_CANA 1 12 | #define USE_CANB 0 13 | #define CAN_Id_Standard 0//表示标准帧 14 | #define CAN_Id_Extended 1//表示扩展帧 15 | #define CAN_ID_STD CAN_Id_Standard 16 | #define CAN_ID_EXT CAN_Id_Extended 17 | #define TXCOUNT 100 18 | typedef enum _CAN_Num 19 | { 20 | Null = 0, 21 | CANA = 1, 22 | CANB = 2, 23 | } CAN_Num; 24 | typedef enum _UPDATE_State 25 | { 26 | NON_CHANGE = 0, 27 | UPDATE = 1, 28 | } UPDATE_State; 29 | typedef union _SAE_ID 30 | { 31 | unsigned long int all; 32 | struct 33 | { 34 | unsigned short int SA :8; 35 | unsigned short int PS :8; 36 | unsigned short int PF :8; 37 | unsigned short int DP :1; 38 | unsigned short int R :1; 39 | unsigned short int Priority :3; 40 | unsigned short int resved :3; 41 | } bit; 42 | } SAE_ID; 43 | typedef struct _CAN_MSG_byte 44 | { 45 | unsigned char data[8]; 46 | } CAN_MSG_byte; 47 | typedef struct _CAN_MSG_BYTE 48 | { 49 | unsigned char byte0; 50 | unsigned char byte1; 51 | unsigned char byte2; 52 | unsigned char byte3; 53 | unsigned char byte4; 54 | unsigned char byte5; 55 | unsigned char byte6; 56 | unsigned char byte7; 57 | } CAN_MSG_BYTE; 58 | typedef union _CAN_MSG_DATA 59 | { 60 | CAN_MSG_byte msg_byte; 61 | CAN_MSG_BYTE msg_Byte; 62 | } CAN_MSG_DATA; 63 | typedef struct _CanTxMsg 64 | { 65 | union 66 | { 67 | unsigned short int all; 68 | struct 69 | { 70 | unsigned short int StdId :11; 71 | unsigned short int resved :5; 72 | } bit; 73 | } StdId; //标准帧ID 74 | union 75 | { 76 | unsigned long int all; 77 | struct 78 | { 79 | unsigned long int ExtId :29; 80 | unsigned long int resved :3; 81 | } bit; 82 | } ExtId; //扩展帧ID 83 | unsigned char SAE_J1939_Flag; //表示是否使用SAE J1939协议 84 | SAE_ID SAE_J1939_ID; 85 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 86 | unsigned char DLC; //数据长度，可为0到8; 87 | unsigned char MBox_num; //邮箱编号,0-31 88 | unsigned short int Tx_timeout_cnt; 89 | CAN_Num CAN_num; 90 | UPDATE_State tx_update; 91 | CAN_MSG_DATA CAN_Tx_msg_data; /*!< 帧消息内容,共8字节 */ 92 | 93 | } CanTxMsg; 94 | typedef struct _CanRxMsg 95 | { 96 | union 97 | { 98 | unsigned short int all; 99 | struct 100 | { 101 | unsigned short int StdId :11; 102 | unsigned short int resved :5; 103 | } bit; 104 | } StdId; ////标准帧ID,值为0x000到0x7FFF; 105 | union 106 | { 107 | unsigned long int all; 108 | struct 109 | { 110 | unsigned long int ExtId :29; 111 | unsigned long int resved :3; 112 | } bit; 113 | } ExtId; ////扩展帧ID,值为0到0x1FFFFFFF 114 | unsigned char SAE_J1939_Flag; //表示是否使用SAE J1939协议 115 | SAE_ID SAE_J1939_ID; 116 | unsigned char IDE; //帧类型,可为：CAN_ID_STD(标准帧),CAN_ID_EXT(扩展帧) 117 | unsigned char DLC; //数据长度，可为0到8; 118 | unsigned char MBox_num; //发送所用邮箱编号 119 | unsigned short int Rx_timeout_cnt; 120 | CAN_MSG_DATA CAN_Rx_msg_data; /*!< 帧消息内容,共8字节 */ 121 | CAN_Num CAN_num; 122 | UPDATE_State rx_update; 123 | } CanRxMsg; 124 | typedef struct _CANBus_Baudrate 125 | { 126 | Uint16 BRPREG: 8; // 23:16 Baudrate prescaler register value 127 | Uint16 TSEG2REG: 3; // 2:0 TSEG2 register value 128 | Uint16 TSEG1REG: 4; // 6:3 TSEG1 register value 129 | unsigned short int BaudRate; 130 | }CANBus_Baudrate; 131 | void CAN_GPIO_Config(CAN_Num CAN); 132 | void CAN_Config(CAN_Num CAN,unsigned short int BaudRate); 133 | void CAN_Tx_Msg(CanTxMsg *can_tx_msg); //发送消息 134 | void CAN_Rx_Msg(CanRxMsg *can_rx_msg); //接收消息 135 | #if USE_CANA 136 | static void CANA_RX_Config(void); 137 | #endif 138 | #if USE_CANB 139 | static void CANB_RX_Config(void); 140 | #endif 141 | void CAN_Rx_Config(void); 142 | void CAN_Rx_IT_Concig(void); 143 | int CAN_GetBaudRateNum(unsigned int BaudRate); 144 | __interrupt void Ecana_isr1(void); 145 | extern CanTxMsg can_tx_msg; 146 | extern CanRxMsg can_rx_msg; 147 | extern CANBus_Baudrate CANBus_Baudrate_table[27]; 148 | #endif /* BSP_INC_CANA_H_ */ 149 | -------------------------------------------------------------------------------- /bsp/inc/Flash.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:Flash.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef BSP_INC_FLASH_H_ 7 | #define BSP_INC_FLASH_H_ 8 | #include "include.h" 9 | #include "data.h" 10 | #include "delay.h" 11 | #include "stdint.h" 12 | #include "Flash280x_API_Library.h" 13 | void FlashAPI_Init(void); 14 | Uint16 Flash_RD(Uint32 addr, Uint16 *buffer, Uint16 leng); 15 | Uint16 Flash_WR(Uint32 addr, Uint16 *buffer, Uint16 leng); 16 | #endif /* BSP_INC_FLASH_H_ */ 17 | -------------------------------------------------------------------------------- /bsp/inc/LED.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:Led.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef BSP_INC_LED_H_ 7 | #define BSP_INC_LED_H_ 8 | #include "include.h" 9 | #include "data.h" 10 | #include "delay.h" 11 | #include "stdint.h" 12 | typedef struct _UPDATA_INFO 13 | { 14 | unsigned short int time_cnt; 15 | unsigned short int time_out_flag; 16 | }UPDATA_INFO; 17 | void LED_GPIO_Config(void); 18 | void LED_Timer_Config(void); 19 | extern UPDATA_INFO updata_info; 20 | interrupt void cpu_timer0_isr(void); 21 | 22 | #endif /* BSP_INC_LED_H_ */ 23 | -------------------------------------------------------------------------------- /bsp/inc/define.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:define.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef TMS320F2808_USER_INC_DEFINE_H_ 7 | #define TMS320F2808_USER_INC_DEFINE_H_ 8 | typedef unsigned short int u16; 9 | typedef unsigned long int u32; 10 | typedef unsigned char u8; 11 | #define TB_CLKDIV1 0x00 12 | #define TB_CLKDIV2 0x01 13 | #define TB_CLKDIV4 0x02 14 | #define TB_CLKDIV8 0x03 15 | #define TB_CLKDIV16 0x04 16 | #define TB_CLKDIV32 0x05 17 | #define TB_CLKDIV64 0x06 18 | #define TB_CLKDIV128 0x07 19 | //HSPCLKDIV and 20 | #define TB_HSPCLKDIV1 0x00 21 | #define TB_HSPCLKDIV2 0x01 22 | #define TB_HSPCLKDIV4 0x02 23 | #define TB_HSPCLKDIV6 0x03 24 | #define TB_HSPCLKDIV8 0x04 25 | #define TB_HSPCLKDIV10 0x05 26 | #define TB_HSPCLKDIV12 0x06 27 | #define TB_HSPCLKDIV14 0x07 28 | //GPIO 工作模式:输入/输出 29 | #define GPIO_Mode_IN 0 /*!< GPIO Input Mode */ 30 | #define GPIO_Mode_OUT 1 /*!< GPIO Output Mode */ 31 | //GPIO上拉电阻 32 | #define GPIO_PuPd_UP 0 33 | #define GPIO_PuPd_DOWN 0 34 | //GPIO的IO状态 35 | #define GPIO_SET 1 36 | #define GPIO_CLR 0 37 | #endif /* TMS320F2808_USER_INC_DEFINE_H_ */ 38 | -------------------------------------------------------------------------------- /bsp/inc/delay.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:delay.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | 7 | #ifndef USER_INC_DELAY_H_ 8 | #define USER_INC_DELAY_H_ 9 | #include "DSP280x_Device.h" // DSP280x Headerfile Include File 10 | #include "DSP280x_Examples.h" // DSP280x Examples Include File 11 | void delay_us(unsigned long int nus); 12 | void delay_ms(unsigned long int nms); 13 | void delay_s(unsigned long int ns); 14 | void delay(unsigned long int i); 15 | #endif /* USER_INC_DELAY_H_ */ 16 | -------------------------------------------------------------------------------- /bsp/inc/include.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:include.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | 7 | #ifndef TMS320F2808_USER_INC_INCLUDE_H_ 8 | #define TMS320F2808_USER_INC_INCLUDE_H_ 9 | #include "DSP280x_Device.h" // DSP280x Headerfile Include File 10 | #include "DSP280x_Examples.h" // DSP280x Examples Include File 11 | #include "IQmathLib.h" 12 | #include "define.h" 13 | #include "delay.h" 14 | typedef struct 15 | { 16 | u16 sys_time_cnt;//表示系统运行时间; 17 | u8 sys_state;//表示系统运行状态 18 | u16 ADC_sample_cnt; 19 | }Sys_Register; 20 | extern Sys_Register sys_reg; 21 | #endif /* TMS320F2808_USER_INC_INCLUDE_H_ */ 22 | -------------------------------------------------------------------------------- /bsp/src/CANA.c: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:CANA.c 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #include "CANA.h" 7 | #include "BootLoader.h" 8 | CANBus_Baudrate CANBus_Baudrate_table[27] = 9 | { 10 | #if CPU_FRQ_150MHZ 11 | {4,2,10,1000},//1000Kbps 12 | {9,2,5,750},//750Kbps 13 | {24,0,1,600},//600Kbps 14 | {9,2,10,500},//500Kbps 15 | {19,2,10,250},//250Kbps 16 | {24,2,10,200},//200Kbps 17 | #endif 18 | 19 | #if CPU_FRQ_100MHZ 20 | {9,1,6,1000},//1000Kbps 21 | {19,1,6,500},//500Kbps 22 | {39,1,6,250},//250Kbps 23 | {49,1,6,200},//200Kbps 24 | #endif 25 | 26 | }; 27 | CanRxMsg can_rx_msg = 28 | { 29 | .DLC = 8, 30 | .ExtId = 0x00, 31 | .CAN_num = CANA, 32 | .IDE = CAN_ID_EXT, 33 | .rx_update = NON_CHANGE, 34 | }; 35 | int CAN_GetBaudRateNum(unsigned int BaudRate) 36 | { 37 | int i =0; 38 | for( i=0;i<27;i++) 39 | { 40 | if(BaudRate == CANBus_Baudrate_table[i].BaudRate) 41 | { 42 | return i; 43 | } 44 | } 45 | return 0; 46 | } 47 | void CAN_GPIO_Config(CAN_Num CAN) 48 | { 49 | 50 | if (CAN == CANA) 51 | { 52 | #if DSP28_2808 ||DSP28_2809 53 | EALLOW; 54 | GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA) 55 | GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA) 56 | GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3; // Asynch qual for GPIO30 (CANRXA) 57 | GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANTXA operation 58 | GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANRXA operation 59 | EDIS; 60 | #endif 61 | 62 | } 63 | else if (CAN == CANB) 64 | { 65 | #if DSP28_2808 ||DSP28_2809 66 | EALLOW; 67 | GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0; // Enable pull-up for GPIO8 (CANTXB) 68 | GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0; // Enable pull-up for GPIO10 (CANRXB) 69 | GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB) 70 | GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2; // Configure GPIO8 for CANTXB operation 71 | GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2; // Configure GPIO10 for CANRXB operation 72 | EDIS; 73 | #endif 74 | } 75 | else 76 | { 77 | return; 78 | } 79 | 80 | } 81 | void CAN_Config(CAN_Num CAN,unsigned short int BaudRate) 82 | { 83 | struct ECAN_REGS ECan_Reg_Shadow; 84 | //------------------------- 85 | volatile struct ECAN_REGS *ECanReg; 86 | volatile struct ECAN_MBOXES *ECanMboxe; 87 | if (CAN == CANA) 88 | { 89 | EALLOW; 90 | SysCtrlRegs.PCLKCR0.bit.ECANAENCLK = 1; 91 | EDIS; 92 | ECanReg = &ECanaRegs; 93 | ECanMboxe = &ECanaMboxes; 94 | } 95 | else if (CAN == CANB) 96 | { 97 | EALLOW; 98 | SysCtrlRegs.PCLKCR0.bit.ECANBENCLK = 1; 99 | EDIS; 100 | ECanReg = &ECanbRegs; 101 | ECanMboxe = &ECanbMboxes; 102 | } 103 | else 104 | { 105 | return; 106 | } 107 | 108 | EALLOW; // EALLOW enables access to protected bits 109 | /* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/ 110 | ECan_Reg_Shadow.CANTIOC.all = ECanReg->CANTIOC.all; 111 | ECan_Reg_Shadow.CANTIOC.bit.TXFUNC = 1; 112 | ECanReg->CANTIOC.all = ECan_Reg_Shadow.CANTIOC.all; 113 | ECan_Reg_Shadow.CANRIOC.all = ECanReg->CANRIOC.all; 114 | ECan_Reg_Shadow.CANRIOC.bit.RXFUNC = 1; 115 | ECanReg->CANRIOC.all = ECan_Reg_Shadow.CANRIOC.all; 116 | /* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */ 117 | // HECC mode also enables time-stamping feature 118 | //选择CAN工作模式工作于eCAN模式,32个邮箱都工作。 119 | ECan_Reg_Shadow.CANMC.all = ECanReg->CANMC.all; 120 | ECan_Reg_Shadow.CANMC.bit.SCB = 1; 121 | ECanReg->CANMC.all = ECan_Reg_Shadow.CANMC.all; 122 | ECanMboxe->MBOX0.MSGCTRL.all = 0x00000000; 123 | ECanMboxe->MBOX1.MSGCTRL.all = 0x00000000; 124 | ECanMboxe->MBOX2.MSGCTRL.all = 0x00000000; 125 | ECanMboxe->MBOX3.MSGCTRL.all = 0x00000000; 126 | ECanMboxe->MBOX4.MSGCTRL.all = 0x00000000; 127 | ECanMboxe->MBOX5.MSGCTRL.all = 0x00000000; 128 | ECanMboxe->MBOX6.MSGCTRL.all = 0x00000000; 129 | ECanMboxe->MBOX7.MSGCTRL.all = 0x00000000; 130 | ECanMboxe->MBOX8.MSGCTRL.all = 0x00000000; 131 | ECanMboxe->MBOX9.MSGCTRL.all = 0x00000000; 132 | ECanMboxe->MBOX10.MSGCTRL.all = 0x00000000; 133 | ECanMboxe->MBOX11.MSGCTRL.all = 0x00000000; 134 | ECanMboxe->MBOX12.MSGCTRL.all = 0x00000000; 135 | ECanMboxe->MBOX13.MSGCTRL.all = 0x00000000; 136 | ECanMboxe->MBOX14.MSGCTRL.all = 0x00000000; 137 | ECanMboxe->MBOX15.MSGCTRL.all = 0x00000000; 138 | ECanMboxe->MBOX16.MSGCTRL.all = 0x00000000; 139 | ECanMboxe->MBOX17.MSGCTRL.all = 0x00000000; 140 | ECanMboxe->MBOX18.MSGCTRL.all = 0x00000000; 141 | ECanMboxe->MBOX19.MSGCTRL.all = 0x00000000; 142 | ECanMboxe->MBOX20.MSGCTRL.all = 0x00000000; 143 | ECanMboxe->MBOX21.MSGCTRL.all = 0x00000000; 144 | ECanMboxe->MBOX22.MSGCTRL.all = 0x00000000; 145 | ECanMboxe->MBOX23.MSGCTRL.all = 0x00000000; 146 | ECanMboxe->MBOX24.MSGCTRL.all = 0x00000000; 147 | ECanMboxe->MBOX25.MSGCTRL.all = 0x00000000; 148 | ECanMboxe->MBOX26.MSGCTRL.all = 0x00000000; 149 | ECanMboxe->MBOX27.MSGCTRL.all = 0x00000000; 150 | ECanMboxe->MBOX28.MSGCTRL.all = 0x00000000; 151 | ECanMboxe->MBOX29.MSGCTRL.all = 0x00000000; 152 | ECanMboxe->MBOX30.MSGCTRL.all = 0x00000000; 153 | ECanMboxe->MBOX31.MSGCTRL.all = 0x00000000; 154 | 155 | // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again 156 | // as a matter of precaution. 157 | /* Clear all TAn bits */ 158 | ECanReg->CANTA.all = 0xFFFFFFFF; 159 | /* Clear all RMPn bits */ 160 | ECanReg->CANRMP.all = 0xFFFFFFFF; 161 | /* Clear all interrupt flag bits */ 162 | ECanReg->CANGIF0.all = 0xFFFFFFFF; 163 | ECanReg->CANGIF1.all = 0xFFFFFFFF; 164 | 165 | /* Configure bit timing parameters for eCANA*/ 166 | //开始配置CAN总线波特率 167 | ECan_Reg_Shadow.CANMC.all = ECanReg->CANMC.all; 168 | ECan_Reg_Shadow.CANMC.bit.CCR = 1; // Set CCR = 1 169 | ECanReg->CANMC.all = ECan_Reg_Shadow.CANMC.all; 170 | ECan_Reg_Shadow.CANES.all = ECanReg->CANES.all; 171 | do 172 | { 173 | ECan_Reg_Shadow.CANES.all = ECanReg->CANES.all; 174 | } 175 | while (ECan_Reg_Shadow.CANES.bit.CCE != 1); // Wait for CCE bit to be set.. 176 | ECan_Reg_Shadow.CANBTC.all = 0; 177 | ECan_Reg_Shadow.CANBTC.bit.BRPREG = CANBus_Baudrate_table[CAN_GetBaudRateNum(BaudRate)].BRPREG; 178 | ECan_Reg_Shadow.CANBTC.bit.TSEG2REG = CANBus_Baudrate_table[CAN_GetBaudRateNum(BaudRate)].TSEG2REG; 179 | ECan_Reg_Shadow.CANBTC.bit.TSEG1REG = CANBus_Baudrate_table[CAN_GetBaudRateNum(BaudRate)].TSEG1REG; 180 | 181 | ECan_Reg_Shadow.CANBTC.bit.SAM = 1; 182 | ECanReg->CANBTC.all = ECan_Reg_Shadow.CANBTC.all; 183 | ECan_Reg_Shadow.CANMC.all = ECanReg->CANMC.all; 184 | ECan_Reg_Shadow.CANMC.bit.CCR = 0; // Set CCR = 0 185 | ECanReg->CANMC.all = ECan_Reg_Shadow.CANMC.all; 186 | ECan_Reg_Shadow.CANES.all = ECanReg->CANES.all; 187 | do 188 | { 189 | ECan_Reg_Shadow.CANES.all = ECanReg->CANES.all; 190 | } 191 | while (ECan_Reg_Shadow.CANES.bit.CCE != 0); // Wait for CCE bit to be cleared.. 192 | /* Disable all Mailboxes */ 193 | ECanReg->CANME.all = 0; // Required before writing the MSGIDs 194 | EDIS; 195 | 196 | } 197 | void CAN_Tx_Msg(CanTxMsg *can_tx_msg) //发送消息 198 | { 199 | Uint32 mbox_enable_temp = 0x0000; 200 | Uint32 mbox_disable_temp = 0x0000; 201 | Uint32 mbox_dir_temp = 0x0000; 202 | mbox_enable_temp = 1<<(can_tx_msg->MBox_num); 203 | mbox_disable_temp = ~(1<<(can_tx_msg->MBox_num)); 204 | mbox_dir_temp = ~(1<<(can_tx_msg->MBox_num)); 205 | volatile struct ECAN_REGS ECan_Reg_Shadow; 206 | volatile struct ECAN_REGS *ECanReg; 207 | volatile struct MBOX *Mailbox; 208 | if(can_tx_msg->CAN_num == CANA) 209 | { 210 | ECanReg = &ECanaRegs; 211 | Mailbox = &ECanaMboxes.MBOX0+can_tx_msg->MBox_num; 212 | } 213 | else if (can_tx_msg->CAN_num == CANB) 214 | { 215 | ECanReg = &ECanbRegs; 216 | Mailbox = &ECanbMboxes.MBOX0+can_tx_msg->MBox_num; 217 | } 218 | else 219 | { 220 | return; 221 | } 222 | ECan_Reg_Shadow.CANME.all = ECanReg->CANME.all; 223 | ECan_Reg_Shadow.CANME.all &= mbox_disable_temp; 224 | ECanReg->CANME.all = ECan_Reg_Shadow.CANME.all; 225 | if(can_tx_msg->IDE == CAN_ID_STD) 226 | { 227 | 228 | Mailbox->MSGID.all = can_tx_msg->StdId.bit.StdId; //standard identifier 229 | Mailbox->MSGID.bit.IDE = can_tx_msg->IDE; 230 | } 231 | else if(can_tx_msg->IDE == CAN_ID_EXT) 232 | { 233 | if(can_tx_msg->SAE_J1939_Flag == 0) 234 | { 235 | Mailbox->MSGID.all = can_tx_msg->ExtId.bit.ExtId; //extended identifier. 236 | Mailbox->MSGID.bit.IDE = can_tx_msg->IDE; 237 | } 238 | else 239 | { 240 | Mailbox->MSGID.all = can_tx_msg->SAE_J1939_ID.all; //extended identifier. 241 | Mailbox->MSGID.bit.IDE = can_tx_msg->IDE; 242 | } 243 | } 244 | ECan_Reg_Shadow.CANMD.all = ECanReg->CANMD.all; 245 | ECan_Reg_Shadow.CANMD.all &=mbox_dir_temp;//设置邮箱工作方向,0表示邮箱工作于发送,1表示工作于接收 246 | ECanReg->CANMD.all = ECan_Reg_Shadow.CANMD.all; 247 | ECan_Reg_Shadow.CANME.all = ECanReg->CANME.all; 248 | ECan_Reg_Shadow.CANME.all |= mbox_enable_temp;//使能邮箱 249 | ECanReg->CANME.all = ECan_Reg_Shadow.CANME.all; 250 | Mailbox->MSGCTRL.bit.DLC = can_tx_msg->DLC;//数据长度 251 | Mailbox->MDL.byte.BYTE0 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte0; 252 | Mailbox->MDL.byte.BYTE1 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte1; 253 | Mailbox->MDL.byte.BYTE2 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte2; 254 | Mailbox->MDL.byte.BYTE3 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte3; 255 | Mailbox->MDH.byte.BYTE4 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte4; 256 | Mailbox->MDH.byte.BYTE5 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte5; 257 | Mailbox->MDH.byte.BYTE6 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte6; 258 | Mailbox->MDH.byte.BYTE7 = can_tx_msg->CAN_Tx_msg_data.msg_Byte.byte7; 259 | ECan_Reg_Shadow.CANTRS.all = 0; 260 | ECan_Reg_Shadow.CANTRS.all |= mbox_enable_temp; // Set TRS for mailbox under test 261 | ECanReg->CANTRS.all = ECan_Reg_Shadow.CANTRS.all; 262 | do 263 | { 264 | ECan_Reg_Shadow.CANTA.all = ECanReg->CANTA.all; 265 | 266 | } while(((ECan_Reg_Shadow.CANTA.all&mbox_enable_temp) == 0 )); 267 | ECan_Reg_Shadow.CANTA.all = 0; 268 | ECan_Reg_Shadow.CANTA.all = mbox_enable_temp; 269 | ECanReg->CANTA.all = ECan_Reg_Shadow.CANTA.all; 270 | } 271 | void CAN_Rx_Msg(CanRxMsg *can_rx_msg) //接收消息 272 | { 273 | // struct ECAN_REGS ECan_Reg_Shadow; 274 | volatile struct MBOX *Mailbox; 275 | if(can_rx_msg->CAN_num == CANA) 276 | { 277 | Mailbox = &ECanaMboxes.MBOX0+can_rx_msg->MBox_num; 278 | } 279 | else if (can_rx_msg->CAN_num == CANB) 280 | { 281 | Mailbox =&ECanbMboxes.MBOX0+can_rx_msg->MBox_num; 282 | } 283 | else 284 | { 285 | return; 286 | } 287 | can_rx_msg->DLC = Mailbox->MSGCTRL.bit.DLC; 288 | can_rx_msg->IDE = Mailbox->MSGID.bit.IDE; 289 | if(can_rx_msg->IDE == CAN_ID_EXT) 290 | { 291 | can_rx_msg->ExtId.bit.ExtId = Mailbox->MSGID.all&0x1FFFFFFF; 292 | can_rx_msg->SAE_J1939_ID.all = can_rx_msg->ExtId.bit.ExtId; 293 | } 294 | else if(can_rx_msg->IDE == CAN_ID_STD) 295 | { 296 | can_rx_msg->StdId.bit.StdId = Mailbox->MSGID.bit.STDMSGID; 297 | } 298 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte0 = Mailbox->MDL.byte.BYTE0; 299 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte1 = Mailbox->MDL.byte.BYTE1; 300 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte2 = Mailbox->MDL.byte.BYTE2; 301 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte3 = Mailbox->MDL.byte.BYTE3; 302 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte4 = Mailbox->MDH.byte.BYTE4; 303 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte5 = Mailbox->MDH.byte.BYTE5; 304 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte6 = Mailbox->MDH.byte.BYTE6; 305 | can_rx_msg->CAN_Rx_msg_data.msg_Byte.byte7 = Mailbox->MDH.byte.BYTE7; 306 | } 307 | #if USE_CANA 308 | /* 309 | * 将邮箱31配置为接收邮箱, 310 | */ 311 | static void CANA_RX_Config(void) 312 | { 313 | struct ECAN_REGS ECan_Reg_Shadow; 314 | ECan_Reg_Shadow.CANME.all = ECanaRegs.CANME.all; 315 | ECan_Reg_Shadow.CANME.bit.ME31 = 0;//不使能邮箱31 316 | ECanaRegs.CANME.all = ECan_Reg_Shadow.CANME.all; 317 | /*----------以下代码是配置接受邮箱的相关代码------------*/ 318 | //邮箱31相关配置 319 | ECanaMboxes.MBOX31.MSGCTRL.bit.DLC = 8;//配置数据长度，应该是没意义的; 320 | ECanaMboxes.MBOX31.MSGID.all = DEVICE_ADDR<<4;//设置接收消息的有效ID 321 | ECanaMboxes.MBOX31.MSGID.bit.AME =1;//屏蔽使能位, 322 | ECanaMboxes.MBOX31.MSGID.bit.IDE = CAN_ID_EXT; 323 | /* 324 | LAM[28:0] 325 | 这些位启用一个进入消息的任意标识符位的屏蔽。 326 | 1 针对接受到的标识符的相应位，接受一个 0 或 1（无关）。 327 | 0 接收到的标识符位值必须与 MSGID 寄存器的相应标识符位相匹配。 328 | */ 329 | 330 | ECanaLAMRegs.LAM31.all = 0x000000F;// 331 | /* 332 | LAMI 本地接受屏蔽标识符扩展位 333 | 1 可以接收标准和扩展帧。在扩展帧的情况下，标识符的所有 29 位被存储在邮箱中，本地接受屏蔽寄 334 | 存器的所有 29 位被过滤器使用。在一个标准帧的情况下，只有标识符的头 11 个位（ 28 至 18 位） 335 | 和本地接受屏蔽被使用。 336 | 0 存储在邮箱中的标识符扩展位决定了哪些消息应该被接收到 337 | */ 338 | ECanaLAMRegs.LAM31.bit.LAMI = 1; 339 | ECanaRegs.CANRMP.all = 0xFFFFFFFF; 340 | ECan_Reg_Shadow.CANMD.all = ECanaRegs.CANMD.all; 341 | //ECan_Reg_Shadow.CANMD.bit.MD1 = 1; 342 | ECan_Reg_Shadow.CANMD.bit.MD31 = 1; 343 | ECanaRegs.CANMD.all = ECan_Reg_Shadow.CANMD.all; 344 | 345 | ECan_Reg_Shadow.CANME.all = ECanaRegs.CANME.all; 346 | //ECan_Reg_Shadow.CANME.bit.ME1 = 1;//使能邮箱1 347 | ECan_Reg_Shadow.CANME.bit.ME31 = 1;//使能邮箱1 348 | ECanaRegs.CANME.all = ECan_Reg_Shadow.CANME.all; 349 | } 350 | #endif 351 | #if USE_CANB 352 | static void CANB_RX_Config(void) 353 | { 354 | struct ECAN_REGS ECan_Reg_Shadow; 355 | ECan_Reg_Shadow.CANME.all = ECanbRegs.CANME.all; 356 | ECan_Reg_Shadow.CANME.bit.ME1 = 0;//不使能邮箱1 357 | ECan_Reg_Shadow.CANME.bit.ME31 = 0;//不使能邮箱31 358 | ECanbRegs.CANME.all = ECan_Reg_Shadow.CANME.all; 359 | /*----------以下代码是配置接受邮箱的相关代码------------*/ 360 | //邮箱1相关配置 361 | ECanbMboxes.MBOX1.MSGCTRL.bit.DLC = 8;//配置数据长度，应该是没意义的; 362 | ECanbMboxes.MBOX1.MSGID.all = 0x1200;//设置接收消息的有效ID 363 | ECanbMboxes.MBOX1.MSGID.bit.AME =1;//屏蔽使能位, 364 | ECanbMboxes.MBOX1.MSGID.bit.IDE = CAN_ID_EXT; 365 | /* 366 | LAM[28:0] 367 | 这些位启用一个进入消息的任意标识符位的屏蔽。 368 | 1 针对接受到的标识符的相应位，接受一个 0 或 1（无关）。 369 | 0 接收到的标识符位值必须与 MSGID 寄存器的相应标识符位相匹配。 370 | */ 371 | 372 | ECanbLAMRegs.LAM1.all = 0x000000F;// 373 | /* 374 | LAMI 本地接受屏蔽标识符扩展位 375 | 1 可以接收标准和扩展帧。在扩展帧的情况下，标识符的所有 29 位被存储在邮箱中，本地接受屏蔽寄 376 | 存器的所有 29 位被过滤器使用。在一个标准帧的情况下，只有标识符的头 11 个位（ 28 至 18 位） 377 | 和本地接受屏蔽被使用。 378 | 0 存储在邮箱中的标识符扩展位决定了哪些消息应该被接收到 379 | */ 380 | ECanbLAMRegs.LAM1.bit.LAMI = 1; 381 | //邮箱31相关配置 382 | ECanbMboxes.MBOX31.MSGCTRL.bit.DLC = 8;//配置数据长度，应该是没意义的; 383 | ECanbMboxes.MBOX31.MSGID.all = 0x07909ABC;//设置接收消息的有效ID 384 | ECanbMboxes.MBOX31.MSGID.bit.AME =1;//屏蔽使能位, 385 | ECanbMboxes.MBOX31.MSGID.bit.IDE = CAN_ID_EXT; 386 | /* 387 | LAM[28:0] 388 | 这些位启用一个进入消息的任意标识符位的屏蔽。 389 | 1 针对接受到的标识符的相应位，接受一个 0 或 1（无关）。 390 | 0 接收到的标识符位值必须与 MSGID 寄存器的相应标识符位相匹配。 391 | */ 392 | 393 | ECanbLAMRegs.LAM31.all = 0x0000000;// 394 | /* 395 | LAMI 本地接受屏蔽标识符扩展位 396 | 1 可以接收标准和扩展帧。在扩展帧的情况下，标识符的所有 29 位被存储在邮箱中，本地接受屏蔽寄 397 | 存器的所有 29 位被过滤器使用。在一个标准帧的情况下，只有标识符的头 11 个位（ 28 至 18 位） 398 | 和本地接受屏蔽被使用。 399 | 0 存储在邮箱中的标识符扩展位决定了哪些消息应该被接收到 400 | */ 401 | ECanbLAMRegs.LAM31.bit.LAMI = 1; 402 | ECanbRegs.CANRMP.all = 0xFFFFFFFF; 403 | ECan_Reg_Shadow.CANMD.all = ECanbRegs.CANMD.all; 404 | ECan_Reg_Shadow.CANMD.bit.MD1 = 1; 405 | ECan_Reg_Shadow.CANMD.bit.MD31 = 1; 406 | ECanbRegs.CANMD.all = ECan_Reg_Shadow.CANMD.all; 407 | 408 | ECan_Reg_Shadow.CANME.all = ECanbRegs.CANME.all; 409 | ECan_Reg_Shadow.CANME.bit.ME1 = 1;//使能邮箱1 410 | ECan_Reg_Shadow.CANME.bit.ME31 = 1;//使能邮箱1 411 | ECanbRegs.CANME.all = ECan_Reg_Shadow.CANME.all; 412 | } 413 | #endif 414 | void CAN_Rx_Config(void) 415 | { 416 | #if USE_CANA 417 | CANA_RX_Config(); 418 | #endif 419 | /*---------------------------------*/ 420 | #if USE_CANB 421 | CANB_RX_Config(); 422 | #endif 423 | } 424 | void CAN_Rx_IT_Concig(void) 425 | { 426 | EALLOW; 427 | ECanaRegs.CANMIM.bit.MIM31 = 1;//使能中断邮箱31的中断; 428 | ECanaRegs.CANMIL.bit.MIL31 = 1;//将中断31连接至中断1; 429 | ECanaRegs.CANGIM.bit.I1EN = 1;//使能中断1; 430 | EDIS; 431 | } 432 | __interrupt void Ecana_isr1(void) 433 | { 434 | if(ECanaRegs.CANGIF1.bit.GMIF1 == 1) 435 | { 436 | if(ECanaRegs.CANRMP.bit.RMP31 == 1) 437 | { 438 | can_rx_msg.rx_update = UPDATE; 439 | can_rx_msg.MBox_num = ECanaRegs.CANGIF1.bit.MIV1; 440 | can_rx_msg.DLC = ECanaMboxes.MBOX31.MSGCTRL.bit.DLC; 441 | can_rx_msg.IDE = ECanaMboxes.MBOX31.MSGID.bit.IDE; 442 | if(can_rx_msg.IDE == CAN_ID_EXT) 443 | { 444 | can_rx_msg.ExtId.bit.ExtId = ECanaMboxes.MBOX31.MSGID.all&0x1FFFFFFF; 445 | can_rx_msg.SAE_J1939_ID.all = can_rx_msg.ExtId.all; 446 | } 447 | else if(can_rx_msg.IDE == CAN_ID_STD) 448 | { 449 | can_rx_msg.StdId.bit.StdId = ECanaMboxes.MBOX31.MSGID.bit.STDMSGID; 450 | } 451 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte0 = ECanaMboxes.MBOX31.MDL.byte.BYTE0; 452 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte1 = ECanaMboxes.MBOX31.MDL.byte.BYTE1; 453 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte2 = ECanaMboxes.MBOX31.MDL.byte.BYTE2; 454 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte3 = ECanaMboxes.MBOX31.MDL.byte.BYTE3; 455 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte4 = ECanaMboxes.MBOX31.MDH.byte.BYTE4; 456 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte5 = ECanaMboxes.MBOX31.MDH.byte.BYTE5; 457 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte6 = ECanaMboxes.MBOX31.MDH.byte.BYTE6; 458 | can_rx_msg.CAN_Rx_msg_data.msg_Byte.byte7 = ECanaMboxes.MBOX31.MDH.byte.BYTE7; 459 | ECanaRegs.CANRMP.bit.RMP31 = 1; 460 | } 461 | } 462 | PieCtrlRegs.PIEACK.bit.ACK9 = 1; 463 | 464 | 465 | } 466 | -------------------------------------------------------------------------------- /bsp/src/Flash.c: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:Flash.c 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #include "Flash.h" 7 | void FlashAPI_Init(void) 8 | { 9 | EALLOW; 10 | Flash_CPUScaleFactor = SCALE_FACTOR; 11 | Flash_CallbackPtr = NULL; 12 | EDIS; 13 | } 14 | #pragma CODE_SECTION(Flash_RD,"ramfuncs"); 15 | Uint16 Flash_RD(Uint32 addr, Uint16 *buffer, Uint16 leng) 16 | { 17 | Uint16 i; 18 | Uint32 addr_temp = addr; 19 | for (i = 0; i < leng; i++) 20 | { 21 | *buffer = *(volatile Uint16*) addr_temp; 22 | buffer++; 23 | addr_temp += 1; 24 | } 25 | return STATUS_SUCCESS; 26 | 27 | } 28 | #pragma CODE_SECTION(Flash_WR,"ramfuncs"); 29 | Uint16 Flash_WR(Uint32 addr, Uint16 *buffer, Uint16 leng) 30 | { 31 | Uint16 *addr_temp = 0x00; 32 | addr_temp = (Uint16*) addr; 33 | FLASH_ST Flash_status; 34 | Uint16 status = 0x0001; 35 | status = Flash_Program(addr_temp, buffer, leng, &Flash_status); 36 | if (status != STATUS_SUCCESS) 37 | { 38 | return status; 39 | } 40 | status = 0x0001; 41 | status = Flash_Verify(addr_temp, buffer, leng, &Flash_status); 42 | if (status != STATUS_SUCCESS) 43 | { 44 | return status; 45 | } 46 | return STATUS_SUCCESS; 47 | } 48 | -------------------------------------------------------------------------------- /bsp/src/LED.c: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:LED.c 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #include "LED.h" 7 | UPDATA_INFO updata_info = 8 | { 9 | .time_cnt = 0, 10 | .time_out_flag = 0, 11 | }; 12 | void LED_GPIO_Config(void) 13 | { 14 | EALLOW; 15 | GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 0; 16 | GpioCtrlRegs.GPADIR.bit.GPIO23 = 1; 17 | EDIS; 18 | GpioDataRegs.GPASET.bit.GPIO23 = 1;; 19 | } 20 | void LED_Timer_Config(void) 21 | { 22 | EALLOW; 23 | //* SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; 24 | EDIS; 25 | InitCpuTimers(); 26 | ConfigCpuTimer(&CpuTimer0, 100, 100000);//250ms 27 | CpuTimer0Regs.TCR.all = 0x4001; // Use write-only instruction to set TSS bit = 0 28 | CpuTimer0.InterruptCount = 0; 29 | 30 | 31 | } 32 | interrupt void cpu_timer0_isr(void) 33 | { 34 | CpuTimer0.InterruptCount++;CpuTimer0.InterruptCount++; 35 | if(updata_info.time_out_flag == 0) 36 | { 37 | if( CpuTimer0.InterruptCount == 10) 38 | { 39 | CpuTimer0.InterruptCount = 0; 40 | } 41 | } 42 | GpioDataRegs.GPATOGGLE.bit.GPIO23 = 1; 43 | PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; 44 | } 45 | 46 | 47 | -------------------------------------------------------------------------------- /bsp/src/delay.c: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:delay.c 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #include "delay.h" 7 | void delay_us(unsigned long int nus) 8 | { 9 | while(nus) 10 | { 11 | DELAY_US(1); 12 | nus--; 13 | } 14 | } 15 | void delay_ms(unsigned long int nms) 16 | { 17 | while(nms) 18 | { 19 | DELAY_US(1000); 20 | nms--; 21 | } 22 | } 23 | 24 | void delay_s(unsigned long int ns) 25 | { 26 | while(ns) 27 | { 28 | delay_ms(1000); 29 | ns--; 30 | } 31 | 32 | } 33 | 34 | void delay(unsigned long int i) 35 | { 36 | while(i) 37 | { 38 | i--; 39 | } 40 | } 41 | 42 | -------------------------------------------------------------------------------- /user/inc/main.h: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:main.h 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #ifndef USER_INC_MAIN_H_ 7 | #define USER_INC_MAIN_H_ 8 | #include "include.h" 9 | #include "data.h" 10 | #include "delay.h" 11 | #include "stdint.h" 12 | #include "Flash280x_API_Library.h" 13 | #include "flash.h" 14 | #endif /* USER_INC_MAIN_H_ */ 15 | -------------------------------------------------------------------------------- /user/src/main.c: -------------------------------------------------------------------------------- 1 | /******************************************************** 2 | *文件名:main.c 3 | *创建时间:2018-10-09 4 | *作者: 皇甫仁和 5 | ********************************************************/ 6 | #include "main.h" 7 | #include "BootLoader.h" 8 | #include "LED.h" 9 | int main(void) 10 | { 11 | DINT; 12 | DRTM; 13 | InitSysCtrl(); 14 | CAN_GPIO_Config(CANA); 15 | LED_GPIO_Config(); 16 | CsmUnlock(); 17 | InitPieCtrl(); 18 | IER = 0x0000; 19 | IFR = 0x0000; 20 | InitPieVectTable(); 21 | EALLOW; 22 | PieVectTable.TINT0 = &cpu_timer0_isr; 23 | PieVectTable.ECAN1INTA = &Ecana_isr1; 24 | EDIS; 25 | MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); 26 | MemCopy(&Flash28_API_LoadStart, &Flash28_API_LoadEnd,&Flash28_API_RunStart); 27 | InitFlash(); 28 | FlashAPI_Init(); 29 | //此处用于判断当前是否存在app应用程序,如果存在就直接跳转至应用层 30 | FLASH_ST Flash_status; 31 | Uint16 status = 0x0001; 32 | status = Flash_Verify((Uint16*)APP_INFO_ADDR,app_check,2,&Flash_status); 33 | if(status == STATUS_SUCCESS) 34 | { 35 | CAN_BOOT_JumpToApplication(APP_START_ADDR); 36 | } 37 | CAN_Config(CANA,250); 38 | CAN_Rx_Config(); 39 | CAN_Rx_IT_Concig(); 40 | //配置LED指示灯 41 | LED_Timer_Config(); 42 | //------------------------------------ 43 | //配置中断 44 | PieCtrlRegs.PIEIER1.bit.INTx7 = 1; 45 | PieCtrlRegs.PIEIER9.bit.INTx6 = 1; //CANA的中断1 46 | IER |= M_INT9; 47 | IER |= M_INT1; 48 | __enable_irq(); 49 | while (1) 50 | { 51 | if(updata_info.time_out_flag == 0) 52 | { 53 | if(can_rx_msg.rx_update == UPDATE) 54 | { 55 | if(CpuTimer0Regs.TCR.bit.TSS == 0) 56 | { 57 | CpuTimer0Regs.TCR.bit.TSS = 1; 58 | } 59 | can_rx_msg.rx_update = NON_CHANGE; 60 | CAN_BOOT_ExecutiveCommand(&can_rx_msg); 61 | GpioDataRegs.GPATOGGLE.bit.GPIO23 = 1; 62 | } 63 | } 64 | else 65 | { 66 | CAN_BOOT_JumpToApplication(APP_START_ADDR); 67 | } 68 | 69 | } 70 | } 71 | --------------------------------------------------------------------------------