├── _config.yml ├── SynthesisLibrary ├── lib │ ├── script.abc │ ├── dff_full │ │ ├── compile.sh │ │ ├── compile.dcsh │ │ └── dff_full.db │ └── generic.sdb ├── lib_BMR │ ├── script.abc │ ├── dff_full │ │ ├── compile.sh │ │ ├── compile.dcsh │ │ └── dff_full.db │ ├── generic.sdb │ └── asic_cell_yosys.lib ├── lib_EMP │ ├── script.abc │ ├── dff_full │ │ ├── compile.sh │ │ ├── compile.dcsh │ │ └── dff_full.db │ ├── generic.sdb │ ├── asic_cell_yosys.lib │ └── asic_cell_yosys_area.lib ├── script │ ├── compile.sh │ ├── count_all.sh │ ├── count.sh │ ├── sample.yos │ └── sample.dcsh └── syn_lib │ ├── FA.v │ ├── TwosComplement.v │ ├── SHIFT_LEFT.v │ ├── SHIFT_RIGHT.v │ ├── MULT.v │ ├── MUX.v │ ├── DIV.v │ ├── ADD_.v │ ├── DIV_.v │ ├── MULT_.v │ ├── SUB.v │ ├── COMP.v │ └── ADD.v ├── Benchmarks ├── argmax │ ├── test │ │ ├── test.do │ │ ├── test.sh │ │ └── testbench.v │ ├── compile.sh │ ├── argmax.v │ └── argmax.dcsh ├── mips │ ├── test │ │ ├── test.do │ │ ├── test.sh │ │ └── benchmarks │ │ │ └── hamming.s │ ├── compile.sh │ ├── Shifter.v │ ├── Reg_Bank.v │ ├── Inst_Mem.v │ ├── mips.dcsh │ ├── ALU.v │ └── PC_Next.v ├── div │ ├── compile.sh │ ├── div.dcsh │ ├── div_q.v │ ├── div_r.v │ └── div.v ├── knns │ └── compile.sh ├── mult │ ├── compile.sh │ ├── mult.dcsh │ └── mult.v ├── rsa │ ├── compile.sh │ ├── test │ │ └── modmult_test.v │ └── rsa.dcsh ├── sha3 │ ├── compile.sh │ ├── test │ │ └── sha3_test.v │ └── sha3.dcsh ├── sum │ ├── compile.sh │ ├── sum.v │ └── sum.dcsh ├── cordic │ ├── compile.sh │ ├── cordic.vh │ ├── tables │ │ ├── circular.txt │ │ ├── linear.txt │ │ ├── hyperbolic.txt │ │ └── table_gen.m │ ├── barrel_shifter_left.v │ ├── barrel_shifter_left_test.v │ ├── cordic_test.v │ └── cordic.dcsh ├── encoder │ ├── compile.sh │ ├── encoder.dcsh │ └── encoder.v ├── float │ ├── compile.sh │ ├── DW_fp_log2_inst.v │ ├── fp_ln.v │ ├── fp_exp.v │ ├── fp_log2.v │ ├── float_add.v │ ├── float_div.v │ ├── float_mul.v │ ├── float.dcsh │ ├── float_cmp.v │ ├── fp_sqrt.v │ └── fp_square.v ├── select │ ├── compile.sh │ ├── select.dcsh │ └── select.v ├── aes │ ├── test │ │ ├── aes_test.do │ │ ├── test_aes.sh │ │ └── aes_testbench.v │ ├── compile.sh │ ├── AddRoundKey.v │ ├── aes.dcsh │ └── KeyExpansionSeq.v ├── compare │ ├── compile.sh │ ├── compare.v │ └── compare.dcsh ├── hamming │ ├── compile.sh │ ├── hamming.v │ └── hamming.dcsh ├── matrix_mult │ ├── compile.sh │ ├── matrix_mult_N_M_3.v │ ├── test │ │ └── matrixMultSeqTest.v │ ├── matrix_mult.dcsh │ ├── matrix_mult_N_M_2.v │ └── matrix_mult_N_M_0.v ├── public_test │ ├── compile.sh │ ├── public_test.dcsh │ └── public_test.v ├── stable_match │ ├── compile.sh │ ├── encoder.v │ └── stable_match.dcsh ├── stack_machine │ ├── compile.sh │ ├── stackMachine.dcsh │ └── test │ │ └── stackMachine_test.v ├── non_secret_test │ ├── compile.sh │ ├── non_secret_test.dcsh │ └── non_secret_test.v ├── compile_all.sh ├── knns_td │ ├── compile.sh │ ├── knns_td.dcsh │ ├── first_nns_seq_td.dcsh │ ├── k_nns_seq_td.dcsh │ ├── first_nns_comb_td.dcsh │ └── taxicab_distance.v └── README.md ├── ProgInt ├── lt │ ├── compile.sh │ ├── lt.sv │ └── lt.tcl ├── add │ ├── compile.sh │ ├── add.sv │ └── add.tcl ├── mac │ ├── compile.sh │ ├── mac.sv │ └── mac.tcl ├── max │ ├── compile.sh │ ├── max.sv │ └── max.tcl ├── min │ ├── compile.sh │ ├── min.sv │ └── min.tcl ├── mult │ ├── _compile.sh │ ├── mult.sv │ └── mult.tcl ├── relu │ ├── compile.sh │ ├── relu.sv │ └── relu.tcl ├── sub │ ├── compile.sh │ ├── sub.sv │ └── sub.tcl ├── ifelse │ ├── compile.sh │ ├── ifelse.sv │ └── ifelse.tcl ├── mult_n_2_2n │ ├── compile.sh │ ├── mult_n_2_2n.sv │ └── mult_n_2_2n.tcl ├── div │ ├── div_nm_2_n.sv │ ├── compile_tmp.sh │ ├── compile.sh │ └── div_nm_2_n.tcl ├── logic2 │ ├── compile.sh │ ├── logic2.sv │ └── logic2.tcl └── compile_yos_all.sh ├── Verilog2EMP ├── v.tar.gz ├── V2EMP_ALL.sh.in ├── configure ├── emp_circuit.h ├── scheduling.h └── parse_netlist.h ├── Verilog2SCD ├── v.tar.gz ├── V2SCD_ALL.sh.in ├── configure ├── scheduling.h ├── scd.h └── parse_netlist.h ├── Benchmarks2 ├── Simulation │ ├── aes_11cc.do │ ├── aes_1cc.do │ ├── aes_ht.do │ ├── fc_layer.do │ ├── fc_layer_relu.do │ ├── setupsim.do │ ├── relu_nbit_1cc.do │ ├── div_nm_2_n.do │ ├── hamming_nbit_ncc.do │ ├── comp_nbit_ncc.do │ ├── sum_nbit_1cc.do │ ├── hamming_nbit_1cc.do │ ├── mult_mnbit_1cc.do │ ├── comp_nbit_1cc.do │ ├── sum_nbit_ncc.do │ ├── mac_nnbit_1cc.do │ ├── mult_mnbit_ncc.do │ ├── maxpool_nbit_kdim_kcc.do │ ├── vdp_nnbit_kdim_kcc.do │ └── mxm_nnbit_mk1dim_mkcc.do ├── aes │ ├── AddRoundKey.sv │ ├── compile.sh │ ├── tb_aes_1cc.sv │ ├── aes_1cc.tcl │ ├── tb_aes_11cc.sv │ ├── aes.dcsh │ └── KeyExpansionSeq.sv ├── aes_ht │ ├── AddRoundKey.sv │ ├── compile.sh │ ├── aes_ht_10.sv │ ├── aes_ht_1.sv │ ├── tb_aes_ht.sv │ ├── aes_ht_0.sv │ ├── MixColumns.sv │ └── KeyExpansion_ht.sv ├── relu │ ├── relu_nbit_1cc.sv │ ├── compile.sh │ ├── relu.tcl │ ├── tb_relu_nbit_1cc.sv │ └── relu.dcsh ├── compare │ ├── comp_nbit_1cc.sv │ ├── compile.sh │ ├── comp_nbit_ncc.sv │ ├── comp.tcl │ ├── tb_comp_nbit_1cc.sv │ ├── comp.dcsh │ └── tb_comp_nbit_ncc.sv ├── mult │ ├── mult_mnbit_1cc.sv │ ├── compile.sh │ ├── mult.tcl │ ├── tb_mult_mnbit_ncc.sv │ └── tb_mult_mnbit_1cc.sv ├── div │ ├── div_nm_2_n.sv │ └── tb_div_nm_2_n.sv ├── sum │ ├── sum_nbit_1cc.sv │ ├── compile.sh │ ├── sum_nbit_ncc.sv │ ├── tb_sum_nbit_1cc.sv │ ├── sum.tcl │ ├── tb_sum_nbit_ncc.sv │ └── sum.dcsh ├── vdp │ ├── compile.sh │ ├── mac.tcl │ ├── mac_nnbit_kcc.sv │ ├── tb_vdp_nnbit_kdim_kcc.sv │ └── mac.dcsh ├── hamming │ ├── compile.sh │ ├── hamming.tcl │ ├── hamming.v │ └── hamming.dcsh ├── maxpool │ ├── compile.sh │ ├── maxpool_nbit_kdim_kcc.sv │ ├── maxpool.tcl │ ├── maxpool.dcsh │ └── tb_maxpool_nbit_kdim_kcc.sv ├── fc_layer │ ├── compile.sh │ ├── mac_comb.sv │ ├── mxv_nnbit_jkdim_relu.tcl │ ├── mxv_nnbit_jkdim_relu.sv │ ├── mxv_nnbit_jkdim.sv │ ├── tb_mxv_nnbit_jkdim.sv │ └── tb_mxv_nnbit_jkdim_relu.sv ├── compile_yos_all.sh ├── compile_all.sh └── Headers │ └── Common_H.vh ├── demo └── vdp │ ├── compile_y.sh │ ├── compile.sh │ ├── mac.tcl │ ├── mac.sv │ └── mac.dcsh ├── Verilog2BMR ├── configure ├── bmr.h ├── scheduling.h └── parse_netlist.h └── .gitignore /_config.yml: -------------------------------------------------------------------------------- 1 | theme: jekyll-theme-slate -------------------------------------------------------------------------------- /SynthesisLibrary/lib/script.abc: -------------------------------------------------------------------------------- 1 | map; 2 | -------------------------------------------------------------------------------- /SynthesisLibrary/lib_BMR/script.abc: -------------------------------------------------------------------------------- 1 | map; 2 | -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/script.abc: -------------------------------------------------------------------------------- 1 | map; 2 | -------------------------------------------------------------------------------- /Benchmarks/argmax/test/test.do: -------------------------------------------------------------------------------- 1 | run -all 2 | exit 3 | -------------------------------------------------------------------------------- /ProgInt/lt/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c lt.tcl -------------------------------------------------------------------------------- /ProgInt/add/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c add.tcl -------------------------------------------------------------------------------- /ProgInt/mac/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c mac.tcl -------------------------------------------------------------------------------- /ProgInt/max/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c max.tcl -------------------------------------------------------------------------------- /ProgInt/min/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c min.tcl -------------------------------------------------------------------------------- /ProgInt/mult/_compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c mult.tcl -------------------------------------------------------------------------------- /ProgInt/relu/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c relu.tcl -------------------------------------------------------------------------------- /ProgInt/sub/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c sub.tcl -------------------------------------------------------------------------------- /ProgInt/ifelse/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c ifelse.tcl -------------------------------------------------------------------------------- /Benchmarks/mips/test/test.do: -------------------------------------------------------------------------------- 1 | add wave sim:/Test_Bench/clk 2 | run -all -------------------------------------------------------------------------------- /ProgInt/mult_n_2_2n/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c mult_n_2_2n.tcl -------------------------------------------------------------------------------- /SynthesisLibrary/lib/dff_full/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | lc_shell -f compile.dcsh -------------------------------------------------------------------------------- /SynthesisLibrary/lib_BMR/dff_full/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | lc_shell -f compile.dcsh -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/dff_full/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | lc_shell -f compile.dcsh -------------------------------------------------------------------------------- /Benchmarks/div/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f div.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/knns/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f knns.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/mips/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f mips.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/mult/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f mult.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/rsa/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f rsa.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/sha3/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f sha3.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/sum/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f sum.dcsh 4 | -------------------------------------------------------------------------------- /SynthesisLibrary/script/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | design_vision -no_gui -f sample.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/argmax/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f argmax.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/cordic/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f cordic.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/encoder/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | dc_shell-t -no_gui -f encoder.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/float/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f float.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/select/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f select.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/aes/test/aes_test.do: -------------------------------------------------------------------------------- 1 | add wave -position insertpoint sim:/aes_testbench/* 2 | 3 | run -all 4 | -------------------------------------------------------------------------------- /Benchmarks/compare/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f compare.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/hamming/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f hamming.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/matrix_mult/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f matrix_mult.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/public_test/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f public_test.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/stable_match/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f stable_match.dcsh 4 | -------------------------------------------------------------------------------- /Benchmarks/stack_machine/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f stackMachine.dcsh 4 | -------------------------------------------------------------------------------- /Verilog2EMP/v.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/Verilog2EMP/v.tar.gz -------------------------------------------------------------------------------- /Verilog2SCD/v.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/Verilog2SCD/v.tar.gz -------------------------------------------------------------------------------- /Benchmarks/non_secret_test/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f non_secret_test.dcsh 4 | -------------------------------------------------------------------------------- /SynthesisLibrary/lib/dff_full/compile.dcsh: -------------------------------------------------------------------------------- 1 | set search_path . 2 | read_lib dff_full.lib 3 | write_lib dff_full -format db 4 | exit -------------------------------------------------------------------------------- /Benchmarks/aes/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | design_vision -no_gui -f aes.dcsh 4 | 5 | rm *.pvl *.syn *.mr *.log *.svf -------------------------------------------------------------------------------- /SynthesisLibrary/lib_BMR/dff_full/compile.dcsh: -------------------------------------------------------------------------------- 1 | set search_path . 2 | read_lib dff_full.lib 3 | write_lib dff_full -format db 4 | exit -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/dff_full/compile.dcsh: -------------------------------------------------------------------------------- 1 | set search_path . 2 | read_lib dff_full.lib 3 | write_lib dff_full -format db 4 | exit -------------------------------------------------------------------------------- /Benchmarks/cordic/cordic.vh: -------------------------------------------------------------------------------- 1 | `define DIR_ROT 0 2 | `define DIR_VEC 1 3 | 4 | `define MOD_CIR 1 5 | `define MOD_LIN 0 6 | `define MOD_HYP -1 -------------------------------------------------------------------------------- /SynthesisLibrary/lib/generic.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib/generic.sdb -------------------------------------------------------------------------------- /Benchmarks2/Simulation/aes_11cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../aes/*.sv 2 | vsim -gui work.tb_aes_1cc -L TG_SynLib 3 | 4 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/aes_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../aes/*.sv 2 | vsim -gui work.tb_aes_11cc -L TG_SynLib 3 | 4 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/aes_ht.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../aes_ht/*.sv 2 | vsim -gui work.tb_aes_ht -L TG_SynLib 3 | 4 | run -all -------------------------------------------------------------------------------- /SynthesisLibrary/lib_BMR/generic.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib_BMR/generic.sdb -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/generic.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib_EMP/generic.sdb -------------------------------------------------------------------------------- /Benchmarks2/Simulation/fc_layer.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../fc_layer/*.sv 2 | vsim -gui work.tb_mxv_nnbit_jkdim -L TG_SynLib 3 | 4 | run -all -------------------------------------------------------------------------------- /SynthesisLibrary/lib/dff_full/dff_full.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib/dff_full/dff_full.db -------------------------------------------------------------------------------- /Benchmarks2/Simulation/fc_layer_relu.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../fc_layer/*.sv 2 | vsim -gui work.tb_mxv_nnbit_jkdim_relu -L TG_SynLib 3 | 4 | run -all -------------------------------------------------------------------------------- /SynthesisLibrary/lib_BMR/dff_full/dff_full.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib_BMR/dff_full/dff_full.db -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/dff_full/dff_full.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACESLabUCSD/TinyGarbleCircuitSynthesis/HEAD/SynthesisLibrary/lib_EMP/dff_full/dff_full.db -------------------------------------------------------------------------------- /Benchmarks2/Simulation/setupsim.do: -------------------------------------------------------------------------------- 1 | vlib TG_SynLib 2 | vmap TG_SynLib TG_SynLib 3 | vlog -reportprogress 300 -work TG_SynLib ../../SynthesisLibrary/syn_lib/*.v 4 | 5 | vlib work 6 | vmap work work -------------------------------------------------------------------------------- /Benchmarks/aes/AddRoundKey.v: -------------------------------------------------------------------------------- 1 | module AddRoundKey( 2 | x, 3 | y, 4 | z); 5 | 6 | input [127:0] x; 7 | input [127:0] y; 8 | output [127:0] z; 9 | 10 | assign z = x ^ y; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /Benchmarks/compile_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn_all 3 | for d in * 4 | do 5 | ( cd "$d" && ./compile.sh && rm *.pvl *.syn *.mr *.log *.svf && cd ".." && cp ${d%/*}/syn/*.v syn_all) 6 | done 7 | rm *.log -------------------------------------------------------------------------------- /Benchmarks2/aes/AddRoundKey.sv: -------------------------------------------------------------------------------- 1 | module AddRoundKey( 2 | x, 3 | y, 4 | z); 5 | 6 | input [127:0] x; 7 | input [127:0] y; 8 | output [127:0] z; 9 | 10 | assign z = x ^ y; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/AddRoundKey.sv: -------------------------------------------------------------------------------- 1 | module AddRoundKey( 2 | x, 3 | y, 4 | z); 5 | 6 | input [127:0] x; 7 | input [127:0] y; 8 | output [127:0] z; 9 | 10 | assign z = x ^ y; 11 | 12 | endmodule 13 | 14 | -------------------------------------------------------------------------------- /Benchmarks/aes/test/test_aes.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf work transcript vsim.wlf 4 | vlib work 5 | vlog ../*.v ./aes_testbench.v ../../../SynthesisLibrary/lib/dff_full/dff_full.v 6 | vsim -do aes_test.do aes_testbench 7 | -------------------------------------------------------------------------------- /SynthesisLibrary/script/count_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | for verilogfile in $1/*.v 3 | do 4 | printf "$verilogfile: " 5 | grep -w -c 'AND\|ANDN\|NAND\|NANDN\|OR\|ORN\|NOR\|NORN\|MUX\|FA\|HA\|HADDER\|FADDER' $verilogfile 6 | done 7 | wait -------------------------------------------------------------------------------- /demo/vdp/compile_y.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c mac.tcl 3 | 4 | for verilogfile in syn/*.v 5 | do 6 | scdfile=${verilogfile%.*}.scd 7 | ../../../../TinyGarble-ES/bin/scd/V2SCD_Main -i $verilogfile -o $scdfile --log2std 8 | done 9 | -------------------------------------------------------------------------------- /Benchmarks/argmax/test/test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | rm -rf work transcript vsim.wlf 4 | vlib work 5 | 6 | 7 | vlog ../argmax.v testbench.v 8 | 9 | #w/o gui 10 | vsim -c -do test.do testbench 11 | 12 | #w/ gui 13 | #vsim -do test.do testbench 14 | -------------------------------------------------------------------------------- /ProgInt/relu/relu.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module relu #(parameter N = 8)( 4 | input [N-1:0] s_input, 5 | output [N-1:0] o 6 | ); 7 | assign o = s_input&{(N){~s_input[N-1]}}; 8 | //assign o = (s_input < 0)? 'b0 : s_input; 9 | 10 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/relu/relu_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module relu_nbit_1cc #(parameter N = 8)( 4 | input signed [N-1:0] s_input, 5 | output signed [N-2:0] o 6 | ); 7 | 8 | assign o = s_input[N-2:0]&{(N-1){~s_input[N-1]}}; 9 | 10 | endmodule -------------------------------------------------------------------------------- /Verilog2EMP/V2EMP_ALL.sh.in: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | 4 | for verilogfile in @CMAKE_CURRENT_BINARY_DIR@/netlists/*.v 5 | do 6 | empfile=${verilogfile%.*}.emp 7 | @CMAKE_CURRENT_BINARY_DIR@/V2EMP_Main -i $verilogfile -o $empfile --log2std & 8 | done 9 | wait 10 | -------------------------------------------------------------------------------- /Verilog2SCD/V2SCD_ALL.sh.in: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | 4 | for verilogfile in @CMAKE_CURRENT_BINARY_DIR@/netlists/*.v 5 | do 6 | scdfile=${verilogfile%.*}.scd 7 | @CMAKE_CURRENT_BINARY_DIR@/V2SCD_Main -i $verilogfile -o $scdfile --log2std & 8 | done 9 | wait 10 | -------------------------------------------------------------------------------- /Verilog2BMR/configure: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | mkdir -p bin 4 | cd bin 5 | cmake -DCMAKE_BUILD_TYPE=Release -DENABLE_LOG=ON .. 6 | if [ $? -eq 0 ] 7 | then 8 | echo "Config is done. Now call '$ cd bin' and then '$ make' to compile TinyGarble-BMR." 9 | fi 10 | 11 | 12 | -------------------------------------------------------------------------------- /Verilog2EMP/configure: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | mkdir -p bin 4 | cd bin 5 | cmake -DCMAKE_BUILD_TYPE=Release -DENABLE_LOG=ON .. 6 | if [ $? -eq 0 ] 7 | then 8 | echo "Config is done. Now call '$ cd bin' and then '$ make' to compile TinyGarble-EMP." 9 | fi 10 | 11 | 12 | -------------------------------------------------------------------------------- /Verilog2SCD/configure: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | mkdir -p bin 4 | cd bin 5 | cmake -DCMAKE_BUILD_TYPE=Release -DENABLE_LOG=ON .. 6 | if [ $? -eq 0 ] 7 | then 8 | echo "Config is done. Now call '$ cd bin' and then '$ make' to compile TinyGarble-BMR." 9 | fi 10 | 11 | 12 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/relu_nbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../relu/*relu_nbit_1cc.sv 2 | vsim -gui work.tb_relu_nbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_relu_nbit_1cc/s_input \ 6 | sim:/tb_relu_nbit_1cc/o \ 7 | sim:/tb_relu_nbit_1cc/o_ref 8 | 9 | run -all -------------------------------------------------------------------------------- /demo/vdp/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | design_vision -no_gui -f mac.dcsh 3 | rm *.pvl *.syn *.mr *.log *.svf 4 | 5 | for verilogfile in syn/*.v 6 | do 7 | scdfile=${verilogfile%.*}.scd 8 | ../../../../TinyGarble-ES/bin/scd/V2SCD_Main -i $verilogfile -o $scdfile --log2std 9 | done 10 | -------------------------------------------------------------------------------- /Benchmarks/mips/test/test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | CC=$1 #clock cycle to evalute 4 | 5 | if [ -z "$CC" ] 6 | then 7 | CC=100 #default is 100 clock cycle 8 | fi 9 | 10 | vlib work 11 | vlog ../../../SynthesisLibrary/syn_lib/*.v ../*.v Test_Bench.v 12 | vsim -gCC=$CC -do test.do Test_Bench 13 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/div_nm_2_n.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../div/*div_nm_2_n.sv 2 | vsim -gui work.tb_div_nm_2_n -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_div_nm_2_n/g_input \ 6 | sim:/tb_div_nm_2_n/e_input \ 7 | sim:/tb_div_nm_2_n/o \ 8 | sim:/tb_div_nm_2_n/o_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /Benchmarks2/compare/comp_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comp_nbit_1cc #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output o 7 | ); 8 | 9 | COMP #(.N(N)) COMP( 10 | .A(g_input), 11 | .B(e_input), 12 | .O(o) 13 | ); 14 | 15 | endmodule -------------------------------------------------------------------------------- /ProgInt/lt/lt.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module lt #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output o 7 | ); 8 | logic [N-1:0] dummy; 9 | 10 | SUB_ #(.N(N)) SUB_( 11 | .A(g_input), 12 | .B(e_input), 13 | .O({o, dummy}) 14 | ); 15 | 16 | endmodule -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/FA.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module FA( 4 | input A, B, CI, 5 | output S, CO 6 | ); 7 | 8 | wire n1, n2, n3; 9 | 10 | assign n1 = A^CI; 11 | assign n2 = B^CI; 12 | assign n3 = n1&n2; 13 | assign S = n1^B; 14 | assign CO = n3^CI; 15 | 16 | 17 | endmodule 18 | 19 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/hamming_nbit_ncc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../hamming/*.sv 2 | vsim -gui work.tb_hamming_nbit_ncc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_hamming_nbit_ncc/G \ 6 | sim:/tb_hamming_nbit_ncc/E \ 7 | sim:/tb_hamming_nbit_ncc/O \ 8 | sim:/tb_hamming_nbit_ncc/O_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /ProgInt/add/add.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module add #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | logic dummy; 9 | 10 | ADD_ #(.N(N)) ADD_( 11 | .A(g_input), 12 | .B(e_input), 13 | .O({dummy, o}) 14 | ); 15 | 16 | endmodule -------------------------------------------------------------------------------- /ProgInt/sub/sub.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sub #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | logic dummy; 9 | 10 | SUB_ #(.N(N)) SUB_( 11 | .A(g_input), 12 | .B(e_input), 13 | .O({dummy, o}) 14 | ); 15 | 16 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/Simulation/comp_nbit_ncc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../compare/*comp_nbit_ncc.sv 2 | vsim -gui work.tb_comp_nbit_ncc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_comp_nbit_ncc/G \ 6 | sim:/tb_comp_nbit_ncc/E \ 7 | sim:/tb_comp_nbit_ncc/O \ 8 | sim:/tb_comp_nbit_ncc/O_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/sum_nbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../sum/*sum_nbit_1cc.sv 2 | vsim -gui work.tb_sum_nbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_sum_nbit_1cc/g_input \ 6 | sim:/tb_sum_nbit_1cc/e_input \ 7 | sim:/tb_sum_nbit_1cc/o \ 8 | sim:/tb_sum_nbit_1cc/o_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /Benchmarks2/mult/mult_mnbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mult_mnbit_1cc #(parameter N = 8, M = N)( 4 | input [N-1:0] g_input, 5 | input [M-1:0] e_input, 6 | output [N+M-1:0] o 7 | ); 8 | 9 | MULT #(.N(N), .M(M)) MULT( 10 | .A(g_input), 11 | .B(e_input), 12 | .O(o) 13 | ); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /ProgInt/ifelse/ifelse.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ifelse #(parameter N = 8)( 4 | input [2*N-1:0] g_input, 5 | input [0:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | 9 | MUX #(.N(N)) MUX( 10 | .A(g_input[N-1:0]), 11 | .B(g_input[2*N-1:N]), 12 | .S(e_input), 13 | .O(o) 14 | ); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/hamming_nbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../hamming/*.sv 2 | vsim -gui work.tb_hamming_nbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_hamming_nbit_1cc/g_input \ 6 | sim:/tb_hamming_nbit_1cc/e_input \ 7 | sim:/tb_hamming_nbit_1cc/o \ 8 | sim:/tb_hamming_nbit_1cc/o_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/mult_mnbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../mult/*mult_mnbit_1cc.sv 2 | vsim -gui work.tb_mult_mnbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_mult_mnbit_1cc/g_input \ 6 | sim:/tb_mult_mnbit_1cc/e_input \ 7 | sim:/tb_mult_mnbit_1cc/o \ 8 | sim:/tb_mult_mnbit_1cc/o_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /ProgInt/div/div_nm_2_n.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module div_nm_2_n #(parameter N = 8, M = N)( 4 | input signed [N-1:0] g_input, 5 | input signed [M-1:0] e_input, 6 | output signed [N-1:0] o 7 | ); 8 | 9 | DIV_ #(.N(N), .M(M)) DIV_( 10 | .A(g_input), 11 | .B(e_input), 12 | .O(o) 13 | ); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/comp_nbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../compare/*comp_nbit_1cc.sv 2 | vsim -gui work.tb_comp_nbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_comp_nbit_1cc/g_input \ 6 | sim:/tb_comp_nbit_1cc/e_input \ 7 | sim:/tb_comp_nbit_1cc/o \ 8 | sim:/tb_comp_nbit_1cc/o_ref 9 | 10 | run -all -------------------------------------------------------------------------------- /Benchmarks2/div/div_nm_2_n.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module div_nm_2_n #(parameter N = 8, M = N)( 4 | input signed [N-1:0] g_input, 5 | input signed [M-1:0] e_input, 6 | output signed [N-1:0] o 7 | ); 8 | 9 | DIV_ #(.N(N), .M(M)) DIV_( 10 | .A(g_input), 11 | .B(e_input), 12 | .O(o) 13 | ); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /ProgInt/div/compile_tmp.sh: -------------------------------------------------------------------------------- 1 | 2 | 3 | for verilogfile in syn/*.v 4 | do 5 | empfile=${verilogfile%.*}.emp 6 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 7 | ../../../tinygarble2/bin/readCircuitFile -i $empfile & 8 | done 9 | wait 10 | 11 | cp syn/*.bin ../../../tinygarble2/tinygarble/netlists_pi/ 12 | -------------------------------------------------------------------------------- /Benchmarks2/sum/sum_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sum_nbit_1cc #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N:0] o 7 | ); 8 | 9 | ADD #(.N(N)) ADD( 10 | .A(g_input), 11 | .B(e_input), 12 | .CI(1'b0), 13 | .S(o[N-1:0]), 14 | .CO(o[N]) 15 | ); 16 | 17 | endmodule -------------------------------------------------------------------------------- /ProgInt/mult_n_2_2n/mult_n_2_2n.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mult_n_2_2n #(parameter N = 8, M = N)( 4 | input signed [N-1:0] g_input, 5 | input signed [M-1:0] e_input, 6 | output signed [N+M-2:0] o 7 | ); 8 | 9 | MULT_ #(.N(N), .M(M)) MULT_( 10 | .A(g_input), 11 | .B(e_input), 12 | .O(o) 13 | ); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /Benchmarks/cordic/tables/circular.txt: -------------------------------------------------------------------------------- 1 | 0011001001000100 2 | 0001110110101100 3 | 0000111110101110 4 | 0000011111110101 5 | 0000001111111111 6 | 0000001000000000 7 | 0000000100000000 8 | 0000000010000000 9 | 0000000001000000 10 | 0000000000100000 11 | 0000000000010000 12 | 0000000000001000 13 | 0000000000000100 14 | 0000000000000010 15 | 0000000000000001 16 | -------------------------------------------------------------------------------- /Benchmarks/cordic/tables/linear.txt: -------------------------------------------------------------------------------- 1 | 0100000000000000 2 | 0010000000000000 3 | 0001000000000000 4 | 0000100000000000 5 | 0000010000000000 6 | 0000001000000000 7 | 0000000100000000 8 | 0000000010000000 9 | 0000000001000000 10 | 0000000000100000 11 | 0000000000010000 12 | 0000000000001000 13 | 0000000000000100 14 | 0000000000000010 15 | 0000000000000001 16 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/sum_nbit_ncc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../sum/*sum_nbit_ncc.sv 2 | vsim -gui work.tb_sum_nbit_ncc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_sum_nbit_ncc/clk \ 6 | sim:/tb_sum_nbit_ncc/rst \ 7 | sim:/tb_sum_nbit_ncc/g_input \ 8 | sim:/tb_sum_nbit_ncc/e_input \ 9 | sim:/tb_sum_nbit_ncc/o \ 10 | 11 | run -all -------------------------------------------------------------------------------- /ProgInt/mult/mult.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mult #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | logic [2*N-2:0] o_2; 9 | 10 | MULT_ #(.N(N)) MULT_( 11 | .A(g_input), 12 | .B(e_input), 13 | .O(o_2) 14 | ); 15 | 16 | assign o = o_2[N-1:0]; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /Benchmarks/cordic/tables/hyperbolic.txt: -------------------------------------------------------------------------------- 1 | 0010001100101000 2 | 0001000001011001 3 | 0000100000001011 4 | 0000010000000001 5 | 0000001000000000 6 | 0000000100000000 7 | 0000000010000000 8 | 0000000001000000 9 | 0000000000100000 10 | 0000000000010000 11 | 0000000000001000 12 | 0000000000000100 13 | 0000000000000010 14 | 0000000000000001 15 | 0000000000000001 16 | -------------------------------------------------------------------------------- /ProgInt/div/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c div_nm_2_n.tcl 3 | 4 | for verilogfile in syn/*.v 5 | do 6 | empfile=${verilogfile%.*}.emp 7 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 8 | ../../../tinygarble2/bin/readCircuitFile -i $empfile & 9 | done 10 | wait 11 | 12 | cp syn/*.bin ../../../tinygarble2/tinygarble/netlists_pi/ -------------------------------------------------------------------------------- /ProgInt/logic2/compile.sh: -------------------------------------------------------------------------------- 1 | mkdir -p syn 2 | yosys -c logic2.tcl 3 | 4 | for verilogfile in syn/*.v 5 | do 6 | empfile=${verilogfile%.*}.emp 7 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 8 | ../../../tinygarble2/bin/readCircuitFile -i $empfile & 9 | done 10 | wait 11 | 12 | cp syn/*.bin ../../../tinygarble2/tinygarble/netlists_pi/ -------------------------------------------------------------------------------- /Benchmarks/knns_td/compile.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn 3 | 4 | if [ $1 == "1" ]; then 5 | design_vision -no_gui -f k_nns_seq_td.dcsh 6 | fi 7 | if [ $2 == "1" ]; then 8 | design_vision -no_gui -f first_nns_seq_td.dcsh 9 | fi 10 | if [ $3 == "1" ]; then 11 | design_vision -no_gui -f first_nns_comb_td.dcsh 12 | fi 13 | 14 | rm *.pvl *.syn *.mr *.log *.svf 15 | -------------------------------------------------------------------------------- /Benchmarks2/Simulation/mac_nnbit_1cc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../vdp/*mac_nnbit_*cc.sv 2 | vsim -gui work.tb_mac_nnbit_1cc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_mac_nnbit_1cc/clk \ 6 | sim:/tb_mac_nnbit_1cc/rst \ 7 | sim:/tb_mac_nnbit_1cc/g_input \ 8 | sim:/tb_mac_nnbit_1cc/e_input \ 9 | sim:/tb_mac_nnbit_1cc/o \ 10 | sim:/tb_mac_nnbit_1cc/o_ref \ 11 | 12 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/mult_mnbit_ncc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../mult/*mult_mnbit_ncc.sv 2 | vsim -gui work.tb_mult_mnbit_ncc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_mult_mnbit_ncc/G \ 6 | sim:/tb_mult_mnbit_ncc/g_input \ 7 | sim:/tb_mult_mnbit_ncc/e_init \ 8 | sim:/tb_mult_mnbit_ncc/o \ 9 | sim:/tb_mult_mnbit_ncc/O \ 10 | sim:/tb_mult_mnbit_ncc/O_ref 11 | 12 | run -all -------------------------------------------------------------------------------- /Benchmarks2/Simulation/maxpool_nbit_kdim_kcc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../maxpool/*.sv 2 | vsim -gui work.tb_maxpool_nbit_kdim_kcc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_maxpool_nbit_kdim_kcc/clk \ 6 | sim:/tb_maxpool_nbit_kdim_kcc/rst \ 7 | sim:/tb_maxpool_nbit_kdim_kcc/s_input \ 8 | sim:/tb_maxpool_nbit_kdim_kcc/o \ 9 | sim:/tb_maxpool_nbit_kdim_kcc/O_ref \ 10 | 11 | run -all -------------------------------------------------------------------------------- /ProgInt/logic2/logic2.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module logic2 #(parameter N = 8, LOGIC = 0)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | 9 | generate 10 | if (LOGIC == 0) assign o = g_input & e_input; 11 | if (LOGIC == 1) assign o = g_input | e_input; 12 | if (LOGIC == 2) assign o = g_input ^ e_input; 13 | endgenerate 14 | 15 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/Simulation/vdp_nnbit_kdim_kcc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../vdp/*.sv 2 | vsim -gui work.tb_vdp_nnbit_kdim_kcc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_vdp_nnbit_kdim_kcc/clk \ 6 | sim:/tb_vdp_nnbit_kdim_kcc/rst \ 7 | sim:/tb_vdp_nnbit_kdim_kcc/g_input \ 8 | sim:/tb_vdp_nnbit_kdim_kcc/e_input \ 9 | sim:/tb_vdp_nnbit_kdim_kcc/o \ 10 | sim:/tb_vdp_nnbit_kdim_kcc/O_ref \ 11 | 12 | run -all -------------------------------------------------------------------------------- /Benchmarks2/sum/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f sum.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c sum.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/vdp/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f mac.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c mac.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/aes/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f aes.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c aes_1cc.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/compare/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f comp.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c comp.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/mult/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f mult.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c mult.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/relu/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f relu.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c relu.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f aes_ht.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c aes_ht.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/hamming/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f hamming.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c hamming.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/maxpool/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f maxpool.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c maxpool.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/sum/sum_nbit_ncc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module sum_nbit_ncc( 4 | input clk, rst, 5 | input g_input, 6 | input e_input, 7 | output o 8 | ); 9 | 10 | logic carry, carry_d; 11 | always@(posedge clk or posedge rst) 12 | if(rst) carry <= 1'b0; 13 | else carry <= carry_d; 14 | 15 | ADD #(.N(1)) ADD( 16 | .A(g_input), 17 | .B(e_input), 18 | .CI(carry), 19 | .S(o), 20 | .CO(carry_d) 21 | ); 22 | 23 | endmodule -------------------------------------------------------------------------------- /ProgInt/max/max.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module max #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | 9 | logic c; 10 | logic [N-1:0] dummy; 11 | 12 | SUB_ #(.N(N)) SUB_( 13 | .A(g_input), 14 | .B(e_input), 15 | .O({c, dummy}) 16 | ); 17 | 18 | MUX #(.N(N)) MUX( 19 | .A(g_input), 20 | .B(e_input), 21 | .S(c), 22 | .O(o) 23 | ); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /ProgInt/min/min.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module min #(parameter N = 8)( 4 | input [N-1:0] g_input, 5 | input [N-1:0] e_input, 6 | output [N-1:0] o 7 | ); 8 | 9 | logic c; 10 | logic [N-1:0] dummy; 11 | 12 | SUB_ #(.N(N)) SUB_( 13 | .A(g_input), 14 | .B(e_input), 15 | .O({c, dummy}) 16 | ); 17 | 18 | MUX #(.N(N)) MUX( 19 | .A(e_input), 20 | .B(g_input), 21 | .S(c), 22 | .O(o) 23 | ); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | bin/ 2 | debug/ 3 | alib-52/ 4 | *.alib 5 | *.log 6 | *.mr 7 | *.syn 8 | *.pvl 9 | *.svf 10 | *.out 11 | *.o 12 | *.cl 13 | *.dat 14 | *~ 15 | .~*# 16 | .nfs* 17 | clog* 18 | .cproject 19 | .project 20 | .settings 21 | .metadata 22 | transcript 23 | *.wlf 24 | syn 25 | syn/* 26 | work/ 27 | work/* 28 | *.dis 29 | *.elf 30 | *.map 31 | *.mem 32 | *.hex 33 | a23/tools/amber-elfsplitter*.scd 34 | *.scd* 35 | *.aby* 36 | *syn_all* 37 | *TG_SynLib* 38 | *modelsim.ini* -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/compile.sh: -------------------------------------------------------------------------------- 1 | echo "Use -d to compile with Synopsys Design Compiler" 2 | 3 | mkdir -p syn 4 | 5 | if [ $1 ] && [ $1 = "-d" ]; then 6 | design_vision -no_gui -f mxv_nnbit_jkdim_relu.dcsh 7 | rm *.pvl *.syn *.mr *.log *.svf 8 | else 9 | yosys -c mxv_nnbit_jkdim_relu.tcl 10 | fi 11 | 12 | for verilogfile in syn/*.v 13 | do 14 | empfile=${verilogfile%.*}.emp 15 | ../../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 16 | done 17 | -------------------------------------------------------------------------------- /Benchmarks2/compare/comp_nbit_ncc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module comp_nbit_ncc( 4 | input clk, rst, 5 | input g_input, 6 | input e_input, 7 | output o 8 | ); 9 | 10 | logic carry, carry_d; 11 | always@(posedge clk or posedge rst) 12 | if(rst) carry <= 1'b1; 13 | else carry <= carry_d; 14 | 15 | ADD #(.N(1)) ADD( 16 | .A(g_input), 17 | .B(~e_input), 18 | .CI(carry), 19 | .S(), 20 | .CO(carry_d) 21 | ); 22 | 23 | assign o = carry_d; 24 | 25 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/Simulation/mxm_nnbit_mk1dim_mkcc.do: -------------------------------------------------------------------------------- 1 | vlog -reportprogress 300 -work work ../vdp/*.sv 2 | vsim -gui work.tb_mxm_nnbit_mk1dim_mkcc -L TG_SynLib 3 | 4 | add wave \ 5 | sim:/tb_mxm_nnbit_mk1dim_mkcc/clk \ 6 | sim:/tb_mxm_nnbit_mk1dim_mkcc/rst \ 7 | sim:/tb_mxm_nnbit_mk1dim_mkcc/m \ 8 | sim:/tb_mxm_nnbit_mk1dim_mkcc/l \ 9 | sim:/tb_mxm_nnbit_mk1dim_mkcc/g_input \ 10 | sim:/tb_mxm_nnbit_mk1dim_mkcc/e_input \ 11 | sim:/tb_mxm_nnbit_mk1dim_mkcc/o \ 12 | sim:/tb_mxm_nnbit_mk1dim_mkcc/O_ref \ 13 | 14 | run -all 15 | 16 | -------------------------------------------------------------------------------- /Benchmarks2/compile_yos_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn_all 3 | echo "./compile_yos_all.sh. use -s to skip synthesis" 4 | if [ "$1" == "-s" ] 5 | then 6 | echo "skipping synthesis" 7 | for d in * 8 | do 9 | ( cp ${d%/*}/syn/*.v syn_all) 10 | done 11 | else 12 | for d in * 13 | do 14 | ( cd "$d" && ./compile.sh && cd ".." && cp ${d%/*}/syn/*.v syn_all) 15 | done 16 | fi 17 | for verilogfile in syn_all/*.v 18 | do 19 | empfile=${verilogfile%.*}.emp 20 | ../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 21 | done 22 | wait -------------------------------------------------------------------------------- /Benchmarks/float/DW_fp_log2_inst.v: -------------------------------------------------------------------------------- 1 | module DW_fp_log2_inst( inst_a, z_inst, status_inst ); 2 | 3 | parameter sig_width = 10; 4 | parameter exp_width = 5; 5 | parameter ieee_compliance = 0; 6 | parameter extra_prec = 0; 7 | parameter arch = 2; 8 | 9 | input [sig_width+exp_width : 0] inst_a; 10 | output [sig_width+exp_width : 0] z_inst; 11 | output [7 : 0] status_inst; 12 | 13 | // Instance of DW_fp_log2 14 | DW_fp_log2 #(sig_width, exp_width, ieee_compliance, extra_prec, arch) 15 | U1 ( .a(inst_a), .z(z_inst), .status(status_inst) ); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/TwosComplement.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module TwosComplement #(parameter N = 8)( 4 | input [N-1:0] A, 5 | output [N-1:0] O 6 | ); 7 | 8 | ADD #(.N(N)) ADD( 9 | .A(~A), 10 | .B({N{1'b0}}), 11 | .CI(1'b1), 12 | .S(O), 13 | .CO() 14 | ); 15 | 16 | 17 | endmodule 18 | 19 | module signRecover #(parameter N = 8)( 20 | input [N-1:0] A, 21 | input s, 22 | output [N-1:0] O 23 | ); 24 | 25 | ADD #(.N(N)) ADD( 26 | .A(A^{N{s}}), 27 | .B({N{1'b0}}), 28 | .CI(s), 29 | .S(O), 30 | .CO() 31 | ); 32 | 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/mac_comb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mac_comb #(parameter N = 8, K = 3, L = 2*(N-1)+K)( //N: input bit-width, K: vector dimension 4 | input signed [N-1:0] A, 5 | input signed [N-1:0] B, 6 | input signed [L-1:0] S0, 7 | output signed [L-1:0] S 8 | ); 9 | 10 | logic signed [2*N-2:0] P; 11 | logic signed [L:0] S_; 12 | 13 | MULT_ #(.N(N), .M(N)) MULT_( 14 | .A(A), 15 | .B(B), 16 | .O(P) 17 | ); 18 | 19 | ADD_ #(.N(L), .M(2*N-1)) ADD_( 20 | .A(S0), 21 | .B(P), 22 | .O(S_) 23 | ); 24 | 25 | assign S = S_[L-1:0]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Benchmarks2/compile_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn_all 3 | echo "./compile_all.sh. use -s to skip synthesis" 4 | if [ "$1" == "-s" ] 5 | then 6 | echo "skipping synthesis" 7 | for d in * 8 | do 9 | ( cp ${d%/*}/syn/*.v syn_all & ) 10 | done 11 | else 12 | for d in * 13 | do 14 | ( cd "$d" && ./compile.sh -d && rm *.pvl *.syn *.mr *.log *.svf && cd ".." && cp ${d%/*}/syn/*.v syn_all) 15 | done 16 | fi 17 | #for verilogfile in syn_all/*.v 18 | #do 19 | # empfile=${verilogfile%.*}.emp 20 | # ../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std & 21 | #done 22 | #wait -------------------------------------------------------------------------------- /Benchmarks/float/fp_ln.v: -------------------------------------------------------------------------------- 1 | module fp_ln (g_input, e_input, o); 2 | 3 | parameter sig_width = 23; 4 | parameter exp_width = 8; 5 | parameter ieee_compliance = 0; 6 | parameter extra_prec = 0; 7 | parameter arch = 2; 8 | 9 | input [sig_width+exp_width : 0] g_input; 10 | input [sig_width+exp_width : 0] e_input; 11 | wire [sig_width+exp_width : 0] num; 12 | output [sig_width+exp_width : 0] o; 13 | 14 | assign num = g_input ^ e_input; 15 | 16 | // Instance of DW_fp_log2 17 | DW_fp_ln #(sig_width, exp_width, ieee_compliance, extra_prec, arch) 18 | U1 ( .a(num), .z(o), .status() ); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /Benchmarks2/maxpool/maxpool_nbit_kdim_kcc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module maxpool_nbit_kdim_kcc #(parameter N = 8)( 4 | input clk, rst, 5 | input [N-1:0] s_input, 6 | output [N-1:0] o 7 | ); 8 | 9 | logic [N-1:0] o_reg; 10 | logic sel; 11 | 12 | always@(posedge clk or posedge rst) begin 13 | if(rst) o_reg <= {N{1'b0}}; 14 | else o_reg <= o; 15 | end 16 | 17 | COMP #(.N(N)) COMP( //A >= B => O = 1; 18 | .A(s_input), 19 | .B(o_reg), 20 | .O(sel) 21 | ); 22 | 23 | MUX #(.N(N)) MUX( 24 | .A(o_reg), 25 | .B(s_input), 26 | .S(sel), 27 | .O(o) 28 | ); 29 | 30 | endmodule -------------------------------------------------------------------------------- /Benchmarks/float/fp_exp.v: -------------------------------------------------------------------------------- 1 | module fp_exp (g_input, e_input, o); 2 | 3 | parameter sig_width = 23; 4 | parameter exp_width = 8; 5 | parameter ieee_compliance = 0; 6 | parameter extra_prec = 0; 7 | parameter arch = 2; 8 | 9 | input [sig_width+exp_width : 0] g_input; 10 | input [sig_width+exp_width : 0] e_input; 11 | wire [sig_width+exp_width : 0] num; 12 | output [sig_width+exp_width : 0] o; 13 | 14 | assign num = g_input ^ e_input; 15 | 16 | // Instance of DW_fp_log2 17 | DW_fp_exp #(sig_width, exp_width, ieee_compliance, extra_prec, arch) 18 | U1 ( .a(num), .z(o), .status() ); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /Benchmarks/README.md: -------------------------------------------------------------------------------- 1 | # Benchmarks 2 | This directory contains implementations of benchmark functions for 2-party GC. 3 | 4 | For multi-party benchmarks visit [here](https://github.com/sadeghriazi/mpc-circuits). 5 | 6 | ## Compile a benchmark 7 | Go inside `benchmark`, where benchmark is the name of the function 8 | and compile the benchmark to generate the netlist: 9 | ``` 10 | $ cd benchmark 11 | $ ./compile 12 | ``` 13 | 14 | By default, it creates `benchmark_syn.v` in the directory `benchmark/syn`. 15 | 16 | To compile all the benchmarks run `compile_all`. It will save the compiled files in a directory named `syn_all` -------------------------------------------------------------------------------- /Benchmarks/float/fp_log2.v: -------------------------------------------------------------------------------- 1 | module fp_log2 (g_input, e_input, o); 2 | 3 | parameter sig_width = 23; 4 | parameter exp_width = 8; 5 | parameter ieee_compliance = 0; 6 | parameter extra_prec = 0; 7 | parameter arch = 2; 8 | 9 | input [sig_width+exp_width : 0] g_input; 10 | input [sig_width+exp_width : 0] e_input; 11 | wire [sig_width+exp_width : 0] num; 12 | output [sig_width+exp_width : 0] o; 13 | 14 | assign num = g_input ^ e_input; 15 | 16 | // Instance of DW_fp_log2 17 | DW_fp_log2 #(sig_width, exp_width, ieee_compliance, extra_prec, arch) 18 | U1 ( .a(num), .z(o), .status() ); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /Benchmarks2/aes/tb_aes_1cc.sv: -------------------------------------------------------------------------------- 1 | `include "../Headers/Common_H.vh" 2 | `timescale 1ns / 1ps 3 | 4 | module tb_aes_1cc; 5 | 6 | reg [127:0] g_input; 7 | reg [127:0] e_input; 8 | wire [127:0] o; 9 | reg [127:0] o_ref; 10 | 11 | aes_1cc uut ( 12 | .g_input(g_input), 13 | .e_input(e_input), 14 | .o(o) 15 | ); 16 | 17 | 18 | initial begin 19 | g_input = changeEndian(128'he4dc18adf3d05ec9e4dcc41acb990007); 20 | e_input = changeEndian(128'h4072da1240f930f7d3c8cf8b9322042e); 21 | o_ref = changeEndian(128'hd225406f484809186cb5d86be4098445); 22 | #100; 23 | $display("%H\n%H", o, o_ref); 24 | $stop; 25 | end 26 | 27 | endmodule -------------------------------------------------------------------------------- /ProgInt/lt/lt.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -defer -sv lt.sv 6 | hierarchy -check -top lt -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/lt_${N}bit.v 15 | } 16 | -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/SHIFT_LEFT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // synopsys_ template 4 | module SHIFT_LEFT 5 | #( 6 | parameter N=16 7 | ) 8 | ( 9 | a, 10 | shift_amount, 11 | o 12 | ); 13 | 14 | localparam LOG_N = $clog2(N); 15 | 16 | input [N-1:0] a; 17 | input [LOG_N:0] shift_amount; 18 | output [N-1:0] o; 19 | 20 | 21 | wire [N-1:0] ai[LOG_N+1:0]; 22 | 23 | assign ai[0] = a; 24 | 25 | genvar i; 26 | generate 27 | for (i = 0; i < LOG_N+1; i = i + 1) begin: ASSIGN 28 | assign ai[i+1] = (shift_amount[i])?(ai[i]>>2**i):(ai[i]); 29 | end 30 | endgenerate 31 | 32 | assign o = ai[LOG_N+1]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /demo/vdp/mac.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach N [list 4 8 16] { 4 | foreach L [list 32] { 5 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -overwrite -defer -sv mac.sv 7 | hierarchy -check -top mac_TG -chparam N $N -chparam L $L 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | write_verilog -noattr -noexpr -nohex syn/mac_${N}_${N}_${L}bit.v 15 | } 16 | } -------------------------------------------------------------------------------- /ProgInt/sub/sub.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -defer -sv sub.sv 6 | hierarchy -check -top sub -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/sub_${N}bit.v 15 | } 16 | -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/SHIFT_RIGHT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // synopsys_ template 4 | module SHIFT_RIGHT 5 | #( 6 | parameter N=16 7 | ) 8 | ( 9 | a, 10 | shift_amount, 11 | o 12 | ); 13 | 14 | localparam LOG_N = $clog2(N); 15 | 16 | input [N-1:0] a; 17 | input [LOG_N:0] shift_amount; 18 | output [N-1:0] o; 19 | 20 | 21 | wire [N-1:0] ai[LOG_N+1:0]; 22 | 23 | assign ai[0] = a; 24 | 25 | genvar i; 26 | generate 27 | for (i = 0; i < LOG_N+1; i = i + 1) begin: ASSIGN 28 | assign ai[i+1] = (shift_amount[i])?(ai[i]<<2**i):(ai[i]); 29 | end 30 | endgenerate 31 | 32 | assign o = ai[LOG_N+1]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Benchmarks/matrix_mult/matrix_mult_N_M_3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys template 3 | module matrix_mult_N_M_3 4 | #( 5 | parameter N=3, 6 | parameter M=32 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | input clk,rst; 16 | input[M-1:0] g_input; 17 | input[M-1:0] e_input; 18 | output[M-1:0] o; 19 | 20 | wire [2*M-1:0] xy; 21 | reg [M-1:0] o_reg; 22 | 23 | assign xy = g_input*e_input; 24 | assign o = xy[M-1:0] + o_reg; 25 | 26 | always@(posedge clk or posedge rst) 27 | begin 28 | if(rst) 29 | begin 30 | o_reg <= 'b0; 31 | end 32 | else 33 | begin 34 | o_reg <= o; 35 | end 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /Benchmarks/cordic/barrel_shifter_left.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "cordic.vh" 3 | 4 | // synopsys_ template 5 | module barrel_shifter_left 6 | #( 7 | parameter N=16 8 | ) 9 | ( 10 | a, 11 | shift, 12 | o 13 | ); 14 | 15 | localparam LOG_N = $clog2(N); 16 | 17 | input [N-1:0] a; 18 | input [LOG_N:0] shift; 19 | output [N-1:0] o; 20 | 21 | 22 | wire [N-1:0] ai[LOG_N+1:0]; 23 | 24 | assign ai[0] = a; 25 | 26 | genvar i; 27 | generate 28 | for (i = 0; i < LOG_N+1; i = i + 1) begin: ASSIGN 29 | assign ai[i+1] = (shift[i])?(ai[i]>>2**i):(ai[i]); 30 | end 31 | endgenerate 32 | 33 | assign o = ai[LOG_N+1]; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /ProgInt/relu/relu.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach N [list 28] { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv relu.sv 6 | hierarchy -check -top relu -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/relu_${N}bit.v 15 | } -------------------------------------------------------------------------------- /ProgInt/compile_yos_all.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | mkdir -p syn_all 3 | echo "./compile_yos_all.sh. use -s to skip synthesis" 4 | if [ "$1" == "-s" ] 5 | then 6 | echo "skipping synthesis" 7 | for d in * 8 | do 9 | ( cp ${d%/*}/syn/*.v syn_all) 10 | done 11 | else 12 | for d in * 13 | do 14 | ( cd "$d" && ./compile.sh && cd ".." && cp ${d%/*}/syn/*.v syn_all) 15 | done 16 | fi 17 | for verilogfile in syn_all/*.v 18 | do 19 | empfile=${verilogfile%.*}.emp 20 | ../Verilog2EMP/bin/V2EMP_Main -i $verilogfile -o $empfile --log2std 21 | ../../tinygarble2/bin/readCircuitFile -i $empfile & 22 | done 23 | wait 24 | 25 | cp syn_all/*.bin ../../tinygarble2/tinygarble/netlists_pi/ -------------------------------------------------------------------------------- /ProgInt/max/max.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv max.sv 6 | hierarchy -check -top max -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/max_${N}bit.v 15 | } -------------------------------------------------------------------------------- /ProgInt/min/min.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv min.sv 6 | hierarchy -check -top min -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/min_${N}bit.v 15 | } -------------------------------------------------------------------------------- /SynthesisLibrary/script/count.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | echo "$1" 3 | 4 | 5 | grep -w -c 'AND' $1 6 | grep -w -c 'ANDN' $1 7 | grep -w -c 'NAND' $1 8 | grep -w -c 'NANDN' $1 9 | grep -w -c 'OR' $1 10 | grep -w -c 'ORN' $1 11 | grep -w -c 'NOR' $1 12 | grep -w -c 'NORN' $1 13 | grep -w -c 'MUX' $1 14 | grep -w -c 'FA' $1 15 | grep -w -c 'HA' $1 16 | grep -w -c 'HADDER' $1 17 | grep -w -c 'FADDER' $1 18 | grep -w -c 'XOR' $1 19 | grep -w -c 'XNOR' $1 20 | grep -w -c 'IV' $1 21 | grep -w -c 'DFF' $1 22 | 23 | echo -n "total non-XOR: " 24 | grep -w -c 'AND\|ANDN\|NAND\|NANDN\|OR\|ORN\|NOR\|NORN\|MUX\|FA\|HA\|HADDER\|FADDER' $1 25 | echo -n "total XOR: " 26 | grep -w -c 'XOR\|XNOR\|IV\|DFF' $1 -------------------------------------------------------------------------------- /ProgInt/mult/mult.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv mult.sv 6 | hierarchy -check -top mult -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/mult_${N}bit.v 15 | } -------------------------------------------------------------------------------- /Benchmarks2/aes/aes_1cc.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | read_verilog ../../SynthesisLibrary/syn_lib/*.v 4 | 5 | read_verilog -sv aes_1cc.sv AddRoundKey.sv KeyExpansionSeq.sv KeyExpansion.sv MixColumns.sv ShiftRows.sv SubBytes.sv 6 | hierarchy -check -top aes_1cc 7 | procs; opt; flatten; opt; 8 | techmap ; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/aes_1cc_syn.v -------------------------------------------------------------------------------- /ProgInt/add/add.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | #foreach N [list 1] { 4 | for {set N 1} {$N < 65} {incr N} { 5 | read_verilog -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -defer -sv add.sv 7 | hierarchy -check -top add -chparam N $N 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 15 | write_verilog -noattr -noexpr -nohex syn/add_${N}bit.v 16 | } -------------------------------------------------------------------------------- /Benchmarks/cordic/barrel_shifter_left_test.v: -------------------------------------------------------------------------------- 1 | `include "cordic.vh" 2 | 3 | module barrel_shifter_left_test(); 4 | 5 | localparam N = 16; 6 | localparam LOG_N = $clog2(N); 7 | 8 | reg [N-1:0] a; 9 | reg [LOG_N:0] shift; 10 | wire [N-1:0] o; 11 | 12 | barrel_shifter_left 13 | #( 14 | .N(N) 15 | ) 16 | _barrel_shifter_left_ 17 | ( 18 | .a(a), 19 | .shift(shift), 20 | .o(o) 21 | ); 22 | 23 | initial begin 24 | a = 16'hAAAA; 25 | shift = 5'h00; 26 | #10 27 | shift = 5'h01; 28 | #10 29 | shift = 5'h02; 30 | #10 31 | shift = 5'h0F; 32 | #10 33 | shift = 5'h10; 34 | #10 35 | $stop; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /ProgInt/ifelse/ifelse.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 1} {$N < 65} {incr N} { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv ifelse.sv 6 | hierarchy -check -top ifelse -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/ifelse_${N}bit.v 15 | } -------------------------------------------------------------------------------- /Benchmarks/sha3/test/sha3_test.v: -------------------------------------------------------------------------------- 1 | module sha3_test(); 2 | 3 | reg clk; 4 | reg rst; 5 | 6 | reg [575:0] in; 7 | wire [1599:0] out; 8 | 9 | parameter CC = 6; 10 | sha3_seq #(.CC(CC))UUT(clk, rst, in, out); 11 | 12 | integer i; 13 | initial 14 | begin 15 | clk = 0; 16 | rst = 1; 17 | in = 576'h933e63aa2ca8f246c9c9cb75fbff5e345c41b285030a19243bb6edac7b3e595f65a04004217e2f818b63a9a54294f96cd012e70c5f7f7e8f998b57997cf4ecddea49b42d459db0c1; 18 | @(negedge clk); 19 | rst = 0; 20 | for(i=0;i>>shift_amount; 30 | `SHIFT_RIGHT_UNSIGNED: 31 | c_shift<=value>>shift_amount; 32 | endcase 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /Benchmarks/matrix_mult/test/matrixMultSeqTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module matrixMultSeqTest(); 4 | 5 | parameter N=3; 6 | parameter M=32; 7 | reg clk, rst; 8 | 9 | reg[M*N*N-1:0] x; 10 | reg[M*N*N-1:0] y; 11 | wire[M*N*N-1:0] o; 12 | 13 | 14 | matrixMultSeq 15 | #( 16 | .N(N), 17 | .M(M) 18 | ) 19 | UTT 20 | ( 21 | .clk(clk), 22 | .x(x), 23 | .y(y), 24 | .o(o) 25 | ); 26 | 27 | integer i; 28 | initial 29 | begin 30 | clk=0; 31 | x = {N*N*M/32{$random}}; 32 | y = {N*N*M/32{$random}}; 33 | for(i=0;i/SynthesisLibrary/syn_lib/*.v 2 | read_verilog 3 | hierarchy -check -top 4 | proc; opt; flatten; opt; 5 | techmap ; opt; 6 | dfflibmap -liberty /SynthesisLibrary/lib/asic_cell_yosys.lib -script /SynthesisLibrary/lib/script.abc; #change library for EMP or BMR 7 | abc -liberty /SynthesisLibrary/lib/asic_cell_yosys.lib -script /SynthesisLibrary/lib/script.abc; #change library for EMP or BMR 8 | opt; clean; opt; 9 | opt_clean -purge 10 | stat -liberty /SynthesisLibrary/lib/asic_cell_yosys.lib 11 | write_verilog -noattr -noexpr _syn_yos.v 12 | exit -------------------------------------------------------------------------------- /Benchmarks2/maxpool/maxpool.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach N [list 9 16 18 20 32 34 36 64 66 68] { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer -sv maxpool_nbit_kdim_kcc.sv 6 | hierarchy -check -top maxpool_nbit_kdim_kcc -chparam N $N 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/maxpool_${N}bit_kdim_kcc_syn.v 15 | } -------------------------------------------------------------------------------- /Benchmarks2/relu/tb_relu_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_relu_nbit_1cc; 4 | 5 | parameter N = 8; 6 | 7 | logic signed [N-1:0] s_input; 8 | logic signed [N-2:0] o, o_ref; 9 | 10 | sum_nbit_1cc #(.N(N)) uut( 11 | .s_input(s_input), 12 | .o(o) 13 | ); 14 | 15 | assign o_ref = (s_input > 0)? s_input : {(N-1){1'b0}}; 16 | 17 | initial begin 18 | s_input = 'd99; 19 | #100; 20 | $display("s_input = %H, o = %H, o_ref = %H", s_input, o, o_ref); 21 | #100; 22 | s_input = 'd0; 23 | #100; 24 | $display("s_input = %H, o = %H, o_ref = %H", s_input, o, o_ref); 25 | #100; 26 | s_input = -'d67; 27 | #100; 28 | $display("s_input = %H, o = %H, o_ref = %H", s_input, o, o_ref); 29 | $stop(); 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /ProgInt/mac/mac.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 2} {$N < 65} {incr N} { 4 | for {set M 2} {$M < 65} {incr M} { 5 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -overwrite -defer -sv mac.sv 7 | hierarchy -check -top mac -chparam N $N -chparam M $M 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 15 | write_verilog -noattr -noexpr -nohex syn/mac_${N}_${M}_64bit.v 16 | } 17 | } -------------------------------------------------------------------------------- /Benchmarks/div/div.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog div_r.v 8 | 9 | elaborate div_r -architecture verilog -library DEFAULT -update 10 | set_max_area -ignore_tns 0 11 | set_flatten false -design * 12 | set_structure false -design * 13 | set_resource_allocation area_only 14 | report_compile_options 15 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 16 | write -hierarchy -format verilog -output syn/div_r_syn_comb.v 17 | 18 | exit 19 | -------------------------------------------------------------------------------- /Benchmarks2/vdp/mac.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach N [list 4 8 16 32] { 4 | foreach K [list 3 5 7 9] { 5 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -overwrite -defer -sv mac_nnbit_kcc.sv 7 | hierarchy -check -top mac_nnbit_kcc -chparam N $N -chparam K $K 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 15 | write_verilog -noattr -noexpr -nohex syn/mac_${N}_${N}bit\_${K}cc.v 16 | } 17 | } -------------------------------------------------------------------------------- /Benchmarks2/Headers/Common_H.vh: -------------------------------------------------------------------------------- 1 | `ifndef _COMMON_H_ 2 | `define _COMMON_H_ 3 | 4 | function automatic integer log2; 5 | input [31:0] value; 6 | logic [31:0] temp; 7 | begin 8 | temp = value - 1; 9 | for (log2 = 0; temp > 0; log2 = log2 + 1) 10 | temp = temp >> 1; 11 | end 12 | endfunction 13 | 14 | function automatic [127:0] changeEndian; 15 | input [127:0] text; 16 | begin 17 | changeEndian = { 18 | text[7:0], 19 | text[15:8], 20 | text[23:16], 21 | text[31:24], 22 | text[39:32], 23 | text[47:40], 24 | text[55:48], 25 | text[63:56], 26 | text[71:64], 27 | text[79:72], 28 | text[87:80], 29 | text[95:88], 30 | text[103:96], 31 | text[111:104], 32 | text[119:112], 33 | text[127:120] 34 | }; 35 | end 36 | endfunction 37 | `endif -------------------------------------------------------------------------------- /ProgInt/div/div_nm_2_n.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 2} {$N < 65} {incr N} { 4 | for {set M 2} {$M < 65} {incr M} { 5 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -overwrite -defer -sv div_nm_2_n.sv 7 | hierarchy -check -top div_nm_2_n -chparam N $N -chparam M $M 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 15 | write_verilog -noattr -noexpr -nohex syn/div_${N}_${M}_${N}bit.v 16 | } 17 | } -------------------------------------------------------------------------------- /ProgInt/mult_n_2_2n/mult_n_2_2n.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | for {set N 2} {$N < 65} {incr N} { 4 | for {set M 2} {$M < 65} {incr M} { 5 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 6 | read_verilog -overwrite -defer -sv mult_n_2_2n.sv 7 | hierarchy -check -top mult_n_2_2n -chparam N $N -chparam M $M 8 | procs; opt; flatten; opt; 9 | techmap; opt; 10 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 11 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 12 | opt; clean; opt; 13 | opt_clean -purge 14 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 15 | write_verilog -noattr -noexpr -nohex syn/mult_${N}_${M}_[expr {$N+$M-1}]bit.v 16 | } 17 | } -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/MULT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module MULT #(parameter N = 8, M = N) 4 | ( 5 | input [N-1:0] A, 6 | input [M-1:0] B, 7 | output [N+M-1:0] O 8 | ); 9 | 10 | wire [N+M-1:0] w[N-1:0]; 11 | wire [N+M-1:0] AA[N-1:0]; 12 | wire [N+M-1:0] B_; 13 | 14 | 15 | assign w[0] = (A[0])?B_:0; 16 | assign B_ = {{N{1'b0}}, B}; 17 | assign O = w[N-1]; 18 | 19 | genvar g; 20 | 21 | generate 22 | for(g=1;g= 0;g = g - 1) 18 | begin:DIV_UNIT 19 | if (g > 0) 20 | ADD #(.N(N+M)) SUB( 21 | .A(A_[g+1]), 22 | .B({{(N-g){1'b1}}, ~B, {g{1'b1}}}), 23 | .CI(1'b1), 24 | .S(D[g]), 25 | .CO(O[g]) 26 | ); 27 | else 28 | ADD #(.N(N+M)) SUB( 29 | .A(A_[g+1]), 30 | .B({{(N-g){1'b1}}, ~B}), 31 | .CI(1'b1), 32 | .S(D[g]), 33 | .CO(O[g]) 34 | ); 35 | MUX #(.N(N+M)) MUX( 36 | .A(A_[g+1]), 37 | .B(D[g]), 38 | .S(O[g]), 39 | .O(A_[g]) 40 | ); 41 | end 42 | endgenerate 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /ProgInt/logic2/logic2.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach LOGIC [list 0 1 2] { 4 | if { $LOGIC == 0 } { set name "and" } 5 | if { $LOGIC == 1 } { set name "or" } 6 | if { $LOGIC == 2 } { set name "xor" } 7 | for {set N 1} {$N < 65} {incr N} { 8 | read_verilog -defer ../../SynthesisLibrary/syn_lib/*.v 9 | read_verilog -defer -sv logic2.sv 10 | hierarchy -check -top logic2 -chparam N $N -chparam LOGIC $LOGIC 11 | procs; opt; flatten; opt; 12 | techmap; opt; 13 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 14 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 15 | opt; clean; opt; 16 | opt_clean -purge 17 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 18 | write_verilog -noattr -noexpr -nohex syn/${name}_${N}bit.v 19 | } 20 | } -------------------------------------------------------------------------------- /Benchmarks/div/div_q.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Output o = {quotient,remainder} 4 | 5 | // Please add +incdir+$SYNOPSYS/dw/sim_ver+ to your verilog simulator 6 | // command line (for simulation). 7 | 8 | module div_q(g_input, e_input, o); 9 | parameter width = 32; 10 | parameter tc_mode = 0; 11 | parameter rem_mode = 1; // corresponds to "%" in Verilog 12 | 13 | input [width-1 : 0] g_input; 14 | input [width-1 : 0] e_input; 15 | output [width-1:0 ] o; 16 | 17 | wire [width-1 : 0] quotient; 18 | wire [width-1 : 0] remainder; 19 | 20 | assign o = quotient; 21 | 22 | // Instance of DW_fp_div 23 | // more info: https://www.synopsys.com/dw/ipdir.php?c=DW_fp_div 24 | DW_div #(width, width, tc_mode, rem_mode) 25 | U1 (.a(g_input), .b(e_input), 26 | .quotient(quotient), .remainder(remainder)); 27 | 28 | endmodule 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Benchmarks/div/div_r.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Output o = {quotient,remainder} 4 | 5 | // Please add +incdir+$SYNOPSYS/dw/sim_ver+ to your verilog simulator 6 | // command line (for simulation). 7 | 8 | module div_r(g_input, e_input, o); 9 | parameter width = 32; 10 | parameter tc_mode = 0; 11 | parameter rem_mode = 1; // corresponds to "%" in Verilog 12 | 13 | input [width-1 : 0] g_input; 14 | input [width-1 : 0] e_input; 15 | output [width-1 : 0] o; 16 | 17 | wire [width-1 : 0] quotient; 18 | wire [width-1 : 0] remainder; 19 | 20 | assign o = remainder; 21 | 22 | // Instance of DW_fp_div 23 | // more info: https://www.synopsys.com/dw/ipdir.php?c=DW_fp_div 24 | DW_div #(width, width, tc_mode, rem_mode) 25 | U1 (.a(g_input), .b(e_input), 26 | .quotient(quotient), .remainder(remainder)); 27 | 28 | endmodule 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Benchmarks/argmax/test/testbench.v: -------------------------------------------------------------------------------- 1 | module testbench(); 2 | 3 | parameter S = 5; // 32 number 4 | parameter M = 8; // of 8-bit int 5 | 6 | reg [M-1:0] ini [2**S-1:0]; 7 | wire [(2**S)*M-1:0] in; 8 | wire [M-1:0] max; 9 | wire [S-1:0] ind; 10 | 11 | argmax 12 | #( 13 | .S(S), 14 | .M(M) 15 | ) 16 | uut 17 | ( 18 | .in(in), 19 | .max(max), 20 | .ind(ind) 21 | ); 22 | 23 | 24 | genvar i; 25 | generate 26 | for(i=0;i<2**S;i=i+1) begin:TEST_GEN1 27 | assign in[(i+1)*M-1:i*M] = ini[i]; 28 | end 29 | endgenerate 30 | 31 | integer j; 32 | initial begin 33 | $display("S = %d, M = %d", S, M); 34 | for(j=0;j<2**S;j=j+1) begin 35 | ini[j] = $urandom%100; 36 | $display("ini[%d] = %d",j ,ini[j]); 37 | end 38 | #10 39 | $display("max = %d, ind = %d", max, ind); 40 | $finish; 41 | end 42 | 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /Benchmarks/div/div.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | // Output o = {quotient,remainder} 4 | 5 | // Please add +incdir+$SYNOPSYS/dw/sim_ver+ to your verilog simulator 6 | // command line (for simulation). 7 | 8 | module div(g_input, e_input, o); 9 | parameter width = 32; 10 | parameter tc_mode = 0; 11 | parameter rem_mode = 1; // corresponds to "%" in Verilog 12 | 13 | input [width-1 : 0] g_input; 14 | input [width-1 : 0] e_input; 15 | output [2*width-1:0] o; 16 | 17 | wire [width-1 : 0] quotient; 18 | wire [width-1 : 0] remainder; 19 | 20 | assign o = {quotient,remainder}; 21 | 22 | // Instance of DW_fp_div 23 | // more info: https://www.synopsys.com/dw/ipdir.php?c=DW_fp_div 24 | DW_div #(width, width, tc_mode, rem_mode) 25 | U1 (.a(g_input), .b(e_input), 26 | .quotient(quotient), .remainder(remainder)); 27 | 28 | endmodule 29 | 30 | 31 | 32 | 33 | -------------------------------------------------------------------------------- /Benchmarks/compare/compare.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module compare 4 | #( 5 | parameter N=16384, 6 | parameter CC=1 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | localparam M = N/CC; 16 | 17 | input clk; 18 | input rst; 19 | input[M-1:0] g_input; 20 | input[M-1:0] e_input; 21 | output o; 22 | 23 | reg ci; 24 | wire co; 25 | 26 | ADD 27 | #( 28 | .N(M) 29 | ) 30 | UCOMP 31 | ( 32 | .A(g_input), 33 | .B(~e_input), 34 | .CI(ci), 35 | .S(), 36 | .CO(co) 37 | ); 38 | 39 | assign o = co; 40 | 41 | generate 42 | if(CC>1) 43 | always@(posedge clk or posedge rst) 44 | begin 45 | if(rst) 46 | begin 47 | ci <= 1'b1; 48 | end 49 | else 50 | begin 51 | ci <= co; 52 | end 53 | end 54 | else 55 | always@(*) 56 | begin 57 | ci <= 1'b1; 58 | end 59 | endgenerate 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /Benchmarks/float/float.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library [concat ../../SynthesisLibrary/lib/dff_full/dff_full.db standard.sldb dw_foundation.sldb] 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set synthetic_library [concat standard.sldb dw_foundation.sldb $synthetic_library] 6 | set hdlin_while_loop_iterations 1024 7 | 8 | analyze -format verilog fp_exp.v 9 | 10 | elaborate fp_exp -architecture verilog -library DEFAULT -update 11 | set_max_area -ignore_tns 0 12 | set_flatten false -design * 13 | set_structure false -design * 14 | set_resource_allocation area_only 15 | report_compile_options 16 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 17 | write -hierarchy -format verilog -output syn/fp_exp_syn_comb.v 18 | 19 | exit 20 | -------------------------------------------------------------------------------- /Benchmarks2/aes/tb_aes_11cc.sv: -------------------------------------------------------------------------------- 1 | `include "../Headers/Common_H.vh" 2 | `timescale 1ns / 1ps 3 | 4 | module tb_aes_11cc; 5 | 6 | localparam CC = 1; 7 | 8 | reg clk; 9 | reg rst; 10 | 11 | reg [127:0] g_init; 12 | reg [127:0] e_init; 13 | wire [127:0] o; 14 | reg [127:0] o_ref; 15 | 16 | aes_11cc uut( 17 | .clk(clk), 18 | .rst(rst), 19 | .g_init(g_init), 20 | .e_init(e_init), 21 | .o(o) 22 | ); 23 | 24 | integer i; 25 | initial begin 26 | g_init = changeEndian(128'he4dc18adf3d05ec9e4dcc41acb990007); 27 | e_init = changeEndian(128'h4072da1240f930f7d3c8cf8b9322042e); 28 | o_ref = changeEndian(128'hd225406f484809186cb5d86be4098445); 29 | clk =0; 30 | rst =1; 31 | @(posedge clk); 32 | rst =0; 33 | for(i=0;i<11;i=i+1) begin 34 | @(posedge clk); 35 | end 36 | $display("%H\n%H", o, o_ref); 37 | $stop; 38 | end 39 | 40 | always #50 clk = ~clk; 41 | 42 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/sum/tb_sum_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_sum_nbit_1cc; 4 | 5 | parameter N = 8; 6 | 7 | logic [N-1:0] g_input; 8 | logic [N-1:0] e_input; 9 | logic [N:0] o, o_ref; 10 | 11 | sum_nbit_1cc #(.N(N)) uut( 12 | .g_input(g_input), 13 | .e_input(e_input), 14 | .o(o) 15 | ); 16 | 17 | assign o_ref = g_input + e_input; 18 | 19 | initial begin 20 | g_input = 'hA9; 21 | e_input = 'h7B; 22 | #100; 23 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 24 | #100; 25 | g_input = 'h74; 26 | e_input = 'h9D; 27 | #100; 28 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 29 | #100; 30 | g_input = 'hFF; 31 | e_input = 'hFF; 32 | #100; 33 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 34 | $stop(); 35 | end 36 | 37 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/compare/tb_comp_nbit_1cc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_comp_nbit_1cc; 4 | 5 | parameter N = 8; 6 | 7 | logic [N-1:0] g_input; 8 | logic [N-1:0] e_input; 9 | logic o, o_ref; 10 | 11 | comp_nbit_1cc #(.N(N)) uut( 12 | .g_input(g_input), 13 | .e_input(e_input), 14 | .o(o) 15 | ); 16 | 17 | assign o_ref = (g_input >= e_input); 18 | 19 | initial begin 20 | g_input = 'hA9; 21 | e_input = 'h7B; 22 | #100; 23 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 24 | #100; 25 | g_input = 'h74; 26 | e_input = 'hFD; 27 | #100; 28 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 29 | #100; 30 | g_input = 'hAA; 31 | e_input = 'hAA; 32 | #100; 33 | $display("g_input = %H, e_input = %H, o = %H, o_ref = %H", g_input, e_input, o, o_ref); 34 | $stop(); 35 | end 36 | 37 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/mxv_nnbit_jkdim_relu.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mxv_nnbit_jkdim_relu #(parameter N = 8, J = 3, K = 3, L = 2*(N-1)+K)( //N: input bit-width, (JxK)(Kx1) = (Jx1) 4 | input signed [J*K*N-1:0] g_input, 5 | input signed [K*N-1:0] e_input, 6 | output logic signed [J*(L-1)-1:0] o 7 | ); 8 | 9 | logic signed [J*L-1:0] o_; 10 | logic signed [L-1:0] WX[J-1:0]; 11 | logic signed [L-2:0] R_WX[J-1:0]; 12 | 13 | genvar r; 14 | 15 | generate 16 | for (r = 0; r < J; r = r+1) begin: relu 17 | assign WX[r] = o_[(r+1)*L-1 -: L]; 18 | assign R_WX[r] = WX[r][L-2:0]&{(L-1){~WX[r][L-1]}}; 19 | assign o[(r+1)*(L-1)-1 -: (L-1)] = R_WX[r]; 20 | end 21 | endgenerate 22 | 23 | 24 | mxv_nnbit_jkdim #(.N(N), .J(J), .K(K)) mxv_nnbit_jkdim( //N: input bit-width, (JxK)(Kx1) = (Jx1) 25 | .g_input(g_input), 26 | .e_input(e_input), 27 | .o(o_) 28 | ); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /SynthesisLibrary/script/sample.dcsh: -------------------------------------------------------------------------------- 1 | set path /SynthesisLibrary 2 | set lib_path $path/lib #change library for EMP or BMR 3 | set syn_path $path/syn_lib 4 | set search_path [list . $lib_path/dff_full/ $syn_path] 5 | set target_library $lib_path/dff_full/dff_full.db 6 | set link_library $lib_path/dff_full/dff_full.db 7 | set symbol_library [concat $lib_path/generic.sdb] 8 | set hdlin_while_loop_iterations 2049 9 | analyze -format verilog {} 10 | analyze -format verilog {} 11 | elaborate -architecture verilog -library DEFAULT -update 12 | set_max_area -ignore_tns 0 13 | set_flatten false -design * 14 | set_structure -design * false 15 | set_resource_allocation area_only 16 | report_compile_options 17 | compile -ungroup_all -map_effort low -area_effort low -no_design_rule 18 | write -hierarchy -format verilog -output _syn.v 19 | exit -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/aes_ht_10.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module aes_ht_10 #(parameter COUNTER = 10)( 4 | input [255:0] s_input, // {key, message} 5 | output [127:0] o 6 | ); 7 | 8 | wire [127:0] key, msg; 9 | wire [127:0] nextKey, add_round_key_input, add_round_key_out, sub_byte_out, shift_row_out, mix_col_out; 10 | 11 | assign {key, msg} = s_input; 12 | assign o = add_round_key_out; 13 | 14 | KeyExpansion_ht #(.COUNTER(COUNTER)) e( .key(key), .nextKey(nextKey)); 15 | 16 | parameter addr_sel = (COUNTER==0)? 'b00 : (COUNTER<10)? 'b01 : 'b11; 17 | 18 | assign add_round_key_input = (addr_sel == 2'b0) ? msg : (addr_sel == 2'b1) ? mix_col_out: shift_row_out; 19 | 20 | SubBytes b(.x(msg), .z(sub_byte_out)); 21 | 22 | ShiftRows c(.x(sub_byte_out), .z(shift_row_out)); 23 | 24 | MixColumns d(.x(shift_row_out), .z(mix_col_out)); 25 | 26 | AddRoundKey a(.x(add_round_key_input), .y(key), .z(add_round_key_out)); 27 | 28 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/aes_ht_1.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module aes_ht_1 #(parameter COUNTER = 1)( 4 | input [255:0] s_input, // {key, message} 5 | output [255:0] o 6 | ); 7 | 8 | wire [127:0] key, msg; 9 | wire [127:0] nextKey, add_round_key_input, add_round_key_out, sub_byte_out, shift_row_out, mix_col_out; 10 | 11 | assign {key, msg} = s_input; 12 | assign o = {nextKey, add_round_key_out}; 13 | 14 | KeyExpansion_ht #(.COUNTER(COUNTER)) e( .key(key), .nextKey(nextKey)); 15 | 16 | parameter addr_sel = (COUNTER==0)? 'b00 : (COUNTER<10)? 'b01 : 'b11; 17 | 18 | assign add_round_key_input = (addr_sel == 2'b0) ? msg : (addr_sel == 2'b1) ? mix_col_out: shift_row_out; 19 | 20 | SubBytes b(.x(msg), .z(sub_byte_out)); 21 | 22 | ShiftRows c(.x(sub_byte_out), .z(shift_row_out)); 23 | 24 | MixColumns d(.x(shift_row_out), .z(mix_col_out)); 25 | 26 | AddRoundKey a(.x(add_round_key_input), .y(key), .z(add_round_key_out)); 27 | 28 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/tb_aes_ht.sv: -------------------------------------------------------------------------------- 1 | `include "../Headers/Common_H.vh" 2 | `timescale 1ns / 1ps 3 | 4 | module tb_aes_ht; 5 | 6 | reg [127:0] g_input; 7 | reg [127:0] e_input; 8 | wire [127:0] o; 9 | reg [127:0] o_ref; 10 | 11 | wire [255:0] s [0:9]; 12 | 13 | aes_ht_0 uut_0 ( 14 | .g_input(g_input), 15 | .e_input(e_input), 16 | .o(s[0]) 17 | ); 18 | genvar i; 19 | 20 | generate 21 | for(i = 1; i < 10; i = i + 1) begin:uut 22 | aes_ht_1 #(.COUNTER(i)) uut_ ( 23 | .s_input(s[i-1]), 24 | .o(s[i]) 25 | ); 26 | end 27 | endgenerate 28 | 29 | aes_ht_10 uut_10( 30 | .s_input(s[9]), 31 | .o(o) 32 | ); 33 | 34 | initial begin 35 | g_input = changeEndian(128'he4dc18adf3d05ec9e4dcc41acb990007); 36 | e_input = changeEndian(128'h4072da1240f930f7d3c8cf8b9322042e); 37 | o_ref = changeEndian(128'hd225406f484809186cb5d86be4098445); 38 | #100; 39 | $display("%H\n%H", o, o_ref); 40 | $stop; 41 | end 42 | 43 | endmodule -------------------------------------------------------------------------------- /Benchmarks/mips/test/benchmarks/hamming.s: -------------------------------------------------------------------------------- 1 | # memory configuration 2 | # 0: l 3 | # 1: answer 4 | # 2: A[0] 5 | # 3: A[1] 6 | # ... 7 | # l+1: A[l-1] 8 | # l+2: B[0] 9 | # l+3: B[1] 10 | # l+4: B[2] 11 | # ... 12 | # 2*l+1: B[l-1] 13 | 14 | #hamming distance between A and B with the length of l 15 | hamming: 16 | lw $9, 0($0) #load l into $9 17 | sll $9, $9, 2 #$9 = $9*4 18 | addi $2, $0, 8 #$2 := A 19 | add $3, $2, $9 #$3 := B = A + l 20 | 21 | # addi $10, $0, 0 # answer, no need to reset 22 | addi $9, $9, 8 # l += 2 to compare with the end of A 23 | loop: 24 | beq $2, $9, end # if A == end of A, we are done 25 | 26 | lw $4, 0($2) #load *A 27 | lw $5, 0($3) #load *B 28 | xor $6, $4, $5 # $6==0 if A[i]==B[i] 29 | beq $6, $0, SAME 30 | addi $10, $10, 1 # answer++ 31 | SAME: 32 | addi $2, $2, 4 # A++ 33 | addi $3, $3, 4 # B++ 34 | j loop # jump back to the top 35 | end: 36 | sw $10, 4($0) #store answer 37 | f: 38 | j f #while(1) -------------------------------------------------------------------------------- /Benchmarks/mips/Reg_Bank.v: -------------------------------------------------------------------------------- 1 | `include "../defined.vh" 2 | 3 | 4 | module Reg_Bank 5 | ( 6 | clk, 7 | rst, 8 | rs_index, 9 | rt_index, 10 | rd_index, 11 | reg_source_out, 12 | reg_target_out, 13 | reg_dest_new 14 | ); 15 | 16 | input clk; 17 | input rst; 18 | input [4:0] rs_index; 19 | input [4:0] rt_index; 20 | input [4:0] rd_index; 21 | output [31:0] reg_source_out; 22 | output [31:0] reg_target_out; 23 | input [31:0] reg_dest_new; 24 | 25 | 26 | reg [31:0] registers[31:0]; 27 | 28 | 29 | integer i; 30 | 31 | 32 | assign reg_source_out = registers[rs_index]; 33 | assign reg_target_out = registers[rt_index]; 34 | 35 | 36 | always@(posedge clk or posedge rst) 37 | begin 38 | if(rst) 39 | begin 40 | for(i=0;i<32;i=i+1) 41 | begin 42 | registers[i] <= 32'b0; 43 | end 44 | end 45 | else if(rd_index != 5'b0) 46 | begin 47 | registers[rd_index[4:0]] <= reg_dest_new; 48 | end 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /Benchmarks/compare/compare.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | set hdlin_while_loop_iterations 16384 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v} 8 | 9 | analyze -format verilog compare.v 10 | 11 | 12 | #n = 16384 13 | foreach cc {16384} { 14 | elaborate compare -architecture verilog -library DEFAULT -update -parameters 16384,$cc 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure -design * false 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/compare_syn_16384_$cc.v 22 | } 23 | 24 | exit 25 | -------------------------------------------------------------------------------- /Benchmarks/stack_machine/stackMachine.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | analyze -format verilog stackMachine.v 6 | set hdlin_while_loop_iterations 16384 7 | 8 | ##This works better! 9 | #set_max_area 0 10 | #compile_ultra -exact_map -no_design_rule -area_high_effort_script 11 | # 12 | 13 | foreach N {4 8 16 32 64} { 14 | elaborate stackMachine -architecture verilog -library DEFAULT -update -parameters $N 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure -design * false 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/stackMachine_syn_$N.v 22 | } 23 | 24 | exit 25 | -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/aes_ht_0.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module aes_ht_0 #(parameter COUNTER = 0)( 4 | input [127:0] g_input, // key 5 | input [127:0] e_input, // message 6 | output [255:0] o 7 | ); 8 | 9 | wire [127:0] key, msg; 10 | wire [127:0] nextKey, add_round_key_input, add_round_key_out, sub_byte_out, shift_row_out, mix_col_out; 11 | 12 | assign key = g_input; 13 | assign msg = e_input; 14 | assign o = {nextKey, add_round_key_out}; 15 | 16 | KeyExpansion_ht #(.COUNTER(COUNTER)) e( .key(key), .nextKey(nextKey)); 17 | 18 | parameter addr_sel = (COUNTER==0)? 'b00 : (COUNTER<10)? 'b01 : 'b11; 19 | 20 | assign add_round_key_input = (addr_sel == 2'b0) ? msg : (addr_sel == 2'b1) ? mix_col_out: shift_row_out; 21 | 22 | SubBytes b(.x(msg), .z(sub_byte_out)); 23 | 24 | ShiftRows c(.x(sub_byte_out), .z(shift_row_out)); 25 | 26 | MixColumns d(.x(shift_row_out), .z(mix_col_out)); 27 | 28 | AddRoundKey a(.x(add_round_key_input), .y(key), .z(add_round_key_out)); 29 | 30 | endmodule -------------------------------------------------------------------------------- /Benchmarks/mult/mult.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | set hdlin_while_loop_iterations 16384 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | analyze -format verilog mult.v 10 | 11 | foreach n {64} { 12 | set cc 1 13 | elaborate mult -architecture verilog -library DEFAULT -update -parameters $n,$cc 14 | set_max_area -ignore_tns 0 15 | set_flatten false -design * 16 | set_structure -design * false 17 | set_resource_allocation area_only 18 | report_compile_options 19 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 20 | write -hierarchy -format verilog -output syn/mult_${n}bit_${cc}cc.v 21 | } 22 | exit 23 | -------------------------------------------------------------------------------- /Benchmarks/cordic/cordic_test.v: -------------------------------------------------------------------------------- 1 | `include "cordic.vh" 2 | 3 | module cordic_test(); 4 | 5 | localparam DEC = 2; 6 | localparam FRAC = 14; 7 | localparam MOD = `MOD_CIR; 8 | localparam DIR = `DIR_ROT; 9 | localparam L = DEC + FRAC; 10 | 11 | reg clk; 12 | reg rst; 13 | reg [L-1:0] x; 14 | reg [L-1:0] y; 15 | reg [L-1:0] z; 16 | wire [L-1:0] a; 17 | wire [L-1:0] b; 18 | wire [L-1:0] c; 19 | wire done; 20 | 21 | cordic 22 | #( 23 | .DEC(DEC), 24 | .FRAC(FRAC), 25 | .MOD(MOD), 26 | .DIR(DIR) 27 | ) 28 | _cordic_ 29 | ( 30 | .clk(clk), 31 | .rst(rst), 32 | .x(x), 33 | .y(y), 34 | .z(z), 35 | .a(a), 36 | .b(b), 37 | .c(c), 38 | .done(done) 39 | ); 40 | 41 | always 42 | #5 clk = ~clk; 43 | 44 | initial begin 45 | clk = 0; 46 | rst = 1; 47 | x = 16'h4000; // 1 48 | y = 0; 49 | z = 16'h2182; // 30 deg 50 | #10 51 | rst = 0; 52 | wait(done==1) 53 | #5 54 | $stop; 55 | end 56 | 57 | endmodule 58 | -------------------------------------------------------------------------------- /demo/vdp/mac.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mac_TG #(parameter N = 8, M = N, L = 64)( 4 | input clk, rst, 5 | input signed [N-1:0] g_input, 6 | input signed [M-1:0] e_input, 7 | output signed [L-1:0] o 8 | ); 9 | 10 | mac #(.N(N), .M(M), .L(L)) mac ( 11 | .clk(clk), .rst(rst), 12 | .A(g_input), 13 | .B(e_input), 14 | .Y(o) 15 | ); 16 | 17 | endmodule 18 | 19 | module mac #(parameter N = 8, M = N, L = 64)( 20 | input clk, rst, 21 | input signed [N-1:0] A, 22 | input signed [M-1:0] B, 23 | output signed [L-1:0] Y 24 | ); 25 | 26 | logic signed [M+N-2:0] product; 27 | logic signed [L-1:0] Y_reg; 28 | logic signed [L:0] Y_1; 29 | 30 | always@(posedge clk or posedge rst) begin 31 | if(rst) Y_reg <= {L{1'b0}}; 32 | else Y_reg <= Y; 33 | end 34 | 35 | MULT_ #(.N(N), .M(M)) MULT_( 36 | .A(A), 37 | .B(B), 38 | .O(product) 39 | ); 40 | 41 | ADD_ #(.N(L), .M(M+N-1)) ADD_( 42 | .A(Y_reg), 43 | .B(product), 44 | .O(Y_1) 45 | ); 46 | 47 | assign Y = Y_1[L-1:0]; 48 | 49 | endmodule -------------------------------------------------------------------------------- /Verilog2EMP/emp_circuit.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef CIRCUIT_H_ 20 | #define CIRCUIT_H_ 21 | 22 | #include "common.h" 23 | #include "v_2_EMPCircuit.h" 24 | 25 | 26 | 27 | int WriteCircuit(const ReadCircuit &read_circuit, const string &file_name); 28 | 29 | 30 | #endif /* CIRCUIT_H_ */ 31 | -------------------------------------------------------------------------------- /Benchmarks/public_test/public_test.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | 10 | analyze -format verilog public_test.v 11 | 12 | elaborate public_test -architecture verilog -library DEFAULT -update -parameters 8 13 | set_max_area -ignore_tns 0 14 | set_flatten false -design * 15 | set_structure false -design * 16 | set_resource_allocation area_only 17 | report_compile_options 18 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 19 | write -hierarchy -format verilog -output syn/public_test_syn.v 20 | 21 | 22 | exit 23 | -------------------------------------------------------------------------------- /Benchmarks/float/float_cmp.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys_ template 3 | 4 | module float_cmp(g_input, e_input, o); 5 | parameter sig_width = 23; 6 | parameter exp_width = 8; 7 | parameter ieee_compliance = 0; 8 | 9 | input [sig_width+exp_width:0] g_input; 10 | input [sig_width+exp_width:0] e_input; 11 | output [3:0] o; // {aeqb_inst, altb_inst, agtb_inst, unordered_inst} 12 | 13 | 14 | wire aeqb_inst; 15 | wire altb_inst; 16 | wire agtb_inst; 17 | wire unordered_inst; 18 | 19 | assign o = {aeqb_inst, altb_inst, agtb_inst, unordered_inst}; 20 | 21 | // Instance of DW_fp_cmp 22 | // more info: https://www.synopsys.com/dw/ipdir.php?c=DW_fp_cmp 23 | DW_fp_cmp 24 | #( 25 | sig_width, 26 | exp_width, 27 | ieee_compliance 28 | ) 29 | U1 30 | ( 31 | .a(g_input), 32 | .b(e_input), 33 | .zctr(1'b0), 34 | .aeqb(aeqb_inst), 35 | .altb(altb_inst), 36 | .agtb(agtb_inst), 37 | .unordered(unordered_inst), 38 | .z0(), 39 | .z1(), 40 | .status0(), 41 | .status1() 42 | ); 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /Benchmarks/float/fp_sqrt.v: -------------------------------------------------------------------------------- 1 | module fp_sqrt(g_input, e_input, o); 2 | // first three bits of g_input and e_input are for inst_rnd 3 | 4 | 5 | parameter inst_sig_width = 23; 6 | parameter inst_exp_width = 8; 7 | parameter inst_ieee_compliance = 0; 8 | 9 | 10 | input [inst_sig_width+inst_exp_width + 3: 0] g_input; 11 | input [inst_sig_width+inst_exp_width + 3: 0] e_input; 12 | 13 | output [inst_sig_width+inst_exp_width : 0] o; 14 | 15 | wire [inst_sig_width+inst_exp_width : 0] inst_a; 16 | wire [2 : 0] inst_rnd; 17 | 18 | assign inst_rnd = g_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1] ^ e_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1]; 19 | assign inst_a = g_input[inst_sig_width+inst_exp_width:0] ^ e_input[inst_sig_width+inst_exp_width:0]; 20 | // Instance of DW_fp_sqrt 21 | DW_fp_sqrt #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 ( 22 | .a(inst_a), 23 | .rnd(inst_rnd), 24 | .z(o), 25 | .status() ); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Benchmarks/float/fp_square.v: -------------------------------------------------------------------------------- 1 | module fp_square(g_input, e_input, o); 2 | // first three bits of g_input and e_input are for inst_rnd 3 | 4 | 5 | parameter inst_sig_width = 23; 6 | parameter inst_exp_width = 8; 7 | parameter inst_ieee_compliance = 0; 8 | 9 | 10 | input [inst_sig_width+inst_exp_width + 3: 0] g_input; 11 | input [inst_sig_width+inst_exp_width + 3: 0] e_input; 12 | 13 | output [inst_sig_width+inst_exp_width : 0] o; 14 | 15 | wire [inst_sig_width+inst_exp_width : 0] inst_a; 16 | wire [2 : 0] inst_rnd; 17 | 18 | assign inst_rnd = g_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1] ^ e_input[inst_sig_width+inst_exp_width + 3:inst_sig_width+inst_exp_width+1]; 19 | assign inst_a = g_input[inst_sig_width+inst_exp_width:0] ^ e_input[inst_sig_width+inst_exp_width:0]; 20 | // Instance of DW_fp_sqrt 21 | DW_fp_square #(inst_sig_width, inst_exp_width, inst_ieee_compliance) U1 ( 22 | .a(inst_a), 23 | .rnd(inst_rnd), 24 | .z(o), 25 | .status() ); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Benchmarks/non_secret_test/non_secret_test.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | 10 | analyze -format verilog non_secret_test.v 11 | 12 | elaborate non_secret_test -architecture verilog -library DEFAULT -update -parameters 8 13 | set_max_area -ignore_tns 0 14 | set_flatten false -design * 15 | set_structure false -design * 16 | set_resource_allocation area_only 17 | report_compile_options 18 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 19 | write -hierarchy -format verilog -output syn/non_secret_test.v 20 | 21 | exit 22 | -------------------------------------------------------------------------------- /Verilog2BMR/bmr.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef BMR_BMR_H_ 20 | #define BMR_BMR_H_ 21 | 22 | #include "common.h" 23 | #include "v_2_bmr.h" 24 | //#include "garbled_circuit/garbled_circuit_util.h" 25 | 26 | int WriteBMRcircuit(const ReadBMRCircuit &read_circuit, const string &file_name); 27 | 28 | 29 | #endif /* SCD_SCD_H_ */ 30 | -------------------------------------------------------------------------------- /Benchmarks/select/select.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | analyze -format verilog select.v 10 | 11 | foreach n {64} { 12 | foreach w {32} { 13 | elaborate select -architecture verilog -library DEFAULT -update -parameters $n,$w 14 | set_max_area -ignore_tns 0 15 | set_flatten false -design * 16 | set_structure false -design * 17 | set_resource_allocation area_only 18 | report_compile_options 19 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 20 | write -hierarchy -format verilog -output syn/select$n\_$w.v 21 | } 22 | } 23 | 24 | exit 25 | -------------------------------------------------------------------------------- /Benchmarks/argmax/argmax.v: -------------------------------------------------------------------------------- 1 | module argmax 2 | #( 3 | parameter N=10, // number of inputs 4 | parameter M=32 // input bit-width 5 | ) 6 | ( 7 | in, 8 | max, 9 | ind 10 | ); 11 | 12 | function integer log2; 13 | input [31:0] value; 14 | reg [31:0] temp; 15 | begin 16 | temp = value; 17 | for (log2=0; temp>0; log2=log2+1) 18 | temp = temp>>1; 19 | end 20 | endfunction 21 | 22 | localparam S = log2(N); 23 | 24 | input [M*N-1:0] in; 25 | output [M-1:0] max; 26 | output [S-1:0] ind; 27 | 28 | wire [M-1:0] max_i [N-1:0]; 29 | wire [S-1:0] ind_i [N-1:0]; 30 | wire greater [N-1:0]; 31 | 32 | assign greater[0] = 0; 33 | assign max_i[0] = in[M-1:0]; 34 | assign ind_i[0] = 0; 35 | 36 | genvar g; 37 | generate 38 | for (g=1;g in[(g+1)*M-1:g*M]); 40 | assign max_i[g] = (greater[g]) ? max_i[g-1]: in[(g+1)*M-1:g*M]; 41 | assign ind_i[g] = (greater[g]) ? ind_i[g-1]: g; 42 | end 43 | endgenerate 44 | 45 | assign max = max_i[N-1]; 46 | assign ind = ind_i[N-1]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /Benchmarks/argmax/argmax.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | 10 | analyze -format verilog argmax.v 11 | 12 | foreach N {10} { 13 | foreach M {32} { 14 | elaborate argmax -architecture verilog -library DEFAULT -update -parameters $N,$M 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure false -design * 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/argmax_syn_$N\_$M\_1cc.v 22 | } 23 | } 24 | 25 | 26 | exit 27 | -------------------------------------------------------------------------------- /Benchmarks/mips/Inst_Mem.v: -------------------------------------------------------------------------------- 1 | `include "../defined.vh" 2 | 3 | module Inst_Mem 4 | # 5 | ( 6 | parameter W = 32, 7 | parameter L = 6 8 | ) 9 | ( 10 | clk, 11 | rst, 12 | inst_mem_in_wire, 13 | pc, 14 | opcode 15 | ); 16 | 17 | localparam N = 2**L; 18 | 19 | input clk; 20 | input rst; 21 | // Interface 22 | input [31:2] pc; 23 | output [W-1:0] opcode; 24 | 25 | input [N*W-1:0] inst_mem_in_wire; 26 | 27 | reg [W-1:0] inst_mem_reg [0:N-1]; 28 | 29 | //initialization 30 | wire [W-1:0] inst_mem_in [0:N-1]; 31 | genvar g; 32 | generate 33 | for (g=0;g= M 4 | input [N-1:0] A, 5 | input [M-1:0] B, 6 | output [N:0] O 7 | ); 8 | 9 | wire [N-1:0] BB; 10 | wire CO; 11 | 12 | generate 13 | if (N > M) 14 | assign BB = {{(N-M){B[M-1]}}, B}; 15 | else 16 | assign BB = B; 17 | endgenerate 18 | 19 | MUX #(.N(1)) MUX( 20 | .A(CO), 21 | .B(O[N-1]), 22 | .S(A[N-1]^B[M-1]), 23 | .O(O[N]) 24 | ); 25 | 26 | 27 | ADD #(.N(N)) ADD( 28 | .A(A), 29 | .B(BB), 30 | .CI(1'b0), 31 | .S(O[N-1:0]), 32 | .CO(CO) 33 | ); 34 | 35 | endmodule 36 | 37 | module uADD_ #(parameter N = 8, M = N)( // N >= M 38 | input [N-1:0] A, 39 | input [M-1:0] B, 40 | output [N:0] O 41 | ); 42 | 43 | wire [N-1:0] BB; 44 | wire CO; 45 | 46 | generate 47 | if (N > M) 48 | assign BB = {{(N-M){1'b0}}, B}; 49 | else 50 | assign BB = B; 51 | endgenerate 52 | 53 | assign O[N] = CO; 54 | 55 | 56 | ADD #(.N(N)) ADD( 57 | .A(A), 58 | .B(BB), 59 | .CI(1'b0), 60 | .S(O[N-1:0]), 61 | .CO(CO) 62 | ); 63 | 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/DIV_.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DIV_ #( parameter N = 8, M = N )( 4 | input [N-1:0] A, 5 | input [M-1:0] B, 6 | output [N-1:0] O 7 | ); 8 | 9 | wire [N-1:0] A_; //-A 10 | wire [N-2:0] A__; //abs(A) 11 | wire [M-1:0] B_; //-B 12 | wire [M-2:0] B__; //abs(B) 13 | wire [N-2:0] O_; //abs(O) 14 | wire [N-1:0] O__; //-abs(O) 15 | 16 | TwosComplement #(.N(N)) TwosComplement_A( 17 | .A(A), 18 | .O(A_) 19 | ); 20 | 21 | MUX #(.N(N-1)) MUX_A( 22 | .A(A[N-2:0]), 23 | .B(A_[N-2:0]), 24 | .S(A[N-1]), 25 | .O(A__) 26 | ); 27 | 28 | TwosComplement #(.N(M)) TwosComplement_B( 29 | .A(B), 30 | .O(B_) 31 | ); 32 | 33 | MUX #(.N(M-1)) MUX_B( 34 | .A(B[M-2:0]), 35 | .B(B_[M-2:0]), 36 | .S(B[M-1]), 37 | .O(B__) 38 | ); 39 | 40 | DIV #(.N(N-1), .M(M-1)) DIV ( 41 | .A(A__), 42 | .B(B__), 43 | .O(O_) 44 | ); 45 | 46 | TwosComplement #(.N(N)) TwosComplement_O( 47 | .A({1'b0, O_}), 48 | .O(O__) 49 | ); 50 | 51 | MUX #(.N(N)) MUX_O( 52 | .A({1'b0, O_}), 53 | .B(O__), 54 | .S(A[N-1]^B[M-1]), 55 | .O(O) 56 | ); 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Benchmarks/matrix_mult/matrix_mult.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | set hdlin_while_loop_iterations 16384 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | foreach p {0 1 2 3} { 10 | analyze -format verilog matrix_mult_N_M_${p}.v 11 | } 12 | 13 | set bits 32 14 | #foreach p {3} { 15 | foreach n {3} { 16 | elaborate matrix_mult_N_M_3 -architecture verilog -library DEFAULT -update -parameters $n,$bits 17 | set_max_area -ignore_tns 0 18 | set_flatten false -design * 19 | set_structure -design * false 20 | set_resource_allocation area_only 21 | report_compile_options 22 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 23 | write -hierarchy -format verilog -output syn/matrix_mult_nxn_${bits}bit_n${p}cc.v 24 | #} 25 | } 26 | 27 | exit 28 | -------------------------------------------------------------------------------- /Benchmarks/non_secret_test/non_secret_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys_ template 3 | module non_secret_test 4 | #( 5 | parameter N=8 6 | ) 7 | ( 8 | clk, 9 | rst, 10 | g_input, 11 | e_input, 12 | o 13 | ); 14 | input clk, rst; 15 | input [N-1:0] g_input; 16 | input [N-1:0] e_input; 17 | output [N-1:0] o; 18 | 19 | reg sel; 20 | wire [N-1:0] o_add; 21 | wire [N-1:0] o_sub; 22 | 23 | 24 | always @(posedge clk or posedge rst) begin 25 | if (rst) begin 26 | sel <= 1'b0; 27 | end else begin 28 | sel <= ~sel; 29 | end 30 | end 31 | 32 | //assign o = (sel)?(g_input+e_input):(g_input-e_input); 33 | 34 | ADD 35 | #( 36 | .N(N) 37 | ) 38 | _ADD 39 | ( 40 | .A(g_input), 41 | .B(e_input), 42 | .CI(1'b0), 43 | .S(o_add) 44 | ); 45 | 46 | SUB 47 | #( 48 | .N(N) 49 | ) 50 | _SUB 51 | ( 52 | .A(g_input), 53 | .B(e_input), 54 | .S(o_sub) 55 | ); 56 | 57 | MUX 58 | #( 59 | .N(N) 60 | ) 61 | _MUX 62 | ( 63 | .A(o_add), 64 | .B(o_sub), 65 | .S(sel), 66 | .O(o) 67 | ); 68 | 69 | 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /Benchmarks/public_test/public_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys_ template 3 | module public_test 4 | ( 5 | clk, 6 | rst, 7 | p_init, 8 | g_init, 9 | e_init, 10 | p_input, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | 16 | input clk, rst; 17 | 18 | input [7:0] p_init; 19 | input [15:0] g_init; 20 | input [31:0] e_init; 21 | 22 | input [31:0] p_input; 23 | input [15:0] g_input; 24 | input [7:0] e_input; 25 | output [31:0] o; 26 | 27 | 28 | reg [7:0] reg_1; 29 | reg [15:0] reg_2; 30 | reg [31:0] reg_3; 31 | 32 | wire [31:0] o1; 33 | wire [31:0] o2; 34 | wire [31:0] o3; 35 | 36 | always@(posedge clk or posedge rst) 37 | begin 38 | if(rst) begin 39 | reg_1 <= p_init; 40 | reg_2 <= g_init; 41 | reg_3 <= e_init; 42 | end else begin 43 | reg_1 <= e_input ^ reg_1; 44 | reg_2 <= g_input ^ reg_2; 45 | reg_3 <= p_input ^ reg_3; 46 | end 47 | end 48 | 49 | assign o1 = {24'b0, e_input ^ reg_1}; 50 | assign o2 = {16'b0, g_input ^ reg_2}; 51 | assign o3 = p_input ^ reg_3; 52 | assign o = o1 ^ o2 ^ o3; 53 | 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /Benchmarks/rsa/test/modmult_test.v: -------------------------------------------------------------------------------- 1 | module modmult_test(); 2 | 3 | 4 | parameter N = 8; 5 | parameter CC = N; 6 | 7 | reg clk; 8 | reg rst; 9 | reg start; 10 | reg [N-1:0] x; 11 | reg [N-1:0] y; 12 | reg [N-1:0] n; 13 | 14 | wire [N-1:0] o; 15 | 16 | modmult 17 | #( 18 | .N(N), 19 | .CC(CC) 20 | ) 21 | UUT 22 | ( 23 | .clk(clk), 24 | .rst(rst), 25 | .start(start), 26 | .x(x), 27 | .y(y), 28 | .n(n), 29 | .o(o) 30 | ); 31 | 32 | integer i; 33 | wire [2*N-1:0] xy; 34 | assign xy = x*y; 35 | 36 | initial 37 | begin 38 | x = 'd45; 39 | y = 'd37; 40 | n = 'd107; 41 | clk = 0; 42 | rst = 0; 43 | start = 0; 44 | #1; 45 | rst = 1; 46 | #1; 47 | @(negedge clk); 48 | start = 1; 49 | rst = 0; 50 | @(negedge clk); 51 | start = 0; 52 | for(i=0;i1) 27 | begin 28 | always@(posedge clk or posedge rst) 29 | begin 30 | if(rst) 31 | carry_on <= 0; 32 | else 33 | carry_on <= carry_on_d; 34 | end 35 | end 36 | endgenerate 37 | 38 | generate 39 | if(CC>1) 40 | begin 41 | //assign {carry_on_d, o} = g_input + e_input + carry_on; 42 | ADD 43 | #( 44 | .N(N/CC) 45 | ) 46 | ADD_ 47 | ( 48 | .A(g_input), 49 | .B(e_input), 50 | .CI(carry_on), 51 | .S(o), 52 | .CO(carry_on_d) 53 | ); 54 | end 55 | else 56 | begin 57 | //assign o = g_input + e_input; 58 | ADD 59 | #( 60 | .N(N/CC) 61 | ) 62 | ADD_ 63 | ( 64 | .A(g_input), 65 | .B(e_input), 66 | .CI(1'b0), 67 | .S(o), 68 | .CO() 69 | ); 70 | end 71 | endgenerate 72 | endmodule 73 | 74 | -------------------------------------------------------------------------------- /Benchmarks/knns_td/first_nns_comb_td.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 2049 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v ../../SynthesisLibrary/syn_lib/COUNT.v} 8 | 9 | 10 | analyze -format verilog {first_nns_comb_td.v taxicab_distance.v} 11 | 12 | foreach w {16 32} { 13 | foreach n {128 256} { 14 | elaborate first_nns_comb_td -architecture verilog -library DEFAULT -update -parameters $w,$n 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure -design * false 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -map_effort low -area_effort low -no_design_rule 21 | write -hierarchy -format verilog -output syn/first_nns_comb_td_$w\_$n.v 22 | } 23 | } 24 | 25 | 26 | exit 27 | -------------------------------------------------------------------------------- /Benchmarks/rsa/rsa.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | set hdlin_while_loop_iterations 16384 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/MUX.v} 8 | 9 | analyze -format verilog modexp_1_N.v 10 | analyze -format verilog modexp_2N_NN.v 11 | analyze -format verilog modmult.v 12 | 13 | 14 | 15 | #N = 1024 16 | foreach cc {2097152} { 17 | elaborate modexp_2N_NN -architecture verilog -library DEFAULT -update -parameters 1024,$cc 18 | set_max_area -ignore_tns 0 19 | set_flatten false -design * 20 | set_structure -design * false 21 | set_resource_allocation area_only 22 | report_compile_options 23 | compile -ungroup_all -boundary_optimization -map_effort low -area_effort low -no_design_rule 24 | write -hierarchy -format verilog -output syn/modexp_syn_1024_$cc.v 25 | } 26 | 27 | 28 | exit 29 | 30 | -------------------------------------------------------------------------------- /Verilog2EMP/scheduling.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef SCHEDULING_H_ 20 | #define SCHEDULING_H_ 21 | 22 | #include "v_2_EMPCircuit.h" 23 | 24 | int SortNetlist(ReadCircuit* read_circuit, 25 | const ReadCircuitString& read_circuit_string); 26 | int WriteMapping(const ReadCircuitString& read_circuit_string, 27 | const ReadCircuit &read_circuit, 28 | const string& out_mapping_filename); 29 | 30 | #endif /* SCHEDULING_H_ */ 31 | -------------------------------------------------------------------------------- /Verilog2SCD/scheduling.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef SCD_SCHEDULING_H_ 20 | #define SCD_SCHEDULING_H_ 21 | 22 | #include "v_2_scd.h" 23 | 24 | int SortNetlist(ReadCircuit* read_circuit, 25 | const ReadCircuitString& read_circuit_string); 26 | int WriteMapping(const ReadCircuitString& read_circuit_string, 27 | const ReadCircuit &read_circuit, 28 | const string& out_mapping_filename); 29 | 30 | #endif /* SCD_SCHEDULING_H_ */ 31 | -------------------------------------------------------------------------------- /Verilog2BMR/scheduling.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef BMR_SCHEDULING_H_ 20 | #define BMR_SCHEDULING_H_ 21 | 22 | #include "v_2_bmr.h" 23 | 24 | int SortNetlist(ReadBMRCircuit* read_circuit, 25 | const ReadBMRCircuitString& read_circuit_string); 26 | int WriteMapping(const ReadBMRCircuitString& read_circuit_string, 27 | const ReadBMRCircuit &read_circuit, 28 | const string& out_mapping_filename); 29 | 30 | #endif /* BMR_SCHEDULING_H_ */ 31 | -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/asic_cell_yosys.lib: -------------------------------------------------------------------------------- 1 | library(demo) { 2 | cell(IV) { 3 | area: 1; 4 | pin(A) { direction: input; } 5 | pin(Z) { direction: output; function: "A'"; } 6 | } 7 | cell(XOR) { 8 | area: 1; 9 | pin(A) { direction: input; } 10 | pin(B) { direction: input; } 11 | pin(Z) { direction: output; function: "(A^B)"; } 12 | } 13 | cell(AND) { 14 | area: 100; 15 | pin(A) { direction: input; } 16 | pin(B) { direction: input; } 17 | pin(Z) { direction: output; function: "(A&B)"; } 18 | } 19 | cell(NOR) { 20 | area: 100; 21 | pin(A) { direction: input; } 22 | pin(B) { direction: input; } 23 | pin(Z) { direction: output; function: "(A+B)'"; } 24 | } 25 | cell(NAND) { 26 | area: 100; 27 | pin(A) { direction: input; } 28 | pin(B) { direction: input; } 29 | pin(Z) { direction: output; function: "(A&B)'"; } 30 | } 31 | cell(DFF) { 32 | area: 0; 33 | ff("IQ", "IQN"){clocked_on: CLK; 34 | next_state: D; 35 | preset: I; 36 | clear: RST; } 37 | pin(CLK) { direction: input; 38 | clock: true; } 39 | pin(D) { direction: input; } 40 | pin(Q) { direction: output; 41 | function: "IQ"; } 42 | pin(I) { direction: input; } 43 | pin(RST) { direction: input; } 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib: -------------------------------------------------------------------------------- 1 | library(demo) { 2 | cell(IV) { 3 | area: 0; 4 | pin(A) { direction: input; } 5 | pin(Z) { direction: output; function: "A'"; } 6 | } 7 | cell(XOR) { 8 | area: 0; 9 | pin(A) { direction: input; } 10 | pin(B) { direction: input; } 11 | pin(Z) { direction: output; function: "(A^B)"; } 12 | } 13 | cell(AND) { 14 | area: 1; 15 | pin(A) { direction: input; } 16 | pin(B) { direction: input; } 17 | pin(Z) { direction: output; function: "(A&B)"; } 18 | } 19 | cell(NOR) { 20 | area: 1; 21 | pin(A) { direction: input; } 22 | pin(B) { direction: input; } 23 | pin(Z) { direction: output; function: "(A+B)'"; } 24 | } 25 | cell(NAND) { 26 | area: 1; 27 | pin(A) { direction: input; } 28 | pin(B) { direction: input; } 29 | pin(Z) { direction: output; function: "(A&B)'"; } 30 | } 31 | cell(DFF) { 32 | area: 0; 33 | ff("IQ", "IQN"){clocked_on: CLK; 34 | next_state: D; 35 | preset: I; 36 | clear: RST; } 37 | pin(CLK) { direction: input; 38 | clock: true; } 39 | pin(D) { direction: input; } 40 | pin(Q) { direction: output; 41 | function: "IQ"; } 42 | pin(I) { direction: input; } 43 | pin(RST) { direction: input; } 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /Benchmarks/stack_machine/test/stackMachine_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module stackMachine_test(); 5 | 6 | 7 | parameter N=8; 8 | parameter S=8; 9 | 10 | reg clk, rst; 11 | 12 | reg [N-1:0] x; 13 | reg [2:0] opcode; 14 | 15 | wire [N-1:0] o; 16 | 17 | 18 | 19 | stackMachine #( 20 | .N(N), 21 | .S(S) 22 | ) 23 | UUT 24 | ( 25 | .clk(clk), 26 | .rst(rst), 27 | .x(x), 28 | .opcode(opcode), 29 | .o(o) 30 | ); 31 | 32 | //compute 2+4*5+6 33 | initial 34 | begin 35 | clk = 0; 36 | rst = 1; 37 | x = 0; 38 | opcode = 0; 39 | @(negedge clk); 40 | @(negedge clk); 41 | @(negedge clk); 42 | rst = 0; 43 | x = 2; 44 | opcode = 4;//push 45 | @(negedge clk); 46 | x = 4; 47 | opcode = 4;//push 48 | @(negedge clk); 49 | x = 5; 50 | opcode = 4;//push 51 | @(negedge clk); 52 | opcode = 3;//mult 53 | @(negedge clk); 54 | x = 6; 55 | opcode = 4;//push 56 | @(negedge clk); 57 | opcode = 1;//add 58 | @(negedge clk); 59 | opcode = 1;//add 60 | @(negedge clk); 61 | if (o !== 2+4*5+6) 62 | begin 63 | $display("Error"); 64 | $finish; 65 | end 66 | $display("Good."); 67 | $finish; 68 | end 69 | 70 | always #5 clk=~clk; 71 | 72 | endmodule 73 | -------------------------------------------------------------------------------- /Benchmarks2/aes_ht/MixColumns.sv: -------------------------------------------------------------------------------- 1 | module xtime ( 2 | output [7:0] y, 3 | input [7:0] x 4 | ); 5 | 6 | wire [7:0] w; 7 | assign w = x << 1; 8 | assign y = x[7]? w ^ 8'h1B : w; 9 | 10 | 11 | endmodule 12 | 13 | 14 | module MixColumns( 15 | x, 16 | z); 17 | 18 | input [127:0] x; 19 | output [127:0] z; 20 | 21 | generate 22 | genvar i; 23 | for (i = 0; i < 4; i = i + 1) begin: gen_loop_enc 24 | 25 | wire[7:0] a0, a1, a2, a3, temp; 26 | wire[7:0] b0, b1, b2, b3; 27 | wire[7:0] c0, c1, c2, c3; 28 | 29 | assign a0 = x[8*(4*i+1)-1:8*(4*i+0)]; 30 | assign a1 = x[8*(4*i+2)-1:8*(4*i+1)]; 31 | assign a2 = x[8*(4*i+3)-1:8*(4*i+2)]; 32 | assign a3 = x[8*(4*i+4)-1:8*(4*i+3)]; 33 | assign temp = a0 ^ a1 ^ a2 ^ a3; 34 | 35 | xtime xtime_0(c0, a0 ^ a1); 36 | xtime xtime_1(c1, a1 ^ a2); 37 | xtime xtime_2(c2, a2 ^ a3); 38 | xtime xtime_3(c3, a3 ^ a0); 39 | 40 | assign b0 = a0 ^ temp ^ c0; 41 | assign b1 = a1 ^ temp ^ c1; 42 | assign b2 = a2 ^ temp ^ c2; 43 | assign b3 = a3 ^ temp ^ c3; 44 | 45 | assign z[8*(4*i+1)-1:8*(4*i+0)] = b0; 46 | assign z[8*(4*i+2)-1:8*(4*i+1)] = b1; 47 | assign z[8*(4*i+3)-1:8*(4*i+2)] = b2; 48 | assign z[8*(4*i+4)-1:8*(4*i+3)] = b3; 49 | 50 | end 51 | endgenerate 52 | 53 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/mxv_nnbit_jkdim.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mxv_nnbit_jkdim #(parameter N = 8, J = 3, K = 3, L = 2*(N-1)+K)( //N: input bit-width, (JxK)(Kx1) = (Jx1) 4 | input signed [J*K*N-1:0] g_input, 5 | input signed [K*N-1:0] e_input, 6 | output logic signed [J*L-1:0] o 7 | ); 8 | 9 | logic signed [N-1:0] W[J-1:0][K-1:0]; 10 | logic signed [N-1:0] X[K-1:0]; 11 | logic signed [L-1:0] WX[J-1:0]; 12 | logic signed [L-1:0] P[J-1:0][K:0]; 13 | 14 | genvar r, c; 15 | 16 | generate 17 | for (r = 0; r < J; r = r+1) begin: row 18 | assign P[r][0] = 'd0; 19 | assign WX[r] = P[r][K]; 20 | assign o[(r+1)*L-1 -: L] = WX[r]; 21 | 22 | for (c = 0; c < K; c = c+1) begin: col 23 | assign W[r][c] = g_input[(r*K+c+1)*N-1 -: N]; 24 | 25 | mac_comb #(.N(N), .K(K)) mac_comb( //N: input bit-width, K: vector dimension 26 | .A(W[r][c]), //input signed [N-1:0] 27 | .B(X[c]), //input signed [N-1:0] 28 | .S0(P[r][c]), //input signed [2*N+K-2:0] 29 | .S(P[r][c+1]) //output signed [2*N+K-2:0] 30 | ); 31 | end 32 | end 33 | 34 | for (c = 0; c < K; c = c+1) begin: col_asn 35 | assign X[c] = e_input[(c+1)*N-1 -: N]; 36 | end 37 | endgenerate 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/SUB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module SUB #( parameter N = 8, M = N)( // N >= M 4 | input [N-1:0] A, 5 | input [M-1:0] B, 6 | output CO, 7 | output [N-1:0] S 8 | ); 9 | 10 | wire [N-1:0] BB; 11 | assign BB = {{(N-M){1'b0}}, B}; 12 | 13 | wire C[N:0]; 14 | 15 | assign C[0] = 1'b1; 16 | assign CO = C[N]; 17 | 18 | genvar g,h; 19 | 20 | localparam MAX_LOOP = 512; 21 | 22 | generate 23 | if(N < MAX_LOOP) begin: IF1 24 | for(g=0;g. 17 | */ 18 | 19 | #ifndef SCD_SCD_H_ 20 | #define SCD_SCD_H_ 21 | 22 | #include "common.h" 23 | #include "v_2_scd.h" 24 | 25 | /** 26 | * @brief Read SCD file and initialize garbledCircuit 27 | * 28 | * 29 | * @param param1 SCD file name. 30 | * @param param2 pointer to garbledCircuit. The garbledCircuit will be filled. 31 | * @return 0 in success and -1 in failure. 32 | * 33 | * @see JustGarble paper. 34 | * @see TinyGarble paper. 35 | */ 36 | 37 | int WriteSCD(const ReadCircuit &read_circuit, const string &file_name); 38 | 39 | 40 | #endif /* SCD_SCD_H_ */ 41 | -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/tb_mxv_nnbit_jkdim.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_mxv_nnbit_jkdim; 4 | 5 | parameter N = 8, J = 3, K = 3, L = 2*(N-1)+K; 6 | 7 | logic signed [J*K*N-1:0] g_input; 8 | logic signed [K*N-1:0] e_input; 9 | logic signed [J*L-1:0] o; 10 | 11 | logic signed [N-1:0] W[J-1:0][K-1:0]; 12 | logic signed [N-1:0] X[K-1:0]; 13 | logic signed [L-1:0] WX[J-1:0], WX_ref[J-1:0]; 14 | 15 | integer j, k; 16 | 17 | always_comb begin 18 | for (j = 0; j < J; j = j+1) 19 | for (k = 0; k < K; k = k + 1) 20 | g_input[(j*K+k+1)*N-1 -: N] = W[j][k]; 21 | 22 | for (k = 0; k < K; k = k + 1) 23 | e_input[(k+1)*N-1 -: N] = X[k]; 24 | 25 | for (j = 0; j < J; j = j+1) 26 | WX[j] = o[(j+1)*L-1 -: L]; 27 | 28 | for (j = 0; j < J; j = j+1) begin 29 | WX_ref[j] = 0; 30 | for (k = 0; k < K; k = k + 1) 31 | WX_ref[j] = WX_ref[j] + W[j][k]*X[k]; 32 | end 33 | end 34 | 35 | mxv_nnbit_jkdim #(.N(N), .J(J), .K(K)) uut( //N: input bit-width, (JxK)(Kx1) = (Jx1) 36 | .g_input(g_input), 37 | .e_input(e_input), 38 | .o(o) 39 | ); 40 | 41 | initial begin 42 | W = '{'{-'d1, 'd2, -'d3}, '{'d2, 'd3, -'d4}, '{-'d4, 'd5, 'd7}}; 43 | //W = '{'{'d1, 'd1, 'd1}, '{'d1, 'd1, 'd1}, '{'d1, 'd1, 'd1}}; 44 | X = '{'d2, 'd3, -'d4}; 45 | //X = '{'d3, 'd3, 'd3}; 46 | #100; 47 | $stop(); 48 | end 49 | 50 | 51 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/hamming/hamming.tcl: -------------------------------------------------------------------------------- 1 | yosys -import 2 | 3 | foreach N [list 128 256 1024] { 4 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 5 | read_verilog -overwrite -defer hamming.v 6 | hierarchy -check -top hamming -chparam N $N -chparam CC 1 7 | procs; opt; flatten; opt; 8 | techmap; opt; 9 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 10 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 11 | opt; clean; opt; 12 | opt_clean -purge 13 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 14 | write_verilog -noattr -noexpr -nohex syn/hamming_${N}bit_1cc.v 15 | } 16 | 17 | foreach N [list 32 512] { 18 | read_verilog -overwrite -defer ../../SynthesisLibrary/syn_lib/*.v 19 | read_verilog -overwrite -defer hamming.v 20 | hierarchy -check -top hamming -chparam N $N -chparam CC $N 21 | procs; opt; flatten; opt; 22 | techmap; opt; 23 | dfflibmap -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib 24 | abc -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys.lib -script ../../SynthesisLibrary/lib_EMP/script.abc; 25 | opt; clean; opt; 26 | opt_clean -purge 27 | stat -liberty ../../SynthesisLibrary/lib_EMP/asic_cell_yosys_area.lib 28 | write_verilog -noattr -noexpr -nohex syn/hamming_${N}bit_${N}cc.v 29 | } 30 | -------------------------------------------------------------------------------- /Benchmarks/aes/test/aes_testbench.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys template 3 | 4 | module aes_testbench(); 5 | 6 | localparam CC = 1; 7 | 8 | wire clk; 9 | wire rst; 10 | 11 | wire [127:0] g_input; 12 | wire [127:0] e_input; 13 | wire [127:0] o; 14 | 15 | aes_1cc utt_aes_comb 16 | ( 17 | .clk(clk), 18 | .rst(rst), 19 | .g_input(g_input), 20 | .e_input(e_input), 21 | .o(o) 22 | ); 23 | 24 | assign clk = 0; 25 | assign rst = 0; 26 | assign g_input = 128'h00000000000000000000000000000000; 27 | assign e_input = 128'h00000000000000000000000000000000; 28 | 29 | 30 | initial begin 31 | #5 32 | $stop; 33 | end 34 | 35 | endmodule 36 | 37 | 38 | module aes_testbench_seq(); 39 | 40 | localparam CC = 1; 41 | 42 | reg clk; 43 | reg rst; 44 | 45 | wire [127:0] g_init; 46 | wire [127:0] e_init; 47 | wire [127:0] o; 48 | 49 | aes_11cc utt_aes_seq 50 | ( 51 | .clk(clk), 52 | .rst(rst), 53 | .g_init(g_init), 54 | .e_init(e_init), 55 | .o(o) 56 | ); 57 | 58 | 59 | assign g_init = 128'h00000000000000000000000000000000; 60 | assign e_init = 128'h00000000000000000000000000000000; 61 | 62 | integer i; 63 | initial begin 64 | clk =1; 65 | rst =1; 66 | #3 67 | rst =0; 68 | for(i=0;i<11;i=i+1) begin 69 | @(posedge clk); 70 | end 71 | $stop; 72 | end 73 | 74 | always #5 clk = ~clk; 75 | 76 | endmodule -------------------------------------------------------------------------------- /Benchmarks/aes/aes.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | analyze -format verilog aes_1cc.v 6 | analyze -format verilog aes_11cc.v 7 | analyze -format verilog AddRoundKey.v 8 | analyze -format verilog SubBytes.v 9 | analyze -format verilog ShiftRows.v 10 | analyze -format verilog MixColumns.v 11 | analyze -format verilog KeyExpansion.v 12 | analyze -format verilog KeyExpansionSeq.v 13 | 14 | elaborate aes_11cc -architecture verilog -library DEFAULT -update 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure -design * false 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/aes_11cc.v 22 | 23 | 24 | elaborate aes_1cc -architecture verilog -library DEFAULT -update 25 | set_max_area -ignore_tns 0 26 | set_flatten false -design * 27 | set_structure -design * false 28 | set_resource_allocation area_only 29 | report_compile_options 30 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 31 | write -hierarchy -format verilog -output syn/aes_1cc.v 32 | 33 | 34 | exit 35 | -------------------------------------------------------------------------------- /Benchmarks/knns_td/taxicab_distance.v: -------------------------------------------------------------------------------- 1 | module taxicab_distance #(parameter N = 32)( 2 | input [N-1:0] x1, y1, x2, y2, 3 | output [N+1:0] dist 4 | ); 5 | 6 | wire signed [N:0] dist_x12, dist_x21, dist_xabs, dist_y12, dist_y21, dist_yabs; 7 | 8 | /*SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .S(dist_x12[N-1:0]), .CO(dist_x12[N])); 9 | SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .S(dist_x21[N-1:0]), .CO(dist_x21[N]));*/ 10 | 11 | SUB_1 #(.N(N)) diff_x12 (.A(x1), .B(x2), .D(dist_x12)); 12 | SUB_1 #(.N(N)) diff_x21 (.A(x2), .B(x1), .D(dist_x21)); 13 | 14 | MUX #(.N(N+1)) abs_x (.A(dist_x12), .B(dist_x21), .S(dist_x12[N]), .O(dist_xabs)); 15 | 16 | /*SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .S(dist_y12[N-1:0]), .CO(dist_y12[N])); 17 | SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .S(dist_y21[N-1:0]), .CO(dist_y21[N]));*/ 18 | 19 | SUB_1 #(.N(N)) diff_y12 (.A(y1), .B(y2), .D(dist_y12)); 20 | SUB_1 #(.N(N)) diff_y21 (.A(y2), .B(y1), .D(dist_y21)); 21 | 22 | MUX #(.N(N+1)) abs_y (.A(dist_y12), .B(dist_y21), .S(dist_y12[N]), .O(dist_yabs)); 23 | 24 | ADD #(.N(N+1))t_d (.A(dist_xabs), .B(dist_yabs), .CI(1'b0), .S(dist[N:0]), .CO(dist[N+1])); 25 | 26 | endmodule 27 | 28 | module SUB_1 #(parameter N = 32)( 29 | input [N-1:0] A, B, 30 | output [N:0] D 31 | ); 32 | 33 | wire CO; 34 | assign D[N] = ~CO; 35 | 36 | ADD 37 | #( 38 | .N(N) 39 | ) 40 | ADD_ 41 | ( 42 | .A(A), 43 | .B(~B), 44 | .CI(1'b1), 45 | .S(D[N-1:0]), 46 | .CO(CO) 47 | ); 48 | 49 | endmodule -------------------------------------------------------------------------------- /Benchmarks2/fc_layer/tb_mxv_nnbit_jkdim_relu.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_mxv_nnbit_jkdim_relu; 4 | 5 | parameter N = 8, J = 3, K = 3, L = 2*(N-1)+K; 6 | 7 | logic signed [J*K*N-1:0] g_input; 8 | logic signed [K*N-1:0] e_input; 9 | logic signed [J*(L-1)-1:0] o; 10 | 11 | logic signed [N-1:0] W[J-1:0][K-1:0]; 12 | logic signed [N-1:0] X[K-1:0]; 13 | logic signed [L-2:0] R_WX[J-1:0], R_WX_ref[J-1:0]; 14 | 15 | integer j, k; 16 | 17 | always_comb begin 18 | for (j = 0; j < J; j = j+1) 19 | for (k = 0; k < K; k = k + 1) 20 | g_input[(j*K+k+1)*N-1 -: N] = W[j][k]; 21 | 22 | for (k = 0; k < K; k = k + 1) 23 | e_input[(k+1)*N-1 -: N] = X[k]; 24 | 25 | for (j = 0; j < J; j = j+1) 26 | R_WX[j] = o[(j+1)*(L-1)-1 -: (L-1)]; 27 | 28 | for (j = 0; j < J; j = j+1) begin 29 | R_WX_ref[j] = 0; 30 | for (k = 0; k < K; k = k + 1) 31 | R_WX_ref[j] = R_WX_ref[j] + W[j][k]*X[k]; 32 | if(R_WX_ref[j] < 0) R_WX_ref[j] = 0; 33 | end 34 | end 35 | 36 | mxv_nnbit_jkdim_relu #(.N(N), .J(J), .K(K)) uut( //N: input bit-width, (JxK)(Kx1) = (Jx1) 37 | .g_input(g_input), 38 | .e_input(e_input), 39 | .o(o) 40 | ); 41 | 42 | initial begin 43 | W = '{'{-'d1, 'd2, -'d3}, '{'d2, 'd3, -'d4}, '{-'d4, 'd5, 'd7}}; 44 | //W = '{'{'d1, 'd1, 'd1}, '{'d1, 'd1, 'd1}, '{'d1, 'd1, 'd1}}; 45 | X = '{'d2, 'd3, -'d4}; 46 | //X = '{'d3, 'd3, 'd3}; 47 | #100; 48 | $stop(); 49 | end 50 | 51 | 52 | endmodule -------------------------------------------------------------------------------- /Benchmarks/mult/mult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module mult 4 | #( 5 | parameter N=128, 6 | parameter CC=1 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | 16 | 17 | input clk; 18 | input rst; 19 | input [N-1:0] g_input; 20 | input [N-1:0] e_input; 21 | output [N-1:0] o; 22 | 23 | // input [N/CC-1:0] e_input; 24 | // output [2*N-1:0] o; 25 | 26 | // reg [2*N-1:0] sreg; 27 | // wire [2*N-1:0] swire; 28 | 29 | // wire [N+N/CC-1:0] clocal; 30 | 31 | // assign clocal = g_input*e_input; 32 | 33 | wire [2*N-1:0] o_large; 34 | assign o = o_large[N-1:0]; 35 | 36 | MULT 37 | #( 38 | .N(N), 39 | .M(N/CC) 40 | ) u_MULT ( 41 | .A(g_input), 42 | .B(e_input), 43 | .O(o_large) 44 | ); 45 | 46 | 47 | 48 | // generate 49 | // if(CC>1) begin:g1 50 | // assign swire = sreg + {clocal,{(N-N/CC){1'b0}}}; 51 | // end 52 | // endgenerate 53 | 54 | // generate 55 | // if(CC>1) begin:g2 56 | // always@(posedge clk or posedge rst) begin 57 | // if(rst) begin 58 | // sreg <= 'b0; 59 | // end else begin 60 | // sreg <= {{N/CC{1'b0}},swire[2*N-1:N/CC]}; 61 | // end 62 | // end 63 | // end 64 | // endgenerate 65 | 66 | // generate 67 | // if(CC>1) begin :g3 68 | // assign o = swire; 69 | // end else begin :g4 70 | // assign o = clocal; 71 | // end 72 | // endgenerate 73 | endmodule 74 | -------------------------------------------------------------------------------- /Benchmarks/matrix_mult/matrix_mult_N_M_2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // synopsys template 3 | module matrix_mult_N_M_2 4 | #( 5 | parameter N=3, 6 | parameter M=32 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | input clk,rst; 16 | input[N*M-1:0] g_input; 17 | input[N*M-1:0] e_input; 18 | output reg[M-1:0] o; 19 | 20 | wire [M-1:0] xi[N-1:0]; 21 | wire [M-1:0] yi[N-1:0]; 22 | 23 | wire [2*M-1:0] xyi[N-1:0]; 24 | wire [M-1:0] oi[N:0]; 25 | 26 | genvar i; 27 | 28 | generate 29 | for (i=0;i. 17 | */ 18 | 19 | #ifndef BMR_PARSE_NETLIST_H_ 20 | #define BMR_PARSE_NETLIST_H_ 21 | 22 | #include "v_2_bmr.h" 23 | 24 | string Type2StrGate(short itype); 25 | int ParseNetlist(const string &file_name, 26 | ReadBMRCircuitString* read_circuit_string); 27 | int IdAssignment(const ReadBMRCircuitString& read_circuit_string, 28 | ReadBMRCircuit* read_circuit, uint64_t no_of_parties, vector bits_per_party); 29 | int TopologicalSort(const ReadBMRCircuit &read_circuit, 30 | vector* sorted_list, 31 | const ReadBMRCircuitString& read_circuit_string); 32 | 33 | #endif /* BMR_PARSE_NETLIST_H_ */ 34 | -------------------------------------------------------------------------------- /Benchmarks2/aes/aes.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib_EMP/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib_EMP/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib_EMP/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib_EMP/generic.sdb 5 | analyze -format sverilog aes_1cc.sv 6 | analyze -format sverilog aes_11cc.sv 7 | analyze -format sverilog AddRoundKey.sv 8 | analyze -format sverilog SubBytes.sv 9 | analyze -format sverilog ShiftRows.sv 10 | analyze -format sverilog MixColumns.sv 11 | analyze -format sverilog KeyExpansion.sv 12 | analyze -format sverilog KeyExpansionSeq.sv 13 | 14 | elaborate aes_11cc -architecture verilog -library DEFAULT -update 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure -design * false 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/aes_11cc_syn.v 22 | 23 | 24 | elaborate aes_1cc -architecture verilog -library DEFAULT -update 25 | set_max_area -ignore_tns 0 26 | set_flatten false -design * 27 | set_structure -design * false 28 | set_resource_allocation area_only 29 | report_compile_options 30 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 31 | write -hierarchy -format verilog -output syn/aes_1cc_syn.v 32 | 33 | 34 | exit 35 | -------------------------------------------------------------------------------- /Benchmarks/hamming/hamming.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module hamming 4 | #( 5 | parameter N=8, 6 | parameter CC=1 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | localparam M = N/CC; 16 | 17 | input clk; 18 | input rst; 19 | input[M-1:0] g_input; 20 | input[M-1:0] e_input; 21 | output[log2(N)-1:0] o; 22 | 23 | function integer log2; 24 | input [31:0] value; 25 | reg [31:0] temp; 26 | begin 27 | temp = value; 28 | for (log2=0; temp>0; log2=log2+1) 29 | temp = temp>>1; 30 | end 31 | endfunction 32 | 33 | reg [log2(N)-1:0] oglobal; 34 | wire [log2(M)-1:0] olocal; 35 | wire [M-1:0] xy; 36 | 37 | 38 | assign xy = g_input^e_input; 39 | 40 | 41 | COUNT 42 | #( 43 | .N(M) 44 | ) 45 | COUNT_ 46 | ( 47 | .A(xy), 48 | .S(olocal) 49 | ); 50 | 51 | 52 | 53 | generate 54 | if(CC>1) 55 | begin 56 | ADD 57 | #( 58 | .N(log2(N)) 59 | ) 60 | ADD_ 61 | ( 62 | .A(oglobal), 63 | .B({{(log2(N) - log2(M)){1'b0}}, olocal}), 64 | .CI(1'b0), 65 | .S(o), 66 | .CO() 67 | ); 68 | 69 | always@(posedge clk or posedge rst) 70 | begin 71 | if(rst) 72 | begin 73 | oglobal <= 0; 74 | end 75 | else 76 | begin 77 | oglobal <= o; 78 | end 79 | end 80 | end 81 | else 82 | begin 83 | assign o = olocal; 84 | always@(*) 85 | begin 86 | oglobal <= 'b0; 87 | end 88 | end 89 | endgenerate 90 | 91 | 92 | 93 | endmodule 94 | 95 | 96 | -------------------------------------------------------------------------------- /Benchmarks/sha3/sha3.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | 6 | analyze -format verilog sha3_seq.v 7 | analyze -format verilog sha3_comb.v 8 | analyze -format verilog rconst.v 9 | analyze -format verilog round.v 10 | 11 | 12 | ## It is better! 13 | #set_max_area 0 14 | #compile_ultra -exact_map -no_design_rule -area_high_effort_script 15 | 16 | 17 | #seq 18 | foreach cc {24} { 19 | elaborate sha3_seq -architecture verilog -library DEFAULT -update -parameters $cc 20 | set_max_area -ignore_tns 0 21 | set_flatten false -design * 22 | set_structure -design * false 23 | set_resource_allocation area_only 24 | report_compile_options 25 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 26 | write -hierarchy -format verilog -output syn/sha3_syn_$cc.v 27 | } 28 | 29 | ##comb 30 | #elaborate sha3_comb -architecture verilog -library DEFAULT -update -parameters 1 31 | #set_max_area -ignore_tns 0 32 | #set_flatten false -design * 33 | #set_structure -design * false 34 | #set_resource_allocation area_only 35 | #report_compile_options 36 | #compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 37 | #write -hierarchy -format verilog -output syn/sha3_syn_1.v 38 | 39 | exit 40 | -------------------------------------------------------------------------------- /Benchmarks2/hamming/hamming.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module hamming 4 | #( 5 | parameter N=8, 6 | parameter CC=1 7 | ) 8 | ( 9 | clk, 10 | rst, 11 | g_input, 12 | e_input, 13 | o 14 | ); 15 | localparam M = N/CC; 16 | 17 | input clk; 18 | input rst; 19 | input[M-1:0] g_input; 20 | input[M-1:0] e_input; 21 | output[log2(N)-1:0] o; 22 | 23 | function integer log2; 24 | input [31:0] value; 25 | reg [31:0] temp; 26 | begin 27 | temp = value; 28 | for (log2=0; temp>0; log2=log2+1) 29 | temp = temp>>1; 30 | end 31 | endfunction 32 | 33 | reg [log2(N)-1:0] oglobal; 34 | wire [log2(M)-1:0] olocal; 35 | wire [M-1:0] xy; 36 | 37 | 38 | assign xy = g_input^e_input; 39 | 40 | 41 | COUNT 42 | #( 43 | .N(M) 44 | ) 45 | COUNT_ 46 | ( 47 | .A(xy), 48 | .S(olocal) 49 | ); 50 | 51 | 52 | 53 | generate 54 | if(CC>1) 55 | begin 56 | ADD 57 | #( 58 | .N(log2(N)) 59 | ) 60 | ADD_ 61 | ( 62 | .A(oglobal), 63 | .B({{(log2(N) - log2(M)){1'b0}}, olocal}), 64 | .CI(1'b0), 65 | .S(o), 66 | .CO() 67 | ); 68 | 69 | always@(posedge clk or posedge rst) 70 | begin 71 | if(rst) 72 | begin 73 | oglobal <= 0; 74 | end 75 | else 76 | begin 77 | oglobal <= o; 78 | end 79 | end 80 | end 81 | else 82 | begin 83 | assign o = olocal; 84 | always@(*) 85 | begin 86 | oglobal <= 'b0; 87 | end 88 | end 89 | endgenerate 90 | 91 | 92 | 93 | endmodule 94 | 95 | 96 | -------------------------------------------------------------------------------- /Benchmarks/encoder/encoder.v: -------------------------------------------------------------------------------- 1 | module encoder 2 | #( 3 | parameter logS=4 4 | ) 5 | ( 6 | g_input, 7 | e_input, 8 | o 9 | ); 10 | 11 | localparam S = 2**logS; 12 | input [S/2-1:0] g_input; 13 | input [S/2-1:0] e_input; 14 | output [logS-1:0] o; 15 | 16 | wire [S-1:0] in; 17 | 18 | assign in[S/2-1:0] = g_input; 19 | assign in[S-1:S/2] = e_input; 20 | 21 | encoder_ 22 | #( 23 | .logS(logS) 24 | ) 25 | encoder0 26 | ( 27 | .in(in), 28 | .o(o) 29 | ); 30 | 31 | endmodule 32 | 33 | 34 | module encoder_ 35 | #( 36 | parameter logS=4 37 | ) 38 | ( 39 | in, 40 | o 41 | ); 42 | 43 | localparam S = 2**logS; 44 | input [S-1:0] in; 45 | output [logS-1:0] o; 46 | 47 | generate 48 | if(logS == 1) 49 | begin 50 | assign o = in[1]; 51 | end 52 | else 53 | begin 54 | 55 | wire [logS-1:0] o0; 56 | wire [logS-1:0] o1; 57 | 58 | 59 | encoder_ 60 | #( 61 | .logS(logS-1) 62 | ) 63 | encoder0 64 | ( 65 | .in(in[S/2-1:0]), 66 | .o(o0[logS-2:0]) 67 | ); 68 | 69 | encoder_ 70 | #( 71 | .logS(logS-1) 72 | ) 73 | encoder1 74 | ( 75 | .in(in[S-1:S/2]), 76 | .o(o1[logS-2:0]) 77 | ); 78 | 79 | assign o = {|in[S-1:S/2], o0[logS-2:0]|o1[logS-2:0]}; 80 | end 81 | endgenerate 82 | 83 | endmodule -------------------------------------------------------------------------------- /Benchmarks/hamming/hamming.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib/generic.sdb 5 | set hdlin_while_loop_iterations 16000 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/COUNT.v} 8 | 9 | analyze -format verilog hamming.v 10 | 11 | foreach n {16 32 64} { 12 | set cc 1 13 | elaborate hamming -architecture verilog -library DEFAULT -update -parameters $n,$cc 14 | set_max_area -ignore_tns 0 15 | set_flatten false -design * 16 | set_structure -design * false 17 | set_resource_allocation area_only 18 | report_compile_options 19 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 20 | write -hierarchy -format verilog -output syn/hamming_${n}bit_${cc}cc.v 21 | } 22 | 23 | foreach n {32 512} { 24 | set cc $n 25 | elaborate hamming -architecture verilog -library DEFAULT -update -parameters $n,$cc 26 | set_max_area -ignore_tns 0 27 | set_flatten false -design * 28 | set_structure -design * false 29 | set_resource_allocation area_only 30 | report_compile_options 31 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 32 | write -hierarchy -format verilog -output syn/hamming_${n}bit_${cc}cc.v 33 | } 34 | 35 | exit 36 | -------------------------------------------------------------------------------- /Benchmarks2/hamming/hamming.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [concat . ../../SynthesisLibrary/lib_EMP/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib_EMP/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib_EMP/dff_full/dff_full.db 4 | set symbol_library ../../SynthesisLibrary/lib_EMP/generic.sdb 5 | set hdlin_while_loop_iterations 16000 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/COUNT.v} 8 | 9 | analyze -format verilog hamming.v 10 | 11 | foreach n {128 256 1024} { 12 | set cc 1 13 | elaborate hamming -architecture verilog -library DEFAULT -update -parameters $n,$cc 14 | set_max_area -ignore_tns 0 15 | set_flatten false -design * 16 | set_structure -design * false 17 | set_resource_allocation area_only 18 | report_compile_options 19 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 20 | write -hierarchy -format verilog -output syn/hamming_${n}bit_${cc}cc.v 21 | } 22 | 23 | foreach n {32 512} { 24 | set cc $n 25 | elaborate hamming -architecture verilog -library DEFAULT -update -parameters $n,$cc 26 | set_max_area -ignore_tns 0 27 | set_flatten false -design * 28 | set_structure -design * false 29 | set_resource_allocation area_only 30 | report_compile_options 31 | compile -ungroup_all -boundary_optimization -map_effort high -area_effort high -no_design_rule 32 | write -hierarchy -format verilog -output syn/hamming_${n}bit_${cc}cc.v 33 | } 34 | 35 | exit 36 | -------------------------------------------------------------------------------- /Verilog2SCD/parse_netlist.h: -------------------------------------------------------------------------------- 1 | /* 2 | This file is part of TinyGarble. It is modified version of JustGarble 3 | under GNU license. 4 | 5 | TinyGarble is free software: you can redistribute it and/or modify 6 | it under the terms of the GNU General Public License as published by 7 | the Free Software Foundation, either version 3 of the License, or 8 | (at your option) any later version. 9 | 10 | TinyGarble is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 | GNU General Public License for more details. 14 | 15 | You should have received a copy of the GNU General Public License 16 | along with TinyGarble. If not, see . 17 | */ 18 | 19 | #ifndef SCD_PARSE_NETLIST_H_ 20 | #define SCD_PARSE_NETLIST_H_ 21 | 22 | #include "v_2_scd.h" 23 | 24 | string Type2StrGate(short itype); 25 | int ParseNetlist(const string &file_name, 26 | ReadCircuitString* read_circuit_string); 27 | int ParseBrisNetlist(const string &file_name, 28 | ReadCircuitString* read_circuit_string); 29 | int IdAssignment(const ReadCircuitString& read_circuit_string, 30 | ReadCircuit* read_circuit); 31 | int TopologicalSort(const ReadCircuit &read_circuit, 32 | vector* sorted_list, 33 | const ReadCircuitString& read_circuit_string); 34 | 35 | #endif /* SCD_PARSE_NETLIST_H_ */ 36 | -------------------------------------------------------------------------------- /demo/vdp/mac.dcsh: -------------------------------------------------------------------------------- 1 | set search_path [list . ../../SynthesisLibrary/lib/dff_full/] 2 | set target_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 3 | set link_library ../../SynthesisLibrary/lib/dff_full/dff_full.db 4 | set symbol_library [concat ../../SynthesisLibrary/lib/generic.sdb] 5 | set hdlin_while_loop_iterations 1024 6 | 7 | analyze -format verilog {../../SynthesisLibrary/syn_lib/ADD.v ../../SynthesisLibrary/syn_lib/ADD_.v ../../SynthesisLibrary/syn_lib/COMP.v ../../SynthesisLibrary/syn_lib/COUNT.v ../../SynthesisLibrary/syn_lib/DIV.v ../../SynthesisLibrary/syn_lib/DIV_.v ../../SynthesisLibrary/syn_lib/FA.v ../../SynthesisLibrary/syn_lib/MULT.v ../../SynthesisLibrary/syn_lib/MULT_.v ../../SynthesisLibrary/syn_lib/MUX.v ../../SynthesisLibrary/syn_lib/SHIFT_LEFT.v ../../SynthesisLibrary/syn_lib/SHIFT_RIGHT.v ../../SynthesisLibrary/syn_lib/SUB.v ../../SynthesisLibrary/syn_lib/SUB_.v ../../SynthesisLibrary/syn_lib/TwosComplement.v ../../SynthesisLibrary/syn_lib/square_root.v } 8 | 9 | analyze -format sverilog mac.sv 10 | 11 | 12 | foreach L {32} { 13 | foreach N {4 8 16} { 14 | elaborate mac_TG -architecture verilog -library DEFAULT -update -parameters $N,$N,$L 15 | set_max_area -ignore_tns 0 16 | set_flatten false -design * 17 | set_structure false -design * 18 | set_resource_allocation area_only 19 | report_compile_options 20 | compile -ungroup_all -map_effort high -area_effort high -no_design_rule 21 | write -hierarchy -format verilog -output syn/mac_${N}_${N}_${L}bit.v 22 | } 23 | } 24 | 25 | exit 26 | -------------------------------------------------------------------------------- /Benchmarks2/sum/tb_sum_nbit_ncc.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module tb_sum_nbit_ncc; 4 | 5 | logic clk, rst; 6 | logic g_input; 7 | logic e_input; 8 | logic o; 9 | 10 | sum_nbit_ncc uut( 11 | .clk(clk), .rst(rst), 12 | .g_input(g_input), 13 | .e_input(e_input), 14 | .o(o) 15 | ); 16 | 17 | parameter N = 8; 18 | 19 | logic [N-1:0] G; 20 | logic [N-1:0] E; 21 | logic [N-1:0] O, O_ref; 22 | 23 | assign O_ref = G + E; 24 | 25 | always #50 clk = ~clk; 26 | 27 | integer k; 28 | 29 | initial begin 30 | clk = 'b0; 31 | 32 | G = 'hA9; 33 | E = 'h7B; 34 | rst = 'b1; 35 | @(posedge clk) 36 | rst = 'b0; 37 | for (k = 0; k < N; k = k + 1) begin 38 | g_input = G[k]; 39 | e_input = E[k]; 40 | @(posedge clk); 41 | O[k] = o; 42 | end 43 | $display("G = %H, E = %H, O = %H, O_ref= %H", G, E, O, O_ref); 44 | 45 | G = 'h18; 46 | E = 'h27; 47 | rst = 'b1; 48 | @(posedge clk) 49 | rst = 'b0; 50 | for (k = 0; k < N; k = k + 1) begin 51 | g_input = G[k]; 52 | e_input = E[k]; 53 | @(posedge clk); 54 | O[k] = o; 55 | end 56 | $display("G = %H, E = %H, O = %H, O_ref= %H", G, E, O, O_ref); 57 | 58 | G = 'h57; 59 | E = 'h63; 60 | rst = 'b1; 61 | @(posedge clk) 62 | rst = 'b0; 63 | for (k = 0; k < N; k = k + 1) begin 64 | g_input = G[k]; 65 | e_input = E[k]; 66 | @(posedge clk); 67 | O[k] = o; 68 | end 69 | $display("G = %H, E = %H, O = %H, O_ref= %H", G, E, O, O_ref); 70 | 71 | $stop(); 72 | end 73 | 74 | endmodule -------------------------------------------------------------------------------- /SynthesisLibrary/syn_lib/ADD.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ADD #(parameter N = 8, M = N)( // N >= M 4 | input [N-1:0] A, 5 | input [M-1:0] B, 6 | input CI, 7 | output CO, 8 | output [N-1:0] S 9 | ); 10 | 11 | wire [N-1:0] BB; 12 | generate 13 | if (N > M) begin: FA_IF 14 | assign BB = {{(N-M){1'b0}}, B}; 15 | end else begin: FA_IF_N 16 | assign BB = B; 17 | end 18 | endgenerate 19 | 20 | 21 | wire C[N:0]; 22 | 23 | assign C[0] = CI; 24 | assign CO = C[N]; 25 | 26 | genvar g; 27 | genvar h; 28 | 29 | localparam MAX_LOOP = 512; 30 | 31 | generate 32 | if(N < MAX_LOOP) begin : FA_IF2 33 | for(g=0;g0; log2=log2+1) 30 | temp = temp>>1; 31 | end 32 | endfunction 33 | 34 | localparam logM = log2(M); 35 | 36 | input clk,rst; 37 | 38 | input [logM-1:0] read_adr; 39 | output [W-1:0] read_data; 40 | input [logM-1:0] write_adr; 41 | input [W-1:0] write_data; 42 | input write_en; 43 | input [logM-1:0] write_adr2; 44 | input [W-1:0] write_data2; 45 | input write_en2; 46 | input [logM-1:0] write_adr3; 47 | input [W-1:0] write_data3; 48 | input write_en3; 49 | 50 | reg [W-1:0] mem_matrix [M-1:0]; 51 | 52 | integer i; 53 | always @(posedge clk or posedge rst) begin 54 | if (rst) begin 55 | for(i=0;i. 17 | */ 18 | 19 | #ifndef PARSE_NETLIST_H_ 20 | #define PARSE_NETLIST_H_ 21 | 22 | #include "v_2_EMPCircuit.h" 23 | #include 24 | 25 | string Type2StrGate(short itype); 26 | int ParseNetlist(const string &file_name, 27 | ReadCircuitString* read_circuit_string); 28 | bool isOutPort(string output); 29 | void AddWireArray(std::map& wire_name_table, const string& name, 30 | uint64_t size, int64_t *wire_index); 31 | int IdAssignment(const ReadCircuitString& read_circuit_string, 32 | ReadCircuit* read_circuit); 33 | int TopologicalSort(const ReadCircuit &read_circuit, 34 | vector* sorted_list, 35 | const ReadCircuitString& read_circuit_string); 36 | 37 | #endif /* PARSE_NETLIST_H_ */ 38 | -------------------------------------------------------------------------------- /Benchmarks/mips/ALU.v: -------------------------------------------------------------------------------- 1 | `include "../defined.vh" 2 | 3 | module ALU 4 | ( 5 | a_in , 6 | b_in , 7 | alu_function , 8 | c_alu 9 | ); 10 | input [31:0]a_in; 11 | input [31:0]b_in; 12 | input [3:0]alu_function; 13 | output reg [31:0]c_alu; 14 | 15 | 16 | 17 | wire signed [31:0]a_in_s, b_in_s; 18 | 19 | assign a_in_s=a_in; 20 | assign b_in_s=b_in; 21 | 22 | 23 | wire [31:0] b_b_not; 24 | wire [31:0] adder_out; 25 | wire cout; 26 | reg cin; 27 | 28 | assign b_b_not = (cin)?~b_in:b_in; 29 | 30 | ADD 31 | #( 32 | .N(32) 33 | ) 34 | ADD_ 35 | ( 36 | .A(a_in), 37 | .B(b_b_not), 38 | .CI(cin), 39 | .S(adder_out), 40 | .CO(cout) 41 | ); 42 | 43 | 44 | always@(*) 45 | begin 46 | c_alu<=32'b0; 47 | cin <= 0; 48 | case(alu_function) 49 | `ALU_NOTHING: 50 | c_alu<=32'b0; 51 | `ALU_ADD: 52 | begin 53 | cin <= 0; 54 | c_alu<=adder_out;//a_in+b_in; 55 | end 56 | `ALU_SUBTRACT: 57 | begin 58 | cin <= 1; 59 | c_alu<=adder_out;//a_in-b_in; 60 | end 61 | `ALU_LESS_THAN://TODO:check 62 | begin 63 | cin <= 1; 64 | c_alu<={31'b0, ~cout};//(a_in