├── .gitignore ├── .gitmodules ├── README.assets ├── cpu.png └── wechat_screenshot.jpg ├── README.md └── riscv ├── Makefile ├── fpga ├── build.sh ├── controller.cpp ├── listener.h ├── pd.tcl └── run.sh ├── script ├── FPGA_test.py ├── autorun_fpga.sh ├── build_test.sh ├── run_test.sh └── run_test_fpga.sh ├── sim └── testbench.v ├── src ├── Basys-3-Master.xdc ├── common │ ├── block_ram │ │ └── block_ram.v │ ├── fifo │ │ └── fifo.v │ └── uart │ │ ├── uart.v │ │ ├── uart_baud_clk.v │ │ ├── uart_rx.v │ │ └── uart_tx.v ├── cpu.v ├── hci.v ├── ram.v └── riscv_top.v ├── sys ├── io.h ├── memory.ld └── rom.s ├── testcase ├── fpga │ ├── array_test1.ans │ ├── array_test1.c │ ├── array_test1.in │ ├── array_test2.ans │ ├── array_test2.c │ ├── array_test2.in │ ├── basicopt1.ans │ ├── basicopt1.c │ ├── bulgarian.ans │ ├── bulgarian.c │ ├── expr.ans │ ├── expr.c │ ├── gcd.ans │ ├── gcd.c │ ├── hanoi.ans │ ├── hanoi.c │ ├── hanoi.in │ ├── heart.ans │ ├── heart.c │ ├── looper.c │ ├── lvalue2.ans │ ├── lvalue2.c │ ├── magic.ans │ ├── magic.c │ ├── manyarguments.ans │ ├── manyarguments.c │ ├── multiarray.ans │ ├── multiarray.c │ ├── pi.ans │ ├── pi.c │ ├── qsort.ans │ ├── qsort.c │ ├── queens.ans │ ├── queens.c │ ├── statement_test.ans │ ├── statement_test.c │ ├── statement_test.in │ ├── superloop.ans │ ├── superloop.c │ ├── superloop.in │ ├── tak.ans │ ├── tak.c │ ├── tak.in │ ├── testsleep.c │ ├── uartboom.ans │ └── uartboom.c └── sim │ ├── 000_array_test1.ans │ ├── 000_array_test1.c │ ├── 001_array_test2.ans │ ├── 001_array_test2.c │ ├── 002_expr.ans │ ├── 002_expr.c │ ├── 003_looper.c │ ├── 004_gcd.ans │ ├── 004_gcd.c │ ├── 005_lvalue2.ans │ ├── 005_lvalue2.c │ ├── 006_multiarray.ans │ ├── 006_multiarray.c │ ├── 007_hanoi.ans │ ├── 007_hanoi.c │ ├── 100_magic.ans │ ├── 100_magic.c │ ├── 101_queens.ans │ ├── 101_queens.c │ ├── 102_qsort.ans │ ├── 102_qsort.c │ ├── 103_bulgarian.ans │ ├── 103_bulgarian.c │ ├── basicopt1.ans │ ├── basicopt1.c │ ├── manyarguments.ans │ ├── manyarguments.c │ ├── statement_test.ans │ ├── statement_test.c │ ├── superloop.ans │ ├── superloop.c │ ├── uartboom.ans │ └── uartboom.c └── testspace └── .keep /.gitignore: -------------------------------------------------------------------------------- 1 | riscv/testspace/* 2 | 3 | *.o 4 | *.vcd 5 | 6 | !.keep -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "serial"] 2 | path = serial 3 | url = https://github.com/wjwwood/serial 4 | -------------------------------------------------------------------------------- /README.assets/cpu.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACMClassCourses/RISCV-CPU/9c5153951e01c8bf072e6b37b874e1408e75af89/README.assets/cpu.png -------------------------------------------------------------------------------- /README.assets/wechat_screenshot.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACMClassCourses/RISCV-CPU/9c5153951e01c8bf072e6b37b874e1408e75af89/README.assets/wechat_screenshot.jpg -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISCV-CPU 2022 2 | 3 | ## 引言 4 | 5 | ![wechat_screenshot](README.assets/wechat_screenshot.jpg) 6 | 7 | 8 | 9 | 10 | 11 | ## 项目说明 12 | 13 | 在本项目中，你需要使用 Verilog 语言完成一个简单的 RISC-V CPU 电路设计。Verilog 代码会以软件仿真和 FPGA 板两种方式运行。你设计的电路将运行若干测试程序并可能有输入数据，执行得到的输出数据将与期望结果比较，从而判定你的 Verilog 代码的正确性。你需要实现 CPU 的运算器与控制器，而内存等部件题面已提供代码。 14 | 15 | 16 | 17 | ### 项目阶段 18 | 19 | - 完成 Speculative CPU 所支持的所有模块 20 | 21 | - 在本地 Simulation 通过可执行的测试 22 | 23 | > 在本地 Simulation 时，部分样例运行时间可能会非常非常长，如 `heart.c` 与 `pi.c`。这些样例不会被算入 Simulation 的测试范围，但会在 FPGA 检查阶段纳入测试范围。 24 | 25 | - 在 FPGA 上通过所有测试 26 | 27 | 28 | 29 | ### 时间安排 30 | 31 | > 时间以上海交通大学 2022-2023 学年校历为准，Week 6 周一为 202210.17 32 | 33 | 每 2 周一次检查，检查时间为每周日 22:00 后，下表为检查形式与标准： 34 | 35 | | 时间 | 检查内容 | 36 | | ----------- | ----------------------------------------------------- | 37 | | **Week 6** | 仓库创建 | 38 | | **Week 8** | 完成电路设计草稿 / 各个 CPU 模块文件创建 | 39 | | **Week 10** | 完成 Instruction Fetch 部分代码，尝试仿真运行 | 40 | | **Week 12** | 各个 CPU 模块文件基本完成，完成 `cpu.v` 连线 | 41 | | **Week 14** | Simulation 通过 `gcd` | 42 | | **Week 16** | Simulation 通过除 `tak`，`heart`，`pi` 之外的所有样例 | 43 | | **Week 18** | FPGA 通过所有样例 | 44 | 45 | 46 | 47 | ### 最终提交 48 | 49 | 你需要向助教单独提交由 Vivado Synthesis 生成出的 `.bit` 文件，截止时间为第 18 周前（2023.1.8 23:59）。 50 | 51 | 52 | 53 | ### 分数构成 54 | 55 | 本作业满分为 100%。 56 | 57 | | 评分项目 | 分数 | 说明 | 58 | | --------------- | ---- | ---------------------------------------- | 59 | | **仿真测试** | 75% | 在 OJ 通过所有仿真测试点 | 60 | | **FPGA 测试** | 10% | 在 OJ 通过所有 FPGA 测试点 | 61 | | **Code Review** | 15% | 以面谈形式考察 CPU 原理与 HDL 的理解掌握 | 62 | 63 | 64 | 65 | 66 | 67 | ## 实现说明 68 | 69 | ### 仓库文件结构 70 | 71 | ```C++ 72 | 📦RISCV-CPU 73 | ┣ 📂riscv // 项目根目录 74 | ┃ ┣ 📂fpga // FPGA 开发板相关 75 | ┃ ┣ 📂script // 编译测试相关参考脚本 76 | ┃ ┣ 📂sim // 仿真运行 Testbench 77 | ┃ ┣ 📂src // HDL 源代码 78 | ┃ ┃ ┣ 📂common // 题面提供部件源代码 79 | ┃ ┃ ┣ 📜cpu.v // CPU 核心代码 80 | ┃ ┣ 📂sys // 编译 C 语言测试点所需文件 81 | ┃ ┣ 📂testcase // 测试点 82 | ┃ ┃ ┣ 📂fpga // 全部测试点 (全集) 83 | ┃ ┃ ┗ 📂sim // 仿真运行测试点 (子集) 84 | ┃ ┣ 📂testspace // 编译运行结果 85 | ┃ ┗ 📜Makefile // 编译及测试脚本 86 | ┣ 📂serial // 用于访问 FPGA 串口的第三方库 87 | ┗ 📜README.md // 题面文档 88 | ``` 89 | 90 | ### 概述 91 | 92 | 1. 根据 [`riscv/src/cpu.v`](https://github.com/ACMClassCourses/RISCV-CPU/blob/main/riscv/src/cpu.v) 提供的接口自顶向下完成代码，其余题面代码尽量不要改动 93 | 2. 设计并实现**支持乱序执行**的 Tomasulo 架构 CPU 94 | 3. 使用 iVerilog 进行本地仿真测试（结果为 `.vcd` 文件） 95 | 4. 依照助教安排，将 Verilog 代码烧录至 FPGA 板上进行所有测试数据的测试 96 | 97 | ### 指令集 98 | 99 | > 可参考资料见 [RISC-V 指令集](#RISC-V-指令集) 100 | 101 | 本项目使用 **RV32I 指令集** 102 | 103 | 基础测试内容不包括 Doubleword 和 Word 相关指令、Environment 相关指令和 CSR 相关等指令。 104 | 105 | 必须要实现的指令为以下 37 个：`LUI`, `AUIPC`, `JAL`, `JALR`, `BEQ`, `BNE`, `BLT`, `BGE`, `BLTU`, `BGEU`, `LB`, `LH`, `LW`, `LBU`, `LHU`, `SB`, `SH`, `SW`, `ADDI`, `SLLI`, `SLTI`, `SLTIU`, `XORI`, `SRLI`, `SRAI`, `ORI`, `ANDI`, `ADD`, `SUB`, `SLL`, `SLT`, `SLTU`, `XOR`, `SRL`, `SRA`, `OR`, `AND` 106 | 107 | 108 | 109 | 110 | 111 | ## 帮助 112 | 113 | > **这可能对你来说非常重要。** 114 | 115 | ### 文档 116 | 117 | - Vivado 不支持 MacOS 系统，故如果使用 Mac 则必须使用虚拟机，推荐 Ubuntu Desktop。此外对于使用 Windows 电脑的同学，RISC-V Toolchain 也推荐在 Linux 系统上安装。 118 | - 更多题面补充文档参见 [本仓库 `doc` 分支](https://github.com/ACMClassCourses/RISCV-CPU/tree/doc) 119 | - 题面附录与 README 以外内容包含上文未提及信息，可能有助于你完成项目，请记得阅读 120 | 121 | 122 | 123 | ### Q & A 124 | 125 | 1. **我的 CPU 会从哪里读取指令并执行？** 126 | 127 | 从 `0x0000000` 地址处开始执行。 128 | 129 | 2. **我的 CPU 如何停机？** 130 | 131 | 见 `cpu.v` 中 `Specification` 部分。 132 | 133 | 3. **我的寄存器堆（Register File）需要多少个寄存器？** 134 | 135 | Unprivileged CPU: 32； 136 | 137 | Privileged CPU: 32 + 8 (CSR)。 138 | 139 | 4. **托马斯洛算法并没有硬件实现的公认唯一标准，那么本项目有什么特殊要求吗？** 140 | 141 | 托马斯洛的要求可参考 [Wikipedia](https://en.wikipedia.org/wiki/Tomasulo%27s_algorithm#Instruction_lifecycle)，即执行一条指令需要涉及 *Issue*、*Execute*、*Write Result* 三步骤。此外，**必须要实现 *Instruction Cache*** 以确保程序运行过程中会出现多条指令的 lifecycle 重叠的情况。 142 | 143 | 5. **我该如何开始运行代码？** 144 | 145 | 在 `riscv/` 路径下运行 `make test_sim name=000` 指令即可自动编译并运行第一个仿真测试点，测试文件均在 `riscv/testspace/` 文件夹中。 146 | 147 | 6. **`io_buffer_full`?** 148 | 149 | 用于指示当前 ram 的 io buffer 是否已满。若已满，可能会出现 overwrite / loss。 150 | 151 | 注意：此信号在 simulation 部分始终为 low (false)，但在 FPGA 上会有高低变化。 152 | 153 | 7. **`in_rdy`?** 154 | 155 | 用于指示当前hci总线是否为active (可工作)，若否，则cpu应当pause。 156 | 157 | 8. **运行测试过程中 build 报错？** 158 | 159 | 请考虑以下几点： 160 | 161 | - 目录错误 162 | 163 | 脚本运行目录应当为 `riscv/` 文件夹 164 | 165 | - 环境缺失，如 `cannot find module -lgcc ...` 166 | 167 | **在配置了riscv-toolchains 的环境下，应当可以正常 build。** 168 | 169 | **请检查连接了 FPGA 的系统是否配置了 riscv-toolchains，若没有，你也可以使用现成的编译结果。** 170 | 171 | 9. **To be continued...** 172 | 173 | 174 | 175 | 176 | 177 | ---- 178 | 179 | > 以下为附录内容。 180 | 181 | 182 | 183 | 184 | 185 | ## 附录 A 186 | 187 | ### RISC-V 指令集 188 | 189 | - 官网 https://riscv.org/ 190 | - [官方文档下载页面](https://riscv.org/technical/specifications/) 191 | - 基础内容见 Volume 1, Unprivileged Spec 192 | - 特权指令集见 Volume 2, Privileged Spec 193 | - 非官方 [Read the Docs 文档](https://msyksphinz-self.github.io/riscv-isadoc/html/index.html) 194 | 195 | - 非官方 Green Card，[PDF 下载链接](https://inst.eecs.berkeley.edu/~cs61c/fa17/img/riscvcard.pdf) 196 | 197 | ### RISC-V C and C++ Cross-compiler 198 | 199 | - https://github.com/riscv-collab/riscv-gnu-toolchain 根据该 Repo 教程安装 200 | - 请注意下载需要 6.6G 空间，安装内容大小为 1G 左右。 201 | 202 | ### 使用 FPGA 板运行代码 203 | 204 | - **Vivado** 205 | 206 | - 你需要该软件将 Verilog 代码编译为可以烧录至 FPGA 板的二进制文件 207 | 208 | - Vivado 安装后软件整体大小达 30G 左右，请准备足够硬盘空间 209 | 210 | - **Serial Communication Library** 211 | 212 | - 程序与 FPGA 板通过 USB 通讯过程中使用该库 213 | - 安装方式参见本仓库 Submodule 214 | 215 | 216 | 217 | 218 | 219 | ## 附录 B 220 | 221 | > 附录 B 为 2021 年旧题面 222 | 223 | ### Repo Structure 224 | 225 | ``` 226 | |--riscv/ 227 | | |--fpga/ Interface with FPGA 228 | | |--sim/ Testbench, add to Vivado project only in simulation 229 | | |--src/ Where your code should be 230 | | | |--common/ Provided UART and RAM 231 | | | |--Basys-3-Master.xdc constraint file 232 | | | |--cpu.v Fill it. 233 | | | |--hci.v A bus between UART/RAM and CPU 234 | | | |--ram.v RAM 235 | | | |--riscv_top.v Top design 236 | | |--sys/ Help compile 237 | | |--testcase/ Testcases 238 | | |--autorun_fpga.sh Autorun Testcase on FPGA 239 | | |--build_test.sh Run it to build test.data from test.c 240 | | |--FPGA_test.py Test correctness on FPGA 241 | | |--pd.tcl Program device the bitstream onto FPGA 242 | | |--run_test.sh Run test 243 | | |--run_test_fpga.sh Run test on FPGA 244 | |--serial/ A third-party library for interfacing with FPGA ports 245 | ``` 246 | 247 | ### Requirement 248 | 249 | #### Basic Requirement 250 | 251 | - Use Verilog to implement a CPU supporting part of RV32I Instruction set(2.1-2.6 in [RISC-V user manual](https://riscv.org//wp-content/uploads/2017/05/riscv-spec-v2.2.pdf)), with the provided code in this repository. 252 | 253 | #### Grading Policy 254 | 255 | - A design meeting part of a requirement can get part of its corresponding points. 256 | - The course project assignment is not mature yet. Please give practical suggestions or bug fixes for next year's project if you feel somewhere uncomfortable with current project. You should prepare a short note or presentation for your findings. You will get extra 2% for this. If you implement your suggestion and it's meaningful in both educational purpose and project perfection purpose, the extra credit will be raised up -- up to 10%. It will be a complement for your bonus part, or extra 1 point in the final grading if you get full mark in the project. 257 | 258 | ### Details 259 | 260 | #### RISCV-Toolchain 261 | 262 | For prerequisites, go to see https://github.com/riscv/riscv-gnu-toolchain to install necessary packages. 263 | The configure is: 264 | 265 | ``` 266 | ./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 267 | sudo make 268 | ``` 269 | **DO NOT** use `sudo make linux` which you may use in PPCA. If you have made it, just rerun `sudo make` without any deletion and everything will be ok. 270 | (BTW, you may use arch rv32gc for your compiler project, so keep the installation package) 271 | 272 | The following are some common problems you may meet when make 273 | 274 | ###### `make failed` 275 | 276 | Please first check whether you use `sudo` before `make` due to default permission setting of linux. 277 | 278 | ###### `checking for sysdeps preconfigure fragments... aarch64 alpha arm csky hppa i386 m68k microblaze mips nios2 powerpc riscv glibc requires the A extension` 279 | 280 | Use configuration `./configure --prefix=/opt/riscv --with-arch=rv32ia --with-abi=ilp32` 281 | 282 | ###### `xxx-ld: cannot find -lgcc` 283 | 284 | Go to see https://github.com/riscv/riscv-gnu-toolchain/issues/522. 285 | 286 | #### Custom 287 | 288 | In this project, the size of memory(ram) is 128K, so only address lower than 0x20000 is available. However, reading and writing from 0x30000 and 0x30004 have special meaning, you can see `riscv/src/cpu.v` for more details. 289 | 290 | #### Simulation using iverilog 291 | 292 | ``` 293 | cd ./riscv/src 294 | iverilog *.v common/*/*.v 295 | vvp a.out 296 | ``` 297 | 298 | #### Serial 299 | 300 | Serial( [wjwwood/serial](https://github.com/wjwwood/serial)) is a cross-platform serial port library to help your design working on FPGA when receiving from UART. Build it by: 301 | 302 | ```bash 303 | git submodule init 304 | git submodule update 305 | cd serial 306 | make 307 | make install 308 | ``` 309 | 310 | #### Build test 311 | 312 | Use the following command to build a test, it will be a `test.data` file in folder `/riscv/test/`: 313 | 314 | ```bash 315 | cd riscv 316 | ./build_test.sh testname 317 | ``` 318 | 319 | You can see all tests in `/riscv/testcase/` folder. 320 | 321 | #### FPGA 322 | 323 | We'll provide you with Basys3 FPGA board. Use Vivado to generate bitstream and program the FPGA device. Then: 324 | 325 | In directory 'ctrl', build the controller by 326 | 327 | ``` 328 | ./build.sh 329 | ``` 330 | 331 | Modify and run the script 332 | 333 | ``` 334 | ./run_test_fpga.sh testname 335 | ``` 336 | 337 | One thing need to be modified is the USB port number of the script. For example in Windows you could find it in Devices and Printers -> Digilent USB Device -> Hardware. The number X that presented in the last line of Device Functions 'USB Serial Port (COMX)' is the port you need. The port format should be like: 338 | 339 | ``` 340 | on Linux: /dev/ttyUSBX 341 | on WSL: /dev/ttySX 342 | on Windows: COMX 343 | ``` 344 | 345 | Your Vivado may be unable to discover your FPGA, this may be caused by the lack of corresponding driver, install it by(use your own version to replace `2018.2`): 346 | 347 | ```bash 348 | cd $PATH_TO_VIVADO/2018.2/data/xicom/cable_drivers/lin64 349 | sudo cp -i -r install_script /opt 350 | cd /opt/install_script/install_drivers 351 | sudo ./install_drivers 352 | ``` 353 | 354 | Then restart Vivado. 355 | 356 | To run your bitstream on FPGA, you can run: 357 | 358 | ```bash 359 | cd riscv 360 | python FPGA_test.py 361 | ``` 362 | 363 | You need to modify the `path_of_bit` in `FPGA_test.py` first. 364 | 365 | ### Update Note 366 | 367 | For some strong students that start project early based on last year's assignment, here are some changes we've made this year: 368 | 369 | 1. Fixed a bug in `riscv_top.v` that may cause you get wrong return value when two consecutive readings are from different data sources. 370 | 371 | 2. A new `input wire io_buffer_full` that will show the UART output buffer is full and you should stall -- otherwise some output will be missing when output requests are intensive. You can ignore the problem in the beginning stage. 372 | 373 | Note: you will receive `io_buffer_full` in the SECOND NEXT CYCLE from your write cycle since the FIFO module's limitation. To ensure FIFO is not full you have to stall one cycle when there are two consecutive writes to 0x30000 in two consecutive clock, especially when i-cache is on. This problem will be detected in the testcase `uartboom`. 374 | 375 | You're welcome to fix this problem by modifying preset code. Elegant implementation will be counted as bonus. 376 | 377 | ### Q&A 378 | 379 | 1. `rdy_in` and `rst_in` 380 | 381 | The `rst_in` has higher priority with `rdy_in`, and you CANNOT DO ANYTING when `rdy_in` is zero. `rdy_in` does not affect the result of simulation, but has effect when running on FPGA. 382 | 383 | 2. Write twice in simulation 384 | 385 | This is often OK in simulation, because it uses `$write()` in a combinational circuit to simulate a write(you can find it in `hci.v`), and by the property of combinational circuit, this instruction may be executed twice. 386 | 387 | In FPGA if everything you write is correct this will not happen. 388 | 389 | 3. connect with FPGA 390 | 391 | Use the micro USB port on the FPGA, since we use RS232 to transmit data. 392 | 393 | You may meet various problems, especially when start testing on FPGA. Feel free to contact any TA for help. 394 | 395 | ### Known issues (2021.2.3) 396 | 397 | 1. Some will fail to run the second time on FPGA. One quick solution is to let `rst = rst_in | ~rdy_in`, however it's somehow incorrect. We hope the future TAs to investigate the phenomenon and give a correct solution. 398 | 399 | 2. There's not a quick simulation check test case. One possible way is to mix up some test cases that can check those CPUs failed to run on FPGA using tolerable time while not to be much easier than passing all test cases. We didn't write one yet. Also, it may be hard to design, since some failures occur with only a few strange and specific conditions. 400 | 401 | 3. Our updated version of `hcl` and `top` are not good enough, since it requires combinational circuits not to consider `rst` --- or timing loop will occur since `rst` is connected to `program_finish` driven by combinational circuits. Better design may be required. 402 | -------------------------------------------------------------------------------- /riscv/Makefile: -------------------------------------------------------------------------------- 1 | prefix = $(shell pwd) 2 | # Folder Path 3 | src = $(prefix)/src 4 | testspace = $(prefix)/testspace 5 | 6 | sim_testcase = $(prefix)/testcase/sim 7 | fpga_testcase = $(prefix)/testcase/fpga 8 | 9 | sim = $(prefix)/sim 10 | riscv_toolchain = /opt/riscv 11 | riscv_bin = $(riscv_toolchain)/bin 12 | sys = $(prefix)/sys 13 | 14 | _no_testcase_name_check: 15 | @$(if $(strip $(name)),, echo 'Missing Testcase Name') 16 | @$(if $(strip $(name)),, exit 1) 17 | 18 | # All build result are put at testspace 19 | build_sim: 20 | @cd $(src) && iverilog -o $(testspace)/test $(sim)/testbench.v $(src)/common/block_ram/*.v $(src)/common/fifo/*.v $(src)/common/uart/*.v $(src)/*.vh $(src)/*.v 21 | 22 | build_sim_test: _no_testcase_name_check 23 | @$(riscv_bin)/riscv32-unknown-elf-as -o $(sys)/rom.o -march=rv32i $(sys)/rom.s 24 | @cp $(sim_testcase)/*$(name)*.c $(testspace)/test.c 25 | @$(riscv_bin)/riscv32-unknown-elf-gcc -o $(testspace)/test.o -I $(sys) -c $(testspace)/test.c -O2 -march=rv32i -mabi=ilp32 -Wall 26 | @$(riscv_bin)/riscv32-unknown-elf-ld -T $(sys)/memory.ld $(sys)/rom.o $(testspace)/test.o -L $(riscv_toolchain)/riscv32-unknown-elf/lib/ -L $(riscv_toolchain)/lib/gcc/riscv32-unknown-elf/10.1.0/ -lc -lgcc -lm -lnosys -o $(testspace)/test.om 27 | @$(riscv_bin)/riscv32-unknown-elf-objcopy -O verilog $(testspace)/test.om $(testspace)/test.data 28 | @$(riscv_bin)/riscv32-unknown-elf-objdump -D $(testspace)/test.om > $(testspace)/test.dump 29 | 30 | run_sim: 31 | @cd $(testspace) && ./test 32 | 33 | clear: 34 | @rm $(sys)/rom.o $(testspace)/test* 35 | 36 | test_sim: build_sim build_sim_test run_sim 37 | 38 | .PHONY: _no_testcase_name_check build_sim build_sim_test run_sim clear test_sim 39 | -------------------------------------------------------------------------------- /riscv/fpga/build.sh: -------------------------------------------------------------------------------- 1 | set -e 2 | dir=`dirname $0` 3 | g++ $dir/controller.cpp -std=c++14 -I /tmp/usr/local/include/ -L /tmp/usr/local/lib/ -lserial -lpthread -o $dir/fpga 4 | -------------------------------------------------------------------------------- /riscv/fpga/controller.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | int run_mode; 9 | 10 | #define error(msg...) printf(msg) 11 | #define info(msg...) do{if(run_mode) printf(msg);}while(0) 12 | 13 | typedef std::uint8_t byte; 14 | typedef std::uint16_t word; 15 | typedef std::uint32_t dword; 16 | 17 | serial::Serial serPort; 18 | 19 | void uart_send(const byte *data, int send_count, byte* recv, int return_count) { 20 | serPort.write(data,send_count); 21 | if (!return_count) return; 22 | try { 23 | serPort.read(recv,return_count); 24 | } catch (std::exception &e) { 25 | error("recv error: %s\n",e.what()); 26 | } 27 | } 28 | void uart_send(const std::vector data, byte* recv, int return_count) { 29 | uart_send(data.data(),data.size(),recv,return_count); 30 | } 31 | void uart_send(const std::string &data) { serPort.write(data); } 32 | void uart_send(const byte *data, int size) { serPort.write(data,size); } 33 | void uart_send(const std::vector &data) { serPort.write(data); } 34 | void uart_read(byte *data, int size) { serPort.read(data, size); } 35 | 36 | #include "listener.h" 37 | 38 | int init_port(char* port) { 39 | serPort.setPort(port); 40 | serPort.setBaudrate(baud_rate); 41 | serPort.setBytesize(byte_size); 42 | serPort.setParity(parity); 43 | serPort.setStopbits(stopbits); 44 | serPort.setTimeout( 45 | inter_byte_timeout, 46 | read_timeout_constant, 47 | read_timeout_multiplier, 48 | write_timeout_constant, 49 | write_timeout_multiplier 50 | ); 51 | try { 52 | serPort.open(); 53 | } catch (std::exception &e) { 54 | error("failed to open port: %s\n",e.what()); 55 | return 1; 56 | } 57 | info("initialized UART port on: %s\n",port); 58 | return 0; 59 | } 60 | 61 | byte ram_data[0x40000]; 62 | byte in_data[0x400]; 63 | 64 | int load_ram(char* rom_path) { 65 | std::ifstream fin(rom_path); 66 | if (!fin.is_open()) return 0; 67 | fin.seekg(0, std::ios_base::end); 68 | int ram_size = fin.tellg(); 69 | info("RAM size: %x\n", ram_size); 70 | fin.seekg(0, std::ios_base::beg); 71 | fin.read(reinterpret_cast(ram_data), ram_size); 72 | for (int i=0;i<0x40; ++i) { 73 | info("%02x ", (byte)ram_data[i+0x1000]); 74 | if (!((i+1)%16)) info("\n"); 75 | } 76 | fin.close(); 77 | return ram_size; 78 | } 79 | 80 | int load_input(char* in_path) { 81 | if (!in_path) return 0; 82 | std::ifstream fin(in_path); 83 | if (!fin.is_open()) return 0; 84 | fin.seekg(0, std::ios_base::end); 85 | int in_size = fin.tellg(); 86 | info("INPUT size: %x\n", in_size); 87 | fin.seekg(0, std::ios_base::beg); 88 | fin.read(reinterpret_cast(in_data), in_size); 89 | for (int i=0;i<0x10; ++i) { 90 | info("%02x ", (byte)in_data[i]); 91 | if (!((i+1)%16)) info("\n"); 92 | } 93 | fin.close(); 94 | return in_size; 95 | } 96 | 97 | clock_t start_tm; 98 | clock_t end_tm; 99 | 100 | void run() { 101 | // demo 102 | 103 | // debug packet format: see hci.v or README.md 104 | // send[0] is always OPCODE 105 | // to send debug packets, use uart_send(send,send_count) 106 | // to receive data after send, use uart_send(send,send_count,recv,recv_count) 107 | char c; 108 | int run = 0; 109 | while (1){ 110 | info("Enter r to run, q to quit, p to get cpu PC(demo)\n"); 111 | c=getchar(); 112 | if (c=='q') { 113 | break; 114 | } 115 | else if (c=='p') { 116 | // demo for debugging cpu 117 | // add support in hci.v to allow more debug operations 118 | byte send[6]={0}; 119 | byte recv[64]={0}; 120 | send[0]=0x01; 121 | uart_send(send,1,recv,4); 122 | int pc = *reinterpret_cast(recv); 123 | info("pc:%08x\n",pc); 124 | send[0] = 0x09; 125 | int get_size = 16; 126 | *reinterpret_cast(send+1)=pc; 127 | *reinterpret_cast(send+4)=get_size; 128 | uart_send(send,6,recv,get_size); 129 | for (int i=0;i<16;++i) { 130 | info("%02x ",recv[i]); 131 | } 132 | info("\n"); 133 | } 134 | else if (c=='r') { 135 | // run or pause cpu 136 | byte send[2]; 137 | send[0]=(run?0x03:0x04); 138 | run = !run; 139 | info("CPU start\n"); 140 | uart_send(send,1); 141 | start_tm = clock(); 142 | // receive output bytes from fpga 143 | while (1) { 144 | byte data; 145 | // to debug cpu at the same time, implement separate thread 146 | while (!serPort.available()); 147 | uart_read(&data,1); 148 | if (on_recv(data)) break; 149 | } 150 | end_tm = clock(); 151 | info("\nCPU returned with running time: %f\n",(double)(end_tm - start_tm) / CLOCKS_PER_SEC); 152 | 153 | // manually pressing reset button is recommended 154 | 155 | // or pause and reset cpu through uart (TODO) 156 | // send[0]=(run?0x03:0x04); 157 | // run = !run; 158 | // uart_send(send,1); 159 | 160 | return; 161 | } 162 | } 163 | } 164 | 165 | void run_auto() { 166 | byte send[2]; 167 | send[0]=(0x04); 168 | uart_send(send,1); 169 | start_tm = clock(); 170 | while (1) { 171 | byte data; 172 | while (!serPort.available()); 173 | uart_read(&data,1); 174 | if (data==0) break; 175 | putchar(data); 176 | } 177 | end_tm = clock(); 178 | } 179 | 180 | int main(int argc, char** argv) { 181 | if (argc<4) { 182 | error("usage: path-to-ram [path-to-input] com-port -I(interactive)/-T(testing)\n"); 183 | return 1; 184 | } 185 | char* ram_path = argv[1]; 186 | int no_input = argc<5; 187 | char* input_path = no_input ? NULL : argv[2]; 188 | char* comport = argv[argc-2]; 189 | char param = argv[argc-1][1]; 190 | if (param=='I') { 191 | run_mode = 1; 192 | } else if (param=='T') { 193 | run_mode = 0; 194 | } 195 | int ram_size = 0, in_size = 0; 196 | if (!(ram_size=load_ram(ram_path))) { 197 | error("failed to read ram file\n"); 198 | return 1; 199 | } 200 | if (!no_input && !(in_size=load_input(input_path))){ 201 | info("input file not found, skipping\n"); 202 | } 203 | if (init_port(comport)) return 1; 204 | if (on_init()) return 1; 205 | upload_ram(ram_data, ram_size); 206 | upload_input(in_data, in_size); 207 | // verify_ram(ram_data, ram_size); 208 | if (run_mode) run(); 209 | else run_auto(); 210 | serPort.close(); 211 | } 212 | -------------------------------------------------------------------------------- /riscv/fpga/listener.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | // UART port configuration, adjust according to implementation 9 | int baud_rate = 115200; 10 | serial::bytesize_t byte_size = serial::eightbits; 11 | serial::parity_t parity = serial::parity_odd; 12 | serial::stopbits_t stopbits = serial::stopbits_one; 13 | int inter_byte_timeout = 50; 14 | int read_timeout_constant = 50; 15 | int read_timeout_multiplier = 10; 16 | int write_timeout_constant = 50; 17 | int write_timeout_multiplier = 10; 18 | 19 | //methods 20 | int on_init() { 21 | using namespace std::chrono_literals; 22 | byte junk[10]; 23 | uart_read(junk,8); 24 | std::this_thread::sleep_for(std::chrono::seconds(1)); 25 | byte init[10]; 26 | byte recv[10]={0}; 27 | init[0] = 0x00; 28 | int len = 4; 29 | *reinterpret_cast(init+1) = len; 30 | char test[10] = "UART"; 31 | for (int i=0;i(recv); 42 | if (strcmp(str,test)) { 43 | error("UART assertion failed\n"); 44 | return 1; 45 | } 46 | return 0; 47 | } 48 | 49 | void upload_ram(byte* ram_data, int ram_size) { 50 | if (!ram_size) return; 51 | const int short blk_size = 0x400; 52 | const int pld_size = 1+3+2+blk_size; 53 | byte payload[pld_size]; 54 | int blk_cnt = (ram_size / blk_size); 55 | if (blk_cnt*blk_size(payload+1) = addr; 63 | *reinterpret_cast(payload+4) = blk_size; 64 | for (int j=0;j(payload+1) = pre_size; 85 | uart_send(payload,1+2+pre_size); 86 | int rem_size = in_size; 87 | for (int i=0; i(payload+1) = dat_size; 93 | for (int j=0;j(payload+1) = addr; 117 | *reinterpret_cast(payload+4) = blk_size; 118 | uart_send(payload,6,recv_data,blk_size); 119 | for (int j=0; j ' + ('NUL' if isWin else '/dev/null')) 18 | 19 | def collect_test_cases(): 20 | test_cases = [] 21 | for f in os.listdir(test_cases_dir): 22 | if os.path.splitext(f)[1] == '.ans': 23 | test_cases.append(os.path.splitext(os.path.split(f)[1])[0]) 24 | for s in excluded_test_cases: 25 | if s in test_cases: test_cases.remove(s) 26 | test_cases.sort() 27 | return test_cases 28 | 29 | def main(): 30 | program_device() 31 | test_cases = collect_test_cases() 32 | 33 | print('Build controller...') 34 | if os.system(wslPrefix + './ctrl/build.sh'): 35 | print(color_red + 'Build Failed' + color_none) 36 | return 37 | print(color_green + 'Success' + color_none) 38 | 39 | for t in test_cases: 40 | print('Testing ' + t + ': ') 41 | if os.system(wslPrefix + './autorun_fpga.sh ' + t): 42 | print(color_red + 'Test Failed' + color_none) 43 | continue 44 | if os.system(wslPrefix + 'diff ./test/test.ans ./test/test.out > diff.out'): 45 | print(color_red + 'Wrong Answer' + color_none) 46 | continue 47 | print(color_green + 'Accepted' + color_none) 48 | 49 | if __name__ == '__main__': 50 | main() -------------------------------------------------------------------------------- /riscv/script/autorun_fpga.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # build testcase 3 | ./build_test.sh $@ 4 | # copy test input 5 | if [ -f ./testspace/$@.in ]; then cp ./testspace/$@.in ./test/test.in; fi 6 | # copy test output 7 | if [ -f ./testspace/$@.ans ]; then cp ./testspace/$@.ans ./test/test.ans; fi 8 | # add your own test script here 9 | # Example: assuming serial port on /dev/ttyUSB1 10 | # ./fpga/build.sh 11 | # ./fpga/run.sh ./test/test.bin ./test/test.in /dev/ttyUSB1 -I 12 | ./fpga/run.sh ./test/test.bin ./test/test.in /dev/ttyUSB1 -T > ./test/test.out -------------------------------------------------------------------------------- /riscv/script/build_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | set -e 3 | prefix='/opt/riscv' 4 | rpath=$prefix/bin/ 5 | # clearing test dir 6 | rm -rf ./test 7 | mkdir ./test 8 | # compiling rom 9 | ${rpath}riscv32-unknown-elf-as -o ./sys/rom.o -march=rv32i ./sys/rom.s 10 | # compiling testcase 11 | cp ./testcase/${1%.*}.c ./test/test.c 12 | ${rpath}riscv32-unknown-elf-gcc -o ./test/test.o -I ./sys -c ./test/test.c -O2 -march=rv32i -mabi=ilp32 -Wall 13 | # linking 14 | ${rpath}riscv32-unknown-elf-ld -T ./sys/memory.ld ./sys/rom.o ./test/test.o -L $prefix/riscv32-unknown-elf/lib/ -L $prefix/lib/gcc/riscv32-unknown-elf/8.2.0/ -lc -lgcc -lm -lnosys -o ./test/test.om 15 | # converting to verilog format 16 | ${rpath}riscv32-unknown-elf-objcopy -O verilog ./test/test.om ./test/test.data 17 | # converting to binary format(for ram uploading) 18 | ${rpath}riscv32-unknown-elf-objcopy -O binary ./test/test.om ./test/test.bin 19 | # decompile (for debugging) 20 | ${rpath}riscv32-unknown-elf-objdump -D ./test/test.om > ./test/test.dump 21 | -------------------------------------------------------------------------------- /riscv/script/run_test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # build testcase 3 | ./build_test.sh $@ 4 | # copy test input 5 | if [ -f ./testspace/$@.in ]; then cp ./testspace/$@.in ./test/test.in; fi 6 | # copy test output 7 | if [ -f ./testspace/$@.ans ]; then cp ./testspace/$@.ans ./test/test.ans; fi 8 | # add your own test script here 9 | # Example: 10 | # - iverilog/gtkwave/vivado 11 | # - diff ./test/test.ans ./test/test.out 12 | -------------------------------------------------------------------------------- /riscv/script/run_test_fpga.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # build testcase 3 | ./build_test.sh $@ 4 | # copy test input 5 | if [ -f ./testspace/$@.in ]; then cp ./testspace/$@.in ./test/test.in; fi 6 | # copy test output 7 | if [ -f ./testspace/$@.ans ]; then cp ./testspace/$@.ans ./test/test.ans; fi 8 | # add your own test script here 9 | # Example: assuming serial port on /dev/ttyUSB1 10 | ./ctrl/build.sh 11 | ./ctrl/run.sh ./test/test.bin ./test/test.in /dev/ttyUSB1 -I 12 | #./ctrl/run.sh ./test/test.bin ./test/test.in /dev/ttyUSB1 -T > ./test/test.out 13 | #if [ -f ./test/test.ans ]; then diff ./test/test.ans ./test/test.out; fi 14 | -------------------------------------------------------------------------------- /riscv/sim/testbench.v: -------------------------------------------------------------------------------- 1 | // testbench top module file 2 | // for simulation only 3 | 4 | `timescale 1ns/1ps 5 | module testbench; 6 | 7 | reg clk; 8 | reg rst; 9 | 10 | riscv_top #(.SIM(1)) top( 11 | .EXCLK(clk), 12 | .btnC(rst), 13 | .Tx(), 14 | .Rx(), 15 | .led() 16 | ); 17 | 18 | initial begin 19 | clk=0; 20 | rst=1; 21 | repeat(50) #1 clk=!clk; 22 | rst=0; 23 | forever #1 clk=!clk; 24 | 25 | $finish; 26 | end 27 | 28 | initial begin 29 | $dumpfile("test.vcd"); 30 | $dumpvars(0, testbench); 31 | #300000000 $finish; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /riscv/src/Basys-3-Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | set_property PACKAGE_PIN W5 [get_ports EXCLK] 8 | set_property IOSTANDARD LVCMOS33 [get_ports EXCLK] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports EXCLK] 10 | 11 | ## Switches 12 | #set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | #set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | #set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | #set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | #set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | #set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | #set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | #set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | #set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | #set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | #set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | #set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | #set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | #set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | #set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | #set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | 46 | ## LEDs 47 | set_property PACKAGE_PIN U16 [get_ports led] 48 | set_property IOSTANDARD LVCMOS33 [get_ports led] 49 | #set_property PACKAGE_PIN E19 [get_ports {led[1]}] 50 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] 51 | #set_property PACKAGE_PIN U19 [get_ports {led[2]}] 52 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] 53 | #set_property PACKAGE_PIN V19 [get_ports {led[3]}] 54 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] 55 | #set_property PACKAGE_PIN W18 [get_ports {led[4]}] 56 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] 57 | #set_property PACKAGE_PIN U15 [get_ports {led[5]}] 58 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] 59 | #set_property PACKAGE_PIN U14 [get_ports {led[6]}] 60 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] 61 | #set_property PACKAGE_PIN V14 [get_ports {led[7]}] 62 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] 63 | #set_property PACKAGE_PIN V13 [get_ports {led[8]}] 64 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] 65 | #set_property PACKAGE_PIN V3 [get_ports {led[9]}] 66 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] 67 | #set_property PACKAGE_PIN W3 [get_ports {led[10]}] 68 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] 69 | #set_property PACKAGE_PIN U3 [get_ports {led[11]}] 70 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] 71 | #set_property PACKAGE_PIN P3 [get_ports {led[12]}] 72 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] 73 | #set_property PACKAGE_PIN N3 [get_ports {led[13]}] 74 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] 75 | #set_property PACKAGE_PIN P1 [get_ports {led[14]}] 76 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] 77 | #set_property PACKAGE_PIN L1 [get_ports {led[15]}] 78 | #set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] 79 | 80 | 81 | ##7 segment display 82 | #set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 83 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 84 | #set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 85 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 86 | #set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 87 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 88 | #set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 89 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 90 | #set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 91 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 92 | #set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 93 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 94 | #set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 95 | #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 96 | 97 | #set_property PACKAGE_PIN V7 [get_ports dp] 98 | #set_property IOSTANDARD LVCMOS33 [get_ports dp] 99 | 100 | #set_property PACKAGE_PIN U2 [get_ports {an[0]}] 101 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 102 | #set_property PACKAGE_PIN U4 [get_ports {an[1]}] 103 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 104 | #set_property PACKAGE_PIN V4 [get_ports {an[2]}] 105 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 106 | #set_property PACKAGE_PIN W4 [get_ports {an[3]}] 107 | #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 108 | 109 | 110 | ##Buttons 111 | set_property PACKAGE_PIN U18 [get_ports btnC] 112 | set_property IOSTANDARD LVCMOS33 [get_ports btnC] 113 | #set_property PACKAGE_PIN T18 [get_ports btnU] 114 | #set_property IOSTANDARD LVCMOS33 [get_ports btnU] 115 | #set_property PACKAGE_PIN W19 [get_ports btnL] 116 | #set_property IOSTANDARD LVCMOS33 [get_ports btnL] 117 | #set_property PACKAGE_PIN T17 [get_ports btnR] 118 | #set_property IOSTANDARD LVCMOS33 [get_ports btnR] 119 | #set_property PACKAGE_PIN U17 [get_ports btnD] 120 | #set_property IOSTANDARD LVCMOS33 [get_ports btnD] 121 | 122 | 123 | 124 | ##Pmod Header JA 125 | ##Sch name = JA1 126 | #set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 127 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 128 | ##Sch name = JA2 129 | #set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 130 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 131 | ##Sch name = JA3 132 | #set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 133 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 134 | ##Sch name = JA4 135 | #set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 136 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 137 | ##Sch name = JA7 138 | #set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 139 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 140 | ##Sch name = JA8 141 | #set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 142 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 143 | ##Sch name = JA9 144 | #set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 145 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 146 | ##Sch name = JA10 147 | #set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 148 | #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 149 | 150 | 151 | 152 | ##Pmod Header JB 153 | ##Sch name = JB1 154 | #set_property PACKAGE_PIN A14 [get_ports {JB[0]}] 155 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] 156 | ##Sch name = JB2 157 | #set_property PACKAGE_PIN A16 [get_ports {JB[1]}] 158 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] 159 | ##Sch name = JB3 160 | #set_property PACKAGE_PIN B15 [get_ports {JB[2]}] 161 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] 162 | ##Sch name = JB4 163 | #set_property PACKAGE_PIN B16 [get_ports {JB[3]}] 164 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] 165 | ##Sch name = JB7 166 | #set_property PACKAGE_PIN A15 [get_ports {JB[4]}] 167 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] 168 | ##Sch name = JB8 169 | #set_property PACKAGE_PIN A17 [get_ports {JB[5]}] 170 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] 171 | ##Sch name = JB9 172 | #set_property PACKAGE_PIN C15 [get_ports {JB[6]}] 173 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] 174 | ##Sch name = JB10 175 | #set_property PACKAGE_PIN C16 [get_ports {JB[7]}] 176 | #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] 177 | 178 | 179 | 180 | ##Pmod Header JC 181 | ##Sch name = JC1 182 | #set_property PACKAGE_PIN K17 [get_ports {JC[0]}] 183 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] 184 | ##Sch name = JC2 185 | #set_property PACKAGE_PIN M18 [get_ports {JC[1]}] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] 187 | ##Sch name = JC3 188 | #set_property PACKAGE_PIN N17 [get_ports {JC[2]}] 189 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] 190 | ##Sch name = JC4 191 | #set_property PACKAGE_PIN P18 [get_ports {JC[3]}] 192 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] 193 | ##Sch name = JC7 194 | #set_property PACKAGE_PIN L17 [get_ports {JC[4]}] 195 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] 196 | ##Sch name = JC8 197 | #set_property PACKAGE_PIN M19 [get_ports {JC[5]}] 198 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] 199 | ##Sch name = JC9 200 | #set_property PACKAGE_PIN P17 [get_ports {JC[6]}] 201 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] 202 | ##Sch name = JC10 203 | #set_property PACKAGE_PIN R18 [get_ports {JC[7]}] 204 | #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] 205 | 206 | 207 | ##Pmod Header JXADC 208 | ##Sch name = XA1_P 209 | #set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}] 210 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] 211 | ##Sch name = XA2_P 212 | #set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}] 213 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] 214 | ##Sch name = XA3_P 215 | #set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}] 216 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] 217 | ##Sch name = XA4_P 218 | #set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}] 219 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] 220 | ##Sch name = XA1_N 221 | #set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}] 222 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] 223 | ##Sch name = XA2_N 224 | #set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}] 225 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] 226 | ##Sch name = XA3_N 227 | #set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}] 228 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] 229 | ##Sch name = XA4_N 230 | #set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}] 231 | #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] 232 | 233 | 234 | 235 | ##VGA Connector 236 | #set_property PACKAGE_PIN G19 [get_ports {vgaRed[0]}] 237 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] 238 | #set_property PACKAGE_PIN H19 [get_ports {vgaRed[1]}] 239 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] 240 | #set_property PACKAGE_PIN J19 [get_ports {vgaRed[2]}] 241 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] 242 | #set_property PACKAGE_PIN N19 [get_ports {vgaRed[3]}] 243 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] 244 | #set_property PACKAGE_PIN N18 [get_ports {vgaBlue[0]}] 245 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] 246 | #set_property PACKAGE_PIN L18 [get_ports {vgaBlue[1]}] 247 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] 248 | #set_property PACKAGE_PIN K18 [get_ports {vgaBlue[2]}] 249 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] 250 | #set_property PACKAGE_PIN J18 [get_ports {vgaBlue[3]}] 251 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] 252 | #set_property PACKAGE_PIN J17 [get_ports {vgaGreen[0]}] 253 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] 254 | #set_property PACKAGE_PIN H17 [get_ports {vgaGreen[1]}] 255 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] 256 | #set_property PACKAGE_PIN G17 [get_ports {vgaGreen[2]}] 257 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] 258 | #set_property PACKAGE_PIN D17 [get_ports {vgaGreen[3]}] 259 | #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] 260 | #set_property PACKAGE_PIN P19 [get_ports Hsync] 261 | #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] 262 | #set_property PACKAGE_PIN R19 [get_ports Vsync] 263 | #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] 264 | 265 | 266 | ##USB-RS232 Interface 267 | set_property PACKAGE_PIN B18 [get_ports Rx] 268 | set_property IOSTANDARD LVCMOS33 [get_ports Rx] 269 | set_property PACKAGE_PIN A18 [get_ports Tx] 270 | set_property IOSTANDARD LVCMOS33 [get_ports Tx] 271 | 272 | 273 | ##USB HID (PS/2) 274 | #set_property PACKAGE_PIN C17 [get_ports PS2Clk] 275 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] 276 | #set_property PULLUP true [get_ports PS2Clk] 277 | #set_property PACKAGE_PIN B17 [get_ports PS2Data] 278 | #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] 279 | #set_property PULLUP true [get_ports PS2Data] 280 | 281 | 282 | ##Quad SPI Flash 283 | ##Note that CCLK_0 cannot be placed in 7 series devices. You can access it using the 284 | ##STARTUPE2 primitive. 285 | #set_property PACKAGE_PIN D18 [get_ports {QspiDB[0]}] 286 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] 287 | #set_property PACKAGE_PIN D19 [get_ports {QspiDB[1]}] 288 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] 289 | #set_property PACKAGE_PIN G18 [get_ports {QspiDB[2]}] 290 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] 291 | #set_property PACKAGE_PIN F18 [get_ports {QspiDB[3]}] 292 | #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] 293 | #set_property PACKAGE_PIN K19 [get_ports QspiCSn] 294 | #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] 295 | 296 | 297 | ## Configuration options, can be used for all designs 298 | set_property CONFIG_VOLTAGE 3.3 [current_design] 299 | set_property CFGBVS VCCO [current_design] 300 | -------------------------------------------------------------------------------- /riscv/src/common/block_ram/block_ram.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | * 3 | * Copyright (c) 2012, Brian Bennett 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without modification, are permitted 7 | * provided that the following conditions are met: 8 | * 9 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 10 | * and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 12 | * conditions and the following disclaimer in the documentation and/or other materials provided 13 | * with the distribution. 14 | * 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 17 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 22 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 | * 24 | * Various generic, inferred block ram descriptors. 25 | ***************************************************************************************************/ 26 | 27 | // Dual port RAM with synchronous read. Modified version of listing 12.4 in "FPGA Prototyping by 28 | // Verilog Examples," itself a modified version of XST 8.11 v_rams_11. 29 | module dual_port_ram_sync 30 | #( 31 | parameter ADDR_WIDTH = 6, 32 | parameter DATA_WIDTH = 8 33 | ) 34 | ( 35 | input wire clk, 36 | input wire we, 37 | input wire [ADDR_WIDTH-1:0] addr_a, 38 | input wire [ADDR_WIDTH-1:0] addr_b, 39 | input wire [DATA_WIDTH-1:0] din_a, 40 | output wire [DATA_WIDTH-1:0] dout_a, 41 | output wire [DATA_WIDTH-1:0] dout_b 42 | ); 43 | 44 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 45 | reg [ADDR_WIDTH-1:0] q_addr_a; 46 | reg [ADDR_WIDTH-1:0] q_addr_b; 47 | 48 | always @(posedge clk) 49 | begin 50 | if (we) 51 | ram[addr_a] <= din_a; 52 | q_addr_a <= addr_a; 53 | q_addr_b <= addr_b; 54 | end 55 | 56 | assign dout_a = ram[q_addr_a]; 57 | assign dout_b = ram[q_addr_b]; 58 | 59 | endmodule 60 | 61 | // Single port RAM with synchronous read. 62 | module single_port_ram_sync 63 | #( 64 | parameter ADDR_WIDTH = 6, 65 | parameter DATA_WIDTH = 8 66 | ) 67 | ( 68 | input wire clk, 69 | input wire we, 70 | input wire [ADDR_WIDTH-1:0] addr_a, 71 | input wire [DATA_WIDTH-1:0] din_a, 72 | output wire [DATA_WIDTH-1:0] dout_a 73 | ); 74 | 75 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 76 | reg [ADDR_WIDTH-1:0] q_addr_a; 77 | 78 | always @(posedge clk) 79 | begin 80 | if (we) 81 | ram[addr_a] <= din_a; 82 | q_addr_a <= addr_a; 83 | end 84 | 85 | assign dout_a = ram[q_addr_a]; 86 | 87 | // initialize ram content (for simulation) 88 | integer i; 89 | initial begin 90 | for (i=0;i<2**ADDR_WIDTH;i=i+1) begin 91 | ram[i] = 0; 92 | end 93 | $readmemh("test.data", ram); // add test.data to vivado project or specify a valid file path 94 | end 95 | 96 | endmodule 97 | 98 | -------------------------------------------------------------------------------- /riscv/src/common/fifo/fifo.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | * 3 | * Copyright (c) 2012, Brian Bennett 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without modification, are permitted 7 | * provided that the following conditions are met: 8 | * 9 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 10 | * and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 12 | * conditions and the following disclaimer in the documentation and/or other materials provided 13 | * with the distribution. 14 | * 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 17 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 22 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 | * 24 | * Circular first in first out buffer implementation. 25 | ***************************************************************************************************/ 26 | 27 | module fifo 28 | #( 29 | parameter DATA_BITS = 8, 30 | parameter ADDR_BITS = 3 31 | ) 32 | ( 33 | input wire clk, // 50MHz system clock 34 | input wire reset, // Reset signal 35 | input wire rd_en, // Read enable, pop front of queue 36 | input wire wr_en, // Write enable, add wr_data to end of queue 37 | input wire [DATA_BITS-1:0] wr_data, // Data to be written on wr_en 38 | output wire [DATA_BITS-1:0] rd_data, // Current front of fifo data 39 | output wire full, // FIFO is full (writes invalid) 40 | output wire empty // FIFO is empty (reads invalid) 41 | ); 42 | 43 | reg [ADDR_BITS-1:0] q_rd_ptr; 44 | wire [ADDR_BITS-1:0] d_rd_ptr; 45 | reg [ADDR_BITS-1:0] q_wr_ptr; 46 | wire [ADDR_BITS-1:0] d_wr_ptr; 47 | reg q_empty; 48 | wire d_empty; 49 | reg q_full; 50 | wire d_full; 51 | 52 | reg [DATA_BITS-1:0] q_data_array [2**ADDR_BITS-1:0]; 53 | wire [DATA_BITS-1:0] d_data; 54 | 55 | wire rd_en_prot; 56 | wire wr_en_prot; 57 | 58 | // FF update logic. Synchronous reset. 59 | always @(posedge clk) 60 | begin 61 | if (reset) 62 | begin 63 | q_rd_ptr <= 0; 64 | q_wr_ptr <= 0; 65 | q_empty <= 1'b1; 66 | q_full <= 1'b0; 67 | end 68 | else 69 | begin 70 | q_rd_ptr <= d_rd_ptr; 71 | q_wr_ptr <= d_wr_ptr; 72 | q_empty <= d_empty; 73 | q_full <= d_full; 74 | q_data_array[q_wr_ptr] <= d_data; 75 | end 76 | end 77 | 78 | // Derive "protected" read/write signals. 79 | assign rd_en_prot = (rd_en && !q_empty); 80 | assign wr_en_prot = (wr_en && !q_full); 81 | 82 | // Handle writes. 83 | assign d_wr_ptr = (wr_en_prot) ? q_wr_ptr + 1'h1 : q_wr_ptr; 84 | assign d_data = (wr_en_prot) ? wr_data : q_data_array[q_wr_ptr]; 85 | 86 | // Handle reads. 87 | assign d_rd_ptr = (rd_en_prot) ? q_rd_ptr + 1'h1 : q_rd_ptr; 88 | 89 | wire [ADDR_BITS-1:0] addr_bits_wide_1; 90 | assign addr_bits_wide_1 = 1; 91 | 92 | // Detect empty state: 93 | // 1) We were empty before and there was no write. 94 | // 2) We had one entry and there was a read. 95 | assign d_empty = ((q_empty && !wr_en_prot) || 96 | (((q_wr_ptr - q_rd_ptr) == addr_bits_wide_1) && rd_en_prot)); 97 | 98 | // Detect full state: 99 | // 1) We were full before and there was no read. 100 | // 2) We had n-1 entries and there was a write. 101 | assign d_full = ((q_full && !rd_en_prot) || 102 | (((q_rd_ptr - q_wr_ptr) == addr_bits_wide_1) && wr_en_prot)); 103 | 104 | // Assign output signals to appropriate FFs. 105 | assign rd_data = q_data_array[q_rd_ptr]; 106 | assign full = q_full; 107 | assign empty = q_empty; 108 | 109 | endmodule 110 | 111 | -------------------------------------------------------------------------------- /riscv/src/common/uart/uart.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | * 3 | * Copyright (c) 2012, Brian Bennett 4 | * All rights reserved. 5 | * 6 | * Redistribution and use in source and binary forms, with or without modification, are permitted 7 | * provided that the following conditions are met: 8 | * 9 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 10 | * and the following disclaimer. 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 12 | * conditions and the following disclaimer in the documentation and/or other materials provided 13 | * with the distribution. 14 | * 15 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 16 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 17 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 21 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 22 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 | * 24 | * UART controller. Universal Asynchronous Receiver/Transmitter control module for an RS-232 25 | * (serial) port. 26 | ***************************************************************************************************/ 27 | 28 | module uart 29 | #( 30 | parameter SYS_CLK_FREQ = 50000000, 31 | parameter BAUD_RATE = 19200, 32 | parameter DATA_BITS = 8, 33 | parameter STOP_BITS = 1, 34 | parameter PARITY_MODE = 0 // 0 = none, 1 = odd, 2 = even 35 | ) 36 | ( 37 | input wire clk, // System clk 38 | input wire reset, // Reset signal 39 | input wire rx, // RS-232 rx pin 40 | input wire [DATA_BITS-1:0] tx_data, // Data to be transmitted when wr_en is 1 41 | input wire rd_en, // Pops current read FIFO front off the queue 42 | input wire wr_en, // Write tx_data over serial connection 43 | output wire tx, // RS-232 tx pin 44 | output wire [DATA_BITS-1:0] rx_data, // Data currently at front of read FIFO 45 | output wire rx_empty, // 1 if there is no more read data available 46 | output wire tx_full, // 1 if the transmit FIFO cannot accept more requests 47 | output wire parity_err // 1 if a parity error has been detected 48 | ); 49 | 50 | localparam BAUD_CLK_OVERSAMPLE_RATE = 16; 51 | 52 | wire baud_clk_tick; 53 | 54 | wire [DATA_BITS-1:0] rx_fifo_wr_data; 55 | wire rx_done_tick; 56 | wire rx_parity_err; 57 | 58 | wire [DATA_BITS-1:0] tx_fifo_rd_data; 59 | wire tx_done_tick; 60 | wire tx_fifo_empty; 61 | 62 | // Store parity error in a flip flop as persistent state. 63 | reg q_rx_parity_err; 64 | wire d_rx_parity_err; 65 | 66 | always @(posedge clk, posedge reset) 67 | begin 68 | if (reset) 69 | q_rx_parity_err <= 1'b0; 70 | else 71 | q_rx_parity_err <= d_rx_parity_err; 72 | end 73 | 74 | assign parity_err = q_rx_parity_err; 75 | assign d_rx_parity_err = q_rx_parity_err || rx_parity_err; 76 | 77 | // BAUD clock module 78 | uart_baud_clk #(.SYS_CLK_FREQ(SYS_CLK_FREQ), 79 | .BAUD(BAUD_RATE), 80 | .BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_baud_clk_blk 81 | ( 82 | .clk(clk), 83 | .reset(reset), 84 | .baud_clk_tick(baud_clk_tick) 85 | ); 86 | 87 | // RX (receiver) module 88 | uart_rx #(.DATA_BITS(DATA_BITS), 89 | .STOP_BITS(STOP_BITS), 90 | .PARITY_MODE(PARITY_MODE), 91 | .BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_rx_blk 92 | ( 93 | .clk(clk), 94 | .reset(reset), 95 | .baud_clk_tick(baud_clk_tick), 96 | .rx(rx), 97 | .rx_data(rx_fifo_wr_data), 98 | .rx_done_tick(rx_done_tick), 99 | .parity_err(rx_parity_err) 100 | ); 101 | 102 | // TX (transmitter) module 103 | uart_tx #(.DATA_BITS(DATA_BITS), 104 | .STOP_BITS(STOP_BITS), 105 | .PARITY_MODE(PARITY_MODE), 106 | .BAUD_CLK_OVERSAMPLE_RATE(BAUD_CLK_OVERSAMPLE_RATE)) uart_tx_blk 107 | ( 108 | .clk(clk), 109 | .reset(reset), 110 | .baud_clk_tick(baud_clk_tick), 111 | .tx_start(~tx_fifo_empty), 112 | .tx_data(tx_fifo_rd_data), 113 | .tx_done_tick(tx_done_tick), 114 | .tx(tx) 115 | ); 116 | 117 | // RX FIFO 118 | fifo #(.DATA_BITS(DATA_BITS), 119 | .ADDR_BITS(3)) uart_rx_fifo 120 | ( 121 | .clk(clk), 122 | .reset(reset), 123 | .rd_en(rd_en), 124 | .wr_en(rx_done_tick), 125 | .wr_data(rx_fifo_wr_data), 126 | .rd_data(rx_data), 127 | .empty(rx_empty), 128 | .full() 129 | ); 130 | 131 | // TX FIFO (increased size) 132 | fifo #(.DATA_BITS(DATA_BITS), 133 | .ADDR_BITS(10)) uart_tx_fifo 134 | ( 135 | .clk(clk), 136 | .reset(reset), 137 | .rd_en(tx_done_tick), 138 | .wr_en(wr_en), 139 | .wr_data(tx_data), 140 | .rd_data(tx_fifo_rd_data), 141 | .empty(tx_fifo_empty), 142 | .full(tx_full) 143 | ); 144 | 145 | endmodule 146 | 147 | -------------------------------------------------------------------------------- /riscv/src/common/uart/uart_baud_clk.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | ** fpga_nes/hw/src/cmn/uart/uart_baud_clk.v 3 | * 4 | * Copyright (c) 2012, Brian Bennett 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without modification, are permitted 8 | * provided that the following conditions are met: 9 | * 10 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 11 | * and the following disclaimer. 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 13 | * conditions and the following disclaimer in the documentation and/or other materials provided 14 | * with the distribution. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 18 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 23 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | * Generates a tick signal at OVERSAMPLE_RATE times the baud rate. Should be fed to the uart_rx 26 | * and uart_tx blocks. 27 | ***************************************************************************************************/ 28 | 29 | module uart_baud_clk 30 | #( 31 | parameter SYS_CLK_FREQ = 50000000, 32 | parameter BAUD = 19200, 33 | parameter BAUD_CLK_OVERSAMPLE_RATE = 16 34 | ) 35 | ( 36 | input wire clk, 37 | input wire reset, 38 | output wire baud_clk_tick 39 | ); 40 | 41 | localparam [15:0] CLKS_PER_OVERSAMPLE_TICK = (SYS_CLK_FREQ / BAUD) / BAUD_CLK_OVERSAMPLE_RATE; 42 | 43 | // Registers 44 | reg [15:0] q_cnt; 45 | wire [15:0] d_cnt; 46 | 47 | always @(posedge clk, posedge reset) 48 | begin 49 | if (reset) 50 | q_cnt <= 0; 51 | else 52 | q_cnt <= d_cnt; 53 | end 54 | 55 | assign d_cnt = (q_cnt == (CLKS_PER_OVERSAMPLE_TICK - 1)) ? 16'h0000 : (q_cnt + 16'h0001); 56 | assign baud_clk_tick = (q_cnt == (CLKS_PER_OVERSAMPLE_TICK - 1)) ? 1'b1 : 1'b0; 57 | 58 | endmodule 59 | 60 | -------------------------------------------------------------------------------- /riscv/src/common/uart/uart_rx.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | ** fpga_nes/hw/src/cmn/uart/uart_rx.v 3 | * 4 | * Copyright (c) 2012, Brian Bennett 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without modification, are permitted 8 | * provided that the following conditions are met: 9 | * 10 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 11 | * and the following disclaimer. 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 13 | * conditions and the following disclaimer in the documentation and/or other materials provided 14 | * with the distribution. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 18 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 23 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | * UART receiver. 26 | ***************************************************************************************************/ 27 | 28 | module uart_rx 29 | #( 30 | parameter DATA_BITS = 8, 31 | parameter STOP_BITS = 1, 32 | parameter PARITY_MODE = 1, // 0 = NONE, 1 = ODD, 2 = EVEN 33 | parameter BAUD_CLK_OVERSAMPLE_RATE = 16 34 | ) 35 | ( 36 | input wire clk, // System clock 37 | input wire reset, // Reset signal 38 | input wire baud_clk_tick, // 1 tick per OVERSAMPLE_RATE baud clks 39 | input wire rx, // RX transmission wire 40 | output wire [DATA_BITS-1:0] rx_data, // Output data 41 | output wire rx_done_tick, // Output rdy signal 42 | output wire parity_err // Asserted for one clk on parity error 43 | ); 44 | 45 | localparam [5:0] STOP_OVERSAMPLE_TICKS = STOP_BITS * BAUD_CLK_OVERSAMPLE_RATE; 46 | 47 | // Symbolic state representations. 48 | localparam [4:0] S_IDLE = 5'h01, 49 | S_START = 5'h02, 50 | S_DATA = 5'h04, 51 | S_PARITY = 5'h08, 52 | S_STOP = 5'h10; 53 | 54 | // Registers 55 | reg [4:0] q_state, d_state; 56 | reg [3:0] q_oversample_tick_cnt, d_oversample_tick_cnt; 57 | reg [DATA_BITS-1:0] q_data, d_data; 58 | reg [2:0] q_data_bit_idx, d_data_bit_idx; 59 | reg q_done_tick, d_done_tick; 60 | reg q_parity_err, d_parity_err; 61 | reg q_rx; 62 | 63 | always @(posedge clk, posedge reset) 64 | begin 65 | if (reset) 66 | begin 67 | q_state <= S_IDLE; 68 | q_oversample_tick_cnt <= 0; 69 | q_data <= 0; 70 | q_data_bit_idx <= 0; 71 | q_done_tick <= 1'b0; 72 | q_parity_err <= 1'b0; 73 | q_rx <= 1'b1; 74 | end 75 | else 76 | begin 77 | q_state <= d_state; 78 | q_oversample_tick_cnt <= d_oversample_tick_cnt; 79 | q_data <= d_data; 80 | q_data_bit_idx <= d_data_bit_idx; 81 | q_done_tick <= d_done_tick; 82 | q_parity_err <= d_parity_err; 83 | q_rx <= rx; 84 | end 85 | end 86 | 87 | always @* 88 | begin 89 | // Default most state to remain unchanged. 90 | d_state = q_state; 91 | d_data = q_data; 92 | d_data_bit_idx = q_data_bit_idx; 93 | 94 | // Increment the tick counter if the baud_clk counter ticked. 95 | d_oversample_tick_cnt = (baud_clk_tick) ? q_oversample_tick_cnt + 4'h1 : q_oversample_tick_cnt; 96 | 97 | // Default the done signal and parity err to 0. 98 | d_done_tick = 1'b0; 99 | d_parity_err = 1'b0; 100 | 101 | case (q_state) 102 | S_IDLE: 103 | begin 104 | // Detect incoming data when rx goes low (start bit). 105 | if (~q_rx) 106 | begin 107 | d_state = S_START; 108 | d_oversample_tick_cnt = 0; 109 | end 110 | end 111 | 112 | S_START: 113 | begin 114 | // Wait for BAUD_CLK_OVERSAMPLE_RATE / 2 ticks to get "centered" in the start bit signal. 115 | if (baud_clk_tick && (q_oversample_tick_cnt == ((BAUD_CLK_OVERSAMPLE_RATE - 1) / 2))) 116 | begin 117 | d_state = S_DATA; 118 | d_oversample_tick_cnt = 0; 119 | d_data_bit_idx = 0; 120 | end 121 | end 122 | 123 | S_DATA: 124 | begin 125 | // Every BAUD_CLK_OVERSAMPLE_RATE clocks, sample rx and shift its value into the data reg. 126 | if (baud_clk_tick && (q_oversample_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1))) 127 | begin 128 | d_data = { q_rx, q_data[DATA_BITS-1:1] }; 129 | d_oversample_tick_cnt = 0; 130 | 131 | if (q_data_bit_idx == (DATA_BITS - 1)) 132 | begin 133 | if (PARITY_MODE == 0) 134 | d_state = S_STOP; 135 | else 136 | d_state = S_PARITY; 137 | end 138 | else 139 | d_data_bit_idx = q_data_bit_idx + 3'h1; 140 | end 141 | end 142 | 143 | S_PARITY: 144 | begin 145 | if (baud_clk_tick && (q_oversample_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1))) 146 | begin 147 | if (PARITY_MODE == 1) 148 | d_parity_err = (q_rx != ~^q_data); 149 | else 150 | d_parity_err = (q_rx != ^q_data); 151 | 152 | d_state = S_STOP; 153 | d_oversample_tick_cnt = 0; 154 | end 155 | end 156 | 157 | S_STOP: 158 | begin 159 | // Wait for stop bit before returning to idle. Signal done_tick. 160 | if (baud_clk_tick && (q_oversample_tick_cnt == STOP_OVERSAMPLE_TICKS - 1)) 161 | begin 162 | d_state = S_IDLE; 163 | d_done_tick = 1'b1; 164 | end 165 | end 166 | endcase 167 | end 168 | 169 | assign rx_data = q_data; 170 | assign rx_done_tick = q_done_tick; 171 | assign parity_err = q_parity_err; 172 | 173 | endmodule 174 | 175 | -------------------------------------------------------------------------------- /riscv/src/common/uart/uart_tx.v: -------------------------------------------------------------------------------- 1 | /*************************************************************************************************** 2 | ** fpga_nes/hw/src/cmn/uart/uart_tx.v 3 | * 4 | * Copyright (c) 2012, Brian Bennett 5 | * All rights reserved. 6 | * 7 | * Redistribution and use in source and binary forms, with or without modification, are permitted 8 | * provided that the following conditions are met: 9 | * 10 | * 1. Redistributions of source code must retain the above copyright notice, this list of conditions 11 | * and the following disclaimer. 12 | * 2. Redistributions in binary form must reproduce the above copyright notice, this list of 13 | * conditions and the following disclaimer in the documentation and/or other materials provided 14 | * with the distribution. 15 | * 16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR 17 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND 18 | * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 19 | * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY 23 | * WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 | * 25 | * UART transmitter. 26 | ***************************************************************************************************/ 27 | 28 | module uart_tx 29 | #( 30 | parameter DATA_BITS = 8, 31 | parameter STOP_BITS = 1, 32 | parameter PARITY_MODE = 1, // 0 = NONE, 1 = ODD, 2 = EVEN 33 | parameter BAUD_CLK_OVERSAMPLE_RATE = 16 34 | ) 35 | ( 36 | input wire clk, // System clock 37 | input wire reset, // Reset signal 38 | input wire baud_clk_tick, // 1 tick per OVERSAMPLE_RATE baud clks 39 | input wire tx_start, // Signal requesting trasmission start 40 | input wire [DATA_BITS-1:0] tx_data, // Data to be transmitted 41 | output wire tx_done_tick, // Transfer done signal 42 | output wire tx // TX transmission wire 43 | ); 44 | 45 | localparam [5:0] STOP_OVERSAMPLE_TICKS = STOP_BITS * BAUD_CLK_OVERSAMPLE_RATE; 46 | 47 | // Symbolic state representations. 48 | localparam [4:0] S_IDLE = 5'h01, 49 | S_START = 5'h02, 50 | S_DATA = 5'h04, 51 | S_PARITY = 5'h08, 52 | S_STOP = 5'h10; 53 | 54 | // Registers 55 | reg [4:0] q_state, d_state; 56 | reg [3:0] q_baud_clk_tick_cnt, d_baud_clk_tick_cnt; 57 | reg [DATA_BITS-1:0] q_data, d_data; 58 | reg [2:0] q_data_bit_idx, d_data_bit_idx; 59 | reg q_parity_bit, d_parity_bit; 60 | reg q_tx, d_tx; 61 | reg q_tx_done_tick, d_tx_done_tick; 62 | 63 | always @(posedge clk, posedge reset) 64 | begin 65 | if (reset) 66 | begin 67 | q_state <= S_IDLE; 68 | q_baud_clk_tick_cnt <= 0; 69 | q_data <= 0; 70 | q_data_bit_idx <= 0; 71 | q_tx <= 1'b1; 72 | q_tx_done_tick <= 1'b0; 73 | q_parity_bit <= 1'b0; 74 | end 75 | else 76 | begin 77 | q_state <= d_state; 78 | q_baud_clk_tick_cnt <= d_baud_clk_tick_cnt; 79 | q_data <= d_data; 80 | q_data_bit_idx <= d_data_bit_idx; 81 | q_tx <= d_tx; 82 | q_tx_done_tick <= d_tx_done_tick; 83 | q_parity_bit <= d_parity_bit; 84 | end 85 | end 86 | 87 | always @* 88 | begin 89 | // Default most state to remain unchanged. 90 | d_state = q_state; 91 | d_data = q_data; 92 | d_data_bit_idx = q_data_bit_idx; 93 | d_parity_bit = q_parity_bit; 94 | 95 | // Increment the tick counter if the baud clk counter ticked. 96 | d_baud_clk_tick_cnt = (baud_clk_tick) ? (q_baud_clk_tick_cnt + 4'h1) : q_baud_clk_tick_cnt; 97 | 98 | d_tx_done_tick = 1'b0; 99 | d_tx = 1'b1; 100 | 101 | case (q_state) 102 | S_IDLE: 103 | begin 104 | // Detect tx_start signal from client, latch data, and begin transmission. Don't latch 105 | // during done_tick. 106 | if (tx_start && ~q_tx_done_tick) 107 | begin 108 | d_state = S_START; 109 | d_baud_clk_tick_cnt = 0; 110 | d_data = tx_data; 111 | 112 | if (PARITY_MODE == 1) 113 | d_parity_bit = ~^tx_data; 114 | else if (PARITY_MODE == 2) 115 | d_parity_bit = ~tx_data; 116 | end 117 | end 118 | 119 | S_START: 120 | begin 121 | // Send low signal to indicate start bit. When done, move to data transmission. 122 | d_tx = 1'b0; 123 | if (baud_clk_tick && (q_baud_clk_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1))) 124 | begin 125 | d_state = S_DATA; 126 | d_baud_clk_tick_cnt = 0; 127 | d_data_bit_idx = 0; 128 | end 129 | end 130 | 131 | S_DATA: 132 | begin 133 | // Transmit current low data bit. After OVERSAMPLE_RATE ticks, shift the data reg 134 | // and move on to the next bit. After DATA_BITS bits, move to stop bit state. 135 | d_tx = q_data[0]; 136 | if (baud_clk_tick && (q_baud_clk_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1))) 137 | begin 138 | d_data = q_data >> 1; 139 | d_data_bit_idx = q_data_bit_idx + 3'h1; 140 | d_baud_clk_tick_cnt = 0; 141 | 142 | if (q_data_bit_idx == (DATA_BITS - 1)) 143 | begin 144 | if (PARITY_MODE == 0) 145 | d_state = S_STOP; 146 | else 147 | d_state = S_PARITY; 148 | end 149 | end 150 | end 151 | 152 | S_PARITY: 153 | begin 154 | // Send parity bit. 155 | d_tx = q_parity_bit; 156 | if (baud_clk_tick && (q_baud_clk_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1))) 157 | begin 158 | d_state = S_STOP; 159 | d_baud_clk_tick_cnt = 0; 160 | end 161 | end 162 | 163 | S_STOP: 164 | begin 165 | // Issue stop bit. 166 | if (baud_clk_tick && (q_baud_clk_tick_cnt == (STOP_OVERSAMPLE_TICKS - 1))) 167 | begin 168 | d_state = S_IDLE; 169 | d_tx_done_tick = 1'b1; 170 | end 171 | end 172 | endcase 173 | end 174 | 175 | assign tx = q_tx; 176 | assign tx_done_tick = q_tx_done_tick; 177 | 178 | endmodule 179 | 180 | -------------------------------------------------------------------------------- /riscv/src/cpu.v: -------------------------------------------------------------------------------- 1 | // RISCV32I CPU top module 2 | // port modification allowed for debugging purposes 3 | 4 | module cpu( 5 | input wire clk_in, // system clock signal 6 | input wire rst_in, // reset signal 7 | input wire rdy_in, // ready signal, pause cpu when low 8 | 9 | input wire [ 7:0] mem_din, // data input bus 10 | output wire [ 7:0] mem_dout, // data output bus 11 | output wire [31:0] mem_a, // address bus (only 17:0 is used) 12 | output wire mem_wr, // write/read signal (1 for write) 13 | 14 | input wire io_buffer_full, // 1 if uart buffer is full 15 | 16 | output wire [31:0] dbgreg_dout // cpu register output (debugging demo) 17 | ); 18 | 19 | // implementation goes here 20 | 21 | // Specifications: 22 | // - Pause cpu(freeze pc, registers, etc.) when rdy_in is low 23 | // - Memory read result will be returned in the next cycle. Write takes 1 cycle(no need to wait) 24 | // - Memory is of size 128KB, with valid address ranging from 0x0 to 0x20000 25 | // - I/O port is mapped to address higher than 0x30000 (mem_a[17:16]==2'b11) 26 | // - 0x30000 read: read a byte from input 27 | // - 0x30000 write: write a byte to output (write 0x00 is ignored) 28 | // - 0x30004 read: read clocks passed since cpu starts (in dword, 4 bytes) 29 | // - 0x30004 write: indicates program stop (will output '\0' through uart tx) 30 | 31 | always @(posedge clk_in) 32 | begin 33 | if (rst_in) 34 | begin 35 | 36 | end 37 | else if (!rdy_in) 38 | begin 39 | 40 | end 41 | else 42 | begin 43 | 44 | end 45 | end 46 | 47 | endmodule -------------------------------------------------------------------------------- /riscv/src/ram.v: -------------------------------------------------------------------------------- 1 | // implements 128KB of on-board RAM 2 | 3 | module ram 4 | #( 5 | parameter ADDR_WIDTH = 17 6 | ) 7 | ( 8 | input wire clk_in, // system clock 9 | input wire en_in, // chip enable 10 | input wire r_nw_in, // read/write select (read: 1, write: 0) 11 | input wire [ADDR_WIDTH-1:0] a_in, // memory address 12 | input wire [ 7:0] d_in, // data input 13 | output wire [ 7:0] d_out // data output 14 | ); 15 | 16 | wire ram_bram_we; 17 | wire [7:0] ram_bram_dout; 18 | 19 | single_port_ram_sync #(.ADDR_WIDTH(ADDR_WIDTH), 20 | .DATA_WIDTH(8)) ram_bram( 21 | .clk(clk_in), 22 | .we(ram_bram_we), 23 | .addr_a(a_in), 24 | .din_a(d_in), 25 | .dout_a(ram_bram_dout) 26 | ); 27 | 28 | assign ram_bram_we = (en_in) ? ~r_nw_in : 1'b0; 29 | assign d_out = (en_in) ? ram_bram_dout : 8'h00; 30 | 31 | endmodule -------------------------------------------------------------------------------- /riscv/src/riscv_top.v: -------------------------------------------------------------------------------- 1 | // riscv top module file 2 | // modification allowed for debugging purposes 3 | 4 | module riscv_top 5 | #( 6 | parameter SIM = 0 // whether in simulation 7 | ) 8 | ( 9 | input wire EXCLK, 10 | input wire btnC, 11 | output wire Tx, 12 | input wire Rx, 13 | output wire led 14 | ); 15 | 16 | localparam SYS_CLK_FREQ = 100000000; 17 | localparam UART_BAUD_RATE = 115200; 18 | localparam RAM_ADDR_WIDTH = 17; // 128KiB ram, should not be modified 19 | 20 | reg rst; 21 | reg rst_delay; 22 | 23 | wire clk; 24 | 25 | // assign EXCLK (or your own clock module) to clk 26 | assign clk = EXCLK; 27 | 28 | always @(posedge clk or posedge btnC) 29 | begin 30 | if (btnC) 31 | begin 32 | rst <= 1'b1; 33 | rst_delay <= 1'b1; 34 | end 35 | else 36 | begin 37 | rst_delay <= 1'b0; 38 | rst <= rst_delay; 39 | end 40 | end 41 | 42 | // 43 | // System Memory Buses 44 | // 45 | wire [ 7:0] cpumc_din; 46 | wire [31:0] cpumc_a; 47 | wire cpumc_wr; 48 | 49 | // 50 | // RAM: internal ram 51 | // 52 | wire ram_en; 53 | wire [RAM_ADDR_WIDTH-1:0] ram_a; 54 | wire [ 7:0] ram_dout; 55 | 56 | ram #(.ADDR_WIDTH(RAM_ADDR_WIDTH))ram0( 57 | .clk_in(clk), 58 | .en_in(ram_en), 59 | .r_nw_in(~cpumc_wr), 60 | .a_in(ram_a), 61 | .d_in(cpumc_din), 62 | .d_out(ram_dout) 63 | ); 64 | 65 | assign ram_en = (cpumc_a[RAM_ADDR_WIDTH:RAM_ADDR_WIDTH-1] == 2'b11) ? 1'b0 : 1'b1; 66 | assign ram_a = cpumc_a[RAM_ADDR_WIDTH-1:0]; 67 | 68 | // 69 | // CPU: CPU that implements RISC-V 32b integer base user-level real-mode ISA 70 | // 71 | wire [31:0] cpu_ram_a; 72 | wire cpu_ram_wr; 73 | wire [ 7:0] cpu_ram_din; 74 | wire [ 7:0] cpu_ram_dout; 75 | wire cpu_rdy; 76 | 77 | wire [31:0] cpu_dbgreg_dout; 78 | 79 | 80 | // 81 | // HCI: host communication interface block. Use controller to interact. 82 | // 83 | wire hci_active_out; 84 | wire [ 7:0] hci_ram_din; 85 | wire [ 7:0] hci_ram_dout; 86 | wire [RAM_ADDR_WIDTH-1:0] hci_ram_a; 87 | wire hci_ram_wr; 88 | 89 | wire hci_io_en; 90 | wire [ 2:0] hci_io_sel; 91 | wire [ 7:0] hci_io_din; 92 | wire [ 7:0] hci_io_dout; 93 | wire hci_io_wr; 94 | wire hci_io_full; 95 | 96 | wire program_finish; 97 | 98 | reg q_hci_io_en; 99 | 100 | cpu cpu0( 101 | .clk_in(clk), 102 | .rst_in(rst | program_finish), 103 | .rdy_in(cpu_rdy), 104 | 105 | .mem_din(cpu_ram_din), 106 | .mem_dout(cpu_ram_dout), 107 | .mem_a(cpu_ram_a), 108 | .mem_wr(cpu_ram_wr), 109 | 110 | .io_buffer_full(hci_io_full), 111 | 112 | .dbgreg_dout(cpu_dbgreg_dout) 113 | ); 114 | 115 | hci #(.SYS_CLK_FREQ(SYS_CLK_FREQ), 116 | .RAM_ADDR_WIDTH(RAM_ADDR_WIDTH), 117 | .BAUD_RATE(UART_BAUD_RATE)) hci0 118 | ( 119 | .clk(clk), 120 | .rst(rst), 121 | .tx(Tx), 122 | .rx(Rx), 123 | .active(hci_active_out), 124 | .ram_din(hci_ram_din), 125 | .ram_dout(hci_ram_dout), 126 | .ram_a(hci_ram_a), 127 | .ram_wr(hci_ram_wr), 128 | .io_sel(hci_io_sel), 129 | .io_en(hci_io_en), 130 | .io_din(hci_io_din), 131 | .io_dout(hci_io_dout), 132 | .io_wr(hci_io_wr), 133 | .io_full(hci_io_full), 134 | 135 | .program_finish(program_finish), 136 | 137 | .cpu_dbgreg_din(cpu_dbgreg_dout) // demo 138 | ); 139 | 140 | assign hci_io_sel = cpumc_a[2:0]; 141 | assign hci_io_en = (cpumc_a[RAM_ADDR_WIDTH:RAM_ADDR_WIDTH-1] == 2'b11) ? 1'b1 : 1'b0; 142 | assign hci_io_wr = cpumc_wr; 143 | assign hci_io_din = cpumc_din; 144 | 145 | // hci is always disabled in simulation 146 | wire hci_active; 147 | assign hci_active = hci_active_out & ~SIM; 148 | 149 | // indicates debug break 150 | assign led = hci_active; 151 | 152 | // pause cpu on hci active 153 | assign cpu_rdy = (hci_active) ? 1'b0 : 1'b1; 154 | 155 | // Mux cpumc signals from cpu or hci blk, depending on debug break state (hci_active). 156 | assign cpumc_a = (hci_active) ? hci_ram_a : cpu_ram_a; 157 | assign cpumc_wr = (hci_active) ? hci_ram_wr : cpu_ram_wr; 158 | assign cpumc_din = (hci_active) ? hci_ram_dout : cpu_ram_dout; 159 | 160 | // Fixed 2020-10-06: Inconsisitency of return value with I/O state 161 | always @ (posedge clk) begin 162 | q_hci_io_en <= hci_io_en; 163 | end 164 | 165 | assign cpu_ram_din = (q_hci_io_en) ? hci_io_dout : ram_dout; 166 | 167 | assign hci_ram_din = ram_dout; 168 | 169 | endmodule -------------------------------------------------------------------------------- /riscv/sys/io.h: -------------------------------------------------------------------------------- 1 | #ifndef CPU_JUDGE_TEST_IO_H 2 | #define CPU_JUDGE_TEST_IO_H 3 | 4 | // #define SIM // whether in simulation 5 | 6 | #define BYTE_PORT_IN 0x30000 // port for reading bytes from input 7 | #define BYTE_PORT_OUT 0x30000 // port for writing bytes to output 8 | 9 | #define CPUCLK_PORT_IN 0x30004 // port that reads clocks passed since cpu starts 10 | 11 | #define CPU_CLK_FREQ 70000000 // clock frequency of the cpu on FPGA 12 | 13 | static inline unsigned char inb() 14 | { 15 | return *((volatile unsigned char *)BYTE_PORT_IN); 16 | } 17 | 18 | static inline void outb(const unsigned char data) 19 | { 20 | *((volatile unsigned char *)BYTE_PORT_OUT) = data; 21 | } 22 | 23 | static inline unsigned long inl() 24 | { 25 | unsigned long ret = 0; 26 | unsigned char ch; 27 | int sign=0; 28 | while ((ch=inb())) if(ch!='\n'&&ch!=' '&&ch!='\t') break; 29 | do { 30 | if(ch=='-'&&!sign) sign=1; 31 | else if(ch<'0'||ch>'9') break; 32 | ret = ret * 10 + ch - '0'; 33 | }while ((ch=inb())); 34 | return sign?-ret:ret; 35 | } 36 | 37 | static inline void getstr(char* data) 38 | { 39 | char c; 40 | int i=0; 41 | while((c=inb())!='\n') data[i++]=c; 42 | data[i]='\0'; 43 | } 44 | 45 | static inline unsigned int ord(char data) 46 | { 47 | return (unsigned int)data; 48 | } 49 | 50 | static inline void outl(const int data) 51 | { 52 | unsigned char str[12]; 53 | int tmp = data; 54 | int i=0, s=0; 55 | if (tmp<0){ 56 | s=1; 57 | tmp=-tmp; 58 | } 59 | do { 60 | str[i++] = tmp % 10 + '0'; 61 | } 62 | while ((tmp/=10)>0); 63 | if(s) str[i++]='-'; 64 | while (i--) { 65 | outb(str[i]); 66 | } 67 | } 68 | 69 | static inline void print(const char *str) 70 | { 71 | for (; *str; str++) 72 | outb(*str); 73 | } 74 | 75 | static inline void println(const char *str) 76 | { 77 | print(str); 78 | outb('\n'); 79 | } 80 | 81 | static inline void outlln(const unsigned int data) 82 | { 83 | outl(data); 84 | outb('\n'); 85 | } 86 | 87 | static inline unsigned int clock() 88 | { 89 | // return *((volatile unsigned int*)CPUCLK_PORT_IN); 90 | unsigned t1 = (unsigned)(*((volatile unsigned char *)(CPUCLK_PORT_IN))); 91 | unsigned t2 = (unsigned)(*((volatile unsigned char *)(CPUCLK_PORT_IN+1))); 92 | unsigned t3 = (unsigned)(*((volatile unsigned char *)(CPUCLK_PORT_IN+2))); 93 | unsigned t4 = (unsigned)(*((volatile unsigned char *)(CPUCLK_PORT_IN+3))); 94 | return (t4<<24) | (t3<<16) | (t2<<8) | (t1); 95 | } 96 | 97 | #ifdef SIM 98 | #define sleep(x) 99 | #else 100 | static inline void sleep(const unsigned int milli_sec) 101 | { 102 | /* bug fix: clock may increase when we load from CPUCLK_PORT_IN */ 103 | /* which will introduce unsigned value overflow. */ 104 | /* unsigned int s = 0, d = milli_sec * (CPU_CLK_FREQ / 1000); */ 105 | int s = 0, d = milli_sec * (CPU_CLK_FREQ / 1000); 106 | s = clock(); 107 | while (clock() - s < d); 108 | } 109 | #endif 110 | 111 | #endif -------------------------------------------------------------------------------- /riscv/sys/memory.ld: -------------------------------------------------------------------------------- 1 | SECTIONS 2 | { 3 | . = 0x00000000; 4 | .rom : 5 | { 6 | *(.rom) 7 | } 8 | 9 | . = 0x00001000; 10 | .text : 11 | { 12 | *(.text) 13 | } 14 | 15 | .rodata ALIGN(4) : 16 | { 17 | *(.rodata) 18 | } 19 | 20 | .data ALIGN(4) : 21 | { 22 | *(.data) 23 | } 24 | 25 | __bss_start = .; 26 | 27 | .bss ALIGN(4) : 28 | { 29 | *(.bss) 30 | } 31 | 32 | __bss_end = .; 33 | __heap_start = (__bss_end + 0xfff) & 0xfffff000; 34 | } 35 | -------------------------------------------------------------------------------- /riscv/sys/rom.s: -------------------------------------------------------------------------------- 1 | .section .rom,"ax" 2 | .globl main 3 | 4 | li sp, 0x00020000 5 | jal main 6 | li a0, 0xff 7 | .L0: 8 | lui a3, 0x30 9 | sb a0, 4(a3) 10 | j .L0 11 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test1.ans: -------------------------------------------------------------------------------- 1 | 0000 2 | 1234 -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test1.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //input: 1 2 3 4 3 | 4 | int a[4]; 5 | int main() 6 | { 7 | int b[4]; 8 | int i; 9 | for (i = 0; i < 4; i++) 10 | { 11 | a[i] = 0; 12 | b[i] = inl(); 13 | } 14 | for (i = 0; i < 4; i++) 15 | { 16 | outl(a[i]); 17 | } 18 | println(""); 19 | int *p; 20 | p=b; 21 | for (i = 0; i < 4; i++) 22 | { 23 | outl(p[i]); 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test1.in: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test2.ans: -------------------------------------------------------------------------------- 1 | 4 2 | 1234 3 | 0000 -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test2.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // input: 1 2 3 4 3 | int a[4]; 4 | int *pa = a; 5 | int main() 6 | { 7 | int *pb[4]; 8 | int i; 9 | pb[0] = pa; 10 | pb[1] = pa; 11 | pb[2] = pa; 12 | pb[3] = pa; 13 | outlln(4); 14 | for (i = 0; i < 4; i++) 15 | pb[0][i] = inl(); 16 | for (i = 0; i < 4; i++) 17 | outl(pb[1][i]); 18 | println(""); 19 | for (i = 0; i < 4; i++) 20 | pb[2][i] = 0; 21 | for (i = 0; i < 4; i++) 22 | outl(pb[3][i]); 23 | } 24 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/array_test2.in: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 3 4 | 4 5 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/basicopt1.ans: -------------------------------------------------------------------------------- 1 | 99850 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/basicopt1.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int main() 3 | { 4 | int a[100][100]; 5 | int i; 6 | int j; 7 | int sum = 0; 8 | 9 | for (i = 0;i < 100;i++) 10 | for (j = 0;j < 100;j++) 11 | a[i][j] = 0; 12 | int quotient; 13 | int remainder; 14 | for (i = 0;i < 100;i++) 15 | if (i > 20 && i < 80) { 16 | for (j = 0;j < 100;j++) 17 | if (j > 5 || i < 90) { 18 | quotient = j * 4 / 100; 19 | remainder = j * 4 % 100; 20 | a[i + quotient][remainder] = j + (100 - 1 + 1 - 1 + 1) / 2; 21 | } 22 | } 23 | 24 | for (i = 0;i < 100;i++) 25 | for (j = 0;j < 100;j++) 26 | sum = sum + a[i][j]; 27 | outlln(sum); 28 | } 29 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/bulgarian.ans: -------------------------------------------------------------------------------- 1 | Let's start! 2 | 5 3 | 5 5 1 6 193 4 | step 1: 5 | 4 4 5 192 5 6 | step 2: 7 | 3 3 4 191 4 5 8 | step 3: 9 | 2 2 3 190 3 4 6 10 | step 4: 11 | 1 1 2 189 2 3 5 7 12 | step 5: 13 | 1 188 1 2 4 6 8 14 | step 6: 15 | 187 1 3 5 7 7 16 | step 7: 17 | 186 2 4 6 6 6 18 | step 8: 19 | 185 1 3 5 5 5 6 20 | step 9: 21 | 184 2 4 4 4 5 7 22 | step 10: 23 | 183 1 3 3 3 4 6 7 24 | step 11: 25 | 182 2 2 2 3 5 6 8 26 | step 12: 27 | 181 1 1 1 2 4 5 7 8 28 | step 13: 29 | 180 1 3 4 6 7 9 30 | step 14: 31 | 179 2 3 5 6 8 7 32 | step 15: 33 | 178 1 2 4 5 7 6 7 34 | step 16: 35 | 177 1 3 4 6 5 6 8 36 | step 17: 37 | 176 2 3 5 4 5 7 8 38 | step 18: 39 | 175 1 2 4 3 4 6 7 8 40 | step 19: 41 | 174 1 3 2 3 5 6 7 9 42 | step 20: 43 | 173 2 1 2 4 5 6 8 9 44 | step 21: 45 | 172 1 1 3 4 5 7 8 9 46 | step 22: 47 | 171 2 3 4 6 7 8 9 48 | step 23: 49 | 170 1 2 3 5 6 7 8 8 50 | step 24: 51 | 169 1 2 4 5 6 7 7 9 52 | step 25: 53 | 168 1 3 4 5 6 6 8 9 54 | step 26: 55 | 167 2 3 4 5 5 7 8 9 56 | step 27: 57 | 166 1 2 3 4 4 6 7 8 9 58 | step 28: 59 | 165 1 2 3 3 5 6 7 8 10 60 | step 29: 61 | 164 1 2 2 4 5 6 7 9 10 62 | step 30: 63 | 163 1 1 3 4 5 6 8 9 10 64 | step 31: 65 | 162 2 3 4 5 7 8 9 10 66 | step 32: 67 | 161 1 2 3 4 6 7 8 9 9 68 | step 33: 69 | 160 1 2 3 5 6 7 8 8 10 70 | step 34: 71 | 159 1 2 4 5 6 7 7 9 10 72 | step 35: 73 | 158 1 3 4 5 6 6 8 9 10 74 | step 36: 75 | 157 2 3 4 5 5 7 8 9 10 76 | step 37: 77 | 156 1 2 3 4 4 6 7 8 9 10 78 | step 38: 79 | 155 1 2 3 3 5 6 7 8 9 11 80 | step 39: 81 | 154 1 2 2 4 5 6 7 8 10 11 82 | step 40: 83 | 153 1 1 3 4 5 6 7 9 10 11 84 | step 41: 85 | 152 2 3 4 5 6 8 9 10 11 86 | step 42: 87 | 151 1 2 3 4 5 7 8 9 10 10 88 | step 43: 89 | 150 1 2 3 4 6 7 8 9 9 11 90 | step 44: 91 | 149 1 2 3 5 6 7 8 8 10 11 92 | step 45: 93 | 148 1 2 4 5 6 7 7 9 10 11 94 | step 46: 95 | 147 1 3 4 5 6 6 8 9 10 11 96 | step 47: 97 | 146 2 3 4 5 5 7 8 9 10 11 98 | step 48: 99 | 145 1 2 3 4 4 6 7 8 9 10 11 100 | step 49: 101 | 144 1 2 3 3 5 6 7 8 9 10 12 102 | step 50: 103 | 143 1 2 2 4 5 6 7 8 9 11 12 104 | step 51: 105 | 142 1 1 3 4 5 6 7 8 10 11 12 106 | step 52: 107 | 141 2 3 4 5 6 7 9 10 11 12 108 | step 53: 109 | 140 1 2 3 4 5 6 8 9 10 11 11 110 | step 54: 111 | 139 1 2 3 4 5 7 8 9 10 10 12 112 | step 55: 113 | 138 1 2 3 4 6 7 8 9 9 11 12 114 | step 56: 115 | 137 1 2 3 5 6 7 8 8 10 11 12 116 | step 57: 117 | 136 1 2 4 5 6 7 7 9 10 11 12 118 | step 58: 119 | 135 1 3 4 5 6 6 8 9 10 11 12 120 | step 59: 121 | 134 2 3 4 5 5 7 8 9 10 11 12 122 | step 60: 123 | 133 1 2 3 4 4 6 7 8 9 10 11 12 124 | step 61: 125 | 132 1 2 3 3 5 6 7 8 9 10 11 13 126 | step 62: 127 | 131 1 2 2 4 5 6 7 8 9 10 12 13 128 | step 63: 129 | 130 1 1 3 4 5 6 7 8 9 11 12 13 130 | step 64: 131 | 129 2 3 4 5 6 7 8 10 11 12 13 132 | step 65: 133 | 128 1 2 3 4 5 6 7 9 10 11 12 12 134 | step 66: 135 | 127 1 2 3 4 5 6 8 9 10 11 11 13 136 | step 67: 137 | 126 1 2 3 4 5 7 8 9 10 10 12 13 138 | step 68: 139 | 125 1 2 3 4 6 7 8 9 9 11 12 13 140 | step 69: 141 | 124 1 2 3 5 6 7 8 8 10 11 12 13 142 | step 70: 143 | 123 1 2 4 5 6 7 7 9 10 11 12 13 144 | step 71: 145 | 122 1 3 4 5 6 6 8 9 10 11 12 13 146 | step 72: 147 | 121 2 3 4 5 5 7 8 9 10 11 12 13 148 | step 73: 149 | 120 1 2 3 4 4 6 7 8 9 10 11 12 13 150 | step 74: 151 | 119 1 2 3 3 5 6 7 8 9 10 11 12 14 152 | step 75: 153 | 118 1 2 2 4 5 6 7 8 9 10 11 13 14 154 | step 76: 155 | 117 1 1 3 4 5 6 7 8 9 10 12 13 14 156 | step 77: 157 | 116 2 3 4 5 6 7 8 9 11 12 13 14 158 | step 78: 159 | 115 1 2 3 4 5 6 7 8 10 11 12 13 13 160 | step 79: 161 | 114 1 2 3 4 5 6 7 9 10 11 12 12 14 162 | step 80: 163 | 113 1 2 3 4 5 6 8 9 10 11 11 13 14 164 | step 81: 165 | 112 1 2 3 4 5 7 8 9 10 10 12 13 14 166 | step 82: 167 | 111 1 2 3 4 6 7 8 9 9 11 12 13 14 168 | step 83: 169 | 110 1 2 3 5 6 7 8 8 10 11 12 13 14 170 | step 84: 171 | 109 1 2 4 5 6 7 7 9 10 11 12 13 14 172 | step 85: 173 | 108 1 3 4 5 6 6 8 9 10 11 12 13 14 174 | step 86: 175 | 107 2 3 4 5 5 7 8 9 10 11 12 13 14 176 | step 87: 177 | 106 1 2 3 4 4 6 7 8 9 10 11 12 13 14 178 | step 88: 179 | 105 1 2 3 3 5 6 7 8 9 10 11 12 13 15 180 | step 89: 181 | 104 1 2 2 4 5 6 7 8 9 10 11 12 14 15 182 | step 90: 183 | 103 1 1 3 4 5 6 7 8 9 10 11 13 14 15 184 | step 91: 185 | 102 2 3 4 5 6 7 8 9 10 12 13 14 15 186 | step 92: 187 | 101 1 2 3 4 5 6 7 8 9 11 12 13 14 14 188 | step 93: 189 | 100 1 2 3 4 5 6 7 8 10 11 12 13 13 15 190 | step 94: 191 | 99 1 2 3 4 5 6 7 9 10 11 12 12 14 15 192 | step 95: 193 | 98 1 2 3 4 5 6 8 9 10 11 11 13 14 15 194 | step 96: 195 | 97 1 2 3 4 5 7 8 9 10 10 12 13 14 15 196 | step 97: 197 | 96 1 2 3 4 6 7 8 9 9 11 12 13 14 15 198 | step 98: 199 | 95 1 2 3 5 6 7 8 8 10 11 12 13 14 15 200 | step 99: 201 | 94 1 2 4 5 6 7 7 9 10 11 12 13 14 15 202 | step 100: 203 | 93 1 3 4 5 6 6 8 9 10 11 12 13 14 15 204 | step 101: 205 | 92 2 3 4 5 5 7 8 9 10 11 12 13 14 15 206 | step 102: 207 | 91 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 208 | step 103: 209 | 90 1 2 3 3 5 6 7 8 9 10 11 12 13 14 16 210 | step 104: 211 | 89 1 2 2 4 5 6 7 8 9 10 11 12 13 15 16 212 | step 105: 213 | 88 1 1 3 4 5 6 7 8 9 10 11 12 14 15 16 214 | step 106: 215 | 87 2 3 4 5 6 7 8 9 10 11 13 14 15 16 216 | step 107: 217 | 86 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 218 | step 108: 219 | 85 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 220 | step 109: 221 | 84 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 222 | step 110: 223 | 83 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 224 | step 111: 225 | 82 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 226 | step 112: 227 | 81 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 228 | step 113: 229 | 80 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 230 | step 114: 231 | 79 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 232 | step 115: 233 | 78 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 234 | step 116: 235 | 77 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 236 | step 117: 237 | 76 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 238 | step 118: 239 | 75 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 240 | step 119: 241 | 74 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 17 242 | step 120: 243 | 73 1 2 2 4 5 6 7 8 9 10 11 12 13 14 16 17 244 | step 121: 245 | 72 1 1 3 4 5 6 7 8 9 10 11 12 13 15 16 17 246 | step 122: 247 | 71 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 248 | step 123: 249 | 70 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 250 | step 124: 251 | 69 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 252 | step 125: 253 | 68 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 254 | step 126: 255 | 67 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 256 | step 127: 257 | 66 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 258 | step 128: 259 | 65 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 260 | step 129: 261 | 64 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 262 | step 130: 263 | 63 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 264 | step 131: 265 | 62 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 266 | step 132: 267 | 61 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 268 | step 133: 269 | 60 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 270 | step 134: 271 | 59 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 272 | step 135: 273 | 58 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 274 | step 136: 275 | 57 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 18 276 | step 137: 277 | 56 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 17 18 278 | step 138: 279 | 55 1 1 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 280 | step 139: 281 | 54 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 282 | step 140: 283 | 53 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 284 | step 141: 285 | 52 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 286 | step 142: 287 | 51 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 288 | step 143: 289 | 50 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 290 | step 144: 291 | 49 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 292 | step 145: 293 | 48 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 294 | step 146: 295 | 47 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 296 | step 147: 297 | 46 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 298 | step 148: 299 | 45 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 300 | step 149: 301 | 44 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 302 | step 150: 303 | 43 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 304 | step 151: 305 | 42 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 306 | step 152: 307 | 41 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 308 | step 153: 309 | 40 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 310 | step 154: 311 | 39 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 19 312 | step 155: 313 | 38 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 314 | step 156: 315 | 37 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 316 | step 157: 317 | 36 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 318 | step 158: 319 | 35 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 18 320 | step 159: 321 | 34 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 19 322 | step 160: 323 | 33 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 19 324 | step 161: 325 | 32 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 19 326 | step 162: 327 | 31 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 19 328 | step 163: 329 | 30 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 19 330 | step 164: 331 | 29 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 19 332 | step 165: 333 | 28 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 19 334 | step 166: 335 | 27 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 19 336 | step 167: 337 | 26 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 19 338 | step 168: 339 | 25 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 19 340 | step 169: 341 | 24 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 342 | step 170: 343 | 23 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 344 | step 171: 345 | 22 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 346 | step 172: 347 | 21 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 348 | step 173: 349 | 20 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 350 | step 174: 351 | 19 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 352 | step 175: 353 | 18 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 354 | step 176: 355 | 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 356 | step 177: 357 | 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 19 358 | step 178: 359 | 15 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 18 20 360 | step 179: 361 | 14 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 19 20 362 | step 180: 363 | 13 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 19 20 364 | step 181: 365 | 12 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 19 20 366 | step 182: 367 | 11 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 19 20 368 | step 183: 369 | 10 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 19 20 370 | step 184: 371 | 9 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 19 20 372 | step 185: 373 | 8 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 19 20 374 | step 186: 375 | 7 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 19 20 376 | step 187: 377 | 6 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 19 20 378 | step 188: 379 | 5 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 19 20 380 | step 189: 381 | 4 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 382 | step 190: 383 | 3 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 384 | step 191: 385 | 2 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 386 | step 192: 387 | 1 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 388 | step 193: 389 | 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 390 | step 194: 391 | 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 392 | step 195: 393 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 20 394 | step 196: 395 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 19 20 396 | step 197: 397 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 18 19 19 398 | step 198: 399 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 17 18 18 20 400 | step 199: 401 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 16 17 17 19 20 402 | step 200: 403 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 16 18 19 20 404 | step 201: 405 | 1 2 3 4 5 6 7 8 9 10 11 13 13 14 15 15 17 18 19 20 406 | step 202: 407 | 1 2 3 4 5 6 7 8 9 10 12 12 13 14 14 16 17 18 19 20 408 | step 203: 409 | 1 2 3 4 5 6 7 8 9 11 11 12 13 13 15 16 17 18 19 20 410 | step 204: 411 | 1 2 3 4 5 6 7 8 10 10 11 12 12 14 15 16 17 18 19 20 412 | step 205: 413 | 1 2 3 4 5 6 7 9 9 10 11 11 13 14 15 16 17 18 19 20 414 | step 206: 415 | 1 2 3 4 5 6 8 8 9 10 10 12 13 14 15 16 17 18 19 20 416 | step 207: 417 | 1 2 3 4 5 7 7 8 9 9 11 12 13 14 15 16 17 18 19 20 418 | step 208: 419 | 1 2 3 4 6 6 7 8 8 10 11 12 13 14 15 16 17 18 19 20 420 | step 209: 421 | 1 2 3 5 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 422 | step 210: 423 | 1 2 4 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 424 | step 211: 425 | 1 3 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 426 | step 212: 427 | 2 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 428 | step 213: 429 | 1 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 430 | step 214: 431 | 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 432 | step 215: 433 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 434 | step 216: 435 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 20 436 | step 217: 437 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 19 19 438 | step 218: 439 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 18 18 20 440 | step 219: 441 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 17 17 19 20 442 | step 220: 443 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 16 16 18 19 20 444 | step 221: 445 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 15 17 18 19 20 446 | step 222: 447 | 1 2 3 4 5 6 7 8 9 10 11 13 13 14 14 16 17 18 19 20 448 | step 223: 449 | 1 2 3 4 5 6 7 8 9 10 12 12 13 13 15 16 17 18 19 20 450 | step 224: 451 | 1 2 3 4 5 6 7 8 9 11 11 12 12 14 15 16 17 18 19 20 452 | step 225: 453 | 1 2 3 4 5 6 7 8 10 10 11 11 13 14 15 16 17 18 19 20 454 | step 226: 455 | 1 2 3 4 5 6 7 9 9 10 10 12 13 14 15 16 17 18 19 20 456 | step 227: 457 | 1 2 3 4 5 6 8 8 9 9 11 12 13 14 15 16 17 18 19 20 458 | step 228: 459 | 1 2 3 4 5 7 7 8 8 10 11 12 13 14 15 16 17 18 19 20 460 | step 229: 461 | 1 2 3 4 6 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 462 | step 230: 463 | 1 2 3 5 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 464 | step 231: 465 | 1 2 4 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 466 | step 232: 467 | 1 3 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 468 | step 233: 469 | 2 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 470 | step 234: 471 | 1 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 472 | step 235: 473 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 474 | step 236: 475 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 476 | step 237: 477 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 19 478 | step 238: 479 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 18 20 480 | step 239: 481 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 17 19 20 482 | step 240: 483 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 16 18 19 20 484 | step 241: 485 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 15 17 18 19 20 486 | step 242: 487 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 14 16 17 18 19 20 488 | step 243: 489 | 1 2 3 4 5 6 7 8 9 10 11 13 13 13 15 16 17 18 19 20 490 | step 244: 491 | 1 2 3 4 5 6 7 8 9 10 12 12 12 14 15 16 17 18 19 20 492 | step 245: 493 | 1 2 3 4 5 6 7 8 9 11 11 11 13 14 15 16 17 18 19 20 494 | step 246: 495 | 1 2 3 4 5 6 7 8 10 10 10 12 13 14 15 16 17 18 19 20 496 | step 247: 497 | 1 2 3 4 5 6 7 9 9 9 11 12 13 14 15 16 17 18 19 20 498 | step 248: 499 | 1 2 3 4 5 6 8 8 8 10 11 12 13 14 15 16 17 18 19 20 500 | step 249: 501 | 1 2 3 4 5 7 7 7 9 10 11 12 13 14 15 16 17 18 19 20 502 | step 250: 503 | 1 2 3 4 6 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 504 | step 251: 505 | 1 2 3 5 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 506 | step 252: 507 | 1 2 4 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 508 | step 253: 509 | 1 3 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 510 | step 254: 511 | 2 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 512 | step 255: 513 | 1 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 514 | step 256: 515 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 516 | step 257: 517 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 518 | Total: 257 step(s) 519 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/bulgarian.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // Target: Simulate a Bulgarian-solitaire game. 3 | // Possible opitimization: Dead code elimination, common expression, inline function, loop unrolling, etc. 4 | // REMARKS: A funny game. If you like, you can try to prove that when n=1+2+..+i(i>0), the game will always stop 5 | // and converge to the only solution: {1,2,...i}. :) 6 | 7 | int n; 8 | int h; 9 | int now; 10 | int a[100]; 11 | int A = 48271; 12 | int M = 2147483647; 13 | int Q; 14 | int R; 15 | int seed=1; 16 | int random() { 17 | int tempseed = A * (seed % Q) - R * (seed / Q); 18 | if (tempseed >= 0) 19 | seed = tempseed; 20 | else 21 | seed = tempseed + M; 22 | return seed; 23 | } 24 | void initialize(int val) { 25 | seed = val; 26 | } 27 | void swap(int x,int y) { 28 | int temp = a[x]; 29 | a[x] = a[y]; 30 | a[y] = temp; 31 | } 32 | int pd(int x) { 33 | for (;h <= x; ++h) 34 | if (x == h * (h + 1) / 2) 35 | return 1; 36 | return 0; 37 | } 38 | void show() { 39 | int i; 40 | for (i = 0; i < now; ++i){ 41 | outl(a[i]); 42 | print(" "); 43 | } 44 | println(""); 45 | } 46 | int win() 47 | { 48 | int i; 49 | int j; 50 | int b[100]; 51 | int temp; 52 | if (now != h) 53 | return 0; 54 | for (j = 0; j < now; ++j) 55 | b[j] = a[j]; 56 | for (i = 0;i < now - 1; ++i) 57 | for (j = i + 1;j < now; ++j) 58 | if (b[i] > b[j]) { 59 | temp = b[i]; 60 | b[i] = b[j]; 61 | b[j] = temp; 62 | } 63 | for (i = 0; i < now; ++i) 64 | if (b[i] != i + 1) 65 | return 0; 66 | return 1; 67 | } 68 | void merge() 69 | { 70 | int i; 71 | for (i = 0;i < now; ++i) 72 | if (a[i] == 0) { 73 | int j; 74 | for (j = i+1; j < now; ++j) 75 | if (a[j] != 0) { 76 | swap(i,j); 77 | break; 78 | } 79 | } 80 | for (i=0;i n) 115 | a[i] = random() % 10 + 1; 116 | temp = temp + a[i]; 117 | } 118 | a[now - 1] = n - temp; 119 | show(); 120 | merge(); 121 | while (!win()) { 122 | print("step "); 123 | outl(++count); 124 | println(":"); 125 | move(); 126 | merge(); 127 | show(); 128 | sleep(10); // to prevent UART buffer from overflowing 129 | } 130 | print("Total: "); 131 | outl(count); 132 | println(" step(s)"); 133 | return 0; 134 | } 135 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/expr.ans: -------------------------------------------------------------------------------- 1 | -66060719 -323398799 -743275679 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/expr.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //This file use massive recursive expression to test: Common Expression substitution. 3 | //For my optimized version: All: 1397 Load: 86 Store: 55 Jumped: 23 4 | //For my unoptimized version: All: 24519 Load: 12183 Store: 55 Jumped: 23 5 | //A better result is welcomed. ------ From JinTianxing. 6 | 7 | int A = 1; 8 | int B = 1; 9 | int C = 1; 10 | 11 | int main(){ 12 | while (C < (1 << 29) && C > -(1 << 29)){ 13 | A = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 14 | B = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 15 | C = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 16 | } 17 | outl(A); 18 | print(" "); 19 | outl(B); 20 | print(" "); 21 | outlln(C); 22 | return 0; 23 | } 24 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/gcd.ans: -------------------------------------------------------------------------------- 1 | 1 2 | 1029 3 | 171 4 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/gcd.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int gcd(int x, int y) { 3 | if (x%y == 0) return y; 4 | else return gcd(y, x%y); 5 | } 6 | 7 | int main() { 8 | outlln(gcd(10,1)); 9 | outlln(gcd(34986,3087)); 10 | outlln(gcd(2907,1539)); 11 | 12 | return 0; 13 | } -------------------------------------------------------------------------------- /riscv/testcase/fpga/hanoi.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int cd(int d, char* a, char* b, char* c, int sum) { 3 | sleep(5); // to prevent UART buffer from overflowing 4 | if (d == 1) { 5 | print("move "); 6 | print(a); 7 | print(" --> "); 8 | println(c); 9 | sum++; 10 | } else { 11 | sum = cd(d - 1, a, c, b, sum); 12 | print("move "); 13 | print(a); 14 | print(" --> "); 15 | println(c); 16 | sum = cd(d - 1, b, a, c, sum); 17 | sum++; 18 | } 19 | return sum; 20 | } 21 | 22 | int main() { 23 | char a[5] = "A"; 24 | char b[5] = "B"; 25 | char c[5] = "C"; 26 | int d = inl(); 27 | int sum = cd(d, a, b, c, 0); 28 | outlln(sum); 29 | return 0; 30 | } 31 | 32 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/hanoi.in: -------------------------------------------------------------------------------- 1 | 10 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/heart.ans: -------------------------------------------------------------------------------- 1 | _________________________________________________________________________________________________________________________ 2 | _________________________________________________________________________________________________________________________ 3 | _________________________________________________________________________________________________________________________ 4 | _________________________________________________________________________________________________________________________ 5 | _________________________________________________________________________________________________________________________ 6 | _________________________________________________________________________________________________________________________ 7 | _______________________________#***##*********++=_______________________#**************++-_______________________________ 8 | ___________________________#############**********+++-_____________############**********++++-___________________________ 9 | ________________________####################********++++=_______*###############*********++++++=-________________________ 10 | ______________________#######################*********+++++___##################**********++++++==-______________________ 11 | _____________________#######################*****************##################*********+++++++====-+____________________ 12 | ___________________########################*****************###############************+*+++++++===--:___________________ 13 | __________________########################*#****************#############**************+++++++++====--:__________________ 14 | _________________###########################***************#*#########****************++++++++++====---:_________________ 15 | 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___________________++++***************************+**+++***+++++++++++++++++==========--------:::::...___________________ 30 | ____________________+++++***************+*******+*++++++*++++++++++++++++=============------::::::...____________________ 31 | _____________________+++++**+*+**+*****+*+**++++*++++++++++++++++++++==+===========--------::::::....____________________ 32 | ______________________++++++++*++*+*++*++++**++++++++++++++++++++++=++===========--------::::::....______________________ 33 | _______________________=++++++++++++++*++++++++++++++++++++++++++++============-=-------::::::...._______________________ 34 | ________________________==++++++++++++++++++++++++++++++++++++++++============---------:::::.....________________________ 35 | _________________________==++++++++++++++++++++++++++++++++++++=============--------:::::::....._________________________ 36 | ___________________________===++++++++++++++++++++++++++++++++=============--------::::::.....___________________________ 37 | ____________________________====++++++++++++++++++++++++++++=+=========----------::::::......____________________________ 38 | ______________________________======++++++++++++++++++++++==+=========----------:::::......______________________________ 39 | ________________________________======+=++++++++++++++++++=+=======----------:::::::.....________________________________ 40 | __________________________________========+++=++++++=+++++========---------:::::::.....__________________________________ 41 | ____________________________________=================+=+========--------:::::::......____________________________________ 42 | ______________________________________-========================-------:::::::......______________________________________ 43 | ________________________________________--====================-----:::::::.......________________________________________ 44 | ___________________________________________--===============-----:::::::......___________________________________________ 45 | _____________________________________________----===========----:::::......._____________________________________________ 46 | ________________________________________________----=======----::::......________________________________________________ 47 | ___________________________________________________-----==---:::......___________________________________________________ 48 | ______________________________________________________-------::....______________________________________________________ 49 | _________________________________________________________---:..._________________________________________________________ 50 | ___________________________________________________________-:.___________________________________________________________ 51 | _________________________________________________________________________________________________________________________ 52 | _________________________________________________________________________________________________________________________ 53 | _________________________________________________________________________________________________________________________ 54 | _________________________________________________________________________________________________________________________ 55 | _________________________________________________________________________________________________________________________ 56 | _________________________________________________________________________________________________________________________ 57 | _________________________________________________________________________________________________________________________ 58 | _________________________________________________________________________________________________________________________ 59 | _________________________________________________________________________________________________________________________ 60 | _________________________________________________________________________________________________________________________ 61 | _________________________________________________________________________________________________________________________ 62 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/heart.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | #define putchar outb 3 | float f(float x, float y, float z) { 4 | float a = x * x + 9.0f / 4.0f * y * y + z * z - 1; 5 | return a * a * a - x * x * z * z * z - 9.0f / 80.0f * y * y * z * z * z; 6 | } 7 | 8 | float h(float x, float z) { 9 | for (float y = 1.0f; y >= 0.0f; y -= 0.001f) 10 | if (f(x, y, z) <= 0.0f) 11 | return y; 12 | return 0.0f; 13 | } 14 | 15 | float mysqrt(float x) { 16 | if (x == 0) return 0; 17 | int i; 18 | double v = x / 2; 19 | for (i = 0; i < 50; ++i) 20 | v = (v + x / v)/2; 21 | 22 | return v; 23 | } 24 | 25 | int main() { 26 | for (float z = 1.5f; z > -1.5f; z -= 0.05f) { 27 | for (float x = -1.5f; x < 1.5f; x += 0.025f) { 28 | float v = f(x, 0.0f, z); 29 | if (v <= 0.0f) { 30 | float y0 = h(x, z); 31 | float ny = 0.01f; 32 | float nx = h(x + ny, z) - y0; 33 | float nz = h(x, z + ny) - y0; 34 | float nd = 1.0f / mysqrt(nx * nx + ny * ny + nz * nz); 35 | float d = (nx + ny - nz) * nd * 0.5f + 0.5f; 36 | int index = (int)(d * 5.0f); 37 | putchar(".:-=+*#%@"[index]); 38 | } 39 | else 40 | putchar('_'); 41 | } 42 | putchar('\n'); 43 | } 44 | } -------------------------------------------------------------------------------- /riscv/testcase/fpga/looper.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // san check: if your predictor && icache work, it should be 1.5s @ 100Mhz 3 | unsigned n, sum; 4 | void work() { 5 | for (int i = 1; i <= 5 * n; i++) { 6 | sum += i * 998244353; 7 | } 8 | } 9 | int main() { 10 | n = 50; 11 | work(); 12 | n = 10000000; 13 | work(); 14 | outlln(sum); 15 | } -------------------------------------------------------------------------------- /riscv/testcase/fpga/lvalue2.ans: -------------------------------------------------------------------------------- 1 | 2 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/lvalue2.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a[4]; 3 | int main() 4 | { 5 | int b[4]; 6 | b[2]=2; 7 | int *p; 8 | p=b; 9 | outlln(p[2]); 10 | } 11 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/magic.ans: -------------------------------------------------------------------------------- 1 | 2 7 6 2 | 9 5 1 3 | 4 3 8 4 | 5 | 2 9 4 6 | 7 5 3 7 | 6 1 8 8 | 9 | 4 3 8 10 | 9 5 1 11 | 2 7 6 12 | 13 | 4 9 2 14 | 3 5 7 15 | 8 1 6 16 | 17 | 6 1 8 18 | 7 5 3 19 | 2 9 4 20 | 21 | 6 7 2 22 | 1 5 9 23 | 8 3 4 24 | 25 | 8 1 6 26 | 3 5 7 27 | 4 9 2 28 | 29 | 8 3 4 30 | 1 5 9 31 | 6 7 2 32 | 33 | 8 34 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/magic.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int make[3][3]; 3 | int color[10]; 4 | int count[1]; 5 | int i; 6 | int j; 7 | 8 | void origin(int N) 9 | { 10 | for (i = 0; i < N; i ++ ) { 11 | for (j = 0; j < N; j ++ ) 12 | make[i][j] = 0; 13 | } 14 | } 15 | 16 | void search(int x, int y, int z) 17 | { 18 | int s; 19 | int i; 20 | int j; 21 | if ((y > 0 || y < 0) || x == 0 || make[x-1][0] + make[x-1][1] + make[x-1][2] == 15) 22 | { 23 | if (x == 2 && y == 2) { 24 | make[2][2] = 45 - z; 25 | s = make[0][0] + make[0][1] + make[0][2]; 26 | if (make[1][0] + make[1][1] + make[1][2] == s && 27 | make[2][0] + make[2][1] + make[2][2] == s && 28 | make[0][0] + make[1][0] + make[2][0] == s && 29 | make[0][1] + make[1][1] + make[2][1] == s && 30 | make[0][2] + make[1][2] + make[2][2] == s && 31 | make[0][0] + make[1][1] + make[2][2] == s && 32 | make[2][0] + make[1][1] + make[0][2] == s) 33 | { 34 | count[0] = count[0] + 1; 35 | for (i = 0;i <= 2;i ++) 36 | { 37 | for (j = 0;j <= 2;j ++) 38 | { 39 | outl(make[i][j]); 40 | print(" "); 41 | } 42 | print("\n"); 43 | } 44 | print("\n"); 45 | } 46 | } 47 | else { 48 | if (y == 2) { 49 | make[x][y] = 15 - make[x][0] - make[x][1]; 50 | if (make[x][y] > 0 && make[x][y] < 10 && color[make[x][y]] == 0) { 51 | color[make[x][y]] = 1; 52 | if (y == 2) 53 | search(x + 1, 0, z+make[x][y]); 54 | else 55 | search(x, y+1, z+make[x][y]); 56 | color[make[x][y]] = 0; 57 | } 58 | } 59 | else { 60 | for (i = 1;i <= 9;i ++) { 61 | if (color[i] == 0) { 62 | color[i] = 1; 63 | make[x][y] = i; 64 | if (y == 2) 65 | search(x + 1, 0, z+i); 66 | else 67 | search(x, y+1, z+i); 68 | make[x][y] = 0; 69 | color[i] = 0; 70 | } 71 | } 72 | } 73 | } 74 | } 75 | } 76 | int main() 77 | { 78 | origin(3); 79 | search(0, 0, 0); 80 | outlln(count[0]); 81 | return 0; 82 | } 83 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/manyarguments.ans: -------------------------------------------------------------------------------- 1 | 120 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/manyarguments.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a(int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8, int a9, int a10, int a11, int a12, int a13, int a14, int a15) 3 | { 4 | return a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15; 5 | } 6 | 7 | int main() 8 | { 9 | outlln(a(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)); 10 | return 0; 11 | } 12 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/multiarray.ans: -------------------------------------------------------------------------------- 1 | 888 2 | 0 3 | 1 4 | 2 5 | 3 6 | 4 7 | 5 8 | 6 9 | 7 10 | 8 11 | 9 12 | 10 13 | 11 14 | 12 15 | 13 16 | 14 17 | 15 18 | 16 19 | 17 20 | 18 21 | 19 22 | 20 23 | 21 24 | 22 25 | 23 26 | 24 27 | 25 28 | 26 29 | 27 30 | 28 31 | 29 32 | 30 33 | 31 34 | 32 35 | 33 36 | 34 37 | 35 38 | 36 39 | 37 40 | 38 41 | 39 42 | 0 43 | -10 44 | -1 45 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/multiarray.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a[4][11]; 3 | int i; 4 | int j; 5 | 6 | struct rec { 7 | int num; 8 | int c; 9 | }b[5]; 10 | 11 | void printNum(int num) { 12 | outlln(num); 13 | } 14 | int main() { 15 | 16 | 17 | for (i = 0; i < 4; i ++) { 18 | for (j = 0; j < 10; j ++) 19 | a[i][j] = 888; 20 | } 21 | for (i = 0; i < 5; i ++) { 22 | b[i].num = -1; 23 | } 24 | 25 | printNum(a[3][9]); 26 | for (i = 0; i <= 3; i ++) 27 | for (j = 0; j <= 9; j ++) 28 | a[i][j] = i * 10 + j; 29 | 30 | for (i = 0; i <= 3; i ++) 31 | for (j = 0; j <= 9; j ++) 32 | printNum(a[i][j]); 33 | a[2][10]=0; 34 | printNum(a[2][10]); 35 | b[0].num = -2; 36 | b[a[2][10]].num = -10; 37 | printNum(b[0].num); 38 | printNum(b[1].num); 39 | return 0; 40 | } 41 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/pi.ans: -------------------------------------------------------------------------------- 1 | 3141592653589793238462643383279528841971693993751058209749445923078164062862089986280348253421170679821480865132823664709384469555822317253594081284811174502841270193852115559644622948954930381964428810975665933446128475648233786783165271201991456485669234634861045432664821339360726024914127372458706606315588174881520920962829254917153643678925903611330530548820466521384146951941511609433057273657595919530921861173819326117931051185480744623799627495673518857527248912279381830119491298336733624406566438602139494639522473719070217986943702770539217176293176752384674818467669451320005681271452635608277857713427577896091736371787214684409012249534301465495853710579227968925892354201995611212902196864344181598136297747713099605187072113499999983729780499510597317328160963185 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/pi.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int f[2801]; 3 | int main() { 4 | int a = 10000; 5 | int b = 0; 6 | int c = 2800; 7 | int d = 0; 8 | int e = 0; 9 | int g = 0; 10 | 11 | for (;b-c!=0;) 12 | f[b++] = a/5; 13 | for (;; e = d%a){ 14 | d = 0; 15 | g = c*2; 16 | if (g==0) break; 17 | 18 | for (b=c;;d=d*b){ 19 | d=d+f[b]*a; 20 | f[b] = d%--g; 21 | d=d/g--; 22 | if (--b==0) break; 23 | } 24 | 25 | c = c-14; 26 | outl(e+d/a); // should be printf("%04b"), but let it be 27 | } 28 | 29 | print("\n"); 30 | return 0; 31 | } 32 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/qsort.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // Target: qsort 3 | // Possible optimization: Dead code elimination, common expression, strength reduction 4 | // REMARKS: nothing. 5 | // 6 | // 7 | 8 | //int a[10100]; 9 | int a[10100]; 10 | int n = 10000; 11 | 12 | int qsrt(int l, int r) { 13 | int i = l; 14 | int j = r; 15 | int x = a[(l + r) / 2]; 16 | while (i <= j) { 17 | while (a[i] < x) i++; 18 | while (a[j] > x) j--; 19 | if (i <= j) { 20 | int temp = a[i]; 21 | a[i] = a[j]; 22 | a[j] = temp; 23 | i++; 24 | j--; 25 | } 26 | } 27 | if (l < j) qsrt(l, j); 28 | if (i < r) qsrt(i, r); 29 | return 0; 30 | } 31 | 32 | int main() { 33 | int i; 34 | for (i = 1; i <= n; i++) 35 | a[i] = n + 1 - i; 36 | qsrt(1, n); 37 | for (i = 1; i <= n; i++) { 38 | outl(a[i]); 39 | print(" "); 40 | sleep(1); // to prevent UART buffer from overflowing 41 | } 42 | print("\n"); 43 | return 0; 44 | } 45 | 46 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/queens.ans: -------------------------------------------------------------------------------- 1 | O . . . . . . . 2 | . . . . O . . . 3 | . . . . . . . O 4 | . . . . . O . . 5 | . . O . . . . . 6 | . . . . . . O . 7 | . O . . . . . . 8 | . . . O . . . . 9 | 10 | O . . . . . . . 11 | . . . . . O . . 12 | . . . . . . . O 13 | . . O . . . . . 14 | . . . . . . O . 15 | . . . O . . . . 16 | . O . . . . . . 17 | . . . . O . . . 18 | 19 | O . . . . . . . 20 | . . . . . . O . 21 | . . . O . . . . 22 | . . . . . O . . 23 | . . . . . . . O 24 | . O . . . . . . 25 | . . . . O . . . 26 | . . O . . . . . 27 | 28 | O . . . . . . . 29 | . . . . . . O . 30 | . . . . O . . . 31 | . . . . . . . O 32 | . O . . . . . . 33 | . . . O . . . . 34 | . . . . . O . . 35 | . . O . . . . . 36 | 37 | . O . . . . . . 38 | . . . O . . . . 39 | . . . . . O . . 40 | . . . . . . . O 41 | . . O . . . . . 42 | O . . . . . . . 43 | . . . . . . O . 44 | . . . . O . . . 45 | 46 | . O . . . . . . 47 | . . . . O . . . 48 | . . . . . . O . 49 | O . . . . . . . 50 | . . O . . . . . 51 | . . . . . . . O 52 | . . . . . O . . 53 | . . . O . . . . 54 | 55 | . O . . . . . . 56 | . . . . O . . . 57 | . . . . . . O . 58 | . . . O . . . . 59 | O . . . . . . . 60 | . . . . . . . O 61 | . . . . . O . . 62 | . . O . . . . . 63 | 64 | . O . . . . . . 65 | . . . . . O . . 66 | O . . . . . . . 67 | . . . . . . O . 68 | . . . O . . . . 69 | . . . . . . . O 70 | . . O . . . . . 71 | . . . . O . . . 72 | 73 | . O . . . . . . 74 | . . . . . O . . 75 | . . . . . . . O 76 | . . O . . . . . 77 | O . . . . . . . 78 | . . . O . . . . 79 | . . . . . . O . 80 | . . . . O . . . 81 | 82 | . O . . . . . . 83 | . . . . . . O . 84 | . . O . . . . . 85 | . . . . . O . . 86 | . . . . . . . O 87 | . . . . O . . . 88 | O . . . . . . . 89 | . . . O . . . . 90 | 91 | . O . . . . . . 92 | . . . . . . O . 93 | . . . . O . . . 94 | . . . . . . . O 95 | O . . . . . . . 96 | . . . O . . . . 97 | . . . . . O . . 98 | . . O . . . . . 99 | 100 | . O . . . . . . 101 | . . . . . . . O 102 | . . . . . O . . 103 | O . . . . . . . 104 | . . O . . . . . 105 | . . . . O . . . 106 | . . . . . . O . 107 | . . . O . . . . 108 | 109 | . . O . . . . . 110 | O . . . . . . . 111 | . . . . . . O . 112 | . . . . O . . . 113 | . . . . . . . O 114 | . O . . . . . . 115 | . . . O . . . . 116 | . . . . . O . . 117 | 118 | . . O . . . . . 119 | . . . . O . . . 120 | . O . . . . . . 121 | . . . . . . . O 122 | O . . . . . . . 123 | . . . . . . O . 124 | . . . O . . . . 125 | . . . . . O . . 126 | 127 | . . O . . . . . 128 | . . . . O . . . 129 | . O . . . . . . 130 | . . . . . . . O 131 | . . . . . O . . 132 | . . . O . . . . 133 | . . . . . . O . 134 | O . . . . . . . 135 | 136 | . . O . . . . . 137 | . . . . O . . . 138 | . . . . . . O . 139 | O . . . . . . . 140 | . . . O . . . . 141 | . O . . . . . . 142 | . . . . . . . O 143 | . . . . . O . . 144 | 145 | . . O . . . . . 146 | . . . . O . . . 147 | . . . . . . . O 148 | . . . O . . . . 149 | O . . . . . . . 150 | . . . . . . O . 151 | . O . . . . . . 152 | . . . . . O . . 153 | 154 | . . O . . . . . 155 | . . . . . O . . 156 | . O . . . . . . 157 | . . . . O . . . 158 | . . . . . . . O 159 | O . . . . . . . 160 | . . . . . . O . 161 | . . . O . . . . 162 | 163 | . . O . . . . . 164 | . . . . . O . . 165 | . O . . . . . . 166 | . . . . . . O . 167 | O . . . . . . . 168 | . . . O . . . . 169 | . . . . . . . O 170 | . . . . O . . . 171 | 172 | . . O . . . . . 173 | . . . . . O . . 174 | . O . . . . . . 175 | . . . . . . O . 176 | . . . . O . . . 177 | O . . . . . . . 178 | . . . . . . . O 179 | . . . O . . . . 180 | 181 | . . O . . . . . 182 | . . . . . O . . 183 | . . . O . . . . 184 | O . . . . . . . 185 | . . . . . . . O 186 | . . . . O . . . 187 | . . . . . . O . 188 | . O . . . . . . 189 | 190 | . . O . . . . . 191 | . . . . . O . . 192 | . . . O . . . . 193 | . O . . . . . . 194 | . . . . . . . O 195 | . . . . O . . . 196 | . . . . . . O . 197 | O . . . . . . . 198 | 199 | . . O . . . . . 200 | . . . . . O . . 201 | . . . . . . . O 202 | O . . . . . . . 203 | . . . O . . . . 204 | . . . . . . O . 205 | . . . . O . . . 206 | . O . . . . . . 207 | 208 | . . O . . . . . 209 | . . . . . O . . 210 | . . . . . . . O 211 | O . . . . . . . 212 | . . . . O . . . 213 | . . . . . . O . 214 | . O . . . . . . 215 | . . . O . . . . 216 | 217 | . . O . . . . . 218 | . . . . . O . . 219 | . . . . . . . O 220 | . O . . . . . . 221 | . . . O . . . . 222 | O . . . . . . . 223 | . . . . . . O . 224 | . . . . O . . . 225 | 226 | . . O . . . . . 227 | . . . . . . O . 228 | . O . . . . . . 229 | . . . . . . . O 230 | . . . . O . . . 231 | O . . . . . . . 232 | . . . O . . . . 233 | . . . . . O . . 234 | 235 | . . O . . . . . 236 | . . . . . . O . 237 | . O . . . . . . 238 | . . . . . . . O 239 | . . . . . O . . 240 | . . . O . . . . 241 | O . . . . . . . 242 | . . . . O . . . 243 | 244 | . . O . . . . . 245 | . . . . . . . O 246 | . . . O . . . . 247 | . . . . . . O . 248 | O . . . . . . . 249 | . . . . . O . . 250 | . O . . . . . . 251 | . . . . O . . . 252 | 253 | . . . O . . . . 254 | O . . . . . . . 255 | . . . . O . . . 256 | . . . . . . . O 257 | . O . . . . . . 258 | . . . . . . O . 259 | . . O . . . . . 260 | . . . . . O . . 261 | 262 | . . . O . . . . 263 | O . . . . . . . 264 | . . . . O . . . 265 | . . . . . . . O 266 | . . . . . O . . 267 | . . O . . . . . 268 | . . . . . . O . 269 | . O . . . . . . 270 | 271 | . . . O . . . . 272 | . O . . . . . . 273 | . . . . O . . . 274 | . . . . . . . O 275 | . . . . . O . . 276 | O . . . . . . . 277 | . . O . . . . . 278 | . . . . . . O . 279 | 280 | . . . O . . . . 281 | . O . . . . . . 282 | . . . . . . O . 283 | . . O . . . . . 284 | . . . . . O . . 285 | . . . . . . . O 286 | O . . . . . . . 287 | . . . . O . . . 288 | 289 | . . . O . . . . 290 | . O . . . . . . 291 | . . . . . . O . 292 | . . O . . . . . 293 | . . . . . O . . 294 | . . . . . . . O 295 | . . . . O . . . 296 | O . . . . . . . 297 | 298 | . . . O . . . . 299 | . O . . . . . . 300 | . . . . . . O . 301 | . . . . O . . . 302 | O . . . . . . . 303 | . . . . . . . O 304 | . . . . . O . . 305 | . . O . . . . . 306 | 307 | . . . O . . . . 308 | . O . . . . . . 309 | . . . . . . . O 310 | . . . . O . . . 311 | . . . . . . O . 312 | O . . . . . . . 313 | . . O . . . . . 314 | . . . . . O . . 315 | 316 | . . . O . . . . 317 | . O . . . . . . 318 | . . . . . . . O 319 | . . . . . O . . 320 | O . . . . . . . 321 | . . O . . . . . 322 | . . . . O . . . 323 | . . . . . . O . 324 | 325 | . . . O . . . . 326 | . . . . . O . . 327 | O . . . . . . . 328 | . . . . O . . . 329 | . O . . . . . . 330 | . . . . . . . O 331 | . . O . . . . . 332 | . . . . . . O . 333 | 334 | . . . O . . . . 335 | . . . . . O . . 336 | . . . . . . . O 337 | . O . . . . . . 338 | . . . . . . O . 339 | O . . . . . . . 340 | . . O . . . . . 341 | . . . . O . . . 342 | 343 | . . . O . . . . 344 | . . . . . O . . 345 | . . . . . . . O 346 | . . O . . . . . 347 | O . . . . . . . 348 | . . . . . . O . 349 | . . . . O . . . 350 | . O . . . . . . 351 | 352 | . . . O . . . . 353 | . . . . . . O . 354 | O . . . . . . . 355 | . . . . . . . O 356 | . . . . O . . . 357 | . O . . . . . . 358 | . . . . . O . . 359 | . . O . . . . . 360 | 361 | . . . O . . . . 362 | . . . . . . O . 363 | . . O . . . . . 364 | . . . . . . . O 365 | . O . . . . . . 366 | . . . . O . . . 367 | O . . . . . . . 368 | . . . . . O . . 369 | 370 | . . . O . . . . 371 | . . . . . . O . 372 | . . . . O . . . 373 | . O . . . . . . 374 | . . . . . O . . 375 | O . . . . . . . 376 | . . O . . . . . 377 | . . . . . . . O 378 | 379 | . . . O . . . . 380 | . . . . . . O . 381 | . . . . O . . . 382 | . . O . . . . . 383 | O . . . . . . . 384 | . . . . . O . . 385 | . . . . . . . O 386 | . O . . . . . . 387 | 388 | . . . O . . . . 389 | . . . . . . . O 390 | O . . . . . . . 391 | . . O . . . . . 392 | . . . . . O . . 393 | . O . . . . . . 394 | . . . . . . O . 395 | . . . . O . . . 396 | 397 | . . . O . . . . 398 | . . . . . . . O 399 | O . . . . . . . 400 | . . . . O . . . 401 | . . . . . . O . 402 | . O . . . . . . 403 | . . . . . O . . 404 | . . O . . . . . 405 | 406 | . . . O . . . . 407 | . . . . . . . O 408 | . . . . O . . . 409 | . . O . . . . . 410 | O . . . . . . . 411 | . . . . . . O . 412 | . O . . . . . . 413 | . . . . . O . . 414 | 415 | . . . . O . . . 416 | O . . . . . . . 417 | . . . O . . . . 418 | . . . . . O . . 419 | . . . . . . . O 420 | . O . . . . . . 421 | . . . . . . O . 422 | . . O . . . . . 423 | 424 | . . . . O . . . 425 | O . . . . . . . 426 | . . . . . . . O 427 | . . . O . . . . 428 | . O . . . . . . 429 | . . . . . . O . 430 | . . O . . . . . 431 | . . . . . O . . 432 | 433 | . . . . O . . . 434 | O . . . . . . . 435 | . . . . . . . O 436 | . . . . . O . . 437 | . . O . . . . . 438 | . . . . . . O . 439 | . O . . . . . . 440 | . . . O . . . . 441 | 442 | . . . . O . . . 443 | . O . . . . . . 444 | . . . O . . . . 445 | . . . . . O . . 446 | . . . . . . . O 447 | . . O . . . . . 448 | O . . . . . . . 449 | . . . . . . O . 450 | 451 | . . . . O . . . 452 | . O . . . . . . 453 | . . . O . . . . 454 | . . . . . . O . 455 | . . O . . . . . 456 | . . . . . . . O 457 | . . . . . O . . 458 | O . . . . . . . 459 | 460 | . . . . O . . . 461 | . O . . . . . . 462 | . . . . . O . . 463 | O . . . . . . . 464 | . . . . . . O . 465 | . . . O . . . . 466 | . . . . . . . O 467 | . . O . . . . . 468 | 469 | . . . . O . . . 470 | . O . . . . . . 471 | . . . . . . . O 472 | O . . . . . . . 473 | . . . O . . . . 474 | . . . . . . O . 475 | . . O . . . . . 476 | . . . . . O . . 477 | 478 | . . . . O . . . 479 | . . O . . . . . 480 | O . . . . . . . 481 | . . . . . O . . 482 | . . . . . . . O 483 | . O . . . . . . 484 | . . . O . . . . 485 | . . . . . . O . 486 | 487 | . . . . O . . . 488 | . . O . . . . . 489 | O . . . . . . . 490 | . . . . . . O . 491 | . O . . . . . . 492 | . . . . . . . O 493 | . . . . . O . . 494 | . . . O . . . . 495 | 496 | . . . . O . . . 497 | . . O . . . . . 498 | . . . . . . . O 499 | . . . O . . . . 500 | . . . . . . O . 501 | O . . . . . . . 502 | . . . . . O . . 503 | . O . . . . . . 504 | 505 | . . . . O . . . 506 | . . . . . . O . 507 | O . . . . . . . 508 | . . O . . . . . 509 | . . . . . . . O 510 | . . . . . O . . 511 | . . . O . . . . 512 | . O . . . . . . 513 | 514 | . . . . O . . . 515 | . . . . . . O . 516 | O . . . . . . . 517 | . . . O . . . . 518 | . O . . . . . . 519 | . . . . . . . O 520 | . . . . . O . . 521 | . . O . . . . . 522 | 523 | . . . . O . . . 524 | . . . . . . O . 525 | . O . . . . . . 526 | . . . O . . . . 527 | . . . . . . . O 528 | O . . . . . . . 529 | . . O . . . . . 530 | . . . . . O . . 531 | 532 | . . . . O . . . 533 | . . . . . . O . 534 | . O . . . . . . 535 | . . . . . O . . 536 | . . O . . . . . 537 | O . . . . . . . 538 | . . . O . . . . 539 | . . . . . . . O 540 | 541 | . . . . O . . . 542 | . . . . . . O . 543 | . O . . . . . . 544 | . . . . . O . . 545 | . . O . . . . . 546 | O . . . . . . . 547 | . . . . . . . O 548 | . . . O . . . . 549 | 550 | . . . . O . . . 551 | . . . . . . O . 552 | . . . O . . . . 553 | O . . . . . . . 554 | . . O . . . . . 555 | . . . . . . . O 556 | . . . . . O . . 557 | . O . . . . . . 558 | 559 | . . . . O . . . 560 | . . . . . . . O 561 | . . . O . . . . 562 | O . . . . . . . 563 | . . O . . . . . 564 | . . . . . O . . 565 | . O . . . . . . 566 | . . . . . . O . 567 | 568 | . . . . O . . . 569 | . . . . . . . O 570 | . . . O . . . . 571 | O . . . . . . . 572 | . . . . . . O . 573 | . O . . . . . . 574 | . . . . . O . . 575 | . . O . . . . . 576 | 577 | . . . . . O . . 578 | O . . . . . . . 579 | . . . . O . . . 580 | . O . . . . . . 581 | . . . . . . . O 582 | . . O . . . . . 583 | . . . . . . O . 584 | . . . O . . . . 585 | 586 | . . . . . O . . 587 | . O . . . . . . 588 | . . . . . . O . 589 | O . . . . . . . 590 | . . O . . . . . 591 | . . . . O . . . 592 | . . . . . . . O 593 | . . . O . . . . 594 | 595 | . . . . . O . . 596 | . O . . . . . . 597 | . . . . . . O . 598 | O . . . . . . . 599 | . . . O . . . . 600 | . . . . . . . O 601 | . . . . O . . . 602 | . . O . . . . . 603 | 604 | . . . . . O . . 605 | . . O . . . . . 606 | O . . . . . . . 607 | . . . . . . O . 608 | . . . . O . . . 609 | . . . . . . . O 610 | . O . . . . . . 611 | . . . O . . . . 612 | 613 | . . . . . O . . 614 | . . O . . . . . 615 | O . . . . . . . 616 | . . . . . . . O 617 | . . . O . . . . 618 | . O . . . . . . 619 | . . . . . . O . 620 | . . . . O . . . 621 | 622 | . . . . . O . . 623 | . . O . . . . . 624 | O . . . . . . . 625 | . . . . . . . O 626 | . . . . O . . . 627 | . O . . . . . . 628 | . . . O . . . . 629 | . . . . . . O . 630 | 631 | . . . . . O . . 632 | . . O . . . . . 633 | . . . . O . . . 634 | . . . . . . O . 635 | O . . . . . . . 636 | . . . O . . . . 637 | . O . . . . . . 638 | . . . . . . . O 639 | 640 | . . . . . O . . 641 | . . O . . . . . 642 | . . . . O . . . 643 | . . . . . . . O 644 | O . . . . . . . 645 | . . . O . . . . 646 | . O . . . . . . 647 | . . . . . . O . 648 | 649 | . . . . . O . . 650 | . . O . . . . . 651 | . . . . . . O . 652 | . O . . . . . . 653 | . . . O . . . . 654 | . . . . . . . O 655 | O . . . . . . . 656 | . . . . O . . . 657 | 658 | . . . . . O . . 659 | . . O . . . . . 660 | . . . . . . O . 661 | . O . . . . . . 662 | . . . . . . . O 663 | . . . . O . . . 664 | O . . . . . . . 665 | . . . O . . . . 666 | 667 | . . . . . O . . 668 | . . O . . . . . 669 | . . . . . . O . 670 | . . . O . . . . 671 | O . . . . . . . 672 | . . . . . . . O 673 | . O . . . . . . 674 | . . . . O . . . 675 | 676 | . . . . . O . . 677 | . . . O . . . . 678 | O . . . . . . . 679 | . . . . O . . . 680 | . . . . . . . O 681 | . O . . . . . . 682 | . . . . . . O . 683 | . . O . . . . . 684 | 685 | . . . . . O . . 686 | . . . O . . . . 687 | . O . . . . . . 688 | . . . . . . . O 689 | . . . . O . . . 690 | . . . . . . O . 691 | O . . . . . . . 692 | . . O . . . . . 693 | 694 | . . . . . O . . 695 | . . . O . . . . 696 | . . . . . . O . 697 | O . . . . . . . 698 | . . O . . . . . 699 | . . . . O . . . 700 | . O . . . . . . 701 | . . . . . . . O 702 | 703 | . . . . . O . . 704 | . . . O . . . . 705 | . . . . . . O . 706 | O . . . . . . . 707 | . . . . . . . O 708 | . O . . . . . . 709 | . . . . O . . . 710 | . . O . . . . . 711 | 712 | . . . . . O . . 713 | . . . . . . . O 714 | . O . . . . . . 715 | . . . O . . . . 716 | O . . . . . . . 717 | . . . . . . O . 718 | . . . . O . . . 719 | . . O . . . . . 720 | 721 | . . . . . . O . 722 | O . . . . . . . 723 | . . O . . . . . 724 | . . . . . . . O 725 | . . . . . O . . 726 | . . . O . . . . 727 | . O . . . . . . 728 | . . . . O . . . 729 | 730 | . . . . . . O . 731 | . O . . . . . . 732 | . . . O . . . . 733 | O . . . . . . . 734 | . . . . . . . O 735 | . . . . O . . . 736 | . . O . . . . . 737 | . . . . . O . . 738 | 739 | . . . . . . O . 740 | . O . . . . . . 741 | . . . . . O . . 742 | . . O . . . . . 743 | O . . . . . . . 744 | . . . O . . . . 745 | . . . . . . . O 746 | . . . . O . . . 747 | 748 | . . . . . . O . 749 | . . O . . . . . 750 | O . . . . . . . 751 | . . . . . O . . 752 | . . . . . . . O 753 | . . . . O . . . 754 | . O . . . . . . 755 | . . . O . . . . 756 | 757 | . . . . . . O . 758 | . . O . . . . . 759 | . . . . . . . O 760 | . O . . . . . . 761 | . . . . O . . . 762 | O . . . . . . . 763 | . . . . . O . . 764 | . . . O . . . . 765 | 766 | . . . . . . O . 767 | . . . O . . . . 768 | . O . . . . . . 769 | . . . . O . . . 770 | . . . . . . . O 771 | O . . . . . . . 772 | . . O . . . . . 773 | . . . . . O . . 774 | 775 | . . . . . . O . 776 | . . . O . . . . 777 | . O . . . . . . 778 | . . . . . . . O 779 | . . . . . O . . 780 | O . . . . . . . 781 | . . O . . . . . 782 | . . . . O . . . 783 | 784 | . . . . . . O . 785 | . . . . O . . . 786 | . . O . . . . . 787 | O . . . . . . . 788 | . . . . . O . . 789 | . . . . . . . O 790 | . O . . . . . . 791 | . . . O . . . . 792 | 793 | . . . . . . . O 794 | . O . . . . . . 795 | . . . O . . . . 796 | O . . . . . . . 797 | . . . . . . O . 798 | . . . . O . . . 799 | . . O . . . . . 800 | . . . . . O . . 801 | 802 | . . . . . . . O 803 | . O . . . . . . 804 | . . . . O . . . 805 | . . O . . . . . 806 | O . . . . . . . 807 | . . . . . . O . 808 | . . . O . . . . 809 | . . . . . O . . 810 | 811 | . . . . . . . O 812 | . . O . . . . . 813 | O . . . . . . . 814 | . . . . . O . . 815 | . O . . . . . . 816 | . . . . O . . . 817 | . . . . . . O . 818 | . . . O . . . . 819 | 820 | . . . . . . . O 821 | . . . O . . . . 822 | O . . . . . . . 823 | . . O . . . . . 824 | . . . . . O . . 825 | . O . . . . . . 826 | . . . . . . O . 827 | . . . . O . . . 828 | 829 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/queens.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int N = 8; 3 | int row[8]; 4 | int col[8]; 5 | int d[2][16]; 6 | 7 | void printBoard() { 8 | int i; 9 | int j; 10 | for (i = 0; i < N; i++) { 11 | for (j = 0; j < N; j++) { 12 | if (col[i] == j) 13 | print(" O"); 14 | else 15 | print(" ."); 16 | } 17 | println(""); 18 | } 19 | println(""); 20 | sleep(50); // to prevent UART buffer from overflowing 21 | } 22 | 23 | void search(int c) { 24 | if (c == N) { 25 | printBoard(); 26 | } 27 | else { 28 | int r; 29 | for (r = 0; r < N; r++) { 30 | if (row[r] == 0 && d[0][r+c] == 0 && d[1][r+N-1-c] == 0) { 31 | row[r] = d[0][r+c] = d[1][r+N-1-c] = 1; 32 | col[c] = r; 33 | search(c+1); 34 | row[r] = d[0][r+c] = d[1][r+N-1-c] = 0; 35 | } 36 | } 37 | } 38 | } 39 | 40 | int main() { 41 | search(0); 42 | return 0; 43 | } 44 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/statement_test.ans: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 2 4 | 4 5 | 2 6 | 6 7 | 4 8 | 6 9 | 4 10 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/statement_test.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //考察点：section 8 语句，包括if,while,for,break,continue,return等 3 | //算法：线性筛法求欧拉函数 4 | //样例输入：10 5 | //样例输出： 6 | //1 7 | //2 8 | //2 9 | //4 10 | //2 11 | //6 12 | //4 13 | //6 14 | //4 15 | 16 | int N; 17 | int M = 0; 18 | int check[20]; 19 | 20 | int main() { 21 | N = inl(); 22 | int i = 0; 23 | while ( i <= N ) check[i++] = 1; 24 | int phi[15]; 25 | int P[15]; 26 | phi[1] = 1; 27 | for (i = 2; ; ++i ) { 28 | if ( i > N ) break; 29 | if ( check[i] ) { 30 | P[++M] = i; 31 | phi[i] = i - 1; 32 | } 33 | int k = i; 34 | int i; 35 | for (i = 1; i <= M && (k * P[i] <= N); i++) { 36 | int tmp = k * P[i]; 37 | if ( tmp > N ) continue; 38 | check[tmp] = 0; 39 | if ( k % P[i] == 0) { 40 | phi[tmp] = phi[k] * P[i]; 41 | break; 42 | } 43 | else { 44 | phi[k * P[i]] = phi[k] * (P[i] - 1); 45 | } 46 | } 47 | outlln(phi[k]); 48 | } 49 | return 0; 50 | } 51 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/statement_test.in: -------------------------------------------------------------------------------- 1 | 10 -------------------------------------------------------------------------------- /riscv/testcase/fpga/superloop.ans: -------------------------------------------------------------------------------- 1 | 720 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/superloop.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //Target: use loops to calculate calculator of 6! 3 | //@author yixi 4 | 5 | int N; 6 | int h = 99; 7 | int i = 100; 8 | int j = 101; 9 | int k = 102; 10 | int total = 0; 11 | 12 | int main() { 13 | int a; 14 | int b; 15 | int c; 16 | int d; 17 | int e; 18 | int f; 19 | N=inl(); 20 | for ( a=1; a<=N; a++ ) 21 | for ( b=1; b<=N; b++ ) 22 | for ( c=1; c<=N; c++ ) 23 | for ( d=1; d<=N; d++ ) 24 | for ( e=1; e<=N; e++ ) 25 | for ( f=1; f<=N; f++ ) 26 | if (a!=b && a!=c && a!=d && a!=e && a!=f && a!=h && a!=i && a!=j && a!=k 27 | && b!=c && b!=d && b!=e && b!=f && b!=h && b!=i && b!=j && b!=k 28 | && c!=d && c!=e && c!=f && c!=h && c!=i && c!=j && c!=k 29 | && d!=e && d!=f && d!=h && d!=i && d!=j && d!=k 30 | && e!=f && e!=h && e!=i && e!=j && e!=k 31 | && f!=h && f!=i && f!=j && f!=k && i!=j && h!=k) 32 | { 33 | total++; 34 | } 35 | 36 | outlln(total); 37 | return 0; 38 | } 39 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/superloop.in: -------------------------------------------------------------------------------- 1 | 6 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/tak.ans: -------------------------------------------------------------------------------- 1 | 13 2 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/tak.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int tak(int x, int y, int z) { 3 | if ( y < x ) return 1 + tak( tak(x-1, y, z), tak(y-1, z, x), tak(z-1, x, y) ); 4 | else return z; 5 | } 6 | 7 | int main(){ 8 | int a; 9 | int b; 10 | int c; 11 | a=inl(); 12 | b=inl(); 13 | c=inl(); 14 | outlln(tak(a,b,c)); 15 | return 0; 16 | } 17 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/tak.in: -------------------------------------------------------------------------------- 1 | 18 2 | 12 3 | 6 4 | -------------------------------------------------------------------------------- /riscv/testcase/fpga/testsleep.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int main() 3 | { 4 | int a = clock(); 5 | sleep(10000); // sleep for 10s 6 | int b = clock(); 7 | outlln(b-a); 8 | outlln((b-a)/CPU_CLK_FREQ); // should be 10 9 | return 0; // check actual running time 10 | } -------------------------------------------------------------------------------- /riscv/testcase/fpga/uartboom.ans: -------------------------------------------------------------------------------- 1 | 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-------------------------------------------------------------------------------- /riscv/testcase/fpga/uartboom.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | 3 | int main(){ 4 | int i = 0; 5 | for ( ; i < 0x1ff; i++) { 6 | outb('a'); 7 | outb('b'); 8 | outb('c'); 9 | outb('d'); 10 | outb('e'); 11 | outb('f'); 12 | outb('g'); 13 | outb('h'); 14 | outb('i'); 15 | outb('j'); 16 | outb('k'); 17 | outb('l'); 18 | outb('m'); 19 | outb('n'); 20 | outb('o'); 21 | outb('p'); 22 | } 23 | return 0; 24 | } 25 | -------------------------------------------------------------------------------- /riscv/testcase/sim/000_array_test1.ans: -------------------------------------------------------------------------------- 1 | 0000 2 | 1234 -------------------------------------------------------------------------------- /riscv/testcase/sim/000_array_test1.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //input: 1 2 3 4 3 | 4 | int a[4]; 5 | int main() 6 | { 7 | int b[4]; 8 | int i; 9 | for (i = 0; i < 4; i++) 10 | { 11 | a[i] = 0; 12 | b[i] = i + 1; 13 | } 14 | for (i = 0; i < 4; i++) 15 | { 16 | outl(a[i]); 17 | } 18 | println(""); 19 | int *p; 20 | p=b; 21 | for (i = 0; i < 4; i++) 22 | { 23 | outl(p[i]); 24 | } 25 | } 26 | -------------------------------------------------------------------------------- /riscv/testcase/sim/001_array_test2.ans: -------------------------------------------------------------------------------- 1 | 4 2 | 1234 3 | 0000 -------------------------------------------------------------------------------- /riscv/testcase/sim/001_array_test2.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // input: 1 2 3 4 3 | int a[4]; 4 | int *pa = a; 5 | int main() 6 | { 7 | int *pb[4]; 8 | int i; 9 | pb[0] = pa; 10 | pb[1] = pa; 11 | pb[2] = pa; 12 | pb[3] = pa; 13 | outlln(4); 14 | for (i = 0; i < 4; i++) 15 | pb[0][i] = i + 1; 16 | for (i = 0; i < 4; i++) 17 | outl(pb[1][i]); 18 | println(""); 19 | for (i = 0; i < 4; i++) 20 | pb[2][i] = 0; 21 | for (i = 0; i < 4; i++) 22 | outl(pb[3][i]); 23 | } 24 | -------------------------------------------------------------------------------- /riscv/testcase/sim/002_expr.ans: -------------------------------------------------------------------------------- 1 | -66060719 -323398799 -743275679 2 | -------------------------------------------------------------------------------- /riscv/testcase/sim/002_expr.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //This file use massive recursive expression to test: Common Expression substitution. 3 | //For my optimized version: All: 1397 Load: 86 Store: 55 Jumped: 23 4 | //For my unoptimized version: All: 24519 Load: 12183 Store: 55 Jumped: 23 5 | //A better result is welcomed. ------ From JinTianxing. 6 | 7 | int A = 1; 8 | int B = 1; 9 | int C = 1; 10 | 11 | int main(){ 12 | while (C < (1 << 29) && C > -(1 << 29)){ 13 | A = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 14 | B = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 15 | C = ((((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))))) - (((((((A + B) + (C - A + B)) - ((A + B) + (C - A + B))) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B)))) + (((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))) + ((((C - A + B) - (A + B)) + (C - A + B)) - (((A + B) + (C - A + B)) - (A + B))))) + ((((((C - A + B) - (A + B)) + ((C - A + B) - (A + B))) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B)))) - (((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))) - ((((A + B) + (C - A + B)) - (A + B)) + (((C - A + B) - (A + B)) + (C - A + B))))))); 16 | } 17 | outl(A); 18 | print(" "); 19 | outl(B); 20 | print(" "); 21 | outlln(C); 22 | return 0; 23 | } 24 | -------------------------------------------------------------------------------- /riscv/testcase/sim/003_looper.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // san check: if your predictor && icache work, it should be 1.5s @ 100Mhz 3 | unsigned n, sum; 4 | void work() { 5 | for (int i = 1; i <= 5 * n; i++) { 6 | sum += i * 998244353; 7 | } 8 | } 9 | int main() { 10 | n = 50; 11 | work(); 12 | n = 10000000; 13 | work(); 14 | outlln(sum); 15 | } -------------------------------------------------------------------------------- /riscv/testcase/sim/004_gcd.ans: -------------------------------------------------------------------------------- 1 | 1 2 | 1029 3 | 171 4 | -------------------------------------------------------------------------------- /riscv/testcase/sim/004_gcd.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int gcd(int x, int y) { 3 | if (x%y == 0) return y; 4 | else return gcd(y, x%y); 5 | } 6 | 7 | int main() { 8 | outlln(gcd(10,1)); 9 | outlln(gcd(34986,3087)); 10 | outlln(gcd(2907,1539)); 11 | 12 | return 0; 13 | } -------------------------------------------------------------------------------- /riscv/testcase/sim/005_lvalue2.ans: -------------------------------------------------------------------------------- 1 | 2 2 | -------------------------------------------------------------------------------- /riscv/testcase/sim/005_lvalue2.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a[4]; 3 | int main() 4 | { 5 | int b[4]; 6 | b[2]=2; 7 | int *p; 8 | p=b; 9 | outlln(p[2]); 10 | } 11 | -------------------------------------------------------------------------------- /riscv/testcase/sim/006_multiarray.ans: -------------------------------------------------------------------------------- 1 | 888 2 | 0 3 | 1 4 | 2 5 | 3 6 | 4 7 | 5 8 | 6 9 | 7 10 | 8 11 | 9 12 | 10 13 | 11 14 | 12 15 | 13 16 | 14 17 | 15 18 | 16 19 | 17 20 | 18 21 | 19 22 | 20 23 | 21 24 | 22 25 | 23 26 | 24 27 | 25 28 | 26 29 | 27 30 | 28 31 | 29 32 | 30 33 | 31 34 | 32 35 | 33 36 | 34 37 | 35 38 | 36 39 | 37 40 | 38 41 | 39 42 | 0 43 | -10 44 | -1 45 | -------------------------------------------------------------------------------- /riscv/testcase/sim/006_multiarray.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a[4][11]; 3 | int i; 4 | int j; 5 | 6 | struct rec { 7 | int num; 8 | int c; 9 | }b[5]; 10 | 11 | void printNum(int num) { 12 | outlln(num); 13 | } 14 | int main() { 15 | 16 | 17 | for (i = 0; i < 4; i ++) { 18 | for (j = 0; j < 10; j ++) 19 | a[i][j] = 888; 20 | } 21 | for (i = 0; i < 5; i ++) { 22 | b[i].num = -1; 23 | } 24 | 25 | printNum(a[3][9]); 26 | for (i = 0; i <= 3; i ++) 27 | for (j = 0; j <= 9; j ++) 28 | a[i][j] = i * 10 + j; 29 | 30 | for (i = 0; i <= 3; i ++) 31 | for (j = 0; j <= 9; j ++) 32 | printNum(a[i][j]); 33 | a[2][10]=0; 34 | printNum(a[2][10]); 35 | b[0].num = -2; 36 | b[a[2][10]].num = -10; 37 | printNum(b[0].num); 38 | printNum(b[1].num); 39 | return 0; 40 | } 41 | -------------------------------------------------------------------------------- /riscv/testcase/sim/007_hanoi.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int cd(int d, char* a, char* b, char* c, int sum) { 3 | sleep(5); // to prevent UART buffer from overflowing 4 | if (d == 1) { 5 | print("move "); 6 | print(a); 7 | print(" --> "); 8 | println(c); 9 | sum++; 10 | } else { 11 | sum = cd(d - 1, a, c, b, sum); 12 | print("move "); 13 | print(a); 14 | print(" --> "); 15 | println(c); 16 | sum = cd(d - 1, b, a, c, sum); 17 | sum++; 18 | } 19 | return sum; 20 | } 21 | 22 | int main() { 23 | char a[5] = "A"; 24 | char b[5] = "B"; 25 | char c[5] = "C"; 26 | int d = 10; 27 | int sum = cd(d, a, b, c, 0); 28 | outlln(sum); 29 | return 0; 30 | } 31 | 32 | -------------------------------------------------------------------------------- /riscv/testcase/sim/100_magic.ans: -------------------------------------------------------------------------------- 1 | 2 7 6 2 | 9 5 1 3 | 4 3 8 4 | 5 | 2 9 4 6 | 7 5 3 7 | 6 1 8 8 | 9 | 4 3 8 10 | 9 5 1 11 | 2 7 6 12 | 13 | 4 9 2 14 | 3 5 7 15 | 8 1 6 16 | 17 | 6 1 8 18 | 7 5 3 19 | 2 9 4 20 | 21 | 6 7 2 22 | 1 5 9 23 | 8 3 4 24 | 25 | 8 1 6 26 | 3 5 7 27 | 4 9 2 28 | 29 | 8 3 4 30 | 1 5 9 31 | 6 7 2 32 | 33 | 8 34 | -------------------------------------------------------------------------------- /riscv/testcase/sim/100_magic.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int make[3][3]; 3 | int color[10]; 4 | int count[1]; 5 | int i; 6 | int j; 7 | 8 | void origin(int N) 9 | { 10 | for (i = 0; i < N; i ++ ) { 11 | for (j = 0; j < N; j ++ ) 12 | make[i][j] = 0; 13 | } 14 | } 15 | 16 | void search(int x, int y, int z) 17 | { 18 | int s; 19 | int i; 20 | int j; 21 | if ((y > 0 || y < 0) || x == 0 || make[x-1][0] + make[x-1][1] + make[x-1][2] == 15) 22 | { 23 | if (x == 2 && y == 2) { 24 | make[2][2] = 45 - z; 25 | s = make[0][0] + make[0][1] + make[0][2]; 26 | if (make[1][0] + make[1][1] + make[1][2] == s && 27 | make[2][0] + make[2][1] + make[2][2] == s && 28 | make[0][0] + make[1][0] + make[2][0] == s && 29 | make[0][1] + make[1][1] + make[2][1] == s && 30 | make[0][2] + make[1][2] + make[2][2] == s && 31 | make[0][0] + make[1][1] + make[2][2] == s && 32 | make[2][0] + make[1][1] + make[0][2] == s) 33 | { 34 | count[0] = count[0] + 1; 35 | for (i = 0;i <= 2;i ++) 36 | { 37 | for (j = 0;j <= 2;j ++) 38 | { 39 | outl(make[i][j]); 40 | print(" "); 41 | } 42 | print("\n"); 43 | } 44 | print("\n"); 45 | } 46 | } 47 | else { 48 | if (y == 2) { 49 | make[x][y] = 15 - make[x][0] - make[x][1]; 50 | if (make[x][y] > 0 && make[x][y] < 10 && color[make[x][y]] == 0) { 51 | color[make[x][y]] = 1; 52 | if (y == 2) 53 | search(x + 1, 0, z+make[x][y]); 54 | else 55 | search(x, y+1, z+make[x][y]); 56 | color[make[x][y]] = 0; 57 | } 58 | } 59 | else { 60 | for (i = 1;i <= 9;i ++) { 61 | if (color[i] == 0) { 62 | color[i] = 1; 63 | make[x][y] = i; 64 | if (y == 2) 65 | search(x + 1, 0, z+i); 66 | else 67 | search(x, y+1, z+i); 68 | make[x][y] = 0; 69 | color[i] = 0; 70 | } 71 | } 72 | } 73 | } 74 | } 75 | } 76 | int main() 77 | { 78 | origin(3); 79 | search(0, 0, 0); 80 | outlln(count[0]); 81 | return 0; 82 | } 83 | -------------------------------------------------------------------------------- /riscv/testcase/sim/101_queens.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int N = 8; 3 | int row[8]; 4 | int col[8]; 5 | int d[2][16]; 6 | 7 | void printBoard() { 8 | int i; 9 | int j; 10 | for (i = 0; i < N; i++) { 11 | for (j = 0; j < N; j++) { 12 | if (col[i] == j) 13 | print(" O"); 14 | else 15 | print(" ."); 16 | } 17 | println(""); 18 | } 19 | println(""); 20 | sleep(50); // to prevent UART buffer from overflowing 21 | } 22 | 23 | void search(int c) { 24 | if (c == N) { 25 | printBoard(); 26 | } 27 | else { 28 | int r; 29 | for (r = 0; r < N; r++) { 30 | if (row[r] == 0 && d[0][r+c] == 0 && d[1][r+N-1-c] == 0) { 31 | row[r] = d[0][r+c] = d[1][r+N-1-c] = 1; 32 | col[c] = r; 33 | search(c+1); 34 | row[r] = d[0][r+c] = d[1][r+N-1-c] = 0; 35 | } 36 | } 37 | } 38 | } 39 | 40 | int main() { 41 | search(0); 42 | return 0; 43 | } 44 | -------------------------------------------------------------------------------- /riscv/testcase/sim/102_qsort.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // Target: qsort 3 | // Possible optimization: Dead code elimination, common expression, strength reduction 4 | // REMARKS: nothing. 5 | // 6 | // 7 | 8 | //int a[10100]; 9 | int a[10100]; 10 | int n = 10000; 11 | 12 | int qsrt(int l, int r) { 13 | int i = l; 14 | int j = r; 15 | int x = a[(l + r) / 2]; 16 | while (i <= j) { 17 | while (a[i] < x) i++; 18 | while (a[j] > x) j--; 19 | if (i <= j) { 20 | int temp = a[i]; 21 | a[i] = a[j]; 22 | a[j] = temp; 23 | i++; 24 | j--; 25 | } 26 | } 27 | if (l < j) qsrt(l, j); 28 | if (i < r) qsrt(i, r); 29 | return 0; 30 | } 31 | 32 | int main() { 33 | int i; 34 | for (i = 1; i <= n; i++) 35 | a[i] = n + 1 - i; 36 | qsrt(1, n); 37 | for (i = 1; i <= n; i++) { 38 | outl(a[i]); 39 | print(" "); 40 | sleep(1); // to prevent UART buffer from overflowing 41 | } 42 | print("\n"); 43 | return 0; 44 | } 45 | 46 | -------------------------------------------------------------------------------- /riscv/testcase/sim/103_bulgarian.ans: -------------------------------------------------------------------------------- 1 | Let's start! 2 | 5 3 | 5 5 1 6 193 4 | step 1: 5 | 4 4 5 192 5 6 | step 2: 7 | 3 3 4 191 4 5 8 | step 3: 9 | 2 2 3 190 3 4 6 10 | step 4: 11 | 1 1 2 189 2 3 5 7 12 | step 5: 13 | 1 188 1 2 4 6 8 14 | step 6: 15 | 187 1 3 5 7 7 16 | step 7: 17 | 186 2 4 6 6 6 18 | step 8: 19 | 185 1 3 5 5 5 6 20 | step 9: 21 | 184 2 4 4 4 5 7 22 | step 10: 23 | 183 1 3 3 3 4 6 7 24 | step 11: 25 | 182 2 2 2 3 5 6 8 26 | step 12: 27 | 181 1 1 1 2 4 5 7 8 28 | step 13: 29 | 180 1 3 4 6 7 9 30 | step 14: 31 | 179 2 3 5 6 8 7 32 | step 15: 33 | 178 1 2 4 5 7 6 7 34 | step 16: 35 | 177 1 3 4 6 5 6 8 36 | step 17: 37 | 176 2 3 5 4 5 7 8 38 | step 18: 39 | 175 1 2 4 3 4 6 7 8 40 | step 19: 41 | 174 1 3 2 3 5 6 7 9 42 | step 20: 43 | 173 2 1 2 4 5 6 8 9 44 | step 21: 45 | 172 1 1 3 4 5 7 8 9 46 | step 22: 47 | 171 2 3 4 6 7 8 9 48 | step 23: 49 | 170 1 2 3 5 6 7 8 8 50 | step 24: 51 | 169 1 2 4 5 6 7 7 9 52 | step 25: 53 | 168 1 3 4 5 6 6 8 9 54 | step 26: 55 | 167 2 3 4 5 5 7 8 9 56 | step 27: 57 | 166 1 2 3 4 4 6 7 8 9 58 | step 28: 59 | 165 1 2 3 3 5 6 7 8 10 60 | step 29: 61 | 164 1 2 2 4 5 6 7 9 10 62 | step 30: 63 | 163 1 1 3 4 5 6 8 9 10 64 | step 31: 65 | 162 2 3 4 5 7 8 9 10 66 | step 32: 67 | 161 1 2 3 4 6 7 8 9 9 68 | step 33: 69 | 160 1 2 3 5 6 7 8 8 10 70 | step 34: 71 | 159 1 2 4 5 6 7 7 9 10 72 | step 35: 73 | 158 1 3 4 5 6 6 8 9 10 74 | step 36: 75 | 157 2 3 4 5 5 7 8 9 10 76 | step 37: 77 | 156 1 2 3 4 4 6 7 8 9 10 78 | step 38: 79 | 155 1 2 3 3 5 6 7 8 9 11 80 | step 39: 81 | 154 1 2 2 4 5 6 7 8 10 11 82 | step 40: 83 | 153 1 1 3 4 5 6 7 9 10 11 84 | step 41: 85 | 152 2 3 4 5 6 8 9 10 11 86 | step 42: 87 | 151 1 2 3 4 5 7 8 9 10 10 88 | step 43: 89 | 150 1 2 3 4 6 7 8 9 9 11 90 | step 44: 91 | 149 1 2 3 5 6 7 8 8 10 11 92 | step 45: 93 | 148 1 2 4 5 6 7 7 9 10 11 94 | step 46: 95 | 147 1 3 4 5 6 6 8 9 10 11 96 | step 47: 97 | 146 2 3 4 5 5 7 8 9 10 11 98 | step 48: 99 | 145 1 2 3 4 4 6 7 8 9 10 11 100 | step 49: 101 | 144 1 2 3 3 5 6 7 8 9 10 12 102 | step 50: 103 | 143 1 2 2 4 5 6 7 8 9 11 12 104 | step 51: 105 | 142 1 1 3 4 5 6 7 8 10 11 12 106 | step 52: 107 | 141 2 3 4 5 6 7 9 10 11 12 108 | step 53: 109 | 140 1 2 3 4 5 6 8 9 10 11 11 110 | step 54: 111 | 139 1 2 3 4 5 7 8 9 10 10 12 112 | step 55: 113 | 138 1 2 3 4 6 7 8 9 9 11 12 114 | step 56: 115 | 137 1 2 3 5 6 7 8 8 10 11 12 116 | step 57: 117 | 136 1 2 4 5 6 7 7 9 10 11 12 118 | step 58: 119 | 135 1 3 4 5 6 6 8 9 10 11 12 120 | step 59: 121 | 134 2 3 4 5 5 7 8 9 10 11 12 122 | step 60: 123 | 133 1 2 3 4 4 6 7 8 9 10 11 12 124 | step 61: 125 | 132 1 2 3 3 5 6 7 8 9 10 11 13 126 | step 62: 127 | 131 1 2 2 4 5 6 7 8 9 10 12 13 128 | step 63: 129 | 130 1 1 3 4 5 6 7 8 9 11 12 13 130 | step 64: 131 | 129 2 3 4 5 6 7 8 10 11 12 13 132 | step 65: 133 | 128 1 2 3 4 5 6 7 9 10 11 12 12 134 | step 66: 135 | 127 1 2 3 4 5 6 8 9 10 11 11 13 136 | step 67: 137 | 126 1 2 3 4 5 7 8 9 10 10 12 13 138 | step 68: 139 | 125 1 2 3 4 6 7 8 9 9 11 12 13 140 | step 69: 141 | 124 1 2 3 5 6 7 8 8 10 11 12 13 142 | step 70: 143 | 123 1 2 4 5 6 7 7 9 10 11 12 13 144 | step 71: 145 | 122 1 3 4 5 6 6 8 9 10 11 12 13 146 | step 72: 147 | 121 2 3 4 5 5 7 8 9 10 11 12 13 148 | step 73: 149 | 120 1 2 3 4 4 6 7 8 9 10 11 12 13 150 | step 74: 151 | 119 1 2 3 3 5 6 7 8 9 10 11 12 14 152 | step 75: 153 | 118 1 2 2 4 5 6 7 8 9 10 11 13 14 154 | step 76: 155 | 117 1 1 3 4 5 6 7 8 9 10 12 13 14 156 | step 77: 157 | 116 2 3 4 5 6 7 8 9 11 12 13 14 158 | step 78: 159 | 115 1 2 3 4 5 6 7 8 10 11 12 13 13 160 | step 79: 161 | 114 1 2 3 4 5 6 7 9 10 11 12 12 14 162 | step 80: 163 | 113 1 2 3 4 5 6 8 9 10 11 11 13 14 164 | step 81: 165 | 112 1 2 3 4 5 7 8 9 10 10 12 13 14 166 | step 82: 167 | 111 1 2 3 4 6 7 8 9 9 11 12 13 14 168 | step 83: 169 | 110 1 2 3 5 6 7 8 8 10 11 12 13 14 170 | step 84: 171 | 109 1 2 4 5 6 7 7 9 10 11 12 13 14 172 | step 85: 173 | 108 1 3 4 5 6 6 8 9 10 11 12 13 14 174 | step 86: 175 | 107 2 3 4 5 5 7 8 9 10 11 12 13 14 176 | step 87: 177 | 106 1 2 3 4 4 6 7 8 9 10 11 12 13 14 178 | step 88: 179 | 105 1 2 3 3 5 6 7 8 9 10 11 12 13 15 180 | step 89: 181 | 104 1 2 2 4 5 6 7 8 9 10 11 12 14 15 182 | step 90: 183 | 103 1 1 3 4 5 6 7 8 9 10 11 13 14 15 184 | step 91: 185 | 102 2 3 4 5 6 7 8 9 10 12 13 14 15 186 | step 92: 187 | 101 1 2 3 4 5 6 7 8 9 11 12 13 14 14 188 | step 93: 189 | 100 1 2 3 4 5 6 7 8 10 11 12 13 13 15 190 | step 94: 191 | 99 1 2 3 4 5 6 7 9 10 11 12 12 14 15 192 | step 95: 193 | 98 1 2 3 4 5 6 8 9 10 11 11 13 14 15 194 | step 96: 195 | 97 1 2 3 4 5 7 8 9 10 10 12 13 14 15 196 | step 97: 197 | 96 1 2 3 4 6 7 8 9 9 11 12 13 14 15 198 | step 98: 199 | 95 1 2 3 5 6 7 8 8 10 11 12 13 14 15 200 | step 99: 201 | 94 1 2 4 5 6 7 7 9 10 11 12 13 14 15 202 | step 100: 203 | 93 1 3 4 5 6 6 8 9 10 11 12 13 14 15 204 | step 101: 205 | 92 2 3 4 5 5 7 8 9 10 11 12 13 14 15 206 | step 102: 207 | 91 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 208 | step 103: 209 | 90 1 2 3 3 5 6 7 8 9 10 11 12 13 14 16 210 | step 104: 211 | 89 1 2 2 4 5 6 7 8 9 10 11 12 13 15 16 212 | step 105: 213 | 88 1 1 3 4 5 6 7 8 9 10 11 12 14 15 16 214 | step 106: 215 | 87 2 3 4 5 6 7 8 9 10 11 13 14 15 16 216 | step 107: 217 | 86 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 218 | step 108: 219 | 85 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 220 | step 109: 221 | 84 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 222 | step 110: 223 | 83 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 224 | step 111: 225 | 82 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 226 | step 112: 227 | 81 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 228 | step 113: 229 | 80 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 230 | step 114: 231 | 79 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 232 | step 115: 233 | 78 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 234 | step 116: 235 | 77 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 236 | step 117: 237 | 76 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 238 | step 118: 239 | 75 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 240 | step 119: 241 | 74 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 17 242 | step 120: 243 | 73 1 2 2 4 5 6 7 8 9 10 11 12 13 14 16 17 244 | step 121: 245 | 72 1 1 3 4 5 6 7 8 9 10 11 12 13 15 16 17 246 | step 122: 247 | 71 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 248 | step 123: 249 | 70 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 250 | step 124: 251 | 69 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 252 | step 125: 253 | 68 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 254 | step 126: 255 | 67 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 256 | step 127: 257 | 66 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 258 | step 128: 259 | 65 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 260 | step 129: 261 | 64 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 262 | step 130: 263 | 63 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 264 | step 131: 265 | 62 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 266 | step 132: 267 | 61 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 268 | step 133: 269 | 60 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 270 | step 134: 271 | 59 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 272 | step 135: 273 | 58 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 274 | step 136: 275 | 57 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 18 276 | step 137: 277 | 56 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 17 18 278 | step 138: 279 | 55 1 1 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 280 | step 139: 281 | 54 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 282 | step 140: 283 | 53 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 284 | step 141: 285 | 52 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 286 | step 142: 287 | 51 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 288 | step 143: 289 | 50 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 290 | step 144: 291 | 49 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 292 | step 145: 293 | 48 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 294 | step 146: 295 | 47 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 296 | step 147: 297 | 46 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 298 | step 148: 299 | 45 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 300 | step 149: 301 | 44 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 302 | step 150: 303 | 43 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 304 | step 151: 305 | 42 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 306 | step 152: 307 | 41 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 308 | step 153: 309 | 40 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 310 | step 154: 311 | 39 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 19 312 | step 155: 313 | 38 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 314 | step 156: 315 | 37 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 316 | step 157: 317 | 36 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 318 | step 158: 319 | 35 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 18 320 | step 159: 321 | 34 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 19 322 | step 160: 323 | 33 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 19 324 | step 161: 325 | 32 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 19 326 | step 162: 327 | 31 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 19 328 | step 163: 329 | 30 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 19 330 | step 164: 331 | 29 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 19 332 | step 165: 333 | 28 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 19 334 | step 166: 335 | 27 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 19 336 | step 167: 337 | 26 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 19 338 | step 168: 339 | 25 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 19 340 | step 169: 341 | 24 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 342 | step 170: 343 | 23 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 344 | step 171: 345 | 22 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 346 | step 172: 347 | 21 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 348 | step 173: 349 | 20 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 350 | step 174: 351 | 19 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 352 | step 175: 353 | 18 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 354 | step 176: 355 | 17 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19 20 356 | step 177: 357 | 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 19 358 | step 178: 359 | 15 1 2 3 4 5 6 7 8 9 10 11 12 13 15 16 17 18 18 20 360 | step 179: 361 | 14 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 17 19 20 362 | step 180: 363 | 13 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 16 18 19 20 364 | step 181: 365 | 12 1 2 3 4 5 6 7 8 9 10 12 13 14 15 15 17 18 19 20 366 | step 182: 367 | 11 1 2 3 4 5 6 7 8 9 11 12 13 14 14 16 17 18 19 20 368 | step 183: 369 | 10 1 2 3 4 5 6 7 8 10 11 12 13 13 15 16 17 18 19 20 370 | step 184: 371 | 9 1 2 3 4 5 6 7 9 10 11 12 12 14 15 16 17 18 19 20 372 | step 185: 373 | 8 1 2 3 4 5 6 8 9 10 11 11 13 14 15 16 17 18 19 20 374 | step 186: 375 | 7 1 2 3 4 5 7 8 9 10 10 12 13 14 15 16 17 18 19 20 376 | step 187: 377 | 6 1 2 3 4 6 7 8 9 9 11 12 13 14 15 16 17 18 19 20 378 | step 188: 379 | 5 1 2 3 5 6 7 8 8 10 11 12 13 14 15 16 17 18 19 20 380 | step 189: 381 | 4 1 2 4 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 382 | step 190: 383 | 3 1 3 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 384 | step 191: 385 | 2 2 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 386 | step 192: 387 | 1 1 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 388 | step 193: 389 | 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 390 | step 194: 391 | 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 392 | step 195: 393 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 20 394 | step 196: 395 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 19 20 396 | step 197: 397 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 18 19 19 398 | step 198: 399 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 17 18 18 20 400 | step 199: 401 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 16 17 17 19 20 402 | step 200: 403 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 16 16 18 19 20 404 | step 201: 405 | 1 2 3 4 5 6 7 8 9 10 11 13 13 14 15 15 17 18 19 20 406 | step 202: 407 | 1 2 3 4 5 6 7 8 9 10 12 12 13 14 14 16 17 18 19 20 408 | step 203: 409 | 1 2 3 4 5 6 7 8 9 11 11 12 13 13 15 16 17 18 19 20 410 | step 204: 411 | 1 2 3 4 5 6 7 8 10 10 11 12 12 14 15 16 17 18 19 20 412 | step 205: 413 | 1 2 3 4 5 6 7 9 9 10 11 11 13 14 15 16 17 18 19 20 414 | step 206: 415 | 1 2 3 4 5 6 8 8 9 10 10 12 13 14 15 16 17 18 19 20 416 | step 207: 417 | 1 2 3 4 5 7 7 8 9 9 11 12 13 14 15 16 17 18 19 20 418 | step 208: 419 | 1 2 3 4 6 6 7 8 8 10 11 12 13 14 15 16 17 18 19 20 420 | step 209: 421 | 1 2 3 5 5 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 422 | step 210: 423 | 1 2 4 4 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 424 | step 211: 425 | 1 3 3 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 426 | step 212: 427 | 2 2 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 428 | step 213: 429 | 1 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 430 | step 214: 431 | 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 432 | step 215: 433 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 434 | step 216: 435 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 20 436 | step 217: 437 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 19 19 438 | step 218: 439 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 18 18 20 440 | step 219: 441 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 17 17 19 20 442 | step 220: 443 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 16 16 18 19 20 444 | step 221: 445 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 15 15 17 18 19 20 446 | step 222: 447 | 1 2 3 4 5 6 7 8 9 10 11 13 13 14 14 16 17 18 19 20 448 | step 223: 449 | 1 2 3 4 5 6 7 8 9 10 12 12 13 13 15 16 17 18 19 20 450 | step 224: 451 | 1 2 3 4 5 6 7 8 9 11 11 12 12 14 15 16 17 18 19 20 452 | step 225: 453 | 1 2 3 4 5 6 7 8 10 10 11 11 13 14 15 16 17 18 19 20 454 | step 226: 455 | 1 2 3 4 5 6 7 9 9 10 10 12 13 14 15 16 17 18 19 20 456 | step 227: 457 | 1 2 3 4 5 6 8 8 9 9 11 12 13 14 15 16 17 18 19 20 458 | step 228: 459 | 1 2 3 4 5 7 7 8 8 10 11 12 13 14 15 16 17 18 19 20 460 | step 229: 461 | 1 2 3 4 6 6 7 7 9 10 11 12 13 14 15 16 17 18 19 20 462 | step 230: 463 | 1 2 3 5 5 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 464 | step 231: 465 | 1 2 4 4 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 466 | step 232: 467 | 1 3 3 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 468 | step 233: 469 | 2 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 470 | step 234: 471 | 1 1 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 472 | step 235: 473 | 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 474 | step 236: 475 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 20 476 | step 237: 477 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 19 19 478 | step 238: 479 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 18 18 20 480 | step 239: 481 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 17 17 19 20 482 | step 240: 483 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 16 16 18 19 20 484 | step 241: 485 | 1 2 3 4 5 6 7 8 9 10 11 12 13 15 15 15 17 18 19 20 486 | step 242: 487 | 1 2 3 4 5 6 7 8 9 10 11 12 14 14 14 16 17 18 19 20 488 | step 243: 489 | 1 2 3 4 5 6 7 8 9 10 11 13 13 13 15 16 17 18 19 20 490 | step 244: 491 | 1 2 3 4 5 6 7 8 9 10 12 12 12 14 15 16 17 18 19 20 492 | step 245: 493 | 1 2 3 4 5 6 7 8 9 11 11 11 13 14 15 16 17 18 19 20 494 | step 246: 495 | 1 2 3 4 5 6 7 8 10 10 10 12 13 14 15 16 17 18 19 20 496 | step 247: 497 | 1 2 3 4 5 6 7 9 9 9 11 12 13 14 15 16 17 18 19 20 498 | step 248: 499 | 1 2 3 4 5 6 8 8 8 10 11 12 13 14 15 16 17 18 19 20 500 | step 249: 501 | 1 2 3 4 5 7 7 7 9 10 11 12 13 14 15 16 17 18 19 20 502 | step 250: 503 | 1 2 3 4 6 6 6 8 9 10 11 12 13 14 15 16 17 18 19 20 504 | step 251: 505 | 1 2 3 5 5 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 506 | step 252: 507 | 1 2 4 4 4 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 508 | step 253: 509 | 1 3 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 510 | step 254: 511 | 2 2 2 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 512 | step 255: 513 | 1 1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 514 | step 256: 515 | 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 516 | step 257: 517 | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 518 | Total: 257 step(s) 519 | -------------------------------------------------------------------------------- /riscv/testcase/sim/103_bulgarian.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | // Target: Simulate a Bulgarian-solitaire game. 3 | // Possible opitimization: Dead code elimination, common expression, inline function, loop unrolling, etc. 4 | // REMARKS: A funny game. If you like, you can try to prove that when n=1+2+..+i(i>0), the game will always stop 5 | // and converge to the only solution: {1,2,...i}. :) 6 | 7 | int n; 8 | int h; 9 | int now; 10 | int a[100]; 11 | int A = 48271; 12 | int M = 2147483647; 13 | int Q; 14 | int R; 15 | int seed=1; 16 | int random() { 17 | int tempseed = A * (seed % Q) - R * (seed / Q); 18 | if (tempseed >= 0) 19 | seed = tempseed; 20 | else 21 | seed = tempseed + M; 22 | return seed; 23 | } 24 | void initialize(int val) { 25 | seed = val; 26 | } 27 | void swap(int x,int y) { 28 | int temp = a[x]; 29 | a[x] = a[y]; 30 | a[y] = temp; 31 | } 32 | int pd(int x) { 33 | for (;h <= x; ++h) 34 | if (x == h * (h + 1) / 2) 35 | return 1; 36 | return 0; 37 | } 38 | void show() { 39 | int i; 40 | for (i = 0; i < now; ++i){ 41 | outl(a[i]); 42 | print(" "); 43 | } 44 | println(""); 45 | } 46 | int win() 47 | { 48 | int i; 49 | int j; 50 | int b[100]; 51 | int temp; 52 | if (now != h) 53 | return 0; 54 | for (j = 0; j < now; ++j) 55 | b[j] = a[j]; 56 | for (i = 0;i < now - 1; ++i) 57 | for (j = i + 1;j < now; ++j) 58 | if (b[i] > b[j]) { 59 | temp = b[i]; 60 | b[i] = b[j]; 61 | b[j] = temp; 62 | } 63 | for (i = 0; i < now; ++i) 64 | if (b[i] != i + 1) 65 | return 0; 66 | return 1; 67 | } 68 | void merge() 69 | { 70 | int i; 71 | for (i = 0;i < now; ++i) 72 | if (a[i] == 0) { 73 | int j; 74 | for (j = i+1; j < now; ++j) 75 | if (a[j] != 0) { 76 | swap(i,j); 77 | break; 78 | } 79 | } 80 | for (i=0;i n) 115 | a[i] = random() % 10 + 1; 116 | temp = temp + a[i]; 117 | } 118 | a[now - 1] = n - temp; 119 | show(); 120 | merge(); 121 | while (!win()) { 122 | print("step "); 123 | outl(++count); 124 | println(":"); 125 | move(); 126 | merge(); 127 | show(); 128 | sleep(10); // to prevent UART buffer from overflowing 129 | } 130 | print("Total: "); 131 | outl(count); 132 | println(" step(s)"); 133 | return 0; 134 | } 135 | -------------------------------------------------------------------------------- /riscv/testcase/sim/basicopt1.ans: -------------------------------------------------------------------------------- 1 | 99850 2 | -------------------------------------------------------------------------------- /riscv/testcase/sim/basicopt1.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int main() 3 | { 4 | int a[100][100]; 5 | int i; 6 | int j; 7 | int sum = 0; 8 | 9 | for (i = 0;i < 100;i++) 10 | for (j = 0;j < 100;j++) 11 | a[i][j] = 0; 12 | int quotient; 13 | int remainder; 14 | for (i = 0;i < 100;i++) 15 | if (i > 20 && i < 80) { 16 | for (j = 0;j < 100;j++) 17 | if (j > 5 || i < 90) { 18 | quotient = j * 4 / 100; 19 | remainder = j * 4 % 100; 20 | a[i + quotient][remainder] = j + (100 - 1 + 1 - 1 + 1) / 2; 21 | } 22 | } 23 | 24 | for (i = 0;i < 100;i++) 25 | for (j = 0;j < 100;j++) 26 | sum = sum + a[i][j]; 27 | outlln(sum); 28 | } 29 | -------------------------------------------------------------------------------- /riscv/testcase/sim/manyarguments.ans: -------------------------------------------------------------------------------- 1 | 120 2 | -------------------------------------------------------------------------------- /riscv/testcase/sim/manyarguments.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | int a(int a1, int a2, int a3, int a4, int a5, int a6, int a7, int a8, int a9, int a10, int a11, int a12, int a13, int a14, int a15) 3 | { 4 | return a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15; 5 | } 6 | 7 | int main() 8 | { 9 | outlln(a(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)); 10 | return 0; 11 | } 12 | -------------------------------------------------------------------------------- /riscv/testcase/sim/statement_test.ans: -------------------------------------------------------------------------------- 1 | 1 2 | 2 3 | 2 4 | 4 5 | 2 6 | 6 7 | 4 8 | 6 9 | 4 10 | -------------------------------------------------------------------------------- /riscv/testcase/sim/statement_test.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //考察点：section 8 语句，包括if,while,for,break,continue,return等 3 | //算法：线性筛法求欧拉函数 4 | //样例输入：10 5 | //样例输出： 6 | //1 7 | //2 8 | //2 9 | //4 10 | //2 11 | //6 12 | //4 13 | //6 14 | //4 15 | 16 | int N; 17 | int M = 0; 18 | int check[20]; 19 | 20 | int main() { 21 | N = 10; 22 | int i = 0; 23 | while ( i <= N ) check[i++] = 1; 24 | int phi[15]; 25 | int P[15]; 26 | phi[1] = 1; 27 | for (i = 2; ; ++i ) { 28 | if ( i > N ) break; 29 | if ( check[i] ) { 30 | P[++M] = i; 31 | phi[i] = i - 1; 32 | } 33 | int k = i; 34 | int i; 35 | for (i = 1; i <= M && (k * P[i] <= N); i++) { 36 | int tmp = k * P[i]; 37 | if ( tmp > N ) continue; 38 | check[tmp] = 0; 39 | if ( k % P[i] == 0) { 40 | phi[tmp] = phi[k] * P[i]; 41 | break; 42 | } 43 | else { 44 | phi[k * P[i]] = phi[k] * (P[i] - 1); 45 | } 46 | } 47 | outlln(phi[k]); 48 | } 49 | return 0; 50 | } 51 | -------------------------------------------------------------------------------- /riscv/testcase/sim/superloop.ans: -------------------------------------------------------------------------------- 1 | 720 2 | -------------------------------------------------------------------------------- /riscv/testcase/sim/superloop.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | //Target: use loops to calculate calculator of 6! 3 | //@author yixi 4 | 5 | int N; 6 | int h = 99; 7 | int i = 100; 8 | int j = 101; 9 | int k = 102; 10 | int total = 0; 11 | 12 | int main() { 13 | int a; 14 | int b; 15 | int c; 16 | int d; 17 | int e; 18 | int f; 19 | N=6; 20 | for ( a=1; a<=N; a++ ) 21 | for ( b=1; b<=N; b++ ) 22 | for ( c=1; c<=N; c++ ) 23 | for ( d=1; d<=N; d++ ) 24 | for ( e=1; e<=N; e++ ) 25 | for ( f=1; f<=N; f++ ) 26 | if (a!=b && a!=c && a!=d && a!=e && a!=f && a!=h && a!=i && a!=j && a!=k 27 | && b!=c && b!=d && b!=e && b!=f && b!=h && b!=i && b!=j && b!=k 28 | && c!=d && c!=e && c!=f && c!=h && c!=i && c!=j && c!=k 29 | && d!=e && d!=f && d!=h && d!=i && d!=j && d!=k 30 | && e!=f && e!=h && e!=i && e!=j && e!=k 31 | && f!=h && f!=i && f!=j && f!=k && i!=j && h!=k) 32 | { 33 | total++; 34 | } 35 | 36 | outlln(total); 37 | return 0; 38 | } 39 | -------------------------------------------------------------------------------- /riscv/testcase/sim/uartboom.ans: -------------------------------------------------------------------------------- 1 | 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-------------------------------------------------------------------------------- /riscv/testcase/sim/uartboom.c: -------------------------------------------------------------------------------- 1 | #include "io.h" 2 | 3 | int main(){ 4 | int i = 0; 5 | for ( ; i < 0x1ff; i++) { 6 | outb('a'); 7 | outb('b'); 8 | outb('c'); 9 | outb('d'); 10 | outb('e'); 11 | outb('f'); 12 | outb('g'); 13 | outb('h'); 14 | outb('i'); 15 | outb('j'); 16 | outb('k'); 17 | outb('l'); 18 | outb('m'); 19 | outb('n'); 20 | outb('o'); 21 | outb('p'); 22 | } 23 | return 0; 24 | } 25 | -------------------------------------------------------------------------------- /riscv/testspace/.keep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ACMClassCourses/RISCV-CPU/9c5153951e01c8bf072e6b37b874e1408e75af89/riscv/testspace/.keep --------------------------------------------------------------------------------