├── LICENSE.txt ├── README.md └── rtl ├── accelerator_manifest.flist ├── accelerator_pkg.sv ├── accelerator_top.sv ├── address_unit.sv ├── arith_stage.sv ├── bit_ext.sv ├── gtkw ├── bit_ext_td.gtkw ├── relu_bound_td.gtkw └── sat_unit_td.gtkw ├── mapping_unit.sv ├── obj ├── tb_bit_ext.vvp ├── tb_relu_bound.vvp └── tb_sat_unit.vvp ├── pe_32b.sv ├── pe_codes.ods ├── relu_bound.sv ├── sat_unit.sv ├── scalar_replicate.sv ├── tb ├── tb_address_unit.c ├── tb_bit_ext.sv ├── tb_relu_bound.sv └── tb_sat_unit.sv ├── temporary_reg.sv ├── vcd ├── bit_ext.vcd ├── relu_bound.vcd └── sat_unit.vcd ├── vector_csrs.sv ├── vector_decoder.sv ├── vector_lsu.sv ├── vector_registers.sv └── vw_sign_ext.sv /LICENSE.txt: -------------------------------------------------------------------------------- 1 | CERN Open Hardware Licence Version 2 - Strongly Reciprocal 2 | 3 | 4 | Preamble 5 | 6 | CERN has developed this licence to promote collaboration among 7 | hardware designers and to provide a legal tool which supports the 8 | freedom to use, study, modify, share and distribute hardware designs 9 | and products based on those designs. Version 2 of the CERN Open 10 | Hardware Licence comes in three variants: CERN-OHL-P (permissive); and 11 | two reciprocal licences: CERN-OHL-W (weakly reciprocal) and this 12 | licence, CERN-OHL-S (strongly reciprocal). 13 | 14 | The CERN-OHL-S is copyright CERN 2020. Anyone is welcome to use it, in 15 | unmodified form only. 16 | 17 | Use of this Licence does not imply any endorsement by CERN of any 18 | Licensor or their designs nor does it imply any involvement by CERN in 19 | their development. 20 | 21 | 22 | 1 Definitions 23 | 24 | 1.1 'Licence' means this CERN-OHL-S. 25 | 26 | 1.2 'Compatible Licence' means 27 | 28 | a) any earlier version of the CERN Open Hardware licence, or 29 | 30 | b) any version of the CERN-OHL-S, or 31 | 32 | c) any licence which permits You to treat the Source to which 33 | it applies as licensed under CERN-OHL-S provided that on 34 | Conveyance of any such Source, or any associated Product You 35 | treat the Source in question as being licensed under 36 | CERN-OHL-S. 37 | 38 | 1.3 'Source' means information such as design materials or digital 39 | code which can be applied to Make or test a Product or to 40 | prepare a Product for use, Conveyance or sale, regardless of its 41 | medium or how it is expressed. It may include Notices. 42 | 43 | 1.4 'Covered Source' means Source that is explicitly made available 44 | under this Licence. 45 | 46 | 1.5 'Product' means any device, component, work or physical object, 47 | whether in finished or intermediate form, arising from the use, 48 | application or processing of Covered Source. 49 | 50 | 1.6 'Make' means to create or configure something, whether by 51 | manufacture, assembly, compiling, loading or applying Covered 52 | Source or another Product or otherwise. 53 | 54 | 1.7 'Available Component' means any part, sub-assembly, library or 55 | code which: 56 | 57 | a) is licensed to You as Complete Source under a Compatible 58 | Licence; or 59 | 60 | b) is available, at the time a Product or the Source containing 61 | it is first Conveyed, to You and any other prospective 62 | licensees 63 | 64 | i) as a physical part with sufficient rights and 65 | information (including any configuration and 66 | programming files and information about its 67 | characteristics and interfaces) to enable it either to 68 | be Made itself, or to be sourced and used to Make the 69 | Product; or 70 | ii) as part of the normal distribution of a tool used to 71 | design or Make the Product. 72 | 73 | 1.8 'Complete Source' means the set of all Source necessary to Make 74 | a Product, in the preferred form for making modifications, 75 | including necessary installation and interfacing information 76 | both for the Product, and for any included Available Components. 77 | If the format is proprietary, it must also be made available in 78 | a format (if the proprietary tool can create it) which is 79 | viewable with a tool available to potential licensees and 80 | licensed under a licence approved by the Free Software 81 | Foundation or the Open Source Initiative. Complete Source need 82 | not include the Source of any Available Component, provided that 83 | You include in the Complete Source sufficient information to 84 | enable a recipient to Make or source and use the Available 85 | Component to Make the Product. 86 | 87 | 1.9 'Source Location' means a location where a Licensor has placed 88 | Covered Source, and which that Licensor reasonably believes will 89 | remain easily accessible for at least three years for anyone to 90 | obtain a digital copy. 91 | 92 | 1.10 'Notice' means copyright, acknowledgement and trademark notices, 93 | Source Location references, modification notices (subsection 94 | 3.3(b)) and all notices that refer to this Licence and to the 95 | disclaimer of warranties that are included in the Covered 96 | Source. 97 | 98 | 1.11 'Licensee' or 'You' means any person exercising rights under 99 | this Licence. 100 | 101 | 1.12 'Licensor' means a natural or legal person who creates or 102 | modifies Covered Source. A person may be a Licensee and a 103 | Licensor at the same time. 104 | 105 | 1.13 'Convey' means to communicate to the public or distribute. 106 | 107 | 108 | 2 Applicability 109 | 110 | 2.1 This Licence governs the use, copying, modification, Conveying 111 | of Covered Source and Products, and the Making of Products. By 112 | exercising any right granted under this Licence, You irrevocably 113 | accept these terms and conditions. 114 | 115 | 2.2 This Licence is granted by the Licensor directly to You, and 116 | shall apply worldwide and without limitation in time. 117 | 118 | 2.3 You shall not attempt to restrict by contract or otherwise the 119 | rights granted under this Licence to other Licensees. 120 | 121 | 2.4 This Licence is not intended to restrict fair use, fair dealing, 122 | or any other similar right. 123 | 124 | 125 | 3 Copying, Modifying and Conveying Covered Source 126 | 127 | 3.1 You may copy and Convey verbatim copies of Covered Source, in 128 | any medium, provided You retain all Notices. 129 | 130 | 3.2 You may modify Covered Source, other than Notices, provided that 131 | You irrevocably undertake to make that modified Covered Source 132 | available from a Source Location should You Convey a Product in 133 | circumstances where the recipient does not otherwise receive a 134 | copy of the modified Covered Source. In each case subsection 3.3 135 | shall apply. 136 | 137 | You may only delete Notices if they are no longer applicable to 138 | the corresponding Covered Source as modified by You and You may 139 | add additional Notices applicable to Your modifications. 140 | Including Covered Source in a larger work is modifying the 141 | Covered Source, and the larger work becomes modified Covered 142 | Source. 143 | 144 | 3.3 You may Convey modified Covered Source (with the effect that You 145 | shall also become a Licensor) provided that You: 146 | 147 | a) retain Notices as required in subsection 3.2; 148 | 149 | b) add a Notice to the modified Covered Source stating that You 150 | have modified it, with the date and brief description of how 151 | You have modified it; 152 | 153 | c) add a Source Location Notice for the modified Covered Source 154 | if You Convey in circumstances where the recipient does not 155 | otherwise receive a copy of the modified Covered Source; and 156 | 157 | d) license the modified Covered Source under the terms and 158 | conditions of this Licence (or, as set out in subsection 159 | 8.3, a later version, if permitted by the licence of the 160 | original Covered Source). Such modified Covered Source must 161 | be licensed as a whole, but excluding Available Components 162 | contained in it, which remain licensed under their own 163 | applicable licences. 164 | 165 | 166 | 4 Making and Conveying Products 167 | 168 | You may Make Products, and/or Convey them, provided that You either 169 | provide each recipient with a copy of the Complete Source or ensure 170 | that each recipient is notified of the Source Location of the Complete 171 | Source. That Complete Source is Covered Source, and You must 172 | accordingly satisfy Your obligations set out in subsection 3.3. If 173 | specified in a Notice, the Product must visibly and securely display 174 | the Source Location on it or its packaging or documentation in the 175 | manner specified in that Notice. 176 | 177 | 178 | 5 Research and Development 179 | 180 | You may Convey Covered Source, modified Covered Source or Products to 181 | a legal entity carrying out development, testing or quality assurance 182 | work on Your behalf provided that the work is performed on terms which 183 | prevent the entity from both using the Source or Products for its own 184 | internal purposes and Conveying the Source or Products or any 185 | modifications to them to any person other than You. Any modifications 186 | made by the entity shall be deemed to be made by You pursuant to 187 | subsection 3.2. 188 | 189 | 190 | 6 DISCLAIMER AND LIABILITY 191 | 192 | 6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products 193 | are provided 'as is' and any express or implied warranties, 194 | including, but not limited to, implied warranties of 195 | merchantability, of satisfactory quality, non-infringement of 196 | third party rights, and fitness for a particular purpose or use 197 | are disclaimed in respect of any Source or Product to the 198 | maximum extent permitted by law. The Licensor makes no 199 | representation that any Source or Product does not or will not 200 | infringe any patent, copyright, trade secret or other 201 | proprietary right. The entire risk as to the use, quality, and 202 | performance of any Source or Product shall be with You and not 203 | the Licensor. This disclaimer of warranty is an essential part 204 | of this Licence and a condition for the grant of any rights 205 | granted under this Licence. 206 | 207 | 6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to 208 | the maximum extent permitted by law, have no liability for 209 | direct, indirect, special, incidental, consequential, exemplary, 210 | punitive or other damages of any character including, without 211 | limitation, procurement of substitute goods or services, loss of 212 | use, data or profits, or business interruption, however caused 213 | and on any theory of contract, warranty, tort (including 214 | negligence), product liability or otherwise, arising in any way 215 | in relation to the Covered Source, modified Covered Source 216 | and/or the Making or Conveyance of a Product, even if advised of 217 | the possibility of such damages, and You shall hold the 218 | Licensor(s) free and harmless from any liability, costs, 219 | damages, fees and expenses, including claims by third parties, 220 | in relation to such use. 221 | 222 | 223 | 7 Patents 224 | 225 | 7.1 Subject to the terms and conditions of this Licence, each 226 | Licensor hereby grants to You a perpetual, worldwide, 227 | non-exclusive, no-charge, royalty-free, irrevocable (except as 228 | stated in subsections 7.2 and 8.4) patent license to Make, have 229 | Made, use, offer to sell, sell, import, and otherwise transfer 230 | the Covered Source and Products, where such licence applies only 231 | to those patent claims licensable by such Licensor that are 232 | necessarily infringed by exercising rights under the Covered 233 | Source as Conveyed by that Licensor. 234 | 235 | 7.2 If You institute patent litigation against any entity (including 236 | a cross-claim or counterclaim in a lawsuit) alleging that the 237 | Covered Source or a Product constitutes direct or contributory 238 | patent infringement, or You seek any declaration that a patent 239 | licensed to You under this Licence is invalid or unenforceable 240 | then any rights granted to You under this Licence shall 241 | terminate as of the date such process is initiated. 242 | 243 | 244 | 8 General 245 | 246 | 8.1 If any provisions of this Licence are or subsequently become 247 | invalid or unenforceable for any reason, the remaining 248 | provisions shall remain effective. 249 | 250 | 8.2 You shall not use any of the name (including acronyms and 251 | abbreviations), image, or logo by which the Licensor or CERN is 252 | known, except where needed to comply with section 3, or where 253 | the use is otherwise allowed by law. Any such permitted use 254 | shall be factual and shall not be made so as to suggest any kind 255 | of endorsement or implication of involvement by the Licensor or 256 | its personnel. 257 | 258 | 8.3 CERN may publish updated versions and variants of this Licence 259 | which it considers to be in the spirit of this version, but may 260 | differ in detail to address new problems or concerns. New 261 | versions will be published with a unique version number and a 262 | variant identifier specifying the variant. If the Licensor has 263 | specified that a given variant applies to the Covered Source 264 | without specifying a version, You may treat that Covered Source 265 | as being released under any version of the CERN-OHL with that 266 | variant. If no variant is specified, the Covered Source shall be 267 | treated as being released under CERN-OHL-S. The Licensor may 268 | also specify that the Covered Source is subject to a specific 269 | version of the CERN-OHL or any later version in which case You 270 | may apply this or any later version of CERN-OHL with the same 271 | variant identifier published by CERN. 272 | 273 | 8.4 This Licence shall terminate with immediate effect if You fail 274 | to comply with any of its terms and conditions. 275 | 276 | 8.5 However, if You cease all breaches of this Licence, then Your 277 | Licence from any Licensor is reinstated unless such Licensor has 278 | terminated this Licence by giving You, while You remain in 279 | breach, a notice specifying the breach and requiring You to cure 280 | it within 30 days, and You have failed to come into compliance 281 | in all material respects by the end of the 30 day period. Should 282 | You repeat the breach after receipt of a cure notice and 283 | subsequent reinstatement, this Licence will terminate 284 | immediately and permanently. Section 6 shall continue to apply 285 | after any termination. 286 | 287 | 8.6 This Licence shall not be enforceable except by a Licensor 288 | acting as such, and third party beneficiary rights are 289 | specifically excluded. 290 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ava-core 2 | 3 | Contains RTL files for the AVA (AI Vector Accelerator) core to be attached to the modified CV32E40P CPU. 4 | 5 | -------------------------------------------------------------------------------- /rtl/accelerator_manifest.flist: -------------------------------------------------------------------------------- 1 | // Manifest for the AVA RTL model - Intended to be used by verilator 2 | // TODO: Relative paths based on environment variable 3 | ${AVA_RTL_DIR}/accelerator_pkg.sv 4 | ${AVA_RTL_DIR}/accelerator_top.sv 5 | ${AVA_RTL_DIR}/arith_stage.sv 6 | ${AVA_RTL_DIR}/bit_ext.sv 7 | ${AVA_RTL_DIR}/pe_32b.sv 8 | ${AVA_RTL_DIR}/processing_element.sv 9 | ${AVA_RTL_DIR}/relu_bound.sv 10 | ${AVA_RTL_DIR}/sat_unit.sv 11 | ${AVA_RTL_DIR}/scalar_replicate.sv 12 | ${AVA_RTL_DIR}/vector_csrs.sv 13 | ${AVA_RTL_DIR}/vector_decoder.sv 14 | ${AVA_RTL_DIR}/vector_registers.sv 15 | ${AVA_RTL_DIR}/vw_sign_ext.sv 16 | ${AVA_RTL_DIR}/vector_lsu.sv 17 | ${AVA_RTL_DIR}/temporary_reg.sv -------------------------------------------------------------------------------- /rtl/accelerator_pkg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | package accelerator_pkg; 17 | 18 | // Arithmetic operations inside PEs 19 | typedef enum logic [3:0] { 20 | PE_ARITH_ADD, 21 | PE_ARITH_SUB, 22 | PE_ARITH_LSHIFT, // left-shift 23 | PE_ARITH_MUL, 24 | PE_ARITH_MULADD, // multiply-add 25 | PE_ARITH_XOR, 26 | PE_ARITH_RSHIFT_LOG, // logical right-shift 27 | PE_ARITH_RSHIFT_AR, // arithmetic right-shift 28 | PE_ARITH_OR, 29 | PE_ARITH_AND 30 | } pe_arith_op_t; 31 | 32 | // PE output mode 33 | // PE_OP_MODE_RESULT: pass through arithmetic result 34 | // PE_OP_MODE_PASS_MAX: pass larger of operands A and B 35 | // PE_OP_MODE_PASS_MIN: pass smaller of operands A and B 36 | typedef enum logic [1:0] { 37 | PE_OP_MODE_RESULT, 38 | PE_OP_MODE_PASS_MAX, 39 | PE_OP_MODE_PASS_MIN 40 | } pe_output_mode_t; 41 | 42 | // PE saturation mode 43 | // PE_SAT_NONE: not saturation of output 44 | // PE_SAT: saturate to element width, keep decimal in same position 45 | // PE_SAT_UPPER: saturate to element width, keeping upper half of result only 46 | typedef enum logic [1:0] { 47 | PE_SAT_NONE, 48 | PE_SAT, 49 | PE_SAT_UPPER 50 | } pe_saturate_mode_t; 51 | 52 | // PE operand selection - select B operand for PE 53 | // PE_OPERAND_VS1: vector from vs1 vector register 54 | // PE_OPERAND_SCALAR: scalar passed from x-register 55 | // PE_OPERAND_IMMEDIATE: scalar immediate passed from instruction 56 | // PE_OPERAND_RIPPLE: configure PEs in ripple mode for reductions 57 | typedef enum logic [1:0] { 58 | PE_OPERAND_VS1, 59 | PE_OPERAND_SCALAR, 60 | PE_OPERAND_IMMEDIATE, 61 | PE_OPERAND_RIPPLE 62 | } pe_operand_t; 63 | 64 | // Source of data written back to vd in vector registers 65 | // VREG_WB_SRC_ARITH: data output from arithmetic stage 66 | // VREG_WB_SRC_MEMORY: data retrieved from RAM 67 | // VREG_WB_SRC_SCALAR: scalar value taken from scalar replicator 68 | typedef enum logic [1:0] { 69 | VREG_WB_SRC_ARITH, 70 | VREG_WB_SRC_MEMORY, 71 | VREG_WB_SRC_SCALAR 72 | } vreg_wb_src_t; 73 | 74 | // Source of address of selected vector register 75 | // VS3_ADDR_SRC_DECODE: address from decoder 76 | // VS3_ADDR_SRC_VLSU: address from vlsu / address unit 77 | typedef enum logic { 78 | VS3_ADDR_SRC_DECODE, 79 | VS3_ADDR_SRC_VLSU 80 | } vreg_addr_src_t; 81 | 82 | // Source of data returned to CPU by via apu_result 83 | // APU_RESULT_SRC_VL: return VL value. For vsetvli 84 | // APU_RESULT_SRC_VS2_0: return first element of vs2. For vmv.x.s 85 | typedef enum logic { 86 | APU_RESULT_SRC_VL, 87 | APU_RESULT_SRC_VS2_0 88 | } apu_result_src_t; 89 | 90 | // Major opcodes converted into 2 bits for the vector accelerator 91 | // parameter V_MAJOR_LOAD_FP = 2'b00; 92 | // parameter V_MAJOR_STORE_FP = 2'b01; 93 | // parameter V_MAJOR_OP_V = 2'b10; 94 | // parameter V_MAJOR_CUSTOM = 2'b11; 95 | parameter V_MAJOR_LOAD_FP = 7'b0000111; 96 | parameter V_MAJOR_STORE_FP = 7'b0100111; 97 | parameter V_MAJOR_OP_V = 7'b1010111; 98 | // parameter V_MAJOR_CUSTOM = 7'b; 99 | 100 | // funct3 bit fields from vector instructions (describe operand/source types) 101 | parameter V_OPIVV = 3'b000; 102 | parameter V_OPFVV = 3'b001; 103 | parameter V_OPMVV = 3'b010; 104 | parameter V_OPIVI = 3'b011; 105 | parameter V_OPIVX = 3'b100; 106 | parameter V_OPFVF = 3'b101; 107 | parameter V_OPMVX = 3'b110; 108 | parameter V_OPCFG = 3'b111; 109 | 110 | 111 | endpackage 112 | -------------------------------------------------------------------------------- /rtl/accelerator_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | // `include "defs.sv" 17 | import accelerator_pkg::*; 18 | 19 | module accelerator_top ( 20 | output logic [31:0] apu_result, 21 | output logic [4:0] apu_flags_o, 22 | output logic apu_gnt, 23 | output logic apu_rvalid, 24 | input wire clk, 25 | input wire n_reset, 26 | input wire apu_req, 27 | input wire [2:0][31:0] apu_operands_i, 28 | input wire [5:0] apu_op, 29 | input wire [14:0] apu_flags_i, 30 | output wire data_req_o, 31 | input wire data_gnt_i, 32 | input wire data_rvalid_i, 33 | output wire data_we_o, 34 | output wire [3:0] data_be_o, 35 | output wire [31:0] data_addr_o, 36 | output wire [31:0] data_wdata_o, 37 | input wire [31:0] data_rdata_i, 38 | output wire core_halt_o 39 | ); 40 | 41 | //////////////////////////////////////////////////////////////////////////////// 42 | // OUTPUT VARIABLE DECLARATIONS 43 | //////////////////////////////////////////////////////////////////////////////// 44 | 45 | // CSR OUTPUTS 46 | wire [4:0] vl; 47 | wire [1:0] vsew; 48 | wire [1:0] vlmul; 49 | 50 | // DECODER OUTPUTS 51 | wire [31:0] scalar_operand1; 52 | wire [31:0] scalar_operand2; 53 | wire [10:0] immediate_operand; 54 | wire [4:0] vs1_addr; 55 | wire [4:0] vs2_addr; 56 | logic [4:0] vd_addr; 57 | wire csr_write; 58 | wire preserve_vl; 59 | wire set_vl_max; 60 | wire [1:0] elements_to_write; 61 | wire [1:0] cycle_count; 62 | wire vec_reg_write; 63 | vreg_wb_src_t vd_data_src; 64 | vreg_addr_src_t vs3_addr_src; 65 | pe_arith_op_t pe_op; 66 | pe_saturate_mode_t saturate_mode; 67 | pe_output_mode_t output_mode; 68 | pe_operand_t operand_select; 69 | wire [1:0] pe_mul_us; 70 | wire [1:0] widening; 71 | apu_result_src_t apu_result_select; 72 | wire unsigned_immediate; 73 | wire wide_vs1; 74 | 75 | // VLSU OUTPUTS 76 | wire [127:0] vlsu_wdata; 77 | logic vec_reg_write_lsu; 78 | logic vlsu_done; 79 | logic [4:0] vl_next_comb; 80 | 81 | logic vlsu_en; 82 | logic vlsu_load; 83 | logic vlsu_store; 84 | logic vlsu_strided; 85 | logic vlsu_ready; 86 | 87 | // VECTOR REGISTERS OUTPUTS 88 | wire [127:0] vs1_data; 89 | wire [127:0] vs2_data; 90 | wire [127:0] vs3_data; 91 | 92 | // ARITHMETIC STAGE OUTPUTS 93 | wire [127:0] arith_output; 94 | wire [127:0] replicated_scalar; 95 | 96 | //////////////////////////////////////////////////////////////////////////////// 97 | // MODULE INSTANTIATION 98 | //////////////////////////////////////////////////////////////////////////////// 99 | 100 | wire [31:0] apu_operands [2:0]; 101 | assign apu_operands[0] = apu_operands_i[0]; 102 | assign apu_operands[1] = apu_operands_i[1]; 103 | assign apu_operands[2] = apu_operands_i[2]; 104 | 105 | //////////////////////////////////////// 106 | // CSRs 107 | vector_csrs vcsrs0 ( 108 | .vl(vl), 109 | .vsew(vsew), 110 | .vlmul(vlmul), 111 | .vl_next_comb(vl_next_comb), 112 | .clk(clk), 113 | .n_reset(n_reset), 114 | .avl_in(scalar_operand1), 115 | .vtype_in(immediate_operand[4:0]), 116 | .write(csr_write), 117 | .saturate_flag(1'b0), 118 | .preserve_vl(preserve_vl), 119 | .set_vl_max(set_vl_max) 120 | ); 121 | 122 | //////////////////////////////////////// 123 | // DECODER 124 | vector_decoder vdec0 ( 125 | .apu_rvalid(apu_rvalid), 126 | .apu_gnt(apu_gnt), 127 | .scalar_operand1(scalar_operand1), 128 | .scalar_operand2(scalar_operand2), 129 | .immediate_operand(immediate_operand), 130 | .vs1_addr(vs1_addr), 131 | .vs2_addr(vs2_addr), 132 | .vd_addr(vd_addr), 133 | .csr_write(csr_write), 134 | .preserve_vl(preserve_vl), 135 | .set_vl_max(set_vl_max), 136 | .elements_to_write(elements_to_write), 137 | .cycle_count(cycle_count), 138 | .vec_reg_write(vec_reg_write), 139 | .vd_data_src(vd_data_src), 140 | .vs3_addr_src(vs3_addr_src), 141 | .pe_op(pe_op), 142 | .saturate_mode(saturate_mode), 143 | .output_mode(output_mode), 144 | .operand_select(operand_select), 145 | .pe_mul_us(pe_mul_us), 146 | .widening(widening), 147 | .apu_result_select(apu_result_select), 148 | .unsigned_immediate(unsigned_immediate), 149 | .wide_vs1(wide_vs1), 150 | .clk(clk), 151 | .n_reset(n_reset), 152 | .apu_req(apu_req), 153 | .apu_operands(apu_operands), 154 | .apu_op(apu_op), 155 | .apu_flags_i(apu_flags_i), 156 | .vl(vl), 157 | .vsew(vsew), 158 | .vlsu_en_o(vlsu_en), 159 | .vlsu_load_o(vlsu_load), 160 | .vlsu_store_o(vlsu_store), 161 | .vlsu_strided_o(vlsu_strided), 162 | .vlsu_ready_i(vlsu_ready), 163 | .vlsu_done_i(vlsu_done), 164 | .core_halt_o(core_halt_o) 165 | ); 166 | 167 | //////////////////////////////////////// 168 | // VECTOR REGISTERS 169 | logic [127:0] vd_data; 170 | logic [4:0] vs3_addr, vs3_addr_vlsu; 171 | always_comb begin 172 | case (vd_data_src) 173 | VREG_WB_SRC_MEMORY: 174 | vd_data = vlsu_wdata; 175 | VREG_WB_SRC_ARITH: 176 | vd_data = arith_output; 177 | VREG_WB_SRC_SCALAR: 178 | vd_data = replicated_scalar; 179 | default: 180 | vd_data = '0; 181 | endcase 182 | 183 | case (vs3_addr_src) 184 | VS3_ADDR_SRC_DECODE: 185 | vs3_addr = vd_addr; 186 | VS3_ADDR_SRC_VLSU: 187 | vs3_addr = vs3_addr_vlsu; 188 | default: 189 | vs3_addr = '0; 190 | endcase 191 | end 192 | 193 | 194 | vector_registers vreg0 ( 195 | .vs1_data(vs1_data), 196 | .vs2_data(vs2_data), 197 | .vs3_data(vs3_data), 198 | .vd_data(vd_data), 199 | .vs1_addr(vs1_addr), 200 | .vs2_addr(vs2_addr), 201 | .vd_addr(vs3_addr), 202 | .vsew(vsew), 203 | .vlmul(vlmul), 204 | .elements_to_write(elements_to_write), 205 | .clk(clk), 206 | .n_reset(n_reset), 207 | .write(vec_reg_write | vec_reg_write_lsu ), 208 | .widening_op(widening[0]), 209 | .wide_vs1(wide_vs1), 210 | .load_operation(vlsu_load) 211 | ); 212 | 213 | //////////////////////////////////////// 214 | // PEs CONTAINED IN ARITHMETIC STAGE WRAPPER 215 | arith_stage arith_stage0 ( 216 | .arith_output(arith_output), 217 | .replicated_scalar(replicated_scalar), 218 | .clk(clk), 219 | .n_reset(n_reset), 220 | .vs1_data(vs1_data), 221 | .vs2_data(vs2_data), 222 | .vs3_data(vs3_data), 223 | .scalar_operand(scalar_operand1), 224 | .imm_operand(immediate_operand[4:0]), 225 | .elements_to_write(elements_to_write), 226 | .cycle_count(cycle_count), 227 | .op(pe_op), 228 | .saturate_mode(saturate_mode), 229 | .output_mode(output_mode), 230 | .operand_select(operand_select), 231 | .widening(widening), 232 | .mul_us(pe_mul_us), 233 | .unsigned_immediate(unsigned_immediate), 234 | .wide_vs1(wide_vs1), 235 | .vl(vl), 236 | .vsew(vsew) 237 | ); 238 | 239 | //////////////////////////////////////// 240 | // VLSU 241 | vector_lsu vlsu0 ( 242 | .clk(clk), 243 | .n_reset(n_reset), 244 | 245 | .vl_i(vl), 246 | .vsew_i(vsew), 247 | .vlmul_i(vlmul), 248 | 249 | .vlsu_en_i(vlsu_en), 250 | .vlsu_load_i(vlsu_load), 251 | .vlsu_store_i(vlsu_store), 252 | .vlsu_strided_i(vlsu_strided), 253 | .vlsu_ready_o(vlsu_ready), 254 | .vlsu_done_o(vlsu_done), 255 | 256 | .data_req_o(data_req_o), 257 | .data_gnt_i(data_gnt_i), 258 | .data_rvalid_i(data_rvalid_i), 259 | .data_addr_o(data_addr_o), 260 | .data_we_o(data_we_o), 261 | .data_be_o(data_be_o), 262 | .data_rdata_i(data_rdata_i), 263 | .data_wdata_o(data_wdata_o), 264 | 265 | .cycle_count_i(cycle_count), 266 | 267 | .op0_data_i(scalar_operand1), 268 | .op1_data_i(scalar_operand2), 269 | 270 | .vs_wdata_o(vlsu_wdata), 271 | .vs_rdata_i(vs3_data), 272 | .vr_addr_i(vd_addr), 273 | .vs3_addr_o(vs3_addr_vlsu), 274 | .vr_we_o(vec_reg_write_lsu) 275 | ); 276 | 277 | //////////////////////////////////////////////////////////////////////////////// 278 | // RESULT SELECTION - what value to return to CPU 279 | //////////////////////////////////////////////////////////////////////////////// 280 | logic [31:0] reg_apu_result; 281 | assign apu_flags_o = '0; 282 | assign apu_result = reg_apu_result; 283 | 284 | // Updated VL is arriving two cycles too late 285 | always_comb begin 286 | reg_apu_result = '0; 287 | case (apu_result_select) 288 | APU_RESULT_SRC_VL: 289 | reg_apu_result = {'0, vl_next_comb}; 290 | APU_RESULT_SRC_VS2_0: 291 | case (vsew) 292 | 2'd0: // 8b 293 | reg_apu_result = { {24{vs2_data[7]}}, vs2_data[7:0] }; 294 | 2'd1: // 16b 295 | reg_apu_result = { {16{vs2_data[15]}}, vs2_data[15:0] }; 296 | 2'd2:// 32b 297 | reg_apu_result = vs2_data[31:0]; 298 | endcase 299 | endcase 300 | end 301 | 302 | 303 | endmodule 304 | -------------------------------------------------------------------------------- /rtl/address_unit.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | /* verilator lint_off ALWCOMBORDER */ 16 | module address_unit( 17 | input logic clk_i, n_rst_i, 18 | input logic [31:0] base_addr_i, 19 | input logic [31:0] stride_i, 20 | input logic [4:0] vl_i, 21 | input logic [1:0] vsew_i, 22 | input logic au_start_i, 23 | input logic au_next_i, 24 | output logic [3:0] au_be_o, 25 | output logic [6:0] au_bc_o, 26 | output logic [31:0] au_addr_o, 27 | output logic [6:0] vd_offset_o, 28 | output logic au_valid_o, 29 | output logic au_ready_o, 30 | output logic au_final_o); 31 | 32 | logic [1:0] ib_select; // Low 2 bits of initial address 33 | logic [3:0] be_gen; 34 | 35 | logic [31:0] next_el_pre, next_el_addr; 36 | logic [31:0] cycle_addr; 37 | logic [6:0] cycle_bytes; 38 | 39 | typedef enum {RESET, FIRST, CYCLE, WAIT, FINAL} be_state; 40 | be_state current_state, next_state; 41 | 42 | logic signed [6:0] byte_track, byte_track_next; 43 | logic cycle_load; 44 | 45 | assign vd_offset_o = (vl_i << vsew_i) - byte_track; 46 | 47 | always_comb begin 48 | if(au_valid_o) begin // Make sure that all our addresses are word aligned 49 | au_addr_o = {cycle_addr[31:2], 2'd0}; 50 | au_be_o = be_gen; 51 | end else begin 52 | au_addr_o = 32'd0; 53 | au_be_o = 4'b0000; 54 | end 55 | end 56 | 57 | always_comb begin 58 | if(au_start_i) 59 | byte_track_next = {2'd0, vl_i} << vsew_i; // Bytes dependent on element size 60 | else if(current_state != CYCLE) 61 | byte_track_next = byte_track; 62 | else 63 | byte_track_next = (byte_track >= cycle_bytes) ? (byte_track - cycle_bytes) : 7'd0; 64 | end 65 | 66 | always_ff @(posedge clk_i, negedge n_rst_i) begin 67 | if(~n_rst_i) 68 | byte_track <= 7'd0; 69 | else 70 | byte_track <= byte_track_next; 71 | end 72 | 73 | always_ff @(posedge clk_i, negedge n_rst_i) begin 74 | if(~n_rst_i) 75 | cycle_addr <= 32'd0; 76 | else if(au_start_i) 77 | cycle_addr <= base_addr_i; 78 | else if(current_state != CYCLE) 79 | cycle_addr <= cycle_addr; 80 | else 81 | cycle_addr <= next_el_addr; 82 | end 83 | 84 | always_ff @(posedge clk_i, negedge n_rst_i) begin 85 | if(~n_rst_i) 86 | current_state <= RESET; 87 | else 88 | current_state <= next_state; 89 | end 90 | 91 | always_comb begin 92 | be_gen = 4'b0000; 93 | case(vsew_i) 94 | 2'b00 : begin // 8 Bit 95 | ib_select = cycle_addr[1:0]; 96 | 97 | if(stride_i > 1) begin 98 | be_gen[ib_select] = 1'b1; 99 | 100 | // Where is our next byte? 101 | next_el_pre = cycle_addr + stride_i; 102 | if(next_el_pre[31:2] == cycle_addr[31:2] && byte_track > 1) begin 103 | be_gen[next_el_pre[1:0]] = 1'b1; 104 | next_el_addr = next_el_pre + stride_i; // Stride by second element 105 | end else begin 106 | next_el_addr = next_el_pre; 107 | end 108 | 109 | // Calculate the number of bytes for cycle 110 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 111 | end else if(stride_i == 1) begin 112 | be_gen[0] = (ib_select == 0) ? 1 : 0; 113 | be_gen[1] = (ib_select == 1 || byte_track > 1) ? 1'b1 : 1'b0; 114 | be_gen[2] = (ib_select == 2 || byte_track > 2) ? 1'b1 : 1'b0; 115 | be_gen[3] = (ib_select == 3 || byte_track > 3) ? 1'b1 : 1'b0; 116 | next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4; 117 | 118 | // Calculate the number of bytes for cycle 119 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 120 | end else if(stride_i == 0) begin 121 | be_gen[ib_select] = 1'b1; 122 | cycle_bytes = {2'b0, vl_i}; // Read all bytes in 1 cycle 123 | end 124 | end 125 | 2'b01 : begin // 16 Bit 126 | ib_select = {cycle_addr[1], 1'b0}; // Force alignment byte 0 or 2 127 | 128 | if(stride_i > 2) begin // Always 1 element 129 | // Always set 2 bytes 130 | be_gen[ib_select] = 1'b1; 131 | be_gen[ib_select+1] = 1'b1; 132 | next_el_addr = {cycle_addr[31:1], 1'b0} + {stride_i[31:1], 1'b0}; 133 | 134 | // Calculate the number of bytes for cycle 135 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 136 | end else if (stride_i == 2) begin // Up to 2 Elements 137 | be_gen[1:0] = (ib_select == 0) ? 2'b11 : 2'b00; 138 | be_gen[3:2] = (ib_select == 2 || byte_track > 2) ? 2'b11 : 2'b00; 139 | next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4; 140 | 141 | // Calculate the number of bytes for cycle 142 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 143 | end else if (stride_i == 0) begin 144 | be_gen[ib_select] = 1'b1; 145 | be_gen[ib_select+1] = 1'b1; 146 | cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 cycle 147 | end 148 | end 149 | 2'b10 : begin // 32 Bit 150 | ib_select = 2'd0; // Force alignment to byte 0 151 | 152 | if(stride_i >= 4) begin // Always 1 element 153 | be_gen = 4'b1111; 154 | next_el_addr = {cycle_addr[31:2], 2'b0} + {stride_i[31:2], 2'b0}; // stride_i is always a multiple of 4 155 | 156 | // Calculate the number of bytes for cycle 157 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 158 | end else if(stride_i == 0) begin 159 | be_gen = 4'b1111; 160 | cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 cycle 161 | end 162 | end 163 | default : $error("Invalid VSEW"); 164 | endcase 165 | end 166 | 167 | always_comb begin 168 | cycle_load = 1'b0; 169 | au_valid_o = 1'b0; 170 | au_ready_o = 1'b0; 171 | au_final_o = 1'b0; 172 | case(current_state) 173 | RESET: begin 174 | au_ready_o = 1'b1; 175 | if(au_start_i) 176 | next_state = FIRST; 177 | else 178 | next_state = RESET; 179 | end 180 | FIRST: begin 181 | au_valid_o = 1'b1; 182 | if(stride_i != 0) begin 183 | next_state = WAIT; 184 | end else begin 185 | next_state = RESET; 186 | end 187 | end 188 | CYCLE: begin 189 | au_valid_o = 1'b1; 190 | if(byte_track_next == 0) begin 191 | next_state = WAIT; 192 | end else begin 193 | cycle_load = 1'b1; 194 | next_state = WAIT; 195 | end 196 | end 197 | WAIT: begin 198 | if(au_next_i) 199 | next_state = CYCLE; 200 | else if(byte_track_next == 0) 201 | next_state = FINAL; 202 | else 203 | next_state = WAIT; 204 | end 205 | FINAL: begin 206 | au_final_o = 1'b1; 207 | next_state = RESET; 208 | end 209 | endcase 210 | end 211 | 212 | initial begin 213 | $dumpfile("test.vcd"); 214 | $dumpvars; 215 | $display(" Model running...\n"); 216 | end 217 | endmodule 218 | /* verilator lint_on ALWCOMBORDER */ 219 | -------------------------------------------------------------------------------- /rtl/arith_stage.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // Module instance to contain the PEs and supporting logic such as input/output 16 | // selection logic. This is just to tidy up the top-level a bit. 17 | 18 | import accelerator_pkg::*; 19 | 20 | module arith_stage ( 21 | output logic [127:0] arith_output, 22 | output logic [127:0] replicated_scalar, // Want this output for vmv.v.i 23 | input wire clk, 24 | input wire n_reset, 25 | input wire [127:0] vs1_data, 26 | input wire [127:0] vs2_data, 27 | input wire [127:0] vs3_data, 28 | input wire [31:0] scalar_operand, 29 | input wire [4:0] imm_operand, 30 | input wire [1:0] elements_to_write, 31 | input wire [1:0] cycle_count, 32 | input pe_arith_op_t op, 33 | input pe_saturate_mode_t saturate_mode, 34 | input pe_output_mode_t output_mode, 35 | input pe_operand_t operand_select, 36 | input wire [1:0] widening, 37 | input wire [1:0] mul_us, 38 | input wire unsigned_immediate, 39 | input wire wide_vs1, 40 | input wire [4:0] vl, 41 | input wire [1:0] vsew 42 | ); 43 | 44 | logic [31:0] reduction_intermediate_reg; 45 | 46 | // logic [127:0] replicated_scalar; 47 | 48 | wire [31:0] pe0_out; 49 | wire [31:0] pe1_out; 50 | wire [31:0] pe2_out; 51 | wire [31:0] pe3_out; 52 | 53 | logic [31:0] pe0_b_data; 54 | logic [31:0] pe1_b_data; 55 | logic [31:0] pe2_b_data; 56 | logic [31:0] pe3_b_data; 57 | 58 | logic [31:0] scalar_to_replicate; 59 | 60 | pe_32b pe0 ( 61 | .out(pe0_out), 62 | .a(vs2_data[31:0]), 63 | .b(pe0_b_data), 64 | .c(vs3_data[31:0]), 65 | .op(op), 66 | .vsew(vsew), 67 | .widening(widening), 68 | .mul_us(mul_us), 69 | .saturate_mode(saturate_mode), 70 | .output_mode(output_mode), 71 | .wide_b(wide_vs1) 72 | ); 73 | 74 | pe_32b pe1 ( 75 | .out(pe1_out), 76 | .a(vs2_data[63:32]), 77 | .b(pe1_b_data), 78 | .c(vs3_data[63:32]), 79 | .op(op), 80 | .vsew(vsew), 81 | .widening(widening), 82 | .mul_us(mul_us), 83 | .saturate_mode(saturate_mode), 84 | .output_mode(output_mode), 85 | .wide_b(wide_vs1) 86 | ); 87 | 88 | pe_32b pe2 ( 89 | .out(pe2_out), 90 | .a(vs2_data[95:64]), 91 | .b(pe2_b_data), 92 | .c(vs3_data[95:64]), 93 | .op(op), 94 | .vsew(vsew), 95 | .widening(widening), 96 | .mul_us(mul_us), 97 | .saturate_mode(saturate_mode), 98 | .output_mode(output_mode), 99 | .wide_b(wide_vs1) 100 | ); 101 | 102 | pe_32b pe3 ( 103 | .out(pe3_out), 104 | .a(vs2_data[127:96]), 105 | .b(pe3_b_data), 106 | .c(vs3_data[127:96]), 107 | .op(op), 108 | .vsew(vsew), 109 | .widening(widening), 110 | .mul_us(mul_us), 111 | .saturate_mode(saturate_mode), 112 | .output_mode(output_mode), 113 | .wide_b(wide_vs1) 114 | ); 115 | 116 | scalar_replicate scalar_rep0 ( 117 | .replicated_out(replicated_scalar), 118 | .scalar_in(scalar_to_replicate), 119 | .vsew(vsew), 120 | .us(1'b0) 121 | ); 122 | 123 | // Update the intermediate register used for reduction operations every cycle 124 | always_ff @(posedge clk, negedge n_reset) 125 | if (~n_reset) 126 | reduction_intermediate_reg <= '0; 127 | else 128 | reduction_intermediate_reg <= pe3_out; 129 | 130 | //////////////////////////////////////////////////////////////////////////////// 131 | // PE INPUT OPERAND SELECTION 132 | //////////////////////////////////////////////////////////////////////////////// 133 | always_comb 134 | begin 135 | scalar_to_replicate = scalar_operand; 136 | 137 | case (operand_select) 138 | PE_OPERAND_VS1: 139 | begin 140 | pe0_b_data = vs1_data[31:0]; 141 | pe1_b_data = vs1_data[63:32]; 142 | pe2_b_data = vs1_data[95:64]; 143 | pe3_b_data = vs1_data[127:96]; 144 | end 145 | PE_OPERAND_SCALAR: 146 | begin 147 | pe0_b_data = replicated_scalar[31:0]; 148 | pe1_b_data = replicated_scalar[63:32]; 149 | pe2_b_data = replicated_scalar[95:64]; 150 | pe3_b_data = replicated_scalar[127:96]; 151 | end 152 | PE_OPERAND_IMMEDIATE: 153 | begin 154 | if (unsigned_immediate) 155 | begin 156 | pe0_b_data = {'0, imm_operand[4:0]}; 157 | pe1_b_data = {'0, imm_operand[4:0]}; 158 | pe2_b_data = {'0, imm_operand[4:0]}; 159 | pe3_b_data = {'0, imm_operand[4:0]}; 160 | end 161 | else 162 | begin 163 | pe0_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]}; 164 | pe1_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]}; 165 | pe2_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]}; 166 | pe3_b_data = {{27{imm_operand[4]}}, imm_operand[4:0]}; 167 | end 168 | // This line handles a special case - the scalar replicate logic is 169 | // used for vmv.v.i instructions but the PE is not used. In this 170 | // case the immediate operand needs to be replicated and returned. 171 | scalar_to_replicate = {{27{imm_operand[4]}}, imm_operand[4:0]}; 172 | end 173 | PE_OPERAND_RIPPLE: 174 | begin 175 | // For first cycle of reduction operation want to look at vs1[0]. 176 | // For later cycles need the intermediate value from last cycle. 177 | if (cycle_count == 2'd0) 178 | pe0_b_data = vs1_data[31:0]; 179 | else 180 | pe0_b_data = reduction_intermediate_reg; 181 | pe1_b_data = pe0_out; 182 | pe2_b_data = pe1_out; 183 | pe3_b_data = pe2_out; 184 | end 185 | endcase 186 | end 187 | 188 | //////////////////////////////////////////////////////////////////////////////// 189 | // PE OUTPUT SELECTION 190 | //////////////////////////////////////////////////////////////////////////////// 191 | always_comb 192 | begin 193 | // For reduction operations the output comes from a single PE (the last in 194 | // the chain), but which PE is last depends on VL. 195 | if (operand_select == PE_OPERAND_RIPPLE) 196 | case (vl[1:0]) 197 | 2'd0: 198 | // Perhaps counterintuitively, if vl[1:0] is zero that means all 199 | // four elements are being written so want the last PE. 200 | arith_output = {'0, pe3_out}; 201 | 2'd1: 202 | arith_output = {'0, pe0_out}; 203 | 2'd2: 204 | arith_output = {'0, pe1_out}; 205 | 2'd3: 206 | arith_output = {'0, pe2_out}; 207 | default: 208 | arith_output = {'0, pe3_out}; 209 | endcase 210 | else 211 | arith_output = {pe3_out, pe2_out, pe1_out, pe0_out}; 212 | end 213 | 214 | 215 | endmodule 216 | -------------------------------------------------------------------------------- /rtl/bit_ext.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // W_IN must be smaller than W_OUT 16 | module bit_ext #(parameter W_IN = 8, parameter W_OUT = 12) 17 | (input logic signed [W_IN-1:0] a_in, 18 | output logic signed [W_OUT-1:0] a_out); 19 | 20 | assign a_out = {{(W_OUT-W_IN){a_in[W_IN-1]}}, a_in}; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /rtl/gtkw/bit_ext_td.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI 3 | [*] Fri Oct 23 23:13:59 2020 4 | [*] 5 | [dumpfile] "/home/bt/open-ai-gdp/rtl/vcd/bit_ext.vcd" 6 | [dumpfile_mtime] "Fri Oct 23 23:10:08 2020" 7 | [dumpfile_size] 14307 8 | [savefile] "/home/bt/open-ai-gdp/rtl/gtkw/bit_ext_td.gtkw" 9 | [timestart] 56470 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-11.000000 2 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb_bit_ext. 14 | [sst_width] 212 15 | [signals_width] 118 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 148 18 | @29 19 | tb_bit_ext.bit_ext.a_in[7:0] 20 | @28 21 | tb_bit_ext.bit_ext.a_out[11:0] 22 | [pattern_trace] 1 23 | [pattern_trace] 0 24 | -------------------------------------------------------------------------------- /rtl/gtkw/relu_bound_td.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI 3 | [*] Fri Oct 23 22:30:26 2020 4 | [*] 5 | [dumpfile] "/home/bt/open-ai-gdp/rtl/relu_bound.vcd" 6 | [dumpfile_mtime] "Fri Oct 23 22:26:48 2020" 7 | [dumpfile_size] 9812 8 | [savefile] "/home/bt/open-ai-gdp/rtl/relu_bound_td.gtkw" 9 | [timestart] 0 10 | [size] 2560 1415 11 | [pos] -771 -400 12 | *-18.000000 951000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb_relu_bound. 14 | [sst_width] 212 15 | [signals_width] 86 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 432 18 | @40000420 19 | [fpshift_count] 4 20 | tb_relu_bound.rb.a[7:0] 21 | @40008420 22 | [fpshift_count] 4 23 | tb_relu_bound.rb.ar[7:0] 24 | @20000 25 | - 26 | - 27 | @20001 28 | - 29 | @20000 30 | - 31 | - 32 | [pattern_trace] 1 33 | [pattern_trace] 0 34 | -------------------------------------------------------------------------------- /rtl/gtkw/sat_unit_td.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI 3 | [*] Fri Oct 23 22:56:00 2020 4 | [*] 5 | [dumpfile] "/home/bt/open-ai-gdp/rtl/sat_unit.vcd" 6 | [dumpfile_mtime] "Fri Oct 23 22:53:59 2020" 7 | [dumpfile_size] 24015 8 | [savefile] "/home/bt/open-ai-gdp/rtl/sat_unit_td.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] 115 -143 12 | *-18.000000 512000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] tb_sat_unit. 14 | [sst_width] 212 15 | [signals_width] 110 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 148 18 | @8420 19 | tb_sat_unit.satu.a_in[12:0] 20 | @20000 21 | - 22 | - 23 | - 24 | - 25 | - 26 | @8421 27 | tb_sat_unit.satu.a_out[7:0] 28 | @20000 29 | - 30 | - 31 | [pattern_trace] 1 32 | [pattern_trace] 0 33 | -------------------------------------------------------------------------------- /rtl/mapping_unit.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | module mapping_unit 16 | (input logic [127:0] arith_format_o, 17 | output logic [31:0] memory_format_i, 18 | input logic [1:0] sew_i, 19 | input logic [1:0] reg_select); 20 | 21 | 22 | 23 | 24 | 25 | vd_wr_data0 = '{ 26 | vd_data[103:96], 27 | vd_data[71:64], 28 | vd_data[39:32], 29 | vd_data[7:0] 30 | }; 31 | 2'd1: // 16b 32 | begin 33 | vd_wr_data1 = { 34 | vd_data[111:96], 35 | vd_data[79:64] 36 | }; 37 | vd_wr_data0 = { 38 | vd_data[47:32], 39 | vd_data[15:0] 40 | }; 41 | end 42 | 2'd2: // 32b 43 | begin 44 | vd_wr_data3 = vd_data[127:96]; 45 | vd_wr_data2 = vd_data[95:64]; 46 | vd_wr_data1 = vd_data[63:32]; 47 | vd_wr_data0 = vd_data[31:0];*/ 48 | endmodule 49 | -------------------------------------------------------------------------------- /rtl/obj/tb_bit_ext.vvp: -------------------------------------------------------------------------------- 1 | #! /opt/iverilog/bin/vvp -v 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 11; 5 | :vpi_module "/opt/iverilog/lib/ivl/system.vpi"; 6 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/opt/iverilog/lib/ivl/v2005_math.vpi"; 9 | :vpi_module "/opt/iverilog/lib/ivl/va_math.vpi"; 10 | :vpi_module "/opt/iverilog/lib/ivl/v2009.vpi"; 11 | S_0x5610f4fa38b0 .scope package, "$unit" "$unit" 2 1; 12 | .timescale 0 0; 13 | S_0x5610f4fa3a40 .scope module, "tb_bit_ext" "tb_bit_ext" 3 5; 14 | .timescale -9 -11; 15 | v0x5610f4fb5650_0 .var/s "in", 7 0; 16 | v0x5610f4fb5740_0 .net/s "out", 11 0, L_0x5610f4fb5a50; 1 drivers 17 | S_0x5610f4f92090 .scope module, "bit_ext" "bit_ext" 3 9, 4 2 0, S_0x5610f4fa3a40; 18 | .timescale -9 -11; 19 | .port_info 0 /INPUT 8 "a_in"; 20 | .port_info 1 /OUTPUT 12 "a_out"; 21 | P_0x5610f4f8fc20 .param/l "W_IN" 0 4 2, +C4<00000000000000000000000000001000>; 22 | P_0x5610f4f8fc60 .param/l "W_OUT" 0 4 2, +C4<00000000000000000000000000001100>; 23 | v0x5610f4fa4320_0 .net *"_ivl_1", 0 0, L_0x5610f4fb5810; 1 drivers 24 | v0x5610f4fb5340_0 .net *"_ivl_2", 3 0, L_0x5610f4fb5930; 1 drivers 25 | v0x5610f4fb5420_0 .net/s "a_in", 7 0, v0x5610f4fb5650_0; 1 drivers 26 | v0x5610f4fb5510_0 .net/s "a_out", 11 0, L_0x5610f4fb5a50; alias, 1 drivers 27 | L_0x5610f4fb5810 .part v0x5610f4fb5650_0, 7, 1; 28 | L_0x5610f4fb5930 .concat [ 1 1 1 1], L_0x5610f4fb5810, L_0x5610f4fb5810, L_0x5610f4fb5810, L_0x5610f4fb5810; 29 | L_0x5610f4fb5a50 .concat [ 8 4 0 0], v0x5610f4fb5650_0, L_0x5610f4fb5930; 30 | .scope S_0x5610f4fa3a40; 31 | T_0 ; 32 | %vpi_call/w 3 13 "$dumpfile", "bit_ext.vcd" {0 0 0}; 33 | %vpi_call/w 3 14 "$dumpvars" {0 0 0}; 34 | %pushi/vec4 128, 0, 8; 35 | %store/vec4 v0x5610f4fb5650_0, 0, 8; 36 | T_0.0 ; 37 | %load/vec4 v0x5610f4fb5650_0; 38 | %pad/s 32; 39 | %cmpi/s 127, 0, 32; 40 | %jmp/0xz T_0.1, 5; 41 | %delay 100, 0; 42 | %vpi_call/w 3 18 "$display", "%d, %d", v0x5610f4fb5650_0, v0x5610f4fb5740_0 {0 0 0}; 43 | ; show_stmt_assign_vector: Get l-value for compressed += operand 44 | %load/vec4 v0x5610f4fb5650_0; 45 | %pushi/vec4 1, 0, 8; 46 | %add; 47 | %store/vec4 v0x5610f4fb5650_0, 0, 8; 48 | %jmp T_0.0; 49 | T_0.1 ; 50 | %vpi_call/w 3 21 "$finish" {0 0 0}; 51 | %end; 52 | .thread T_0; 53 | # The file index is used to find the file name in the following table. 54 | :file_names 5; 55 | "N/A"; 56 | ""; 57 | "-"; 58 | "tb_bit_ext.sv"; 59 | "./bit_ext.sv"; 60 | -------------------------------------------------------------------------------- /rtl/obj/tb_relu_bound.vvp: -------------------------------------------------------------------------------- 1 | #! /opt/iverilog/bin/vvp -v 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 11; 5 | :vpi_module "/opt/iverilog/lib/ivl/system.vpi"; 6 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/opt/iverilog/lib/ivl/v2005_math.vpi"; 9 | :vpi_module "/opt/iverilog/lib/ivl/va_math.vpi"; 10 | :vpi_module "/opt/iverilog/lib/ivl/v2009.vpi"; 11 | S_0x56049b449510 .scope package, "$unit" "$unit" 2 1; 12 | .timescale 0 0; 13 | S_0x56049b4496a0 .scope module, "tb_relu_bound" "tb_relu_bound" 3 5; 14 | .timescale -9 -11; 15 | v0x56049b45b470_0 .var/s "in", 7 0; 16 | v0x56049b45b560_0 .net/s "out", 7 0, v0x56049b434960_0; 1 drivers 17 | S_0x56049b437330 .scope module, "rb" "relu_bound" 3 8, 4 1 0, S_0x56049b4496a0; 18 | .timescale -9 -11; 19 | .port_info 0 /INPUT 8 "a"; 20 | .port_info 1 /OUTPUT 8 "ar"; 21 | P_0x56049b4350a0 .param/l "N" 0 4 2, +C4<000000000000000000000000000001100000>; 22 | P_0x56049b4350e0 .param/l "W" 0 4 2, +C4<00000000000000000000000000001000>; 23 | v0x56049b434600_0 .net/s "a", 7 0, v0x56049b45b470_0; 1 drivers 24 | v0x56049b434960_0 .var/s "ar", 7 0; 25 | v0x56049b45b320_0 .var/s "zero_signed", 7 0; 26 | E_0x56049b40f270 .event edge, v0x56049b434600_0, v0x56049b45b320_0; 27 | .scope S_0x56049b437330; 28 | T_0 ; 29 | %pushi/vec4 0, 0, 8; 30 | %store/vec4 v0x56049b45b320_0, 0, 8; 31 | %end; 32 | .thread T_0, $init; 33 | .scope S_0x56049b437330; 34 | T_1 ; 35 | Ewait_0 .event/or E_0x56049b40f270, E_0x0; 36 | %wait Ewait_0; 37 | %load/vec4 v0x56049b434600_0; 38 | %load/vec4 v0x56049b45b320_0; 39 | %cmp/s; 40 | %jmp/0xz T_1.0, 5; 41 | %pushi/vec4 0, 0, 8; 42 | %store/vec4 v0x56049b434960_0, 0, 8; 43 | %jmp T_1.1; 44 | T_1.0 ; 45 | %load/vec4 v0x56049b434600_0; 46 | %pad/s 36; 47 | %cmpi/s 96, 0, 36; 48 | %flag_or 5, 4; GT is !LE 49 | %flag_inv 5; 50 | %jmp/0xz T_1.2, 5; 51 | %pushi/vec4 96, 0, 8; 52 | %store/vec4 v0x56049b434960_0, 0, 8; 53 | %jmp T_1.3; 54 | T_1.2 ; 55 | %load/vec4 v0x56049b434600_0; 56 | %store/vec4 v0x56049b434960_0, 0, 8; 57 | T_1.3 ; 58 | T_1.1 ; 59 | %jmp T_1; 60 | .thread T_1, $push; 61 | .scope S_0x56049b4496a0; 62 | T_2 ; 63 | %vpi_call/w 3 14 "$dumpfile", "relu_bound.vcd" {0 0 0}; 64 | %vpi_call/w 3 15 "$dumpvars" {0 0 0}; 65 | %pushi/vec4 128, 0, 8; 66 | %store/vec4 v0x56049b45b470_0, 0, 8; 67 | T_2.0 ; 68 | %load/vec4 v0x56049b45b470_0; 69 | %pad/s 32; 70 | %cmpi/s 127, 0, 32; 71 | %jmp/0xz T_2.1, 5; 72 | %delay 1000, 0; 73 | %vpi_call/w 3 19 "$display", "%d, %d", v0x56049b45b470_0, v0x56049b45b560_0 {0 0 0}; 74 | ; show_stmt_assign_vector: Get l-value for compressed += operand 75 | %load/vec4 v0x56049b45b470_0; 76 | %pushi/vec4 1, 0, 8; 77 | %add; 78 | %store/vec4 v0x56049b45b470_0, 0, 8; 79 | %jmp T_2.0; 80 | T_2.1 ; 81 | %vpi_call/w 3 22 "$finish" {0 0 0}; 82 | %end; 83 | .thread T_2; 84 | # The file index is used to find the file name in the following table. 85 | :file_names 5; 86 | "N/A"; 87 | ""; 88 | "-"; 89 | "tb_relu_bound.sv"; 90 | "./relu_bound.sv"; 91 | -------------------------------------------------------------------------------- /rtl/obj/tb_sat_unit.vvp: -------------------------------------------------------------------------------- 1 | #! /opt/iverilog/bin/vvp -v 2 | :ivl_version "11.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 11; 5 | :vpi_module "/opt/iverilog/lib/ivl/system.vpi"; 6 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_sys.vpi"; 7 | :vpi_module "/opt/iverilog/lib/ivl/vhdl_textio.vpi"; 8 | :vpi_module "/opt/iverilog/lib/ivl/v2005_math.vpi"; 9 | :vpi_module "/opt/iverilog/lib/ivl/va_math.vpi"; 10 | :vpi_module "/opt/iverilog/lib/ivl/v2009.vpi"; 11 | S_0x55c9a22830f0 .scope package, "$unit" "$unit" 2 1; 12 | .timescale 0 0; 13 | S_0x55c9a22842f0 .scope module, "tb_sat_unit" "tb_sat_unit" 3 5; 14 | .timescale -9 -11; 15 | v0x55c9a22aac90_0 .var/s "in", 12 0; 16 | v0x55c9a22aad50_0 .net/s "out", 7 0, L_0x55c9a22ab210; 1 drivers 17 | S_0x55c9a2284480 .scope module, "satu" "sat_unit" 3 9, 4 2 0, S_0x55c9a22842f0; 18 | .timescale -9 -11; 19 | .port_info 0 /INPUT 13 "a_in"; 20 | .port_info 1 /OUTPUT 8 "a_out"; 21 | P_0x55c9a2282280 .param/l "W_IN" 0 4 2, +C4<00000000000000000000000000001101>; 22 | P_0x55c9a22822c0 .param/l "W_OUT" 0 4 2, +C4<00000000000000000000000000001000>; 23 | v0x55c9a2297c30_0 .net *"_ivl_0", 0 0, L_0x55c9a22aae20; 1 drivers 24 | v0x55c9a22aa410_0 .net *"_ivl_2", 0 0, L_0x55c9a22aaf20; 1 drivers 25 | v0x55c9a22aa4d0_0 .net *"_ivl_5", 7 0, L_0x55c9a22aaff0; 1 drivers 26 | v0x55c9a22aa5c0_0 .net *"_ivl_6", 7 0, L_0x55c9a22ab0c0; 1 drivers 27 | v0x55c9a22aa6a0_0 .net/s "a_in", 12 0, v0x55c9a22aac90_0; 1 drivers 28 | v0x55c9a22aa7d0_0 .net/s "a_out", 7 0, L_0x55c9a22ab210; alias, 1 drivers 29 | v0x55c9a22aa8b0_0 .var/s "max_in", 12 0; 30 | v0x55c9a22aa990_0 .var/s "max_out", 7 0; 31 | v0x55c9a22aaa70_0 .var/s "min_in", 12 0; 32 | v0x55c9a22aab50_0 .var/s "min_out", 7 0; 33 | L_0x55c9a22aae20 .cmp/gt.s 13, v0x55c9a22aaa70_0, v0x55c9a22aac90_0; 34 | L_0x55c9a22aaf20 .cmp/gt.s 13, v0x55c9a22aac90_0, v0x55c9a22aa8b0_0; 35 | L_0x55c9a22aaff0 .part v0x55c9a22aac90_0, 0, 8; 36 | L_0x55c9a22ab0c0 .functor MUXZ 8, L_0x55c9a22aaff0, v0x55c9a22aa990_0, L_0x55c9a22aaf20, C4<>; 37 | L_0x55c9a22ab210 .functor MUXZ 8, L_0x55c9a22ab0c0, v0x55c9a22aab50_0, L_0x55c9a22aae20, C4<>; 38 | .scope S_0x55c9a2284480; 39 | T_0 ; 40 | %pushi/vec4 127, 0, 13; 41 | %store/vec4 v0x55c9a22aa8b0_0, 0, 13; 42 | %pushi/vec4 8064, 0, 13; 43 | %store/vec4 v0x55c9a22aaa70_0, 0, 13; 44 | %pushi/vec4 127, 0, 8; 45 | %store/vec4 v0x55c9a22aa990_0, 0, 8; 46 | %pushi/vec4 128, 0, 8; 47 | %store/vec4 v0x55c9a22aab50_0, 0, 8; 48 | %end; 49 | .thread T_0, $init; 50 | .scope S_0x55c9a2284480; 51 | T_1 ; 52 | %vpi_call/w 4 13 "$display", "%d, %d, %d, %d", v0x55c9a22aa8b0_0, v0x55c9a22aaa70_0, v0x55c9a22aa990_0, v0x55c9a22aab50_0 {0 0 0}; 53 | %end; 54 | .thread T_1; 55 | .scope S_0x55c9a22842f0; 56 | T_2 ; 57 | %vpi_call/w 3 15 "$dumpfile", "sat_unit.vcd" {0 0 0}; 58 | %vpi_call/w 3 16 "$dumpvars" {0 0 0}; 59 | %pushi/vec4 7936, 0, 13; 60 | %store/vec4 v0x55c9a22aac90_0, 0, 13; 61 | T_2.0 ; 62 | %load/vec4 v0x55c9a22aac90_0; 63 | %pad/s 32; 64 | %cmpi/s 256, 0, 32; 65 | %jmp/0xz T_2.1, 5; 66 | %delay 100, 0; 67 | %vpi_call/w 3 20 "$display", "%d, %d", v0x55c9a22aac90_0, v0x55c9a22aad50_0 {0 0 0}; 68 | ; show_stmt_assign_vector: Get l-value for compressed += operand 69 | %load/vec4 v0x55c9a22aac90_0; 70 | %pushi/vec4 1, 0, 13; 71 | %add; 72 | %store/vec4 v0x55c9a22aac90_0, 0, 13; 73 | %jmp T_2.0; 74 | T_2.1 ; 75 | %vpi_call/w 3 23 "$finish" {0 0 0}; 76 | %end; 77 | .thread T_2; 78 | # The file index is used to find the file name in the following table. 79 | :file_names 5; 80 | "N/A"; 81 | ""; 82 | "-"; 83 | "tb_sat_unit.sv"; 84 | "./sat_unit.sv"; 85 | -------------------------------------------------------------------------------- /rtl/pe_32b.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // NOTE (Matthew Johns) - there is similarity between parts of this code and the 16 | // proc_unit.sv module made by me in my third-year project. This is because the 17 | // functionality is similar and therefore I'm using what I learnt previously. 18 | 19 | // `include "defs.sv" 20 | import accelerator_pkg::*; 21 | 22 | module pe_32b ( 23 | output logic [31:0] out, 24 | // output logic flag_saturated // TODO: add this flag for CSRs 25 | input wire [31:0] a, 26 | input wire [31:0] b, 27 | input wire [31:0] c, 28 | input pe_arith_op_t op, 29 | input wire [1:0] vsew, 30 | input wire [1:0] widening, // 2'd1 for widening, 2'd2 for quad widening 31 | input wire [1:0] mul_us, // Specifies each multiplier input as signed or unsigned 32 | input pe_saturate_mode_t saturate_mode, 33 | input pe_output_mode_t output_mode, 34 | input wire wide_b 35 | ); 36 | 37 | // Usually input "a" is vs2, input "b" is vs1 and "c" is vs3/vd. (This is for 38 | // most standard arithmetic operations) 39 | 40 | logic signed [32:0] mult_a; 41 | logic signed [32:0] mult_b; 42 | logic signed [65:0] mult_wide; 43 | logic signed [32:0] selected_mult_out; 44 | 45 | logic [32:0] add_out; 46 | logic [32:0] add_a; 47 | logic [32:0] add_b; 48 | logic [32:0] addend; 49 | 50 | // Intermediate before saturation/ReLU 51 | // Has to be 33 bits to give at least one bit for saturation 52 | logic [32:0] arith_result; 53 | 54 | logic macc; 55 | logic subtract; 56 | 57 | // Instantiate sign extension module for inputs a, b and c 58 | wire [31:0] sign_ext_a; 59 | wire [31:0] sign_ext_b; 60 | wire [31:0] sign_ext_c; 61 | vw_sign_ext se0 ( 62 | .sign_ext_a(sign_ext_a), 63 | .sign_ext_b(sign_ext_b), 64 | .sign_ext_c(sign_ext_c), 65 | .a(a), 66 | .b(b), 67 | .c(c), 68 | .widening(widening), 69 | .vsew(vsew), 70 | .wide_b(wide_b) 71 | ); 72 | 73 | //////////////////////////////////////////////////////////////////////////////// 74 | // ARITHMETIC STAGE 75 | //////////////////////////////////////////////////////////////////////////////// 76 | always_comb 77 | begin 78 | subtract = 1'b0; 79 | macc = 1'b0; 80 | arith_result = '0; 81 | 82 | case (op) 83 | // 4'h0: // Add 84 | PE_ARITH_ADD: 85 | arith_result = add_out; 86 | // 4'h1: // Sub 87 | PE_ARITH_SUB: 88 | begin 89 | arith_result = add_out; 90 | subtract = 1'b1; 91 | end 92 | // 4'h2: // Left-shift 93 | PE_ARITH_LSHIFT: 94 | arith_result = {1'b0, (a << b)}; 95 | // 4'h3: // Multiply 96 | PE_ARITH_MUL: 97 | arith_result = selected_mult_out; 98 | // 4'h4: // Multiply-add 99 | PE_ARITH_MULADD: 100 | begin 101 | macc = 1'b1; 102 | arith_result = add_out; 103 | end 104 | // 4'h5: // XOR 105 | PE_ARITH_XOR: 106 | arith_result = {1'b0, (a ^ b)}; 107 | // 4'h6: // Right-shift 108 | PE_ARITH_RSHIFT_LOG: 109 | arith_result = {1'b0, (a >> b)}; 110 | // 4'h7: // Right-shift (arithmetic) 111 | PE_ARITH_RSHIFT_AR: 112 | arith_result = {1'b0, (a >>> b)}; 113 | // 4'h8: // OR 114 | PE_ARITH_OR: 115 | arith_result = {1'b0, (a | b)}; 116 | // 4'h9: // AND 117 | PE_ARITH_AND: 118 | arith_result = {1'b0, (a & b)}; 119 | endcase 120 | end 121 | 122 | always_comb 123 | begin 124 | // Multiplier needs to be able to be toggled between signed/unsigned for the 125 | // individual operands (depending on instructions). Can do this by adding an 126 | // extra bit to the inputs and sign-extending them for signed operations. 127 | // Then take the correct number of bits from the bottom. 128 | if (mul_us[1]) 129 | mult_a = {1'b0, a}; 130 | else 131 | mult_a = {sign_ext_a[31], sign_ext_a}; 132 | if (mul_us[0]) 133 | mult_b = {1'b0, b}; 134 | else 135 | mult_b = {sign_ext_b[31], sign_ext_b}; 136 | 137 | mult_wide = mult_a * mult_b; 138 | 139 | // Select adder inputs 140 | if (macc) 141 | begin 142 | add_a = {1'b0, mult_wide[31:0]}; 143 | add_b = {1'b0, c}; 144 | end 145 | else 146 | begin 147 | // Need to sign extend for saturated ops as another bit is gained to be 148 | // used for saturation. 149 | // This means instructions are fixed as signed. Would have to split up 150 | // if wanted to toggle signed/unsigned. 151 | // For some operations (such as regular addition) sign extension isn't 152 | // needed. But it doesn't do any harm and simplifies the logic. 153 | add_a = {sign_ext_a[31], sign_ext_a}; 154 | add_b = {sign_ext_b[31], sign_ext_b}; 155 | end 156 | 157 | if (subtract) 158 | addend = ~add_b + 1'b1; 159 | else 160 | addend = add_b; 161 | add_out = add_a + addend; 162 | 163 | end 164 | 165 | // Select multiplier output. V spec requires fractional saturating multiplies to 166 | // take the upper bits for saturation instead of lower bits. Should be able to 167 | // toggle this as we might need to saturate it and keep lower bits later on 168 | always_comb 169 | begin 170 | if (saturate_mode == PE_SAT_UPPER) 171 | case (vsew) 172 | 2'd0: // 8b 173 | selected_mult_out = {{24{1'b0}}, mult_wide[8:0]}; 174 | 2'd1: // 16b 175 | selected_mult_out = {{16{1'b0}}, mult_wide[16:0]}; 176 | 2'd2: // 32b 177 | selected_mult_out = mult_wide[32:0]; 178 | default: 179 | selected_mult_out = mult_wide[32:0]; 180 | endcase 181 | else 182 | selected_mult_out = mult_wide[32:0]; 183 | end 184 | 185 | //////////////////////////////////////////////////////////////////////////////// 186 | // SATURATE STAGE 187 | //////////////////////////////////////////////////////////////////////////////// 188 | logic [31:0] sat_result; 189 | // Instantiate the saturation blocks. One for each element width. Output is 190 | // selected from one of them at a time. 191 | wire [7:0] sat8_result; 192 | sat_unit #( 193 | .W_IN(33), 194 | .W_OUT(8) 195 | ) sat8 196 | ( 197 | .a_in(arith_result), 198 | .a_out(sat8_result) 199 | ); 200 | wire [15:0] sat16_result; 201 | sat_unit #( 202 | .W_IN(33), 203 | .W_OUT(16) 204 | ) sat16 205 | ( 206 | .a_in(arith_result), 207 | .a_out(sat16_result) 208 | ); 209 | wire [31:0] sat32_result; 210 | sat_unit #( 211 | .W_IN(33), 212 | .W_OUT(32) 213 | ) sat32 214 | ( 215 | .a_in(arith_result), 216 | .a_out(sat32_result) 217 | ); 218 | 219 | always_comb 220 | begin 221 | sat_result = arith_result[31:0]; 222 | // For widening, need to saturate to next larger element size 223 | if (widening[0]) 224 | case (vsew) 225 | 2'd0: // 8b -> 16b 226 | sat_result = {'0, sat16_result}; 227 | 2'd1: // 16b -> 32b 228 | sat_result = sat32_result; 229 | endcase 230 | // Quad widening should always use 32b 231 | else if (widening[1]) 232 | sat_result = sat32_result; 233 | // For non-widening, use vsew 234 | else 235 | case (vsew) 236 | 2'd0: // 8b 237 | sat_result = {'0, sat8_result}; 238 | 2'd1: // 16b 239 | sat_result = {'0, sat16_result}; 240 | 2'd2: // 32b 241 | sat_result = sat32_result; 242 | endcase 243 | end 244 | 245 | //////////////////////////////////////////////////////////////////////////////// 246 | // OUTPUT MODE SELECT 247 | //////////////////////////////////////////////////////////////////////////////// 248 | always_comb 249 | begin 250 | out = arith_result[31:0]; 251 | case (output_mode) 252 | PE_OP_MODE_RESULT: 253 | if (saturate_mode == PE_SAT_NONE) 254 | out = arith_result[31:0]; 255 | else 256 | out = sat_result; 257 | PE_OP_MODE_PASS_MAX: 258 | // Will do arithmetic op of a-b. If negative, b is larger so pass b 259 | if (arith_result[32]) 260 | out = b; 261 | else 262 | out = a; 263 | PE_OP_MODE_PASS_MIN: 264 | if (arith_result[32]) 265 | out = a; 266 | else 267 | out = b; 268 | // Important point for this: am looking at bit 31 (not 32) because 269 | // the inputs aren't sign-extended for anything non-saturating. 270 | endcase 271 | end 272 | 273 | endmodule 274 | -------------------------------------------------------------------------------- /rtl/pe_codes.ods: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AI-Vector-Accelerator/ava-core/dedf5ae1cfb373e984973d3c4b7472ec3bf9baca/rtl/pe_codes.ods -------------------------------------------------------------------------------- /rtl/relu_bound.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | module relu_bound 16 | #(parameter W=8, parameter N=(6<<4)) 17 | (input logic signed [W-1:0] a, 18 | output logic [W-2:0] ar); 19 | 20 | logic signed [W-1:0] zero = 'd0; 21 | always_comb begin 22 | if(a < zero) 23 | ar = 0; 24 | else if (a > N) 25 | ar = N[6:0]; 26 | else 27 | ar = a[6:0]; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /rtl/sat_unit.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // W_IN must be larger than W_OUT 16 | module sat_unit #(parameter W_IN = 13, parameter W_OUT = 8) 17 | (input logic signed [W_IN-1:0] a_in, 18 | output logic signed [W_OUT-1:0] a_out); 19 | 20 | logic signed [W_IN-1:0] max_in = {{(W_IN-W_OUT+1){1'b0}},{(W_OUT-1){1'b1}}}; 21 | logic signed [W_IN-1:0] min_in = {{(W_IN-W_OUT+1){1'b1}},{(W_OUT-1){1'b0}}}; 22 | logic signed [W_OUT-1:0] max_out = {1'b0,{(W_OUT-1){1'b1}}}; 23 | logic signed [W_OUT-1:0] min_out = {1'b1,{(W_OUT-1){1'b0}}}; 24 | 25 | assign a_out = a_in < min_in ? min_out : (a_in > max_in) ? max_out : a_in[W_OUT-1:0]; 26 | 27 | //initial $display("%d, %d, %d, %d", max_in, min_in, max_out, min_out); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /rtl/scalar_replicate.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // import accelerator_pkg::*; 16 | 17 | module scalar_replicate ( 18 | output logic [127:0] replicated_out, 19 | input wire [31:0] scalar_in, 20 | input wire [1:0] vsew, 21 | input wire us 22 | ); 23 | 24 | // When a scalar operand comes into the accelerator there is only one copy of 25 | // it. However, each PE needs a copy for it's calculation, so it must be 26 | // replicated into the right position for each PE. This module does that. 27 | 28 | always_comb 29 | case (vsew) 30 | 2'd0: // 8b 31 | if (us) 32 | replicated_out = { 33 | 24'd0, 34 | scalar_in[7:0], 35 | 24'd0, 36 | scalar_in[7:0], 37 | 24'd0, 38 | scalar_in[7:0], 39 | 24'd0, 40 | scalar_in[7:0] 41 | }; 42 | else 43 | replicated_out = { 44 | {24{scalar_in[7]}}, 45 | scalar_in[7:0], 46 | {24{scalar_in[7]}}, 47 | scalar_in[7:0], 48 | {24{scalar_in[7]}}, 49 | scalar_in[7:0], 50 | {24{scalar_in[7]}}, 51 | scalar_in[7:0] 52 | }; 53 | 2'd1: // 16b 54 | if (us) 55 | replicated_out = { 56 | 16'd0, 57 | scalar_in[15:0], 58 | 16'd0, 59 | scalar_in[15:0], 60 | 16'd0, 61 | scalar_in[15:0], 62 | 16'd0, 63 | scalar_in[15:0] 64 | }; 65 | else 66 | replicated_out = { 67 | {16{scalar_in[15]}}, 68 | scalar_in[15:0], 69 | {16{scalar_in[15]}}, 70 | scalar_in[15:0], 71 | {16{scalar_in[15]}}, 72 | scalar_in[15:0], 73 | {16{scalar_in[15]}}, 74 | scalar_in[15:0] 75 | }; 76 | 2'd2: // 32b 77 | replicated_out = { 78 | {4{scalar_in}} 79 | }; 80 | default: 81 | replicated_out = {'0, scalar_in}; 82 | endcase 83 | 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /rtl/tb/tb_address_unit.c: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | #include 16 | #include "Vbyte_enable.h" 17 | #include "verilated.h" 18 | 19 | vluint64_t main_time = 0; // Current simulation time 20 | 21 | double sc_time_stamp () { // Called by $time in Verilog 22 | return main_time; // converts to double, to match 23 | } 24 | 25 | int main(int argc, char **argv) { 26 | // Initialize Verilators variables 27 | Verilated::commandArgs(argc, argv); 28 | Verilated::traceEverOn(true); 29 | 30 | // Create an instance of our module under test 31 | Vbyte_enable *tb = new Vbyte_enable; 32 | 33 | tb->clk_i = 0; 34 | tb->n_rst_i = 1; 35 | tb->base_addr_i = 4; 36 | tb->stride = 8; 37 | tb->vl_i = 4; 38 | tb->vsew_i = 2; 39 | tb->load_first = 0; 40 | tb->next_cycle = 0; 41 | tb->eval(); 42 | main_time++; 43 | tb->n_rst_i = 0; 44 | tb->eval(); 45 | main_time++; 46 | tb->n_rst_i = 1; 47 | tb->eval(); 48 | main_time++; 49 | 50 | // Tick the clock until we are done 51 | while(!Verilated::gotFinish() && main_time < 100) { 52 | tb->clk_i = !(tb->clk_i); 53 | tb->eval(); 54 | main_time++; 55 | if(main_time == 15) tb->load_first = 1; 56 | if(main_time == 17) tb->load_first = 0; 57 | 58 | if(main_time == 21) tb->next_cycle = 1; 59 | if(main_time == 23) tb->next_cycle = 0; 60 | 61 | if(main_time == 27) tb->next_cycle = 1; 62 | if(main_time == 29) tb->next_cycle = 0; 63 | 64 | if(main_time == 33) tb->next_cycle = 1; 65 | if(main_time == 35) tb->next_cycle = 0; 66 | 67 | if(main_time == 39) tb->next_cycle = 1; 68 | if(main_time == 41) tb->next_cycle = 0; 69 | 70 | if(main_time == 45) tb->next_cycle = 1; 71 | if(main_time == 47) tb->next_cycle = 0; 72 | } 73 | tb->final(); 74 | delete(tb); 75 | 76 | return 0; 77 | } 78 | -------------------------------------------------------------------------------- /rtl/tb/tb_bit_ext.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | `timescale 1ns/10ps 16 | 17 | `include "bit_ext.sv" 18 | 19 | module tb_bit_ext; 20 | 21 | logic signed [7:0] in; 22 | logic signed [11:0] out; 23 | bit_ext #(.W_IN(8), .W_OUT(12)) bit_ext(in, out); 24 | 25 | initial begin 26 | `ifndef VERILATOR 27 | $dumpfile("bit_ext.vcd"); 28 | $dumpvars; 29 | `endif 30 | 31 | for(in = -128; in < 127; in++) begin 32 | #1ns $display("%d, %d", in, out); 33 | end 34 | 35 | $finish; 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /rtl/tb/tb_relu_bound.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | `timescale 1ns/10ps 16 | 17 | `include "relu_bound.sv" 18 | 19 | module tb_relu_bound; 20 | 21 | logic signed [7:0] in; 22 | logic [6:0] out; 23 | relu_bound #(.W(8)) rb(in, out); 24 | 25 | logic signed [7:0] i; 26 | 27 | initial begin 28 | `ifndef VERILATOR 29 | $dumpfile("relu_bound.vcd"); 30 | $dumpvars; 31 | `endif 32 | 33 | for(in = -128; in < 127; in++) begin 34 | #10ns $display("%d, %d", in, out); 35 | end 36 | 37 | $finish; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/tb/tb_sat_unit.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | `timescale 1ns/10ps 16 | 17 | `include "sat_unit.sv" 18 | 19 | module tb_sat_unit; 20 | 21 | logic signed [12:0] in; 22 | logic signed [7:0] out; 23 | sat_unit #(.W_IN(13), .W_OUT(8)) satu(in, out); 24 | 25 | logic signed [7:0] i; 26 | 27 | initial begin 28 | `ifndef VERILATOR 29 | $dumpfile("sat_unit.vcd"); 30 | $dumpvars; 31 | `endif 32 | 33 | for(in = -256; in < 256; in++) begin 34 | #1ns $display("%d, %d", in, out); 35 | end 36 | 37 | $finish; 38 | end 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /rtl/temporary_reg.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Byron Theobald 7 | // 8 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 9 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 10 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 11 | // conditions. 12 | // Source location: https://github.com/AI-Vector-Accelerator 13 | // 14 | 15 | // 32-Bit input, byte_position selects the bytes to load. 16 | // Selected bytes will be packed and loaded into the 17 | // register starting from byte_loaded 18 | 19 | module temporary_reg ( 20 | input logic clk_i, n_rst_i, 21 | input logic byte_enable_valid, 22 | input logic read_data_valid, 23 | input logic clear_register, 24 | input logic [31:0] memory_read_i, 25 | input logic [3:0] byte_enable_i, 26 | input logic [6:0] byte_select_i, 27 | output logic [127:0] wide_vd_o); 28 | 29 | logic [3:0] byte_enable_reg; 30 | 31 | always_ff @(posedge clk_i, negedge n_rst_i) begin 32 | if(~n_rst_i) 33 | byte_enable_reg <= 1'b0; 34 | else if(byte_enable_valid) 35 | byte_enable_reg <= byte_enable_i; 36 | end 37 | 38 | // Tempoary register, split into bytes. 39 | logic [7:0] temp_reg [15:0]; 40 | 41 | // Split memory read into bytes 42 | logic [7:0] memory_read_bytes [3:0]; 43 | 44 | always_comb begin // Split bytes out of word 45 | memory_read_bytes[0] = memory_read_i[7:0]; 46 | memory_read_bytes[1] = memory_read_i[15:8]; 47 | memory_read_bytes[2] = memory_read_i[23:16]; 48 | memory_read_bytes[3] = memory_read_i[31:24]; 49 | end 50 | 51 | // Packed read bytes, shift higher elements down 52 | logic [7:0] memory_read_packed [3:0]; 53 | logic [3:0] packed_set; 54 | 55 | always_comb begin 56 | memory_read_packed = '{default:0}; 57 | packed_set = 4'b0000; 58 | if(byte_enable_reg[0]) begin 59 | packed_set[0] = 1'b1; 60 | memory_read_packed[0] = memory_read_bytes[0]; 61 | end 62 | if(byte_enable_reg[1]) begin 63 | casez(packed_set) 64 | 4'bzzz0 : begin 65 | packed_set[0] = 1'b1; 66 | memory_read_packed[0] = memory_read_bytes[1]; 67 | end 68 | 4'bzzz1 : begin 69 | packed_set[1] = 1'b1; 70 | memory_read_packed[1] = memory_read_bytes[1]; 71 | end 72 | default: begin 73 | memory_read_packed[1] = '0; 74 | end 75 | endcase 76 | end 77 | if(byte_enable_reg[2]) begin 78 | casez(packed_set) 79 | 4'bzz00 : begin 80 | packed_set[0] = 1'b1; 81 | memory_read_packed[0] = memory_read_bytes[2]; 82 | end 83 | 4'bzz01 : begin 84 | packed_set[1] = 1'b1; 85 | memory_read_packed[1] = memory_read_bytes[2]; 86 | end 87 | 4'bzz11 : begin 88 | packed_set[2] = 1'b1; 89 | memory_read_packed[2] = memory_read_bytes[2]; 90 | end 91 | default: begin 92 | memory_read_packed[2] = '0; 93 | end 94 | endcase 95 | end 96 | if(byte_enable_reg[3]) begin 97 | casez(packed_set) 98 | 4'bz000 : begin 99 | packed_set[0] = 1'b1; 100 | memory_read_packed[0] = memory_read_bytes[3]; 101 | end 102 | 4'bz001 : begin 103 | packed_set[1] = 1'b1; 104 | memory_read_packed[1] = memory_read_bytes[3]; 105 | end 106 | 4'bz011 : begin 107 | packed_set[2] = 1'b1; 108 | memory_read_packed[2] = memory_read_bytes[3]; 109 | end 110 | 4'bz111 : begin 111 | packed_set[3] = 1'b1; 112 | memory_read_packed[3] = memory_read_bytes[3]; 113 | end 114 | default: begin 115 | memory_read_packed[3] = '0; 116 | end 117 | endcase 118 | end 119 | end 120 | 121 | // Write elements into register 122 | always_ff @(posedge clk_i, negedge n_rst_i) begin 123 | if(~n_rst_i) begin 124 | temp_reg <= '{default: 8'd0}; 125 | end else if(clear_register) begin 126 | temp_reg <= '{default: 8'd0}; 127 | end else if(read_data_valid) begin 128 | if(packed_set[0]) temp_reg[byte_select_i+0] <= memory_read_packed[0]; 129 | if(packed_set[1]) temp_reg[byte_select_i+1] <= memory_read_packed[1]; 130 | if(packed_set[2]) temp_reg[byte_select_i+2] <= memory_read_packed[2]; 131 | if(packed_set[3]) temp_reg[byte_select_i+3] <= memory_read_packed[3]; 132 | end 133 | end 134 | 135 | assign wide_vd_o = {temp_reg[15], temp_reg[14], temp_reg[13], temp_reg[12], 136 | temp_reg[11], temp_reg[10], temp_reg[ 9], temp_reg[ 8], 137 | temp_reg[ 7], temp_reg[ 6], temp_reg[ 5], temp_reg[ 4], 138 | temp_reg[ 3], temp_reg[ 2], temp_reg[ 1], temp_reg[ 0]}; 139 | 140 | endmodule 141 | -------------------------------------------------------------------------------- /rtl/vcd/bit_ext.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat Oct 24 00:10:08 2020 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 10ps 9 | $end 10 | $scope module tb_bit_ext $end 11 | $var wire 12 ! out [11:0] $end 12 | $var reg 8 " in [7:0] $end 13 | $scope module bit_ext $end 14 | $var wire 8 # a_in [7:0] $end 15 | $var wire 12 $ a_out [11:0] $end 16 | $upscope $end 17 | $upscope $end 18 | $enddefinitions $end 19 | #0 20 | $dumpvars 21 | b111110000000 $ 22 | b10000000 # 23 | b10000000 " 24 | b111110000000 ! 25 | $end 26 | #100 27 | b111110000001 ! 28 | b111110000001 $ 29 | b10000001 " 30 | b10000001 # 31 | #200 32 | b111110000010 ! 33 | b111110000010 $ 34 | b10000010 " 35 | b10000010 # 36 | #300 37 | b111110000011 ! 38 | b111110000011 $ 39 | b10000011 " 40 | b10000011 # 41 | #400 42 | b111110000100 ! 43 | b111110000100 $ 44 | b10000100 " 45 | b10000100 # 46 | #500 47 | b111110000101 ! 48 | b111110000101 $ 49 | b10000101 " 50 | b10000101 # 51 | #600 52 | b111110000110 ! 53 | b111110000110 $ 54 | b10000110 " 55 | b10000110 # 56 | #700 57 | b111110000111 ! 58 | b111110000111 $ 59 | b10000111 " 60 | b10000111 # 61 | #800 62 | b111110001000 ! 63 | b111110001000 $ 64 | b10001000 " 65 | b10001000 # 66 | #900 67 | b111110001001 ! 68 | b111110001001 $ 69 | b10001001 " 70 | b10001001 # 71 | #1000 72 | b111110001010 ! 73 | b111110001010 $ 74 | b10001010 " 75 | b10001010 # 76 | #1100 77 | b111110001011 ! 78 | b111110001011 $ 79 | b10001011 " 80 | b10001011 # 81 | #1200 82 | b111110001100 ! 83 | b111110001100 $ 84 | b10001100 " 85 | b10001100 # 86 | #1300 87 | b111110001101 ! 88 | b111110001101 $ 89 | b10001101 " 90 | b10001101 # 91 | #1400 92 | b111110001110 ! 93 | b111110001110 $ 94 | b10001110 " 95 | b10001110 # 96 | #1500 97 | b111110001111 ! 98 | b111110001111 $ 99 | b10001111 " 100 | b10001111 # 101 | #1600 102 | b111110010000 ! 103 | b111110010000 $ 104 | b10010000 " 105 | b10010000 # 106 | #1700 107 | b111110010001 ! 108 | b111110010001 $ 109 | b10010001 " 110 | b10010001 # 111 | #1800 112 | b111110010010 ! 113 | b111110010010 $ 114 | b10010010 " 115 | b10010010 # 116 | #1900 117 | b111110010011 ! 118 | b111110010011 $ 119 | b10010011 " 120 | b10010011 # 121 | #2000 122 | b111110010100 ! 123 | b111110010100 $ 124 | b10010100 " 125 | b10010100 # 126 | #2100 127 | b111110010101 ! 128 | b111110010101 $ 129 | b10010101 " 130 | b10010101 # 131 | #2200 132 | b111110010110 ! 133 | b111110010110 $ 134 | b10010110 " 135 | b10010110 # 136 | #2300 137 | b111110010111 ! 138 | b111110010111 $ 139 | b10010111 " 140 | b10010111 # 141 | #2400 142 | b111110011000 ! 143 | b111110011000 $ 144 | b10011000 " 145 | b10011000 # 146 | #2500 147 | b111110011001 ! 148 | b111110011001 $ 149 | b10011001 " 150 | b10011001 # 151 | #2600 152 | b111110011010 ! 153 | b111110011010 $ 154 | b10011010 " 155 | b10011010 # 156 | #2700 157 | b111110011011 ! 158 | b111110011011 $ 159 | b10011011 " 160 | b10011011 # 161 | #2800 162 | b111110011100 ! 163 | b111110011100 $ 164 | b10011100 " 165 | b10011100 # 166 | #2900 167 | b111110011101 ! 168 | b111110011101 $ 169 | b10011101 " 170 | b10011101 # 171 | #3000 172 | b111110011110 ! 173 | b111110011110 $ 174 | b10011110 " 175 | b10011110 # 176 | #3100 177 | b111110011111 ! 178 | b111110011111 $ 179 | b10011111 " 180 | b10011111 # 181 | #3200 182 | b111110100000 ! 183 | b111110100000 $ 184 | b10100000 " 185 | b10100000 # 186 | #3300 187 | b111110100001 ! 188 | b111110100001 $ 189 | b10100001 " 190 | b10100001 # 191 | #3400 192 | b111110100010 ! 193 | b111110100010 $ 194 | b10100010 " 195 | b10100010 # 196 | #3500 197 | b111110100011 ! 198 | b111110100011 $ 199 | b10100011 " 200 | b10100011 # 201 | #3600 202 | b111110100100 ! 203 | b111110100100 $ 204 | b10100100 " 205 | b10100100 # 206 | #3700 207 | b111110100101 ! 208 | b111110100101 $ 209 | b10100101 " 210 | b10100101 # 211 | #3800 212 | b111110100110 ! 213 | b111110100110 $ 214 | b10100110 " 215 | b10100110 # 216 | #3900 217 | b111110100111 ! 218 | b111110100111 $ 219 | b10100111 " 220 | b10100111 # 221 | #4000 222 | b111110101000 ! 223 | b111110101000 $ 224 | b10101000 " 225 | b10101000 # 226 | #4100 227 | b111110101001 ! 228 | b111110101001 $ 229 | b10101001 " 230 | b10101001 # 231 | #4200 232 | b111110101010 ! 233 | b111110101010 $ 234 | b10101010 " 235 | b10101010 # 236 | #4300 237 | b111110101011 ! 238 | b111110101011 $ 239 | b10101011 " 240 | b10101011 # 241 | #4400 242 | b111110101100 ! 243 | b111110101100 $ 244 | b10101100 " 245 | b10101100 # 246 | #4500 247 | b111110101101 ! 248 | b111110101101 $ 249 | b10101101 " 250 | b10101101 # 251 | #4600 252 | b111110101110 ! 253 | b111110101110 $ 254 | b10101110 " 255 | b10101110 # 256 | #4700 257 | b111110101111 ! 258 | b111110101111 $ 259 | b10101111 " 260 | b10101111 # 261 | #4800 262 | b111110110000 ! 263 | b111110110000 $ 264 | b10110000 " 265 | b10110000 # 266 | #4900 267 | b111110110001 ! 268 | b111110110001 $ 269 | b10110001 " 270 | b10110001 # 271 | #5000 272 | b111110110010 ! 273 | b111110110010 $ 274 | b10110010 " 275 | b10110010 # 276 | #5100 277 | b111110110011 ! 278 | b111110110011 $ 279 | b10110011 " 280 | b10110011 # 281 | #5200 282 | b111110110100 ! 283 | b111110110100 $ 284 | b10110100 " 285 | b10110100 # 286 | #5300 287 | b111110110101 ! 288 | b111110110101 $ 289 | b10110101 " 290 | b10110101 # 291 | #5400 292 | b111110110110 ! 293 | b111110110110 $ 294 | b10110110 " 295 | b10110110 # 296 | #5500 297 | b111110110111 ! 298 | b111110110111 $ 299 | b10110111 " 300 | b10110111 # 301 | #5600 302 | b111110111000 ! 303 | b111110111000 $ 304 | b10111000 " 305 | b10111000 # 306 | #5700 307 | b111110111001 ! 308 | b111110111001 $ 309 | b10111001 " 310 | b10111001 # 311 | #5800 312 | b111110111010 ! 313 | b111110111010 $ 314 | b10111010 " 315 | b10111010 # 316 | #5900 317 | b111110111011 ! 318 | b111110111011 $ 319 | b10111011 " 320 | b10111011 # 321 | #6000 322 | b111110111100 ! 323 | b111110111100 $ 324 | b10111100 " 325 | b10111100 # 326 | #6100 327 | b111110111101 ! 328 | b111110111101 $ 329 | b10111101 " 330 | b10111101 # 331 | #6200 332 | b111110111110 ! 333 | b111110111110 $ 334 | b10111110 " 335 | b10111110 # 336 | #6300 337 | b111110111111 ! 338 | b111110111111 $ 339 | b10111111 " 340 | b10111111 # 341 | #6400 342 | b111111000000 ! 343 | b111111000000 $ 344 | b11000000 " 345 | b11000000 # 346 | #6500 347 | b111111000001 ! 348 | b111111000001 $ 349 | b11000001 " 350 | b11000001 # 351 | #6600 352 | b111111000010 ! 353 | b111111000010 $ 354 | b11000010 " 355 | b11000010 # 356 | #6700 357 | b111111000011 ! 358 | b111111000011 $ 359 | b11000011 " 360 | b11000011 # 361 | #6800 362 | b111111000100 ! 363 | b111111000100 $ 364 | b11000100 " 365 | b11000100 # 366 | #6900 367 | b111111000101 ! 368 | b111111000101 $ 369 | b11000101 " 370 | b11000101 # 371 | #7000 372 | b111111000110 ! 373 | b111111000110 $ 374 | b11000110 " 375 | b11000110 # 376 | #7100 377 | b111111000111 ! 378 | b111111000111 $ 379 | b11000111 " 380 | b11000111 # 381 | #7200 382 | b111111001000 ! 383 | b111111001000 $ 384 | b11001000 " 385 | b11001000 # 386 | #7300 387 | b111111001001 ! 388 | b111111001001 $ 389 | b11001001 " 390 | b11001001 # 391 | #7400 392 | b111111001010 ! 393 | b111111001010 $ 394 | b11001010 " 395 | b11001010 # 396 | #7500 397 | b111111001011 ! 398 | b111111001011 $ 399 | b11001011 " 400 | b11001011 # 401 | #7600 402 | b111111001100 ! 403 | b111111001100 $ 404 | b11001100 " 405 | b11001100 # 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461 | #8800 462 | b111111011000 ! 463 | b111111011000 $ 464 | b11011000 " 465 | b11011000 # 466 | #8900 467 | b111111011001 ! 468 | b111111011001 $ 469 | b11011001 " 470 | b11011001 # 471 | #9000 472 | b111111011010 ! 473 | b111111011010 $ 474 | b11011010 " 475 | b11011010 # 476 | #9100 477 | b111111011011 ! 478 | b111111011011 $ 479 | b11011011 " 480 | b11011011 # 481 | #9200 482 | b111111011100 ! 483 | b111111011100 $ 484 | b11011100 " 485 | b11011100 # 486 | #9300 487 | b111111011101 ! 488 | b111111011101 $ 489 | b11011101 " 490 | b11011101 # 491 | #9400 492 | b111111011110 ! 493 | b111111011110 $ 494 | b11011110 " 495 | b11011110 # 496 | #9500 497 | b111111011111 ! 498 | b111111011111 $ 499 | b11011111 " 500 | b11011111 # 501 | #9600 502 | b111111100000 ! 503 | b111111100000 $ 504 | b11100000 " 505 | b11100000 # 506 | #9700 507 | b111111100001 ! 508 | b111111100001 $ 509 | b11100001 " 510 | b11100001 # 511 | #9800 512 | b111111100010 ! 513 | b111111100010 $ 514 | b11100010 " 515 | b11100010 # 516 | #9900 517 | b111111100011 ! 518 | b111111100011 $ 519 | b11100011 " 520 | b11100011 # 521 | #10000 522 | b111111100100 ! 523 | b111111100100 $ 524 | b11100100 " 525 | b11100100 # 526 | #10100 527 | b111111100101 ! 528 | b111111100101 $ 529 | b11100101 " 530 | b11100101 # 531 | #10200 532 | b111111100110 ! 533 | b111111100110 $ 534 | b11100110 " 535 | b11100110 # 536 | #10300 537 | b111111100111 ! 538 | b111111100111 $ 539 | b11100111 " 540 | b11100111 # 541 | #10400 542 | b111111101000 ! 543 | b111111101000 $ 544 | b11101000 " 545 | b11101000 # 546 | #10500 547 | b111111101001 ! 548 | b111111101001 $ 549 | b11101001 " 550 | b11101001 # 551 | #10600 552 | b111111101010 ! 553 | b111111101010 $ 554 | b11101010 " 555 | b11101010 # 556 | #10700 557 | b111111101011 ! 558 | b111111101011 $ 559 | b11101011 " 560 | b11101011 # 561 | #10800 562 | b111111101100 ! 563 | b111111101100 $ 564 | b11101100 " 565 | b11101100 # 566 | #10900 567 | b111111101101 ! 568 | b111111101101 $ 569 | b11101101 " 570 | b11101101 # 571 | #11000 572 | b111111101110 ! 573 | b111111101110 $ 574 | b11101110 " 575 | b11101110 # 576 | #11100 577 | b111111101111 ! 578 | b111111101111 $ 579 | b11101111 " 580 | b11101111 # 581 | #11200 582 | b111111110000 ! 583 | b111111110000 $ 584 | b11110000 " 585 | b11110000 # 586 | #11300 587 | b111111110001 ! 588 | b111111110001 $ 589 | b11110001 " 590 | b11110001 # 591 | #11400 592 | b111111110010 ! 593 | b111111110010 $ 594 | b11110010 " 595 | b11110010 # 596 | #11500 597 | b111111110011 ! 598 | b111111110011 $ 599 | b11110011 " 600 | b11110011 # 601 | #11600 602 | b111111110100 ! 603 | b111111110100 $ 604 | b11110100 " 605 | b11110100 # 606 | #11700 607 | b111111110101 ! 608 | b111111110101 $ 609 | b11110101 " 610 | b11110101 # 611 | #11800 612 | b111111110110 ! 613 | b111111110110 $ 614 | b11110110 " 615 | b11110110 # 616 | #11900 617 | b111111110111 ! 618 | b111111110111 $ 619 | b11110111 " 620 | b11110111 # 621 | #12000 622 | b111111111000 ! 623 | b111111111000 $ 624 | b11111000 " 625 | b11111000 # 626 | #12100 627 | b111111111001 ! 628 | b111111111001 $ 629 | b11111001 " 630 | b11111001 # 631 | #12200 632 | b111111111010 ! 633 | b111111111010 $ 634 | b11111010 " 635 | b11111010 # 636 | #12300 637 | b111111111011 ! 638 | b111111111011 $ 639 | b11111011 " 640 | b11111011 # 641 | #12400 642 | b111111111100 ! 643 | b111111111100 $ 644 | b11111100 " 645 | b11111100 # 646 | #12500 647 | b111111111101 ! 648 | b111111111101 $ 649 | b11111101 " 650 | b11111101 # 651 | #12600 652 | b111111111110 ! 653 | b111111111110 $ 654 | b11111110 " 655 | b11111110 # 656 | #12700 657 | b111111111111 ! 658 | b111111111111 $ 659 | b11111111 " 660 | b11111111 # 661 | #12800 662 | b0 ! 663 | b0 $ 664 | b0 " 665 | b0 # 666 | #12900 667 | b1 ! 668 | b1 $ 669 | b1 " 670 | b1 # 671 | #13000 672 | b10 ! 673 | b10 $ 674 | b10 " 675 | b10 # 676 | #13100 677 | b11 ! 678 | b11 $ 679 | b11 " 680 | b11 # 681 | #13200 682 | b100 ! 683 | b100 $ 684 | b100 " 685 | b100 # 686 | #13300 687 | b101 ! 688 | b101 $ 689 | b101 " 690 | b101 # 691 | #13400 692 | b110 ! 693 | b110 $ 694 | b110 " 695 | b110 # 696 | #13500 697 | b111 ! 698 | b111 $ 699 | b111 " 700 | b111 # 701 | #13600 702 | b1000 ! 703 | b1000 $ 704 | b1000 " 705 | b1000 # 706 | #13700 707 | b1001 ! 708 | b1001 $ 709 | b1001 " 710 | b1001 # 711 | #13800 712 | b1010 ! 713 | b1010 $ 714 | b1010 " 715 | b1010 # 716 | #13900 717 | b1011 ! 718 | b1011 $ 719 | b1011 " 720 | b1011 # 721 | #14000 722 | b1100 ! 723 | b1100 $ 724 | b1100 " 725 | b1100 # 726 | #14100 727 | b1101 ! 728 | b1101 $ 729 | b1101 " 730 | b1101 # 731 | #14200 732 | b1110 ! 733 | b1110 $ 734 | b1110 " 735 | b1110 # 736 | #14300 737 | b1111 ! 738 | b1111 $ 739 | b1111 " 740 | b1111 # 741 | #14400 742 | b10000 ! 743 | b10000 $ 744 | b10000 " 745 | b10000 # 746 | #14500 747 | b10001 ! 748 | b10001 $ 749 | b10001 " 750 | b10001 # 751 | #14600 752 | b10010 ! 753 | b10010 $ 754 | b10010 " 755 | b10010 # 756 | #14700 757 | b10011 ! 758 | b10011 $ 759 | b10011 " 760 | b10011 # 761 | #14800 762 | b10100 ! 763 | b10100 $ 764 | b10100 " 765 | b10100 # 766 | #14900 767 | b10101 ! 768 | b10101 $ 769 | b10101 " 770 | b10101 # 771 | #15000 772 | b10110 ! 773 | b10110 $ 774 | b10110 " 775 | b10110 # 776 | #15100 777 | b10111 ! 778 | b10111 $ 779 | b10111 " 780 | b10111 # 781 | #15200 782 | b11000 ! 783 | b11000 $ 784 | b11000 " 785 | b11000 # 786 | #15300 787 | b11001 ! 788 | b11001 $ 789 | b11001 " 790 | b11001 # 791 | #15400 792 | b11010 ! 793 | b11010 $ 794 | b11010 " 795 | b11010 # 796 | #15500 797 | b11011 ! 798 | b11011 $ 799 | b11011 " 800 | b11011 # 801 | #15600 802 | b11100 ! 803 | b11100 $ 804 | b11100 " 805 | b11100 # 806 | #15700 807 | b11101 ! 808 | b11101 $ 809 | b11101 " 810 | b11101 # 811 | #15800 812 | b11110 ! 813 | b11110 $ 814 | b11110 " 815 | b11110 # 816 | #15900 817 | b11111 ! 818 | b11111 $ 819 | b11111 " 820 | b11111 # 821 | #16000 822 | b100000 ! 823 | b100000 $ 824 | b100000 " 825 | b100000 # 826 | #16100 827 | b100001 ! 828 | b100001 $ 829 | b100001 " 830 | b100001 # 831 | #16200 832 | b100010 ! 833 | b100010 $ 834 | b100010 " 835 | b100010 # 836 | #16300 837 | b100011 ! 838 | b100011 $ 839 | b100011 " 840 | b100011 # 841 | #16400 842 | b100100 ! 843 | b100100 $ 844 | b100100 " 845 | b100100 # 846 | #16500 847 | b100101 ! 848 | b100101 $ 849 | b100101 " 850 | b100101 # 851 | #16600 852 | b100110 ! 853 | b100110 $ 854 | b100110 " 855 | b100110 # 856 | #16700 857 | b100111 ! 858 | b100111 $ 859 | b100111 " 860 | b100111 # 861 | #16800 862 | b101000 ! 863 | b101000 $ 864 | b101000 " 865 | b101000 # 866 | #16900 867 | b101001 ! 868 | b101001 $ 869 | b101001 " 870 | b101001 # 871 | #17000 872 | b101010 ! 873 | b101010 $ 874 | b101010 " 875 | b101010 # 876 | #17100 877 | b101011 ! 878 | b101011 $ 879 | b101011 " 880 | b101011 # 881 | #17200 882 | b101100 ! 883 | b101100 $ 884 | b101100 " 885 | b101100 # 886 | #17300 887 | b101101 ! 888 | b101101 $ 889 | b101101 " 890 | b101101 # 891 | #17400 892 | b101110 ! 893 | b101110 $ 894 | b101110 " 895 | b101110 # 896 | #17500 897 | b101111 ! 898 | b101111 $ 899 | b101111 " 900 | b101111 # 901 | #17600 902 | b110000 ! 903 | b110000 $ 904 | b110000 " 905 | b110000 # 906 | #17700 907 | b110001 ! 908 | b110001 $ 909 | b110001 " 910 | b110001 # 911 | #17800 912 | b110010 ! 913 | b110010 $ 914 | b110010 " 915 | b110010 # 916 | #17900 917 | b110011 ! 918 | b110011 $ 919 | b110011 " 920 | b110011 # 921 | #18000 922 | b110100 ! 923 | b110100 $ 924 | b110100 " 925 | b110100 # 926 | #18100 927 | b110101 ! 928 | b110101 $ 929 | b110101 " 930 | b110101 # 931 | #18200 932 | b110110 ! 933 | b110110 $ 934 | b110110 " 935 | b110110 # 936 | #18300 937 | b110111 ! 938 | b110111 $ 939 | b110111 " 940 | b110111 # 941 | #18400 942 | b111000 ! 943 | b111000 $ 944 | b111000 " 945 | b111000 # 946 | #18500 947 | b111001 ! 948 | b111001 $ 949 | b111001 " 950 | b111001 # 951 | #18600 952 | b111010 ! 953 | b111010 $ 954 | b111010 " 955 | b111010 # 956 | #18700 957 | b111011 ! 958 | b111011 $ 959 | b111011 " 960 | b111011 # 961 | #18800 962 | b111100 ! 963 | b111100 $ 964 | b111100 " 965 | b111100 # 966 | #18900 967 | b111101 ! 968 | b111101 $ 969 | b111101 " 970 | b111101 # 971 | #19000 972 | b111110 ! 973 | b111110 $ 974 | b111110 " 975 | b111110 # 976 | #19100 977 | b111111 ! 978 | b111111 $ 979 | b111111 " 980 | b111111 # 981 | #19200 982 | b1000000 ! 983 | b1000000 $ 984 | b1000000 " 985 | b1000000 # 986 | #19300 987 | b1000001 ! 988 | b1000001 $ 989 | b1000001 " 990 | b1000001 # 991 | #19400 992 | b1000010 ! 993 | b1000010 $ 994 | b1000010 " 995 | b1000010 # 996 | #19500 997 | b1000011 ! 998 | b1000011 $ 999 | b1000011 " 1000 | b1000011 # 1001 | #19600 1002 | b1000100 ! 1003 | b1000100 $ 1004 | b1000100 " 1005 | b1000100 # 1006 | #19700 1007 | b1000101 ! 1008 | b1000101 $ 1009 | b1000101 " 1010 | b1000101 # 1011 | #19800 1012 | b1000110 ! 1013 | b1000110 $ 1014 | b1000110 " 1015 | b1000110 # 1016 | #19900 1017 | b1000111 ! 1018 | b1000111 $ 1019 | b1000111 " 1020 | b1000111 # 1021 | #20000 1022 | b1001000 ! 1023 | b1001000 $ 1024 | b1001000 " 1025 | b1001000 # 1026 | #20100 1027 | b1001001 ! 1028 | b1001001 $ 1029 | b1001001 " 1030 | b1001001 # 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1211 | #23800 1212 | b1101110 ! 1213 | b1101110 $ 1214 | b1101110 " 1215 | b1101110 # 1216 | #23900 1217 | b1101111 ! 1218 | b1101111 $ 1219 | b1101111 " 1220 | b1101111 # 1221 | #24000 1222 | b1110000 ! 1223 | b1110000 $ 1224 | b1110000 " 1225 | b1110000 # 1226 | #24100 1227 | b1110001 ! 1228 | b1110001 $ 1229 | b1110001 " 1230 | b1110001 # 1231 | #24200 1232 | b1110010 ! 1233 | b1110010 $ 1234 | b1110010 " 1235 | b1110010 # 1236 | #24300 1237 | b1110011 ! 1238 | b1110011 $ 1239 | b1110011 " 1240 | b1110011 # 1241 | #24400 1242 | b1110100 ! 1243 | b1110100 $ 1244 | b1110100 " 1245 | b1110100 # 1246 | #24500 1247 | b1110101 ! 1248 | b1110101 $ 1249 | b1110101 " 1250 | b1110101 # 1251 | #24600 1252 | b1110110 ! 1253 | b1110110 $ 1254 | b1110110 " 1255 | b1110110 # 1256 | #24700 1257 | b1110111 ! 1258 | b1110111 $ 1259 | b1110111 " 1260 | b1110111 # 1261 | #24800 1262 | b1111000 ! 1263 | b1111000 $ 1264 | b1111000 " 1265 | b1111000 # 1266 | #24900 1267 | b1111001 ! 1268 | b1111001 $ 1269 | b1111001 " 1270 | b1111001 # 1271 | #25000 1272 | b1111010 ! 1273 | b1111010 $ 1274 | b1111010 " 1275 | b1111010 # 1276 | #25100 1277 | b1111011 ! 1278 | b1111011 $ 1279 | b1111011 " 1280 | b1111011 # 1281 | #25200 1282 | b1111100 ! 1283 | b1111100 $ 1284 | b1111100 " 1285 | b1111100 # 1286 | #25300 1287 | b1111101 ! 1288 | b1111101 $ 1289 | b1111101 " 1290 | b1111101 # 1291 | #25400 1292 | b1111110 ! 1293 | b1111110 $ 1294 | b1111110 " 1295 | b1111110 # 1296 | #25500 1297 | b1111111 ! 1298 | b1111111 $ 1299 | b1111111 " 1300 | b1111111 # 1301 | -------------------------------------------------------------------------------- /rtl/vcd/relu_bound.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat Oct 24 00:10:14 2020 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 10ps 9 | $end 10 | $scope module tb_relu_bound $end 11 | $var wire 8 ! out [7:0] $end 12 | $var reg 8 " in [7:0] $end 13 | $scope module rb $end 14 | $var wire 8 # a [7:0] $end 15 | $var reg 8 $ ar [7:0] $end 16 | $var reg 8 % zero_signed [7:0] $end 17 | $upscope $end 18 | $upscope $end 19 | $enddefinitions $end 20 | #0 21 | $dumpvars 22 | b0 % 23 | b0 $ 24 | b10000000 # 25 | b10000000 " 26 | b0 ! 27 | $end 28 | #1000 29 | b10000001 " 30 | b10000001 # 31 | #2000 32 | b10000010 " 33 | b10000010 # 34 | #3000 35 | b10000011 " 36 | b10000011 # 37 | #4000 38 | b10000100 " 39 | b10000100 # 40 | #5000 41 | b10000101 " 42 | b10000101 # 43 | #6000 44 | b10000110 " 45 | b10000110 # 46 | #7000 47 | b10000111 " 48 | b10000111 # 49 | #8000 50 | b10001000 " 51 | b10001000 # 52 | #9000 53 | b10001001 " 54 | b10001001 # 55 | #10000 56 | b10001010 " 57 | b10001010 # 58 | #11000 59 | b10001011 " 60 | b10001011 # 61 | #12000 62 | b10001100 " 63 | b10001100 # 64 | #13000 65 | b10001101 " 66 | b10001101 # 67 | #14000 68 | b10001110 " 69 | b10001110 # 70 | #15000 71 | b10001111 " 72 | b10001111 # 73 | #16000 74 | b10010000 " 75 | b10010000 # 76 | #17000 77 | b10010001 " 78 | b10010001 # 79 | #18000 80 | b10010010 " 81 | b10010010 # 82 | #19000 83 | b10010011 " 84 | b10010011 # 85 | #20000 86 | b10010100 " 87 | b10010100 # 88 | #21000 89 | b10010101 " 90 | b10010101 # 91 | #22000 92 | b10010110 " 93 | b10010110 # 94 | #23000 95 | b10010111 " 96 | b10010111 # 97 | #24000 98 | b10011000 " 99 | b10011000 # 100 | #25000 101 | b10011001 " 102 | b10011001 # 103 | #26000 104 | b10011010 " 105 | b10011010 # 106 | #27000 107 | b10011011 " 108 | b10011011 # 109 | #28000 110 | b10011100 " 111 | b10011100 # 112 | #29000 113 | b10011101 " 114 | b10011101 # 115 | #30000 116 | b10011110 " 117 | b10011110 # 118 | #31000 119 | b10011111 " 120 | b10011111 # 121 | #32000 122 | b10100000 " 123 | b10100000 # 124 | #33000 125 | b10100001 " 126 | b10100001 # 127 | #34000 128 | b10100010 " 129 | b10100010 # 130 | #35000 131 | b10100011 " 132 | b10100011 # 133 | #36000 134 | b10100100 " 135 | b10100100 # 136 | #37000 137 | b10100101 " 138 | b10100101 # 139 | #38000 140 | b10100110 " 141 | b10100110 # 142 | #39000 143 | b10100111 " 144 | b10100111 # 145 | #40000 146 | b10101000 " 147 | b10101000 # 148 | #41000 149 | b10101001 " 150 | b10101001 # 151 | #42000 152 | b10101010 " 153 | b10101010 # 154 | #43000 155 | b10101011 " 156 | b10101011 # 157 | #44000 158 | b10101100 " 159 | b10101100 # 160 | #45000 161 | b10101101 " 162 | b10101101 # 163 | #46000 164 | b10101110 " 165 | b10101110 # 166 | #47000 167 | b10101111 " 168 | b10101111 # 169 | #48000 170 | b10110000 " 171 | b10110000 # 172 | #49000 173 | b10110001 " 174 | b10110001 # 175 | #50000 176 | b10110010 " 177 | b10110010 # 178 | #51000 179 | b10110011 " 180 | b10110011 # 181 | #52000 182 | b10110100 " 183 | b10110100 # 184 | #53000 185 | b10110101 " 186 | b10110101 # 187 | #54000 188 | b10110110 " 189 | b10110110 # 190 | #55000 191 | b10110111 " 192 | b10110111 # 193 | #56000 194 | b10111000 " 195 | b10111000 # 196 | #57000 197 | b10111001 " 198 | b10111001 # 199 | #58000 200 | b10111010 " 201 | b10111010 # 202 | #59000 203 | b10111011 " 204 | b10111011 # 205 | #60000 206 | b10111100 " 207 | b10111100 # 208 | #61000 209 | b10111101 " 210 | b10111101 # 211 | #62000 212 | b10111110 " 213 | b10111110 # 214 | #63000 215 | b10111111 " 216 | b10111111 # 217 | #64000 218 | b11000000 " 219 | b11000000 # 220 | #65000 221 | b11000001 " 222 | b11000001 # 223 | #66000 224 | b11000010 " 225 | b11000010 # 226 | #67000 227 | b11000011 " 228 | b11000011 # 229 | #68000 230 | b11000100 " 231 | b11000100 # 232 | #69000 233 | b11000101 " 234 | b11000101 # 235 | #70000 236 | b11000110 " 237 | b11000110 # 238 | #71000 239 | b11000111 " 240 | b11000111 # 241 | #72000 242 | b11001000 " 243 | b11001000 # 244 | #73000 245 | b11001001 " 246 | b11001001 # 247 | #74000 248 | b11001010 " 249 | b11001010 # 250 | #75000 251 | b11001011 " 252 | b11001011 # 253 | #76000 254 | b11001100 " 255 | b11001100 # 256 | #77000 257 | b11001101 " 258 | b11001101 # 259 | #78000 260 | b11001110 " 261 | b11001110 # 262 | #79000 263 | b11001111 " 264 | b11001111 # 265 | #80000 266 | b11010000 " 267 | b11010000 # 268 | #81000 269 | b11010001 " 270 | b11010001 # 271 | #82000 272 | b11010010 " 273 | b11010010 # 274 | #83000 275 | b11010011 " 276 | b11010011 # 277 | #84000 278 | b11010100 " 279 | b11010100 # 280 | #85000 281 | b11010101 " 282 | b11010101 # 283 | #86000 284 | b11010110 " 285 | b11010110 # 286 | #87000 287 | b11010111 " 288 | b11010111 # 289 | #88000 290 | b11011000 " 291 | b11011000 # 292 | #89000 293 | b11011001 " 294 | b11011001 # 295 | #90000 296 | b11011010 " 297 | b11011010 # 298 | #91000 299 | b11011011 " 300 | b11011011 # 301 | #92000 302 | b11011100 " 303 | b11011100 # 304 | #93000 305 | b11011101 " 306 | b11011101 # 307 | #94000 308 | b11011110 " 309 | b11011110 # 310 | #95000 311 | b11011111 " 312 | b11011111 # 313 | #96000 314 | b11100000 " 315 | b11100000 # 316 | #97000 317 | b11100001 " 318 | b11100001 # 319 | #98000 320 | b11100010 " 321 | b11100010 # 322 | #99000 323 | b11100011 " 324 | b11100011 # 325 | #100000 326 | b11100100 " 327 | b11100100 # 328 | #101000 329 | b11100101 " 330 | b11100101 # 331 | #102000 332 | b11100110 " 333 | b11100110 # 334 | #103000 335 | b11100111 " 336 | b11100111 # 337 | #104000 338 | b11101000 " 339 | b11101000 # 340 | #105000 341 | b11101001 " 342 | b11101001 # 343 | #106000 344 | b11101010 " 345 | b11101010 # 346 | #107000 347 | b11101011 " 348 | b11101011 # 349 | #108000 350 | b11101100 " 351 | b11101100 # 352 | #109000 353 | b11101101 " 354 | b11101101 # 355 | #110000 356 | b11101110 " 357 | b11101110 # 358 | #111000 359 | b11101111 " 360 | b11101111 # 361 | #112000 362 | b11110000 " 363 | b11110000 # 364 | #113000 365 | b11110001 " 366 | b11110001 # 367 | #114000 368 | b11110010 " 369 | b11110010 # 370 | #115000 371 | b11110011 " 372 | b11110011 # 373 | #116000 374 | b11110100 " 375 | b11110100 # 376 | #117000 377 | b11110101 " 378 | b11110101 # 379 | #118000 380 | b11110110 " 381 | b11110110 # 382 | #119000 383 | b11110111 " 384 | b11110111 # 385 | #120000 386 | b11111000 " 387 | b11111000 # 388 | #121000 389 | b11111001 " 390 | b11111001 # 391 | #122000 392 | b11111010 " 393 | b11111010 # 394 | #123000 395 | b11111011 " 396 | b11111011 # 397 | #124000 398 | b11111100 " 399 | b11111100 # 400 | #125000 401 | b11111101 " 402 | b11111101 # 403 | #126000 404 | b11111110 " 405 | b11111110 # 406 | #127000 407 | b11111111 " 408 | b11111111 # 409 | #128000 410 | b0 " 411 | b0 # 412 | #129000 413 | b1 ! 414 | b1 $ 415 | b1 " 416 | b1 # 417 | #130000 418 | b10 ! 419 | b10 $ 420 | b10 " 421 | b10 # 422 | #131000 423 | b11 ! 424 | b11 $ 425 | b11 " 426 | b11 # 427 | #132000 428 | b100 ! 429 | b100 $ 430 | b100 " 431 | b100 # 432 | #133000 433 | b101 ! 434 | b101 $ 435 | b101 " 436 | b101 # 437 | #134000 438 | b110 ! 439 | b110 $ 440 | b110 " 441 | b110 # 442 | #135000 443 | b111 ! 444 | b111 $ 445 | b111 " 446 | b111 # 447 | #136000 448 | b1000 ! 449 | b1000 $ 450 | b1000 " 451 | b1000 # 452 | #137000 453 | b1001 ! 454 | b1001 $ 455 | b1001 " 456 | b1001 # 457 | #138000 458 | b1010 ! 459 | b1010 $ 460 | b1010 " 461 | b1010 # 462 | #139000 463 | b1011 ! 464 | b1011 $ 465 | b1011 " 466 | b1011 # 467 | #140000 468 | b1100 ! 469 | b1100 $ 470 | b1100 " 471 | b1100 # 472 | #141000 473 | b1101 ! 474 | b1101 $ 475 | b1101 " 476 | b1101 # 477 | #142000 478 | b1110 ! 479 | b1110 $ 480 | b1110 " 481 | b1110 # 482 | #143000 483 | b1111 ! 484 | b1111 $ 485 | b1111 " 486 | b1111 # 487 | #144000 488 | b10000 ! 489 | b10000 $ 490 | b10000 " 491 | b10000 # 492 | #145000 493 | b10001 ! 494 | b10001 $ 495 | b10001 " 496 | b10001 # 497 | #146000 498 | b10010 ! 499 | b10010 $ 500 | b10010 " 501 | b10010 # 502 | #147000 503 | b10011 ! 504 | b10011 $ 505 | b10011 " 506 | b10011 # 507 | #148000 508 | b10100 ! 509 | b10100 $ 510 | b10100 " 511 | b10100 # 512 | #149000 513 | b10101 ! 514 | b10101 $ 515 | b10101 " 516 | b10101 # 517 | #150000 518 | b10110 ! 519 | b10110 $ 520 | b10110 " 521 | b10110 # 522 | #151000 523 | b10111 ! 524 | b10111 $ 525 | b10111 " 526 | b10111 # 527 | #152000 528 | b11000 ! 529 | b11000 $ 530 | b11000 " 531 | b11000 # 532 | #153000 533 | b11001 ! 534 | b11001 $ 535 | b11001 " 536 | b11001 # 537 | #154000 538 | b11010 ! 539 | b11010 $ 540 | b11010 " 541 | b11010 # 542 | #155000 543 | b11011 ! 544 | b11011 $ 545 | b11011 " 546 | b11011 # 547 | #156000 548 | b11100 ! 549 | b11100 $ 550 | b11100 " 551 | b11100 # 552 | #157000 553 | b11101 ! 554 | b11101 $ 555 | b11101 " 556 | b11101 # 557 | #158000 558 | b11110 ! 559 | b11110 $ 560 | b11110 " 561 | b11110 # 562 | #159000 563 | b11111 ! 564 | b11111 $ 565 | b11111 " 566 | b11111 # 567 | #160000 568 | b100000 ! 569 | b100000 $ 570 | b100000 " 571 | b100000 # 572 | #161000 573 | b100001 ! 574 | b100001 $ 575 | b100001 " 576 | b100001 # 577 | #162000 578 | b100010 ! 579 | b100010 $ 580 | b100010 " 581 | b100010 # 582 | #163000 583 | b100011 ! 584 | b100011 $ 585 | b100011 " 586 | b100011 # 587 | #164000 588 | b100100 ! 589 | b100100 $ 590 | b100100 " 591 | b100100 # 592 | #165000 593 | b100101 ! 594 | b100101 $ 595 | b100101 " 596 | b100101 # 597 | #166000 598 | b100110 ! 599 | b100110 $ 600 | b100110 " 601 | b100110 # 602 | #167000 603 | b100111 ! 604 | b100111 $ 605 | b100111 " 606 | b100111 # 607 | #168000 608 | b101000 ! 609 | b101000 $ 610 | b101000 " 611 | b101000 # 612 | #169000 613 | b101001 ! 614 | b101001 $ 615 | b101001 " 616 | b101001 # 617 | #170000 618 | b101010 ! 619 | b101010 $ 620 | b101010 " 621 | b101010 # 622 | #171000 623 | b101011 ! 624 | b101011 $ 625 | b101011 " 626 | b101011 # 627 | #172000 628 | b101100 ! 629 | b101100 $ 630 | b101100 " 631 | b101100 # 632 | #173000 633 | b101101 ! 634 | b101101 $ 635 | b101101 " 636 | b101101 # 637 | #174000 638 | b101110 ! 639 | b101110 $ 640 | b101110 " 641 | b101110 # 642 | #175000 643 | b101111 ! 644 | b101111 $ 645 | b101111 " 646 | b101111 # 647 | #176000 648 | b110000 ! 649 | b110000 $ 650 | b110000 " 651 | b110000 # 652 | #177000 653 | b110001 ! 654 | b110001 $ 655 | b110001 " 656 | b110001 # 657 | #178000 658 | b110010 ! 659 | b110010 $ 660 | b110010 " 661 | b110010 # 662 | #179000 663 | b110011 ! 664 | b110011 $ 665 | b110011 " 666 | b110011 # 667 | #180000 668 | b110100 ! 669 | b110100 $ 670 | b110100 " 671 | b110100 # 672 | #181000 673 | b110101 ! 674 | b110101 $ 675 | b110101 " 676 | b110101 # 677 | #182000 678 | b110110 ! 679 | b110110 $ 680 | b110110 " 681 | b110110 # 682 | #183000 683 | b110111 ! 684 | b110111 $ 685 | b110111 " 686 | b110111 # 687 | #184000 688 | b111000 ! 689 | b111000 $ 690 | b111000 " 691 | b111000 # 692 | #185000 693 | b111001 ! 694 | b111001 $ 695 | b111001 " 696 | b111001 # 697 | #186000 698 | b111010 ! 699 | b111010 $ 700 | b111010 " 701 | b111010 # 702 | #187000 703 | b111011 ! 704 | b111011 $ 705 | b111011 " 706 | b111011 # 707 | #188000 708 | b111100 ! 709 | b111100 $ 710 | b111100 " 711 | b111100 # 712 | #189000 713 | b111101 ! 714 | b111101 $ 715 | b111101 " 716 | b111101 # 717 | #190000 718 | b111110 ! 719 | b111110 $ 720 | b111110 " 721 | b111110 # 722 | #191000 723 | b111111 ! 724 | b111111 $ 725 | b111111 " 726 | b111111 # 727 | #192000 728 | b1000000 ! 729 | b1000000 $ 730 | b1000000 " 731 | b1000000 # 732 | #193000 733 | b1000001 ! 734 | b1000001 $ 735 | b1000001 " 736 | b1000001 # 737 | #194000 738 | b1000010 ! 739 | b1000010 $ 740 | b1000010 " 741 | b1000010 # 742 | #195000 743 | b1000011 ! 744 | b1000011 $ 745 | b1000011 " 746 | b1000011 # 747 | #196000 748 | b1000100 ! 749 | b1000100 $ 750 | b1000100 " 751 | b1000100 # 752 | #197000 753 | b1000101 ! 754 | b1000101 $ 755 | b1000101 " 756 | b1000101 # 757 | #198000 758 | b1000110 ! 759 | b1000110 $ 760 | b1000110 " 761 | b1000110 # 762 | #199000 763 | b1000111 ! 764 | b1000111 $ 765 | b1000111 " 766 | b1000111 # 767 | #200000 768 | b1001000 ! 769 | b1001000 $ 770 | b1001000 " 771 | b1001000 # 772 | #201000 773 | b1001001 ! 774 | b1001001 $ 775 | b1001001 " 776 | b1001001 # 777 | #202000 778 | b1001010 ! 779 | b1001010 $ 780 | b1001010 " 781 | b1001010 # 782 | #203000 783 | b1001011 ! 784 | b1001011 $ 785 | b1001011 " 786 | b1001011 # 787 | #204000 788 | b1001100 ! 789 | b1001100 $ 790 | b1001100 " 791 | b1001100 # 792 | #205000 793 | b1001101 ! 794 | b1001101 $ 795 | b1001101 " 796 | b1001101 # 797 | #206000 798 | b1001110 ! 799 | b1001110 $ 800 | b1001110 " 801 | b1001110 # 802 | #207000 803 | b1001111 ! 804 | b1001111 $ 805 | b1001111 " 806 | b1001111 # 807 | #208000 808 | b1010000 ! 809 | b1010000 $ 810 | b1010000 " 811 | b1010000 # 812 | #209000 813 | b1010001 ! 814 | b1010001 $ 815 | b1010001 " 816 | b1010001 # 817 | #210000 818 | b1010010 ! 819 | b1010010 $ 820 | b1010010 " 821 | b1010010 # 822 | #211000 823 | b1010011 ! 824 | b1010011 $ 825 | b1010011 " 826 | b1010011 # 827 | #212000 828 | b1010100 ! 829 | b1010100 $ 830 | b1010100 " 831 | b1010100 # 832 | #213000 833 | b1010101 ! 834 | b1010101 $ 835 | b1010101 " 836 | b1010101 # 837 | #214000 838 | b1010110 ! 839 | b1010110 $ 840 | b1010110 " 841 | b1010110 # 842 | #215000 843 | b1010111 ! 844 | b1010111 $ 845 | b1010111 " 846 | b1010111 # 847 | #216000 848 | b1011000 ! 849 | b1011000 $ 850 | b1011000 " 851 | b1011000 # 852 | #217000 853 | b1011001 ! 854 | b1011001 $ 855 | b1011001 " 856 | b1011001 # 857 | #218000 858 | b1011010 ! 859 | b1011010 $ 860 | b1011010 " 861 | b1011010 # 862 | #219000 863 | b1011011 ! 864 | b1011011 $ 865 | b1011011 " 866 | b1011011 # 867 | #220000 868 | b1011100 ! 869 | b1011100 $ 870 | b1011100 " 871 | b1011100 # 872 | #221000 873 | b1011101 ! 874 | b1011101 $ 875 | b1011101 " 876 | b1011101 # 877 | #222000 878 | b1011110 ! 879 | b1011110 $ 880 | b1011110 " 881 | b1011110 # 882 | #223000 883 | b1011111 ! 884 | b1011111 $ 885 | b1011111 " 886 | b1011111 # 887 | #224000 888 | b1100000 ! 889 | b1100000 $ 890 | b1100000 " 891 | b1100000 # 892 | #225000 893 | b1100001 " 894 | b1100001 # 895 | #226000 896 | b1100010 " 897 | b1100010 # 898 | #227000 899 | b1100011 " 900 | b1100011 # 901 | #228000 902 | b1100100 " 903 | b1100100 # 904 | #229000 905 | b1100101 " 906 | b1100101 # 907 | #230000 908 | b1100110 " 909 | b1100110 # 910 | #231000 911 | b1100111 " 912 | b1100111 # 913 | #232000 914 | b1101000 " 915 | b1101000 # 916 | #233000 917 | b1101001 " 918 | b1101001 # 919 | #234000 920 | b1101010 " 921 | b1101010 # 922 | #235000 923 | b1101011 " 924 | b1101011 # 925 | #236000 926 | b1101100 " 927 | b1101100 # 928 | #237000 929 | b1101101 " 930 | b1101101 # 931 | #238000 932 | b1101110 " 933 | b1101110 # 934 | #239000 935 | b1101111 " 936 | b1101111 # 937 | #240000 938 | b1110000 " 939 | b1110000 # 940 | #241000 941 | b1110001 " 942 | b1110001 # 943 | #242000 944 | b1110010 " 945 | b1110010 # 946 | #243000 947 | b1110011 " 948 | b1110011 # 949 | #244000 950 | b1110100 " 951 | b1110100 # 952 | #245000 953 | b1110101 " 954 | b1110101 # 955 | #246000 956 | b1110110 " 957 | b1110110 # 958 | #247000 959 | b1110111 " 960 | b1110111 # 961 | #248000 962 | b1111000 " 963 | b1111000 # 964 | #249000 965 | b1111001 " 966 | b1111001 # 967 | #250000 968 | b1111010 " 969 | b1111010 # 970 | #251000 971 | b1111011 " 972 | b1111011 # 973 | #252000 974 | b1111100 " 975 | b1111100 # 976 | #253000 977 | b1111101 " 978 | b1111101 # 979 | #254000 980 | b1111110 " 981 | b1111110 # 982 | #255000 983 | b1111111 " 984 | b1111111 # 985 | -------------------------------------------------------------------------------- /rtl/vcd/sat_unit.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat Oct 24 00:10:19 2020 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 10ps 9 | $end 10 | $scope module tb_sat_unit $end 11 | $var wire 8 ! out [7:0] $end 12 | $var reg 13 " in [12:0] $end 13 | $scope module satu $end 14 | $var wire 13 # a_in [12:0] $end 15 | $var wire 8 $ a_out [7:0] $end 16 | $var reg 13 % max_in [12:0] $end 17 | $var reg 8 & max_out [7:0] $end 18 | $var reg 13 ' min_in [12:0] $end 19 | $var reg 8 ( min_out [7:0] $end 20 | $upscope $end 21 | $upscope $end 22 | $enddefinitions $end 23 | #0 24 | $dumpvars 25 | b10000000 ( 26 | b1111110000000 ' 27 | b1111111 & 28 | b1111111 % 29 | b10000000 $ 30 | b1111100000000 # 31 | b1111100000000 " 32 | b10000000 ! 33 | $end 34 | #100 35 | b1111100000001 " 36 | b1111100000001 # 37 | #200 38 | b1111100000010 " 39 | b1111100000010 # 40 | #300 41 | b1111100000011 " 42 | b1111100000011 # 43 | #400 44 | b1111100000100 " 45 | b1111100000100 # 46 | #500 47 | b1111100000101 " 48 | b1111100000101 # 49 | #600 50 | b1111100000110 " 51 | b1111100000110 # 52 | #700 53 | b1111100000111 " 54 | b1111100000111 # 55 | #800 56 | b1111100001000 " 57 | b1111100001000 # 58 | #900 59 | b1111100001001 " 60 | b1111100001001 # 61 | #1000 62 | b1111100001010 " 63 | b1111100001010 # 64 | #1100 65 | b1111100001011 " 66 | b1111100001011 # 67 | #1200 68 | b1111100001100 " 69 | b1111100001100 # 70 | #1300 71 | b1111100001101 " 72 | b1111100001101 # 73 | #1400 74 | b1111100001110 " 75 | b1111100001110 # 76 | #1500 77 | b1111100001111 " 78 | b1111100001111 # 79 | #1600 80 | b1111100010000 " 81 | b1111100010000 # 82 | #1700 83 | b1111100010001 " 84 | b1111100010001 # 85 | #1800 86 | b1111100010010 " 87 | b1111100010010 # 88 | #1900 89 | b1111100010011 " 90 | b1111100010011 # 91 | #2000 92 | b1111100010100 " 93 | b1111100010100 # 94 | #2100 95 | b1111100010101 " 96 | b1111100010101 # 97 | #2200 98 | b1111100010110 " 99 | b1111100010110 # 100 | #2300 101 | b1111100010111 " 102 | b1111100010111 # 103 | #2400 104 | b1111100011000 " 105 | b1111100011000 # 106 | #2500 107 | b1111100011001 " 108 | b1111100011001 # 109 | #2600 110 | b1111100011010 " 111 | b1111100011010 # 112 | #2700 113 | b1111100011011 " 114 | b1111100011011 # 115 | #2800 116 | b1111100011100 " 117 | b1111100011100 # 118 | #2900 119 | b1111100011101 " 120 | b1111100011101 # 121 | #3000 122 | b1111100011110 " 123 | b1111100011110 # 124 | #3100 125 | b1111100011111 " 126 | b1111100011111 # 127 | #3200 128 | b1111100100000 " 129 | b1111100100000 # 130 | #3300 131 | b1111100100001 " 132 | b1111100100001 # 133 | #3400 134 | b1111100100010 " 135 | b1111100100010 # 136 | #3500 137 | b1111100100011 " 138 | b1111100100011 # 139 | #3600 140 | b1111100100100 " 141 | b1111100100100 # 142 | #3700 143 | b1111100100101 " 144 | b1111100100101 # 145 | #3800 146 | b1111100100110 " 147 | b1111100100110 # 148 | #3900 149 | b1111100100111 " 150 | b1111100100111 # 151 | #4000 152 | b1111100101000 " 153 | b1111100101000 # 154 | #4100 155 | b1111100101001 " 156 | b1111100101001 # 157 | #4200 158 | b1111100101010 " 159 | b1111100101010 # 160 | #4300 161 | b1111100101011 " 162 | b1111100101011 # 163 | #4400 164 | b1111100101100 " 165 | b1111100101100 # 166 | #4500 167 | b1111100101101 " 168 | b1111100101101 # 169 | #4600 170 | b1111100101110 " 171 | b1111100101110 # 172 | #4700 173 | b1111100101111 " 174 | b1111100101111 # 175 | #4800 176 | b1111100110000 " 177 | b1111100110000 # 178 | #4900 179 | b1111100110001 " 180 | b1111100110001 # 181 | #5000 182 | b1111100110010 " 183 | b1111100110010 # 184 | #5100 185 | b1111100110011 " 186 | b1111100110011 # 187 | #5200 188 | b1111100110100 " 189 | b1111100110100 # 190 | #5300 191 | b1111100110101 " 192 | b1111100110101 # 193 | #5400 194 | b1111100110110 " 195 | b1111100110110 # 196 | #5500 197 | b1111100110111 " 198 | b1111100110111 # 199 | #5600 200 | b1111100111000 " 201 | b1111100111000 # 202 | #5700 203 | b1111100111001 " 204 | b1111100111001 # 205 | #5800 206 | b1111100111010 " 207 | b1111100111010 # 208 | #5900 209 | b1111100111011 " 210 | b1111100111011 # 211 | #6000 212 | b1111100111100 " 213 | b1111100111100 # 214 | #6100 215 | b1111100111101 " 216 | b1111100111101 # 217 | #6200 218 | b1111100111110 " 219 | b1111100111110 # 220 | #6300 221 | b1111100111111 " 222 | b1111100111111 # 223 | #6400 224 | b1111101000000 " 225 | b1111101000000 # 226 | #6500 227 | b1111101000001 " 228 | b1111101000001 # 229 | #6600 230 | b1111101000010 " 231 | b1111101000010 # 232 | #6700 233 | b1111101000011 " 234 | b1111101000011 # 235 | #6800 236 | b1111101000100 " 237 | b1111101000100 # 238 | #6900 239 | b1111101000101 " 240 | b1111101000101 # 241 | #7000 242 | b1111101000110 " 243 | b1111101000110 # 244 | #7100 245 | b1111101000111 " 246 | b1111101000111 # 247 | #7200 248 | b1111101001000 " 249 | b1111101001000 # 250 | #7300 251 | b1111101001001 " 252 | b1111101001001 # 253 | #7400 254 | b1111101001010 " 255 | b1111101001010 # 256 | #7500 257 | b1111101001011 " 258 | b1111101001011 # 259 | #7600 260 | b1111101001100 " 261 | b1111101001100 # 262 | #7700 263 | b1111101001101 " 264 | b1111101001101 # 265 | #7800 266 | b1111101001110 " 267 | b1111101001110 # 268 | #7900 269 | b1111101001111 " 270 | b1111101001111 # 271 | #8000 272 | b1111101010000 " 273 | b1111101010000 # 274 | #8100 275 | b1111101010001 " 276 | b1111101010001 # 277 | #8200 278 | b1111101010010 " 279 | b1111101010010 # 280 | #8300 281 | b1111101010011 " 282 | b1111101010011 # 283 | #8400 284 | b1111101010100 " 285 | b1111101010100 # 286 | #8500 287 | b1111101010101 " 288 | b1111101010101 # 289 | #8600 290 | b1111101010110 " 291 | b1111101010110 # 292 | #8700 293 | b1111101010111 " 294 | b1111101010111 # 295 | #8800 296 | b1111101011000 " 297 | b1111101011000 # 298 | #8900 299 | b1111101011001 " 300 | b1111101011001 # 301 | #9000 302 | b1111101011010 " 303 | b1111101011010 # 304 | #9100 305 | b1111101011011 " 306 | b1111101011011 # 307 | #9200 308 | b1111101011100 " 309 | b1111101011100 # 310 | #9300 311 | b1111101011101 " 312 | b1111101011101 # 313 | #9400 314 | b1111101011110 " 315 | b1111101011110 # 316 | #9500 317 | b1111101011111 " 318 | b1111101011111 # 319 | #9600 320 | b1111101100000 " 321 | b1111101100000 # 322 | #9700 323 | b1111101100001 " 324 | b1111101100001 # 325 | #9800 326 | b1111101100010 " 327 | b1111101100010 # 328 | #9900 329 | b1111101100011 " 330 | b1111101100011 # 331 | #10000 332 | b1111101100100 " 333 | b1111101100100 # 334 | #10100 335 | b1111101100101 " 336 | b1111101100101 # 337 | #10200 338 | b1111101100110 " 339 | b1111101100110 # 340 | #10300 341 | b1111101100111 " 342 | b1111101100111 # 343 | #10400 344 | b1111101101000 " 345 | b1111101101000 # 346 | #10500 347 | b1111101101001 " 348 | b1111101101001 # 349 | #10600 350 | b1111101101010 " 351 | b1111101101010 # 352 | #10700 353 | b1111101101011 " 354 | b1111101101011 # 355 | #10800 356 | b1111101101100 " 357 | b1111101101100 # 358 | #10900 359 | b1111101101101 " 360 | b1111101101101 # 361 | #11000 362 | b1111101101110 " 363 | b1111101101110 # 364 | #11100 365 | b1111101101111 " 366 | b1111101101111 # 367 | #11200 368 | b1111101110000 " 369 | b1111101110000 # 370 | #11300 371 | b1111101110001 " 372 | b1111101110001 # 373 | #11400 374 | b1111101110010 " 375 | b1111101110010 # 376 | #11500 377 | b1111101110011 " 378 | b1111101110011 # 379 | #11600 380 | b1111101110100 " 381 | b1111101110100 # 382 | #11700 383 | b1111101110101 " 384 | b1111101110101 # 385 | #11800 386 | b1111101110110 " 387 | b1111101110110 # 388 | #11900 389 | b1111101110111 " 390 | b1111101110111 # 391 | #12000 392 | b1111101111000 " 393 | b1111101111000 # 394 | #12100 395 | b1111101111001 " 396 | b1111101111001 # 397 | #12200 398 | b1111101111010 " 399 | b1111101111010 # 400 | #12300 401 | b1111101111011 " 402 | b1111101111011 # 403 | #12400 404 | b1111101111100 " 405 | b1111101111100 # 406 | #12500 407 | b1111101111101 " 408 | b1111101111101 # 409 | #12600 410 | b1111101111110 " 411 | b1111101111110 # 412 | #12700 413 | b1111101111111 " 414 | b1111101111111 # 415 | #12800 416 | b10000000 ! 417 | b10000000 $ 418 | b1111110000000 " 419 | b1111110000000 # 420 | #12900 421 | b10000001 ! 422 | b10000001 $ 423 | b1111110000001 " 424 | b1111110000001 # 425 | #13000 426 | b10000010 ! 427 | b10000010 $ 428 | b1111110000010 " 429 | b1111110000010 # 430 | #13100 431 | b10000011 ! 432 | b10000011 $ 433 | b1111110000011 " 434 | b1111110000011 # 435 | #13200 436 | b10000100 ! 437 | b10000100 $ 438 | b1111110000100 " 439 | b1111110000100 # 440 | #13300 441 | b10000101 ! 442 | b10000101 $ 443 | b1111110000101 " 444 | b1111110000101 # 445 | #13400 446 | b10000110 ! 447 | b10000110 $ 448 | b1111110000110 " 449 | b1111110000110 # 450 | #13500 451 | b10000111 ! 452 | b10000111 $ 453 | b1111110000111 " 454 | b1111110000111 # 455 | #13600 456 | b10001000 ! 457 | b10001000 $ 458 | b1111110001000 " 459 | b1111110001000 # 460 | #13700 461 | b10001001 ! 462 | b10001001 $ 463 | b1111110001001 " 464 | b1111110001001 # 465 | #13800 466 | b10001010 ! 467 | b10001010 $ 468 | b1111110001010 " 469 | b1111110001010 # 470 | #13900 471 | b10001011 ! 472 | b10001011 $ 473 | b1111110001011 " 474 | b1111110001011 # 475 | #14000 476 | b10001100 ! 477 | b10001100 $ 478 | b1111110001100 " 479 | b1111110001100 # 480 | #14100 481 | b10001101 ! 482 | b10001101 $ 483 | b1111110001101 " 484 | b1111110001101 # 485 | #14200 486 | b10001110 ! 487 | b10001110 $ 488 | b1111110001110 " 489 | b1111110001110 # 490 | #14300 491 | b10001111 ! 492 | b10001111 $ 493 | b1111110001111 " 494 | b1111110001111 # 495 | #14400 496 | b10010000 ! 497 | b10010000 $ 498 | b1111110010000 " 499 | b1111110010000 # 500 | #14500 501 | b10010001 ! 502 | b10010001 $ 503 | b1111110010001 " 504 | b1111110010001 # 505 | #14600 506 | b10010010 ! 507 | b10010010 $ 508 | b1111110010010 " 509 | b1111110010010 # 510 | #14700 511 | b10010011 ! 512 | b10010011 $ 513 | b1111110010011 " 514 | b1111110010011 # 515 | #14800 516 | b10010100 ! 517 | b10010100 $ 518 | b1111110010100 " 519 | b1111110010100 # 520 | #14900 521 | b10010101 ! 522 | b10010101 $ 523 | b1111110010101 " 524 | b1111110010101 # 525 | #15000 526 | b10010110 ! 527 | b10010110 $ 528 | b1111110010110 " 529 | b1111110010110 # 530 | #15100 531 | b10010111 ! 532 | b10010111 $ 533 | b1111110010111 " 534 | b1111110010111 # 535 | #15200 536 | b10011000 ! 537 | b10011000 $ 538 | b1111110011000 " 539 | b1111110011000 # 540 | #15300 541 | b10011001 ! 542 | b10011001 $ 543 | b1111110011001 " 544 | b1111110011001 # 545 | #15400 546 | b10011010 ! 547 | b10011010 $ 548 | b1111110011010 " 549 | b1111110011010 # 550 | #15500 551 | b10011011 ! 552 | b10011011 $ 553 | b1111110011011 " 554 | b1111110011011 # 555 | #15600 556 | b10011100 ! 557 | b10011100 $ 558 | b1111110011100 " 559 | b1111110011100 # 560 | #15700 561 | b10011101 ! 562 | b10011101 $ 563 | b1111110011101 " 564 | b1111110011101 # 565 | #15800 566 | b10011110 ! 567 | b10011110 $ 568 | b1111110011110 " 569 | b1111110011110 # 570 | #15900 571 | b10011111 ! 572 | b10011111 $ 573 | b1111110011111 " 574 | b1111110011111 # 575 | #16000 576 | b10100000 ! 577 | b10100000 $ 578 | b1111110100000 " 579 | b1111110100000 # 580 | #16100 581 | b10100001 ! 582 | b10100001 $ 583 | b1111110100001 " 584 | b1111110100001 # 585 | #16200 586 | b10100010 ! 587 | b10100010 $ 588 | b1111110100010 " 589 | b1111110100010 # 590 | #16300 591 | b10100011 ! 592 | b10100011 $ 593 | b1111110100011 " 594 | b1111110100011 # 595 | #16400 596 | b10100100 ! 597 | b10100100 $ 598 | b1111110100100 " 599 | b1111110100100 # 600 | #16500 601 | b10100101 ! 602 | b10100101 $ 603 | b1111110100101 " 604 | b1111110100101 # 605 | #16600 606 | b10100110 ! 607 | b10100110 $ 608 | b1111110100110 " 609 | b1111110100110 # 610 | #16700 611 | b10100111 ! 612 | b10100111 $ 613 | b1111110100111 " 614 | b1111110100111 # 615 | #16800 616 | b10101000 ! 617 | b10101000 $ 618 | b1111110101000 " 619 | b1111110101000 # 620 | #16900 621 | b10101001 ! 622 | b10101001 $ 623 | b1111110101001 " 624 | b1111110101001 # 625 | #17000 626 | b10101010 ! 627 | b10101010 $ 628 | b1111110101010 " 629 | b1111110101010 # 630 | #17100 631 | b10101011 ! 632 | b10101011 $ 633 | b1111110101011 " 634 | b1111110101011 # 635 | #17200 636 | b10101100 ! 637 | b10101100 $ 638 | b1111110101100 " 639 | b1111110101100 # 640 | #17300 641 | b10101101 ! 642 | b10101101 $ 643 | b1111110101101 " 644 | b1111110101101 # 645 | #17400 646 | b10101110 ! 647 | b10101110 $ 648 | b1111110101110 " 649 | b1111110101110 # 650 | #17500 651 | b10101111 ! 652 | b10101111 $ 653 | b1111110101111 " 654 | b1111110101111 # 655 | #17600 656 | b10110000 ! 657 | b10110000 $ 658 | b1111110110000 " 659 | b1111110110000 # 660 | #17700 661 | b10110001 ! 662 | b10110001 $ 663 | b1111110110001 " 664 | b1111110110001 # 665 | #17800 666 | b10110010 ! 667 | b10110010 $ 668 | b1111110110010 " 669 | b1111110110010 # 670 | #17900 671 | b10110011 ! 672 | b10110011 $ 673 | b1111110110011 " 674 | b1111110110011 # 675 | #18000 676 | b10110100 ! 677 | b10110100 $ 678 | b1111110110100 " 679 | b1111110110100 # 680 | #18100 681 | b10110101 ! 682 | b10110101 $ 683 | b1111110110101 " 684 | b1111110110101 # 685 | #18200 686 | b10110110 ! 687 | b10110110 $ 688 | b1111110110110 " 689 | b1111110110110 # 690 | #18300 691 | b10110111 ! 692 | b10110111 $ 693 | b1111110110111 " 694 | b1111110110111 # 695 | #18400 696 | b10111000 ! 697 | b10111000 $ 698 | b1111110111000 " 699 | b1111110111000 # 700 | #18500 701 | b10111001 ! 702 | b10111001 $ 703 | b1111110111001 " 704 | b1111110111001 # 705 | #18600 706 | b10111010 ! 707 | b10111010 $ 708 | b1111110111010 " 709 | b1111110111010 # 710 | #18700 711 | b10111011 ! 712 | b10111011 $ 713 | b1111110111011 " 714 | b1111110111011 # 715 | #18800 716 | b10111100 ! 717 | b10111100 $ 718 | b1111110111100 " 719 | b1111110111100 # 720 | #18900 721 | b10111101 ! 722 | b10111101 $ 723 | b1111110111101 " 724 | b1111110111101 # 725 | #19000 726 | b10111110 ! 727 | b10111110 $ 728 | b1111110111110 " 729 | b1111110111110 # 730 | #19100 731 | b10111111 ! 732 | b10111111 $ 733 | b1111110111111 " 734 | b1111110111111 # 735 | #19200 736 | b11000000 ! 737 | b11000000 $ 738 | b1111111000000 " 739 | b1111111000000 # 740 | #19300 741 | b11000001 ! 742 | b11000001 $ 743 | b1111111000001 " 744 | b1111111000001 # 745 | #19400 746 | b11000010 ! 747 | b11000010 $ 748 | b1111111000010 " 749 | b1111111000010 # 750 | #19500 751 | b11000011 ! 752 | b11000011 $ 753 | b1111111000011 " 754 | b1111111000011 # 755 | #19600 756 | b11000100 ! 757 | b11000100 $ 758 | b1111111000100 " 759 | b1111111000100 # 760 | #19700 761 | b11000101 ! 762 | b11000101 $ 763 | b1111111000101 " 764 | b1111111000101 # 765 | #19800 766 | b11000110 ! 767 | b11000110 $ 768 | b1111111000110 " 769 | b1111111000110 # 770 | #19900 771 | b11000111 ! 772 | b11000111 $ 773 | b1111111000111 " 774 | b1111111000111 # 775 | #20000 776 | b11001000 ! 777 | b11001000 $ 778 | b1111111001000 " 779 | b1111111001000 # 780 | #20100 781 | b11001001 ! 782 | b11001001 $ 783 | b1111111001001 " 784 | b1111111001001 # 785 | #20200 786 | b11001010 ! 787 | b11001010 $ 788 | b1111111001010 " 789 | b1111111001010 # 790 | #20300 791 | b11001011 ! 792 | b11001011 $ 793 | b1111111001011 " 794 | b1111111001011 # 795 | #20400 796 | b11001100 ! 797 | b11001100 $ 798 | b1111111001100 " 799 | b1111111001100 # 800 | #20500 801 | b11001101 ! 802 | b11001101 $ 803 | b1111111001101 " 804 | b1111111001101 # 805 | #20600 806 | b11001110 ! 807 | b11001110 $ 808 | b1111111001110 " 809 | b1111111001110 # 810 | #20700 811 | b11001111 ! 812 | b11001111 $ 813 | b1111111001111 " 814 | b1111111001111 # 815 | #20800 816 | b11010000 ! 817 | b11010000 $ 818 | b1111111010000 " 819 | b1111111010000 # 820 | #20900 821 | b11010001 ! 822 | b11010001 $ 823 | b1111111010001 " 824 | b1111111010001 # 825 | #21000 826 | b11010010 ! 827 | b11010010 $ 828 | b1111111010010 " 829 | b1111111010010 # 830 | #21100 831 | b11010011 ! 832 | b11010011 $ 833 | b1111111010011 " 834 | b1111111010011 # 835 | #21200 836 | b11010100 ! 837 | b11010100 $ 838 | b1111111010100 " 839 | b1111111010100 # 840 | #21300 841 | b11010101 ! 842 | b11010101 $ 843 | b1111111010101 " 844 | b1111111010101 # 845 | #21400 846 | b11010110 ! 847 | b11010110 $ 848 | b1111111010110 " 849 | b1111111010110 # 850 | #21500 851 | b11010111 ! 852 | b11010111 $ 853 | b1111111010111 " 854 | b1111111010111 # 855 | #21600 856 | b11011000 ! 857 | b11011000 $ 858 | b1111111011000 " 859 | b1111111011000 # 860 | #21700 861 | b11011001 ! 862 | b11011001 $ 863 | b1111111011001 " 864 | b1111111011001 # 865 | #21800 866 | b11011010 ! 867 | b11011010 $ 868 | b1111111011010 " 869 | b1111111011010 # 870 | #21900 871 | b11011011 ! 872 | b11011011 $ 873 | b1111111011011 " 874 | b1111111011011 # 875 | #22000 876 | b11011100 ! 877 | b11011100 $ 878 | b1111111011100 " 879 | b1111111011100 # 880 | #22100 881 | b11011101 ! 882 | b11011101 $ 883 | b1111111011101 " 884 | b1111111011101 # 885 | #22200 886 | b11011110 ! 887 | b11011110 $ 888 | b1111111011110 " 889 | b1111111011110 # 890 | #22300 891 | b11011111 ! 892 | b11011111 $ 893 | b1111111011111 " 894 | b1111111011111 # 895 | #22400 896 | b11100000 ! 897 | b11100000 $ 898 | b1111111100000 " 899 | b1111111100000 # 900 | #22500 901 | b11100001 ! 902 | b11100001 $ 903 | b1111111100001 " 904 | b1111111100001 # 905 | #22600 906 | b11100010 ! 907 | b11100010 $ 908 | b1111111100010 " 909 | b1111111100010 # 910 | #22700 911 | b11100011 ! 912 | b11100011 $ 913 | b1111111100011 " 914 | b1111111100011 # 915 | #22800 916 | b11100100 ! 917 | b11100100 $ 918 | b1111111100100 " 919 | b1111111100100 # 920 | #22900 921 | b11100101 ! 922 | b11100101 $ 923 | b1111111100101 " 924 | b1111111100101 # 925 | #23000 926 | b11100110 ! 927 | b11100110 $ 928 | b1111111100110 " 929 | b1111111100110 # 930 | #23100 931 | b11100111 ! 932 | b11100111 $ 933 | b1111111100111 " 934 | b1111111100111 # 935 | #23200 936 | b11101000 ! 937 | b11101000 $ 938 | b1111111101000 " 939 | b1111111101000 # 940 | #23300 941 | b11101001 ! 942 | b11101001 $ 943 | b1111111101001 " 944 | b1111111101001 # 945 | #23400 946 | b11101010 ! 947 | b11101010 $ 948 | b1111111101010 " 949 | b1111111101010 # 950 | #23500 951 | b11101011 ! 952 | b11101011 $ 953 | b1111111101011 " 954 | b1111111101011 # 955 | #23600 956 | b11101100 ! 957 | b11101100 $ 958 | b1111111101100 " 959 | b1111111101100 # 960 | #23700 961 | b11101101 ! 962 | b11101101 $ 963 | b1111111101101 " 964 | b1111111101101 # 965 | #23800 966 | b11101110 ! 967 | b11101110 $ 968 | b1111111101110 " 969 | b1111111101110 # 970 | #23900 971 | b11101111 ! 972 | b11101111 $ 973 | b1111111101111 " 974 | b1111111101111 # 975 | #24000 976 | b11110000 ! 977 | b11110000 $ 978 | b1111111110000 " 979 | b1111111110000 # 980 | #24100 981 | b11110001 ! 982 | b11110001 $ 983 | b1111111110001 " 984 | b1111111110001 # 985 | #24200 986 | b11110010 ! 987 | b11110010 $ 988 | b1111111110010 " 989 | b1111111110010 # 990 | #24300 991 | b11110011 ! 992 | b11110011 $ 993 | b1111111110011 " 994 | b1111111110011 # 995 | #24400 996 | b11110100 ! 997 | b11110100 $ 998 | b1111111110100 " 999 | b1111111110100 # 1000 | #24500 1001 | b11110101 ! 1002 | b11110101 $ 1003 | b1111111110101 " 1004 | b1111111110101 # 1005 | #24600 1006 | b11110110 ! 1007 | b11110110 $ 1008 | b1111111110110 " 1009 | b1111111110110 # 1010 | #24700 1011 | b11110111 ! 1012 | b11110111 $ 1013 | b1111111110111 " 1014 | b1111111110111 # 1015 | #24800 1016 | b11111000 ! 1017 | b11111000 $ 1018 | b1111111111000 " 1019 | b1111111111000 # 1020 | #24900 1021 | b11111001 ! 1022 | b11111001 $ 1023 | b1111111111001 " 1024 | b1111111111001 # 1025 | #25000 1026 | b11111010 ! 1027 | b11111010 $ 1028 | b1111111111010 " 1029 | b1111111111010 # 1030 | #25100 1031 | b11111011 ! 1032 | b11111011 $ 1033 | b1111111111011 " 1034 | b1111111111011 # 1035 | #25200 1036 | b11111100 ! 1037 | b11111100 $ 1038 | b1111111111100 " 1039 | b1111111111100 # 1040 | #25300 1041 | b11111101 ! 1042 | b11111101 $ 1043 | b1111111111101 " 1044 | b1111111111101 # 1045 | #25400 1046 | b11111110 ! 1047 | b11111110 $ 1048 | b1111111111110 " 1049 | b1111111111110 # 1050 | #25500 1051 | b11111111 ! 1052 | b11111111 $ 1053 | b1111111111111 " 1054 | b1111111111111 # 1055 | #25600 1056 | b0 ! 1057 | b0 $ 1058 | b0 " 1059 | b0 # 1060 | #25700 1061 | b1 ! 1062 | b1 $ 1063 | b1 " 1064 | b1 # 1065 | #25800 1066 | b10 ! 1067 | b10 $ 1068 | b10 " 1069 | b10 # 1070 | #25900 1071 | b11 ! 1072 | b11 $ 1073 | b11 " 1074 | b11 # 1075 | #26000 1076 | b100 ! 1077 | b100 $ 1078 | b100 " 1079 | b100 # 1080 | #26100 1081 | b101 ! 1082 | b101 $ 1083 | b101 " 1084 | b101 # 1085 | #26200 1086 | b110 ! 1087 | b110 $ 1088 | b110 " 1089 | b110 # 1090 | #26300 1091 | b111 ! 1092 | b111 $ 1093 | b111 " 1094 | b111 # 1095 | #26400 1096 | b1000 ! 1097 | b1000 $ 1098 | b1000 " 1099 | b1000 # 1100 | #26500 1101 | b1001 ! 1102 | b1001 $ 1103 | b1001 " 1104 | b1001 # 1105 | #26600 1106 | b1010 ! 1107 | b1010 $ 1108 | b1010 " 1109 | b1010 # 1110 | #26700 1111 | b1011 ! 1112 | b1011 $ 1113 | b1011 " 1114 | b1011 # 1115 | #26800 1116 | b1100 ! 1117 | b1100 $ 1118 | b1100 " 1119 | b1100 # 1120 | #26900 1121 | b1101 ! 1122 | b1101 $ 1123 | b1101 " 1124 | b1101 # 1125 | #27000 1126 | b1110 ! 1127 | b1110 $ 1128 | b1110 " 1129 | b1110 # 1130 | #27100 1131 | b1111 ! 1132 | b1111 $ 1133 | b1111 " 1134 | b1111 # 1135 | #27200 1136 | b10000 ! 1137 | b10000 $ 1138 | b10000 " 1139 | b10000 # 1140 | #27300 1141 | b10001 ! 1142 | b10001 $ 1143 | b10001 " 1144 | b10001 # 1145 | #27400 1146 | b10010 ! 1147 | b10010 $ 1148 | b10010 " 1149 | b10010 # 1150 | #27500 1151 | b10011 ! 1152 | b10011 $ 1153 | b10011 " 1154 | b10011 # 1155 | #27600 1156 | b10100 ! 1157 | b10100 $ 1158 | b10100 " 1159 | b10100 # 1160 | #27700 1161 | b10101 ! 1162 | b10101 $ 1163 | b10101 " 1164 | b10101 # 1165 | #27800 1166 | b10110 ! 1167 | b10110 $ 1168 | b10110 " 1169 | b10110 # 1170 | #27900 1171 | b10111 ! 1172 | b10111 $ 1173 | b10111 " 1174 | b10111 # 1175 | #28000 1176 | b11000 ! 1177 | b11000 $ 1178 | b11000 " 1179 | b11000 # 1180 | #28100 1181 | b11001 ! 1182 | b11001 $ 1183 | b11001 " 1184 | b11001 # 1185 | #28200 1186 | b11010 ! 1187 | b11010 $ 1188 | b11010 " 1189 | b11010 # 1190 | #28300 1191 | b11011 ! 1192 | b11011 $ 1193 | b11011 " 1194 | b11011 # 1195 | #28400 1196 | b11100 ! 1197 | b11100 $ 1198 | b11100 " 1199 | b11100 # 1200 | #28500 1201 | b11101 ! 1202 | b11101 $ 1203 | b11101 " 1204 | b11101 # 1205 | #28600 1206 | b11110 ! 1207 | b11110 $ 1208 | b11110 " 1209 | b11110 # 1210 | #28700 1211 | b11111 ! 1212 | b11111 $ 1213 | b11111 " 1214 | b11111 # 1215 | #28800 1216 | b100000 ! 1217 | b100000 $ 1218 | b100000 " 1219 | b100000 # 1220 | #28900 1221 | b100001 ! 1222 | b100001 $ 1223 | b100001 " 1224 | b100001 # 1225 | #29000 1226 | b100010 ! 1227 | b100010 $ 1228 | b100010 " 1229 | b100010 # 1230 | #29100 1231 | b100011 ! 1232 | b100011 $ 1233 | b100011 " 1234 | b100011 # 1235 | #29200 1236 | b100100 ! 1237 | b100100 $ 1238 | b100100 " 1239 | b100100 # 1240 | #29300 1241 | b100101 ! 1242 | b100101 $ 1243 | b100101 " 1244 | b100101 # 1245 | #29400 1246 | b100110 ! 1247 | b100110 $ 1248 | b100110 " 1249 | b100110 # 1250 | #29500 1251 | b100111 ! 1252 | b100111 $ 1253 | b100111 " 1254 | b100111 # 1255 | #29600 1256 | b101000 ! 1257 | b101000 $ 1258 | b101000 " 1259 | b101000 # 1260 | #29700 1261 | b101001 ! 1262 | b101001 $ 1263 | b101001 " 1264 | b101001 # 1265 | #29800 1266 | b101010 ! 1267 | b101010 $ 1268 | b101010 " 1269 | b101010 # 1270 | #29900 1271 | b101011 ! 1272 | b101011 $ 1273 | b101011 " 1274 | b101011 # 1275 | #30000 1276 | b101100 ! 1277 | b101100 $ 1278 | b101100 " 1279 | b101100 # 1280 | #30100 1281 | b101101 ! 1282 | b101101 $ 1283 | b101101 " 1284 | b101101 # 1285 | #30200 1286 | b101110 ! 1287 | b101110 $ 1288 | b101110 " 1289 | b101110 # 1290 | #30300 1291 | b101111 ! 1292 | b101111 $ 1293 | b101111 " 1294 | b101111 # 1295 | #30400 1296 | b110000 ! 1297 | b110000 $ 1298 | b110000 " 1299 | b110000 # 1300 | #30500 1301 | b110001 ! 1302 | b110001 $ 1303 | b110001 " 1304 | b110001 # 1305 | #30600 1306 | b110010 ! 1307 | b110010 $ 1308 | b110010 " 1309 | b110010 # 1310 | #30700 1311 | b110011 ! 1312 | b110011 $ 1313 | b110011 " 1314 | b110011 # 1315 | #30800 1316 | b110100 ! 1317 | b110100 $ 1318 | b110100 " 1319 | b110100 # 1320 | #30900 1321 | b110101 ! 1322 | b110101 $ 1323 | b110101 " 1324 | b110101 # 1325 | #31000 1326 | b110110 ! 1327 | b110110 $ 1328 | b110110 " 1329 | b110110 # 1330 | #31100 1331 | b110111 ! 1332 | b110111 $ 1333 | b110111 " 1334 | b110111 # 1335 | #31200 1336 | b111000 ! 1337 | b111000 $ 1338 | b111000 " 1339 | b111000 # 1340 | #31300 1341 | b111001 ! 1342 | b111001 $ 1343 | b111001 " 1344 | b111001 # 1345 | #31400 1346 | b111010 ! 1347 | b111010 $ 1348 | b111010 " 1349 | b111010 # 1350 | #31500 1351 | b111011 ! 1352 | b111011 $ 1353 | b111011 " 1354 | b111011 # 1355 | #31600 1356 | b111100 ! 1357 | b111100 $ 1358 | b111100 " 1359 | b111100 # 1360 | #31700 1361 | b111101 ! 1362 | b111101 $ 1363 | b111101 " 1364 | b111101 # 1365 | #31800 1366 | b111110 ! 1367 | b111110 $ 1368 | b111110 " 1369 | b111110 # 1370 | #31900 1371 | b111111 ! 1372 | b111111 $ 1373 | b111111 " 1374 | b111111 # 1375 | #32000 1376 | b1000000 ! 1377 | b1000000 $ 1378 | b1000000 " 1379 | b1000000 # 1380 | #32100 1381 | b1000001 ! 1382 | b1000001 $ 1383 | b1000001 " 1384 | b1000001 # 1385 | #32200 1386 | b1000010 ! 1387 | b1000010 $ 1388 | b1000010 " 1389 | b1000010 # 1390 | #32300 1391 | b1000011 ! 1392 | b1000011 $ 1393 | b1000011 " 1394 | b1000011 # 1395 | #32400 1396 | b1000100 ! 1397 | b1000100 $ 1398 | b1000100 " 1399 | b1000100 # 1400 | #32500 1401 | b1000101 ! 1402 | b1000101 $ 1403 | b1000101 " 1404 | b1000101 # 1405 | #32600 1406 | b1000110 ! 1407 | b1000110 $ 1408 | b1000110 " 1409 | b1000110 # 1410 | #32700 1411 | b1000111 ! 1412 | b1000111 $ 1413 | b1000111 " 1414 | b1000111 # 1415 | #32800 1416 | b1001000 ! 1417 | b1001000 $ 1418 | b1001000 " 1419 | b1001000 # 1420 | #32900 1421 | b1001001 ! 1422 | b1001001 $ 1423 | b1001001 " 1424 | b1001001 # 1425 | #33000 1426 | b1001010 ! 1427 | b1001010 $ 1428 | b1001010 " 1429 | b1001010 # 1430 | #33100 1431 | b1001011 ! 1432 | b1001011 $ 1433 | b1001011 " 1434 | b1001011 # 1435 | #33200 1436 | b1001100 ! 1437 | b1001100 $ 1438 | b1001100 " 1439 | b1001100 # 1440 | #33300 1441 | b1001101 ! 1442 | b1001101 $ 1443 | b1001101 " 1444 | b1001101 # 1445 | #33400 1446 | b1001110 ! 1447 | b1001110 $ 1448 | b1001110 " 1449 | b1001110 # 1450 | #33500 1451 | b1001111 ! 1452 | b1001111 $ 1453 | b1001111 " 1454 | b1001111 # 1455 | #33600 1456 | b1010000 ! 1457 | b1010000 $ 1458 | b1010000 " 1459 | b1010000 # 1460 | #33700 1461 | b1010001 ! 1462 | b1010001 $ 1463 | b1010001 " 1464 | b1010001 # 1465 | #33800 1466 | b1010010 ! 1467 | b1010010 $ 1468 | b1010010 " 1469 | b1010010 # 1470 | #33900 1471 | b1010011 ! 1472 | b1010011 $ 1473 | b1010011 " 1474 | b1010011 # 1475 | #34000 1476 | b1010100 ! 1477 | b1010100 $ 1478 | b1010100 " 1479 | b1010100 # 1480 | #34100 1481 | b1010101 ! 1482 | b1010101 $ 1483 | b1010101 " 1484 | b1010101 # 1485 | #34200 1486 | b1010110 ! 1487 | b1010110 $ 1488 | b1010110 " 1489 | b1010110 # 1490 | #34300 1491 | b1010111 ! 1492 | b1010111 $ 1493 | b1010111 " 1494 | b1010111 # 1495 | #34400 1496 | b1011000 ! 1497 | b1011000 $ 1498 | b1011000 " 1499 | b1011000 # 1500 | #34500 1501 | b1011001 ! 1502 | b1011001 $ 1503 | b1011001 " 1504 | b1011001 # 1505 | #34600 1506 | b1011010 ! 1507 | b1011010 $ 1508 | b1011010 " 1509 | b1011010 # 1510 | #34700 1511 | b1011011 ! 1512 | b1011011 $ 1513 | b1011011 " 1514 | b1011011 # 1515 | #34800 1516 | b1011100 ! 1517 | b1011100 $ 1518 | b1011100 " 1519 | b1011100 # 1520 | #34900 1521 | b1011101 ! 1522 | b1011101 $ 1523 | b1011101 " 1524 | b1011101 # 1525 | #35000 1526 | b1011110 ! 1527 | b1011110 $ 1528 | b1011110 " 1529 | b1011110 # 1530 | #35100 1531 | b1011111 ! 1532 | b1011111 $ 1533 | b1011111 " 1534 | b1011111 # 1535 | #35200 1536 | b1100000 ! 1537 | b1100000 $ 1538 | b1100000 " 1539 | b1100000 # 1540 | #35300 1541 | b1100001 ! 1542 | b1100001 $ 1543 | b1100001 " 1544 | b1100001 # 1545 | #35400 1546 | b1100010 ! 1547 | b1100010 $ 1548 | b1100010 " 1549 | b1100010 # 1550 | #35500 1551 | b1100011 ! 1552 | b1100011 $ 1553 | b1100011 " 1554 | b1100011 # 1555 | #35600 1556 | b1100100 ! 1557 | b1100100 $ 1558 | b1100100 " 1559 | b1100100 # 1560 | #35700 1561 | b1100101 ! 1562 | b1100101 $ 1563 | b1100101 " 1564 | b1100101 # 1565 | #35800 1566 | b1100110 ! 1567 | b1100110 $ 1568 | b1100110 " 1569 | b1100110 # 1570 | #35900 1571 | b1100111 ! 1572 | b1100111 $ 1573 | b1100111 " 1574 | b1100111 # 1575 | #36000 1576 | b1101000 ! 1577 | b1101000 $ 1578 | b1101000 " 1579 | b1101000 # 1580 | #36100 1581 | b1101001 ! 1582 | b1101001 $ 1583 | b1101001 " 1584 | b1101001 # 1585 | #36200 1586 | b1101010 ! 1587 | b1101010 $ 1588 | b1101010 " 1589 | b1101010 # 1590 | #36300 1591 | b1101011 ! 1592 | b1101011 $ 1593 | b1101011 " 1594 | b1101011 # 1595 | #36400 1596 | b1101100 ! 1597 | b1101100 $ 1598 | b1101100 " 1599 | b1101100 # 1600 | #36500 1601 | b1101101 ! 1602 | b1101101 $ 1603 | b1101101 " 1604 | b1101101 # 1605 | #36600 1606 | b1101110 ! 1607 | b1101110 $ 1608 | b1101110 " 1609 | b1101110 # 1610 | #36700 1611 | b1101111 ! 1612 | b1101111 $ 1613 | b1101111 " 1614 | b1101111 # 1615 | #36800 1616 | b1110000 ! 1617 | b1110000 $ 1618 | b1110000 " 1619 | b1110000 # 1620 | #36900 1621 | b1110001 ! 1622 | b1110001 $ 1623 | b1110001 " 1624 | b1110001 # 1625 | #37000 1626 | b1110010 ! 1627 | b1110010 $ 1628 | b1110010 " 1629 | b1110010 # 1630 | #37100 1631 | b1110011 ! 1632 | b1110011 $ 1633 | b1110011 " 1634 | b1110011 # 1635 | #37200 1636 | b1110100 ! 1637 | b1110100 $ 1638 | b1110100 " 1639 | b1110100 # 1640 | #37300 1641 | b1110101 ! 1642 | b1110101 $ 1643 | b1110101 " 1644 | b1110101 # 1645 | #37400 1646 | b1110110 ! 1647 | b1110110 $ 1648 | b1110110 " 1649 | b1110110 # 1650 | #37500 1651 | b1110111 ! 1652 | b1110111 $ 1653 | b1110111 " 1654 | b1110111 # 1655 | #37600 1656 | b1111000 ! 1657 | b1111000 $ 1658 | b1111000 " 1659 | b1111000 # 1660 | #37700 1661 | b1111001 ! 1662 | b1111001 $ 1663 | b1111001 " 1664 | b1111001 # 1665 | #37800 1666 | b1111010 ! 1667 | b1111010 $ 1668 | b1111010 " 1669 | b1111010 # 1670 | #37900 1671 | b1111011 ! 1672 | b1111011 $ 1673 | b1111011 " 1674 | b1111011 # 1675 | #38000 1676 | b1111100 ! 1677 | b1111100 $ 1678 | b1111100 " 1679 | b1111100 # 1680 | #38100 1681 | b1111101 ! 1682 | b1111101 $ 1683 | b1111101 " 1684 | b1111101 # 1685 | #38200 1686 | b1111110 ! 1687 | b1111110 $ 1688 | b1111110 " 1689 | b1111110 # 1690 | #38300 1691 | b1111111 ! 1692 | b1111111 $ 1693 | b1111111 " 1694 | b1111111 # 1695 | #38400 1696 | b10000000 " 1697 | b10000000 # 1698 | #38500 1699 | b10000001 " 1700 | b10000001 # 1701 | #38600 1702 | b10000010 " 1703 | b10000010 # 1704 | #38700 1705 | b10000011 " 1706 | b10000011 # 1707 | #38800 1708 | b10000100 " 1709 | b10000100 # 1710 | #38900 1711 | b10000101 " 1712 | b10000101 # 1713 | #39000 1714 | b10000110 " 1715 | b10000110 # 1716 | #39100 1717 | b10000111 " 1718 | b10000111 # 1719 | #39200 1720 | b10001000 " 1721 | b10001000 # 1722 | #39300 1723 | b10001001 " 1724 | b10001001 # 1725 | #39400 1726 | b10001010 " 1727 | b10001010 # 1728 | #39500 1729 | b10001011 " 1730 | b10001011 # 1731 | #39600 1732 | b10001100 " 1733 | b10001100 # 1734 | #39700 1735 | b10001101 " 1736 | b10001101 # 1737 | #39800 1738 | b10001110 " 1739 | b10001110 # 1740 | #39900 1741 | b10001111 " 1742 | b10001111 # 1743 | #40000 1744 | b10010000 " 1745 | b10010000 # 1746 | #40100 1747 | b10010001 " 1748 | b10010001 # 1749 | #40200 1750 | b10010010 " 1751 | b10010010 # 1752 | #40300 1753 | b10010011 " 1754 | b10010011 # 1755 | #40400 1756 | b10010100 " 1757 | b10010100 # 1758 | #40500 1759 | b10010101 " 1760 | b10010101 # 1761 | #40600 1762 | b10010110 " 1763 | b10010110 # 1764 | #40700 1765 | b10010111 " 1766 | b10010111 # 1767 | #40800 1768 | b10011000 " 1769 | b10011000 # 1770 | #40900 1771 | b10011001 " 1772 | b10011001 # 1773 | #41000 1774 | b10011010 " 1775 | b10011010 # 1776 | #41100 1777 | b10011011 " 1778 | b10011011 # 1779 | #41200 1780 | b10011100 " 1781 | b10011100 # 1782 | #41300 1783 | b10011101 " 1784 | b10011101 # 1785 | #41400 1786 | b10011110 " 1787 | b10011110 # 1788 | #41500 1789 | b10011111 " 1790 | b10011111 # 1791 | #41600 1792 | b10100000 " 1793 | b10100000 # 1794 | #41700 1795 | b10100001 " 1796 | b10100001 # 1797 | #41800 1798 | b10100010 " 1799 | b10100010 # 1800 | #41900 1801 | b10100011 " 1802 | b10100011 # 1803 | #42000 1804 | b10100100 " 1805 | b10100100 # 1806 | #42100 1807 | b10100101 " 1808 | b10100101 # 1809 | #42200 1810 | b10100110 " 1811 | b10100110 # 1812 | #42300 1813 | b10100111 " 1814 | b10100111 # 1815 | #42400 1816 | b10101000 " 1817 | b10101000 # 1818 | #42500 1819 | b10101001 " 1820 | b10101001 # 1821 | #42600 1822 | b10101010 " 1823 | b10101010 # 1824 | #42700 1825 | b10101011 " 1826 | b10101011 # 1827 | #42800 1828 | b10101100 " 1829 | b10101100 # 1830 | #42900 1831 | b10101101 " 1832 | b10101101 # 1833 | #43000 1834 | b10101110 " 1835 | b10101110 # 1836 | #43100 1837 | b10101111 " 1838 | b10101111 # 1839 | #43200 1840 | b10110000 " 1841 | b10110000 # 1842 | #43300 1843 | b10110001 " 1844 | b10110001 # 1845 | #43400 1846 | b10110010 " 1847 | b10110010 # 1848 | #43500 1849 | b10110011 " 1850 | b10110011 # 1851 | #43600 1852 | b10110100 " 1853 | b10110100 # 1854 | #43700 1855 | b10110101 " 1856 | b10110101 # 1857 | #43800 1858 | b10110110 " 1859 | b10110110 # 1860 | #43900 1861 | b10110111 " 1862 | b10110111 # 1863 | #44000 1864 | b10111000 " 1865 | b10111000 # 1866 | #44100 1867 | b10111001 " 1868 | b10111001 # 1869 | #44200 1870 | b10111010 " 1871 | b10111010 # 1872 | #44300 1873 | b10111011 " 1874 | b10111011 # 1875 | #44400 1876 | b10111100 " 1877 | b10111100 # 1878 | #44500 1879 | b10111101 " 1880 | b10111101 # 1881 | #44600 1882 | b10111110 " 1883 | b10111110 # 1884 | #44700 1885 | b10111111 " 1886 | b10111111 # 1887 | #44800 1888 | b11000000 " 1889 | b11000000 # 1890 | #44900 1891 | b11000001 " 1892 | b11000001 # 1893 | #45000 1894 | b11000010 " 1895 | b11000010 # 1896 | #45100 1897 | b11000011 " 1898 | b11000011 # 1899 | #45200 1900 | b11000100 " 1901 | b11000100 # 1902 | #45300 1903 | b11000101 " 1904 | b11000101 # 1905 | #45400 1906 | b11000110 " 1907 | b11000110 # 1908 | #45500 1909 | b11000111 " 1910 | b11000111 # 1911 | #45600 1912 | b11001000 " 1913 | b11001000 # 1914 | #45700 1915 | b11001001 " 1916 | b11001001 # 1917 | #45800 1918 | b11001010 " 1919 | b11001010 # 1920 | #45900 1921 | b11001011 " 1922 | b11001011 # 1923 | #46000 1924 | b11001100 " 1925 | b11001100 # 1926 | #46100 1927 | b11001101 " 1928 | b11001101 # 1929 | #46200 1930 | b11001110 " 1931 | b11001110 # 1932 | #46300 1933 | b11001111 " 1934 | b11001111 # 1935 | #46400 1936 | b11010000 " 1937 | b11010000 # 1938 | #46500 1939 | b11010001 " 1940 | b11010001 # 1941 | #46600 1942 | b11010010 " 1943 | b11010010 # 1944 | #46700 1945 | b11010011 " 1946 | b11010011 # 1947 | #46800 1948 | b11010100 " 1949 | b11010100 # 1950 | #46900 1951 | b11010101 " 1952 | b11010101 # 1953 | #47000 1954 | b11010110 " 1955 | b11010110 # 1956 | #47100 1957 | b11010111 " 1958 | b11010111 # 1959 | #47200 1960 | b11011000 " 1961 | b11011000 # 1962 | #47300 1963 | b11011001 " 1964 | b11011001 # 1965 | #47400 1966 | b11011010 " 1967 | b11011010 # 1968 | #47500 1969 | b11011011 " 1970 | b11011011 # 1971 | #47600 1972 | b11011100 " 1973 | b11011100 # 1974 | #47700 1975 | b11011101 " 1976 | b11011101 # 1977 | #47800 1978 | b11011110 " 1979 | b11011110 # 1980 | #47900 1981 | b11011111 " 1982 | b11011111 # 1983 | #48000 1984 | b11100000 " 1985 | b11100000 # 1986 | #48100 1987 | b11100001 " 1988 | b11100001 # 1989 | #48200 1990 | b11100010 " 1991 | b11100010 # 1992 | #48300 1993 | b11100011 " 1994 | b11100011 # 1995 | #48400 1996 | b11100100 " 1997 | b11100100 # 1998 | #48500 1999 | b11100101 " 2000 | b11100101 # 2001 | #48600 2002 | b11100110 " 2003 | b11100110 # 2004 | #48700 2005 | b11100111 " 2006 | b11100111 # 2007 | #48800 2008 | b11101000 " 2009 | b11101000 # 2010 | #48900 2011 | b11101001 " 2012 | b11101001 # 2013 | #49000 2014 | b11101010 " 2015 | b11101010 # 2016 | #49100 2017 | b11101011 " 2018 | b11101011 # 2019 | #49200 2020 | b11101100 " 2021 | b11101100 # 2022 | #49300 2023 | b11101101 " 2024 | b11101101 # 2025 | #49400 2026 | b11101110 " 2027 | b11101110 # 2028 | #49500 2029 | b11101111 " 2030 | b11101111 # 2031 | #49600 2032 | b11110000 " 2033 | b11110000 # 2034 | #49700 2035 | b11110001 " 2036 | b11110001 # 2037 | #49800 2038 | b11110010 " 2039 | b11110010 # 2040 | #49900 2041 | b11110011 " 2042 | b11110011 # 2043 | #50000 2044 | b11110100 " 2045 | b11110100 # 2046 | #50100 2047 | b11110101 " 2048 | b11110101 # 2049 | #50200 2050 | b11110110 " 2051 | b11110110 # 2052 | #50300 2053 | b11110111 " 2054 | b11110111 # 2055 | #50400 2056 | b11111000 " 2057 | b11111000 # 2058 | #50500 2059 | b11111001 " 2060 | b11111001 # 2061 | #50600 2062 | b11111010 " 2063 | b11111010 # 2064 | #50700 2065 | b11111011 " 2066 | b11111011 # 2067 | #50800 2068 | b11111100 " 2069 | b11111100 # 2070 | #50900 2071 | b11111101 " 2072 | b11111101 # 2073 | #51000 2074 | b11111110 " 2075 | b11111110 # 2076 | #51100 2077 | b11111111 " 2078 | b11111111 # 2079 | #51200 2080 | b100000000 " 2081 | b100000000 # 2082 | -------------------------------------------------------------------------------- /rtl/vector_csrs.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | // NOTE (Matthew Johns) - there is similarity between parts of this code and the 17 | // csr.sv module made by me in my third-year project. This is because the 18 | // functionality is similar and therefore I'm using what I learnt previously. 19 | 20 | module vector_csrs ( 21 | output logic [4:0] vl, 22 | output logic [1:0] vsew, 23 | output logic [1:0] vlmul, 24 | output logic [4:0] vl_next_comb, 25 | input wire clk, 26 | input wire n_reset, 27 | input wire [31:0] avl_in, 28 | input wire [4:0] vtype_in, 29 | input wire write, 30 | input wire saturate_flag, 31 | input wire preserve_vl, 32 | input wire set_vl_max 33 | ); 34 | 35 | // CSRs included in this implementation: 36 | // 0x009 vxsat fixed-point saturate flag 37 | // 0x00A vxrm fixed-point rounding mode (fixed to ) 38 | // 0xC20 vl vector length 39 | // 0xC21 vtype vector data type register 40 | // 0xC22 vlenb vector register length in bytes 41 | // For this accelerator they're separate from the standard CSR file - so we 42 | // might as well put them in one block of their own, in this order 43 | 44 | logic [31:0] csrs [4:0]; 45 | 46 | logic [4:0] vl_next; 47 | logic [4:0] max_vl; 48 | logic [2:0] per_reg; 49 | 50 | always_ff @(posedge clk, negedge n_reset) 51 | if (~n_reset) 52 | begin 53 | for (int i=0; i<4; i++) 54 | csrs[i] <= '0; 55 | // vlenb is read-only, so can assign it at reset 56 | csrs[4] <= 32'd4; 57 | end 58 | else 59 | begin 60 | if (write) 61 | begin 62 | // vtype will be changed for every vsetvli instruction 63 | csrs[3] <= {'0, vtype_in}; 64 | 65 | // Don't always want to write VL, eg. if rd == 0 and rs1 == 0 66 | // preserve_vl controls when it's left unchanged 67 | if (~preserve_vl) 68 | csrs[2] <= {'0 , vl_next}; 69 | end 70 | end 71 | 72 | 73 | always_comb 74 | begin 75 | // Spec defines vsew as 3 bits of vtype, but our max element is 32b so the 76 | // top bit will always be zero and we can just look at the lower two 77 | vsew = csrs[3][3:2]; 78 | vlmul = csrs[3][1:0]; 79 | 80 | // If the AVL being suggested in the instruction is larger than max_vl, need 81 | // to set VL to max_vl. Also do this if set_vl_max asserted 82 | if ( set_vl_max | (avl_in > max_vl) ) 83 | vl_next = max_vl; 84 | else 85 | vl_next = avl_in[4:0]; 86 | 87 | end 88 | 89 | // VL will update on the next clock edge, but that's ok because there will be at 90 | // least a single cycle delay before another instruction comes due to the state 91 | // machine for the APU interface 92 | assign vl = csrs[2][4:0]; 93 | 94 | // How many elements fit into a single register for each value of VSEW? 95 | // Can work this out by dividing vlenb by vsew 96 | assign per_reg = csrs[4][2:0] >> vtype_in[4:2]; 97 | 98 | // Max VL value equals the max number of elements per register * LMUL. LMUL is 99 | // in powers of 2 so can use a shift 100 | assign max_vl = per_reg << vtype_in[1:0]; 101 | 102 | assign vl_next_comb = vl_next; 103 | 104 | endmodule 105 | -------------------------------------------------------------------------------- /rtl/vector_decoder.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | // `include "defs.sv" 17 | import accelerator_pkg::*; 18 | 19 | module vector_decoder ( 20 | output logic apu_rvalid, 21 | output logic apu_gnt, 22 | output logic [31:0] scalar_operand1, 23 | output logic [31:0] scalar_operand2, 24 | output logic [10:0] immediate_operand, 25 | output logic [4:0] vs1_addr, 26 | output logic [4:0] vs2_addr, 27 | output logic [4:0] vd_addr, 28 | output logic csr_write, 29 | output logic preserve_vl, 30 | output logic set_vl_max, 31 | output logic [1:0] elements_to_write, 32 | output logic [1:0] cycle_count, 33 | output logic vec_reg_write, 34 | output vreg_wb_src_t vd_data_src, 35 | output vreg_addr_src_t vs3_addr_src, 36 | output pe_arith_op_t pe_op, 37 | output pe_saturate_mode_t saturate_mode, 38 | output pe_output_mode_t output_mode, 39 | output pe_operand_t operand_select, 40 | output logic [1:0] pe_mul_us, 41 | output logic [1:0] widening, 42 | output apu_result_src_t apu_result_select, 43 | output logic unsigned_immediate, 44 | output logic wide_vs1, 45 | input wire clk, 46 | input wire n_reset, 47 | input wire apu_req, 48 | input wire [31:0] apu_operands [2:0], 49 | input wire [5:0] apu_op, 50 | input wire [14:0] apu_flags_i, 51 | input wire [4:0] vl, 52 | input wire [1:0] vsew, 53 | output logic vlsu_en_o, 54 | output logic vlsu_load_o, 55 | output logic vlsu_store_o, 56 | output logic vlsu_strided_o, 57 | input logic vlsu_ready_i, 58 | input logic vlsu_done_i, 59 | output logic core_halt_o 60 | ); 61 | 62 | enum {WAIT, EXEC, VALID} state, next_state; 63 | 64 | logic [1:0] max_cycle_count; 65 | logic multi_cycle_instr; 66 | logic fix_vd_addr; 67 | 68 | // Registers to store values from APU interface during instruction execution 69 | logic [31:0] reg_apu_operands [2:0]; 70 | logic [5:0] reg_apu_op; 71 | logic [14:0] reg_apu_flags_i; 72 | 73 | // Assign variables for individual parts of instructions for readability 74 | logic [2:0] funct3; 75 | logic [6:0] major_opcode; 76 | logic [5:0] funct6; 77 | logic [4:0] source1; 78 | logic [4:0] source2; 79 | logic [4:0] destination; 80 | logic [2:0] mop; // Vector Addressing Mode 81 | assign funct3 = reg_apu_operands[0][14:12]; 82 | assign major_opcode = reg_apu_operands[0][6:0]; 83 | assign funct6 = reg_apu_operands[0][31:26]; 84 | assign source1 = reg_apu_operands[0][19:15]; 85 | assign source2 = reg_apu_operands[0][24:20]; 86 | assign destination = reg_apu_operands[0][11:7]; 87 | assign mop = funct6[2:0]; 88 | 89 | assign scalar_operand1 = reg_apu_operands[1]; 90 | assign scalar_operand2 = reg_apu_operands[2]; 91 | 92 | always_ff @(posedge clk, negedge n_reset) 93 | if(~n_reset) 94 | begin 95 | state <= WAIT; 96 | reg_apu_operands <= '{3{'0}}; 97 | reg_apu_op <= '0; 98 | reg_apu_flags_i <= '0; 99 | end 100 | else 101 | begin 102 | state <= next_state; 103 | 104 | // In wait state, can load data from APU interface ready for the next 105 | // instruction. Only do this when it's valid, otherwise will screw any 106 | // invalid instruction checking code 107 | if ((state == WAIT) & apu_req) 108 | begin 109 | reg_apu_operands[0] <= apu_operands[0]; 110 | reg_apu_operands[1] <= apu_operands[1]; 111 | reg_apu_operands[2] <= apu_operands[2]; 112 | reg_apu_op <= apu_op; 113 | reg_apu_flags_i <= apu_flags_i; 114 | end 115 | end 116 | 117 | logic core_halt_ctrl; 118 | 119 | assign core_halt_o = core_halt_ctrl; 120 | 121 | /*always_ff @(posedge clk, negedge n_reset) begin 122 | if(~n_reset) 123 | core_halt_o <= 1'b0; 124 | else 125 | core_halt_o <= core_halt_ctrl; 126 | end*/ 127 | 128 | always_comb 129 | begin 130 | apu_rvalid = 1'b0; 131 | apu_gnt = 1'b0; 132 | next_state = state; 133 | core_halt_ctrl = 1'b0; 134 | 135 | case (state) 136 | WAIT: 137 | begin 138 | apu_gnt = 1'b1; 139 | if (apu_req) 140 | next_state = EXEC; 141 | else 142 | next_state = WAIT; 143 | end 144 | EXEC: 145 | begin 146 | core_halt_ctrl = 1'b1; 147 | 148 | if (vlsu_load_o | vlsu_store_o) begin 149 | if(vlsu_done_i) begin 150 | apu_rvalid = 1'b1; 151 | next_state = WAIT; 152 | end 153 | end else if (cycle_count == max_cycle_count) begin 154 | apu_rvalid = 1'b1; 155 | next_state = WAIT; 156 | end 157 | end 158 | endcase 159 | end 160 | 161 | // VECTOR REGISTER ADDRESS GENERATION 162 | always_ff @(posedge clk, negedge n_reset) 163 | if (~n_reset) 164 | begin 165 | cycle_count <= '0; 166 | end 167 | else 168 | begin 169 | if (state == WAIT || (vlsu_load_o | vlsu_store_o)) 170 | cycle_count <= '0; 171 | else 172 | cycle_count <= cycle_count + 1'b1; 173 | 174 | end 175 | 176 | 177 | logic [3:0] vl_zero_indexed; 178 | 179 | always_comb 180 | begin 181 | // Subtract 1 because if VL=4/8/16 it will want another cycle otherwise 182 | // Number of loads dependant on SEW (For contiguous 8-bit values) 183 | // TODO: Determine strided count 184 | // vl_zero_indexed = (vl - 1'b1) >> (2'd2 - vsew); // Used for memory 185 | vl_zero_indexed = vl - 1'b1; 186 | // Elements can be handled 4 at a time so divide VL by 4, or force 0 187 | max_cycle_count = multi_cycle_instr ? vl_zero_indexed[3:2] : 2'd0; 188 | 189 | case (vsew) 190 | 2'd0: // 8b 191 | begin 192 | vs1_addr = source1 + cycle_count; 193 | vs2_addr = source2 + cycle_count; 194 | if (fix_vd_addr) 195 | vd_addr = destination; 196 | else 197 | begin 198 | if(widening[0]) 199 | vd_addr = destination + {cycle_count, 1'b0}; 200 | else 201 | vd_addr = destination + cycle_count; 202 | end 203 | end 204 | 2'd1: // 16b 205 | begin 206 | vs1_addr = source1 + {cycle_count, 1'b0}; 207 | vs2_addr = source2 + {cycle_count, 1'b0}; 208 | if (fix_vd_addr) 209 | vd_addr = destination; 210 | else 211 | vd_addr = destination + {cycle_count, 1'b0}; 212 | end 213 | default: 214 | begin 215 | vs1_addr = source1 + cycle_count; 216 | vs2_addr = source2 + cycle_count; 217 | if (fix_vd_addr) 218 | vd_addr = destination; 219 | else 220 | vd_addr = destination + cycle_count; 221 | end 222 | endcase 223 | 224 | if (funct3 == V_OPCFG) 225 | immediate_operand = reg_apu_operands[0][30:20]; 226 | else 227 | immediate_operand = {'0, reg_apu_operands[0][19:15]}; 228 | end 229 | 230 | always_comb 231 | begin 232 | elements_to_write = 2'd0; 233 | 234 | if (multi_cycle_instr) 235 | begin 236 | if (cycle_count == max_cycle_count) 237 | if (operand_select == PE_OPERAND_RIPPLE) 238 | // Reductions only want to write in last cycle to only one element 239 | elements_to_write = 2'd1; 240 | else 241 | // On last cycle, work out how many elements remain 242 | elements_to_write = vl[1:0]; 243 | else 244 | elements_to_write = 2'd0; 245 | end 246 | end 247 | 248 | //////////////////////////////////////////////////////////////////////////////// 249 | // ACCELERATOR CONTROL SIGNALS 250 | always_comb 251 | begin 252 | // Assign defaults for when not executing 253 | csr_write = 1'b0; 254 | preserve_vl = 1'b0; 255 | set_vl_max = 1'b0; 256 | vec_reg_write = 1'b0; 257 | vd_data_src = VREG_WB_SRC_ARITH; 258 | vs3_addr_src = VS3_ADDR_SRC_DECODE; 259 | pe_op = PE_ARITH_ADD; 260 | operand_select = PE_OPERAND_VS1; 261 | saturate_mode = PE_SAT_NONE; 262 | output_mode = PE_OP_MODE_RESULT; 263 | pe_mul_us = 2'b00; 264 | widening = 2'b00; 265 | apu_result_select = APU_RESULT_SRC_VL; 266 | multi_cycle_instr = 1'b0; 267 | unsigned_immediate = 1'b0; 268 | wide_vs1 = 1'b0; 269 | 270 | vlsu_en_o = 1'b0; 271 | vlsu_load_o = 1'b0; 272 | vlsu_store_o = 1'b0; 273 | vlsu_strided_o = 1'b0; 274 | 275 | // Used to control decoder module itself 276 | fix_vd_addr = 1'b0; 277 | 278 | // Control signals during instruction execution 279 | if (state == EXEC) 280 | begin 281 | if (major_opcode == V_MAJOR_LOAD_FP) 282 | begin 283 | if(funct3 == 3'b111) begin 284 | vd_data_src = VREG_WB_SRC_MEMORY; 285 | vlsu_en_o = 1'b1; 286 | vlsu_load_o = 1'b1; 287 | if(mop == 3'b010) vlsu_strided_o = 1'b1; 288 | end else $error("Unimplemented LOAD_FP instruction"); 289 | end 290 | else if (major_opcode == V_MAJOR_STORE_FP) 291 | begin 292 | if(funct3 == 3'b111) begin 293 | vs3_addr_src = VS3_ADDR_SRC_VLSU; 294 | fix_vd_addr = 1'b1; 295 | vlsu_en_o = 1'b1; 296 | vlsu_store_o = 1'b1; 297 | end else $error("Unimplemented STORE_FP instruction"); 298 | end 299 | else if (major_opcode == V_MAJOR_OP_V) 300 | begin 301 | // Consider vsetvli instructions separately (different format) 302 | if (funct3 == V_OPCFG) 303 | begin 304 | csr_write = 1'b1; 305 | apu_result_select = APU_RESULT_SRC_VL; 306 | if (source1 == '0) 307 | begin 308 | if (destination == '0) 309 | preserve_vl = 1'b1; 310 | else 311 | set_vl_max = 1'b1; 312 | end 313 | end 314 | else 315 | begin 316 | // Look for all other OP-V instructions 317 | case (funct6) 318 | 319 | // vadd, vredsum 320 | 6'b000000: 321 | begin 322 | pe_op = PE_ARITH_ADD; 323 | vec_reg_write = 1'b1; 324 | multi_cycle_instr = 1'b1; 325 | // vadd.vv 326 | if (funct3 == V_OPIVV) 327 | operand_select = PE_OPERAND_VS1; 328 | // vadd.vx 329 | else if (funct3 == V_OPIVX) 330 | operand_select = PE_OPERAND_SCALAR; 331 | else if (funct3 == V_OPMVV) // vredsum 332 | begin 333 | operand_select = PE_OPERAND_RIPPLE; 334 | fix_vd_addr = 1'b1; 335 | end 336 | end 337 | 338 | // vsub 339 | 6'b000010: 340 | begin 341 | pe_op = PE_ARITH_SUB; 342 | vec_reg_write = 1'b1; 343 | multi_cycle_instr = 1'b1; 344 | end 345 | 346 | // vmin 347 | 6'b000101: 348 | begin 349 | pe_op = PE_ARITH_SUB; 350 | output_mode = PE_OP_MODE_PASS_MIN; 351 | vec_reg_write = 1'b1; 352 | multi_cycle_instr = 1'b1; 353 | // Supports vmin.vv and vmin.vx 354 | if (funct3 == V_OPIVV) 355 | operand_select = PE_OPERAND_VS1; 356 | else if (funct3 == V_OPIVX) 357 | operand_select = PE_OPERAND_SCALAR; 358 | end 359 | 360 | // vmax, vredmax 361 | 6'b000111: 362 | begin 363 | pe_op = PE_ARITH_SUB; 364 | vec_reg_write = 1'b1; 365 | output_mode = PE_OP_MODE_PASS_MAX; 366 | multi_cycle_instr = 1'b1; 367 | // vredmax 368 | if (funct3 == V_OPMVV) 369 | begin 370 | fix_vd_addr = 1'b1; 371 | operand_select = PE_OPERAND_RIPPLE; 372 | end 373 | // Supports vmax.vv and vmax.vx 374 | else if (funct3 == V_OPIVV) 375 | operand_select = PE_OPERAND_VS1; 376 | else if (funct3 == V_OPIVX) 377 | operand_select = PE_OPERAND_SCALAR; 378 | end 379 | 380 | // vand 381 | 6'b001001: 382 | begin 383 | pe_op = PE_ARITH_AND; 384 | vec_reg_write = 1'b1; 385 | multi_cycle_instr = 1'b1; 386 | end 387 | 388 | // vor 389 | 6'b001010: 390 | begin 391 | pe_op = PE_ARITH_OR; 392 | vec_reg_write = 1'b1; 393 | multi_cycle_instr = 1'b1; 394 | end 395 | 396 | // vxor 397 | 6'b001011: 398 | begin 399 | pe_op = PE_ARITH_XOR; 400 | vec_reg_write = 1'b1; 401 | multi_cycle_instr = 1'b1; 402 | end 403 | 404 | // VWXUNARY0 (vmv.x.s) 405 | 6'b010000: 406 | begin 407 | apu_result_select = APU_RESULT_SRC_VS2_0; 408 | end 409 | 410 | // vmv.v 411 | 6'b010111: 412 | begin 413 | vec_reg_write = 1'b1; 414 | multi_cycle_instr = 1'b1; 415 | vd_data_src = VREG_WB_SRC_SCALAR; 416 | // vmv.v.i 417 | if (funct3 == V_OPIVI) 418 | operand_select = PE_OPERAND_IMMEDIATE; 419 | // vmv.v.x 420 | else if (funct3 == V_OPIVX) 421 | operand_select = PE_OPERAND_SCALAR; 422 | end 423 | 424 | // vsadd 425 | 6'b100001: 426 | begin 427 | pe_op = PE_ARITH_ADD; 428 | saturate_mode = PE_SAT; 429 | vec_reg_write = 1'b1; 430 | multi_cycle_instr = 1'b1; 431 | end 432 | 433 | // vsll/vmul 434 | 6'b100101: 435 | begin 436 | vec_reg_write = 1'b1; 437 | multi_cycle_instr = 1'b1; 438 | if (funct3 == V_OPIVV) 439 | begin 440 | pe_op = PE_ARITH_LSHIFT; 441 | operand_select = PE_OPERAND_VS1; 442 | end 443 | else if (funct3 == V_OPIVX) 444 | begin 445 | pe_op = PE_ARITH_LSHIFT; 446 | operand_select = PE_OPERAND_SCALAR; 447 | end 448 | else if (funct3 == V_OPIVI) 449 | begin 450 | pe_op = PE_ARITH_LSHIFT; 451 | operand_select = PE_OPERAND_IMMEDIATE; 452 | end 453 | else if (funct3 == V_OPMVV) 454 | begin 455 | pe_op = PE_ARITH_MUL; 456 | operand_select = PE_OPERAND_VS1; 457 | end 458 | 459 | end 460 | 461 | // vsmul 462 | 6'b100111: 463 | begin 464 | pe_op = PE_ARITH_MUL; 465 | saturate_mode = PE_SAT_UPPER; 466 | vec_reg_write = 1'b1; 467 | multi_cycle_instr = 1'b1; 468 | if (funct3 == V_OPIVV) 469 | operand_select = PE_OPERAND_VS1; 470 | else if (funct3 == V_OPIVX) 471 | operand_select = PE_OPERAND_SCALAR; 472 | end 473 | 474 | // vsrl 475 | 6'b101000: 476 | begin 477 | pe_op = PE_ARITH_RSHIFT_LOG; 478 | vec_reg_write = 1'b1; 479 | multi_cycle_instr = 1'b1; 480 | if (funct3 == V_OPIVV) 481 | operand_select = PE_OPERAND_VS1; 482 | else if (funct3 == V_OPIVX) 483 | operand_select = PE_OPERAND_SCALAR; 484 | else if (funct3 == V_OPIVI) 485 | begin 486 | unsigned_immediate = 1'b1; 487 | operand_select = PE_OPERAND_IMMEDIATE; 488 | end 489 | end 490 | 491 | // vsra 492 | 6'b101001: 493 | begin 494 | pe_op = PE_ARITH_RSHIFT_AR; 495 | vec_reg_write = 1'b1; 496 | multi_cycle_instr = 1'b1; 497 | if (funct3 == V_OPIVV) 498 | operand_select = PE_OPERAND_VS1; 499 | else if (funct3 == V_OPIVX) 500 | operand_select = PE_OPERAND_SCALAR; 501 | else if (funct3 == V_OPIVI) 502 | begin 503 | unsigned_immediate = 1'b1; 504 | operand_select = PE_OPERAND_IMMEDIATE; 505 | end 506 | end 507 | 508 | // vwredsum 509 | 6'b110001: 510 | begin 511 | pe_op = PE_ARITH_ADD; 512 | operand_select = PE_OPERAND_RIPPLE; 513 | vec_reg_write = 1'b1; 514 | fix_vd_addr = 1'b1; 515 | multi_cycle_instr = 1'b1; 516 | widening = 2'b01; 517 | wide_vs1 = 1'b1; 518 | end 519 | 520 | // vwmul 521 | 6'b111011: 522 | begin 523 | pe_op = PE_ARITH_MUL; 524 | vec_reg_write = 1'b1; 525 | multi_cycle_instr = 1'b1; 526 | widening = 2'b01; 527 | if (funct3 == V_OPMVV) 528 | operand_select = PE_OPERAND_VS1; 529 | else if (funct3 == V_OPMVX) 530 | operand_select = PE_OPERAND_SCALAR; 531 | end 532 | 533 | default: 534 | $error("Unsupported vector instruction"); 535 | 536 | endcase 537 | end 538 | end 539 | else 540 | $error("Unrecognised major opcode"); 541 | end 542 | end 543 | 544 | endmodule 545 | -------------------------------------------------------------------------------- /rtl/vector_lsu.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | import accelerator_pkg::*; 17 | 18 | module vector_lsu ( 19 | input wire clk, 20 | input wire n_reset, 21 | 22 | // Vector CSR 23 | input wire [4:0] vl_i, 24 | input wire [1:0] vsew_i, 25 | input wire [1:0] vlmul_i, 26 | 27 | // VLSU Decoded Control 28 | input wire vlsu_en_i, 29 | input wire vlsu_load_i, 30 | input wire vlsu_store_i, 31 | input wire vlsu_strided_i, 32 | output logic vlsu_ready_o, 33 | output logic vlsu_done_o, 34 | 35 | // OBI Memory Master 36 | output logic data_req_o, 37 | input logic data_gnt_i, 38 | input logic data_rvalid_i, 39 | output logic [31:0] data_addr_o, 40 | output logic data_we_o, 41 | output logic [3:0] data_be_o, 42 | input logic [31:0] data_rdata_i, 43 | output logic [31:0] data_wdata_o, 44 | 45 | input logic [1:0] cycle_count_i, 46 | 47 | // Target Data 48 | input wire [31:0] op0_data_i, // Source (Load) / Destination (Store) 49 | input wire [31:0] op1_data_i, // Stride 50 | 51 | // Wide vector register port 52 | output logic [127:0] vs_wdata_o, 53 | input logic [127:0] vs_rdata_i, 54 | input logic [4:0] vr_addr_i, 55 | output logic [4:0] vs3_addr_o, // Redirected vector register address 56 | output logic vr_we_o 57 | ); 58 | 59 | logic [31:0] vs_rdata_sel; 60 | logic [5:0] vsew_size; 61 | 62 | logic au_start; 63 | logic [3:0] au_be; 64 | logic [6:0] au_bc; 65 | logic [31:0] au_addr; 66 | logic au_valid, au_ready; 67 | logic [6:0] vd_offset; 68 | 69 | temporary_reg tr ( 70 | .clk_i (clk), 71 | .n_rst_i (n_reset), 72 | .byte_enable_valid (data_req_o), 73 | .read_data_valid (data_rvalid_i), 74 | .clear_register (au_start), 75 | .memory_read_i (data_rdata_i), 76 | .byte_enable_i (au_be), 77 | .byte_select_i (vd_offset + {vr_addr_i[1:0], 2'b00}), 78 | .wide_vd_o (vs_wdata_o) 79 | ); 80 | 81 | always_comb begin 82 | data_wdata_o = 'd0; 83 | case(vsew_i) 84 | 2'd0 : begin 85 | data_wdata_o = {vs_rdata_i[103:96], vs_rdata_i[71:64], vs_rdata_i[39:32], vs_rdata_i[7:0]}; 86 | end 87 | 2'd1 : begin 88 | case(vs3_addr_o[0]) 89 | 1'd0 : data_wdata_o = {vs_rdata_i[47:32], vs_rdata_i[15:0]}; 90 | 1'd1 : data_wdata_o = {vs_rdata_i[111:96], vs_rdata_i[79:64]}; 91 | endcase 92 | end 93 | 2'd2 : begin 94 | case(vs3_addr_o[1:0]) 95 | 2'd0 : data_wdata_o = vs_rdata_i[31:0]; 96 | 2'd1 : data_wdata_o = vs_rdata_i[63:32]; 97 | 2'd2 : data_wdata_o = vs_rdata_i[95:64]; 98 | 2'd3 : data_wdata_o = vs_rdata_i[127:96]; 99 | endcase 100 | end 101 | endcase 102 | end 103 | 104 | logic [1:0] ib_select; // Low 2 bits of initial address 105 | logic [3:0] be_gen; 106 | 107 | logic [31:0] next_el_pre, next_el_addr; 108 | logic [31:0] cycle_addr, stride; 109 | logic [6:0] cycle_bytes; 110 | 111 | typedef enum {RESET, LOAD_FIRST, LOAD_CYCLE, LOAD_WAIT, LOAD_FINAL, STORE_CYCLE, STORE_WAIT, STORE_FINAL} be_state; 112 | be_state current_state, next_state; 113 | 114 | logic signed [6:0] byte_track, byte_track_next; 115 | logic cycle_load, cycle_addr_inc, store_cycles_inc; 116 | 117 | logic [2:0] store_cycle_bytes; 118 | logic [3:0] store_cycle_be; 119 | logic [2:0] store_cycles, store_cycles_cnt; 120 | 121 | assign stride = vlsu_strided_i ? op1_data_i : (32'd1 << vsew_i); 122 | assign data_addr_o = vlsu_store_i ? ({cycle_addr[31:2], 2'd0} + (store_cycles_cnt << 2)) : {cycle_addr[31:2], 2'd0}; 123 | assign au_be = be_gen; 124 | assign vd_offset = (vl_i << vsew_i) - byte_track; 125 | 126 | always_comb begin 127 | if(byte_track >= 4) 128 | store_cycle_be = 4'b1111; 129 | else if(byte_track >= 3) 130 | store_cycle_be = 4'b0111; 131 | else if(byte_track >= 2) 132 | store_cycle_be = 4'b0011; 133 | else 134 | store_cycle_be = 4'b0001; 135 | 136 | data_be_o = vlsu_store_i ? store_cycle_be : 4'b1111; 137 | end 138 | 139 | always_comb begin 140 | if(au_start) 141 | byte_track_next = {2'd0, vl_i} << vsew_i; // Bytes dependent on element size 142 | else if(cycle_addr_inc) 143 | byte_track_next = (byte_track >= cycle_bytes) ? (byte_track - cycle_bytes) : 7'd0; 144 | else if(store_cycles_inc) 145 | byte_track_next = byte_track - store_cycle_bytes; 146 | else 147 | byte_track_next = byte_track; 148 | end 149 | 150 | always_ff @(posedge clk, negedge n_reset) begin 151 | if(~n_reset) 152 | byte_track <= 7'd0; 153 | else 154 | byte_track <= byte_track_next; 155 | end 156 | 157 | always_ff @(posedge clk, negedge n_reset) begin 158 | if(~n_reset) 159 | cycle_addr <= 32'd0; 160 | else if(au_start) 161 | cycle_addr <= op0_data_i; 162 | else if(cycle_addr_inc) 163 | cycle_addr <= next_el_addr; 164 | else 165 | cycle_addr <= cycle_addr; 166 | end 167 | 168 | assign store_cycles = (vl_i >> 2-vsew_i)+1; 169 | assign vs3_addr_o = vr_addr_i + store_cycles_cnt; 170 | always_ff @(posedge clk, negedge n_reset) begin 171 | if(~n_reset) 172 | store_cycles_cnt <= 2'd0; 173 | else if(au_start) 174 | store_cycles_cnt <= 2'd0; 175 | else if (store_cycles_inc) 176 | store_cycles_cnt <= store_cycles_cnt + 2'd1; 177 | end 178 | 179 | always_ff @(posedge clk, negedge n_reset) begin 180 | if(~n_reset) 181 | current_state <= RESET; 182 | else 183 | current_state <= next_state; 184 | end 185 | 186 | always_comb begin 187 | be_gen = 4'b0000; 188 | next_el_pre = '0; 189 | cycle_bytes = '0; 190 | ib_select = '0; 191 | next_el_addr = '0; 192 | case(vsew_i) 193 | 2'b00 : begin // 8 Bit 194 | ib_select = cycle_addr[1:0]; 195 | 196 | if(stride > 32'd1) begin 197 | be_gen[ib_select] = 1'b1; 198 | 199 | // Where is our next byte? 200 | next_el_pre = cycle_addr + stride; 201 | if(next_el_pre[31:2] == cycle_addr[31:2] && byte_track > 1) begin 202 | be_gen[next_el_pre[1:0]] = 1'b1; 203 | next_el_addr = next_el_pre + stride; // Stride by second element 204 | end else begin 205 | next_el_addr = next_el_pre; 206 | end 207 | 208 | // Calculate the number of bytes for LOAD_CYCLE 209 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 210 | end else if(stride == 1) begin 211 | be_gen[0] = (ib_select == 32'd0) ? 1 : 0; 212 | be_gen[1] = (ib_select == 1 || byte_track > 1) ? 1'b1 : 1'b0; 213 | be_gen[2] = (ib_select == 2 || byte_track > 2) ? 1'b1 : 1'b0; 214 | be_gen[3] = (ib_select == 3 || byte_track > 3) ? 1'b1 : 1'b0; 215 | next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4; 216 | 217 | // Calculate the number of bytes for LOAD_CYCLE 218 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 219 | end else if(stride == 32'd0) begin 220 | be_gen[ib_select] = 1'b1; 221 | cycle_bytes = {2'b0, vl_i}; // Read all bytes in 1 LOAD_CYCLE 222 | end 223 | end 224 | 2'b01 : begin // 16 Bit 225 | ib_select = {cycle_addr[1], 1'b0}; // Force alignment byte 0 or 2 226 | 227 | if(stride > 32'd2) begin // Always 1 element 228 | // Always set 2 bytes 229 | be_gen[ib_select] = 1'b1; 230 | be_gen[ib_select+1] = 1'b1; 231 | next_el_addr = {cycle_addr[31:1], 1'b0} + {stride[31:1], 1'b0}; 232 | 233 | // Calculate the number of bytes for LOAD_CYCLE 234 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 235 | end else if (stride == 32'd2) begin // Up to 2 Elements 236 | be_gen[1:0] = (ib_select == 0) ? 2'b11 : 2'b00; 237 | be_gen[3:2] = (ib_select == 2 || byte_track > 2) ? 2'b11 : 2'b00; 238 | next_el_addr = {cycle_addr[31:2], 2'b0} + 32'd4; 239 | 240 | // Calculate the number of bytes for LOAD_CYCLE 241 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 242 | end else if (stride == 32'd0) begin 243 | be_gen[ib_select] = 1'b1; 244 | be_gen[ib_select+1] = 1'b1; 245 | cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 LOAD_CYCLE 246 | end 247 | end 248 | 2'b10 : begin // 32 Bit 249 | ib_select = 2'd0; // Force alignment to byte 0 250 | 251 | if(stride >= 32'd4) begin // Always 1 element 252 | be_gen = 4'b1111; 253 | next_el_addr = {cycle_addr[31:2], 2'b0} + {stride[31:2], 2'b0}; // stride is always a multiple of 4 254 | 255 | // Calculate the number of bytes for LOAD_CYCLE 256 | cycle_bytes = {5'd0, be_gen[3]} + {5'd0, be_gen[2]} + {5'd0, be_gen[1]} + {5'd0, be_gen[0]}; 257 | end else if(stride == 32'd0) begin 258 | be_gen = 4'b1111; 259 | cycle_bytes = {1'b0, vl_i, 1'b0}; // Read all bytes in 1 LOAD_CYCLE 260 | end 261 | end 262 | default : $error("Invalid VSEW"); 263 | endcase 264 | end 265 | 266 | always_comb begin 267 | cycle_load = 1'b0; 268 | data_req_o = 1'b0; 269 | data_we_o = 1'b0; 270 | au_start = 1'b0; 271 | au_ready = 1'b0; 272 | vlsu_done_o = 1'b0; 273 | vlsu_ready_o = 1'b0; 274 | cycle_addr_inc = 1'b0; 275 | store_cycles_inc = 1'b0; 276 | vr_we_o = 1'b0; 277 | case(current_state) 278 | RESET: begin 279 | vlsu_ready_o = 1'b1; 280 | if(vlsu_load_i) begin 281 | au_start = 1'b1; 282 | next_state = LOAD_FIRST; 283 | end else if (vlsu_store_i) begin 284 | au_start = 1'b1; 285 | next_state = STORE_CYCLE; 286 | end else begin 287 | next_state = RESET; 288 | end 289 | end 290 | LOAD_FIRST: begin 291 | next_state = LOAD_CYCLE; 292 | end 293 | LOAD_CYCLE: begin 294 | if(byte_track_next == 0) begin 295 | next_state = LOAD_WAIT; 296 | end else begin 297 | data_req_o = 1'b1; 298 | cycle_load = 1'b1; 299 | next_state = LOAD_WAIT; 300 | end 301 | end 302 | LOAD_WAIT: begin 303 | if(data_rvalid_i) begin 304 | cycle_addr_inc = 1'b1; 305 | next_state = LOAD_CYCLE; 306 | end else if(byte_track_next == 0) 307 | next_state = LOAD_FINAL; 308 | else 309 | next_state = LOAD_WAIT; 310 | end 311 | LOAD_FINAL: begin 312 | next_state = RESET; 313 | vlsu_done_o = 1'b1; 314 | vr_we_o = 1'b1; 315 | end 316 | STORE_CYCLE: begin 317 | data_req_o = 1'b1; 318 | data_we_o = 1'b1; 319 | next_state = STORE_WAIT; 320 | end 321 | STORE_WAIT: begin 322 | if(data_rvalid_i) begin 323 | if(store_cycles_cnt == store_cycles) begin 324 | next_state = STORE_FINAL; 325 | end else begin 326 | store_cycles_inc = 1'b1; 327 | next_state = STORE_CYCLE; 328 | end 329 | end else begin 330 | next_state = STORE_WAIT; 331 | end 332 | end 333 | STORE_FINAL: begin 334 | vlsu_done_o = 1'b1; 335 | next_state = RESET; 336 | end 337 | endcase 338 | end 339 | 340 | 341 | endmodule 342 | -------------------------------------------------------------------------------- /rtl/vector_registers.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | module vector_registers ( 17 | output logic [127:0] vs1_data, 18 | output logic [127:0] vs2_data, 19 | output logic [127:0] vs3_data, 20 | input wire [127:0] vd_data, 21 | input wire [4:0] vs1_addr, 22 | input wire [4:0] vs2_addr, 23 | input wire [4:0] vd_addr, // Generally this doubles up as vs3 address 24 | input wire [1:0] vsew, 25 | input wire [1:0] vlmul, 26 | input wire [1:0] elements_to_write, 27 | input wire clk, 28 | input wire n_reset, 29 | input wire write, 30 | input wire widening_op, 31 | input wire wide_vs1, 32 | input logic load_operation 33 | ); 34 | 35 | localparam VLEN = 32; 36 | 37 | logic [VLEN-1:0] vregs [31:0]; 38 | 39 | // Addresses for each of the read ports for each operand. 40 | // Each operand may require up to four read ports. 41 | // Reason: need 4 elements per operand per cycle to maintain throughput in 42 | // the 4 PEs. For 8b elements, 4 elements are stored in a single register; 43 | // however with 32b elements they will be spread across 4 registers (when 44 | // LMUL > 1). Otherwise SIMD throughput would be tiny. 45 | // These addresses will be consecutive for each operand. Just want a tidy 46 | // efficient way of producing them without an adder for each one. 47 | logic [4:0] vs1_addr0; 48 | logic [4:0] vs1_addr1; 49 | logic [4:0] vs1_addr2; 50 | logic [4:0] vs1_addr3; 51 | 52 | logic [4:0] vs2_addr0; 53 | logic [4:0] vs2_addr1; 54 | logic [4:0] vs2_addr2; 55 | logic [4:0] vs2_addr3; 56 | 57 | logic [4:0] vd_addr0; 58 | logic [4:0] vd_addr1; 59 | logic [4:0] vd_addr2; 60 | logic [4:0] vd_addr3; 61 | 62 | // Structured data to write back to registers 63 | logic [VLEN-1:0] vd_wr_data0; 64 | logic [VLEN-1:0] vd_wr_data1; 65 | logic [VLEN-1:0] vd_wr_data2; 66 | logic [VLEN-1:0] vd_wr_data3; 67 | 68 | // Unstructured data read from registers 69 | logic [VLEN-1:0] vs1_rd_data0; 70 | logic [VLEN-1:0] vs1_rd_data1; 71 | logic [VLEN-1:0] vs1_rd_data2; 72 | logic [VLEN-1:0] vs1_rd_data3; 73 | 74 | logic [VLEN-1:0] vs2_rd_data0; 75 | logic [VLEN-1:0] vs2_rd_data1; 76 | logic [VLEN-1:0] vs2_rd_data2; 77 | logic [VLEN-1:0] vs2_rd_data3; 78 | 79 | logic [VLEN-1:0] vs3_rd_data0; 80 | logic [VLEN-1:0] vs3_rd_data1; 81 | logic [VLEN-1:0] vs3_rd_data2; 82 | logic [VLEN-1:0] vs3_rd_data3; 83 | 84 | // Write-enable signals for each write port. Could get away with making wr_en1 85 | // only 2 bits, as will only write 16b elements. Similarly could make wr_en2 and 86 | // wr_en3 single bits. But I don't know what that would synthesise to if I did 87 | logic [3:0] wr_en0; 88 | logic [3:0] wr_en1; 89 | logic [3:0] wr_en2; 90 | logic [3:0] wr_en3; 91 | 92 | // Effective vsew can be modified for widening ops 93 | logic [1:0] eff_vsew; 94 | 95 | 96 | // REGISTER WRITE 97 | always_ff @(posedge clk, negedge n_reset) 98 | if (~n_reset) 99 | vregs <= '{VLEN{'0}}; 100 | else 101 | begin 102 | // Don't want to write to v0 (reserved for vector mask) 103 | if (write & (vd_addr != '0)) 104 | begin 105 | if (wr_en0[0]) 106 | vregs[vd_addr0][7:0] <= vd_wr_data0[7:0]; 107 | if (wr_en0[1]) 108 | vregs[vd_addr0][15:8] <= vd_wr_data0[15:8]; 109 | if (wr_en0[2]) 110 | vregs[vd_addr0][23:16] <= vd_wr_data0[23:16]; 111 | if (wr_en0[3]) 112 | vregs[vd_addr0][31:24] <= vd_wr_data0[31:24]; 113 | 114 | if (wr_en1[0]) 115 | vregs[vd_addr1][7:0] <= vd_wr_data1[7:0]; 116 | if (wr_en1[1]) 117 | vregs[vd_addr1][15:8] <= vd_wr_data1[15:8]; 118 | if (wr_en1[2]) 119 | vregs[vd_addr1][23:16] <= vd_wr_data1[23:16]; 120 | if (wr_en1[3]) 121 | vregs[vd_addr1][31:24] <= vd_wr_data1[31:24]; 122 | 123 | if (wr_en2[0]) 124 | vregs[vd_addr2][7:0] <= vd_wr_data2[7:0]; 125 | if (wr_en2[1]) 126 | vregs[vd_addr2][15:8] <= vd_wr_data2[15:8]; 127 | if (wr_en2[2]) 128 | vregs[vd_addr2][23:16] <= vd_wr_data2[23:16]; 129 | if (wr_en2[3]) 130 | vregs[vd_addr2][31:24] <= vd_wr_data2[31:24]; 131 | 132 | if (wr_en3[0]) 133 | vregs[vd_addr3][7:0] <= vd_wr_data3[7:0]; 134 | if (wr_en3[1]) 135 | vregs[vd_addr3][15:8] <= vd_wr_data3[15:8]; 136 | if (wr_en3[2]) 137 | vregs[vd_addr3][23:16] <= vd_wr_data3[23:16]; 138 | if (wr_en3[3]) 139 | vregs[vd_addr3][31:24] <= vd_wr_data3[31:24]; 140 | end 141 | end 142 | 143 | 144 | // REGISTER READ 145 | assign vs1_rd_data0 = vregs[vs1_addr0]; 146 | assign vs1_rd_data1 = vregs[vs1_addr1]; 147 | assign vs1_rd_data2 = vregs[vs1_addr2]; 148 | assign vs1_rd_data3 = vregs[vs1_addr3]; 149 | assign vs2_rd_data0 = vregs[vs2_addr0]; 150 | assign vs2_rd_data1 = vregs[vs2_addr1]; 151 | assign vs2_rd_data2 = vregs[vs2_addr2]; 152 | assign vs2_rd_data3 = vregs[vs2_addr3]; 153 | assign vs3_rd_data0 = vregs[vd_addr0]; 154 | assign vs3_rd_data1 = vregs[vd_addr1]; 155 | assign vs3_rd_data2 = vregs[vd_addr2]; 156 | assign vs3_rd_data3 = vregs[vd_addr3]; 157 | 158 | 159 | // ADDRESS CALCULATION 160 | always_comb 161 | begin 162 | // Logic behind this: Need 4 consecutive addresses, but don't want to just 163 | // have adders for each one to increment the address. 164 | // This is only useful for LMUL > 1, as for LMUL = 1, only one register will 165 | // be read anyway. If LMUL > 1, base addresses will always be even. So can 166 | // add one to it by making last bit 1. Add 2 by making second-last bit 1. 167 | // Add 3 by doing both. 168 | // If LMUL = 2 then adding 2 that way won't work, but also it won't be used 169 | // because only the first 2 registers will be used. 170 | vs1_addr0 = vs1_addr; 171 | vs1_addr1 = {vs1_addr[4:1], 1'b1}; 172 | vs1_addr2 = {vs1_addr[4:2], 1'b1, vs1_addr[0]}; 173 | vs1_addr3 = {vs1_addr[4:2], 2'b11}; 174 | 175 | vs2_addr0 = vs2_addr; 176 | vs2_addr1 = {vs2_addr[4:1], 1'b1}; 177 | vs2_addr2 = {vs2_addr[4:2], 1'b1, vs2_addr[0]}; 178 | vs2_addr3 = {vs2_addr[4:2], 2'b11}; 179 | 180 | vd_addr0 = vd_addr; 181 | vd_addr1 = {vd_addr[4:1], 1'b1}; 182 | vd_addr2 = {vd_addr[4:2], 1'b1, vd_addr[0]}; 183 | vd_addr3 = {vd_addr[4:2], 2'b11}; 184 | end 185 | 186 | 187 | // WRITE-ENABLE GENERATION 188 | always_comb 189 | begin 190 | // Note: can ignore LMUL in below cases as LMUL will restrict the max of VL, 191 | // which will prevent from writing to higher registers than LMUL wants 192 | if (widening_op) 193 | case (vsew) 194 | 2'd0: // 8b -> 16b 195 | eff_vsew = 2'd1; 196 | 2'd1: // 16b -> 32b 197 | eff_vsew = 2'd2; 198 | default: 199 | begin 200 | // Shouldn't come to this 201 | eff_vsew = vsew; 202 | $error("Widening ops with VSEW=32b are not supported"); 203 | end 204 | endcase 205 | else 206 | eff_vsew = vsew; 207 | 208 | wr_en0 = '0; 209 | wr_en1 = '0; 210 | wr_en2 = '0; 211 | wr_en3 = '0; 212 | 213 | if(load_operation) begin 214 | case (vlmul) 215 | 2'd0: begin 216 | case(vd_addr[1:0]) 217 | 2'b00 : wr_en0 = 4'b1111; 218 | 2'b01 : wr_en1 = 4'b1111; 219 | 2'b10 : wr_en2 = 4'b1111; 220 | 2'b11 : wr_en3 = 4'b1111; 221 | endcase 222 | end 223 | 2'd1: begin 224 | if(vd_addr[1] == 1'b0) begin 225 | wr_en0 = 4'b1111; 226 | wr_en1 = 4'b1111; 227 | end else begin 228 | wr_en2 = 4'b1111; 229 | wr_en3 = 4'b1111; 230 | end 231 | end 232 | 2'd2: begin 233 | wr_en0 = 4'b1111; 234 | wr_en1 = 4'b1111; 235 | wr_en2 = 4'b1111; 236 | wr_en3 = 4'b1111; 237 | end 238 | endcase 239 | end else begin 240 | case (eff_vsew) 241 | 2'd0: // 8b 242 | begin 243 | // Only interested in first write port 244 | case (elements_to_write) 245 | 2'd0: // Write all elements 246 | wr_en0 = 4'b1111; 247 | 2'd1: 248 | wr_en0 = 4'b0001; 249 | 2'd2: 250 | wr_en0 = 4'b0011; 251 | 2'd3: 252 | wr_en0 = 4'b0111; 253 | endcase 254 | end 255 | 2'd1: // 16b 256 | begin 257 | // Only interested in first 2 write ports 258 | case (elements_to_write) 259 | 2'd0: // Write all elements 260 | begin 261 | wr_en0 = 4'b1111; 262 | wr_en1 = 4'b1111; 263 | end 264 | 2'd1: 265 | begin 266 | wr_en0 = 4'b0011; 267 | end 268 | 2'd2: 269 | begin 270 | wr_en0 = 4'b1111; 271 | end 272 | 4'd3: 273 | begin 274 | wr_en0 = 4'b1111; 275 | wr_en1 = 4'b0011; 276 | end 277 | endcase 278 | end 279 | 2'd2: // 32b 280 | begin 281 | // Need to consider all write ports 282 | // wr_en0 always enabled, otherwise would be writing no elements 283 | wr_en0 = 4'b1111; 284 | case (elements_to_write) 285 | 2'd0: // Write all elements 286 | begin 287 | wr_en1 = 4'b1111; 288 | wr_en2 = 4'b1111; 289 | wr_en3 = 4'b1111; 290 | end 291 | // 2'd1: // Not needed, just wr_en0 = '1 292 | 2'd2: 293 | begin 294 | wr_en1 = 4'b1111; 295 | end 296 | 2'd3: 297 | begin 298 | wr_en1 = 4'b1111; 299 | wr_en2 = 4'b1111; 300 | end 301 | endcase 302 | end 303 | endcase 304 | end 305 | end 306 | 307 | 308 | // OUTPUT DATA MAP 309 | // TODO: consider need for sign extension for VSEW<32b 310 | // Have to pad the extra space when using smaller elements to give correct 311 | // alignment into the PEs 312 | always_comb 313 | begin 314 | case (vsew) 315 | 2'd0: // 8b 316 | begin 317 | // For vwredsum (theoretically other mixed-width instructions) the B 318 | // operand (which comes from vs1[0]) is 2*VSEW bits. So treat it as 319 | // for wider ones. 320 | if (wide_vs1) 321 | vs1_data = { 322 | {16{1'b0}}, 323 | vs1_rd_data1[31:16], 324 | {16{1'b0}}, 325 | vs1_rd_data1[15:0], 326 | {16{1'b0}}, 327 | vs1_rd_data0[31:16], 328 | {16{1'b0}}, 329 | vs1_rd_data0[15:0] 330 | }; 331 | else 332 | vs1_data = { 333 | {24{1'b0}}, 334 | vs1_rd_data0[31:24], 335 | {24{1'b0}}, 336 | vs1_rd_data0[23:16], 337 | {24{1'b0}}, 338 | vs1_rd_data0[15:8], 339 | {24{1'b0}}, 340 | vs1_rd_data0[7:0] 341 | }; 342 | 343 | vs2_data = { 344 | {24{1'b0}}, 345 | vs2_rd_data0[31:24], 346 | {24{1'b0}}, 347 | vs2_rd_data0[23:16], 348 | {24{1'b0}}, 349 | vs2_rd_data0[15:8], 350 | {24{1'b0}}, 351 | vs2_rd_data0[7:0] 352 | }; 353 | // For widening ops such as MACC, the third operand needs to be the 354 | // widened width rather than VSEW. Copy the mapping of vs3 from the 355 | // next largest element. Does not apply to VSEW=32b as widening ops 356 | // are not supported. 357 | if (widening_op) 358 | vs3_data = { 359 | {16{1'b0}}, 360 | vs3_rd_data1[31:16], 361 | {16{1'b0}}, 362 | vs3_rd_data1[15:0], 363 | {16{1'b0}}, 364 | vs3_rd_data0[31:16], 365 | {16{1'b0}}, 366 | vs3_rd_data0[15:0] 367 | }; 368 | else 369 | vs3_data = { 370 | {24{1'b0}}, 371 | vs3_rd_data0[31:24], 372 | {24{1'b0}}, 373 | vs3_rd_data0[23:16], 374 | {24{1'b0}}, 375 | vs3_rd_data0[15:8], 376 | {24{1'b0}}, 377 | vs3_rd_data0[7:0] 378 | }; 379 | end 380 | 2'd1: // 16b 381 | begin 382 | if (wide_vs1) 383 | vs1_data = { 384 | vs1_rd_data3, 385 | vs1_rd_data2, 386 | vs1_rd_data1, 387 | vs1_rd_data0 388 | }; 389 | else 390 | vs1_data = { 391 | {16{1'b0}}, 392 | vs1_rd_data1[31:16], 393 | {16{1'b0}}, 394 | vs1_rd_data1[15:0], 395 | {16{1'b0}}, 396 | vs1_rd_data0[31:16], 397 | {16{1'b0}}, 398 | vs1_rd_data0[15:0] 399 | }; 400 | 401 | vs2_data = { 402 | {16{1'b0}}, 403 | vs2_rd_data1[31:16], 404 | {16{1'b0}}, 405 | vs2_rd_data1[15:0], 406 | {16{1'b0}}, 407 | vs2_rd_data0[31:16], 408 | {16{1'b0}}, 409 | vs2_rd_data0[15:0] 410 | }; 411 | if (widening_op) 412 | vs3_data = { 413 | vs3_rd_data3, 414 | vs3_rd_data2, 415 | vs3_rd_data1, 416 | vs3_rd_data0 417 | }; 418 | else 419 | vs3_data = { 420 | {16{1'b0}}, 421 | vs3_rd_data1[31:16], 422 | {16{1'b0}}, 423 | vs3_rd_data1[15:0], 424 | {16{1'b0}}, 425 | vs3_rd_data0[31:16], 426 | {16{1'b0}}, 427 | vs3_rd_data0[15:0] 428 | }; 429 | end 430 | 2'd2: // 32b 431 | begin 432 | vs1_data = { 433 | vs1_rd_data3, 434 | vs1_rd_data2, 435 | vs1_rd_data1, 436 | vs1_rd_data0 437 | }; 438 | vs2_data = { 439 | vs2_rd_data3, 440 | vs2_rd_data2, 441 | vs2_rd_data1, 442 | vs2_rd_data0 443 | }; 444 | vs3_data = { 445 | vs3_rd_data3, 446 | vs3_rd_data2, 447 | vs3_rd_data1, 448 | vs3_rd_data0 449 | }; 450 | end 451 | default: 452 | begin 453 | vs1_data = '0; 454 | vs2_data = '0; 455 | vs3_data = '0; 456 | end 457 | endcase 458 | end 459 | 460 | 461 | // INPUT DATA MAP 462 | // Take wide combined result data from PEs and remove padding 463 | always_comb 464 | begin 465 | vd_wr_data3 = '0; 466 | vd_wr_data2 = '0; 467 | vd_wr_data1 = '0; 468 | vd_wr_data0 = '0; 469 | 470 | if(load_operation) begin 471 | case (vlmul) 472 | 2'd0: begin 473 | case(vd_addr[1:0]) 474 | 2'b00 : vd_wr_data0 = vd_data[31:0]; 475 | 2'b01 : vd_wr_data1 = vd_data[63:32]; 476 | 2'b10 : vd_wr_data2 = vd_data[95:64]; 477 | 2'b11 : vd_wr_data3 = vd_data[127:96]; 478 | endcase 479 | end 480 | 2'd1: begin 481 | if(vd_addr[1] == 1'b0) begin 482 | vd_wr_data1 = vd_data[63:32]; 483 | vd_wr_data0 = vd_data[31:0]; 484 | end else begin 485 | vd_wr_data3 = vd_data[127:96]; 486 | vd_wr_data2 = vd_data[95:64]; 487 | end 488 | end 489 | 2'd2: begin 490 | vd_wr_data3 = vd_data[127:96]; 491 | vd_wr_data2 = vd_data[95:64]; 492 | vd_wr_data1 = vd_data[63:32]; 493 | vd_wr_data0 = vd_data[31:0]; 494 | end 495 | endcase 496 | end else begin 497 | case (eff_vsew) 498 | 2'd0: // 8b 499 | vd_wr_data0 = { 500 | vd_data[103:96], 501 | vd_data[71:64], 502 | vd_data[39:32], 503 | vd_data[7:0] 504 | }; 505 | 2'd1: // 16b 506 | begin 507 | vd_wr_data1 = { 508 | vd_data[111:96], 509 | vd_data[79:64] 510 | }; 511 | vd_wr_data0 = { 512 | vd_data[47:32], 513 | vd_data[15:0] 514 | }; 515 | end 516 | 2'd2: // 32b 517 | begin 518 | vd_wr_data3 = vd_data[127:96]; 519 | vd_wr_data2 = vd_data[95:64]; 520 | vd_wr_data1 = vd_data[63:32]; 521 | vd_wr_data0 = vd_data[31:0]; 522 | end 523 | endcase 524 | end 525 | end 526 | 527 | endmodule -------------------------------------------------------------------------------- /rtl/vw_sign_ext.sv: -------------------------------------------------------------------------------- 1 | // 2 | // SPDX-License-Identifier: CERN-OHL-S-2.0+ 3 | // 4 | // Copyright (C) 2020-21 Embecosm Limited 5 | // Contributed by: 6 | // Matthew Johns 7 | // Byron Theobald 8 | // 9 | // This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, 10 | // INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR 11 | // A PARTICULAR PURPOSE. Please see the CERN-OHL-S v2 for applicable 12 | // conditions. 13 | // Source location: https://github.com/AI-Vector-Accelerator 14 | // 15 | 16 | // Variable width sign extension module. Used to sign-extend 3 PE inputs for 17 | // signed/widening multiplication 18 | 19 | module vw_sign_ext ( 20 | output logic [31:0] sign_ext_a, 21 | output logic [31:0] sign_ext_b, 22 | output logic [31:0] sign_ext_c, 23 | input wire [31:0] a, 24 | input wire [31:0] b, 25 | input wire [31:0] c, 26 | input wire [1:0] widening, // 2'd1 for 2*widening, 2'd2 for quad widening 27 | input wire [1:0] vsew, 28 | input wire wide_b 29 | ); 30 | 31 | always_comb begin 32 | sign_ext_a = '0; 33 | sign_ext_b = '0; 34 | sign_ext_c = '0; 35 | case(vsew) 36 | 2'd0: // 8b 37 | begin 38 | sign_ext_a = {{24{a[7]}}, a[7:0]}; 39 | 40 | // For vwredsum (theoretically other mixed-width instructions) the b 41 | // operand for each PE is 2*VSEW bits because it is an intermediate 42 | // result. So treat it as if vsew was twice as large 43 | if (wide_b) 44 | sign_ext_b = {{16{b[15]}}, b[15:0]}; 45 | else 46 | sign_ext_b = {{24{b[7]}}, b[7:0]}; 47 | 48 | if (widening[0]) 49 | sign_ext_c = {{16{c[15]}}, c[15:0]}; 50 | else if (widening[1]) 51 | sign_ext_c = c; 52 | else 53 | sign_ext_c = {{24{c[7]}}, c[7:0]}; 54 | end 55 | 2'd1: // 16b 56 | begin 57 | sign_ext_a = {{16{a[15]}}, a[15:0]}; 58 | 59 | if (wide_b) 60 | sign_ext_b = b; 61 | else 62 | sign_ext_b = {{16{b[15]}}, b[15:0]}; 63 | 64 | if (widening[0]) 65 | sign_ext_c = c; 66 | else if (widening[1]) 67 | $error("Trying to quad-widen 16b elements!"); 68 | else 69 | sign_ext_c = {{16{c[15]}}, c[15:0]}; 70 | end 71 | default: 72 | begin 73 | sign_ext_a = a; 74 | sign_ext_b = b; 75 | sign_ext_c = c; 76 | end 77 | endcase 78 | end 79 | 80 | endmodule --------------------------------------------------------------------------------