├── .gitattributes ├── .github ├── dependabot.yaml └── workflows │ ├── eventlist.yml │ ├── gh-pages.yml │ ├── pack.yml │ └── tpip-check.yml ├── .gitignore ├── ARM.CMSIS-View.pdsc ├── Documentation ├── Doxygen │ ├── gen_doc.sh │ ├── linkchecker.rc │ ├── src │ │ ├── cmp_viewer.md │ │ ├── ev_stat.md │ │ ├── event_recorder.md │ │ ├── eventlist.md │ │ ├── examples.md │ │ ├── fault.md │ │ ├── history.md │ │ ├── images │ │ │ ├── ARM_FaultPrint.PNG │ │ │ ├── ARM_FaultRecord.PNG │ │ │ ├── ArmFault.png │ │ │ ├── CM0_RTOS.png │ │ │ ├── CM0_SysTick.png │ │ │ ├── CMSIS_Logo_Final.png │ │ │ ├── CalcMemUsed.png │ │ │ ├── ComponentViewerOverview.png │ │ │ ├── ER_ES.png │ │ │ ├── EventOutput1.png │ │ │ ├── EventOutput2.png │ │ │ ├── EventRecorder.pptx │ │ │ ├── EventRecorder.vsd │ │ │ ├── EventRecorderFilter.png │ │ │ ├── EventRecorderOverview.png │ │ │ ├── EventStatistics.vsdx │ │ │ ├── EventStatistics_w_Energy.png │ │ │ ├── EventStatistics_wo_Energy.png │ │ │ ├── Examples.png │ │ │ ├── Fault_CM33_CV_MemManage.png │ │ │ ├── Fault_CM33_CV_NoFault.png │ │ │ ├── Fault_CM33_EvR_MemManage.png │ │ │ ├── Fault_CM33_STDIO_MemManage.png │ │ │ ├── Fault_CM33_UI.png │ │ │ ├── Fault_CM7_UI.png │ │ │ ├── Fault_CM7_eventlist_MemManage.png │ │ │ ├── Fault_STDIO_MemManage.png │ │ │ ├── Fault_create_iram2.png │ │ │ ├── Fault_memory_location.png │ │ │ ├── Fault_set_comp.png │ │ │ ├── Manage_MyTest_SCVD.png │ │ │ ├── Manage_SCVD_Files.png │ │ │ ├── My1stViewer.png │ │ │ ├── My1stViewerFindSymbolOffset.png │ │ │ ├── My1stViewerMenu.png │ │ │ ├── My2ndViewer.png │ │ │ ├── MyComponentEvents.png │ │ │ ├── MyComponentEvents_withAnnotations.png │ │ │ ├── SCVDExample.png │ │ │ ├── SelEventRecorder.png │ │ │ ├── SelSWComp.png │ │ │ ├── StaticOutput.png │ │ │ ├── Systick_configuration.PNG │ │ │ ├── USB_MSC_Ex.png │ │ │ ├── alert_bold_spec.png │ │ │ ├── c_spec.png │ │ │ ├── config_wizard.png │ │ │ ├── create_iram2.png │ │ │ ├── d_spec.png │ │ │ ├── e_spec.png │ │ │ ├── er_doxygen_links.png │ │ │ ├── er_memory_location.png │ │ │ ├── er_with_statistics.png │ │ │ ├── er_with_statistics_annotated.png │ │ │ ├── es_start_stop_w_energy.png │ │ │ ├── es_start_stop_wo_energy.png │ │ │ ├── es_start_stop_wo_energy_annotated.png │ │ │ ├── estat_ER.png │ │ │ ├── estat_SA.png │ │ │ ├── filter_button.png │ │ │ ├── filtering_events.png │ │ │ ├── form_spec_decimal.png │ │ │ ├── form_spec_text.png │ │ │ ├── i_spec.png │ │ │ ├── mycomponent.png │ │ │ ├── n_spec.png │ │ │ ├── print_spec.png │ │ │ ├── ram_for_algorithm_area.png │ │ │ ├── reset_and_run.png │ │ │ ├── t_spec.png │ │ │ └── webinar_video_preview.png │ │ ├── mainpage.md │ │ ├── ref_evr.txt │ │ ├── ref_fault.txt │ │ └── ref_scvd.txt │ ├── style_template │ │ ├── cmsis_logo_white_small.png │ │ ├── darkmode_toggle.js │ │ ├── dropdown.png │ │ ├── extra_navtree.css │ │ ├── extra_search.css │ │ ├── extra_stylesheet.css │ │ ├── extra_tabs.css │ │ ├── footer.html │ │ ├── footer.js.in │ │ ├── header.html │ │ ├── layout.xml │ │ ├── navtree.js │ │ ├── resize.js │ │ ├── search.css │ │ ├── tab_b.png │ │ ├── tab_topnav.png │ │ ├── tabs.js │ │ └── version.css │ └── view.dxy.in ├── Overview.md ├── README.md ├── index.html └── version.js ├── EventRecorder ├── Config │ └── EventRecorderConf.h ├── EventRecorder.scvd ├── Include │ └── EventRecorder.h └── Source │ └── EventRecorder.c ├── Examples ├── EventStatistic │ ├── EventStatistic.cproject.yml │ ├── EventStatistic.csolution.yml │ ├── README.md │ ├── RTE │ │ ├── CMSIS-View │ │ │ ├── EventRecorderConf.h │ │ │ └── EventRecorderConf.h.base@1.1.0 │ │ ├── Device │ │ │ └── SSE-300-MPS3 │ │ │ │ ├── RTE_Device.h │ │ │ │ ├── RTE_Device.h.base@1.1.0 │ │ │ │ ├── cmsis_driver_config.h │ │ │ │ ├── cmsis_driver_config.h.base@1.1.1 │ │ │ │ ├── device_cfg.h │ │ │ │ ├── device_cfg.h.base@1.1.4 │ │ │ │ ├── fvp_sse300_mps3_s.sct │ │ │ │ ├── fvp_sse300_mps3_s.sct.base@1.1.0 │ │ │ │ ├── platform_base_address.h │ │ │ │ ├── platform_base_address.h.base@1.1.2 │ │ │ │ ├── region_defs.h │ │ │ │ ├── region_defs.h.base@1.0.0 │ │ │ │ ├── region_limits.h │ │ │ │ ├── region_limits.h.base@1.0.0 │ │ │ │ ├── regions_SSE-300-MPS3.h │ │ │ │ ├── startup_SSE300MPS3.c │ │ │ │ ├── startup_SSE300MPS3.c.base@1.1.1 │ │ │ │ ├── system_SSE300MPS3.c │ │ │ │ ├── system_SSE300MPS3.c.base@1.1.1 │ │ │ │ ├── system_SSE300MPS3.h │ │ │ │ └── system_SSE300MPS3.h.base@1.1.1 │ │ ├── _Debug_AVH │ │ │ └── RTE_Components.h │ │ └── _Release_AVH │ │ │ └── RTE_Components.h │ ├── fvp_config.txt │ └── main.c └── Fault │ ├── B-U585I-IOT02A │ ├── Debug.ini │ ├── Fault.cbuild-set.yml │ ├── Fault.csolution.yml │ ├── Fault.uvmpw │ ├── Fault.uvmpw.uvgui │ ├── Flash.ini │ ├── NonSecure │ │ ├── ARM_FaultPrint.c │ │ ├── ARM_FaultTrigger.c │ │ ├── ARM_FaultTrigger.h │ │ ├── Fault.c │ │ ├── Fault_NS.cproject.yml │ │ ├── Fault_NS.uvguix │ │ ├── Fault_NS.uvoptx │ │ ├── Fault_NS.uvprojx │ │ ├── RTE │ │ │ ├── CMSIS-View │ │ │ │ ├── EventRecorderConf.h │ │ │ │ └── EventRecorderConf.h.base@1.1.0 │ │ │ ├── CMSIS │ │ │ │ ├── RTX_Config.c │ │ │ │ ├── RTX_Config.c.base@5.2.0 │ │ │ │ ├── RTX_Config.h │ │ │ │ └── RTX_Config.h.base@5.6.0 │ │ │ └── _Debug_B-U585I-IOT02A │ │ │ │ └── RTE_Components.h │ │ ├── STM32U585AIIXQ_FLASH.ld │ │ ├── retarget_stdio.c │ │ └── stm32u585xx_flash_ns.sct │ ├── README.md │ ├── STM32CubeMX │ │ └── B-U585I-IOT02A │ │ │ ├── Fault_NS.cgen.yml │ │ │ ├── Fault_S.cgen.yml │ │ │ ├── MX_Device │ │ │ ├── NonSecure │ │ │ │ └── MX_Device.h │ │ │ └── Secure │ │ │ │ └── MX_Device.h │ │ │ ├── STM32CubeMX │ │ │ ├── .mxproject │ │ │ ├── Drivers │ │ │ │ ├── CMSIS │ │ │ │ │ ├── Device │ │ │ │ │ │ └── ST │ │ │ │ │ │ │ └── STM32U5xx │ │ │ │ │ │ │ ├── Include │ │ │ │ │ │ │ ├── partition_stm32u5xx.h │ │ │ │ │ │ │ ├── stm32u585xx.h │ │ │ │ │ │ │ ├── stm32u5xx.h │ │ │ │ │ │ │ └── system_stm32u5xx.h │ │ │ │ │ │ │ └── LICENSE.txt │ │ │ │ │ └── LICENSE.txt │ │ │ │ └── STM32U5xx_HAL_Driver │ │ │ │ │ ├── Inc │ │ │ │ │ ├── Legacy │ │ │ │ │ │ └── stm32_hal_legacy.h │ │ │ │ │ ├── stm32u5xx_hal.h │ │ │ │ │ ├── stm32u5xx_hal_cortex.h │ │ │ │ │ ├── stm32u5xx_hal_def.h │ │ │ │ │ ├── stm32u5xx_hal_dma.h │ │ │ │ │ ├── stm32u5xx_hal_dma_ex.h │ │ │ │ │ ├── stm32u5xx_hal_exti.h │ │ │ │ │ ├── stm32u5xx_hal_flash.h │ │ │ │ │ ├── stm32u5xx_hal_flash_ex.h │ │ │ │ │ ├── stm32u5xx_hal_gpio.h │ │ │ │ │ ├── stm32u5xx_hal_gpio_ex.h │ │ │ │ │ ├── stm32u5xx_hal_gtzc.h │ │ │ │ │ ├── stm32u5xx_hal_i2c.h │ │ │ │ │ ├── stm32u5xx_hal_i2c_ex.h │ │ │ │ │ ├── stm32u5xx_hal_icache.h │ │ │ │ │ ├── stm32u5xx_hal_mdf.h │ │ │ │ │ ├── stm32u5xx_hal_ospi.h │ │ │ │ │ ├── stm32u5xx_hal_pcd.h │ │ │ │ │ ├── stm32u5xx_hal_pcd_ex.h │ │ │ │ │ ├── stm32u5xx_hal_pwr.h │ │ │ │ │ ├── stm32u5xx_hal_pwr_ex.h │ │ │ │ │ ├── stm32u5xx_hal_rcc.h │ │ │ │ │ ├── stm32u5xx_hal_rcc_ex.h │ │ │ │ │ ├── stm32u5xx_hal_spi.h │ │ │ │ │ ├── stm32u5xx_hal_spi_ex.h │ │ │ │ │ ├── stm32u5xx_hal_tim.h │ │ │ │ │ ├── stm32u5xx_hal_tim_ex.h │ │ │ │ │ ├── stm32u5xx_hal_uart.h │ │ │ │ │ ├── stm32u5xx_hal_uart_ex.h │ │ │ │ │ ├── stm32u5xx_ll_bus.h │ │ │ │ │ ├── stm32u5xx_ll_cortex.h │ │ │ │ │ ├── stm32u5xx_ll_crs.h │ │ │ │ │ ├── stm32u5xx_ll_dlyb.h │ │ │ │ │ ├── stm32u5xx_ll_dma.h │ │ │ │ │ ├── stm32u5xx_ll_exti.h │ │ │ │ │ ├── stm32u5xx_ll_gpio.h │ │ │ │ │ ├── stm32u5xx_ll_i2c.h │ │ │ │ │ ├── stm32u5xx_ll_icache.h │ │ │ │ │ ├── stm32u5xx_ll_lpgpio.h │ │ │ │ │ ├── stm32u5xx_ll_lpuart.h │ │ │ │ │ ├── stm32u5xx_ll_pwr.h │ │ │ │ │ ├── stm32u5xx_ll_rcc.h │ │ │ │ │ ├── stm32u5xx_ll_spi.h │ │ │ │ │ ├── stm32u5xx_ll_system.h │ │ │ │ │ ├── stm32u5xx_ll_ucpd.h │ │ │ │ │ ├── stm32u5xx_ll_usart.h │ │ │ │ │ ├── stm32u5xx_ll_usb.h │ │ │ │ │ └── stm32u5xx_ll_utils.h │ │ │ │ │ ├── LICENSE.txt │ │ │ │ │ └── Src │ │ │ │ │ ├── stm32u5xx_hal.c │ │ │ │ │ ├── stm32u5xx_hal_cortex.c │ │ │ │ │ ├── stm32u5xx_hal_dma.c │ │ │ │ │ ├── stm32u5xx_hal_dma_ex.c │ │ │ │ │ ├── stm32u5xx_hal_exti.c │ │ │ │ │ ├── stm32u5xx_hal_flash.c │ │ │ │ │ ├── stm32u5xx_hal_flash_ex.c │ │ │ │ │ ├── stm32u5xx_hal_gpio.c │ │ │ │ │ ├── stm32u5xx_hal_gtzc.c │ │ │ │ │ ├── stm32u5xx_hal_i2c.c │ │ │ │ │ ├── stm32u5xx_hal_i2c_ex.c │ │ │ │ │ ├── stm32u5xx_hal_icache.c │ │ │ │ │ ├── stm32u5xx_hal_mdf.c │ │ │ │ │ ├── stm32u5xx_hal_ospi.c │ │ │ │ │ ├── stm32u5xx_hal_pcd.c │ │ │ │ │ ├── stm32u5xx_hal_pcd_ex.c │ │ │ │ │ ├── stm32u5xx_hal_pwr.c │ │ │ │ │ ├── stm32u5xx_hal_pwr_ex.c │ │ │ │ │ ├── stm32u5xx_hal_rcc.c │ │ │ │ │ ├── stm32u5xx_hal_rcc_ex.c │ │ │ │ │ ├── stm32u5xx_hal_spi.c │ │ │ │ │ ├── stm32u5xx_hal_spi_ex.c │ │ │ │ │ ├── stm32u5xx_hal_tim.c │ │ │ │ │ ├── stm32u5xx_hal_tim_ex.c │ │ │ │ │ ├── stm32u5xx_hal_uart.c │ │ │ │ │ ├── stm32u5xx_hal_uart_ex.c │ │ │ │ │ ├── stm32u5xx_ll_dlyb.c │ │ │ │ │ ├── stm32u5xx_ll_dma.c │ │ │ │ │ ├── stm32u5xx_ll_exti.c │ │ │ │ │ ├── stm32u5xx_ll_gpio.c │ │ │ │ │ ├── stm32u5xx_ll_lpgpio.c │ │ │ │ │ ├── stm32u5xx_ll_ucpd.c │ │ │ │ │ ├── stm32u5xx_ll_usb.c │ │ │ │ │ └── stm32u5xx_ll_utils.c │ │ │ ├── MDK-ARM │ │ │ │ └── startup_stm32u585xx.s │ │ │ ├── NonSecure │ │ │ │ ├── Inc │ │ │ │ │ ├── main.h │ │ │ │ │ ├── stm32u5xx_hal_conf.h │ │ │ │ │ └── stm32u5xx_it.h │ │ │ │ └── Src │ │ │ │ │ ├── main.c │ │ │ │ │ ├── stm32u5xx_hal_msp.c │ │ │ │ │ ├── stm32u5xx_hal_timebase_tim.c │ │ │ │ │ ├── stm32u5xx_it.c │ │ │ │ │ └── system_stm32u5xx_ns.c │ │ │ ├── STM32CubeMX.ioc │ │ │ ├── Secure │ │ │ │ ├── Inc │ │ │ │ │ ├── main.h │ │ │ │ │ ├── partition_stm32u585xx.h │ │ │ │ │ ├── stm32_assert.h │ │ │ │ │ ├── stm32u5xx_hal_conf.h │ │ │ │ │ └── stm32u5xx_it.h │ │ │ │ └── Src │ │ │ │ │ ├── main.c │ │ │ │ │ ├── secure_nsc.c │ │ │ │ │ ├── stm32u5xx_hal_msp.c │ │ │ │ │ ├── stm32u5xx_hal_timebase_tim.c │ │ │ │ │ ├── stm32u5xx_it.c │ │ │ │ │ └── system_stm32u5xx_s.c │ │ │ └── Secure_nsclib │ │ │ │ └── secure_nsc.h │ │ │ └── project.script │ └── Secure │ │ ├── Fault_S.cproject.yml │ │ ├── Fault_S.uvguix │ │ ├── Fault_S.uvoptx │ │ ├── Fault_S.uvprojx │ │ ├── RTE │ │ └── _Debug_B-U585I-IOT02A │ │ │ └── RTE_Components.h │ │ ├── STM32U585AIIXQ_FLASH.ld │ │ └── stm32u585xx_flash_s.sct │ └── FVP_MPS2_Cortex-M7 │ ├── ARM_FaultTrigger.c │ ├── ARM_FaultTrigger.h │ ├── Fault.c │ ├── Fault.cproject.yml │ ├── Fault.csolution.yml │ ├── README.md │ ├── RTE │ ├── CMSIS-View │ │ ├── EventRecorderConf.h │ │ └── EventRecorderConf.h.base@1.1.0 │ ├── CMSIS │ │ ├── RTX_Config.c │ │ ├── RTX_Config.c.base@5.2.0 │ │ ├── RTX_Config.h │ │ └── RTX_Config.h.base@5.6.0 │ ├── Device │ │ └── CMSDK_CM7_SP_VHT │ │ │ ├── RTE_Device.h │ │ │ ├── RTE_Device.h.base@1.0.0 │ │ │ ├── ac6_arm.sct │ │ │ ├── ac6_arm.sct.base@1.0.0 │ │ │ ├── gcc_arm.ld │ │ │ ├── gcc_arm.ld.base@1.1.0 │ │ │ ├── startup_CMSDK_CM7.c │ │ │ ├── startup_CMSDK_CM7.c.base@1.1.0 │ │ │ ├── system_CMSDK_CM7.c │ │ │ └── system_CMSDK_CM7.c.base@1.1.0 │ └── _Debug_FVP_MPS2_Cortex-M7 │ │ └── RTE_Components.h │ ├── debug.ini │ ├── fvp_config.txt │ └── retarget_stdio.c ├── Fault ├── ARM_Fault.scvd ├── Include │ └── ARM_Fault.h ├── Source │ ├── ARM_FaultRecord.c │ └── ARM_FaultStorage.c └── Template │ └── ARM_FaultPrint.c ├── LICENSE ├── README.md ├── Schema └── Component_Viewer.xsd ├── gen_pack.sh └── tools └── eventlist ├── .golangci.yaml ├── README.md ├── cmd ├── eventlist │ ├── main.go │ └── main_test.go └── make │ └── make.go ├── docs ├── eventlist.tsdl └── index.html ├── go.mod ├── go.sum ├── make.sh ├── pkg ├── elf │ ├── elf.go │ └── elf_test.go ├── eval │ ├── eval.go │ ├── eval_test.go │ ├── expression.go │ ├── expression_test.go │ ├── value.go │ ├── value_test.go │ ├── variable.go │ └── variable_test.go ├── event │ ├── event.go │ └── event_test.go ├── output │ ├── output.go │ └── output_test.go └── xml │ └── scvd │ ├── scvd.go │ └── scvd_test.go ├── template └── third_party_licenses.md.template ├── testdata ├── elfsym.elf ├── elftest.elf ├── test.binary ├── test.xml ├── test0.binary ├── test1.binary ├── test1.xml ├── test10.binary ├── test11.binary ├── test12.binary ├── test13.binary ├── test2.binary ├── test3.binary ├── test4.binary ├── test5.binary ├── test6.binary ├── test7.binary ├── test8.binary ├── test9.binary ├── test_err1.xml ├── test_err2.xml └── test_err3.xml └── third_party_licenses.md /.gitattributes: -------------------------------------------------------------------------------- 1 | # Denote all files that are truly binary and should not be modified. 2 | *.binary binary 3 | *.syso binary 4 | -------------------------------------------------------------------------------- /.github/dependabot.yaml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: github-actions 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | open-pull-requests-limit: 10 8 | rebase-strategy: disabled 9 | -------------------------------------------------------------------------------- /.github/workflows/gh-pages.yml: -------------------------------------------------------------------------------- 1 | # Simple workflow for deploying static content to GitHub Pages 2 | name: Deploy static content to GitHub Pages 3 | 4 | on: 5 | # Runs on pushes targeting the default branch 6 | push: 7 | branches: [gh-pages] 8 | 9 | # Allows you to run this workflow manually from the Actions tab 10 | workflow_dispatch: 11 | 12 | # Sets permissions of the GITHUB_TOKEN to allow deployment to GitHub Pages 13 | permissions: 14 | contents: read 15 | pages: write 16 | id-token: write 17 | 18 | # Allow only one concurrent deployment, skipping runs queued between the run in-progress and latest queued. 19 | # However, do NOT cancel in-progress runs as we want to allow these production deployments to complete. 20 | concurrency: 21 | group: "pages" 22 | cancel-in-progress: false 23 | 24 | jobs: 25 | # Single deploy job since we're just deploying 26 | deploy: 27 | environment: 28 | name: github-pages 29 | url: ${{ steps.deployment.outputs.page_url }} 30 | runs-on: ubuntu-latest 31 | steps: 32 | - name: Checkout 33 | uses: actions/checkout@v4 34 | 35 | - name: Setup Pages 36 | uses: actions/configure-pages@v5 37 | 38 | - name: Upload artifact 39 | uses: actions/upload-pages-artifact@v3 40 | with: 41 | # Upload entire repository 42 | path: '.' 43 | 44 | - name: Deploy to GitHub Pages 45 | id: deployment 46 | uses: actions/deploy-pages@v4 47 | -------------------------------------------------------------------------------- /.github/workflows/pack.yml: -------------------------------------------------------------------------------- 1 | name: Build documentation and pack 2 | on: 3 | workflow_dispatch: 4 | pull_request: 5 | push: 6 | branches: [main] 7 | release: 8 | types: [published] 9 | 10 | concurrency: 11 | group: ${{ github.workflow }}-${{ github.ref }} 12 | cancel-in-progress: true 13 | 14 | jobs: 15 | pack: 16 | name: Generate pack 17 | runs-on: ubuntu-22.04 18 | steps: 19 | - uses: actions/checkout@v4 20 | with: 21 | fetch-depth: 0 22 | 23 | - name: Fetch tags 24 | if: github.event_name == 'release' 25 | run: | 26 | git fetch --tags --force 27 | 28 | - uses: Open-CMSIS-Pack/gen-pack-action@main 29 | with: 30 | doxygen-version: 1.13.2 31 | packchk-version: 1.4.1 32 | gen-doc-script: ./Documentation/Doxygen/gen_doc.sh 33 | doc-path: ./Documentation/html 34 | gen-pack-script: ./gen_pack.sh --no-preprocess 35 | gen-pack-output: ./output 36 | gh-pages-branch: gh-pages 37 | -------------------------------------------------------------------------------- /.github/workflows/tpip-check.yml: -------------------------------------------------------------------------------- 1 | name: TPIP Check 2 | 3 | on: 4 | pull_request: 5 | paths: 6 | - ".github/workflows/tpip-check.yml" 7 | - "**/go.mod" 8 | - "**/go.sum" 9 | - "tools/eventlist/template/**" 10 | workflow_dispatch: 11 | schedule: 12 | - cron: '0 0 * * *' 13 | 14 | env: 15 | tpip_report: "third_party_licenses.md" 16 | 17 | jobs: 18 | check-licenses: 19 | runs-on: ubuntu-latest 20 | timeout-minutes: 5 21 | steps: 22 | - uses: actions/checkout@v4 23 | 24 | - name: Set up Go 25 | uses: actions/setup-go@v5 26 | with: 27 | cache-dependency-path: tools/eventlist/go.sum 28 | go-version-file: tools/eventlist/go.mod 29 | check-latest: true 30 | 31 | - name: Go tidy 32 | run: go mod tidy 33 | working-directory: ./tools/eventlist 34 | 35 | - name: Install go-licenses 36 | run: go install github.com/google/go-licenses@latest 37 | 38 | - name: Generate TPIP Report 39 | run: | 40 | cp LICENSE ./tools/eventlist 41 | 42 | - name: Generate TPIP Report 43 | run: | 44 | go-licenses report . ../make --ignore github.com/ARM-software/CMSIS-View/tree/main/tools/eventlist --template ../../template/${{ env.tpip_report }}.template > ../../${{ env.tpip_report }} 45 | working-directory: ./tools/eventlist/cmd/eventlist 46 | 47 | - name: Archive TPIP report 48 | uses: actions/upload-artifact@v4 49 | with: 50 | name: tpip-report 51 | path: ./tools/eventlist/${{ env.tpip_report }} 52 | 53 | - name: Print TPIP Report 54 | run: cat ${{ env.tpip_report }} >> $GITHUB_STEP_SUMMARY 55 | working-directory: ./tools/eventlist 56 | 57 | - name: Check Licenses 58 | run: go-licenses check . --ignore github.com/ARM-software/CMSIS-View/tree/main/tools/eventlist --disallowed_types=forbidden,restricted 59 | working-directory: ./tools/eventlist/cmd/eventlist 60 | 61 | commit-changes: 62 | # Running this job only on specific event 63 | # in order to have workaround for issue 64 | # related to deletion of GH checks/status data 65 | if: (github.event_name == 'schedule') || (github.event_name == 'workflow_dispatch') 66 | needs: [ check-licenses ] 67 | runs-on: ubuntu-latest 68 | timeout-minutes: 5 69 | steps: 70 | - uses: actions/checkout@v4 71 | with: 72 | ref: ${{ github.event.pull_request.head.ref }} 73 | 74 | - name: Restore Changes 75 | uses: actions/download-artifact@v4 76 | with: 77 | name: tpip-report 78 | path: ./tools/eventlist 79 | 80 | - name: Create Pull Request 81 | uses: peter-evans/create-pull-request@v7 82 | with: 83 | commit-message: Update TPIP report 84 | title: ':robot: [TPIP] Automated report updates' 85 | body: | 86 | Third party IP report updates 87 | branch: update-tpip 88 | delete-branch: true 89 | labels: TPIP 90 | reviewers: soumeh01 91 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Binaries 2 | *.o 3 | *.lib 4 | *.exe 5 | *.dll 6 | *.so 7 | *.dylib 8 | 9 | # macOS 10 | .DS_Store 11 | 12 | # Generated Files 13 | /Documentation/html 14 | /Documentation/Doxygen/src/history.txt 15 | /Documentation/Doxygen/view.dxy 16 | /PACK.xsd 17 | /output 18 | /build 19 | /Examples/**/*.cbuild.yml 20 | /Examples/**/*.cbuild-run.yml 21 | /Examples/**/*.cbuild-pack.yml 22 | /Examples/**/*.cprj 23 | /Examples/**/RTE/_**/* 24 | /Examples/**/.clangd 25 | /Examples/**/*.cbuild-idx.yml 26 | /Examples/**/*.uvgui*.* 27 | /Examples/**/DebugConfig/*.dbgconf 28 | /Examples/**/out 29 | /Examples/**/tmp 30 | /Examples/**/Listings 31 | /Examples/**/Objects 32 | 33 | # Test binary, built with `go test -c` 34 | *.test 35 | __debug_bin 36 | 37 | # Output of the go coverage tool 38 | *.out 39 | 40 | # Output of the linkchecker tool 41 | linkchecker-out.csv 42 | 43 | *.sw* 44 | **/.trunk 45 | **/.vscode 46 | 47 | *.bak 48 | *.syso 49 | *.log 50 | *~ 51 | -------------------------------------------------------------------------------- /Documentation/Doxygen/gen_doc.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # Version: 3.0 3 | # Date: 2023-11-06 4 | # This bash script generates CMSIS-View documentation 5 | # 6 | # Pre-requisites: 7 | # - bash shell (for Windows: install git for Windows) 8 | # - doxygen 1.9.6 9 | # - linkchecker (can be skipped with -s) 10 | 11 | set -o pipefail 12 | 13 | # Set version of gen pack library 14 | # For available versions see https://github.com/Open-CMSIS-Pack/gen-pack/tags. 15 | # Use the tag name without the prefix "v", e.g., 0.7.0 16 | REQUIRED_GEN_PACK_LIB="0.11.2" 17 | 18 | DIRNAME=$(dirname "$(readlink -f "$0")") 19 | GENDIR=../html 20 | REQ_DXY_VERSION="1.13.2" 21 | 22 | RUN_LINKCHECKER=1 23 | COMPONENTS=() 24 | 25 | function usage() { 26 | echo "Usage: $(basename "$0") [-h] [-s] [-c ]" 27 | echo " -h,--help Show usage" 28 | echo " -s,--no-linkcheck Skip linkcheck" 29 | echo " -c,--component Select component to generate documentation for. " 30 | echo " Can be given multiple times. Defaults to all components." 31 | } 32 | 33 | while [[ $# -gt 0 ]]; do 34 | case $1 in 35 | '-h'|'help') 36 | usage 37 | exit 1 38 | ;; 39 | '-s'|'--no-linkcheck') 40 | RUN_LINKCHECKER=0 41 | ;; 42 | '-c'|'--component') 43 | shift 44 | COMPONENTS+=("$1") 45 | ;; 46 | *) 47 | echo "Invalid command line argument: $1" >&2 48 | usage 49 | exit 1 50 | ;; 51 | esac 52 | shift # past argument 53 | done 54 | 55 | ############ DO NOT EDIT BELOW ########### 56 | 57 | # Set GEN_PACK_LIB_PATH to use a specific gen-pack library root 58 | # ... instead of bootstrap based on REQUIRED_GEN_PACK_LIB 59 | if [[ -f "${GEN_PACK_LIB_PATH}/gen-pack" ]]; then 60 | . "${GEN_PACK_LIB_PATH}/gen-pack" 61 | else 62 | . <(curl -sL "https://raw.githubusercontent.com/Open-CMSIS-Pack/gen-pack/main/bootstrap") 63 | fi 64 | 65 | find_git 66 | find_doxygen "${REQ_DXY_VERSION}" 67 | [[ ${RUN_LINKCHECKER} != 0 ]] && find_linkchecker 68 | 69 | if [ -z "${VERSION_FULL}" ]; then 70 | VERSION_FULL=$(git_describe "pack/") 71 | fi 72 | 73 | pushd "${DIRNAME}" > /dev/null 74 | 75 | echo "Generating documentation ..." 76 | 77 | projectName=$(grep -E "PROJECT_NAME\s+=" view.dxy.in | sed -r -e 's/[^"]*"([^"]+)".*/\1/') 78 | projectNumberFull="${VERSION_FULL}" 79 | projectNumber="${projectNumberFull%+*}" 80 | datetime=$(date -u +'%a %b %e %Y %H:%M:%S') 81 | year=$(date -u +'%Y') 82 | 83 | sed -e "s/{projectNumber}/${projectNumber}/" view.dxy.in > view.dxy 84 | 85 | git_changelog -f html -p "pack/" > src/history.txt 86 | 87 | echo "\"${UTILITY_DOXYGEN}\" view.dxy" 88 | "${UTILITY_DOXYGEN}" view.dxy 89 | 90 | mkdir -p "${DIRNAME}/${GENDIR}/search/" 91 | cp -f "${DIRNAME}/style_template/search.css" "${DIRNAME}/${GENDIR}/search/" 92 | cp -f "${DIRNAME}/style_template/navtree.js" "${DIRNAME}/${GENDIR}/" 93 | cp -f "${DIRNAME}/style_template/resize.js" "${DIRNAME}/${GENDIR}/" 94 | 95 | sed -e "s/{datetime}/${datetime}/" "${DIRNAME}/style_template/footer.js.in" \ 96 | | sed -e "s/{year}/${year}/" \ 97 | | sed -e "s/{projectName}/${projectName}/" \ 98 | | sed -e "s/{projectNumber}/${projectNumber}/" \ 99 | | sed -e "s/{projectNumberFull}/${projectNumberFull}/" \ 100 | > "${DIRNAME}/${GENDIR}/footer.js" 101 | 102 | popd > /dev/null 103 | 104 | [[ ${RUN_LINKCHECKER} != 0 ]] && check_links "${DIRNAME}/../html/index.html" "${DIRNAME}" 105 | 106 | 107 | exit 0 108 | -------------------------------------------------------------------------------- /Documentation/Doxygen/linkchecker.rc: -------------------------------------------------------------------------------- 1 | [output] 2 | ignoreerrors= 3 | mag.svg 4 | mag_sel.svg 5 | mag_d.svg 6 | mag_seld.svg 7 | ../tab_a.png 8 | ../tab_ad.png 9 | 10 | [filtering] 11 | ignorewarnings= 12 | http-redirected 13 | -------------------------------------------------------------------------------- /Documentation/Doxygen/src/ev_stat.md: -------------------------------------------------------------------------------- 1 | # Event Statistics {#ev_stat} 2 | 3 | ## Overview {#about_event_statistics} 4 | 5 | The \ref Event_Execution_Statistic functions allow you to collect and statistical data about the code execution. Any debug adapter can be used to record execution timing and number of calls for annotated code sections: 6 | 7 | ![Event Statistics for user code](./images/EventStatistics_wo_Energy.png) 8 | 9 | Energy profiling is of annotated code sections is possible using [ULINKplus](https://developer.arm.com/Tools%20and%20Software/ULINKplus). When combined with power measurement, the Event Statistics window displays the energy consumption of the code section with min/man/average values: 10 | 11 | ![User code energy profiling](./images/EventStatistics_w_Energy.png) 12 | 13 | For more information, refer to the \ref scvd_evt_stat example. 14 | 15 | **Benefits of Event Statistics:** 16 | 17 | - Collect statistical data about the code execution (time and energy). 18 | - Log files enable comparisons between different build runs in continuous integration (CI) environments. 19 | - Improve overall code quality and energy profile (especially relevant for battery driven applications). 20 | 21 | ## Display current consumption{#es_display_energy} 22 | 23 | Using a ULINKplus debug adapter, you can also record and analyze the energy that has been consumed in each execution slot. Using the above example on a hardware target with a ULINKplus, you get the 24 | following display in the \estatistics window of µVision (the \erecorder window does not change): 25 | 26 | ![Event Statistics displaying the energy consumption](./images/es_start_stop_w_energy.png) 27 | 28 | -------------------------------------------------------------------------------- /Documentation/Doxygen/src/history.md: -------------------------------------------------------------------------------- 1 | # Revision History {#rev_hist} 2 | 3 | CMSIS-View version is officially updated upon releases of the [CMSIS-View pack](https://www.keil.arm.com/packs/cmsis-view-arm/versions/). 4 | 5 | The table below provides information about the changes delivered with specific versions of CMSIS-View. 6 | -------------------------------------------------------------------------------- /Documentation/Doxygen/src/images/ARM_FaultPrint.PNG: -------------------------------------------------------------------------------- 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writeHeader() { 2 | document.write('Version {projectNumber}'); 3 | }; 4 | 5 | function writeFooter() { 6 | document.write('Generated on {datetime} for {projectName} {projectNumberFull}. Copyright © {year} Arm Limited (or its affiliates). All rights reserved.'); 7 | }; 8 | -------------------------------------------------------------------------------- /Documentation/Doxygen/style_template/header.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | $projectname: $title 9 | $title 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | $treeview 22 | $search 23 | $mathjax 24 | $darkmode 25 | $extrastylesheet 26 | 27 | 28 | 29 | 30 | 31 |
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  • ' + this.tabTxt + '
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    • '; 10 | }; 11 | 12 | // array of objects 13 | var arr = []; 14 | 15 | // fill array 16 | // arr.push( new tabElement( "Zone", ".", "Zone")); 17 | 18 | // write tabs 19 | // called from the header file. 20 | function writeComponentTabs() { 21 | for ( var i=0; i < arr.length; i++ ) { 22 | str = "/" + arr[i].folderName + "/" 23 | if (strgURL.search(str) > 0) { // if this is the current folder 24 | document.write(arr[i].currentListItem); // then print and highlight the tab 25 | } else { 26 | document.write(arr[i].listItem); // else, print the tab 27 | } 28 | } 29 | }; 30 | -------------------------------------------------------------------------------- /Documentation/Doxygen/style_template/version.css: -------------------------------------------------------------------------------- 1 | :root { 2 | --arm_light_blue: #00C1DE; 3 | --arm_blue: #11809F; 4 | --arm_blue1: #0091BD; 5 | --arm_dark_blue: #002B49; 6 | --arm_light_gray: #E5ECEB; 7 | --arm_light_gray1: #EFF5F4; 8 | --arm_light_gray2: #EBEBEB; 9 | --arm_light_gray3: #F7F7F7; 10 | --arm_dark_gray: #7D868C; 11 | --arm_black: #333E48; 12 | --arm_orange: #FF6B00; 13 | --arm_yellow: #FFC700; 14 | } 15 | 16 | /* Dropdown Button */ 17 | .dropbtn { 18 | margin: 0px; 19 | padding: 0px 20px 0px 0em; 20 | background-image: url("dropdown.png"); 21 | background-repeat: no-repeat; 22 | background-size: 0.5em; 23 | background-position: right center; 24 | cursor: pointer; 25 | } 26 | 27 | /* The container
    - needed to position the dropdown content */ 28 | .dropdown { 29 | position: relative; 30 | display: inline-block; 31 | } 32 | 33 | /* Dropdown Content (Hidden by Default) */ 34 | .dropdown-content { 35 | display: none; 36 | position: absolute; 37 | background-color: var(--arm_light_gray3); 38 | min-width: 160px; 39 | box-shadow: 0px 8px 16px 0px rgba(0,0,0,0.4); 40 | white-space: nowrap; 41 | cursor: pointer; 42 | z-index: 1; 43 | } 44 | 45 | /* Links inside the dropdown */ 46 | .dropdown-content a { 47 | # color: black; 48 | color: var(--arm_dark_gray); 49 | padding: 4px 6px; 50 | text-decoration: none; 51 | display: block; 52 | } 53 | 54 | /* Change color of dropdown links on hover */ 55 | .dropdown-content a:hover {background-color: #ddd} 56 | 57 | /* Show the dropdown menu (use JS to add this class to the .dropdown-content container when the user clicks on the dropdown button) */ 58 | .show {display:block;} 59 | -------------------------------------------------------------------------------- /Documentation/Overview.md: -------------------------------------------------------------------------------- 1 | # Introduction 2 | 3 | **CMSIS-View** provides software components and utilities that allow embedded software developers to analyze program execution flows, debug potential issues, and measure code execution times. The data can be observed in real-time in an IDE or can be saved as a log file during program execution. 4 | 5 | CMSIS-View contains these components: 6 | 7 | - [Event Recorder](https://arm-software.github.io/CMSIS-View/latest/evr.html) - lets you record event timing and data information while the program is executing. 8 | - [Event Statistics](https://arm-software.github.io/CMSIS-View/latest/ev_stat.html) - allows you to collect and statistical data about the code execution. 9 | - [eventlist utility](https://arm-software.github.io/CMSIS-View/latest/evntlst.html) - a command line tool for processing Event Recorder log files. 10 | - [Component Viewer](https://arm-software.github.io/CMSIS-View/latest/cmp_viewer.html) - provides visibility to the user relevant static information of a software component or application program. 11 | - [Fault](https://arm-software.github.io/CMSIS-View/latest/fault.html) - allows you to store, record, and analyze exception fault information. 12 | 13 | For more information, please refer to: 14 | 15 | - [Repository](https://github.com/ARM-software/CMSIS-View) 16 | - [Documentation](https://arm-software.github.io/CMSIS-View/latest/index.html) 17 | 18 | ## CMSIS-View Introduction Webinar 19 | 20 | Watch the [introduction webinar](https://developer.arm.com/Additional%20Resources/Video%20Tutorials/CMSIS-View%20and%20CMSIS-Compiler) to learn about CMSIS-View and how to use it. 21 | 22 | [![Using CMSIS-View and CMSIS-Compiler Webinar](./Doxygen/src/images/webinar_video_preview.png)](https://developer.arm.com/Additional%20Resources/Video%20Tutorials/CMSIS-View%20and%20CMSIS-Compiler) 23 | 24 | ## Related CMSIS-Packs 25 | 26 | The following CMSIS-Packs are maintained by Arm and related to CMSIS-View. 27 | 28 | ### CMSIS Component Packs 29 | 30 | - [CMSIS-Compiler](https://www.keil.arm.com/packs/cmsis-compiler-arm): Retarget I/O functions of the standard C run-time library. 31 | - [CMSIS-DSP](https://www.keil.arm.com/packs/cmsis-dsp-arm/): Optimized compute functions for embedded systems. 32 | - [CMSIS-NN](https://www.keil.arm.com/packs/cmsis-nn-arm): Efficient and performant neural network kernels. 33 | 34 | ### Real-time Operating Systems 35 | 36 | - [CMSIS-RTX](https://www.keil.arm.com/packs/cmsis-rtx-arm): Keil RTX5, a CMSIS-RTOS2 API compliant real-time operating system. 37 | - [CMSIS-FreeRTOS](https://github.com/ARM-software/CMSIS-FreeRTOS): CMSIS-RTOS adaptation of FreeRTOS. 38 | - [CMSIS-RTOS2 Validation](https://github.com/arm-software/CMSIS-RTOS2_Validation): Validation suite for RTOS2 compliant implementations. 39 | 40 | ### Middleware 41 | 42 | - [MDK-Middleware](https://www.keil.arm.com/packs/mdk-middleware-keil): File system, network, and USB stacks. 43 | - [CMSIS-mbedTLS](https://github.com/ARM-software/CMSIS-mbedTLS): Mbed TLS framed in a CMSIS-Pack. 44 | - [SDS-Framework](https://github.com/ARM-software/SDS-Framework): Synchronous data streaming. 45 | 46 | ### Other Software Components 47 | 48 | - [Cortex_DFP](https://github.com/ARM-software/CMSIS-DFP): Generic Arm Cortex-M device family pack. 49 | - [CMSIS-Driver](https://github.com/ARM-software/CMSIS-Driver): MCU peripheral driver implementations. 50 | - [CMSIS-Driver Validation](https://github.com/ARM-software/CMSIS-Driver_Validation/): Validation suite for CMSIS-Driver implementations. 51 | -------------------------------------------------------------------------------- /Documentation/README.md: -------------------------------------------------------------------------------- 1 | # CMSIS-View Documentation 2 | 3 | CMSIS-View Documentation in HTML format is published online at [https://arm-software.github.io/CMSIS-View](https://arm-software.github.io/CMSIS-View). 4 | 5 | The version drop-down menu there allows to switch between the documentation provided with official releases and the latest draft documentation for the main branch. 6 | 7 | The documentation source is maintained in `Documentation/Doxygen/` folder as a mixture of markdown and doxygen formats. Component source files, templates and examples may also contribute information that gets integrated into the final documentation. 8 | 9 | Generating the HTML-formatted documentation from the source is done with `gen_doc.sh` script: 10 | 11 | ```sh 12 | CMSIS-View $ ./Documentation/Doxygen/gen_doc.sh 13 | ``` 14 | 15 | The script expects specific version of [doxygen](https://www.doxygen.nl/) to be installed locally. After successful execution the resulting documentation package is then available in `./Documentation/html/`. 16 | -------------------------------------------------------------------------------- /Documentation/index.html: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | Redirect to the main page after 0 seconds 5 | 6 | 7 | 8 | 9 | 10 | 11 | If the automatic redirection is failing, click open Documentation. 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /Documentation/version.js: -------------------------------------------------------------------------------- 1 | function writeVersionDropdown() { 2 | }; 3 | -------------------------------------------------------------------------------- /EventRecorder/Config/EventRecorderConf.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 0 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/EventStatistic/EventStatistic.cproject.yml: -------------------------------------------------------------------------------- 1 | project: 2 | description: Event Statistic example 3 | 4 | packs: 5 | - pack: ARM::CMSIS-View@^1.2.0-0 6 | - pack: ARM::CMSIS@^6.1.0 7 | 8 | groups: 9 | - group: Documentation 10 | files: 11 | - file: README.md 12 | 13 | - group: Source Files 14 | files: 15 | - file: main.c 16 | 17 | components: 18 | - component: CMSIS:CORE 19 | 20 | - component: CMSIS-View:Event Recorder&Semihosting 21 | 22 | - component: Device:Definition 23 | - component: Device:Native Driver:SysCounter 24 | - component: Device:Native Driver:SysTimer 25 | - component: Device:Native Driver:Timeout 26 | 27 | - component: Device:Startup&C Startup 28 | 29 | linker: 30 | - script: ./RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct 31 | for-compiler: AC6 32 | -------------------------------------------------------------------------------- /Examples/EventStatistic/EventStatistic.csolution.yml: -------------------------------------------------------------------------------- 1 | solution: 2 | description: Event Statistic example 3 | created-for: CMSIS-Toolbox@2.6.0 4 | cdefault: 5 | 6 | select-compiler: 7 | # list of tested compilers that can be selected 8 | - compiler: AC6 9 | 10 | packs: 11 | - pack: ARM::V2M_MPS3_SSE_300_BSP@1.5.0 12 | 13 | target-types: 14 | - type: AVH 15 | board: ARM::V2M-MPS3-SSE-300-FVP 16 | device: ARM::SSE-300-MPS3 17 | 18 | build-types: 19 | - type: Debug 20 | debug: on 21 | optimize: debug 22 | 23 | - type: Release 24 | debug: off 25 | optimize: size 26 | 27 | projects: 28 | - project: EventStatistic.cproject.yml 29 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 1 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 0 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __CMSIS_DRIVER_CONFIG_H__ 18 | #define __CMSIS_DRIVER_CONFIG_H__ 19 | 20 | #include "system_SSE300MPS3.h" 21 | #include "device_cfg.h" 22 | #include "device_definition.h" 23 | #include "platform_base_address.h" 24 | 25 | #endif /* __CMSIS_DRIVER_CONFIG_H__ */ 26 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/cmsis_driver_config.h.base@1.1.1: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019-2022 Arm Limited. All rights reserved. 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __CMSIS_DRIVER_CONFIG_H__ 18 | #define __CMSIS_DRIVER_CONFIG_H__ 19 | 20 | #include "system_SSE300MPS3.h" 21 | #include "device_cfg.h" 22 | #include "device_definition.h" 23 | #include "platform_base_address.h" 24 | 25 | #endif /* __CMSIS_DRIVER_CONFIG_H__ */ 26 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct: -------------------------------------------------------------------------------- 1 | #! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc 2 | 3 | ;/* 4 | ; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. 5 | ; * 6 | ; * Licensed under the Apache License, Version 2.0 (the "License"); 7 | ; * you may not use this file except in compliance with the License. 8 | ; * You may obtain a copy of the License at 9 | ; * 10 | ; * http://www.apache.org/licenses/LICENSE-2.0 11 | ; * 12 | ; * Unless required by applicable law or agreed to in writing, software 13 | ; * distributed under the License is distributed on an "AS IS" BASIS, 14 | ; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ; * See the License for the specific language governing permissions and 16 | ; * limitations under the License. 17 | ; * 18 | ; */ 19 | 20 | #include "region_defs.h" 21 | 22 | LR_CODE S_CODE_START { 23 | ER_CODE S_CODE_START { 24 | *.o (RESET +First) 25 | .ANY (+RO) 26 | } 27 | 28 | /* 29 | * Place the CMSE Veneers (containing the SG instruction) after the code, in 30 | * a separate 32 bytes aligned region so that the SAU can programmed to just 31 | * set this region as Non-Secure Callable. The maximum size of this 32 | * executable region makes it only used the space left over by the ER_CODE 33 | * region so that you can rely on code+veneer size combined will not exceed 34 | * the S_CODE_SIZE value. We also substract from the available space the 35 | * area used to align this section on 32 bytes boundary (for SAU conf). 36 | */ 37 | ER_CODE_CMSE_VENEER +0 ALIGN 32 { 38 | *(Veneer$$CMSE) 39 | } 40 | /* 41 | * This dummy region ensures that the next one will be aligned on a 32 bytes 42 | * boundary, so that the following region will not be mistakenly configured 43 | * as Non-Secure Callable by the SAU. 44 | */ 45 | ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} 46 | 47 | /* This empty, zero long execution region is here to mark the limit address 48 | * of the last execution region that is allocated in SRAM. 49 | */ 50 | CODE_WATERMARK +0 EMPTY 0x0 { 51 | } 52 | /* Make sure that the sections allocated in the SRAM does not exceed the 53 | * size of the SRAM available. 54 | */ 55 | ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) 56 | 57 | ER_DATA S_DATA_START { 58 | .ANY (+ZI +RW) 59 | } 60 | 61 | ER_DATA_NOINIT +0 ALIGN 64 UNINIT 0x00002000 { 62 | *(.bss.noinit) 63 | *(.bss.noinit.*) 64 | } 65 | 66 | #if HEAP_SIZE > 0 67 | ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap 68 | } 69 | #endif 70 | 71 | ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack 72 | } 73 | 74 | /* This empty, zero long execution region is here to mark the limit address 75 | * of the last execution region that is allocated in SRAM. 76 | */ 77 | SRAM_WATERMARK +0 EMPTY 0x0 { 78 | } 79 | /* Make sure that the sections allocated in the SRAM does not exceed the 80 | * size of the SRAM available. 81 | */ 82 | ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) 83 | } 84 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/fvp_sse300_mps3_s.sct.base@1.1.0: -------------------------------------------------------------------------------- 1 | #! armclang --target=arm-arm-none-eabi -march=armv8.1-m.main -E -xc 2 | 3 | ;/* 4 | ; * Copyright (c) 2018-2021 Arm Limited. All rights reserved. 5 | ; * 6 | ; * Licensed under the Apache License, Version 2.0 (the "License"); 7 | ; * you may not use this file except in compliance with the License. 8 | ; * You may obtain a copy of the License at 9 | ; * 10 | ; * http://www.apache.org/licenses/LICENSE-2.0 11 | ; * 12 | ; * Unless required by applicable law or agreed to in writing, software 13 | ; * distributed under the License is distributed on an "AS IS" BASIS, 14 | ; * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | ; * See the License for the specific language governing permissions and 16 | ; * limitations under the License. 17 | ; * 18 | ; */ 19 | 20 | #include "region_defs.h" 21 | 22 | LR_CODE S_CODE_START { 23 | ER_CODE S_CODE_START { 24 | *.o (RESET +First) 25 | .ANY (+RO) 26 | } 27 | 28 | /* 29 | * Place the CMSE Veneers (containing the SG instruction) after the code, in 30 | * a separate 32 bytes aligned region so that the SAU can programmed to just 31 | * set this region as Non-Secure Callable. The maximum size of this 32 | * executable region makes it only used the space left over by the ER_CODE 33 | * region so that you can rely on code+veneer size combined will not exceed 34 | * the S_CODE_SIZE value. We also substract from the available space the 35 | * area used to align this section on 32 bytes boundary (for SAU conf). 36 | */ 37 | ER_CODE_CMSE_VENEER +0 ALIGN 32 { 38 | *(Veneer$$CMSE) 39 | } 40 | /* 41 | * This dummy region ensures that the next one will be aligned on a 32 bytes 42 | * boundary, so that the following region will not be mistakenly configured 43 | * as Non-Secure Callable by the SAU. 44 | */ 45 | ER_CODE_CMSE_VENEER_DUMMY +0 ALIGN 32 EMPTY 0 {} 46 | 47 | /* This empty, zero long execution region is here to mark the limit address 48 | * of the last execution region that is allocated in SRAM. 49 | */ 50 | CODE_WATERMARK +0 EMPTY 0x0 { 51 | } 52 | /* Make sure that the sections allocated in the SRAM does not exceed the 53 | * size of the SRAM available. 54 | */ 55 | ScatterAssert(ImageLimit(CODE_WATERMARK) <= S_CODE_START + S_CODE_SIZE) 56 | 57 | ER_DATA S_DATA_START { 58 | .ANY (+ZI +RW) 59 | } 60 | 61 | #if HEAP_SIZE > 0 62 | ARM_LIB_HEAP +0 ALIGN 8 EMPTY HEAP_SIZE { ; Reserve empty region for heap 63 | } 64 | #endif 65 | 66 | ARM_LIB_STACK +0 ALIGN 32 EMPTY STACK_SIZE { ; Reserve empty region for stack 67 | } 68 | 69 | /* This empty, zero long execution region is here to mark the limit address 70 | * of the last execution region that is allocated in SRAM. 71 | */ 72 | SRAM_WATERMARK +0 EMPTY 0x0 { 73 | } 74 | /* Make sure that the sections allocated in the SRAM does not exceed the 75 | * size of the SRAM available. 76 | */ 77 | ScatterAssert(ImageLimit(SRAM_WATERMARK) <= S_DATA_START + S_DATA_SIZE) 78 | } 79 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2022 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __REGION_DEFS_H__ 18 | #define __REGION_DEFS_H__ 19 | 20 | #include "region_limits.h" 21 | 22 | /* ************************************************************** 23 | * WARNING: this file is parsed both by the C/C++ compiler 24 | * and the linker. As a result the syntax must be valid not only 25 | * for C/C++ but for the linker scripts too. 26 | * Beware of the following limitations: 27 | * - LD (GCC linker) requires white space around operators. 28 | * - UL postfix for macros is not suported by the linker script 29 | ****************************************************************/ 30 | 31 | /* Secure regions */ 32 | #define S_CODE_START ( S_ROM_ALIAS ) 33 | #define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) 34 | #define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) 35 | 36 | #define S_DATA_START ( S_RAM_ALIAS ) 37 | #define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) 38 | #define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) 39 | 40 | #define S_DDR4_START ( S_DDR4_ALIAS ) 41 | #define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) 42 | #define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) 43 | 44 | #endif /* __REGION_DEFS_H__ */ 45 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_defs.h.base@1.0.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2022 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __REGION_DEFS_H__ 18 | #define __REGION_DEFS_H__ 19 | 20 | #include "region_limits.h" 21 | 22 | /* ************************************************************** 23 | * WARNING: this file is parsed both by the C/C++ compiler 24 | * and the linker. As a result the syntax must be valid not only 25 | * for C/C++ but for the linker scripts too. 26 | * Beware of the following limitations: 27 | * - LD (GCC linker) requires white space around operators. 28 | * - UL postfix for macros is not suported by the linker script 29 | ****************************************************************/ 30 | 31 | /* Secure regions */ 32 | #define S_CODE_START ( S_ROM_ALIAS ) 33 | #define S_CODE_SIZE ( TOTAL_S_ROM_SIZE ) 34 | #define S_CODE_LIMIT ( S_CODE_START + S_CODE_SIZE ) 35 | 36 | #define S_DATA_START ( S_RAM_ALIAS ) 37 | #define S_DATA_SIZE ( TOTAL_S_RAM_SIZE ) 38 | #define S_DATA_LIMIT ( S_DATA_START + S_DATA_SIZE ) 39 | 40 | #define S_DDR4_START ( S_DDR4_ALIAS ) 41 | #define S_DDR4_SIZE ( TOTAL_S_DDR4_SIZE ) 42 | #define S_DDR4_LIMIT ( S_DDR4_START + S_DDR4_SIZE ) 43 | 44 | #endif /* __REGION_DEFS_H__ */ 45 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018-2022 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __REGION_LIMITS_H__ 18 | #define __REGION_LIMITS_H__ 19 | 20 | /* ************************************************************** 21 | * WARNING: this file is parsed both by the C/C++ compiler 22 | * and the linker. As a result the syntax must be valid not only 23 | * for C/C++ but for the linker scripts too. 24 | * Beware of the following limitations: 25 | * - LD (GCC linker) requires white space around operators. 26 | * - UL postfix for macros is not suported by the linker script 27 | ****************************************************************/ 28 | 29 | /* Secure Code */ 30 | #define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ 31 | #define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ 32 | 33 | /* Secure Data */ 34 | #define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ 35 | #define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ 36 | 37 | /* Secure DDR4 */ 38 | #define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ 39 | #define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ 40 | 41 | /* Heap and Stack sizes for secure and nonsecure applications */ 42 | #define HEAP_SIZE (0x00000400) /* 1 KiB */ 43 | #define STACK_SIZE (0x00000400) /* 1 KiB */ 44 | 45 | #endif /* __REGION_LIMITS_H__ */ 46 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/region_limits.h.base@1.0.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2018-2022 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | #ifndef __REGION_LIMITS_H__ 18 | #define __REGION_LIMITS_H__ 19 | 20 | /* ************************************************************** 21 | * WARNING: this file is parsed both by the C/C++ compiler 22 | * and the linker. As a result the syntax must be valid not only 23 | * for C/C++ but for the linker scripts too. 24 | * Beware of the following limitations: 25 | * - LD (GCC linker) requires white space around operators. 26 | * - UL postfix for macros is not suported by the linker script 27 | ****************************************************************/ 28 | 29 | /* Secure Code */ 30 | #define S_ROM_ALIAS (0x10000000) /* ITCM_BASE_S */ 31 | #define TOTAL_S_ROM_SIZE (0x00080000) /* 512 kB */ 32 | 33 | /* Secure Data */ 34 | #define S_RAM_ALIAS (0x30000000) /* DTCM_BASE_S */ 35 | #define TOTAL_S_RAM_SIZE (0x00080000) /* 512 kB */ 36 | 37 | /* Secure DDR4 */ 38 | #define S_DDR4_ALIAS (0x70000000) /* DDR4_BLK1_BASE_S */ 39 | #define TOTAL_S_DDR4_SIZE (0x10000000) /* 256 MB */ 40 | 41 | /* Heap and Stack sizes for secure and nonsecure applications */ 42 | #define HEAP_SIZE (0x00000400) /* 1 KiB */ 43 | #define STACK_SIZE (0x00000400) /* 1 KiB */ 44 | 45 | #endif /* __REGION_LIMITS_H__ */ 46 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | /* 20 | * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c 21 | * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b 22 | */ 23 | 24 | #include "SSE300MPS3.h" 25 | 26 | /*---------------------------------------------------------------------------- 27 | Define clocks 28 | *----------------------------------------------------------------------------*/ 29 | #define XTAL (100000000UL) 30 | #define SYSTEM_CLOCK (XTAL) 31 | #define PERIPHERAL_CLOCK (25000000UL) 32 | 33 | /*---------------------------------------------------------------------------- 34 | Externals 35 | *----------------------------------------------------------------------------*/ 36 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 37 | extern uint32_t __VECTOR_TABLE; 38 | #endif 39 | 40 | /*---------------------------------------------------------------------------- 41 | System Core Clock Variable 42 | *----------------------------------------------------------------------------*/ 43 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 44 | uint32_t PeripheralClock = PERIPHERAL_CLOCK; 45 | 46 | /*---------------------------------------------------------------------------- 47 | System Core Clock update function 48 | *----------------------------------------------------------------------------*/ 49 | void SystemCoreClockUpdate (void) 50 | { 51 | SystemCoreClock = SYSTEM_CLOCK; 52 | PeripheralClock = PERIPHERAL_CLOCK; 53 | } 54 | 55 | /*---------------------------------------------------------------------------- 56 | System initialization function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemInit (void) 59 | { 60 | 61 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 62 | SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); 63 | #endif 64 | 65 | #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ 66 | (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) 67 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 68 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 69 | 70 | /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set 71 | * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU 72 | * into retention state 73 | */ 74 | PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; 75 | #endif 76 | 77 | #ifdef UNALIGNED_SUPPORT_DISABLE 78 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 79 | #endif 80 | 81 | /* Enable Loop and branch info cache */ 82 | SCB->CCR |= SCB_CCR_LOB_Msk; 83 | __DSB(); 84 | __ISB(); 85 | 86 | } 87 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.c.base@1.1.1: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | /* 20 | * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.c 21 | * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b 22 | */ 23 | 24 | #include "SSE300MPS3.h" 25 | 26 | /*---------------------------------------------------------------------------- 27 | Define clocks 28 | *----------------------------------------------------------------------------*/ 29 | #define XTAL (32000000UL) 30 | #define SYSTEM_CLOCK (XTAL) 31 | #define PERIPHERAL_CLOCK (25000000UL) 32 | 33 | /*---------------------------------------------------------------------------- 34 | Externals 35 | *----------------------------------------------------------------------------*/ 36 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 37 | extern uint32_t __VECTOR_TABLE; 38 | #endif 39 | 40 | /*---------------------------------------------------------------------------- 41 | System Core Clock Variable 42 | *----------------------------------------------------------------------------*/ 43 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 44 | uint32_t PeripheralClock = PERIPHERAL_CLOCK; 45 | 46 | /*---------------------------------------------------------------------------- 47 | System Core Clock update function 48 | *----------------------------------------------------------------------------*/ 49 | void SystemCoreClockUpdate (void) 50 | { 51 | SystemCoreClock = SYSTEM_CLOCK; 52 | PeripheralClock = PERIPHERAL_CLOCK; 53 | } 54 | 55 | /*---------------------------------------------------------------------------- 56 | System initialization function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemInit (void) 59 | { 60 | 61 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 62 | SCB->VTOR = (uint32_t)(&__VECTOR_TABLE); 63 | #endif 64 | 65 | #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ 66 | (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE >= 1U)) 67 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 68 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 69 | 70 | /* Set CPDLPSTATE.CLPSTATE to 0, so PDCORE will not enter low-power state. Set 71 | * CPDLPSTATE.ELPSTATE to 0, to stop the processor from trying to switch the EPU 72 | * into retention state 73 | */ 74 | PWRMODCTL->CPDLPSTATE &= 0xFFFFFF00UL; 75 | #endif 76 | 77 | #ifdef UNALIGNED_SUPPORT_DISABLE 78 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 79 | #endif 80 | 81 | /* Enable Loop and branch info cache */ 82 | SCB->CCR |= SCB_CCR_LOB_Msk; 83 | __DSB(); 84 | __ISB(); 85 | 86 | } 87 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009-2020 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | /* 18 | * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h 19 | * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b 20 | */ 21 | 22 | #ifndef __SYSTEM_CORE_INIT_H__ 23 | #define __SYSTEM_CORE_INIT_H__ 24 | 25 | #include 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 32 | extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ 33 | 34 | /** 35 | * \brief Initializes the system 36 | */ 37 | extern void SystemInit(void); 38 | 39 | /** 40 | * \brief Restores system core clock 41 | */ 42 | extern void SystemCoreClockUpdate(void); 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | 48 | #endif /* __SYSTEM_CORE_INIT_H__ */ 49 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/Device/SSE-300-MPS3/system_SSE300MPS3.h.base@1.1.1: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2009-2020 Arm Limited 3 | * 4 | * Licensed under the Apache License, Version 2.0 (the "License"); 5 | * you may not use this file except in compliance with the License. 6 | * You may obtain a copy of the License at 7 | * 8 | * http://www.apache.org/licenses/LICENSE-2.0 9 | * 10 | * Unless required by applicable law or agreed to in writing, software 11 | * distributed under the License is distributed on an "AS IS" BASIS, 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 | * See the License for the specific language governing permissions and 14 | * limitations under the License. 15 | */ 16 | 17 | /* 18 | * This file is derivative of CMSIS V5.6.0 system_ARMv81MML.h 19 | * Git SHA: b5f0603d6a584d1724d952fd8b0737458b90d62b 20 | */ 21 | 22 | #ifndef __SYSTEM_CORE_INIT_H__ 23 | #define __SYSTEM_CORE_INIT_H__ 24 | 25 | #include 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 32 | extern uint32_t PeripheralClock; /*!< Peripheral Clock Frequency */ 33 | 34 | /** 35 | * \brief Initializes the system 36 | */ 37 | extern void SystemInit(void); 38 | 39 | /** 40 | * \brief Restores system core clock 41 | */ 42 | extern void SystemCoreClockUpdate(void); 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | 48 | #endif /* __SYSTEM_CORE_INIT_H__ */ 49 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/_Debug_AVH/RTE_Components.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CSOLUTION generated file: DO NOT EDIT! 3 | * Generated by: csolution version 2.6.0 4 | * 5 | * Project: 'EventStatistic.Debug+AVH' 6 | * Target: 'Debug+AVH' 7 | */ 8 | 9 | #ifndef RTE_COMPONENTS_H 10 | #define RTE_COMPONENTS_H 11 | 12 | 13 | /* 14 | * Define the Device Header File: 15 | */ 16 | #define CMSIS_device_header "SSE300MPS3.h" 17 | 18 | /* ARM::CMSIS-View:Event Recorder&Semihosting@1.6.0 */ 19 | #define RTE_CMSIS_View_EventRecorder 20 | #define RTE_CMSIS_View_EventRecorder_DAP 21 | #define RTE_CMSIS_View_EventRecorder_Semihosting 22 | /* ARM::Device:Native Driver:SysCounter@1.1.0 */ 23 | #define RTE_SYSCOUNTER 1 24 | /* ARM::Device:Native Driver:Timeout@1.0.0 */ 25 | #define RTE_TIMEOUT 1 26 | 27 | 28 | #endif /* RTE_COMPONENTS_H */ 29 | -------------------------------------------------------------------------------- /Examples/EventStatistic/RTE/_Release_AVH/RTE_Components.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CSOLUTION generated file: DO NOT EDIT! 3 | * Generated by: csolution version 2.6.0 4 | * 5 | * Project: 'EventStatistic.Release+AVH' 6 | * Target: 'Release+AVH' 7 | */ 8 | 9 | #ifndef RTE_COMPONENTS_H 10 | #define RTE_COMPONENTS_H 11 | 12 | 13 | /* 14 | * Define the Device Header File: 15 | */ 16 | #define CMSIS_device_header "SSE300MPS3.h" 17 | 18 | /* ARM::CMSIS-View:Event Recorder&Semihosting@1.6.0 */ 19 | #define RTE_CMSIS_View_EventRecorder 20 | #define RTE_CMSIS_View_EventRecorder_DAP 21 | #define RTE_CMSIS_View_EventRecorder_Semihosting 22 | /* ARM::Device:Native Driver:SysCounter@1.1.0 */ 23 | #define RTE_SYSCOUNTER 1 24 | /* ARM::Device:Native Driver:Timeout@1.0.0 */ 25 | #define RTE_TIMEOUT 1 26 | 27 | 28 | #endif /* RTE_COMPONENTS_H */ 29 | -------------------------------------------------------------------------------- /Examples/EventStatistic/fvp_config.txt: -------------------------------------------------------------------------------- 1 | # Parameters: 2 | # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] 3 | #------------------------------------------------------------------------------ 4 | core_clk.mul=100000000 # (int , init-time) default = '0x17d7840' : Clock Rate Multiplier. This parameter is not exposed via CADI and can only be set in LISA 5 | cpu0.semihosting-enable=1 # (bool , init-time) default = '1' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. 6 | mps3_board.telnetterminal0.start_telnet=1 # (bool , init-time) default = '1' : Start telnet if nothing connected 7 | mps3_board.visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation 8 | #------------------------------------------------------------------------------ -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Debug.ini: -------------------------------------------------------------------------------- 1 | /*---------------------------------------------------------------------------- 2 | * Name: Debug.ini 3 | * Purpose: Debugger initialization script 4 | *----------------------------------------------------------------------------*/ 5 | 6 | FUNC void OnResetExec (void) { /* This function executes upon software RESET */ 7 | /* Allow debugger access to non-secure Internal Flash (for reading osRtxConfig and EventRecorderInfo structures) */ 8 | _WDWORD(0xE000EDD8, 0x00000000); /* SAU RNR: Region = 0 */ 9 | _WDWORD(0xE000EDDC, 0x08100000); /* SAU RBAR: Base address = 0x08100000 (start of non-secure Internal Flash as configured by SECWM2_PSTRT and SECWM2_PEND Flash Option Bytes) */ 10 | _WDWORD(0xE000EDE0, 0x081FFFE1); /* SAU RLAR: Limit address = 0x081FFFFF (end of non-secure Internal Flash as configured by SECWM2_PSTRT and SECWM2_PEND Flash Option Bytes), NSC = 0, ENABLE = 1 */ 11 | _WDWORD(0xE000EDD0, 0x00000001); /* SAU CTRL: enable SAU */ 12 | 13 | /* Clear first part of non-secure SRAM3 to clear any RTOS states */ 14 | MEMSET(0x20040000, 0x10000, 0); 15 | } 16 | 17 | LOAD "..\\Secure\\Objects\\Fault_S.axf" incremental 18 | LOAD "..\\NonSecure\\Objects\\Fault_NS.axf" incremental 19 | 20 | RESET /* Reset the CPU */ 21 | 22 | OnResetExec(); /* Call this function on initial hardware reset */ 23 | 24 | /* Go To start of the main function in the Non-Secure application */ 25 | G, \\Fault_NS\../STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/NonSecure/Src/main.c\main 26 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Fault.cbuild-set.yml: -------------------------------------------------------------------------------- 1 | cbuild-set: 2 | generated-by: vscode-cmsis-csolution version 1.44.0 3 | contexts: 4 | - context: Fault_S.Debug+B-U585I-IOT02A 5 | - context: Fault_NS.Debug+B-U585I-IOT02A 6 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Fault.csolution.yml: -------------------------------------------------------------------------------- 1 | solution: 2 | description: Fault example for B-U585I-IOT02A board (Cortex-M33) 3 | created-for: CMSIS-Toolbox@2.6.0 4 | cdefault: 5 | 6 | select-compiler: 7 | # list of tested compilers that can be selected 8 | - compiler: AC6 9 | 10 | packs: 11 | - pack: Keil::STM32U5xx_DFP@^3.0.0 12 | - pack: Keil::B-U585I-IOT02A_BSP@^2.0.0 13 | 14 | target-types: 15 | - type: B-U585I-IOT02A 16 | board: STMicroelectronics::B-U585I-IOT02A 17 | device: STMicroelectronics::STM32U585AIIx 18 | 19 | build-types: 20 | - type: Debug 21 | debug: on 22 | optimize: debug 23 | 24 | projects: 25 | - project: Secure/Fault_S.cproject.yml 26 | - project: NonSecure/Fault_NS.cproject.yml 27 | compiler: AC6 28 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Fault.uvmpw: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
    ### uVision Project, (C) Keil Software
    7 | 8 | WorkSpace 9 | 10 | 11 | .\Secure\Fault_S.uvprojx 12 | 1 13 | 1 14 | 15 | 16 | 17 | .\NonSecure\Fault_NS.uvprojx 18 | 1 19 | 20 | 21 |     22 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Flash.ini: -------------------------------------------------------------------------------- 1 | /*---------------------------------------------------------------------------- 2 | * Name: Flash.ini 3 | * Purpose: Debugger flashing script 4 | *----------------------------------------------------------------------------*/ 5 | 6 | LOAD "..\\Secure\\Objects\\Fault_S.axf" incremental 7 | LOAD "..\\NonSecure\\Objects\\Fault_NS.axf" incremental 8 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2024 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | #include "ARM_FaultTrigger.h" 20 | 21 | #include "RTE_Components.h" 22 | #include CMSIS_device_header 23 | #include "../STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Secure_nsclib/secure_nsc.h" 24 | 25 | // ARM_FaultTrigger function --------------------------------------------------- 26 | 27 | /** 28 | Trigger a fault. 29 | \param[in] fault_id Fault ID of the fault to be triggered 30 | */ 31 | void ARM_FaultTrigger (uint32_t fault_id) { 32 | volatile uint32_t val; 33 | void (*ptr_func) (void); 34 | 35 | switch (fault_id) { 36 | case ARM_FAULT_ID_MEM_DATA: // Trigger Non-Secure MemManage fault - data access 37 | val = *((uint32_t *)0x20040000); // Read from address not allowed by the MPU (non-privileged access not allowed) 38 | break; 39 | 40 | case ARM_FAULT_ID_BUS_DATA: // Trigger Non-Secure BusFault - data access 41 | val = *((uint32_t *)0x200C0000); // Read from invalid RAM address 42 | break; 43 | 44 | case ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION: // Trigger Non-Secure UsageFault - undefined instruction 45 | __ASM volatile ( 46 | ".syntax unified\n" 47 | ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 48 | ); 49 | break; 50 | 51 | case ARM_FAULT_ID_USG_DIV_0: // Trigger Non-Secure UsageFault - divide by 0 52 | val = 0U; 53 | val = 123/val; 54 | break; 55 | 56 | case ARM_FAULT_ID_SEC_DATA: // Trigger Secure BusFault - data access 57 | val = *((uint32_t *)0x30000000); // Read from Secure RAM address 58 | break; 59 | 60 | case ARM_FAULT_ID_SEC_INSTRUCTION: // Trigger Secure BusFault - instruction execution 61 | ptr_func = (void (*) (void))(0xC000000); 62 | ptr_func(); // Call function from Secure Flash address 63 | break; 64 | 65 | case ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION: // Trigger Secure - UsageFault - undefined instruction 66 | Secure_TriggerFault(fault_id); // Call Secure function that will trigger a fault 67 | break; 68 | 69 | default: 70 | break; 71 | } 72 | } 73 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/ARM_FaultTrigger.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | #include 20 | 21 | // Fault IDs for fault triggering 22 | #define ARM_FAULT_ID_MEM_DATA (1U) 23 | #define ARM_FAULT_ID_BUS_DATA (2U) 24 | #define ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION (3U) 25 | #define ARM_FAULT_ID_USG_DIV_0 (4U) 26 | #define ARM_FAULT_ID_SEC_DATA (5U) 27 | #define ARM_FAULT_ID_SEC_INSTRUCTION (6U) 28 | #define ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION (7U) 29 | 30 | // ARM_FaultTrigger function --------------------------------------------------- 31 | 32 | /// Trigger a fault. 33 | /// \param[in] fault_id Fault Id of the fault to be triggered 34 | extern void ARM_FaultTrigger (uint32_t fault_id); 35 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/Fault.c: -------------------------------------------------------------------------------- 1 | /*----------------------------------------------------------------------------- 2 | * Name: Fault.c 3 | * Purpose: Fault example program 4 | *----------------------------------------------------------------------------*/ 5 | 6 | #include 7 | 8 | #include "main.h" 9 | 10 | #include "RTE_Components.h" 11 | #include CMSIS_device_header 12 | 13 | #include "cmsis_os2.h" 14 | #include "cmsis_vio.h" 15 | 16 | #include "ARM_Fault.h" 17 | #include "ARM_FaultTrigger.h" 18 | 19 | #include "EventRecorder.h" 20 | 21 | extern osThreadId_t tid_AppThread; 22 | extern osThreadId_t tid_FaultTriggerThread; 23 | 24 | /* Global Thread IDs (for debug) */ 25 | osThreadId_t tid_AppThread; 26 | osThreadId_t tid_FaultTriggerThread; 27 | 28 | /*----------------------------------------------------------------------------- 29 | * Application thread 30 | *----------------------------------------------------------------------------*/ 31 | static __NO_RETURN void AppThread (void *argument) { 32 | 33 | (void)argument; 34 | 35 | for (;;) { 36 | osDelay(500U); 37 | vioSetSignal(vioLED1, vioLEDon); // Switch LED1 on 38 | osDelay(500U); 39 | vioSetSignal(vioLED1, vioLEDoff); // Switch LED1 off 40 | } 41 | } 42 | 43 | /*----------------------------------------------------------------------------- 44 | * Fault trigger thread 45 | *----------------------------------------------------------------------------*/ 46 | static __NO_RETURN void FaultTriggerThread (void *argument) { 47 | char ch; 48 | 49 | (void)argument; 50 | 51 | // Display user interface message 52 | printf("\r\n--- Fault example ---\r\n\r\n"); 53 | printf("To trigger a fault please input a corresponding number:\r\n"); 54 | printf(" - 1: Non-Secure fault, Non-Secure data access Memory Management fault\r\n"); 55 | printf(" - 2: Non-Secure fault, Non-Secure data access Bus fault\r\n"); 56 | printf(" - 3: Non-Secure fault, Non-Secure undefined instruction Usage fault\r\n"); 57 | printf(" - 4: Non-Secure fault, Non-Secure divide by 0 Usage fault\r\n"); 58 | printf(" - 5: Secure fault, Non-Secure data access from Secure RAM memory\r\n"); 59 | printf(" - 6: Secure fault, Non-Secure instruction execution from Secure Flash memory\r\n"); 60 | printf(" - 7: Secure fault, Secure undefined instruction Usage fault\r\n\r\n"); 61 | printf("Input>"); 62 | 63 | for (;;) { 64 | ch = (char)getchar(); // Read character from console (blocking) 65 | ARM_FaultTrigger((uint32_t)(ch - '0')); // Trigger a fault 66 | } 67 | } 68 | 69 | /*----------------------------------------------------------------------------- 70 | * Application main thread 71 | *----------------------------------------------------------------------------*/ 72 | __NO_RETURN void app_main_thread (void *argument) { 73 | 74 | tid_AppThread = osThreadNew(AppThread, NULL, NULL); 75 | tid_FaultTriggerThread = osThreadNew(FaultTriggerThread, NULL, NULL); 76 | 77 | for (;;) { // Loop forever 78 | } 79 | } 80 | 81 | /*----------------------------------------------------------------------------- 82 | * Application initialization 83 | *----------------------------------------------------------------------------*/ 84 | int app_main (void) { 85 | osKernelInitialize(); /* Initialize CMSIS-RTOS2 */ 86 | osThreadNew(app_main_thread, NULL, NULL); 87 | osKernelStart(); /* Start thread execution */ 88 | return 0; 89 | } 90 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/Fault_NS.cproject.yml: -------------------------------------------------------------------------------- 1 | project: 2 | description: Fault example for B-U585I-IOT02A board (Cortex-M33) - non-secure application 3 | 4 | processor: 5 | trustzone: non-secure 6 | 7 | packs: 8 | - pack: ARM::CMSIS-View@^1.2.0-0 9 | - pack: ARM::CMSIS@^6.1.0 10 | - pack: ARM::CMSIS-Compiler@^2.1.0 11 | - pack: ARM::CMSIS-RTX@^5.9.0 12 | - pack: ARM::CMSIS-Driver_STM32@^1.0.0 13 | 14 | groups: 15 | - group: Documentation 16 | files: 17 | - file: ../README.md 18 | 19 | - group: Source Files 20 | files: 21 | - file: Fault.c 22 | - file: ARM_FaultTrigger.c 23 | - file: ARM_FaultPrint.c 24 | - file: retarget_stdio.c 25 | define: 26 | - RETARGET_STDIO_UART: 1 27 | 28 | components: 29 | - component: CMSIS:CORE 30 | 31 | - component: CMSIS:OS Tick:SysTick 32 | - component: CMSIS:RTOS2:Keil RTX5&Source 33 | 34 | - component: CMSIS-Compiler:CORE 35 | - component: CMSIS-Compiler:STDIN:Custom 36 | - component: CMSIS-Compiler:STDOUT:Custom 37 | - component: CMSIS-Compiler:STDERR:Custom 38 | 39 | - component: CMSIS-View:Event Recorder&DAP 40 | - component: CMSIS-View:Fault:Record 41 | - component: CMSIS-View:Fault:Storage 42 | 43 | - component: Device:CubeMX 44 | - component: CMSIS Driver:GPIO 45 | - component: CMSIS Driver:USART 46 | - component: CMSIS Driver:VIO:Board 47 | 48 | linker: 49 | - script: stm32u585xx_flash_ns.sct 50 | for-compiler: AC6 51 | 52 | - script: STM32U585AIIXQ_FLASH.ld 53 | for-compiler: GCC 54 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 2 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 0 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013-2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * ----------------------------------------------------------------------------- 19 | * 20 | * $Revision: V5.2.0 21 | * 22 | * Project: CMSIS-RTOS RTX 23 | * Title: RTX Configuration 24 | * 25 | * ----------------------------------------------------------------------------- 26 | */ 27 | 28 | #include "cmsis_compiler.h" 29 | #include "rtx_os.h" 30 | 31 | // OS Idle Thread 32 | __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { 33 | (void)argument; 34 | 35 | for (;;) {} 36 | } 37 | 38 | // OS Error Callback function 39 | __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { 40 | (void)object_id; 41 | 42 | switch (code) { 43 | case osRtxErrorStackOverflow: 44 | // Stack overflow detected for thread (thread_id=object_id) 45 | break; 46 | case osRtxErrorISRQueueOverflow: 47 | // ISR Queue overflow detected when inserting object (object_id) 48 | break; 49 | case osRtxErrorTimerQueueOverflow: 50 | // User Timer Callback Queue overflow detected for timer (timer_id=object_id) 51 | break; 52 | case osRtxErrorClibSpace: 53 | // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM 54 | break; 55 | case osRtxErrorClibMutex: 56 | // Standard C/C++ library mutex initialization failed 57 | break; 58 | case osRtxErrorSVC: 59 | // Invalid SVC function called (function=object_id) 60 | break; 61 | default: 62 | // Reserved 63 | break; 64 | } 65 | for (;;) {} 66 | //return 0U; 67 | } 68 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/CMSIS/RTX_Config.c.base@5.2.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013-2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * ----------------------------------------------------------------------------- 19 | * 20 | * $Revision: V5.2.0 21 | * 22 | * Project: CMSIS-RTOS RTX 23 | * Title: RTX Configuration 24 | * 25 | * ----------------------------------------------------------------------------- 26 | */ 27 | 28 | #include "cmsis_compiler.h" 29 | #include "rtx_os.h" 30 | 31 | // OS Idle Thread 32 | __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { 33 | (void)argument; 34 | 35 | for (;;) {} 36 | } 37 | 38 | // OS Error Callback function 39 | __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { 40 | (void)object_id; 41 | 42 | switch (code) { 43 | case osRtxErrorStackOverflow: 44 | // Stack overflow detected for thread (thread_id=object_id) 45 | break; 46 | case osRtxErrorISRQueueOverflow: 47 | // ISR Queue overflow detected when inserting object (object_id) 48 | break; 49 | case osRtxErrorTimerQueueOverflow: 50 | // User Timer Callback Queue overflow detected for timer (timer_id=object_id) 51 | break; 52 | case osRtxErrorClibSpace: 53 | // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM 54 | break; 55 | case osRtxErrorClibMutex: 56 | // Standard C/C++ library mutex initialization failed 57 | break; 58 | case osRtxErrorSVC: 59 | // Invalid SVC function called (function=object_id) 60 | break; 61 | default: 62 | // Reserved 63 | break; 64 | } 65 | for (;;) {} 66 | //return 0U; 67 | } 68 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/RTE/_Debug_B-U585I-IOT02A/RTE_Components.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CSOLUTION generated file: DO NOT EDIT! 3 | * Generated by: csolution version 2.7.0 4 | * 5 | * Project: 'Fault_NS.Debug+B-U585I-IOT02A' 6 | * Target: 'Debug+B-U585I-IOT02A' 7 | */ 8 | 9 | #ifndef RTE_COMPONENTS_H 10 | #define RTE_COMPONENTS_H 11 | 12 | /* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ 13 | #define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ 14 | #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ 15 | /* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ 16 | #define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ 17 | #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ 18 | /* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ 19 | #define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ 20 | #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ 21 | /* ARM::CMSIS-View:Event Recorder&DAP@1.6.0 */ 22 | #define RTE_CMSIS_View_EventRecorder 23 | #define RTE_CMSIS_View_EventRecorder_DAP 24 | /* ARM::CMSIS-View:Fault:Record@1.1.0 */ 25 | #define RTE_CMSIS_View_Fault_Record 26 | /* ARM::CMSIS-View:Fault:Storage@1.1.0 */ 27 | #define RTE_CMSIS_View_Fault_Storage 28 | /* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ 29 | #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ 30 | #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ 31 | #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ 32 | #define RTE_CMSIS_RTOS2_RTX5_ARMV8M_NS /* CMSIS-RTOS2 Keil RTX5 Armv8-M Non-secure domain */ 33 | /* Keil::CMSIS Driver:GPIO@1.0.0 */ 34 | #define RTE_Drivers_GPIO0 /* Driver GPIO0 */ 35 | /* Keil::CMSIS Driver:USART@3.0.0 */ 36 | #define RTE_CMSIS_Driver_USART1 /* Driver USART1 */ 37 | #define RTE_CMSIS_Driver_USART2 /* Driver USART2 */ 38 | #define RTE_CMSIS_Driver_USART3 /* Driver USART3 */ 39 | #define RTE_CMSIS_Driver_USART4 /* Driver USART4 */ 40 | #define RTE_CMSIS_Driver_USART5 /* Driver USART5 */ 41 | #define RTE_CMSIS_Driver_USART6 /* Driver USART6 */ 42 | #define RTE_CMSIS_Driver_USART7 /* Driver USART7 */ 43 | #define RTE_CMSIS_Driver_USART8 /* Driver USART8 */ 44 | #define RTE_CMSIS_Driver_USART9 /* Driver USART9 */ 45 | #define RTE_CMSIS_Driver_USART9 /* Driver USART9 */ 46 | #define RTE_CMSIS_Driver_USART10 /* Driver USART10 */ 47 | #define RTE_CMSIS_Driver_USART11 /* Driver USART11 */ 48 | #define RTE_CMSIS_Driver_USART12 /* Driver USART12 */ 49 | #define RTE_CMSIS_Driver_USART13 /* Driver USART13 */ 50 | #define RTE_CMSIS_Driver_USART14 /* Driver USART14 */ 51 | #define RTE_CMSIS_Driver_USART15 /* Driver USART15 */ 52 | #define RTE_CMSIS_Driver_USART21 /* Driver USART21 (LPUART1) */ 53 | #define RTE_CMSIS_Driver_USART22 /* Driver USART22 (LPUART2) */ 54 | #define RTE_CMSIS_Driver_USART23 /* Driver USART23 (LPUART3) */ 55 | /* Keil::CMSIS Driver:VIO:Board@2.0.2 */ 56 | #define RTE_VIO_BOARD 57 | #define RTE_VIO_B_U585I_IOT02A 58 | /* Keil::Device:CubeMX@1.0.0 */ 59 | #define RTE_DEVICE_CUBE_MX 60 | #define CMSIS_device_header "stm32u5xx.h" 61 | 62 | 63 | #endif /* RTE_COMPONENTS_H */ 64 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/NonSecure/stm32u585xx_flash_ns.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc 2 | /* command above MUST be in first line (no comment above!) */ 3 | 4 | /****************************************************************************** 5 | * @file stm32u585xx_flash_ns.sct 6 | * @brief ARM Linker Script for STM32U575xx Device 7 | * @version V2.0.0 8 | * @date 16. March 2023 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2023 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | /* 29 | // <<< Use Configuration Wizard in Context Menu >>> 30 | */ 31 | 32 | /* 33 | // Flash Configuration 34 | // specify the base address and the size of the used Flash 35 | // Flash Base Address <0x0-0xFFFFFFFF:8> 36 | // Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 37 | // 38 | */ 39 | #define __ROM_BASE 0x08100000 40 | #define __ROM_SIZE 0x00100000 41 | 42 | /* 43 | // RAM Configuration 44 | // specify the base address and the complete size of the used RAM 45 | // RAM Base Address <0x0-0xFFFFFFFF:8> 46 | // RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 47 | // 48 | */ 49 | #define __RAM_BASE 0x20040000 50 | #define __RAM_SIZE 0x00080000 51 | 52 | /* 53 | // NOINIT Data Configuration 54 | // specify the size of the section which holds the uninitialized data 55 | // NOINIT Size (in Bytes) <0x0-0xFFFFFFFF:32> 56 | // 57 | */ 58 | #define __NOINIT_SIZE 0x00000500 59 | 60 | /* 61 | // <<< end of configuration section >>> 62 | */ 63 | 64 | #define __LR_BASE ( __ROM_BASE ) 65 | #define __LR_SIZE ( __ROM_SIZE ) 66 | 67 | #define __RW_BASE ( __RAM_BASE ) 68 | #define __RW_SIZE ( __RAM_SIZE - __NOINIT_SIZE - 0x200 ) 69 | #define __RW_NOINIT_BASE ( __RAM_BASE + __RW_SIZE ) /* starts after RW_RAM section */ 70 | 71 | 72 | LR_APP __LR_BASE __LR_SIZE { /* load region for application */ 73 | ER_APP __LR_BASE __LR_SIZE { /* execution region for application */ 74 | *.o (RESET, +First) 75 | *(InRoot$$Sections) 76 | .ANY (+RO) 77 | .ANY (+XO) 78 | } 79 | 80 | RW_RAM_PRIV __RW_BASE EMPTY 0x100 { /* RAM allowing privileged access only (for showing MemManage fault) */ 81 | } 82 | 83 | RW_RAM (__RW_BASE + 0x100) __RW_SIZE { /* RW, ZI data */ 84 | .ANY (+RW +ZI) 85 | } 86 | 87 | RW_NOINIT_FAULT 0x200B0000 UNINIT 0x100 { /* Uninitialized memory for Fault information (ARM_FaultInfo) */ 88 | *(.bss.noinit.fault) 89 | } 90 | 91 | #if __NOINIT_SIZE > 0 92 | RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { /* no init data */ 93 | *(.bss.noinit) 94 | } 95 | #endif 96 | 97 | } 98 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/Fault_NS.cgen.yml: -------------------------------------------------------------------------------- 1 | generator-import: 2 | for-device: STM32U585AIIx 3 | for-board: B-U585I-IOT02A 4 | define: 5 | - USE_HAL_DRIVER 6 | - STM32U585xx 7 | add-path: 8 | - ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc 9 | - ./STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include 10 | - ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy 11 | - ./STM32CubeMX/NonSecure/Inc 12 | - ./STM32CubeMX/Secure_nsclib 13 | - ./MX_Device/NonSecure 14 | groups: 15 | - group: CubeMX 16 | files: 17 | - file: ./STM32CubeMX/NonSecure/Src/main.c 18 | - file: ./STM32CubeMX/NonSecure/Src/stm32u5xx_it.c 19 | - file: ./STM32CubeMX/NonSecure/Src/stm32u5xx_hal_msp.c 20 | - file: ./STM32CubeMX/NonSecure/Src/stm32u5xx_hal_timebase_tim.c 21 | - file: ./STM32CubeMX/MDK-ARM/startup_stm32u585xx.s 22 | - file: ./STM32CubeMX/NonSecure/Src/system_stm32u5xx_ns.c 23 | - group: STM32 HAL Driver 24 | files: 25 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c 26 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c 27 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c 28 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c 29 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c 30 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c 31 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c 32 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c 33 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c 34 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c 35 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c 36 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c 37 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c 38 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c 39 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c 40 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c 41 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c 42 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c 43 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c 44 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c 45 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c 46 | - file: ./STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c 47 | - group: CMSE Library 48 | files: 49 | - file: $cmse-lib(Fault_S)$ 50 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/MX_Device/NonSecure/MX_Device.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * File Name : MX_Device.h 3 | * Date : 15/11/2024 10:26:27 4 | * Description : STM32Cube MX parameter definitions 5 | * Note : This file is generated with a generator out of the 6 | * STM32CubeMX project and its generated files (DO NOT EDIT!) 7 | ******************************************************************************/ 8 | 9 | #ifndef MX_DEVICE_H__ 10 | #define MX_DEVICE_H__ 11 | 12 | /* MX_Device.h version */ 13 | #define MX_DEVICE_VERSION 0x01000000 14 | 15 | 16 | /*------------------------------ USART1 -----------------------------*/ 17 | #define MX_USART1 1 18 | 19 | /* Virtual mode */ 20 | #define MX_USART1_VM VM_ASYNC 21 | #define MX_USART1_VM_ASYNC 1 22 | 23 | /* Pins */ 24 | 25 | /* USART1_RX */ 26 | #define MX_USART1_RX_Pin PA10 27 | #define MX_USART1_RX_GPIO_Pin GPIO_PIN_10 28 | #define MX_USART1_RX_GPIOx GPIOA 29 | #define MX_USART1_RX_GPIO_Mode GPIO_MODE_AF_PP 30 | #define MX_USART1_RX_GPIO_PuPd GPIO_NOPULL 31 | #define MX_USART1_RX_GPIO_Speed GPIO_SPEED_FREQ_LOW 32 | #define MX_USART1_RX_GPIO_AF GPIO_AF7_USART1 33 | 34 | /* USART1_TX */ 35 | #define MX_USART1_TX_Pin PA9 36 | #define MX_USART1_TX_GPIO_Pin GPIO_PIN_9 37 | #define MX_USART1_TX_GPIOx GPIOA 38 | #define MX_USART1_TX_GPIO_Mode GPIO_MODE_AF_PP 39 | #define MX_USART1_TX_GPIO_PuPd GPIO_NOPULL 40 | #define MX_USART1_TX_GPIO_Speed GPIO_SPEED_FREQ_LOW 41 | #define MX_USART1_TX_GPIO_AF GPIO_AF7_USART1 42 | 43 | #endif /* MX_DEVICE_H__ */ 44 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file partition_stm32u5xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32U5xx Device Header File for Initial Setup for 6 | * Secure / Non-Secure Zones based on CMSIS CORE V5.4.0 7 | * 8 | * The file is included in system_stm32u5xx_s.c in secure application. 9 | * It includes the configuration section that allows to select the 10 | * STM32U5xx device partitioning file for system core secure attributes 11 | * and interrupt secure and non-secure assignment. 12 | * 13 | ****************************************************************************** 14 | * @attention 15 | * 16 | * Copyright (c) 2021 STMicroelectronics. 17 | * All rights reserved. 18 | * 19 | * This software is licensed under terms that can be found in the LICENSE file 20 | * in the root directory of this software component. 21 | * If no LICENSE file comes with this software, it is provided AS-IS. 22 | * 23 | ****************************************************************************** 24 | */ 25 | 26 | /** @addtogroup CMSIS 27 | * @{ 28 | */ 29 | 30 | /** @addtogroup stm32u5xx 31 | * @{ 32 | */ 33 | 34 | #ifndef PARTITION_STM32U5XX_H 35 | #define PARTITION_STM32U5XX_H 36 | 37 | #ifdef __cplusplus 38 | extern "C" { 39 | #endif /* __cplusplus */ 40 | 41 | /** @addtogroup Secure_configuration_section 42 | * @{ 43 | */ 44 | 45 | #if defined(STM32U575xx) 46 | #include "partition_stm32u575xx.h" 47 | #elif defined(STM32U585xx) 48 | #include "partition_stm32u585xx.h" 49 | #elif defined(STM32U595xx) 50 | #include "partition_stm32u595xx.h" 51 | #elif defined(STM32U5A5xx) 52 | #include "partition_stm32u5a5xx.h" 53 | #elif defined(STM32U599xx) 54 | #include "partition_stm32u599xx.h" 55 | #elif defined(STM32U5A9xx) 56 | #include "partition_stm32u5a9xx.h" 57 | #elif defined(STM32U5F7xx) 58 | #include "partition_stm32u5f7xx.h" 59 | #elif defined(STM32U5G7xx) 60 | #include "partition_stm32u5g7xx.h" 61 | #elif defined(STM32U5F9xx) 62 | #include "partition_stm32u5f9xx.h" 63 | #elif defined(STM32U5G9xx) 64 | #include "partition_stm32u5g9xx.h" 65 | #elif defined(STM32U535xx) 66 | #include "partition_stm32u535xx.h" 67 | #elif defined(STM32U545xx) 68 | #include "partition_stm32u545xx.h" 69 | #else 70 | #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" 71 | #endif 72 | 73 | #ifdef __cplusplus 74 | } 75 | #endif /* __cplusplus */ 76 | 77 | #endif /* PARTITION_STM32U5XX_H */ 78 | /** 79 | * @} 80 | */ 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | 87 | 88 | 89 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32u5xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /** @addtogroup CMSIS 20 | * @{ 21 | */ 22 | 23 | /** @addtogroup stm32u5xx_system 24 | * @{ 25 | */ 26 | 27 | #ifndef SYSTEM_STM32U5XX_H 28 | #define SYSTEM_STM32U5XX_H 29 | 30 | #ifdef __cplusplus 31 | extern "C" { 32 | #endif 33 | 34 | /** @addtogroup STM32U5xx_System_Includes 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @addtogroup STM32U5xx_System_Exported_Variables 43 | * @{ 44 | */ 45 | /* The SystemCoreClock variable is updated in three ways: 46 | 1) by calling CMSIS function SystemCoreClockUpdate() 47 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 48 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 49 | Note: If you use this function to configure the system clock; then there 50 | is no need to call the 2 first functions listed above, since SystemCoreClock 51 | variable is updated automatically. 52 | */ 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 56 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 57 | extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | 64 | /** @addtogroup STM32U5xx_System_Exported_Functions 65 | * @{ 66 | */ 67 | 68 | /** 69 | * @brief Setup the microcontroller system. 70 | * 71 | * Initialize the System and update the SystemCoreClock variable. 72 | */ 73 | extern void SystemInit (void); 74 | 75 | 76 | /** 77 | * @brief Update SystemCoreClock variable. 78 | * 79 | * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 80 | */ 81 | extern void SystemCoreClockUpdate (void); 82 | 83 | 84 | /** 85 | * @brief Update SystemCoreClock variable from secure application and return its value 86 | * when security is implemented in the system (Non-secure callable function). 87 | * 88 | * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. 89 | */ 90 | extern uint32_t SECURE_SystemCoreClockUpdate(void); 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | #ifdef __cplusplus 97 | } 98 | #endif 99 | 100 | #endif /* SYSTEM_STM32U5XX_H */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the Apache-2.0 license shall apply. 5 | You may obtain a copy of the Apache-2.0 at: 6 | https://opensource.org/licenses/Apache-2.0 -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32u5xx_hal_pcd_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of PCD HAL Extension module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef STM32U5xx_HAL_PCD_EX_H 21 | #define STM32U5xx_HAL_PCD_EX_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif /* __cplusplus */ 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "stm32u5xx_hal_def.h" 29 | 30 | #if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) 31 | /** @addtogroup STM32U5xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PCDEx 36 | * @{ 37 | */ 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* Exported macros -----------------------------------------------------------*/ 41 | /* Exported functions --------------------------------------------------------*/ 42 | /** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions 43 | * @{ 44 | */ 45 | /** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions 46 | * @{ 47 | */ 48 | 49 | #if defined (USB_OTG_FS) || defined (USB_OTG_HS) 50 | HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); 51 | HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); 52 | #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ 53 | 54 | #if defined (USB_DRD_FS) 55 | HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, 56 | uint16_t ep_kind, uint32_t pmaadress); 57 | #endif /* defined (USB_DRD_FS) */ 58 | 59 | HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); 60 | HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); 61 | 62 | 63 | HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); 64 | HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); 65 | void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); 66 | 67 | void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); 68 | void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** 83 | * @} 84 | */ 85 | #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ 86 | 87 | #ifdef __cplusplus 88 | } 89 | #endif /* __cplusplus */ 90 | 91 | 92 | #endif /* STM32U5xx_HAL_PCD_EX_H */ 93 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt: -------------------------------------------------------------------------------- 1 | This software component is provided to you as part of a software package and 2 | applicable license terms are in the Package_license file. If you received this 3 | software component outside of a package or without applicable license terms, 4 | the terms of the BSD-3-Clause license shall apply. 5 | You may obtain a copy of the BSD-3-Clause at: 6 | https://opensource.org/licenses/BSD-3-Clause 7 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/NonSecure/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2024 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __MAIN_H 23 | #define __MAIN_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32u5xx_hal.h" 31 | 32 | #include "secure_nsc.h" /* For export Non-secure callable APIs */ 33 | 34 | /* Private includes ----------------------------------------------------------*/ 35 | /* USER CODE BEGIN Includes */ 36 | 37 | /* USER CODE END Includes */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* USER CODE BEGIN ET */ 41 | 42 | /* USER CODE END ET */ 43 | 44 | /* Exported constants --------------------------------------------------------*/ 45 | /* USER CODE BEGIN EC */ 46 | 47 | /* USER CODE END EC */ 48 | 49 | /* Exported macro ------------------------------------------------------------*/ 50 | /* USER CODE BEGIN EM */ 51 | 52 | /* USER CODE END EM */ 53 | 54 | /* Exported functions prototypes ---------------------------------------------*/ 55 | void Error_Handler(void); 56 | 57 | /* USER CODE BEGIN EFP */ 58 | extern int stdio_init (void); 59 | extern int app_main (void); 60 | /* USER CODE END EFP */ 61 | 62 | /* Private defines -----------------------------------------------------------*/ 63 | #define PC14_OSC32_IN_Pin GPIO_PIN_14 64 | #define PC14_OSC32_IN_GPIO_Port GPIOC 65 | #define PC15_OSC32_OUT_Pin GPIO_PIN_15 66 | #define PC15_OSC32_OUT_GPIO_Port GPIOC 67 | #define LED_RED_Pin GPIO_PIN_6 68 | #define LED_RED_GPIO_Port GPIOH 69 | #define LED_GREEN_Pin GPIO_PIN_7 70 | #define LED_GREEN_GPIO_Port GPIOH 71 | #define T_VCP_RX_Pin GPIO_PIN_10 72 | #define T_VCP_RX_GPIO_Port GPIOA 73 | #define T_VCP_TX_Pin GPIO_PIN_9 74 | #define T_VCP_TX_GPIO_Port GPIOA 75 | 76 | /* USER CODE BEGIN Private defines */ 77 | 78 | /* USER CODE END Private defines */ 79 | 80 | #ifdef __cplusplus 81 | } 82 | #endif 83 | 84 | #endif /* __MAIN_H */ 85 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/NonSecure/Inc/stm32u5xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32u5xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2024 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32U5xx_IT_H 22 | #define __STM32U5xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void USART1_IRQHandler(void); 50 | void TIM16_IRQHandler(void); 51 | /* USER CODE BEGIN EFP */ 52 | 53 | extern void HardFault_Handler (void); 54 | extern void MemManage_Handler (void); 55 | extern void BusFault_Handler (void); 56 | extern void UsageFault_Handler (void); 57 | 58 | /* USER CODE END EFP */ 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* __STM32U5xx_IT_H */ 65 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32_assert.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32_assert.h 5 | * @author MCD Application Team 6 | * @brief STM32 assert file. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32_ASSERT_H 22 | #define __STM32_ASSERT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Exported types ------------------------------------------------------------*/ 29 | /* Exported constants --------------------------------------------------------*/ 30 | /* Includes ------------------------------------------------------------------*/ 31 | /* Exported macro ------------------------------------------------------------*/ 32 | #ifdef USE_FULL_ASSERT 33 | /** 34 | * @brief The assert_param macro is used for function's parameters check. 35 | * @param expr If expr is false, it calls assert_failed function 36 | * which reports the name of the source file and the source 37 | * line number of the call that failed. 38 | * If expr is true, it returns no value. 39 | * @retval None 40 | */ 41 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 42 | /* Exported functions ------------------------------------------------------- */ 43 | void assert_failed(uint8_t *file, uint32_t line); 44 | #else 45 | #define assert_param(expr) ((void)0U) 46 | #endif /* USE_FULL_ASSERT */ 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __STM32_ASSERT_H */ 53 | 54 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Secure/Inc/stm32u5xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32u5xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | * Copyright (c) 2024 STMicroelectronics. 10 | * All rights reserved. 11 | * 12 | * This software is licensed under terms that can be found in the LICENSE file 13 | * in the root directory of this software component. 14 | * If no LICENSE file comes with this software, it is provided AS-IS. 15 | * 16 | ****************************************************************************** 17 | */ 18 | /* USER CODE END Header */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32U5xx_IT_H 22 | #define __STM32U5xx_IT_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Private includes ----------------------------------------------------------*/ 29 | /* USER CODE BEGIN Includes */ 30 | 31 | /* USER CODE END Includes */ 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN ET */ 35 | 36 | /* USER CODE END ET */ 37 | 38 | /* Exported constants --------------------------------------------------------*/ 39 | /* USER CODE BEGIN EC */ 40 | 41 | /* USER CODE END EC */ 42 | 43 | /* Exported macro ------------------------------------------------------------*/ 44 | /* USER CODE BEGIN EM */ 45 | 46 | /* USER CODE END EM */ 47 | 48 | /* Exported functions prototypes ---------------------------------------------*/ 49 | void TIM17_IRQHandler(void); 50 | /* USER CODE BEGIN EFP */ 51 | 52 | extern void HardFault_Handler (void); 53 | extern void MemManage_Handler (void); 54 | extern void BusFault_Handler (void); 55 | extern void UsageFault_Handler (void); 56 | extern void SecureFault_Handler (void); 57 | extern void DebugMon_Handler (void); 58 | 59 | /* USER CODE END EFP */ 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __STM32U5xx_IT_H */ 66 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Secure/Src/secure_nsc.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file Secure/Src/secure_nsc.c 5 | * @author MCD Application Team 6 | * @brief This file contains the non-secure callable APIs (secure world) 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2024 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* USER CODE BEGIN Non_Secure_CallLib */ 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | #include "secure_nsc.h" 25 | 26 | #include "..\..\..\..\NonSecure\ARM_FaultTrigger.h" 27 | /** @addtogroup STM32U5xx_HAL_Examples 28 | * @{ 29 | */ 30 | 31 | /** @addtogroup Templates 32 | * @{ 33 | */ 34 | 35 | /* Global variables ----------------------------------------------------------*/ 36 | void *pSecureFaultCallback = NULL; /* Pointer to secure fault callback in Non-secure */ 37 | void *pSecureErrorCallback = NULL; /* Pointer to secure error callback in Non-secure */ 38 | 39 | /* Private typedef -----------------------------------------------------------*/ 40 | /* Private define ------------------------------------------------------------*/ 41 | /* Private macro -------------------------------------------------------------*/ 42 | /* Private variables ---------------------------------------------------------*/ 43 | /* Private function prototypes -----------------------------------------------*/ 44 | /* Private functions ---------------------------------------------------------*/ 45 | 46 | /** 47 | * @brief Secure registration of non-secure callback. 48 | * @param CallbackId callback identifier 49 | * @param func pointer to non-secure function 50 | * @retval None 51 | */ 52 | CMSE_NS_ENTRY void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func) 53 | { 54 | if(func != NULL) 55 | { 56 | switch(CallbackId) 57 | { 58 | case SECURE_FAULT_CB_ID: /* SecureFault Interrupt occurred */ 59 | pSecureFaultCallback = func; 60 | break; 61 | case GTZC_ERROR_CB_ID: /* GTZC Interrupt occurred */ 62 | pSecureErrorCallback = func; 63 | break; 64 | default: 65 | /* unknown */ 66 | break; 67 | } 68 | } 69 | } 70 | 71 | /* This function is used to trigger Secure fault */ 72 | CMSE_NS_ENTRY void Secure_TriggerFault (uint32_t fault_id) { 73 | 74 | switch (fault_id) { 75 | case ARM_FAULT_ID_SEC_USG_UNDEFINED_INSTRUCTION: // Trigger Secure - UsageFault - undefined instruction 76 | __ASM volatile ( 77 | ".syntax unified\n" 78 | ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 79 | ); 80 | break; 81 | } 82 | } 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | /** 89 | * @} 90 | */ 91 | /* USER CODE END Non_Secure_CallLib */ 92 | 93 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/STM32CubeMX/Secure_nsclib/secure_nsc.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file Secure_nsclib/secure_nsc.h 5 | * @author MCD Application Team 6 | * @brief Header for secure non-secure callable APIs list 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | * Copyright (c) 2024 STMicroelectronics. 11 | * All rights reserved. 12 | * 13 | * This software is licensed under terms that can be found in the LICENSE file 14 | * in the root directory of this software component. 15 | * If no LICENSE file comes with this software, it is provided AS-IS. 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* USER CODE BEGIN Non_Secure_CallLib_h */ 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef SECURE_NSC_H 24 | #define SECURE_NSC_H 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | #include 28 | 29 | /* Exported types ------------------------------------------------------------*/ 30 | /** 31 | * @brief non-secure callback ID enumeration definition 32 | */ 33 | typedef enum 34 | { 35 | SECURE_FAULT_CB_ID = 0x00U, /*!< System secure fault callback ID */ 36 | GTZC_ERROR_CB_ID = 0x01U /*!< GTZC secure error callback ID */ 37 | } SECURE_CallbackIDTypeDef; 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* Exported macro ------------------------------------------------------------*/ 41 | /* Exported functions ------------------------------------------------------- */ 42 | void SECURE_RegisterCallback(SECURE_CallbackIDTypeDef CallbackId, void *func); 43 | 44 | /* Non-secure callable function */ 45 | extern void Secure_TriggerFault (uint32_t fault_id); 46 | 47 | #endif /* SECURE_NSC_H */ 48 | /* USER CODE END Non_Secure_CallLib_h */ 49 | 50 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/STM32CubeMX/B-U585I-IOT02A/project.script: -------------------------------------------------------------------------------- 1 | loadboard B-U585I-IOT02A allmodes 2 | project name STM32CubeMX 3 | project toolchain "MDK-ARM V5" 4 | SetCopyLibrary "copy only" 5 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Secure/Fault_S.cproject.yml: -------------------------------------------------------------------------------- 1 | project: 2 | description: Fault example for B-U585I-IOT02A board (Cortex-M33) - secure application 3 | 4 | processor: 5 | trustzone: secure 6 | 7 | packs: 8 | - pack: ARM::CMSIS-View@^1.2.0-0 9 | - pack: ARM::CMSIS@^6.1.0 10 | - pack: ARM::CMSIS-Compiler@^2.1.0 11 | - pack: ARM::CMSIS-Driver_STM32@^1.0.0 12 | 13 | groups: 14 | - group: Documentation 15 | files: 16 | - file: ../README.md 17 | 18 | components: 19 | - component: CMSIS:CORE 20 | 21 | - component: CMSIS-Compiler:CORE 22 | - component: CMSIS-Compiler:STDIN:Breakpoint 23 | - component: CMSIS-Compiler:STDOUT:Breakpoint 24 | - component: CMSIS-Compiler:STDERR:Breakpoint 25 | 26 | - component: CMSIS-View:Fault:Storage 27 | 28 | - component: Device:CubeMX 29 | 30 | linker: 31 | - script: stm32u585xx_flash_s.sct 32 | for-compiler: AC6 33 | 34 | - script: STM32U585AIIXQ_FLASH.ld 35 | for-compiler: GCC 36 | -------------------------------------------------------------------------------- /Examples/Fault/B-U585I-IOT02A/Secure/RTE/_Debug_B-U585I-IOT02A/RTE_Components.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CSOLUTION generated file: DO NOT EDIT! 3 | * Generated by: csolution version 2.6.0 4 | * 5 | * Project: 'Fault_S.Debug+B-U585I-IOT02A' 6 | * Target: 'Debug+B-U585I-IOT02A' 7 | */ 8 | 9 | #ifndef RTE_COMPONENTS_H 10 | #define RTE_COMPONENTS_H 11 | 12 | /* ARM::CMSIS-Compiler:STDERR:Breakpoint@1.1.0 */ 13 | #define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ 14 | #define RTE_CMSIS_Compiler_STDERR_Breakpoint /* CMSIS-Compiler STDERR: Breakpoint */ 15 | /* ARM::CMSIS-Compiler:STDIN:Breakpoint@1.1.0 */ 16 | #define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ 17 | #define RTE_CMSIS_Compiler_STDIN_Breakpoint /* CMSIS-Compiler STDIN: Breakpoint */ 18 | /* ARM::CMSIS-Compiler:STDOUT:Breakpoint@1.1.0 */ 19 | #define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ 20 | #define RTE_CMSIS_Compiler_STDOUT_Breakpoint /* CMSIS-Compiler STDOUT: Breakpoint */ 21 | /* ARM::CMSIS-View:Fault:Storage@1.1.0 */ 22 | #define RTE_CMSIS_View_Fault_Storage 23 | /* Keil::Device:CubeMX@1.0.0 */ 24 | #define RTE_DEVICE_CUBE_MX 25 | #define CMSIS_device_header "stm32u5xx.h" 26 | 27 | 28 | #endif /* RTE_COMPONENTS_H */ 29 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/ARM_FaultTrigger.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023-2025 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | #include "ARM_FaultTrigger.h" 20 | 21 | #include "RTE_Components.h" 22 | #include CMSIS_device_header 23 | 24 | // ARM_FaultTrigger function --------------------------------------------------- 25 | 26 | /** 27 | Trigger a fault. 28 | \param[in] fault_id Fault ID of the fault to be triggered 29 | */ 30 | void ARM_FaultTrigger (uint32_t fault_id) { 31 | volatile uint32_t val; 32 | void (*ptr_func) (void); 33 | 34 | switch (fault_id) { 35 | case ARM_FAULT_ID_MEM_DATA: // Trigger MemManage fault - data access 36 | val = *((uint32_t *)0x20000000); // Read from address not allowed by the MPU (non-privileged access not allowed) 37 | break; 38 | 39 | case ARM_FAULT_ID_BUS_DATA_PRECISE: // Trigger BusFault - data access (precise) 40 | val = *((uint32_t *)0x3FFFFFFC); // Read from invalid address 41 | break; 42 | 43 | case ARM_FAULT_ID_BUS_DATA_IMPRECISE: // Trigger BusFault - data access (imprecise) 44 | *((uint32_t *)0x3FFFFFFC) = 1U; // Write to invalid address 45 | break; 46 | 47 | case ARM_FAULT_ID_BUS_INSTRUCTION: // Trigger BusFault - instruction execution 48 | ptr_func = (void (*) (void))(0x1FFFFFFC); 49 | ptr_func(); // Call function from invalid address 50 | break; 51 | 52 | case ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION: // Trigger UsageFault - undefined instruction 53 | __ASM volatile ( 54 | ".syntax unified\n" 55 | ".inst.w 0xF1234567\n" // Execute undefined 32-bit instruction encoded as 0xF1234567 56 | ); 57 | break; 58 | 59 | case ARM_FAULT_ID_USG_DIV_0: // Trigger UsageFault - divide by 0 60 | val = 0U; 61 | val = 123/val; 62 | break; 63 | 64 | default: 65 | break; 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/ARM_FaultTrigger.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | #include 20 | 21 | // Fault IDs for fault triggering 22 | #define ARM_FAULT_ID_MEM_DATA (1U) 23 | #define ARM_FAULT_ID_BUS_DATA_PRECISE (2U) 24 | #define ARM_FAULT_ID_BUS_DATA_IMPRECISE (3U) 25 | #define ARM_FAULT_ID_BUS_INSTRUCTION (4U) 26 | #define ARM_FAULT_ID_USG_UNDEFINED_INSTRUCTION (5U) 27 | #define ARM_FAULT_ID_USG_DIV_0 (6U) 28 | 29 | // ARM_FaultTrigger function --------------------------------------------------- 30 | 31 | /// Trigger a fault. 32 | /// \param[in] fault_id Fault Id of the fault to be triggered 33 | extern void ARM_FaultTrigger (uint32_t fault_id); 34 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/Fault.cproject.yml: -------------------------------------------------------------------------------- 1 | project: 2 | description: Fault example (Cortex-M7) 3 | 4 | packs: 5 | - pack: ARM::CMSIS-View@^1.2.0-0 6 | - pack: ARM::CMSIS@^6.1.0 7 | - pack: ARM::CMSIS-Compiler@^2.1.0 8 | - pack: ARM::CMSIS-RTX@^5.9.0 9 | 10 | groups: 11 | - group: Documentation 12 | files: 13 | - file: README.md 14 | 15 | - group: Source Files 16 | files: 17 | - file: Fault.c 18 | - file: ARM_FaultTrigger.c 19 | - file: retarget_stdio.c 20 | 21 | components: 22 | - component: CMSIS:CORE 23 | 24 | - component: CMSIS:OS Tick:SysTick 25 | - component: CMSIS:RTOS2:Keil RTX5&Source 26 | 27 | - component: CMSIS-Compiler:CORE 28 | - component: CMSIS-Compiler:STDIN:Custom 29 | - component: CMSIS-Compiler:STDOUT:Custom 30 | - component: CMSIS-Compiler:STDERR:Custom 31 | 32 | - component: CMSIS-View:Event Recorder&Semihosting 33 | - component: CMSIS-View:Fault:Record 34 | - component: CMSIS-View:Fault:Storage 35 | 36 | - component: Device:Startup&C Startup 37 | - component: CMSIS Driver:USART 38 | 39 | linker: 40 | - script: ./RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct 41 | for-compiler: AC6 42 | 43 | - script: ./RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld 44 | for-compiler: GCC 45 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/Fault.csolution.yml: -------------------------------------------------------------------------------- 1 | solution: 2 | description: Fault example (Cortex-M7) 3 | created-for: CMSIS-Toolbox@2.6.0 4 | cdefault: 5 | 6 | select-compiler: 7 | # list of tested compilers that can be selected 8 | - compiler: AC6 9 | - compiler: GCC 10 | 11 | packs: 12 | - pack: Keil::V2M-MPS2_CMx_BSP@^1.8.0 13 | 14 | target-types: 15 | - type: FVP_MPS2_Cortex-M7 16 | board: ARM::V2M-MPS2:B 17 | device: ARM::CMSDK_CM7_SP_VHT 18 | 19 | build-types: 20 | - type: Debug 21 | debug: on 22 | optimize: debug 23 | 24 | projects: 25 | - project: Fault.cproject.yml 26 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 2 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/CMSIS-View/EventRecorderConf.h.base@1.1.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2016-2021 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: EventRecorderConf.h 19 | * Purpose: Event Recorder software component configuration options 20 | * Rev.: V1.1.0 21 | */ 22 | 23 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 24 | 25 | // Event Recorder 26 | 27 | // Number of Records 28 | // <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 29 | // <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 30 | // <65536=>65536 31 | // Configures size of Event Record Buffer (each record is 16 bytes) 32 | // Must be 2^n (min=8, max=65536) 33 | #define EVENT_RECORD_COUNT 64U 34 | 35 | // Time Stamp Source 36 | // <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer 37 | // <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) 38 | // Selects source for 32-bit time stamp 39 | #define EVENT_TIMESTAMP_SOURCE 0 40 | 41 | // Time Stamp Clock Frequency [Hz] <0-1000000000> 42 | // Defines initial time stamp clock frequency (0 when not used) 43 | #define EVENT_TIMESTAMP_FREQ 0U 44 | 45 | // 46 | 47 | //------------- <<< end of configuration section >>> --------------------------- 48 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013-2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * ----------------------------------------------------------------------------- 19 | * 20 | * $Revision: V5.2.0 21 | * 22 | * Project: CMSIS-RTOS RTX 23 | * Title: RTX Configuration 24 | * 25 | * ----------------------------------------------------------------------------- 26 | */ 27 | 28 | #include "cmsis_compiler.h" 29 | #include "rtx_os.h" 30 | 31 | // OS Idle Thread 32 | __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { 33 | (void)argument; 34 | 35 | for (;;) {} 36 | } 37 | 38 | // OS Error Callback function 39 | __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { 40 | (void)object_id; 41 | 42 | switch (code) { 43 | case osRtxErrorStackOverflow: 44 | // Stack overflow detected for thread (thread_id=object_id) 45 | break; 46 | case osRtxErrorISRQueueOverflow: 47 | // ISR Queue overflow detected when inserting object (object_id) 48 | break; 49 | case osRtxErrorTimerQueueOverflow: 50 | // User Timer Callback Queue overflow detected for timer (timer_id=object_id) 51 | break; 52 | case osRtxErrorClibSpace: 53 | // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM 54 | break; 55 | case osRtxErrorClibMutex: 56 | // Standard C/C++ library mutex initialization failed 57 | break; 58 | case osRtxErrorSVC: 59 | // Invalid SVC function called (function=object_id) 60 | break; 61 | default: 62 | // Reserved 63 | break; 64 | } 65 | for (;;) {} 66 | //return 0U; 67 | } 68 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/CMSIS/RTX_Config.c.base@5.2.0: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2013-2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * ----------------------------------------------------------------------------- 19 | * 20 | * $Revision: V5.2.0 21 | * 22 | * Project: CMSIS-RTOS RTX 23 | * Title: RTX Configuration 24 | * 25 | * ----------------------------------------------------------------------------- 26 | */ 27 | 28 | #include "cmsis_compiler.h" 29 | #include "rtx_os.h" 30 | 31 | // OS Idle Thread 32 | __WEAK __NO_RETURN void osRtxIdleThread (void *argument) { 33 | (void)argument; 34 | 35 | for (;;) {} 36 | } 37 | 38 | // OS Error Callback function 39 | __WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { 40 | (void)object_id; 41 | 42 | switch (code) { 43 | case osRtxErrorStackOverflow: 44 | // Stack overflow detected for thread (thread_id=object_id) 45 | break; 46 | case osRtxErrorISRQueueOverflow: 47 | // ISR Queue overflow detected when inserting object (object_id) 48 | break; 49 | case osRtxErrorTimerQueueOverflow: 50 | // User Timer Callback Queue overflow detected for timer (timer_id=object_id) 51 | break; 52 | case osRtxErrorClibSpace: 53 | // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM 54 | break; 55 | case osRtxErrorClibMutex: 56 | // Standard C/C++ library mutex initialization failed 57 | break; 58 | case osRtxErrorSVC: 59 | // Invalid SVC function called (function=object_id) 60 | break; 61 | default: 62 | // Reserved 63 | break; 64 | } 65 | for (;;) {} 66 | //return 0U; 67 | } 68 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h: -------------------------------------------------------------------------------- 1 | /* ----------------------------------------------------------------------------- 2 | * Copyright (c) 2016 ARM Ltd. 3 | * 4 | * This software is provided 'as-is', without any express or implied warranty. 5 | * In no event will the authors be held liable for any damages arising from 6 | * the use of this software. Permission is granted to anyone to use this 7 | * software for any purpose, including commercial applications, and to alter 8 | * it and redistribute it freely, subject to the following restrictions: 9 | * 10 | * 1. The origin of this software must not be misrepresented; you must not 11 | * claim that you wrote the original software. If you use this software in 12 | * a product, an acknowledgment in the product documentation would be 13 | * appreciated but is not required. 14 | * 15 | * 2. Altered source versions must be plainly marked as such, and must not be 16 | * misrepresented as being the original software. 17 | * 18 | * 3. This notice may not be removed or altered from any source distribution. 19 | * 20 | * $Date: 25. April 2016 21 | * $Revision: V1.0.0 22 | * 23 | * Project: RTE Device Configuration for ARM CMSDK_CM device 24 | * -------------------------------------------------------------------------- */ 25 | 26 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 27 | 28 | #ifndef __RTE_DEVICE_H 29 | #define __RTE_DEVICE_H 30 | 31 | // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] 32 | // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART 33 | #define RTE_USART0 1 34 | 35 | 36 | // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] 37 | // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART 38 | #define RTE_USART1 0 39 | 40 | 41 | // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] 42 | // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART 43 | #define RTE_UART2 0 44 | 45 | 46 | // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] 47 | // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART 48 | #define RTE_UART3 0 49 | 50 | #endif /* __RTE_DEVICE_H */ 51 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/RTE_Device.h.base@1.0.0: -------------------------------------------------------------------------------- 1 | /* ----------------------------------------------------------------------------- 2 | * Copyright (c) 2016 ARM Ltd. 3 | * 4 | * This software is provided 'as-is', without any express or implied warranty. 5 | * In no event will the authors be held liable for any damages arising from 6 | * the use of this software. Permission is granted to anyone to use this 7 | * software for any purpose, including commercial applications, and to alter 8 | * it and redistribute it freely, subject to the following restrictions: 9 | * 10 | * 1. The origin of this software must not be misrepresented; you must not 11 | * claim that you wrote the original software. If you use this software in 12 | * a product, an acknowledgment in the product documentation would be 13 | * appreciated but is not required. 14 | * 15 | * 2. Altered source versions must be plainly marked as such, and must not be 16 | * misrepresented as being the original software. 17 | * 18 | * 3. This notice may not be removed or altered from any source distribution. 19 | * 20 | * $Date: 25. April 2016 21 | * $Revision: V1.0.0 22 | * 23 | * Project: RTE Device Configuration for ARM CMSDK_CM device 24 | * -------------------------------------------------------------------------- */ 25 | 26 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 27 | 28 | #ifndef __RTE_DEVICE_H 29 | #define __RTE_DEVICE_H 30 | 31 | // USART0 (Universal synchronous asynchronous receiver transmitter) [Driver_USART0] 32 | // Configuration settings for Driver_USART0 in component ::CMSIS Driver:USART 33 | #define RTE_USART0 0 34 | 35 | 36 | // USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] 37 | // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART 38 | #define RTE_USART1 0 39 | 40 | 41 | // USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] 42 | // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART 43 | #define RTE_UART2 0 44 | 45 | 46 | // USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] 47 | // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART 48 | #define RTE_UART3 0 49 | 50 | #endif /* __RTE_DEVICE_H */ 51 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /*--------------------- Uninitilized RAM Configuration ----------------------- 36 | ; Uninitialized RAM Configuration 37 | ; Uninitilized RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 38 | ; 39 | *----------------------------------------------------------------------------*/ 40 | #define __NOINIT_SIZE 0x00001000 41 | 42 | /* 43 | ;------------- <<< end of configuration section >>> --------------------------- 44 | */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | User Stack & Heap boundary definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 51 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 52 | 53 | 54 | /*---------------------------------------------------------------------------- 55 | Scatter File Definitions definition 56 | *----------------------------------------------------------------------------*/ 57 | #define __RO_BASE __ROM_BASE 58 | #define __RO_SIZE __ROM_SIZE 59 | 60 | #define __RW_BASE __RAM_BASE 61 | #define __RW_SIZE (__RAM_SIZE - 0x100 - __STACK_SIZE - __HEAP_SIZE - __NOINIT_SIZE) 62 | #define __RW_NOINIT_BASE (__RAM_BASE + __RW_SIZE) 63 | 64 | 65 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 66 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 67 | *.o (RESET, +First) 68 | *(InRoot$$Sections) 69 | .ANY (+RO) 70 | .ANY (+XO) 71 | } 72 | 73 | RW_RAM_PRIV __RW_BASE EMPTY 0x100 { ; RAM only accessible by privileged code (MPU) 74 | } 75 | 76 | RW_RAM (__RW_BASE + 0x100) __RW_SIZE { ; RW data 77 | .ANY (+RW +ZI) 78 | } 79 | 80 | #if __NOINIT_SIZE > 0 81 | RW_NOINIT __RW_NOINIT_BASE UNINIT __NOINIT_SIZE { ; no init data 82 | *(.bss.noinit) 83 | *(.bss.noinit.*) 84 | } 85 | #endif 86 | 87 | #if __HEAP_SIZE > 0 88 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 89 | } 90 | #endif 91 | 92 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 93 | } 94 | } 95 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/ac6_arm.sct.base@1.0.0: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_RAM __RW_BASE __RW_SIZE { ; RW data 66 | .ANY (+RW +ZI) 67 | } 68 | 69 | #if __HEAP_SIZE > 0 70 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 71 | } 72 | #endif 73 | 74 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ARM-software/CMSIS-View/486ca2726d4a5de4895c9d3c273781d141b4a5b3/Examples/Fault/FVP_MPS2_Cortex-M7/RTE/Device/CMSDK_CM7_SP_VHT/gcc_arm.ld.base@1.1.0 -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/RTE/_Debug_FVP_MPS2_Cortex-M7/RTE_Components.h: -------------------------------------------------------------------------------- 1 | /* 2 | * CSOLUTION generated file: DO NOT EDIT! 3 | * Generated by: csolution version 2.6.0 4 | * 5 | * Project: 'Fault.Debug+FVP_MPS2_Cortex-M7' 6 | * Target: 'Debug+FVP_MPS2_Cortex-M7' 7 | */ 8 | 9 | #ifndef RTE_COMPONENTS_H 10 | #define RTE_COMPONENTS_H 11 | 12 | 13 | /* 14 | * Define the Device Header File: 15 | */ 16 | #define CMSIS_device_header "CMSDK_CM7_SP.h" 17 | 18 | /* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ 19 | #define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ 20 | #define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ 21 | /* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ 22 | #define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ 23 | #define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ 24 | /* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ 25 | #define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ 26 | #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ 27 | /* ARM::CMSIS-View:Event Recorder&Semihosting@1.6.0 */ 28 | #define RTE_CMSIS_View_EventRecorder 29 | #define RTE_CMSIS_View_EventRecorder_DAP 30 | #define RTE_CMSIS_View_EventRecorder_Semihosting 31 | /* ARM::CMSIS-View:Fault:Record@1.1.0 */ 32 | #define RTE_CMSIS_View_Fault_Record 33 | /* ARM::CMSIS-View:Fault:Storage@1.1.0 */ 34 | #define RTE_CMSIS_View_Fault_Storage 35 | /* ARM::CMSIS:RTOS2:Keil RTX5&Source@5.9.0 */ 36 | #define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ 37 | #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ 38 | #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ 39 | /* Keil::CMSIS Driver:USART@1.0.3 */ 40 | #define RTE_Drivers_USART 41 | 42 | 43 | #endif /* RTE_COMPONENTS_H */ 44 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/debug.ini: -------------------------------------------------------------------------------- 1 | CORE_CLK=25000000 2 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/fvp_config.txt: -------------------------------------------------------------------------------- 1 | # Parameters: 2 | # instance.parameter=value #(type, mode) default = 'def value' : description : [min..max] 3 | #------------------------------------------------------------------------------ 4 | armcortexm7ct.vfp-present=1 # (bool , init-time) default = '1' : Set whether the model has VFP support 5 | armcortexm7ct.semihosting-enable=1 # (bool , init-time) default = '0' : Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false. 6 | fvp_mps2.UART0.out_file=- # (string, init-time) default = '' : Output file to hold data written by the UART (use '-' to send all output to stdout) 7 | fvp_mps2.UART0.shutdown_on_eot=1 # (bool , init-time) default = '0' : Shutdown simulation when a EOT (ASCII 4) char is transmitted (useful for regression tests when semihosting is not available) 8 | fvp_mps2.UART0.unbuffered_output=1 # (bool , init-time) default = '0' : Unbuffered output 9 | fvp_mps2.mps2_visualisation.disable-visualisation=1 # (bool , init-time) default = '0' : Enable/disable visualisation 10 | #------------------------------------------------------------------------------ 11 | -------------------------------------------------------------------------------- /Examples/Fault/FVP_MPS2_Cortex-M7/retarget_stdio.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2023 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | * 18 | * Name: retarget_stdio.c 19 | * Purpose: Retarget STDIO to USART0 20 | * 21 | */ 22 | 23 | #include "Driver_USART.h" 24 | 25 | extern int stdio_init (void); 26 | extern int stderr_putchar (int ch); 27 | extern int stdout_putchar (int ch); 28 | extern int stdin_getchar (void); 29 | 30 | #define USART_DRV_NUM 0 31 | #define USART_BAUDRATE 115200 32 | 33 | #define _USART_Driver_(n) Driver_USART##n 34 | #define USART_Driver_(n) _USART_Driver_(n) 35 | 36 | extern ARM_DRIVER_USART USART_Driver_(USART_DRV_NUM); 37 | #define ptrUSART (&USART_Driver_(USART_DRV_NUM)) 38 | 39 | /** 40 | Initialize stdio 41 | 42 | \return 0 on success, or -1 on error. 43 | */ 44 | int stdio_init (void) { 45 | 46 | if (ptrUSART->Initialize(NULL) != ARM_DRIVER_OK) { 47 | return -1; 48 | } 49 | 50 | if (ptrUSART->PowerControl(ARM_POWER_FULL) != ARM_DRIVER_OK) { 51 | return -1; 52 | } 53 | 54 | if (ptrUSART->Control(ARM_USART_MODE_ASYNCHRONOUS | 55 | ARM_USART_DATA_BITS_8 | 56 | ARM_USART_PARITY_NONE | 57 | ARM_USART_STOP_BITS_1 | 58 | ARM_USART_FLOW_CONTROL_NONE, 59 | USART_BAUDRATE) != ARM_DRIVER_OK) { 60 | return -1; 61 | } 62 | 63 | if (ptrUSART->Control(ARM_USART_CONTROL_RX, 1U) != ARM_DRIVER_OK) { 64 | return -1; 65 | } 66 | 67 | return 0; 68 | } 69 | 70 | /** 71 | Put a character to the stderr 72 | 73 | \param[in] ch Character to output 74 | \return The character written, or -1 on error. 75 | */ 76 | int stderr_putchar (int ch) { 77 | uint8_t buf[1]; 78 | 79 | buf[0] = (uint8_t)ch; 80 | 81 | if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { 82 | return -1; 83 | } 84 | 85 | while (ptrUSART->GetTxCount() != 1U); 86 | 87 | return ch; 88 | } 89 | 90 | /** 91 | Put a character to the stdout 92 | 93 | \param[in] ch Character to output 94 | \return The character written, or -1 on write error. 95 | */ 96 | int stdout_putchar (int ch) { 97 | uint8_t buf[1]; 98 | 99 | buf[0] = (uint8_t)ch; 100 | 101 | if (ptrUSART->Send(buf, 1U) != ARM_DRIVER_OK) { 102 | return -1; 103 | } 104 | 105 | while (ptrUSART->GetTxCount() != 1U); 106 | 107 | return ch; 108 | } 109 | 110 | /** 111 | Get a character from the stdio 112 | 113 | \return The next character from the input, or -1 on error. 114 | */ 115 | int stdin_getchar (void) { 116 | uint8_t buf[1]; 117 | 118 | if (ptrUSART->Receive(buf, 1U) != ARM_DRIVER_OK) { 119 | return -1; 120 | } 121 | 122 | while (ptrUSART->GetRxCount() != 1U); 123 | 124 | return (int)buf[0]; 125 | } 126 | -------------------------------------------------------------------------------- /gen_pack.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # Version: 3.0 3 | # Date: 2023-11-06 4 | # This bash script generates a CMSIS Software Pack: 5 | # 6 | 7 | set -o pipefail 8 | 9 | # Set version of gen pack library 10 | # For available versions see https://github.com/Open-CMSIS-Pack/gen-pack/tags. 11 | # Use the tag name without the prefix "v", e.g., 0.7.0 12 | REQUIRED_GEN_PACK_LIB="0.11.1" 13 | 14 | # Set default command line arguments 15 | DEFAULT_ARGS=(-c "pack/") 16 | 17 | # Pack warehouse directory - destination 18 | # Default: ./output 19 | # 20 | # PACK_OUTPUT=./output 21 | 22 | # Temporary pack build directory, 23 | # Default: ./build 24 | # 25 | # PACK_BUILD=./build 26 | 27 | # Specify directory names to be added to pack base directory 28 | # An empty list defaults to all folders next to this script. 29 | # Default: empty (all folders) 30 | # 31 | PACK_DIRS=" 32 | Documentation 33 | EventRecorder 34 | Examples 35 | Fault 36 | " 37 | 38 | # Specify file names to be added to pack base directory 39 | # Default: empty 40 | # 41 | PACK_BASE_FILES=" 42 | LICENSE 43 | " 44 | 45 | # Specify file names to be deleted from pack build directory 46 | # Default: empty 47 | # 48 | PACK_DELETE_FILES=" 49 | Documentation/Doxygen 50 | Documentation/README.md 51 | " 52 | 53 | # Specify patches to be applied 54 | # Default: empty 55 | # 56 | # PACK_PATCH_FILES="" 57 | 58 | # Specify addition argument to packchk 59 | # Default: empty 60 | # 61 | # PACKCHK_ARGS=() 62 | 63 | # Specify additional dependencies for packchk 64 | # Default: empty 65 | # 66 | PACKCHK_DEPS=" 67 | ARM.CMSIS.pdsc 68 | ARM.V2M_MPS3_SSE_300_BSP.pdsc 69 | Keil.B-U585I-IOT02A_BSP.pdsc 70 | Keil.V2M-MPS2_CMx_BSP.pdsc 71 | " 72 | 73 | # Optional: restrict fallback modes for changelog generation 74 | # Default: full 75 | # Values: 76 | # - full Tag annotations, release descriptions, or commit messages (in order) 77 | # - release Tag annotations, or release descriptions (in order) 78 | # - tag Tag annotations only 79 | # 80 | PACK_CHANGELOG_MODE="tag" 81 | 82 | # 83 | # custom pre-processing steps 84 | # 85 | # usage: preprocess 86 | # The build folder 87 | # 88 | function preprocess() { 89 | # add custom steps here to be executed 90 | # before populating the pack build folder 91 | ./Documentation/Doxygen/gen_doc.sh 92 | return 0 93 | } 94 | 95 | # 96 | # custom post-processing steps 97 | # 98 | # usage: postprocess 99 | # The build folder 100 | # 101 | function postprocess() { 102 | # add custom steps here to be executed 103 | # after populating the pack build folder 104 | # but before archiving the pack into output folder 105 | return 0 106 | } 107 | 108 | ############ DO NOT EDIT BELOW ########### 109 | 110 | # Set GEN_PACK_LIB_PATH to use a specific gen-pack library root 111 | # ... instead of bootstrap based on REQUIRED_GEN_PACK_LIB 112 | if [[ -f "${GEN_PACK_LIB_PATH}/gen-pack" ]]; then 113 | . "${GEN_PACK_LIB}/gen-pack" 114 | else 115 | . <(curl -sL "https://raw.githubusercontent.com/Open-CMSIS-Pack/gen-pack/main/bootstrap") 116 | fi 117 | 118 | gen_pack "${DEFAULT_ARGS[@]}" "$@" 119 | 120 | exit 0 121 | -------------------------------------------------------------------------------- /tools/eventlist/.golangci.yaml: -------------------------------------------------------------------------------- 1 | linters: 2 | enable: 3 | - errname 4 | - errorlint 5 | - goerr113 6 | - makezero 7 | - nilerr 8 | - paralleltest 9 | - prealloc 10 | - predeclared 11 | - revive 12 | - thelper 13 | - unconvert 14 | - unparam 15 | - wastedassign 16 | -------------------------------------------------------------------------------- /tools/eventlist/docs/eventlist.tsdl: -------------------------------------------------------------------------------- 1 | 2 | 3 | /* Common Trace Format (CTF) TSDL description 1.8 */ 4 | // TSDL of log file format used by EventList 5 | // Maps to definitions in EventRecorder.h 6 | 7 | integer { 8 | size = 16; 9 | align = 16; 10 | byte_order = le; 11 | signed = false; 12 | }; 13 | 14 | typealias integer { 15 | size = 64; 16 | } := time; 17 | 18 | typealias integer { 19 | size = 16; 20 | } := uint16; 21 | 22 | typealias integer { 23 | size = 32; 24 | } := uint32; 25 | 26 | typealias struct { 27 | uint16 class:8; 28 | uint16 group:3; 29 | uint16 stop:1; 30 | uint16 idx:4; 31 | } := id; 32 | 33 | typealias struct { 34 | uint16 irq:1; 35 | uint16 length:15; 36 | } := len; 37 | 38 | typealias struct { 39 | id _id; 40 | len _len; 41 | } := info; 42 | 43 | struct { 44 | enum: uint16 { EventRecordData = 1, EventRecord2, EventRecord4 } tag; 45 | uint16 size; 46 | time _time; 47 | info _info; 48 | variant { 49 | struct { // EventRecordData 50 | char data[_info.length]; 51 | } EventRecordData; 52 | struct { // EventRecord2 53 | uint32 value1; 54 | uint32 value2; 55 | } EventRecord2; 56 | struct { // EventRecord4 57 | uint32 value1; 58 | uint32 value2; 59 | uint32 value3; 60 | uint32 value4; 61 | } EventRecord4; 62 | } v; 63 | }; 64 | 65 | -------------------------------------------------------------------------------- /tools/eventlist/docs/index.html: -------------------------------------------------------------------------------- 1 |  2 | 3 | 4 | Redirect to the eventlist documentation page after 0 seconds 5 | 6 | 7 | 8 | 9 | 10 | 11 | If the automatic redirection is failing, click open eventlist documentation. 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /tools/eventlist/go.mod: -------------------------------------------------------------------------------- 1 | module eventlist 2 | 3 | go 1.20 4 | 5 | require ( 6 | github.com/akavel/rsrc v0.10.2 // indirect 7 | github.com/josephspurrier/goversioninfo v1.4.0 8 | ) 9 | -------------------------------------------------------------------------------- /tools/eventlist/go.sum: -------------------------------------------------------------------------------- 1 | github.com/PaesslerAG/jsonpath v0.1.0/go.mod h1:4BzmtoM/PI8fPO4aQGIusjGxGir2BzcV0grWtFzq1Y8= 2 | github.com/akavel/rsrc v0.10.2 h1:Zxm8V5eI1hW4gGaYsJQUhxpjkENuG91ki8B4zCrvEsw= 3 | github.com/akavel/rsrc v0.10.2/go.mod h1:uLoCtb9J+EyAqh+26kdrTgmzRBFPGOolLWKpdxkKq+c= 4 | github.com/davecgh/go-spew v1.1.0/go.mod h1:J7Y8YcW2NihsgmVo/mv3lAwl/skON4iLHjSsI+c5H38= 5 | github.com/josephspurrier/goversioninfo v1.4.0 h1:Puhl12NSHUSALHSuzYwPYQkqa2E1+7SrtAPJorKK0C8= 6 | github.com/josephspurrier/goversioninfo v1.4.0/go.mod h1:JWzv5rKQr+MmW+LvM412ToT/IkYDZjaclF2pKDss8IY= 7 | github.com/pmezard/go-difflib v1.0.0/go.mod h1:iKH77koFhYxTK1pcRnkKkqfTogsbg7gZNVY4sRDYZ/4= 8 | github.com/stretchr/objx v0.1.0/go.mod h1:HFkY916IF+rwdDfMAkV7OtwuqBVzrE8GR6GFx+wExME= 9 | github.com/stretchr/testify v1.6.1/go.mod h1:6Fq8oRcR53rry900zMqJjRRixrwX3KX962/h/Wwjteg= 10 | gopkg.in/check.v1 v0.0.0-20161208181325-20d25e280405/go.mod h1:Co6ibVJAznAaIkqp8huTwlJQCZ016jof/cbN4VW5Yz0= 11 | gopkg.in/yaml.v3 v3.0.0-20200313102051-9f266ea9e77c/go.mod h1:K4uyk7z7BCEPqu6E+C64Yfv1cQ7kz7rIZviUmN+EgEM= 12 | -------------------------------------------------------------------------------- /tools/eventlist/make.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | # ------------------------------------------------------- 4 | # Copyright (c) 2023 Arm Limited. All rights reserved. 5 | # 6 | # SPDX-License-Identifier: Apache-2.0 7 | # ------------------------------------------------------- 8 | 9 | # usage 10 | usage() { 11 | echo "" 12 | echo "Usage:" 13 | echo " make.sh [OPTIONS...]" 14 | echo "" 15 | echo "commands:" 16 | echo " build : Build executable" 17 | echo " coverage : Run tests with coverage info" 18 | echo " format : Align indentation and format code" 19 | echo " lint : Run linter" 20 | echo " test : Run all tests" 21 | echo "" 22 | echo "build options:" 23 | echo " -arch arg : Optional target architecture for e.g amd64 etc [default: host arch]" 24 | echo " -os arg : Optional target operating system for e.g windows, linux, darwin etc [default: host OS]" 25 | echo " -outdir arg : Optional output directory for executable generation [default: current directory]" 26 | echo "" 27 | echo "coverage options:" 28 | echo " -html arg : Coverage file path" 29 | } 30 | 31 | if [ $# -eq 0 ] 32 | then 33 | usage 34 | exit 0 35 | fi 36 | 37 | for cmdline in "$@" 38 | do 39 | if [[ "${cmdline}" == "help" || "${cmdline}" == "-h" || "${cmdline}" == "--help" ]]; then 40 | usage 41 | exit 0 42 | fi 43 | arg="${cmdline}" 44 | args+=("${arg}") 45 | done 46 | 47 | go run cmd/make/make.go "${args[@]}" 48 | 49 | RESULT=$? 50 | if [ $RESULT -ne 0 ]; then 51 | usage 52 | exit 1 53 | fi 54 | exit 0 -------------------------------------------------------------------------------- /tools/eventlist/pkg/eval/eval.go: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2022-2025 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | package eval 20 | 21 | import ( 22 | "errors" 23 | ) 24 | 25 | type Member struct { 26 | Offset string 27 | IType Type 28 | Enums map[int64]string 29 | } 30 | type ITypedef struct { 31 | Size uint32 32 | BigEndian bool 33 | Members map[string]Member 34 | } 35 | type Typedefs map[string]ITypedef 36 | 37 | // Eval evaluates a string expression and returns its computed Value. 38 | // It takes a pointer to the string expression `s`, a map of type definitions `typedefs`, 39 | // and a map `tdUsed` to track used type definitions. 40 | // It returns the evaluated Value and an error if the evaluation fails. 41 | // 42 | // Parameters: 43 | // - s: A pointer to the string expression to be evaluated. 44 | // - typedefs: A map of type definitions used in the evaluation. 45 | // - tdUsed: A map to track used type definitions during the evaluation. 46 | // 47 | // Returns: 48 | // - Value: The computed value of the evaluated expression. 49 | // - error: An error if the evaluation fails. 50 | func Eval(s *string, typedefs Typedefs, tdUsed map[string]string) (Value, error) { 51 | var ex Expression 52 | var v Value 53 | var err error 54 | 55 | ex.in = s 56 | ex.pos = 0 57 | ex.typedefs = typedefs 58 | ex.tdUsed = tdUsed 59 | if ex.next, err = ex.lex(); err != nil { 60 | return v, err 61 | } 62 | return ex.expression() 63 | } 64 | 65 | // GetValue evaluates the value of the Enum and returns it as an int64. 66 | // If an error occurs during evaluation, it returns the error unless the error is eval.ErrEof. 67 | // 68 | // Returns: 69 | // - int64: The evaluated integer value of the Enum. 70 | // - error: An error if the evaluation fails, except for eval.ErrEof. 71 | func GetValue(value string, typedefs Typedefs) (int64, error) { 72 | n, err := Eval(&value, typedefs, nil) 73 | if err != nil && !errors.Is(err, ErrEof) { 74 | return 0, err 75 | } 76 | return n.GetInt(), nil 77 | } 78 | 79 | // GetIdValue evaluates the ID and returns its value as an IDType(uint16). 80 | // If an error occurs during evaluation, it returns 0 and the error. 81 | // It ignores eval.ErrEof. 82 | func GetIdValue(id string, typedefs Typedefs) (uint16, error) { //nolint:golint,revive 83 | n, err := Eval(&id, typedefs, nil) 84 | if err != nil && !errors.Is(err, ErrEof) { 85 | return 0, err 86 | } 87 | return uint16(n.GetInt()), nil 88 | } 89 | -------------------------------------------------------------------------------- /tools/eventlist/pkg/eval/eval_test.go: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2022-2025 Arm Limited. All rights reserved. 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Licensed under the Apache License, Version 2.0 (the License); you may 7 | * not use this file except in compliance with the License. 8 | * You may obtain a copy of the License at 9 | * 10 | * www.apache.org/licenses/LICENSE-2.0 11 | * 12 | * Unless required by applicable law or agreed to in writing, software 13 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 | * See the License for the specific language governing permissions and 16 | * limitations under the License. 17 | */ 18 | 19 | package eval 20 | 21 | import ( 22 | "reflect" 23 | "testing" 24 | ) 25 | 26 | func TestEval(t *testing.T) { 27 | t.Parallel() 28 | 29 | var s0 = "1+1" 30 | var s1 = "1+0.23" 31 | var s2 = "1+" 32 | var s3 = "" 33 | tds := make(Typedefs) 34 | 35 | type args struct { 36 | s *string 37 | typedefs Typedefs 38 | tdUsed map[string]string 39 | } 40 | tests := []struct { 41 | name string 42 | args args 43 | want Value 44 | wantErr bool 45 | }{ 46 | {"test " + s0, args{&s0, tds, nil}, Value{t: Integer, i: 2}, false}, 47 | {"test " + s1, args{&s1, tds, nil}, Value{t: Floating, f: 1.23}, false}, 48 | {"test " + s2, args{&s2, tds, nil}, Value{t: Nix}, true}, 49 | {"test eof", args{&s3, tds, nil}, Value{t: Nix}, true}, 50 | } 51 | for _, tt := range tests { 52 | tt := tt 53 | t.Run(tt.name, func(t *testing.T) { 54 | t.Parallel() 55 | 56 | got, err := Eval(tt.args.s, tt.args.typedefs, tt.args.tdUsed) 57 | if (err != nil) != tt.wantErr { 58 | t.Errorf("Eval() error = %v, wantErr %v", err, tt.wantErr) 59 | return 60 | } 61 | if !reflect.DeepEqual(got, tt.want) { 62 | t.Errorf("Eval() = %v, want %v", got, tt.want) 63 | } 64 | }) 65 | } 66 | } 67 | 68 | func TestGetValue(t *testing.T) { //nolint:golint,paralleltest 69 | var tds = make(Typedefs) 70 | 71 | type args struct { 72 | value string 73 | typedefs Typedefs 74 | } 75 | tests := []struct { 76 | name string 77 | args args 78 | want int64 79 | wantErr bool 80 | }{ 81 | {"GetInfo", args{"1+1", tds}, 2, false}, 82 | {"GetInfo err", args{"??", tds}, 0, true}, 83 | } 84 | for _, tt := range tests { //nolint:golint,paralleltest 85 | t.Run(tt.name, func(t *testing.T) { 86 | got, err := GetValue(tt.args.value, tt.args.typedefs) 87 | if (err != nil) != tt.wantErr { 88 | t.Errorf("GetInfo() error = %v, wantErr %v", err, tt.wantErr) 89 | return 90 | } 91 | if got != tt.want { 92 | t.Errorf("GetInfo() = %v, want %v", got, tt.want) 93 | } 94 | }) 95 | } 96 | } 97 | 98 | func TestGetIdValue(t *testing.T) { //nolint:golint,paralleltest 99 | id1 := "2+3" 100 | id2 := "==" 101 | var tds = make(Typedefs) 102 | 103 | type args struct { 104 | id string 105 | typedefs Typedefs 106 | } 107 | tests := []struct { 108 | name string 109 | args args 110 | want uint16 111 | wantErr bool 112 | }{ 113 | {"getIdValue", args{id1, tds}, 5, false}, 114 | {"getIdValue err", args{id2, tds}, 0, true}, 115 | } 116 | for _, tt := range tests { //nolint:golint,paralleltest 117 | t.Run(tt.name, func(t *testing.T) { 118 | got, err := GetIdValue(tt.args.id, tt.args.typedefs) 119 | if (err != nil) != tt.wantErr { 120 | t.Errorf("GetIdValue() error = %v, wantErr %v", err, tt.wantErr) 121 | return 122 | } 123 | if got != tt.want { 124 | t.Errorf("GetIdValue() = %v, want %v", got, tt.want) 125 | } 126 | }) 127 | } 128 | } 129 | -------------------------------------------------------------------------------- /tools/eventlist/template/third_party_licenses.md.template: -------------------------------------------------------------------------------- 1 | # Third Party Intellectual Property (TPIP) Report for [eventlist](https://github.com/ARM-software/CMSIS-View/tree/main/tools/eventlist) 2 | 3 | | __Name__ | __Version__ | __Licence__ | 4 | |----------|-------------|-------------| 5 | {{- range . }} 6 | | {{ .Name }} | {{ .Version }} | [{{ .LicenseName }}]({{ .LicenseURL }}) | 7 | {{- end }} 8 | 9 | Report generated and repository checked for [forbidden](https://github.com/google/licenseclassifier/blob/842c0d70d7027215932deb13801890992c9ba364/license_type.go#L323) and [restricted](https://github.com/google/licenseclassifier/blob/842c0d70d7027215932deb13801890992c9ba364/license_type.go#L176) licenses. -------------------------------------------------------------------------------- /tools/eventlist/testdata/elfsym.elf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ARM-software/CMSIS-View/486ca2726d4a5de4895c9d3c273781d141b4a5b3/tools/eventlist/testdata/elfsym.elf -------------------------------------------------------------------------------- /tools/eventlist/testdata/elftest.elf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /tools/eventlist/testdata/test1.binary: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /tools/eventlist/testdata/test1.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | -------------------------------------------------------------------------------- /tools/eventlist/testdata/test10.binary: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ARM-software/CMSIS-View/486ca2726d4a5de4895c9d3c273781d141b4a5b3/tools/eventlist/testdata/test10.binary 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| 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /tools/eventlist/testdata/test_err2.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /tools/eventlist/testdata/test_err3.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /tools/eventlist/third_party_licenses.md: -------------------------------------------------------------------------------- 1 | # Third Party Intellectual Property (TPIP) Report for [eventlist](https://github.com/ARM-software/CMSIS-View/tree/main/tools/eventlist) 2 | 3 | | __Name__ | __Version__ | __Licence__ | 4 | |----------|-------------|-------------| 5 | | eventlist | Unknown | [Apache-2.0](Unknown) | 6 | | github.com/akavel/rsrc | v0.10.2 | [MIT](https://github.com/akavel/rsrc/blob/v0.10.2/LICENSE.txt) | 7 | | github.com/josephspurrier/goversioninfo | v1.4.0 | [MIT](https://github.com/josephspurrier/goversioninfo/blob/v1.4.0/LICENSE) | 8 | 9 | Report generated and repository checked for [forbidden](https://github.com/google/licenseclassifier/blob/842c0d70d7027215932deb13801890992c9ba364/license_type.go#L323) and [restricted](https://github.com/google/licenseclassifier/blob/842c0d70d7027215932deb13801890992c9ba364/license_type.go#L176) licenses. --------------------------------------------------------------------------------