├── .github ├── dependabot.yml └── workflows │ └── pack.yaml ├── .gitignore ├── ARM.Cortex_DFP.pdsc ├── Device ├── ARMCA35 │ ├── Config │ │ ├── ARMCA35_ac6.sct │ │ ├── ARMCA35_gcc.ld │ │ ├── ARMCA35_iar.icf │ │ └── mem_ARMCA35.h │ ├── Include │ │ ├── ARMCA35.h │ │ └── system_ARMCA35.h │ └── Source │ │ ├── startup_ARMCA35.c │ │ └── system_ARMCA35.c ├── ARMCA5 │ ├── Config │ │ ├── ARMCA5_ac6.sct │ │ ├── ARMCA5_gcc.ld │ │ ├── ARMCA5_iar.icf │ │ └── mem_ARMCA5.h │ ├── Include │ │ ├── ARMCA5.h │ │ └── system_ARMCA5.h │ └── Source │ │ ├── mmu_ARMCA5.c │ │ ├── startup_ARMCA5.c │ │ └── system_ARMCA5.c ├── ARMCA53 │ ├── Config │ │ ├── ARMCA53_ac6.sct │ │ ├── ARMCA53_gcc.ld │ │ ├── ARMCA53_iar.icf │ │ └── mem_ARMCA53.h │ ├── Include │ │ ├── ARMCA53.h │ │ └── system_ARMCA53.h │ └── Source │ │ ├── startup_ARMCA53.c │ │ └── system_ARMCA53.c ├── ARMCA55 │ ├── Config │ │ ├── ARMCA55_ac6.sct │ │ ├── ARMCA55_gcc.ld │ │ ├── ARMCA55_iar.icf │ │ └── mem_ARMCA55.h │ ├── Include │ │ ├── ARMCA55.h │ │ └── system_ARMCA55.h │ └── Source │ │ ├── startup_ARMCA55.c │ │ └── system_ARMCA55.c ├── ARMCA57 │ ├── Config │ │ ├── ARMCA57_ac6.sct │ │ ├── ARMCA57_gcc.ld │ │ ├── ARMCA57_iar.icf │ │ └── mem_ARMCA57.h │ ├── Include │ │ ├── ARMCA57.h │ │ └── system_ARMCA57.h │ └── Source │ │ ├── startup_ARMCA57.c │ │ └── system_ARMCA57.c ├── ARMCA7 │ ├── Config │ │ ├── ARMCA7_ac6.sct │ │ ├── ARMCA7_gcc.ld │ │ ├── ARMCA7_iar.icf │ │ └── mem_ARMCA7.h │ ├── Include │ │ ├── ARMCA7.h │ │ └── system_ARMCA7.h │ └── Source │ │ ├── mmu_ARMCA7.c │ │ ├── startup_ARMCA7.c │ │ └── system_ARMCA7.c ├── ARMCA9 │ ├── Config │ │ ├── ARMCA9_ac6.sct │ │ ├── ARMCA9_gcc.ld │ │ ├── ARMCA9_iar.icf │ │ └── mem_ARMCA9.h │ ├── Include │ │ ├── ARMCA9.h │ │ └── system_ARMCA9.h │ └── Source │ │ ├── mmu_ARMCA9.c │ │ ├── startup_ARMCA9.c │ │ └── system_ARMCA9.c ├── ARMCM0 │ ├── Config │ │ ├── ARMCM0_ac6.sct │ │ └── ARMCM0_gcc.ld │ ├── Include │ │ ├── ARMCM0.h │ │ └── system_ARMCM0.h │ └── Source │ │ ├── startup_ARMCM0.c │ │ └── system_ARMCM0.c ├── ARMCM0plus │ ├── Config │ │ ├── ARMCM0plus_ac6.sct │ │ └── ARMCM0plus_gcc.ld │ ├── Include │ │ ├── ARMCM0plus.h │ │ └── system_ARMCM0plus.h │ └── Source │ │ ├── startup_ARMCM0plus.c │ │ └── system_ARMCM0plus.c ├── ARMCM1 │ ├── Config │ │ ├── ARMCM1_ac6.sct │ │ └── ARMCM1_gcc.ld │ ├── Include │ │ ├── ARMCM1.h │ │ └── system_ARMCM1.h │ └── Source │ │ ├── startup_ARMCM1.c │ │ └── system_ARMCM1.c ├── ARMCM23 │ ├── Config │ │ ├── ARMCM23_ac6.sct │ │ ├── ARMCM23_gcc.ld │ │ └── partition_ARMCM23.h │ ├── Include │ │ ├── ARMCM23.h │ │ └── system_ARMCM23.h │ └── Source │ │ ├── startup_ARMCM23.c │ │ └── system_ARMCM23.c ├── ARMCM3 │ ├── Config │ │ ├── ARMCM3_ac6.sct │ │ └── ARMCM3_gcc.ld │ ├── Include │ │ ├── ARMCM3.h │ │ └── system_ARMCM3.h │ └── Source │ │ ├── startup_ARMCM3.c │ │ └── system_ARMCM3.c ├── ARMCM33 │ ├── Config │ │ ├── ARMCM33_ac6.sct │ │ ├── ARMCM33_gcc.ld │ │ └── partition_ARMCM33.h │ ├── Include │ │ ├── ARMCM33.h │ │ └── system_ARMCM33.h │ └── Source │ │ ├── startup_ARMCM33.c │ │ └── system_ARMCM33.c ├── ARMCM35P │ ├── Config │ │ ├── ARMCM35P_ac6.sct │ │ ├── ARMCM35P_gcc.ld │ │ └── partition_ARMCM35P.h │ ├── Include │ │ ├── ARMCM35P.h │ │ └── system_ARMCM35P.h │ └── Source │ │ ├── startup_ARMCM35P.c │ │ └── system_ARMCM35P.c ├── ARMCM4 │ ├── Config │ │ ├── ARMCM4_ac6.sct │ │ └── ARMCM4_gcc.ld │ ├── Include │ │ ├── ARMCM4.h │ │ └── system_ARMCM4.h │ └── Source │ │ ├── startup_ARMCM4.c │ │ └── system_ARMCM4.c ├── ARMCM52 │ ├── Config │ │ ├── ARMCM52_ac6.sct │ │ ├── ARMCM52_gcc.ld │ │ └── partition_ARMCM52.h │ ├── Include │ │ ├── ARMCM52.h │ │ └── system_ARMCM52.h │ └── Source │ │ ├── startup_ARMCM52.c │ │ └── system_ARMCM52.c ├── ARMCM55 │ ├── Config │ │ ├── ARMCM55_ac6.sct │ │ ├── ARMCM55_gcc.ld │ │ └── partition_ARMCM55.h │ ├── Include │ │ ├── ARMCM55.h │ │ └── system_ARMCM55.h │ └── Source │ │ ├── startup_ARMCM55.c │ │ └── system_ARMCM55.c ├── ARMCM7 │ ├── Config │ │ ├── ARMCM7_ac6.sct │ │ └── ARMCM7_gcc.ld │ ├── Include │ │ ├── ARMCM7.h │ │ └── system_ARMCM7.h │ └── Source │ │ ├── startup_ARMCM7.c │ │ └── system_ARMCM7.c ├── ARMCM85 │ ├── Config │ │ ├── ARMCM85_ac6.sct │ │ ├── ARMCM85_gcc.ld │ │ └── partition_ARMCM85.h │ ├── Include │ │ ├── ARMCM85.h │ │ └── system_ARMCM85.h │ └── Source │ │ ├── startup_ARMCM85.c │ │ └── system_ARMCM85.c ├── ARMCR4 │ ├── Config │ │ ├── ARMCR4_ac6.sct │ │ ├── ARMCR4_gcc.ld │ │ ├── ARMCR4_iar.icf │ │ └── mem_ARMCR4.h │ ├── Include │ │ ├── ARMCR4.h │ │ └── system_ARMCR4.h │ └── Source │ │ ├── startup_ARMCR4.c │ │ └── system_ARMCR4.c ├── ARMCR5 │ ├── Config │ │ ├── ARMCR5_ac6.sct │ │ ├── ARMCR5_gcc.ld │ │ ├── ARMCR5_iar.icf │ │ └── mem_ARMCR5.h │ ├── Include │ │ ├── ARMCR5.h │ │ └── system_ARMCR5.h │ └── Source │ │ ├── startup_ARMCR5.c │ │ └── system_ARMCR5.c ├── ARMCR7 │ ├── Config │ │ ├── ARMCR7_ac6.sct │ │ ├── ARMCR7_gcc.ld │ │ ├── ARMCR7_iar.icf │ │ └── mem_ARMCR7.h │ ├── Include │ │ ├── ARMCR7.h │ │ └── system_ARMCR7.h │ └── Source │ │ ├── startup_ARMCR7.c │ │ └── system_ARMCR7.c ├── ARMCR8 │ ├── Config │ │ ├── ARMCR8_ac6.sct │ │ ├── ARMCR8_gcc.ld │ │ ├── ARMCR8_iar.icf │ │ └── mem_ARMCR8.h │ ├── Include │ │ ├── ARMCR8.h │ │ └── system_ARMCR8.h │ └── Source │ │ ├── startup_ARMCR8.c │ │ └── system_ARMCR8.c ├── ARMSC000 │ ├── Config │ │ ├── ARMSC000_ac6.sct │ │ └── ARMSC000_gcc.ld │ ├── Include │ │ ├── ARMSC000.h │ │ └── system_ARMSC000.h │ └── Source │ │ ├── startup_ARMSC000.c │ │ └── system_ARMSC000.c ├── ARMSC300 │ ├── Config │ │ ├── ARMSC300_ac6.sct │ │ └── ARMSC300_gcc.ld │ ├── Include │ │ ├── ARMSC300.h │ │ └── system_ARMSC300.h │ └── Source │ │ ├── startup_ARMSC300.c │ │ └── system_ARMSC300.c └── Template │ └── Flash │ ├── Abstract.txt │ ├── FlashDev.c │ ├── FlashOS.h │ ├── FlashPrg.c │ ├── NewDevice.uvguix │ ├── NewDevice.uvoptx │ ├── NewDevice.uvprojx │ └── Target.lin ├── LICENSE ├── README.md ├── SVD ├── ARMCM0.svd ├── ARMCM0P.svd ├── ARMCM1.svd ├── ARMCM23.svd ├── ARMCM3.svd ├── ARMCM33.svd ├── ARMCM35P.svd ├── ARMCM4.svd ├── ARMCM52.svd ├── ARMCM55.svd ├── ARMCM7.svd ├── ARMCM85.svd ├── ARMSC000.svd └── ARMSC300.svd └── gen_pack.sh /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | version: 2 2 | updates: 3 | - package-ecosystem: github-actions 4 | directory: "/" 5 | schedule: 6 | interval: "weekly" 7 | open-pull-requests-limit: 10 8 | rebase-strategy: disabled 9 | -------------------------------------------------------------------------------- /.github/workflows/pack.yaml: -------------------------------------------------------------------------------- 1 | name: Build pack 2 | on: 3 | workflow_dispatch: 4 | push: 5 | branches: [ main ] 6 | pull_request: 7 | branches: [ main ] 8 | release: 9 | types: [published] 10 | 11 | concurrency: 12 | group: ${{ github.workflow }}-${{ github.ref }} 13 | cancel-in-progress: true 14 | 15 | jobs: 16 | pack: 17 | if: | 18 | github.event_name != 'release' || 19 | (github.event_name == 'release' && startsWith(github.ref, 'refs/tags/v')) 20 | name: Generate pack 21 | runs-on: ubuntu-22.04 22 | steps: 23 | - uses: actions/checkout@v4 24 | with: 25 | fetch-depth: 0 26 | 27 | - name: Fetch tags 28 | if: github.event_name == 'release' 29 | run: | 30 | git fetch --tags --force 31 | 32 | - uses: Open-CMSIS-Pack/gen-pack-action@main 33 | with: 34 | packchk-version: 1.3.98 35 | gen-pack-script: ./gen_pack.sh 36 | gen-pack-output: ./output 37 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .vs 2 | build 3 | output 4 | -------------------------------------------------------------------------------- /Device/ARMCA35/Config/ARMCA35_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a35 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA35.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA35/Config/ARMCA35_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA35/Include/system_ARMCA35.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA35.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA35_H 29 | #define __SYSTEM_ARMCA35_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA35_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA35/Source/startup_ARMCA35.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file startup_ARMCA35.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2024 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #include 26 | 27 | 28 | /*---------------------------------------------------------------------------- 29 | Internal References 30 | *----------------------------------------------------------------------------*/ 31 | void Vectors (void) __attribute__ ((naked, section("RESET"))); 32 | void Reset_Handler (void) __attribute__ ((naked)); 33 | void Default_Handler(void) __attribute__ ((noreturn)); 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | Exception / Interrupt Vector Table 38 | *----------------------------------------------------------------------------*/ 39 | void Vectors(void) 40 | { 41 | } 42 | 43 | /*---------------------------------------------------------------------------- 44 | Reset Handler called on controller reset 45 | *----------------------------------------------------------------------------*/ 46 | void Reset_Handler(void) 47 | { 48 | __ASM volatile( 49 | // Call __main 50 | "BL __main \n" 51 | ); 52 | } 53 | 54 | /*---------------------------------------------------------------------------- 55 | Default Handler for Exceptions / Interrupts 56 | *----------------------------------------------------------------------------*/ 57 | void Default_Handler(void) { 58 | while(1); 59 | } 60 | -------------------------------------------------------------------------------- /Device/ARMCA35/Source/system_ARMCA35.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA35.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mau 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | // __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | // __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | // __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | // MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | // MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCA5/Config/ARMCA5_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a5 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2017 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA5.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA5/Config/ARMCA5_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA5/Include/system_ARMCA5.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA5.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A5 Device Series 4 | * @version V1.00 5 | * @date 10. January 2018 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA5_H 29 | #define __SYSTEM_ARMCA5_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA5_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA5/Source/system_ARMCA5.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA5.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A5 Device Series 4 | * @version V1.0.1 5 | * @date 13. February 2019 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCA53/Config/ARMCA53_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a53 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2017 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA53.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA53/Config/ARMCA53_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA53/Include/ARMCA53.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ARM-software/Cortex_DFP/36d0d3b118ab8493865044551d05248a5fe53427/Device/ARMCA53/Include/ARMCA53.h -------------------------------------------------------------------------------- /Device/ARMCA53/Include/system_ARMCA53.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA53.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA53_H 29 | #define __SYSTEM_ARMCA53_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA53_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA53/Source/system_ARMCA53.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA53.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | __DSB(); 56 | __ISB(); 57 | 58 | // Invalidate data cache 59 | L1C_InvalidateDCacheAll(); 60 | 61 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 62 | // Enable FPU 63 | __FPU_Enable(); 64 | #endif 65 | 66 | // Create Translation Table 67 | // MMU_CreateTranslationTable(); 68 | 69 | // Enable MMU 70 | // MMU_Enable(); 71 | 72 | // Enable Caches 73 | L1C_EnableCaches(); 74 | L1C_EnableBTAC(); 75 | 76 | #if (__L2C_PRESENT == 1) 77 | // Enable GIC 78 | L2C_Enable(); 79 | #endif 80 | 81 | // IRQ Initialize 82 | IRQ_Initialize(); 83 | } 84 | -------------------------------------------------------------------------------- /Device/ARMCA55/Config/ARMCA55_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-A55 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA55.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA55/Config/ARMCA55_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA55/Include/system_ARMCA55.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA55.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA55_H 29 | #define __SYSTEM_ARMCA55_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA55_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA55/Source/startup_ARMCA55.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file startup_ARMCA55.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2024 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #include 26 | 27 | 28 | /*---------------------------------------------------------------------------- 29 | Internal References 30 | *----------------------------------------------------------------------------*/ 31 | void Vectors (void) __attribute__ ((naked, section("RESET"))); 32 | void Reset_Handler (void) __attribute__ ((naked)); 33 | void Default_Handler(void) __attribute__ ((noreturn)); 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | Exception / Interrupt Vector Table 38 | *----------------------------------------------------------------------------*/ 39 | void Vectors(void) 40 | { 41 | } 42 | 43 | /*---------------------------------------------------------------------------- 44 | Reset Handler called on controller reset 45 | *----------------------------------------------------------------------------*/ 46 | void Reset_Handler(void) 47 | { 48 | __ASM volatile( 49 | // Call __main 50 | "BL __main \n" 51 | ); 52 | } 53 | 54 | /*---------------------------------------------------------------------------- 55 | Default Handler for Exceptions / Interrupts 56 | *----------------------------------------------------------------------------*/ 57 | void Default_Handler(void) { 58 | while(1); 59 | } 60 | -------------------------------------------------------------------------------- /Device/ARMCA55/Source/system_ARMCA55.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA55.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mau 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | // __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | // __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | // __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | // MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | // MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCA57/Config/ARMCA57_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-A57 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA57.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA57/Config/ARMCA57_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA57/Include/system_ARMCA57.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA57.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA57_H 29 | #define __SYSTEM_ARMCA57_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA57_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA57/Source/startup_ARMCA57.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file startup_ARMCA57.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mai 2024 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2024 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #include 26 | 27 | 28 | /*---------------------------------------------------------------------------- 29 | Internal References 30 | *----------------------------------------------------------------------------*/ 31 | void Vectors (void) __attribute__ ((naked, section("RESET"))); 32 | void Reset_Handler (void) __attribute__ ((naked)); 33 | void Default_Handler(void) __attribute__ ((noreturn)); 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | Exception / Interrupt Vector Table 38 | *----------------------------------------------------------------------------*/ 39 | void Vectors(void) 40 | { 41 | } 42 | 43 | /*---------------------------------------------------------------------------- 44 | Reset Handler called on controller reset 45 | *----------------------------------------------------------------------------*/ 46 | void Reset_Handler(void) 47 | { 48 | __ASM volatile( 49 | // Call __main 50 | "BL __main \n" 51 | ); 52 | } 53 | 54 | /*---------------------------------------------------------------------------- 55 | Default Handler for Exceptions / Interrupts 56 | *----------------------------------------------------------------------------*/ 57 | void Default_Handler(void) { 58 | while(1); 59 | } 60 | -------------------------------------------------------------------------------- /Device/ARMCA57/Source/system_ARMCA57.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA57.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 26. Mau 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | // __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | // __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | // __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | // MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | // MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCA7/Config/ARMCA7_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a7 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2017 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA7.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA7/Config/ARMCA7_iar.icf: -------------------------------------------------------------------------------- 1 | 2 | /*-Memory Regions-*/ 3 | define symbol __ICFEDIT_region_IROM1_start__ = 0x80000000; 4 | define symbol __ICFEDIT_region_IROM1_end__ = 0x801FFFFF; 5 | define symbol __ICFEDIT_region_IROM2_start__ = 0x0; 6 | define symbol __ICFEDIT_region_IROM2_end__ = 0x0; 7 | define symbol __ICFEDIT_region_EROM1_start__ = 0x0; 8 | define symbol __ICFEDIT_region_EROM1_end__ = 0x0; 9 | define symbol __ICFEDIT_region_EROM2_start__ = 0x0; 10 | define symbol __ICFEDIT_region_EROM2_end__ = 0x0; 11 | define symbol __ICFEDIT_region_EROM3_start__ = 0x0; 12 | define symbol __ICFEDIT_region_EROM3_end__ = 0x0; 13 | define symbol __ICFEDIT_region_IRAM1_start__ = 0x80200000; 14 | define symbol __ICFEDIT_region_IRAM1_end__ = 0x803FFFFF; 15 | define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; 16 | define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; 17 | define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; 18 | define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; 19 | define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; 20 | define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; 21 | define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; 22 | define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; 23 | define symbol __ICFEDIT_region_TTB_start__ = 0x80500000; 24 | define symbol __ICFEDIT_region_TTB_end__ = 0x805FFFFF; 25 | 26 | /*-Sizes-*/ 27 | define symbol __ICFEDIT_size_cstack__ = 0x1000; 28 | define symbol __ICFEDIT_size_irqstack__ = 0x100; 29 | define symbol __ICFEDIT_size_fiqstack__ = 0x100; 30 | define symbol __ICFEDIT_size_svcstack__ = 0x100; 31 | define symbol __ICFEDIT_size_abtstack__ = 0x100; 32 | define symbol __ICFEDIT_size_undstack__ = 0x100; 33 | define symbol __ICFEDIT_size_heap__ = 0x8000; 34 | define symbol __ICFEDIT_size_ttb__ = 0x4000; 35 | 36 | define memory mem with size = 4G; 37 | define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] 38 | | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; 39 | define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] 40 | | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; 41 | define region ERAM_region = mem:[from __ICFEDIT_region_ERAM1_start__ to __ICFEDIT_region_ERAM1_end__] 42 | | mem:[from __ICFEDIT_region_ERAM2_start__ to __ICFEDIT_region_ERAM2_end__] 43 | | mem:[from __ICFEDIT_region_ERAM3_start__ to __ICFEDIT_region_ERAM3_end__]; 44 | define region TTB_region = mem:[from __ICFEDIT_region_TTB_start__ to __ICFEDIT_region_TTB_end__ ]; 45 | 46 | define block USR_STACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; 47 | define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; 48 | define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; 49 | define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; 50 | define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; 51 | define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; 52 | define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; 53 | define block TTB with alignment = 8, size = __ICFEDIT_size_ttb__ { section TTB }; 54 | 55 | do not initialize { section .noinit }; 56 | 57 | initialize by copy { readwrite }; 58 | if (isdefinedsymbol(__USE_DLIB_PERTHREAD)) 59 | { 60 | // Required in a multi-threaded application 61 | initialize by copy with packing = none { section __DLIB_PERTHREAD }; 62 | } 63 | 64 | place at address mem:__ICFEDIT_region_IROM1_start__ { readonly section RESET }; 65 | place in IROM_region { readonly }; 66 | place in IRAM_region { readwrite, block HEAP, block USR_STACK, block IRQ_STACK, block FIQ_STACK, block SVC_STACK, block ABT_STACK, block UND_STACK }; 67 | place in TTB_region { block TTB }; -------------------------------------------------------------------------------- /Device/ARMCA7/Include/system_ARMCA7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA7.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A7 Device Series 4 | * @version V1.00 5 | * @date 10. January 2018 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA7_H 29 | #define __SYSTEM_ARMCA7_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA7_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA7/Source/system_ARMCA7.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA7.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A7 Device Series 4 | * @version V1.0.1 5 | * @date 13. February 2019 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCA9/Config/ARMCA9_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-a9 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2017 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCA9.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCA9/Include/system_ARMCA9.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA9.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.00 5 | * @date 10. January 2018 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCA9_H 29 | #define __SYSTEM_ARMCA9_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | /** 55 | \brief Create Translation Table. 56 | 57 | Creates Memory Management Unit Translation Table. 58 | */ 59 | extern void MMU_CreateTranslationTable(void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* __SYSTEM_ARMCA9_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMCA9/Source/system_ARMCA9.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCA9.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.1 5 | * @date 13. February 2019 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | 55 | // Invalidate entire Unified TLB 56 | __set_TLBIALL(0); 57 | 58 | // Invalidate entire branch predictor array 59 | __set_BPIALL(0); 60 | __DSB(); 61 | __ISB(); 62 | 63 | // Invalidate instruction cache and flush branch target cache 64 | __set_ICIALLU(0); 65 | __DSB(); 66 | __ISB(); 67 | 68 | // Invalidate data cache 69 | L1C_InvalidateDCacheAll(); 70 | 71 | #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 72 | // Enable FPU 73 | __FPU_Enable(); 74 | #endif 75 | 76 | // Create Translation Table 77 | MMU_CreateTranslationTable(); 78 | 79 | // Enable MMU 80 | MMU_Enable(); 81 | 82 | // Enable Caches 83 | L1C_EnableCaches(); 84 | L1C_EnableBTAC(); 85 | 86 | #if (__L2C_PRESENT == 1) 87 | // Enable GIC 88 | L2C_Enable(); 89 | #endif 90 | 91 | // IRQ Initialize 92 | IRQ_Initialize(); 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCM0/Config/ARMCM0_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM0/Include/system_ARMCM0.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM0 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM0_H 27 | #define SYSTEM_ARMCM0_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM0_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM0/Source/system_ARMCM0.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM0 Device 5 | * @version V1.0.0 6 | * @date 09. July 2018 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM0.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL (50000000UL) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (XTAL / 2U) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | System Core Clock Variable 38 | *----------------------------------------------------------------------------*/ 39 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | System Core Clock update function 44 | *----------------------------------------------------------------------------*/ 45 | void SystemCoreClockUpdate (void) 46 | { 47 | SystemCoreClock = SYSTEM_CLOCK; 48 | } 49 | 50 | /*---------------------------------------------------------------------------- 51 | System initialization function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemInit (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | -------------------------------------------------------------------------------- /Device/ARMCM0plus/Config/ARMCM0plus_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0+ -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM0plus/Include/system_ARMCM0plus.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0plus.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM0 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM0plus_H 27 | #define SYSTEM_ARMCM0plus_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM0plus_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM0plus/Source/system_ARMCM0plus.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM0plus.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM0plus Device 5 | * @version V2.0.0 6 | * @date 06. April 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM0P) 27 | #include "ARMCM0plus.h" 28 | #else 29 | #error device not specified! 30 | #endif 31 | 32 | /*---------------------------------------------------------------------------- 33 | Define clocks 34 | *----------------------------------------------------------------------------*/ 35 | #define XTAL (50000000UL) /* Oscillator frequency */ 36 | 37 | #define SYSTEM_CLOCK (XTAL / 2U) 38 | 39 | /*---------------------------------------------------------------------------- 40 | Exception / Interrupt Vector table 41 | *----------------------------------------------------------------------------*/ 42 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; 43 | 44 | /*---------------------------------------------------------------------------- 45 | System Core Clock Variable 46 | *----------------------------------------------------------------------------*/ 47 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 48 | 49 | 50 | /*---------------------------------------------------------------------------- 51 | System Core Clock update function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemCoreClockUpdate (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | 58 | /*---------------------------------------------------------------------------- 59 | System initialization function 60 | *----------------------------------------------------------------------------*/ 61 | void SystemInit (void) 62 | { 63 | 64 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 65 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 66 | #endif 67 | 68 | SystemCoreClock = SYSTEM_CLOCK; 69 | } 70 | -------------------------------------------------------------------------------- /Device/ARMCM1/Config/ARMCM1_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m1 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM1/Include/system_ARMCM1.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM1.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM1 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM1_H 27 | #define SYSTEM_ARMCM1_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM1_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM1/Source/system_ARMCM1.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM1.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM1 Device 5 | * @version V1.0.0 6 | * @date 20. July 2018 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM1.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL (50000000UL) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (XTAL / 2U) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | System Core Clock Variable 38 | *----------------------------------------------------------------------------*/ 39 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | System Core Clock update function 44 | *----------------------------------------------------------------------------*/ 45 | void SystemCoreClockUpdate (void) 46 | { 47 | SystemCoreClock = SYSTEM_CLOCK; 48 | } 49 | 50 | /*---------------------------------------------------------------------------- 51 | System initialization function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemInit (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | -------------------------------------------------------------------------------- /Device/ARMCM23/Include/system_ARMCM23.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM23.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM23 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM23_H 27 | #define SYSTEM_ARMCM23_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM23_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM23/Source/system_ARMCM23.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM23.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM23 Device 5 | * @version V2.0.0 6 | * @date 06. April 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM23) 27 | #include "ARMCM23.h" 28 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 29 | #include "partition_ARMCM23.h" 30 | #endif 31 | #else 32 | #error device not specified! 33 | #endif 34 | 35 | /*---------------------------------------------------------------------------- 36 | Define clocks 37 | *----------------------------------------------------------------------------*/ 38 | #define XTAL (50000000UL) /* Oscillator frequency */ 39 | 40 | #define SYSTEM_CLOCK (XTAL / 2U) 41 | 42 | /*---------------------------------------------------------------------------- 43 | Exception / Interrupt Vector table 44 | *----------------------------------------------------------------------------*/ 45 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; 46 | 47 | 48 | /*---------------------------------------------------------------------------- 49 | System Core Clock Variable 50 | *----------------------------------------------------------------------------*/ 51 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 52 | 53 | 54 | /*---------------------------------------------------------------------------- 55 | System Core Clock update function 56 | *----------------------------------------------------------------------------*/ 57 | void SystemCoreClockUpdate (void) 58 | { 59 | SystemCoreClock = SYSTEM_CLOCK; 60 | } 61 | 62 | /*---------------------------------------------------------------------------- 63 | System initialization function 64 | *----------------------------------------------------------------------------*/ 65 | void SystemInit (void) 66 | { 67 | 68 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 69 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 70 | #endif 71 | 72 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 73 | TZ_SAU_Setup(); 74 | #endif 75 | 76 | SystemCoreClock = SYSTEM_CLOCK; 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCM3/Config/ARMCM3_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m3 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM3/Include/system_ARMCM3.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM3.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM3 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM3_H 27 | #define SYSTEM_ARMCM3_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM3_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM3/Source/system_ARMCM3.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM3.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM3 Device 5 | * @version V1.0.1 6 | * @date 15. November 2019 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMCM3.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL (50000000UL) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (XTAL / 2U) 34 | 35 | /*---------------------------------------------------------------------------- 36 | Exception / Interrupt Vector table 37 | *----------------------------------------------------------------------------*/ 38 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; 39 | 40 | /*---------------------------------------------------------------------------- 41 | System Core Clock Variable 42 | *----------------------------------------------------------------------------*/ 43 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 44 | 45 | 46 | /*---------------------------------------------------------------------------- 47 | System Core Clock update function 48 | *----------------------------------------------------------------------------*/ 49 | void SystemCoreClockUpdate (void) 50 | { 51 | SystemCoreClock = SYSTEM_CLOCK; 52 | } 53 | 54 | /*---------------------------------------------------------------------------- 55 | System initialization function 56 | *----------------------------------------------------------------------------*/ 57 | void SystemInit (void) 58 | { 59 | 60 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 61 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 62 | #endif 63 | 64 | SystemCoreClock = SYSTEM_CLOCK; 65 | } 66 | -------------------------------------------------------------------------------- /Device/ARMCM33/Include/system_ARMCM33.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM33.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM33 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM33_H 27 | #define SYSTEM_ARMCM33_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM33_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM33/Source/system_ARMCM33.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM33.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM33 Device 5 | * @version V2.0.0 6 | * @date 06. Aril 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM33) 27 | #include "ARMCM33.h" 28 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 29 | #include "partition_ARMCM33.h" 30 | #endif 31 | #else 32 | #error device not specified! 33 | #endif 34 | 35 | /*---------------------------------------------------------------------------- 36 | Define clocks 37 | *----------------------------------------------------------------------------*/ 38 | #define XTAL (50000000UL) /* Oscillator frequency */ 39 | 40 | #define SYSTEM_CLOCK (XTAL / 2U) 41 | 42 | /*---------------------------------------------------------------------------- 43 | Exception / Interrupt Vector table 44 | *----------------------------------------------------------------------------*/ 45 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; 46 | 47 | 48 | /*---------------------------------------------------------------------------- 49 | System Core Clock Variable 50 | *----------------------------------------------------------------------------*/ 51 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 52 | 53 | 54 | /*---------------------------------------------------------------------------- 55 | System Core Clock update function 56 | *----------------------------------------------------------------------------*/ 57 | void SystemCoreClockUpdate (void) 58 | { 59 | SystemCoreClock = SYSTEM_CLOCK; 60 | } 61 | 62 | /*---------------------------------------------------------------------------- 63 | System initialization function 64 | *----------------------------------------------------------------------------*/ 65 | void SystemInit (void) 66 | { 67 | 68 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 69 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 70 | #endif 71 | 72 | #if defined (__FPU_USED) && (__FPU_USED == 1U) 73 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 74 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 75 | #endif 76 | 77 | #ifdef UNALIGNED_SUPPORT_DISABLE 78 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 79 | #endif 80 | 81 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 82 | TZ_SAU_Setup(); 83 | #endif 84 | 85 | SystemCoreClock = SYSTEM_CLOCK; 86 | } 87 | -------------------------------------------------------------------------------- /Device/ARMCM35P/Include/system_ARMCM35P.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM35P.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM35P Device 5 | * @version V1.0.2 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM35P_H 27 | #define SYSTEM_ARMCM35P_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM35P_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM35P/Source/system_ARMCM35P.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM35P.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM35P Device 5 | * @version V2.0.0 6 | * @date 13. July 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM35P) 27 | #include "ARMCM35P.h" 28 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 29 | #include "partition_ARMCM35P.h" 30 | #endif 31 | #else 32 | #error device not specified! 33 | #endif 34 | 35 | /*---------------------------------------------------------------------------- 36 | Define clocks 37 | *----------------------------------------------------------------------------*/ 38 | #define XTAL (50000000UL) /* Oscillator frequency */ 39 | 40 | #define SYSTEM_CLOCK (XTAL / 2U) 41 | 42 | /*---------------------------------------------------------------------------- 43 | Exception / Interrupt Vector table 44 | *----------------------------------------------------------------------------*/ 45 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; 46 | 47 | 48 | /*---------------------------------------------------------------------------- 49 | System Core Clock Variable 50 | *----------------------------------------------------------------------------*/ 51 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 52 | 53 | 54 | /*---------------------------------------------------------------------------- 55 | System Core Clock update function 56 | *----------------------------------------------------------------------------*/ 57 | void SystemCoreClockUpdate (void) 58 | { 59 | SystemCoreClock = SYSTEM_CLOCK; 60 | } 61 | 62 | /*---------------------------------------------------------------------------- 63 | System initialization function 64 | *----------------------------------------------------------------------------*/ 65 | void SystemInit (void) 66 | { 67 | 68 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 69 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 70 | #endif 71 | 72 | #if defined (__FPU_USED) && (__FPU_USED == 1U) 73 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 74 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 75 | #endif 76 | 77 | #ifdef UNALIGNED_SUPPORT_DISABLE 78 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 79 | #endif 80 | 81 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 82 | TZ_SAU_Setup(); 83 | #endif 84 | 85 | SystemCoreClock = SYSTEM_CLOCK; 86 | } 87 | -------------------------------------------------------------------------------- /Device/ARMCM4/Config/ARMCM4_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m4 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM4/Include/system_ARMCM4.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM4.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM4 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM4_H 27 | #define SYSTEM_ARMCM4_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM4_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM4/Source/system_ARMCM4.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM4.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM4 Device 5 | * @version V2.0.0 6 | * @date 06. April 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM4) 27 | #include "ARMCM4.h" 28 | #else 29 | #error device not specified! 30 | #endif 31 | 32 | /*---------------------------------------------------------------------------- 33 | Define clocks 34 | *----------------------------------------------------------------------------*/ 35 | #define XTAL (50000000UL) /* Oscillator frequency */ 36 | 37 | #define SYSTEM_CLOCK (XTAL / 2U) 38 | 39 | /*---------------------------------------------------------------------------- 40 | Exception / Interrupt Vector table 41 | *----------------------------------------------------------------------------*/ 42 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; 43 | 44 | 45 | /*---------------------------------------------------------------------------- 46 | System Core Clock Variable 47 | *----------------------------------------------------------------------------*/ 48 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 49 | 50 | 51 | /*---------------------------------------------------------------------------- 52 | System Core Clock update function 53 | *----------------------------------------------------------------------------*/ 54 | void SystemCoreClockUpdate (void) 55 | { 56 | SystemCoreClock = SYSTEM_CLOCK; 57 | } 58 | 59 | /*---------------------------------------------------------------------------- 60 | System initialization function 61 | *----------------------------------------------------------------------------*/ 62 | void SystemInit (void) 63 | { 64 | 65 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 66 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 67 | #endif 68 | 69 | #if defined (__FPU_USED) && (__FPU_USED == 1U) 70 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 71 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 72 | #endif 73 | 74 | #ifdef UNALIGNED_SUPPORT_DISABLE 75 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 76 | #endif 77 | 78 | SystemCoreClock = SYSTEM_CLOCK; 79 | } 80 | -------------------------------------------------------------------------------- /Device/ARMCM52/Include/system_ARMCM52.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM52.h 3 | * @brief CMSIS Device System Header File for ARMCM52 Device 4 | * @version V1.0.0 5 | * @date 08. April 2024 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2024 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef SYSTEM_ARMCM52_H 26 | #define SYSTEM_ARMCM52_H 27 | 28 | #ifdef __cplusplus 29 | extern "C" { 30 | #endif 31 | 32 | #include 33 | 34 | /** 35 | \brief Exception / Interrupt Handler Function Prototype 36 | */ 37 | typedef void(*VECTOR_TABLE_Type)(void); 38 | 39 | /** 40 | \brief System Clock Frequency (Core Clock) 41 | */ 42 | extern uint32_t SystemCoreClock; 43 | 44 | /** 45 | \brief Setup the microcontroller system. 46 | 47 | Initialize the System and update the SystemCoreClock variable. 48 | */ 49 | extern void SystemInit (void); 50 | 51 | 52 | /** 53 | \brief Update SystemCoreClock variable. 54 | 55 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 56 | */ 57 | extern void SystemCoreClockUpdate (void); 58 | 59 | #ifdef __cplusplus 60 | } 61 | #endif 62 | 63 | #endif /* SYSTEM_ARMCM52_H */ 64 | -------------------------------------------------------------------------------- /Device/ARMCM52/Source/system_ARMCM52.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM52.c 3 | * @brief CMSIS Device System Source File for ARMCM52 Device 4 | * @version V1.0.0 5 | * @date 08. April 2024 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2024 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined (ARMCM52) 26 | #include "ARMCM52.h" 27 | #else 28 | #error device not specified! 29 | #endif 30 | 31 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 32 | #include "partition_ARMCM52.h" 33 | #endif 34 | 35 | /*---------------------------------------------------------------------------- 36 | Define clocks 37 | *----------------------------------------------------------------------------*/ 38 | #define XTAL ( 5000000UL) /* Oscillator frequency */ 39 | 40 | #define SYSTEM_CLOCK (5U * XTAL) 41 | 42 | 43 | /*---------------------------------------------------------------------------- 44 | Exception / Interrupt Vector table 45 | *----------------------------------------------------------------------------*/ 46 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[496]; 47 | 48 | 49 | /*---------------------------------------------------------------------------- 50 | System Core Clock Variable 51 | *----------------------------------------------------------------------------*/ 52 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 53 | 54 | 55 | /*---------------------------------------------------------------------------- 56 | System Core Clock update function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemCoreClockUpdate (void) 59 | { 60 | SystemCoreClock = SYSTEM_CLOCK; 61 | } 62 | 63 | /*---------------------------------------------------------------------------- 64 | System initialization function 65 | *----------------------------------------------------------------------------*/ 66 | void SystemInit (void) 67 | { 68 | 69 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 70 | SCB->VTOR = (uint32_t)(&__VECTOR_TABLE[0]); 71 | #endif 72 | 73 | #if (defined (__FPU_USED) && (__FPU_USED == 1U)) || \ 74 | (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0U)) 75 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 76 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 77 | #endif 78 | 79 | #ifdef UNALIGNED_SUPPORT_DISABLE 80 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 81 | #endif 82 | 83 | /* Enable Loop and branch info cache */ 84 | SCB->CCR |= SCB_CCR_LOB_Msk; 85 | __DSB(); 86 | __ISB(); 87 | 88 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 89 | TZ_SAU_Setup(); 90 | #endif 91 | 92 | SystemCoreClock = SYSTEM_CLOCK; 93 | } 94 | -------------------------------------------------------------------------------- /Device/ARMCM55/Include/system_ARMCM55.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM55.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM55 Device 5 | * @version V1.0.1 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2020-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM55_H 27 | #define SYSTEM_ARMCM55_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM55_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM7/Config/ARMCM7_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m7 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_NOINIT __RW_BASE UNINIT __RW_SIZE { 66 | *(.bss.noinit) 67 | } 68 | 69 | RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { 70 | *(+RW +ZI) 71 | } 72 | 73 | #if __HEAP_SIZE > 0 74 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 75 | } 76 | #endif 77 | 78 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 79 | } 80 | } 81 | -------------------------------------------------------------------------------- /Device/ARMCM7/Include/system_ARMCM7.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM7.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMCM7 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMCM7_H 27 | #define SYSTEM_ARMCM7_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMCM7_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMCM7/Source/system_ARMCM7.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM7.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMCM7 Device 5 | * @version V2.0.0 6 | * @date 06. April 2023 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2023 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #if defined (ARMCM7) 27 | #include "ARMCM7.h" 28 | #else 29 | #error device not specified! 30 | #endif 31 | 32 | /*---------------------------------------------------------------------------- 33 | Define clocks 34 | *----------------------------------------------------------------------------*/ 35 | #define XTAL (50000000UL) /* Oscillator frequency */ 36 | 37 | #define SYSTEM_CLOCK (XTAL / 2U) 38 | 39 | /*---------------------------------------------------------------------------- 40 | Exception / Interrupt Vector table 41 | *----------------------------------------------------------------------------*/ 42 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; 43 | 44 | 45 | /*---------------------------------------------------------------------------- 46 | System Core Clock Variable 47 | *----------------------------------------------------------------------------*/ 48 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 49 | 50 | 51 | /*---------------------------------------------------------------------------- 52 | System Core Clock update function 53 | *----------------------------------------------------------------------------*/ 54 | void SystemCoreClockUpdate (void) 55 | { 56 | SystemCoreClock = SYSTEM_CLOCK; 57 | } 58 | 59 | /*---------------------------------------------------------------------------- 60 | System initialization function 61 | *----------------------------------------------------------------------------*/ 62 | void SystemInit (void) 63 | { 64 | 65 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 66 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 67 | #endif 68 | 69 | #if defined (__FPU_USED) && (__FPU_USED == 1U) 70 | SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ 71 | (3U << 11U*2U) ); /* enable CP11 Full Access */ 72 | #endif 73 | 74 | #ifdef UNALIGNED_SUPPORT_DISABLE 75 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 76 | #endif 77 | 78 | SystemCoreClock = SYSTEM_CLOCK; 79 | } 80 | -------------------------------------------------------------------------------- /Device/ARMCM85/Include/system_ARMCM85.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMCM85.h 3 | * @brief CMSIS Device System Header File for ARMCM85 Device 4 | * @version V1.0.1 5 | * @date 11. July 2022 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2022 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef SYSTEM_ARMCM85_H 26 | #define SYSTEM_ARMCM85_H 27 | 28 | #ifdef __cplusplus 29 | extern "C" { 30 | #endif 31 | 32 | #include 33 | 34 | /** 35 | \brief Exception / Interrupt Handler Function Prototype 36 | */ 37 | typedef void(*VECTOR_TABLE_Type)(void); 38 | 39 | /** 40 | \brief System Clock Frequency (Core Clock) 41 | */ 42 | extern uint32_t SystemCoreClock; 43 | 44 | /** 45 | \brief Setup the microcontroller system. 46 | 47 | Initialize the System and update the SystemCoreClock variable. 48 | */ 49 | extern void SystemInit (void); 50 | 51 | 52 | /** 53 | \brief Update SystemCoreClock variable. 54 | 55 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 56 | */ 57 | extern void SystemCoreClockUpdate (void); 58 | 59 | #ifdef __cplusplus 60 | } 61 | #endif 62 | 63 | #endif /* SYSTEM_ARMCM85_H */ 64 | -------------------------------------------------------------------------------- /Device/ARMCR4/Config/ARMCR4_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-r4 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCR4.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCR4/Config/mem_ARMCR4.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file mem_ARMCR4.h 3 | * @brief Memory base and size definitions (used in scatter file) 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __MEM_ARMCR4_H 29 | #define __MEM_ARMCR4_H 30 | 31 | /*---------------------------------------------------------------------------- 32 | User Stack & Heap size definition 33 | *----------------------------------------------------------------------------*/ 34 | /* 35 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 36 | */ 37 | 38 | /*--------------------- ROM Configuration ------------------------------------ 39 | // 40 | // ROM Configuration 41 | // For compatibility with MMU config the sections must be multiple of 1MB 42 | // ROM Base Address <0x0-0xFFFFFFFF:0x100000> 43 | // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 44 | // 45 | *----------------------------------------------------------------------------*/ 46 | #define __ROM_BASE 0x80000000 47 | #define __ROM_SIZE 0x00200000 48 | 49 | /*--------------------- RAM Configuration ----------------------------------- 50 | // RAM Configuration 51 | // For compatibility with MMU config the sections must be multiple of 1MB 52 | // RAM Base Address <0x0-0xFFFFFFFF:0x100000> 53 | // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 54 | // Data Sections 55 | // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 | // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 | // 58 | // Stack / Heap Configuration 59 | // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 | // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 61 | // Exceptional Modes 62 | // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 63 | // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 64 | // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 65 | // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 66 | // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 67 | // 68 | // 69 | // 70 | *----------------------------------------------------------------------------*/ 71 | #define __RAM_BASE 0x80200000 72 | #define __RAM_SIZE 0x00200000 73 | 74 | #define __RW_DATA_SIZE 0x00100000 75 | #define __ZI_DATA_SIZE 0x000F0000 76 | 77 | #define __STACK_SIZE 0x00001000 78 | #define __HEAP_SIZE 0x00008000 79 | 80 | #define __UND_STACK_SIZE 0x00000100 81 | #define __ABT_STACK_SIZE 0x00000100 82 | #define __SVC_STACK_SIZE 0x00000100 83 | #define __IRQ_STACK_SIZE 0x00000100 84 | #define __FIQ_STACK_SIZE 0x00000100 85 | 86 | /*----------------------------------------------------------------------------*/ 87 | 88 | #endif /* __MEM_ARMCR4_H */ 89 | -------------------------------------------------------------------------------- /Device/ARMCR4/Include/system_ARMCR4.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR4.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCR4_H 29 | #define __SYSTEM_ARMCR4_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* __SYSTEM_ARMCR4_H */ 59 | -------------------------------------------------------------------------------- /Device/ARMCR4/Source/system_ARMCR4.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR4.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | } 55 | -------------------------------------------------------------------------------- /Device/ARMCR5/Config/ARMCR5_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-r5 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCR5.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCR5/Config/mem_ARMCR5.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file mem_ARMCR5.h 3 | * @brief Memory base and size definitions (used in scatter file) 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __MEM_ARMCR5_H 29 | #define __MEM_ARMCR5_H 30 | 31 | /*---------------------------------------------------------------------------- 32 | User Stack & Heap size definition 33 | *----------------------------------------------------------------------------*/ 34 | /* 35 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 36 | */ 37 | 38 | /*--------------------- ROM Configuration ------------------------------------ 39 | // 40 | // ROM Configuration 41 | // For compatibility with MMU config the sections must be multiple of 1MB 42 | // ROM Base Address <0x0-0xFFFFFFFF:0x100000> 43 | // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 44 | // 45 | *----------------------------------------------------------------------------*/ 46 | #define __ROM_BASE 0x80000000 47 | #define __ROM_SIZE 0x00200000 48 | 49 | /*--------------------- RAM Configuration ----------------------------------- 50 | // RAM Configuration 51 | // For compatibility with MMU config the sections must be multiple of 1MB 52 | // RAM Base Address <0x0-0xFFFFFFFF:0x100000> 53 | // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 54 | // Data Sections 55 | // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 | // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 | // 58 | // Stack / Heap Configuration 59 | // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 | // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 61 | // Exceptional Modes 62 | // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 63 | // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 64 | // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 65 | // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 66 | // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 67 | // 68 | // 69 | // 70 | *----------------------------------------------------------------------------*/ 71 | #define __RAM_BASE 0x80200000 72 | #define __RAM_SIZE 0x00200000 73 | 74 | #define __RW_DATA_SIZE 0x00100000 75 | #define __ZI_DATA_SIZE 0x000F0000 76 | 77 | #define __STACK_SIZE 0x00001000 78 | #define __HEAP_SIZE 0x00008000 79 | 80 | #define __UND_STACK_SIZE 0x00000100 81 | #define __ABT_STACK_SIZE 0x00000100 82 | #define __SVC_STACK_SIZE 0x00000100 83 | #define __IRQ_STACK_SIZE 0x00000100 84 | #define __FIQ_STACK_SIZE 0x00000100 85 | 86 | /*----------------------------------------------------------------------------*/ 87 | 88 | #endif /* __MEM_ARMCR5_H */ 89 | -------------------------------------------------------------------------------- /Device/ARMCR5/Include/system_ARMCR5.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR5.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCR5_H 29 | #define __SYSTEM_ARMCR5_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* __SYSTEM_ARMCR5_H */ 59 | -------------------------------------------------------------------------------- /Device/ARMCR5/Source/system_ARMCR5.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR5.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | } 55 | -------------------------------------------------------------------------------- /Device/ARMCR7/Config/ARMCR7_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-r7 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCR7.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCR7/Config/mem_ARMCR7.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file mem_ARMCR7.h 3 | * @brief Memory base and size definitions (used in scatter file) 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __MEM_ARMCR7_H 29 | #define __MEM_ARMCR7_H 30 | 31 | /*---------------------------------------------------------------------------- 32 | User Stack & Heap size definition 33 | *----------------------------------------------------------------------------*/ 34 | /* 35 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 36 | */ 37 | 38 | /*--------------------- ROM Configuration ------------------------------------ 39 | // 40 | // ROM Configuration 41 | // For compatibility with MMU config the sections must be multiple of 1MB 42 | // ROM Base Address <0x0-0xFFFFFFFF:0x100000> 43 | // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 44 | // 45 | *----------------------------------------------------------------------------*/ 46 | #define __ROM_BASE 0x80000000 47 | #define __ROM_SIZE 0x00200000 48 | 49 | /*--------------------- RAM Configuration ----------------------------------- 50 | // RAM Configuration 51 | // For compatibility with MMU config the sections must be multiple of 1MB 52 | // RAM Base Address <0x0-0xFFFFFFFF:0x100000> 53 | // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 54 | // Data Sections 55 | // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 | // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 | // 58 | // Stack / Heap Configuration 59 | // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 | // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 61 | // Exceptional Modes 62 | // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 63 | // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 64 | // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 65 | // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 66 | // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 67 | // 68 | // 69 | // 70 | *----------------------------------------------------------------------------*/ 71 | #define __RAM_BASE 0x80200000 72 | #define __RAM_SIZE 0x00200000 73 | 74 | #define __RW_DATA_SIZE 0x00100000 75 | #define __ZI_DATA_SIZE 0x000F0000 76 | 77 | #define __STACK_SIZE 0x00001000 78 | #define __HEAP_SIZE 0x00008000 79 | 80 | #define __UND_STACK_SIZE 0x00000100 81 | #define __ABT_STACK_SIZE 0x00000100 82 | #define __SVC_STACK_SIZE 0x00000100 83 | #define __IRQ_STACK_SIZE 0x00000100 84 | #define __FIQ_STACK_SIZE 0x00000100 85 | 86 | /*----------------------------------------------------------------------------*/ 87 | 88 | #endif /* __MEM_ARMCR7_H */ 89 | -------------------------------------------------------------------------------- /Device/ARMCR7/Include/system_ARMCR7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR7.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCR7_H 29 | #define __SYSTEM_ARMCR7_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* __SYSTEM_ARMCR7_H */ 59 | -------------------------------------------------------------------------------- /Device/ARMCR7/Source/system_ARMCR7.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR7.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | } 55 | -------------------------------------------------------------------------------- /Device/ARMCR8/Config/ARMCR8_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-r8 -xc 2 | ;************************************************** 3 | ; Copyright (c) 2024 ARM Ltd. All rights reserved. 4 | ;************************************************** 5 | 6 | ; Scatter-file for RTX Example on Versatile Express 7 | 8 | ; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map. 9 | 10 | ; This platform has 2GB SDRAM starting at 0x80000000. 11 | 12 | #include "mem_ARMCR8.h" 13 | 14 | SDRAM __ROM_BASE __ROM_SIZE ; load region size_region 15 | { 16 | VECTORS __ROM_BASE __ROM_SIZE ; load address = execution address 17 | { 18 | * (RESET, +FIRST) ; Vector table and other startup code 19 | * (InRoot$$Sections) ; All (library) code that must be in a root region 20 | * (+RO-CODE) ; Application RO code (.text) 21 | * (+RO-DATA) ; Application RO data (.constdata) 22 | } 23 | 24 | RW_DATA __RAM_BASE __RW_DATA_SIZE 25 | { * (+RW) } ; Application RW data (.data) 26 | 27 | ZI_DATA (__RAM_BASE+ 28 | __RW_DATA_SIZE) __ZI_DATA_SIZE 29 | { * (+ZI) } ; Application ZI data (.bss) 30 | 31 | ARM_LIB_HEAP (__RAM_BASE 32 | +__RW_DATA_SIZE 33 | +__ZI_DATA_SIZE) EMPTY __HEAP_SIZE ; Heap region growing up 34 | { } 35 | 36 | ARM_LIB_STACK (__RAM_BASE 37 | +__RAM_SIZE 38 | -__FIQ_STACK_SIZE 39 | -__IRQ_STACK_SIZE 40 | -__SVC_STACK_SIZE 41 | -__ABT_STACK_SIZE 42 | -__UND_STACK_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down 43 | { } 44 | 45 | UND_STACK (__RAM_BASE 46 | +__RAM_SIZE 47 | -__FIQ_STACK_SIZE 48 | -__IRQ_STACK_SIZE 49 | -__SVC_STACK_SIZE 50 | -__ABT_STACK_SIZE) EMPTY -__UND_STACK_SIZE ; UND mode stack 51 | { } 52 | 53 | ABT_STACK (__RAM_BASE 54 | +__RAM_SIZE 55 | -__FIQ_STACK_SIZE 56 | -__IRQ_STACK_SIZE 57 | -__SVC_STACK_SIZE) EMPTY -__ABT_STACK_SIZE ; ABT mode stack 58 | { } 59 | 60 | SVC_STACK (__RAM_BASE 61 | +__RAM_SIZE 62 | -__FIQ_STACK_SIZE 63 | -__IRQ_STACK_SIZE) EMPTY -__SVC_STACK_SIZE ; SVC mode stack 64 | { } 65 | 66 | IRQ_STACK (__RAM_BASE 67 | +__RAM_SIZE 68 | -__FIQ_STACK_SIZE) EMPTY -__IRQ_STACK_SIZE ; IRQ mode stack 69 | { } 70 | 71 | FIQ_STACK (__RAM_BASE 72 | +__RAM_SIZE) EMPTY -__FIQ_STACK_SIZE ; FIQ mode stack 73 | { } 74 | 75 | TTB __TTB_BASE EMPTY __TTB_SIZE ; Level-1 Translation Table for MMU 76 | { } 77 | } 78 | -------------------------------------------------------------------------------- /Device/ARMCR8/Config/mem_ARMCR8.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file mem_ARMCR8.h 3 | * @brief Memory base and size definitions (used in scatter file) 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __MEM_ARMCR8_H 29 | #define __MEM_ARMCR8_H 30 | 31 | /*---------------------------------------------------------------------------- 32 | User Stack & Heap size definition 33 | *----------------------------------------------------------------------------*/ 34 | /* 35 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ 36 | */ 37 | 38 | /*--------------------- ROM Configuration ------------------------------------ 39 | // 40 | // ROM Configuration 41 | // For compatibility with MMU config the sections must be multiple of 1MB 42 | // ROM Base Address <0x0-0xFFFFFFFF:0x100000> 43 | // ROM Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 44 | // 45 | *----------------------------------------------------------------------------*/ 46 | #define __ROM_BASE 0x80000000 47 | #define __ROM_SIZE 0x00200000 48 | 49 | /*--------------------- RAM Configuration ----------------------------------- 50 | // RAM Configuration 51 | // For compatibility with MMU config the sections must be multiple of 1MB 52 | // RAM Base Address <0x0-0xFFFFFFFF:0x100000> 53 | // RAM Total Size (in Bytes) <0x0-0xFFFFFFFF:0x100000> 54 | // Data Sections 55 | // RW_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 56 | // ZI_DATA Size (in Bytes) <0x0-0xFFFFFFFF:8> 57 | // 58 | // Stack / Heap Configuration 59 | // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 60 | // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 61 | // Exceptional Modes 62 | // UND Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 63 | // ABT Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 64 | // SVC Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 65 | // IRQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 66 | // FIQ Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 67 | // 68 | // 69 | // 70 | *----------------------------------------------------------------------------*/ 71 | #define __RAM_BASE 0x80200000 72 | #define __RAM_SIZE 0x00200000 73 | 74 | #define __RW_DATA_SIZE 0x00100000 75 | #define __ZI_DATA_SIZE 0x000F0000 76 | 77 | #define __STACK_SIZE 0x00001000 78 | #define __HEAP_SIZE 0x00008000 79 | 80 | #define __UND_STACK_SIZE 0x00000100 81 | #define __ABT_STACK_SIZE 0x00000100 82 | #define __SVC_STACK_SIZE 0x00000100 83 | #define __IRQ_STACK_SIZE 0x00000100 84 | #define __FIQ_STACK_SIZE 0x00000100 85 | 86 | /*----------------------------------------------------------------------------*/ 87 | 88 | #endif /* __MEM_ARMCR8_H */ 89 | -------------------------------------------------------------------------------- /Device/ARMCR8/Include/system_ARMCR8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR8.h 3 | * @brief CMSIS Device System Header File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #ifndef __SYSTEM_ARMCR8_H 29 | #define __SYSTEM_ARMCR8_H 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | #include 36 | 37 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 38 | 39 | /** 40 | \brief Setup the microcontroller system. 41 | 42 | Initialize the System and update the SystemCoreClock variable. 43 | */ 44 | extern void SystemInit (void); 45 | 46 | 47 | /** 48 | \brief Update SystemCoreClock variable. 49 | 50 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 51 | */ 52 | extern void SystemCoreClockUpdate (void); 53 | 54 | #ifdef __cplusplus 55 | } 56 | #endif 57 | 58 | #endif /* __SYSTEM_ARMCR8_H */ 59 | -------------------------------------------------------------------------------- /Device/ARMCR8/Source/system_ARMCR8.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file system_ARMCR8.c 3 | * @brief CMSIS Device System Source File for Arm Cortex-A9 Device Series 4 | * @version V1.0.0 5 | * @date 31. March 2024 6 | * 7 | * @note 8 | * 9 | ******************************************************************************/ 10 | /* 11 | * Copyright (c) 2024 Arm Limited. All rights reserved. 12 | * 13 | * SPDX-License-Identifier: Apache-2.0 14 | * 15 | * Licensed under the Apache License, Version 2.0 (the License); you may 16 | * not use this file except in compliance with the License. 17 | * You may obtain a copy of the License at 18 | * 19 | * www.apache.org/licenses/LICENSE-2.0 20 | * 21 | * Unless required by applicable law or agreed to in writing, software 22 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 23 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 | * See the License for the specific language governing permissions and 25 | * limitations under the License. 26 | */ 27 | 28 | #include "RTE_Components.h" 29 | #include CMSIS_device_header 30 | #include "irq_ctrl.h" 31 | 32 | #define SYSTEM_CLOCK 12000000U 33 | 34 | /*---------------------------------------------------------------------------- 35 | System Core Clock Variable 36 | *----------------------------------------------------------------------------*/ 37 | uint32_t SystemCoreClock = SYSTEM_CLOCK; 38 | 39 | /*---------------------------------------------------------------------------- 40 | System Core Clock update function 41 | *----------------------------------------------------------------------------*/ 42 | void SystemCoreClockUpdate (void) 43 | { 44 | SystemCoreClock = SYSTEM_CLOCK; 45 | } 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Initialization 49 | *----------------------------------------------------------------------------*/ 50 | void SystemInit (void) 51 | { 52 | /* do not use global variables because this function is called before 53 | reaching pre-main. RW section may be overwritten afterwards. */ 54 | } 55 | -------------------------------------------------------------------------------- /Device/ARMSC000/Config/ARMSC000_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=sc000 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_RAM __RW_BASE __RW_SIZE { ; RW data 66 | .ANY (+RW +ZI) 67 | } 68 | 69 | #if __HEAP_SIZE > 0 70 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 71 | } 72 | #endif 73 | 74 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /Device/ARMSC000/Include/system_ARMSC000.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMSC000.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMSC000 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMSC000_H 27 | #define SYSTEM_ARMSC000_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | /** 46 | \brief Setup the microcontroller system. 47 | 48 | Initialize the System and update the SystemCoreClock variable. 49 | */ 50 | extern void SystemInit (void); 51 | 52 | 53 | /** 54 | \brief Update SystemCoreClock variable. 55 | 56 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 57 | */ 58 | extern void SystemCoreClockUpdate (void); 59 | 60 | #ifdef __cplusplus 61 | } 62 | #endif 63 | 64 | #endif /* SYSTEM_ARMSC000_H */ 65 | -------------------------------------------------------------------------------- /Device/ARMSC000/Source/system_ARMSC000.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMSC000.c 3 | * @brief CMSIS Device System Source File for 4 | * for ARMSC000 Device 5 | * @version V1.0.0 6 | * @date 09. July 2018 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMSC000.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL (50000000UL) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (XTAL / 2U) 34 | 35 | 36 | /*---------------------------------------------------------------------------- 37 | System Core Clock Variable 38 | *----------------------------------------------------------------------------*/ 39 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 40 | 41 | 42 | /*---------------------------------------------------------------------------- 43 | System Core Clock update function 44 | *----------------------------------------------------------------------------*/ 45 | void SystemCoreClockUpdate (void) 46 | { 47 | SystemCoreClock = SYSTEM_CLOCK; 48 | } 49 | 50 | /*---------------------------------------------------------------------------- 51 | System initialization function 52 | *----------------------------------------------------------------------------*/ 53 | void SystemInit (void) 54 | { 55 | SystemCoreClock = SYSTEM_CLOCK; 56 | } 57 | -------------------------------------------------------------------------------- /Device/ARMSC300/Config/ARMSC300_ac6.sct: -------------------------------------------------------------------------------- 1 | #! armclang -E --target=arm-arm-none-eabi -mcpu=sc300 -xc 2 | ; command above MUST be in first line (no comment above!) 3 | 4 | /* 5 | ;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- 6 | */ 7 | 8 | /*--------------------- Flash Configuration ---------------------------------- 9 | ; Flash Configuration 10 | ; Flash Base Address <0x0-0xFFFFFFFF:8> 11 | ; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> 12 | ; 13 | *----------------------------------------------------------------------------*/ 14 | #define __ROM_BASE 0x00000000 15 | #define __ROM_SIZE 0x00080000 16 | 17 | /*--------------------- Embedded RAM Configuration --------------------------- 18 | ; RAM Configuration 19 | ; RAM Base Address <0x0-0xFFFFFFFF:8> 20 | ; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> 21 | ; 22 | *----------------------------------------------------------------------------*/ 23 | #define __RAM_BASE 0x20000000 24 | #define __RAM_SIZE 0x00040000 25 | 26 | /*--------------------- Stack / Heap Configuration --------------------------- 27 | ; Stack / Heap Configuration 28 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 29 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 30 | ; 31 | *----------------------------------------------------------------------------*/ 32 | #define __STACK_SIZE 0x00000200 33 | #define __HEAP_SIZE 0x00000C00 34 | 35 | /* 36 | ;------------- <<< end of configuration section >>> --------------------------- 37 | */ 38 | 39 | 40 | /*---------------------------------------------------------------------------- 41 | User Stack & Heap boundary definition 42 | *----------------------------------------------------------------------------*/ 43 | #define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ 44 | #define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | Scatter File Definitions definition 49 | *----------------------------------------------------------------------------*/ 50 | #define __RO_BASE __ROM_BASE 51 | #define __RO_SIZE __ROM_SIZE 52 | 53 | #define __RW_BASE __RAM_BASE 54 | #define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) 55 | 56 | 57 | LR_ROM __RO_BASE __RO_SIZE { ; load region size_region 58 | ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address 59 | *.o (RESET, +First) 60 | *(InRoot$$Sections) 61 | .ANY (+RO) 62 | .ANY (+XO) 63 | } 64 | 65 | RW_RAM __RW_BASE __RW_SIZE { ; RW data 66 | .ANY (+RW +ZI) 67 | } 68 | 69 | #if __HEAP_SIZE > 0 70 | ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap 71 | } 72 | #endif 73 | 74 | ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack 75 | } 76 | } 77 | -------------------------------------------------------------------------------- /Device/ARMSC300/Include/system_ARMSC300.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMSC300.h 3 | * @brief CMSIS Device System Header File for 4 | * ARMSC300 Device 5 | * @version V5.3.3 6 | * @date 11. July 2022 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2022 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #ifndef SYSTEM_ARMSC300_H 27 | #define SYSTEM_ARMSC300_H 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | #include 34 | 35 | /** 36 | \brief Exception / Interrupt Handler Function Prototype 37 | */ 38 | typedef void(*VECTOR_TABLE_Type)(void); 39 | 40 | /** 41 | \brief System Clock Frequency (Core Clock) 42 | */ 43 | extern uint32_t SystemCoreClock; 44 | 45 | 46 | /** 47 | \brief Setup the microcontroller system. 48 | 49 | Initialize the System and update the SystemCoreClock variable. 50 | */ 51 | extern void SystemInit (void); 52 | 53 | 54 | /** 55 | \brief Update SystemCoreClock variable. 56 | 57 | Updates the SystemCoreClock with current core Clock retrieved from cpu registers. 58 | */ 59 | extern void SystemCoreClockUpdate (void); 60 | 61 | #ifdef __cplusplus 62 | } 63 | #endif 64 | 65 | #endif /* SYSTEM_ARMSC300_H */ 66 | -------------------------------------------------------------------------------- /Device/ARMSC300/Source/system_ARMSC300.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file system_ARMSC300.c 3 | * @brief CMSIS Device System Source File for 4 | * ARMSC300 Device 5 | * @version V1.0.1 6 | * @date 15. November 2019 7 | ******************************************************************************/ 8 | /* 9 | * Copyright (c) 2009-2019 Arm Limited. All rights reserved. 10 | * 11 | * SPDX-License-Identifier: Apache-2.0 12 | * 13 | * Licensed under the Apache License, Version 2.0 (the License); you may 14 | * not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at 16 | * 17 | * www.apache.org/licenses/LICENSE-2.0 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | */ 25 | 26 | #include "ARMSC300.h" 27 | 28 | /*---------------------------------------------------------------------------- 29 | Define clocks 30 | *----------------------------------------------------------------------------*/ 31 | #define XTAL (50000000UL) /* Oscillator frequency */ 32 | 33 | #define SYSTEM_CLOCK (XTAL / 2U) 34 | 35 | /*---------------------------------------------------------------------------- 36 | Exception / Interrupt Vector table 37 | *----------------------------------------------------------------------------*/ 38 | extern const VECTOR_TABLE_Type __VECTOR_TABLE[240]; 39 | 40 | 41 | /*---------------------------------------------------------------------------- 42 | System Core Clock Variable 43 | *----------------------------------------------------------------------------*/ 44 | uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ 45 | 46 | 47 | /*---------------------------------------------------------------------------- 48 | System Core Clock update function 49 | *----------------------------------------------------------------------------*/ 50 | void SystemCoreClockUpdate (void) 51 | { 52 | SystemCoreClock = SYSTEM_CLOCK; 53 | } 54 | 55 | /*---------------------------------------------------------------------------- 56 | System initialization function 57 | *----------------------------------------------------------------------------*/ 58 | void SystemInit (void) 59 | { 60 | 61 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) 62 | SCB->VTOR = (uint32_t) &(__VECTOR_TABLE[0]); 63 | #endif 64 | 65 | #ifdef UNALIGNED_SUPPORT_DISABLE 66 | SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; 67 | #endif 68 | 69 | SystemCoreClock = SYSTEM_CLOCK; 70 | } 71 | -------------------------------------------------------------------------------- /Device/Template/Flash/Abstract.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ARM-software/Cortex_DFP/36d0d3b118ab8493865044551d05248a5fe53427/Device/Template/Flash/Abstract.txt -------------------------------------------------------------------------------- /Device/Template/Flash/FlashDev.c: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file FlashDev.c 3 | * @brief Flash Device Description for New Device Flash 4 | * @version V1.0.0 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2010-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #include "FlashOS.h" // FlashOS Structures 26 | 27 | 28 | struct FlashDevice const FlashDevice = { 29 | FLASH_DRV_VERS, // Driver Version, do not modify! 30 | "New Device 256kB Flash", // Device Name 31 | ONCHIP, // Device Type 32 | 0x00000000, // Device Start Address 33 | 0x00040000, // Device Size in Bytes (256kB) 34 | 1024, // Programming Page Size 35 | 0, // Reserved, must be 0 36 | 0xFF, // Initial Content of Erased Memory 37 | 100, // Program Page Timeout 100 mSec 38 | 3000, // Erase Sector Timeout 3000 mSec 39 | 40 | // Specify Size and Address of Sectors 41 | 0x002000, 0x000000, // Sector Size 8kB (8 Sectors) 42 | 0x010000, 0x010000, // Sector Size 64kB (2 Sectors) 43 | 0x002000, 0x030000, // Sector Size 8kB (8 Sectors) 44 | SECTOR_END 45 | }; 46 | -------------------------------------------------------------------------------- /Device/Template/Flash/FlashOS.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file FlashOS.h 3 | * @brief Data structures and entries Functions 4 | * @version V1.0.0 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2010-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #define VERS 1 // Interface Version 1.01 26 | 27 | #define UNKNOWN 0 // Unknown 28 | #define ONCHIP 1 // On-chip Flash Memory 29 | #define EXT8BIT 2 // External Flash Device on 8-bit Bus 30 | #define EXT16BIT 3 // External Flash Device on 16-bit Bus 31 | #define EXT32BIT 4 // External Flash Device on 32-bit Bus 32 | #define EXTSPI 5 // External Flash Device on SPI 33 | 34 | #define SECTOR_NUM 512 // Max Number of Sector Items 35 | #define PAGE_MAX 65536 // Max Page Size for Programming 36 | 37 | struct FlashSectors { 38 | unsigned long szSector; // Sector Size in Bytes 39 | unsigned long AddrSector; // Address of Sector 40 | }; 41 | 42 | #define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF 43 | 44 | struct FlashDevice { 45 | unsigned short Vers; // Version Number and Architecture 46 | char DevName[128]; // Device Name and Description 47 | unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... 48 | unsigned long DevAdr; // Default Device Start Address 49 | unsigned long szDev; // Total Size of Device 50 | unsigned long szPage; // Programming Page Size 51 | unsigned long Res; // Reserved for future Extension 52 | unsigned char valEmpty; // Content of Erased Memory 53 | 54 | unsigned long toProg; // Time Out of Program Page Function 55 | unsigned long toErase; // Time Out of Erase Sector Function 56 | 57 | struct FlashSectors sectors[SECTOR_NUM]; 58 | }; 59 | 60 | #define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify! 61 | 62 | // Flash Programming Functions (Called by FlashOS) 63 | extern int Init (unsigned long adr, // Initialize Flash 64 | unsigned long clk, 65 | unsigned long fnc); 66 | extern int UnInit (unsigned long fnc); // De-initialize Flash 67 | extern int BlankCheck (unsigned long adr, // Blank Check 68 | unsigned long sz, 69 | unsigned char pat); 70 | extern int EraseChip (void); // Erase complete Device 71 | extern int EraseSector (unsigned long adr); // Erase Sector Function 72 | extern int ProgramPage (unsigned long adr, // Program Page Function 73 | unsigned long sz, 74 | unsigned char *buf); 75 | extern unsigned long Verify (unsigned long adr, // Verify Function 76 | unsigned long sz, 77 | unsigned char *buf); 78 | -------------------------------------------------------------------------------- /Device/Template/Flash/Target.lin: -------------------------------------------------------------------------------- 1 | ; Linker Control File (scatter-loading) 2 | ; 3 | 4 | PRG 0 PI ; Programming Functions 5 | { 6 | PrgCode +0 ; Code 7 | { 8 | * (+RO) 9 | } 10 | PrgData +0 ; Data 11 | { 12 | * (+RW,+ZI) 13 | } 14 | } 15 | 16 | DSCR +0 ; Device Description 17 | { 18 | DevDscr +0 19 | { 20 | FlashDev.o 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /gen_pack.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | # Version: 3.0 3 | # Date: 2023-11-06 4 | # This bash script generates a CMSIS Software Pack: 5 | # 6 | 7 | set -o pipefail 8 | 9 | # Set version of gen pack library 10 | # For available versions see https://github.com/Open-CMSIS-Pack/gen-pack/tags. 11 | # Use the tag name without the prefix "v", e.g., 0.7.0 12 | REQUIRED_GEN_PACK_LIB="0.11.1" 13 | 14 | # Set default command line arguments 15 | DEFAULT_ARGS=(-c "v") 16 | 17 | # Pack warehouse directory - destination 18 | # Default: ./output 19 | # 20 | # PACK_OUTPUT=./output 21 | 22 | # Temporary pack build directory, 23 | # Default: ./build 24 | # 25 | # PACK_BUILD=./build 26 | 27 | # Specify directory names to be added to pack base directory 28 | # An empty list defaults to all folders next to this script. 29 | # Default: empty (all folders) 30 | # 31 | PACK_DIRS=" 32 | Device 33 | SVD 34 | " 35 | 36 | # Specify file names to be added to pack base directory 37 | # Default: empty 38 | # 39 | PACK_BASE_FILES=" 40 | LICENSE 41 | " 42 | 43 | # Specify file names to be deleted from pack build directory 44 | # Default: empty 45 | # 46 | # PACK_DELETE_FILES=" 47 | # 48 | # " 49 | 50 | # Specify patches to be applied 51 | # Default: empty 52 | # 53 | # PACK_PATCH_FILES=" 54 | # 55 | # " 56 | 57 | # Specify addition argument to packchk 58 | # Default: empty 59 | # 60 | # PACKCHK_ARGS=() 61 | 62 | # Specify additional dependencies for packchk 63 | # Default: empty 64 | # 65 | PACKCHK_DEPS=" " 66 | 67 | # Optional: restrict fallback modes for changelog generation 68 | # Default: full 69 | # Values: 70 | # - full Tag annotations, release descriptions, or commit messages (in order) 71 | # - release Tag annotations, or release descriptions (in order) 72 | # - tag Tag annotations only 73 | # 74 | # PACK_CHANGELOG_MODE="" 75 | 76 | # 77 | # custom pre-processing steps 78 | # 79 | # usage: preprocess 80 | # The build folder 81 | # 82 | function preprocess() { 83 | # add custom steps here to be executed 84 | # before populating the pack build folder 85 | return 0 86 | } 87 | 88 | # 89 | # custom post-processing steps 90 | # 91 | # usage: postprocess 92 | # The build folder 93 | # 94 | function postprocess() { 95 | # add custom steps here to be executed 96 | # after populating the pack build folder 97 | # but before archiving the pack into output folder 98 | return 0 99 | } 100 | 101 | ############ DO NOT EDIT BELOW ########### 102 | 103 | # Set GEN_PACK_LIB_PATH to use a specific gen-pack library root 104 | # ... instead of bootstrap based on REQUIRED_GEN_PACK_LIB 105 | if [[ -f "${GEN_PACK_LIB_PATH}/gen-pack" ]]; then 106 | . "${GEN_PACK_LIB}/gen-pack" 107 | else 108 | . <(curl -sL "https://raw.githubusercontent.com/Open-CMSIS-Pack/gen-pack/main/bootstrap") 109 | fi 110 | 111 | gen_pack "${DEFAULT_ARGS[@]}" "$@" 112 | 113 | exit 0 114 | --------------------------------------------------------------------------------