├── .gitignore ├── README.md └── sv_design_verification_v20-3 ├── .class_setup ├── .revDates ├── .testMaster └── test.sv ├── .testscript ├── COPYRIGHT.TXT ├── README.TXT ├── lab02-reg ├── register.sv ├── register_test.sv └── run.f ├── lab03-mux ├── run.f ├── scale_mux.sv └── scale_mux_test.sv ├── lab04-count ├── counter.sv ├── counter_test.sv └── run.f ├── lab05-ctrl ├── control.sv ├── control_test.sv ├── response.pat ├── run.f ├── stimulus.pat └── typedefs.sv ├── lab06-alu ├── alu.sv ├── alu_test.sv ├── run.f └── typedefs.sv ├── lab07-mem ├── mem.sv ├── mem_test.sv ├── run.f └── top.sv ├── lab08-intf ├── mem.sv ├── mem_intf.sv ├── mem_test.sv ├── run.f └── top.sv ├── lab09-cpu ├── CPUtest1.dat ├── CPUtest2.dat ├── CPUtest3.dat ├── cpu.sv ├── cpu_test.sv └── mem.sv ├── lab10-cb ├── flipflop.sv ├── flipflop_test.sv └── run.f ├── lab11-memrnd ├── files │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ └── top.sv ├── mem.sv ├── mem_intf.sv ├── mem_test.sv ├── run.f └── top.sv ├── lab12-countclass ├── counter.sv └── run.f ├── lab14-memclass ├── mem.sv ├── mem_intf.sv ├── mem_test.sv ├── run.f └── top.sv ├── lab17-alucov └── files │ ├── alu.sv │ ├── alu_test.sv │ └── typedefs.sv ├── lab19-svamux ├── mux.sv └── mux_test.sv ├── lab20-svaseq └── seqtest.sv ├── lab21-simpledpi ├── math.sv ├── stdlibs.c └── stdlibs_compile ├── lab22-mailbox ├── ex_trans_pkg.sv ├── mailbox_consumer_m.sv ├── mailbox_if.sv ├── mailbox_producer_m.sv └── mailbox_top_m.sv ├── lab23-semaphore └── semaphore_m.sv ├── lab24-event └── event_m_1.sv ├── setup.bash ├── solutions ├── lab02-reg │ ├── register.sv │ ├── register_test.sv │ └── runlab2 ├── lab03-mux │ ├── runlab3 │ ├── scale_mux.sv │ └── scale_mux_test.sv ├── lab04-count │ ├── counter.sv │ ├── counter_test.sv │ └── runlab4 ├── lab05-ctrl │ ├── control.sv │ ├── control_test.sv │ ├── response.pat │ ├── runlab5 │ ├── stimulus.pat │ └── typedefs.sv ├── lab06-alu │ ├── alu.sv │ ├── alu_test.sv │ ├── runlab6 │ └── typedefs.sv ├── lab07-mem │ ├── mem.sv │ ├── mem_test.sv │ ├── runlab7 │ └── top.sv ├── lab08-intf │ ├── a_interface │ │ ├── mem.sv │ │ ├── mem_intf.sv │ │ ├── mem_test.sv │ │ ├── runlab8 │ │ └── top.sv │ ├── b_clkport │ │ ├── mem.sv │ │ ├── mem_intf.sv │ │ ├── mem_test.sv │ │ ├── runlab8 │ │ └── top.sv │ ├── c_modport │ │ ├── mem.sv │ │ ├── mem_intf.sv │ │ ├── mem_test.sv │ │ ├── runlab8 │ │ └── top.sv │ └── d_methods │ │ ├── mem.sv │ │ ├── mem_intf.sv │ │ ├── mem_test.sv │ │ ├── runlab8 │ │ └── top.sv ├── lab09-cpu │ ├── .simvision │ │ ├── dbrowser-bookmarks │ │ ├── schematic-bookmarks │ │ └── source-bookmarks │ ├── CPUtest1.dat │ ├── CPUtest2.dat │ ├── CPUtest3.dat │ ├── alu.sv │ ├── control.sv │ ├── counter.sv │ ├── cpu.sv │ ├── cpu_test.sv │ ├── mem.sv │ ├── register.sv │ ├── runlab9 │ ├── scale_mux.sv │ └── typedefs.sv ├── lab10-cb │ ├── .simvision │ │ ├── dbrowser-bookmarks │ │ ├── schematic-bookmarks │ │ └── source-bookmarks │ ├── flipflop.sv │ ├── flipflop_test.sv │ └── runlab10 ├── lab11-memrnd │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ ├── runlab11 │ └── top.sv ├── lab12-countclass │ ├── 01_simple_class.sv │ ├── 02_constructor.sv │ ├── 03_derived_class.sv │ ├── 04_counter_limits.sv │ ├── 05_roll_over_under.sv │ ├── 06_static_members.sv │ └── 07_aggregate.sv ├── lab13_polymorph │ └── count_polymorph.sv ├── lab14-memclass │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ ├── runlab14 │ └── top.sv ├── lab15-memvif │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ ├── mem_test_multmem.sv │ ├── multmemrunlab13 │ ├── runlab15 │ ├── top.sv │ └── top_multmem.sv ├── lab16-memcov │ ├── .imc.trace │ ├── classcoveragerunlab14 │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ ├── mem_test_class_coverage.sv │ ├── runlab16 │ └── top.sv ├── lab17-alucov │ ├── .imc.trace │ ├── alu.sv │ ├── alu_test.sv │ ├── runlab17 │ └── typedefs.sv ├── lab18-memarr │ ├── mem.sv │ ├── mem_intf.sv │ ├── mem_test.sv │ ├── mem_test_assoc.sv │ ├── mem_test_dynarr.sv │ ├── mem_test_queue.sv │ ├── runassoc │ ├── rundyn │ ├── runqueue │ └── top.sv ├── lab19-svamux │ ├── mux.sv │ ├── mux_asserted1.sv │ ├── mux_asserted2.sv │ └── mux_test.sv ├── lab20-svaseq │ ├── seqtest.sv │ ├── seqtest_asserted1.sv │ └── seqtest_asserted2.sv ├── lab21-simpledpi │ ├── dpi.sv │ ├── math.sv │ ├── stdlibs.c │ └── stdlibs_compile ├── lab22-mailbox │ ├── ex_trans_pkg.sv │ ├── mailbox_consumer_m.sv │ ├── mailbox_if.sv │ ├── mailbox_producer_m.sv │ ├── mailbox_top_m.sv │ └── runlab22 ├── lab23-semaphore │ └── semaphore_m.sv └── lab24-event │ ├── event_m_1a.sv │ └── event_m_1b.sv └── sv_src └── files ├── alu.sv ├── control.sv ├── counter.sv ├── mem.sv ├── register.sv └── scale_mux.sv /.gitignore: -------------------------------------------------------------------------------- 1 | sv_design_verification_v20-3/*/irun* 2 | sv_design_verification_v20-3/*/INCA_libs 3 | sv_design_verification_v20-3/*/.simvision 4 | sv_design_verification_v20-3/*/waves.shm 5 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # System-Verilog-Practice 2 | Repository for system verilog labs from cadence. You should have irun version 15.20-s022 which is a HDL compiler for system verilog(cadence incisive) 3 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/.class_setup: -------------------------------------------------------------------------------- 1 | set filec 2 | 3 | stty erase ^h 4 | 5 | set IUSHOME = /cds/INCISIV111 6 | 7 | set path = ( ${IUSHOME}/tools/bin ${IUSHOME}/tools/systemc/gcc/install/bin $path ) 8 | 9 | setenv LD_LIBRARY_PATH .:${IUSHOME}/tools/lib:${IUSHOME}/tools/systemc/gcc/install/lib:${IUSHOME}/tools/tbsc/lib/gnu 10 | 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/.revDates: -------------------------------------------------------------------------------- 1 | June 25 2013 2 | SystemVerilog Design and Verification - version 20.3 REVISION 2 3 | IUS 11.10-s050 4 | lab09_cpu timing corrections. 5 | ========================================================= 6 | 7 | June 1 2013 8 | SystemVerilog Design and Verification - version 20.3 9 | IUS 11.10-s050 10 | ========================================================= 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/.testMaster/test.sv: -------------------------------------------------------------------------------- 1 | interface intfc; 2 | logic i1, i0, s; // test output to mux input 3 | logic o; // mux output to test input 4 | modport mux_port (output o, input i1, i0, s); 5 | modport tst_port ( input o, output i1, i0, s); 6 | endinterface : intfc 7 | 8 | 9 | module mux (interface ifp); 10 | always_comb 11 | unique case (ifp.s) 12 | 1'b0 : ifp.o = ifp.i0; 13 | 1'b1 : ifp.o = ifp.i1; 14 | default ifp.o = 1'bx; 15 | endcase 16 | MUX_ASSERT: assert property (@(ifp.o) ifp.o==ifp.s?ifp.i1:ifp.i0); 17 | endmodule : mux 18 | 19 | 20 | program test (interface ifp, input bit clk); 21 | 22 | class randclass; 23 | randc logic [2:0] randvar; 24 | endclass : randclass 25 | 26 | randclass r1 = new; 27 | 28 | default clocking c1 @(posedge clk); 29 | default input #1step output negedge; 30 | input o=ifp.o; output i1=ifp.i1,i0=ifp.i0,s=ifp.s; 31 | endclocking : c1 32 | 33 | function void check (input logic e); 34 | if (ifp.o !== e) 35 | begin 36 | $display("o is %b and should be %b", ifp.o, e); 37 | $display("TEST FAILED"); 38 | $finish; 39 | end 40 | endfunction : check 41 | 42 | initial 43 | begin 44 | for (int unsigned i=1;i<=8;++i) 45 | begin 46 | int ok; 47 | assert (r1.randomize()); 48 | {ifp.i1,ifp.i0,ifp.s} <= r1.randvar; 49 | ##1 check(ifp.s?ifp.i1:ifp.i0); 50 | end 51 | $display("TEST PASSED"); 52 | $finish; 53 | end 54 | 55 | endprogram : test 56 | 57 | 58 | module top; 59 | bit clk=0; 60 | intfc if1(); 61 | mux mx1(.ifp(if1.mux_port)); 62 | test tb1(.ifp(if1.tst_port), .clk); 63 | always #10 clk = ~clk; 64 | endmodule : top 65 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/COPYRIGHT.TXT: -------------------------------------------------------------------------------- 1 | Copyright 2005-2013 Cadence Design Systems, Inc. All rights reserved. 2 | 3 | This work may not be copied, modified, re-published, uploaded, executed, or 4 | distributed in any way, in any medium, whether in whole or in part, without 5 | prior written permission from Cadence Design Systems, Inc. 6 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/README.TXT: -------------------------------------------------------------------------------- 1 | This is the README file for: 2 | 3 | SystemVerilog Design and Verification - version 20.3 REVISION 2 4 | 5 | For a class at a customer site: 6 | - Before you run any Cadence software, verify your system patch level with 7 | "checkSysConf INCISIV11.1" and install any missing required patches. 8 | - After installing the course, source the .class_setup script in 9 | this directory. This shell script sets the path variables to find executables 10 | and libraries. Modify this script as needed for your platform and shells. 11 | 12 | The software products and versions required for this course are: 13 | 14 | -> 29651 : Incisive Enterprise Simulator - XL : versions GREATER THAN 09.20-p007 15 | 16 | This database has been tested only with version 11.10-s050 on these operating 17 | systems: 18 | Linux RH EE 5.0 19 | 20 | The lab database is not tested on any other platform or tool version. 21 | 22 | UNIX users can test the database with the C-shell script: 23 | 24 | .testscript 25 | 26 | The test script tests for the following licenses: 27 | Incisive Unified Simulator 28 | 29 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab02-reg/register.sv: -------------------------------------------------------------------------------- 1 | module register(output logic [7:0]out, input logic [7:0]data, input logic clk, input logic rst_, input logic enable); 2 | timeunit 1ns; 3 | timeprecision 100ps; 4 | 5 | always_ff@(posedge clk iff (enable == 1) or negedge rst_) begin 6 | if(rst_ == 0) 7 | out <= 8'b0; 8 | else 9 | out <= data ; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab02-reg/register_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : register_test.sv 5 | // Title : Register Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the register testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module register_test; 14 | timeunit 1ns; 15 | timeprecision 100ps; 16 | 17 | logic [7:0] out ; 18 | logic [7:0] data ; 19 | logic enable ; 20 | logic rst_ = 1'b1; 21 | logic clk = 1'b1; 22 | 23 | `define PERIOD 10 24 | 25 | always 26 | #(`PERIOD/2) clk = ~clk; 27 | 28 | // INSTANCE register 29 | register r1 (.enable(enable), .clk(clk), .out(out), .data(data), .rst_(rst_)); 30 | 31 | // Monitor Results 32 | initial 33 | begin 34 | $timeformat ( -9, 1, " ns", 9 ); 35 | $monitor ( "time=%t enable=%b rst_=%b data=%h out=%h", 36 | $time, enable, rst_, data, out ); 37 | #(`PERIOD * 99) 38 | $display ( "REGISTER TEST TIMEOUT" ); 39 | $finish; 40 | end 41 | 42 | // Verify Results 43 | task expect_test (input [7:0] expects) ; 44 | if ( out !== expects ) 45 | begin 46 | $display ( "out=%b, should be %b", out, expects ); 47 | $display ( "REGISTER TEST FAILED" ); 48 | $finish; 49 | end 50 | endtask 51 | 52 | initial 53 | begin 54 | @(negedge clk) 55 | { rst_, enable, data } = 10'b1_X_XXXXXXXX; @(negedge clk) expect_test ( 8'hXX ); 56 | { rst_, enable, data } = 10'b0_X_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 57 | { rst_, enable, data } = 10'b1_0_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 58 | { rst_, enable, data } = 10'b1_1_10101010; @(negedge clk) expect_test ( 8'hAA ); 59 | { rst_, enable, data } = 10'b1_0_01010101; @(negedge clk) expect_test ( 8'hAA ); 60 | { rst_, enable, data } = 10'b0_X_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 61 | { rst_, enable, data } = 10'b1_0_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 62 | { rst_, enable, data } = 10'b1_1_01010101; @(negedge clk) expect_test ( 8'h55 ); 63 | { rst_, enable, data } = 10'b1_0_10101010; @(negedge clk) expect_test ( 8'h55 ); 64 | $display ( "REGISTER TEST PASSED" ); 65 | $finish; 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab02-reg/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab01 3 | //------------------------------------------------ 4 | 5 | register.sv // compile src file 6 | register_test.sv // compile top level module 7 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab03-mux/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab03 3 | //------------------------------------------------ 4 | 5 | scale_mux.sv // compile src file 6 | scale_mux_test.sv // compile top level module 7 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab03-mux/scale_mux.sv: -------------------------------------------------------------------------------- 1 | `timescale 1ns/100ps 2 | 3 | module scale_mux #(parameter WIDTH=1)(input in_a, input in_b, input sel_a, output out); 4 | logic [WIDTH-1:0]in_a; 5 | logic [WIDTH-1:0]in_b; 6 | logic sel_a; 7 | logic [WIDTH-1:0]out; 8 | 9 | always_comb begin 10 | unique casex(sel_a) 11 | 1'b1 : out = in_a; 12 | 1'b0 : out = in_b; 13 | default: out = 'bx; 14 | endcase 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab03-mux/scale_mux_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : scale_mux_test.sv 5 | // Title : MUX Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module scale_mux_test; 14 | 15 | timeunit 1ns ; 16 | timeprecision 100ps ; 17 | 18 | localparam WIDTH = 8 ; 19 | 20 | logic [WIDTH-1:0] out; // mux output 21 | logic [WIDTH-1:0] in_a; // mux_test data_a 22 | logic [WIDTH-1:0] in_b; // mux_test data_b 23 | logic sel_a; // mux_test select a 24 | 25 | // Instantiate mux 26 | scale_mux #(WIDTH) mux8 (.out(out), .in_a(in_a), .in_b(in_b), .sel_a(sel_a)); 27 | 28 | // Monitor Results 29 | initial 30 | begin 31 | $timeformat ( -9, 0, "ns", 3 ) ; 32 | $monitor ( "%t in_a=%h in_b=%h sel_a=%h out=%h", 33 | $time, in_a, in_b, sel_a, out ) ; 34 | end 35 | 36 | // Verify Results 37 | task xpect (input [WIDTH-1:0] expects) ; 38 | if ( out !== expects ) 39 | begin 40 | $display ( "out is %b and should be %b", out, expects ) ; 41 | $display ( "MUX TEST FAILED" ); 42 | $finish ; 43 | end 44 | endtask 45 | 46 | // Apply Stimulus 47 | initial 48 | begin 49 | in_a='0; in_b='0; sel_a=0; #1ns xpect('0); 50 | in_a='0; in_b='0; sel_a=1; #1ns xpect('0); 51 | in_a='0; in_b='1; sel_a=0; #1ns xpect('1); 52 | in_a='0; in_b='1; sel_a=1; #1ns xpect('0); 53 | in_a='1; in_b='0; sel_a=0; #1ns xpect('0); 54 | in_a='1; in_b='0; sel_a=1; #1ns xpect('1); 55 | in_a='1; in_b='1; sel_a=0; #1ns xpect('1); 56 | in_a='1; in_b='1; sel_a=1; #1ns xpect('1); 57 | $display ( "MUX TEST PASSED" ) ; 58 | $finish(0) ; 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab04-count/counter.sv: -------------------------------------------------------------------------------- 1 | timeunit 1ns; 2 | timeprecision 100ps; 3 | 4 | 5 | module counter(input data, input load, input enable, input clk, input rst_, output count); 6 | 7 | logic load; 8 | logic [4:0]data; 9 | logic enable; 10 | logic clk; 11 | logic rst_; 12 | logic [4:0]count; 13 | 14 | always_ff @ (posedge clk iff rst_ == 1'b1 or negedge rst_) begin 15 | if(rst_ == 0) begin 16 | count = 0; 17 | end 18 | else if(load == 1'b1) begin 19 | count = data; 20 | end 21 | else if(enable == 1'b1) begin 22 | count = count + 1; 23 | end 24 | else begin 25 | count = count; 26 | end 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab04-count/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab04 3 | //------------------------------------------------ 4 | 5 | counter.sv // compile src file 6 | counter_test.sv // compile top level module 7 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab05-ctrl/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab04 3 | //------------------------------------------------ 4 | 5 | typedefs.sv 6 | control.sv // compile src file 7 | control_test.sv // compile top level module 8 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab05-ctrl/stimulus.pat: -------------------------------------------------------------------------------- 1 | //zero_opcode 2 | 0_000 3 | 0_001 4 | 0_010 5 | 0_011 6 | 0_100 7 | 0_101 8 | 0_110 9 | 0_111 10 | 1_000 11 | 1_001 12 | 1_010 13 | 1_011 14 | 1_100 15 | 1_101 16 | 1_110 17 | 1_111 18 | 0_000 19 | 0_001 20 | 0_010 21 | 0_011 22 | 0_100 23 | 0_101 24 | 0_110 25 | 0_111 26 | 1_000 27 | 1_001 28 | 1_010 29 | 1_011 30 | 1_100 31 | 1_101 32 | 1_110 33 | 1_111 34 | 0_000 35 | 0_001 36 | 0_010 37 | 0_011 38 | 0_100 39 | 0_101 40 | 0_110 41 | 0_111 42 | 1_000 43 | 1_001 44 | 1_010 45 | 1_011 46 | 1_100 47 | 1_101 48 | 1_110 49 | 1_111 50 | 0_000 51 | 0_001 52 | 0_010 53 | 0_011 54 | 0_100 55 | 0_101 56 | 0_110 57 | 0_111 58 | 1_000 59 | 1_001 60 | 1_010 61 | 1_011 62 | 1_100 63 | 1_101 64 | 1_110 65 | 1_111 66 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab05-ctrl/typedefs.sv: -------------------------------------------------------------------------------- 1 | package typedefs; 2 | typedef enum logic [2:0] 3 | { 4 | HLT = 3'b000, 5 | SKZ = 3'b001, 6 | ADD = 3'b010, 7 | AND = 3'b011, 8 | XOR = 3'b100, 9 | LDA = 3'b101, 10 | STO = 3'b110, 11 | JMP = 3'b111 12 | } opcode_t; 13 | 14 | typedef enum bit[2:0] 15 | { 16 | INST_ADDR = 3'b000, 17 | INST_FETCH = 3'b001, 18 | INST_LOAD = 3'b010, 19 | IDLE = 3'b011, 20 | OP_ADDR = 3'b100, 21 | OP_FETCH = 3'b101, 22 | ALU_OP = 3'b110, 23 | STORE = 3'b111 24 | } state_t; 25 | endpackage: typedefs 26 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab06-alu/alu.sv: -------------------------------------------------------------------------------- 1 | // Importing the typedef 2 | import typedefs::*; 3 | 4 | module alu ( 5 | input logic [7:0] accum, // Accumulator 6 | input logic [7:0] data, // Data 7 | input opcode_t opcode, // Opcode 8 | input clk, // Clock 9 | output logic [7:0] out, // Output of the ALU 10 | output logic zero // Zero signal 11 | ); 12 | 13 | // SystemVerilog: time units and time precision specification 14 | timeunit 1ns; 15 | timeprecision 100ps; 16 | 17 | // Block to define the zero value based on the accum value 18 | always_comb begin 19 | if(accum == 0) begin 20 | zero = 1; 21 | end 22 | else begin 23 | zero = 0; 24 | end 25 | 26 | end 27 | 28 | // Block to define the out value based on the accum, data and opcode 29 | always_ff @(negedge clk) begin 30 | unique case (opcode) 31 | HLT: out = accum; 32 | SKZ: out = accum; 33 | ADD: out = data + accum; 34 | AND: out = data & accum; 35 | XOR: out = data ^ accum; 36 | LDA: out = data; 37 | STO: out = accum; 38 | JMP: out = accum; 39 | default: out = 'x; 40 | endcase 41 | end 42 | 43 | endmodule -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab06-alu/alu_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu_test.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // package with opcode_t declaration 14 | import typedefs::*; 15 | 16 | module alu_test; 17 | // SystemVerilog: time unit and time precision specification 18 | timeunit 1ns; 19 | timeprecision 100ps; 20 | 21 | // SystemVerilog: logic and enumeration and user-defined data types 22 | logic [7:0] accum, data, out; 23 | logic zero; 24 | 25 | opcode_t opcode = HLT; 26 | 27 | // ---- clock generator code begin------ 28 | `define PERIOD 10 29 | logic clk = 1'b1; 30 | 31 | always 32 | #(`PERIOD/2)clk = ~clk; 33 | 34 | // ---- clock generator code end------ 35 | 36 | alu alu1 (.out(out), .zero(zero), .clk(clk), .accum(accum), .data(data), .opcode(opcode)); 37 | 38 | // Verify Response 39 | task checkit (input [8:0] expects ) ; 40 | begin 41 | $display ( "%t opcode=%s data=%h accum=%h | zero=%b out=%h", 42 | $time, opcode.name(), data, accum, zero, out); 43 | if ({zero, out} !== expects ) 44 | begin 45 | $display ( "zero:%b out:%b s/b:%b_%b", zero, out, 46 | expects[8], expects[7:0] ); 47 | $display ( "ALU TEST FAILED" ); 48 | $finish; 49 | end 50 | end 51 | endtask 52 | 53 | // Apply Stimulus 54 | initial 55 | begin 56 | @(posedge clk) 57 | { opcode, data, accum } = 19'h0_37_DA; @(posedge clk) checkit('h0_da); 58 | { opcode, data, accum } = 19'h1_37_DA; @(posedge clk) checkit('h0_da); 59 | { opcode, data, accum } = 19'h2_37_DA; @(posedge clk) checkit('h0_11); 60 | { opcode, data, accum } = 19'h3_37_DA; @(posedge clk) checkit('h0_12); 61 | { opcode, data, accum } = 19'h4_37_DA; @(posedge clk) checkit('h0_ed); 62 | { opcode, data, accum } = 19'h5_37_DA; @(posedge clk) checkit('h0_37); 63 | { opcode, data, accum } = 19'h6_37_DA; @(posedge clk) checkit('h0_da); 64 | { opcode, data, accum } = 19'h7_37_00; @(posedge clk) checkit('h1_00); 65 | { opcode, data, accum } = 19'h2_07_12; @(posedge clk) checkit('h0_19); 66 | { opcode, data, accum } = 19'h3_1F_35; @(posedge clk) checkit('h0_15); 67 | { opcode, data, accum } = 19'h4_1E_1D; @(posedge clk) checkit('h0_03); 68 | { opcode, data, accum } = 19'h5_72_00; @(posedge clk) checkit('h1_72); 69 | { opcode, data, accum } = 19'h6_00_10; @(posedge clk) checkit('h0_10); 70 | $display ( "ALU TEST PASSED" ); 71 | $finish; 72 | end 73 | 74 | initial 75 | begin 76 | $timeformat ( -9, 1, " ns", 9 ); 77 | // SystemVerilog: enhanced literal notation 78 | #2000ns 79 | $display ( "ALU TEST TIMEOUT" ); 80 | $finish; 81 | end 82 | endmodule 83 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab06-alu/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab06 3 | //------------------------------------------------ 4 | 5 | typedefs.sv 6 | alu.sv // compile src file 7 | alu_test.sv // compile top level module 8 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab06-alu/typedefs.sv: -------------------------------------------------------------------------------- 1 | package typedefs; 2 | typedef enum logic [2:0] 3 | { 4 | HLT = 3'b000, 5 | SKZ = 3'b001, 6 | ADD = 3'b010, 7 | AND = 3'b011, 8 | XOR = 3'b100, 9 | LDA = 3'b101, 10 | STO = 3'b110, 11 | JMP = 3'b111 12 | } opcode_t; 13 | 14 | typedef enum bit[2:0] 15 | { 16 | INST_ADDR = 3'b000, 17 | INST_FETCH = 3'b001, 18 | INST_LOAD = 3'b010, 19 | IDLE = 3'b011, 20 | OP_ADDR = 3'b100, 21 | OP_FETCH = 3'b101, 22 | ALU_OP = 3'b110, 23 | STORE = 3'b111 24 | } state_t; 25 | endpackage: typedefs 26 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab07-mem/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | input clk, 22 | input read, 23 | input write, 24 | input logic [4:0] addr , 25 | input logic [7:0] data_in , 26 | output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge clk) 36 | if (write && !read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[addr] <= data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) 42 | data_out <= memory[addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab07-mem/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab07 3 | //------------------------------------------------ 4 | 5 | mem.sv // compile src file 6 | mem_test.sv // compile top level module 7 | top.sv // top file 8 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab07-mem/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top module for Memory labs 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory labs 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | bit clk; 22 | wire read; 23 | wire write; 24 | wire [4:0] addr; 25 | 26 | wire [7:0] data_out; // data_from_mem 27 | wire [7:0] data_in; // data_to_mem 28 | 29 | // SYSTEMVERILOG:: implicit .* port connections 30 | mem_test test (.*); 31 | 32 | // SYSTEMVERILOG:: implicit .name port connections 33 | mem memory ( .clk, .read, .write, .addr, 34 | .data_in, .data_out 35 | ); 36 | 37 | always #5 clk = ~clk; 38 | endmodule 39 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab08-intf/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_inft.design mem_inf 22 | // input read, 23 | // input write, 24 | // input logic [4:0] addr , 25 | // input logic [7:0] data_in , 26 | // output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge mem_inf.clk) 36 | if (mem_inf.write && !mem_inf.read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[mem_inf.addr] <= mem_inf.data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge mem_inf.clk iff ((mem_inf.read == '1)&&(mem_inf.write == '0)) ) 42 | mem_inf.data_out <= memory[mem_inf.addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab08-intf/mem_intf.sv: -------------------------------------------------------------------------------- 1 | timeunit 1ns; 2 | timeprecision 1ns; 3 | 4 | interface mem_inft(input bit clk); 5 | logic read; // Read signal to memory 6 | logic write; // Write signal to memory 7 | logic [4:0] addr; // Address being accessed 8 | logic [7:0] data_in; // Data to memory 9 | logic [7:0] data_out; // Data from memory 10 | 11 | // Module ports for the test bench 12 | modport test(output read, write, addr, data_in, input data_out, clk, import write_mem, import read_mem); 13 | 14 | // Module ports for the memory design 15 | modport design(input read, write, addr, data_in, clk, output data_out); 16 | 17 | // SYSTEMVERILOG: default task input argument values 18 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug = 0); 19 | @(negedge clk); 20 | write <= 1; 21 | read <= 0; 22 | addr <= waddr; 23 | data_in <= wdata; 24 | @(negedge clk); 25 | write <= 0; 26 | if (debug == 1) 27 | $display("Write - Address:%d Data:%h", waddr, wdata); 28 | endtask 29 | 30 | // SYSTEMVERILOG: default task input argument values 31 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug = 0); 32 | @(negedge clk); 33 | write <= 0; 34 | read <= 1; 35 | addr <= raddr; 36 | @(negedge clk); 37 | read <= 0; 38 | rdata = data_out; 39 | if (debug == 1) 40 | $display("Read - Address:%d Data:%h", raddr, rdata); 41 | endtask 42 | 43 | endinterface : mem_inft 44 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab08-intf/mem_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_test.sv 5 | // Title : Memory Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module mem_test ( 14 | mem_inft.test mem_inf 15 | // output logic read, 16 | // output logic write, 17 | // output logic [4:0] addr, 18 | // output logic [7:0] data_in, // data TO memory 19 | // input wire [7:0] data_out // data FROM memory 20 | ); 21 | // SYSTEMVERILOG: timeunit and timeprecision specification 22 | timeunit 1ns; 23 | timeprecision 1ns; 24 | 25 | // SYSTEMVERILOG: new data types - bit ,logic 26 | bit debug = 1; 27 | logic [7:0] rdata; // stores data read from memory for checking 28 | 29 | // Monitor Results 30 | initial begin 31 | $timeformat ( -9, 0, " ns", 9 ); 32 | // SYSTEMVERILOG: Time Literals 33 | #40000ns $display ( "MEMORY TEST TIMEOUT" ); 34 | $finish; 35 | end 36 | 37 | initial 38 | begin: memtest 39 | int error_status; 40 | 41 | $display("Clear Memory Test"); 42 | // SYSTEMVERILOG: enhanced for loop 43 | for (int i = 0; i< 32; i++) 44 | mem_inf.write_mem (i, 0, debug); 45 | for (int i = 0; i<32; i++) 46 | begin 47 | mem_inf.read_mem (i, rdata, debug); 48 | // check each memory location for data = 'h00 49 | error_status = checkit (i, rdata, 8'h00); 50 | end 51 | // SYSTEMVERILOG: void function 52 | printstatus(error_status); 53 | 54 | $display("Data = Address Test"); 55 | // SYSTEMVERILOG: enhanced for loop 56 | for (int i = 0; i< 32; i++) 57 | mem_inf.write_mem (i, i, debug); 58 | for (int i = 0; i<32; i++) 59 | begin 60 | mem_inf.read_mem (i, rdata, debug); 61 | // check each memory location for data = address 62 | error_status = checkit (i, rdata, i); 63 | end 64 | // SYSTEMVERILOG: void function 65 | printstatus(error_status); 66 | 67 | $finish; 68 | end 69 | 70 | function int checkit (input [4:0] address, 71 | input [7:0] actual, expected); 72 | static int error_status; // static variable 73 | if (actual !== expected) begin 74 | $display("ERROR: Address:%h Data:%h Expected:%h", 75 | address, actual, expected); 76 | // SYSTEMVERILOG: post-increment 77 | error_status++; 78 | end 79 | // SYSTEMVERILOG: function return 80 | return (error_status); 81 | endfunction: checkit 82 | 83 | // SYSTEMVERILOG: void function 84 | function void printstatus(input int status); 85 | if (status == 0) 86 | $display("Test Passed - No Errors!"); 87 | else 88 | $display("Test Failed with %d Errors", status); 89 | endfunction 90 | 91 | endmodule 92 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab08-intf/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab08 3 | //------------------------------------------------ 4 | 5 | mem_intf.sv // compile interface file 6 | mem.sv // compile src file 7 | mem_test.sv // compile top level module 8 | top.sv // top file 9 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab08-intf/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top module for Memory labs 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory labs 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | bit clk; 22 | // wire read; 23 | // wire write; 24 | // wire [4:0] addr; 25 | 26 | // wire [7:0] data_out; // data_from_mem 27 | // wire [7:0] data_in; // data_to_mem 28 | 29 | mem_inft mem_inf(clk); 30 | // SYSTEMVERILOG:: implicit .* port connections 31 | mem_test test (.*); 32 | 33 | 34 | // SYSTEMVERILOG:: implicit .name port connections 35 | mem memory ( .mem_inf//.read, .write, .addr, 36 | //.data_in, .data_out 37 | ); 38 | 39 | always #5 clk = ~clk; 40 | endmodule 41 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab09-cpu/CPUtest1.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 1 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This diagnostic program tests the basic instruction set of the VeriRisc 6 | * system. If the system executes each instruction correctly, then it should 7 | * halt when the HLT instruction at address 17(hex) is executed. 8 | * 9 | * If the system halts at any other location, then an instruction did not 10 | * execute properly. Refer to the comments in this file to see which 11 | * instruction failed. 12 | *****************************************************************************/ 13 | 14 | //opcode_operand // addr assembly code 15 | //-------------- // ---- ----------------------------------------------- 16 | @00 111_11110 // 00 BEGIN: JMP TST_JMP 17 | 000_00000 // 01 HLT //JMP did not work at all 18 | 000_00000 // 02 HLT //JMP did not load PC, it skipped 19 | 101_11010 // 03 JMP_OK: LDA DATA_1 20 | 001_00000 // 04 SKZ 21 | 000_00000 // 05 HLT //SKZ or LDA did not work 22 | 101_11011 // 06 LDA DATA_2 23 | 001_00000 // 07 SKZ 24 | 111_01010 // 08 JMP SKZ_OK 25 | 000_00000 // 09 HLT //SKZ or LDA did not work 26 | 110_11100 // 0A SKZ_OK: STO TEMP //store non-zero value in TEMP 27 | 101_11010 // 0B LDA DATA_1 28 | 110_11100 // 0C STO TEMP //store zero value in TEMP 29 | 101_11100 // 0D LDA TEMP 30 | 001_00000 // 0E SKZ //check to see if STO worked 31 | 000_00000 // 0F HLT //STO did not work 32 | 100_11011 // 10 XOR DATA_2 33 | 001_00000 // 11 SKZ //check to see if XOR worked 34 | 111_10100 // 12 JMP XOR_OK 35 | 000_00000 // 13 HLT //XOR did not work at all 36 | 100_11011 // 14 XOR_OK: XOR DATA_2 37 | 001_00000 // 15 SKZ 38 | 000_00000 // 16 HLT //XOR did not switch all bits 39 | 000_00000 // 17 END: HLT //CONGRATULATIONS - TEST1 PASSED! 40 | 111_00000 // 18 JMP BEGIN //run test again 41 | 42 | @1A 00000000 // 1A DATA_1: //constant 00(hex) 43 | 11111111 // 1B DATA_2: //constant FF(hex) 44 | 10101010 // 1C TEMP: //variable - starts with AA(hex) 45 | 46 | @1E 111_00011 // 1E TST_JMP: JMP JMP_OK 47 | 000_00000 // 1F HLT //JMP is broken 48 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab09-cpu/CPUtest2.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 2 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This diagnostic program tests the advanced instruction set of the VeriRisc 6 | * system. If the system executes each instruction correctly, then it should 7 | * halt when the HLT instruction at address 10(hex) is executed. 8 | * 9 | * If the system halts at any other location, then an instruction did not 10 | * execute properly. Refer to the comments in this file to see which 11 | * instruction failed. 12 | * 13 | * WARNING: The CPUtest1 diagnostic program should be completed successfully 14 | * before this test is run. 15 | *****************************************************************************/ 16 | 17 | //opcode_operand // addr assembly code 18 | //-------------- // ---- ----------------------------------------------- 19 | @00 101_11011 // 00 BEGIN: LDA DATA_2 20 | 011_11100 // 01 AND DATA_3 21 | 100_11011 // 02 XOR DATA_2 22 | 001_00000 // 03 SKZ 23 | 000_00000 // 04 HLT //AND doesn't work 24 | 010_11010 // 05 ADD DATA_1 25 | 001_00000 // 06 SKZ 26 | 111_01001 // 07 JMP ADD_OK 27 | 000_00000 // 08 HLT //ADD doesn't work 28 | 100_11100 // 09 XOR DATA_3 29 | 010_11010 // 0A ADD DATA_1 //FF plus 1 makes -1 30 | 110_11101 // 0B STO TEMP 31 | 101_11010 // 0C LDA DATA_1 32 | 010_11101 // 0D ADD TEMP //-1 plus 1 should make zero 33 | 001_00000 // 0E SKZ 34 | 000_00000 // 0F HLT //ADD Doesn't work 35 | 000_00000 // 10 END: HLT //CONGRATULATIONS - TEST2 PASSED! 36 | 111_00000 // 11 JMP BEGIN //run test again 37 | 38 | @1A 00000001 // 1A DATA_1: //constant 1(hex) 39 | 10101010 // 1B DATA_2: //constant AA(hex) 40 | 11111111 // 1C DATA_3: //constant FF(hex) 41 | 00000000 // 1D TEMP: 42 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab09-cpu/CPUtest3.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 3 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This is an actual program that calculates the Fibonacci number sequence 6 | * from 0 to 144. The Fibonacci number sequence is a series of numbers in 7 | * which each number in the sequence is the sum of the preceding two numbers 8 | * (i.e.: 0, 1, 1, 2, 3, 5, 8, 13 ...). This number sequence is often used 9 | * in financial analysis, and can also be found in the patterns of pineapple 10 | * shells and some flower petals. 11 | * 12 | * WARNING: Do not run this program before the CPUtest1 and CPUtest2 diagnostic 13 | * programs have completed successfully. Those who do are asking for 14 | endless heartache. 15 | *****************************************************************************/ 16 | 17 | //opcode_operand // addr assembly code 18 | //-------------- // ---- ---------------------------------------------------- 19 | 111_00011 // 00 JMP LOOP //jump to the address of LOOP 20 | @03 101_11011 // 03 LOOP: LDA FN2 //load value in FN2 into accum 21 | 110_11100 // 04 STO TEMP //store accumulator in TEMP 22 | 010_11010 // 05 ADD FN1 //add value in FN1 to accumulator 23 | 110_11011 // 06 STO FN2 //store result in FN2 24 | 101_11100 // 07 LDA TEMP //load TEMP into the accumulator 25 | 110_11010 // 08 STO FN1 //store accumulator in FN1 26 | 100_11101 // 09 XOR LIMIT //compare accumulator to LIMIT 27 | 001_00000 // 0A SKZ //if accum = 0, skip to DONE 28 | 111_00011 // 0B JMP LOOP //jump to address of LOOP 29 | 000_00000 // 0C DONE: HLT //end of program 30 | 101_11111 // 0D AGAIN: LDA ONE 31 | 110_11010 // 0E STO FN1 32 | 101_11110 // 0F LDA ZERO 33 | 110_11011 // 10 STO FN2 34 | 111_00011 // 11 JMP LOOP //jump to address of LOOP 35 | 36 | @1A 00000001 // 1A FN1: //data storage for 1st Fib. No. 37 | 00000000 // 1B FN2: //data storage for 2nd Fib. No. 38 | 00000000 // 1C TEMP: //temproray data storage 39 | 10010000 // 1D LIMIT: //max value to calculate 144(dec) 40 | 00000000 // 1E ZERO: //constant 0(decimal) 41 | 00000001 // 1F ONE: //constant 1(decimal) 42 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab09-cpu/cpu.sv: -------------------------------------------------------------------------------- 1 | module cpu ( 2 | output logic halt , 3 | output logic load_ir , 4 | input logic clk , 5 | input logic cntrl_clk , 6 | input logic alu_clk , 7 | input logic fetch , 8 | input logic rst_ 9 | ); 10 | //SystemVerilog: timeunit and timeprecision notation 11 | timeunit 1ns; 12 | timeprecision 100ps; 13 | 14 | import typedefs::*; 15 | 16 | logic [7:0] data_out, alu_out, accum, ir_out; 17 | logic [4:0] pc_addr, ir_addr, addr; 18 | opcode_t opcode; 19 | logic load_ac, mem_rd, mem_wr, inc_pc, load_pc, zero; 20 | 21 | //SystemVerilog: .name port connections 22 | register ac ( .out (accum ), 23 | .data (alu_out), 24 | .clk, 25 | .enable (load_ac), 26 | .rst_ 27 | ); 28 | 29 | register ir ( .out (ir_out), 30 | .data(data_out), 31 | .clk, 32 | .enable (load_ir), 33 | .rst_ 34 | ); 35 | 36 | assign opcode = opcode_t'(ir_out[7:5]); 37 | 38 | assign ir_addr = ir_out[4:0]; 39 | 40 | counter pc ( .count (pc_addr), 41 | .data (ir_addr), 42 | .clk (clk), 43 | .load (load_pc), 44 | .enable (inc_pc), 45 | .rst_ 46 | ); 47 | 48 | alu alu1 ( .out (alu_out), 49 | .zero, 50 | .clk (alu_clk), 51 | .accum, 52 | .data(data_out), 53 | .opcode 54 | ); 55 | 56 | scale_mux #5 smx( .out (addr), 57 | .in_a (pc_addr), 58 | .in_b (ir_addr), 59 | .sel_a (fetch) 60 | ); 61 | 62 | mem mem1 ( .clk(~cntrl_clk), 63 | .read (mem_rd), 64 | .write (mem_wr), 65 | .addr , 66 | .data_in(alu_out) , 67 | .data_out(data_out) 68 | ); 69 | 70 | 71 | control cntl ( .load_ac, 72 | .mem_rd, 73 | .mem_wr, 74 | .inc_pc, 75 | .load_pc, 76 | .load_ir, 77 | .halt, 78 | .opcode, 79 | .zero, 80 | .clk(cntrl_clk), 81 | .rst_ 82 | ); 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab09-cpu/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | input clk, 22 | input read, 23 | input write, 24 | input logic [4:0] addr , 25 | input logic [7:0] data_in , 26 | output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge clk) 36 | if (write && !read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[addr] <= data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) 42 | data_out <= memory[addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab10-cb/flipflop.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : flipflop.sv 5 | // Title : Flipflop Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Flipflop module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module flipflop (input logic clk, reset, 14 | input logic [7:0] qin, 15 | output logic [7:0] qout); 16 | timeunit 1ns; 17 | 18 | always @(posedge clk or posedge reset) 19 | if (reset) 20 | qout = '0; 21 | else 22 | qout = qin; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab10-cb/flipflop_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : flipflop_test.sv 5 | // Title : Flipflop Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Flipflop testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module testflop (); 14 | timeunit 1ns; 15 | 16 | logic reset; 17 | logic [7:0] qin,qout; 18 | 19 | // ---- clock generator code begin------ 20 | `define PERIOD 10 21 | logic clk = 1'b1; 22 | 23 | always 24 | #(`PERIOD/2)clk = ~clk; 25 | 26 | // ---- clock generator code end------ 27 | 28 | 29 | flipflop DUV(.*); 30 | 31 | default clocking cb @(posedge clk); 32 | input qout; 33 | output qin, reset; 34 | 35 | default input #1step output #4; 36 | 37 | endclocking 38 | 39 | initial begin 40 | @(cb); 41 | cb.qin <= '0; 42 | cb.reset <= 0; 43 | ##2 cb.reset <=1; 44 | ##3 cb.reset <= 0; 45 | for(int i=0; i < 8; i++) begin 46 | ##1 cb.qin <= i; 47 | end 48 | ##3; 49 | $finish; 50 | end 51 | 52 | endmodule 53 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab10-cb/run.f: -------------------------------------------------------------------------------- 1 | flipflop.sv 2 | flipflop_test.sv 3 | -gui 4 | -access +rwc 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/files/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/files/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug = 0); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h", waddr, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug = 0); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h", raddr, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/files/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_inft.design mem_inf 22 | // input read, 23 | // input write, 24 | // input logic [4:0] addr , 25 | // input logic [7:0] data_in , 26 | // output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 100ps; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge mem_inf.clk) 36 | if (mem_inf.write && !mem_inf.read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[mem_inf.addr] <= mem_inf.data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge mem_inf.clk iff ((mem_inf.read == '1)&&(mem_inf.write == '0)) ) 42 | mem_inf.data_out <= memory[mem_inf.addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/mem_intf.sv: -------------------------------------------------------------------------------- 1 | timeunit 1ns; 2 | timeprecision 100ps; 3 | 4 | interface mem_inft(input bit clk); 5 | logic read; // Read signal to memory 6 | logic write; // Write signal to memory 7 | logic [4:0] addr; // Address being accessed 8 | logic [7:0] data_in; // Data to memory 9 | logic [7:0] data_out; // Data from memory 10 | 11 | // Module ports for the test bench 12 | modport test(output read, write, addr, data_in, input data_out, clk, import write_mem, read_mem); 13 | 14 | // Module ports for the memory design 15 | modport design(input read, write, addr, data_in, clk, output data_out); 16 | 17 | // SYSTEMVERILOG: default task input argument values 18 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug = 0); 19 | @(negedge clk); 20 | write <= 1; 21 | read <= 0; 22 | addr <= waddr; 23 | data_in <= wdata; 24 | @(negedge clk); 25 | write <= 0; 26 | if (debug == 1) 27 | $display("Write - Address:%d Data:%h", waddr, wdata); 28 | endtask 29 | 30 | // SYSTEMVERILOG: default task input argument values 31 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug = 0); 32 | @(negedge clk); 33 | write <= 0; 34 | read <= 1; 35 | addr <= raddr; 36 | @(negedge clk); 37 | read <= 0; 38 | rdata = data_out; 39 | if (debug == 1) 40 | $display("Read - Address:%d Data:%h", raddr, rdata); 41 | endtask 42 | 43 | endinterface : mem_inft 44 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab11 3 | //------------------------------------------------ 4 | 5 | mem_intf.sv // compile interface file 6 | mem.sv // compile src file 7 | mem_test.sv // compile top level module 8 | top.sv // top file 9 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab11-memrnd/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top module for Memory labs 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory labs 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 100ps; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | bit clk; 22 | // wire read; 23 | // wire write; 24 | // wire [4:0] addr; 25 | 26 | // wire [7:0] data_out; // data_from_mem 27 | // wire [7:0] data_in; // data_to_mem 28 | 29 | mem_inft mem_inf(clk); 30 | // SYSTEMVERILOG:: implicit .* port connections 31 | mem_test test (.*); 32 | 33 | 34 | // SYSTEMVERILOG:: implicit .name port connections 35 | mem memory ( .mem_inf//.read, .write, .addr, 36 | //.data_in, .data_out 37 | ); 38 | 39 | always #5 clk = ~clk; 40 | endmodule 41 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab12-countclass/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab13 3 | //------------------------------------------------ 4 | 5 | counter.sv // Compile the design and test file 6 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab14-memclass/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_inft.design mem_inf 22 | // input read, 23 | // input write, 24 | // input logic [4:0] addr , 25 | // input logic [7:0] data_in , 26 | // output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 100ps; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge mem_inf.clk) 36 | if (mem_inf.write && !mem_inf.read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[mem_inf.addr] <= mem_inf.data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge mem_inf.clk iff ((mem_inf.read == '1)&&(mem_inf.write == '0)) ) 42 | mem_inf.data_out <= memory[mem_inf.addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab14-memclass/mem_intf.sv: -------------------------------------------------------------------------------- 1 | timeunit 1ns; 2 | timeprecision 100ps; 3 | 4 | interface mem_inft(input bit clk); 5 | logic read; // Read signal to memory 6 | logic write; // Write signal to memory 7 | logic [4:0] addr; // Address being accessed 8 | logic [7:0] data_in; // Data to memory 9 | logic [7:0] data_out; // Data from memory 10 | 11 | // Module ports for the test bench 12 | modport test(output read, write, addr, data_in, input data_out, clk, import write_mem, read_mem); 13 | 14 | // Module ports for the memory design 15 | modport design(input read, write, addr, data_in, clk, output data_out); 16 | 17 | // SYSTEMVERILOG: default task input argument values 18 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug = 0); 19 | @(negedge clk); 20 | write <= 1; 21 | read <= 0; 22 | addr <= waddr; 23 | data_in <= wdata; 24 | @(negedge clk); 25 | write <= 0; 26 | if (debug == 1) 27 | $display("Write - Address:%d Data:%h", waddr, wdata); 28 | endtask 29 | 30 | // SYSTEMVERILOG: default task input argument values 31 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug = 0); 32 | @(negedge clk); 33 | write <= 0; 34 | read <= 1; 35 | addr <= raddr; 36 | @(negedge clk); 37 | read <= 0; 38 | rdata = data_out; 39 | if (debug == 1) 40 | $display("Read - Address:%d Data:%h", raddr, rdata); 41 | endtask 42 | 43 | endinterface : mem_inft 44 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab14-memclass/run.f: -------------------------------------------------------------------------------- 1 | //----------------------------------------------- 2 | // System Verilog run file for lab14 3 | //------------------------------------------------ 4 | 5 | mem_intf.sv // compile interface file 6 | mem.sv // compile src file 7 | mem_test.sv // compile top level module 8 | top.sv // top file 9 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab14-memclass/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top module for Memory labs 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory labs 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 100ps; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | bit clk; 22 | // wire read; 23 | // wire write; 24 | // wire [4:0] addr; 25 | 26 | // wire [7:0] data_out; // data_from_mem 27 | // wire [7:0] data_in; // data_to_mem 28 | 29 | mem_inft mem_inf(clk); 30 | // SYSTEMVERILOG:: implicit .* port connections 31 | mem_test test (.*); 32 | 33 | 34 | // SYSTEMVERILOG:: implicit .name port connections 35 | mem memory ( .mem_inf//.read, .write, .addr, 36 | //.data_in, .data_out 37 | ); 38 | 39 | always #5 clk = ~clk; 40 | endmodule 41 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab17-alucov/files/alu.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog: import package with opcode_t enum type declaration 14 | import typedefs::*; 15 | module alu ( 16 | output logic [7:0] out , 17 | output logic zero , 18 | input logic clk , 19 | input logic [7:0] accum , 20 | input logic [7:0] data , 21 | input opcode_t opcode 22 | ); 23 | // SystemVerilog: time unit and time precision specification 24 | timeunit 1ns; 25 | timeprecision 100ps; 26 | 27 | // SystemVerilog: unique case synthesis intent specification 28 | always @(negedge clk) 29 | unique case ( opcode ) 30 | ADD : out <= accum + data; 31 | AND : out <= accum & data; 32 | XOR : out <= accum ^ data; 33 | LDA : out <= data; 34 | HLT, 35 | SKZ, 36 | JMP, 37 | STO : out <= accum; 38 | // default : out <= 8'bx; 39 | endcase 40 | 41 | // SystemVerilog: always_comb synthesis intent specification 42 | always_comb 43 | zero = ~(|accum); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab17-alucov/files/typedefs.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : typdefs.sv 5 | // Title : Opcode and state enum types 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the opcode and state type declarations 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | package typedefs; 14 | //SystemVerilog: User-defined data types using enumerations 15 | // CPU Operations 16 | typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 17 | // Control Sequencer States 18 | typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 19 | OP_ADDR, OP_FETCH, ALU_OP, STORE} state_t; 20 | 21 | endpackage : typedefs 22 | 23 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab19-svamux/mux.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux.sv 5 | // Title : MUX module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | `timescale 1 ns / 1 ns 13 | 14 | module mux 15 | ( 16 | input logic clock , 17 | input logic [3:0] ip1 , 18 | input logic [3:0] ip2 , 19 | input logic [3:0] ip3 , 20 | input logic sel1 , 21 | input logic sel2 , 22 | input logic sel3 , 23 | output logic [3:0] mux_op 24 | ) ; 25 | 26 | always @(posedge clock) 27 | if (sel1 == 1) 28 | mux_op <= ip1 ; 29 | else 30 | if (sel2 == 1) 31 | mux_op <= ip2 ; 32 | else 33 | if (sel3 == 1) 34 | mux_op <= ip3 ; 35 | 36 | // assertions go here 37 | //#### edit ### 38 | 39 | 40 | 41 | 42 | //#### end of edit ### 43 | endmodule 44 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/lab19-svamux/mux_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux_test.sv 5 | // Title : MUX testbench 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux testbench 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | `timescale 1 ns / 1 ns 14 | 15 | module t_mux ; 16 | 17 | parameter PERIOD = 10 ; 18 | 19 | logic clock ; 20 | logic [3:0] ip1 ; 21 | logic [3:0] ip2 ; 22 | logic [3:0] ip3 ; 23 | logic [2:0] sel ; 24 | logic [3:0] mux_op ; 25 | 26 | 27 | mux mux1 28 | ( 29 | .clock ( clock ), 30 | .ip1 ( ip1 ), 31 | .ip2 ( ip2 ), 32 | .ip3 ( ip3 ), 33 | .sel1 ( sel[0] ), 34 | .sel2 ( sel[1] ), 35 | .sel3 ( sel[2] ), 36 | .mux_op ( mux_op ) 37 | ) ; 38 | 39 | always 40 | begin 41 | clock <= 0 ; 42 | #(PERIOD/2) ; 43 | clock <= 1 ; 44 | #(PERIOD/2) ; 45 | end 46 | 47 | initial 48 | begin : TEST 49 | @(posedge clock); 50 | #(PERIOD/4); // Keep changes away from clock edges 51 | ip1 <= 4'b0001 ; 52 | ip2 <= 4'b0010 ; 53 | ip3 <= 4'b0100 ; 54 | 55 | $display ("Starting 1st set of test vectors."); 56 | 57 | for (int i=0; i<=2; i++) 58 | begin 59 | sel <= 1< e1 ; 39 | end : EMITTER_1 40 | 41 | /////////////////////////////////////////////////////// 42 | // TO DO PART 1 - REPLACE WITH NON-BLOCKING OPERATOR // 43 | /////////////////////////////////////////////////////// 44 | begin : EMITTER_2 45 | $display ( "%m emitting event e2" ) ; 46 | -> e2 ; 47 | end : EMITTER_2 48 | 49 | ///////////////////////////////////////////////////////////// 50 | // TO DO PART 2 - REPLACE WITH WAIT FOR triggered PROPERTY // 51 | ///////////////////////////////////////////////////////////// 52 | begin : WAITER_2 53 | $display ( "%m waiting event e2" ) ; 54 | @ e2 55 | $display ( "%m received event e2" ) ; 56 | end : WAITER_2 57 | 58 | join_none 59 | #10ns; 60 | disable fork; 61 | $display("TEST COMPLETE"); 62 | $finish(0); 63 | end 64 | 65 | endmodule : event_m 66 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/setup.bash: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | export UVMHOME="/softwares/Linux/cadence/INCISIVE152/tools/methodology/UVM/CDNS-1.1d/sv" 3 | source /softwares/setup/cadence/setup.incisive152.bash 4 | echo Success 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab02-reg/register.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : register.sv 5 | // Title : Register Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the register module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module register ( 14 | // Verilog2001: port and variable declarations in module definition 15 | // SystemVerilog: logic data type 16 | output logic [7:0] out, 17 | input logic [7:0] data , 18 | input clk , 19 | input enable , 20 | input rst_ 21 | ); 22 | // SystemVerilog: time unit and time precision declaration 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | // SystemVerilog: always_ff - sequential behavior intent specification 27 | // SystemVerilog: iff conditional execution 28 | always_ff @(posedge clk iff (enable == 1) or negedge rst_) 29 | if (!rst_) 30 | out <= 0; 31 | else 32 | out <= data; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab02-reg/register_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : register_test.sv 5 | // Title : Register Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the register testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module register_test; 14 | timeunit 1ns; 15 | timeprecision 100ps; 16 | 17 | logic [7:0] out ; 18 | logic [7:0] data ; 19 | logic enable ; 20 | logic rst_ = 1'b1; 21 | logic clk = 1'b1; 22 | 23 | `define PERIOD 10 24 | 25 | always 26 | #(`PERIOD/2) clk = ~clk; 27 | 28 | // INSTANCE register 29 | register r1 (.enable(enable), .clk(clk), .out(out), .data(data), .rst_(rst_)); 30 | 31 | // Monitor Results 32 | initial 33 | begin 34 | $timeformat ( -9, 1, " ns", 9 ); 35 | $monitor ( "time=%t enable=%b rst_=%b data=%h out=%h", 36 | $time, enable, rst_, data, out ); 37 | #(`PERIOD * 99) 38 | $display ( "REGISTER TEST TIMEOUT" ); 39 | $finish; 40 | end 41 | 42 | // Verify Results 43 | task expect_test (input [7:0] expects) ; 44 | if ( out !== expects ) 45 | begin 46 | $display ( "out=%b, should be %b", out, expects ); 47 | $display ( "REGISTER TEST FAILED" ); 48 | $finish; 49 | end 50 | endtask 51 | 52 | initial 53 | begin 54 | @(negedge clk) 55 | { rst_, enable, data } = 10'b1_X_XXXXXXXX; @(negedge clk) expect_test ( 8'hXX ); 56 | { rst_, enable, data } = 10'b0_X_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 57 | { rst_, enable, data } = 10'b1_0_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 58 | { rst_, enable, data } = 10'b1_1_10101010; @(negedge clk) expect_test ( 8'hAA ); 59 | { rst_, enable, data } = 10'b1_0_01010101; @(negedge clk) expect_test ( 8'hAA ); 60 | { rst_, enable, data } = 10'b0_X_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 61 | { rst_, enable, data } = 10'b1_0_XXXXXXXX; @(negedge clk) expect_test ( 8'h00 ); 62 | { rst_, enable, data } = 10'b1_1_01010101; @(negedge clk) expect_test ( 8'h55 ); 63 | { rst_, enable, data } = 10'b1_0_10101010; @(negedge clk) expect_test ( 8'h55 ); 64 | $display ( "REGISTER TEST PASSED" ); 65 | $finish; 66 | end 67 | endmodule 68 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab02-reg/runlab2: -------------------------------------------------------------------------------- 1 | register.sv 2 | register_test.sv 3 | //+gui 4 | +access+rwc 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab03-mux/runlab3: -------------------------------------------------------------------------------- 1 | scale_mux.sv 2 | scale_mux_test.sv 3 | //+gui 4 | +access+rwc 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab03-mux/scale_mux.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : scale_mux.sv 5 | // Title : MUX Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module 9 | // Notes : 10 | // Scalable Mux - Specification: 11 | // when sel_a = 1, out = in_a 12 | // when sel_a = 0, out = in_b 13 | // when sel_a = x, out = x 14 | // 15 | /////////////////////////////////////////////////////////////////////////// 16 | 17 | module scale_mux #(WIDTH = 1) 18 | (output logic [WIDTH-1:0] out, 19 | input logic [WIDTH-1:0] in_a, 20 | input logic [WIDTH-1:0] in_b, 21 | input logic sel_a); 22 | 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | always_comb 27 | unique case (sel_a) 28 | 1'b1: out = in_a; 29 | 1'b0: out = in_b; 30 | default: out = 'x; 31 | endcase 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab03-mux/scale_mux_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : scale_mux_test.sv 5 | // Title : MUX Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module scale_mux_test; 14 | 15 | timeunit 1ns ; 16 | timeprecision 100ps ; 17 | 18 | localparam WIDTH = 8 ; 19 | 20 | logic [WIDTH-1:0] out; // mux output 21 | logic [WIDTH-1:0] in_a; // mux_test data_a 22 | logic [WIDTH-1:0] in_b; // mux_test data_b 23 | logic sel_a; // mux_test select a 24 | 25 | // Instantiate mux 26 | scale_mux #(WIDTH) mux8 (.out(out), .in_a(in_a), .in_b(in_b), .sel_a(sel_a)); 27 | 28 | // Monitor Results 29 | initial 30 | begin 31 | $timeformat ( -9, 0, "ns", 3 ) ; 32 | $monitor ( "%t in_a=%h in_b=%h sel_a=%h out=%h", 33 | $time, in_a, in_b, sel_a, out ) ; 34 | end 35 | 36 | // Verify Results 37 | task xpect (input [WIDTH-1:0] expects) ; 38 | if ( out !== expects ) 39 | begin 40 | $display ( "out is %b and should be %b", out, expects ) ; 41 | $display ( "MUX TEST FAILED" ); 42 | $finish ; 43 | end 44 | endtask 45 | 46 | // Apply Stimulus 47 | initial 48 | begin 49 | in_a='0; in_b='0; sel_a=0; #1ns xpect('0); 50 | in_a='0; in_b='0; sel_a=1; #1ns xpect('0); 51 | in_a='0; in_b='1; sel_a=0; #1ns xpect('1); 52 | in_a='0; in_b='1; sel_a=1; #1ns xpect('0); 53 | in_a='1; in_b='0; sel_a=0; #1ns xpect('0); 54 | in_a='1; in_b='0; sel_a=1; #1ns xpect('1); 55 | in_a='1; in_b='1; sel_a=0; #1ns xpect('1); 56 | in_a='1; in_b='1; sel_a=1; #1ns xpect('1); 57 | $display ( "MUX TEST PASSED" ) ; 58 | $finish(0) ; 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab04-count/counter.sv: -------------------------------------------------------------------------------- 1 | 2 | // Verilog2001: port and variable declarations in module definition 3 | module counter ( 4 | output logic [4:0] count, 5 | input logic [4:0] data , 6 | input clk , 7 | input load , 8 | input enable , 9 | input rst_ 10 | ); 11 | 12 | // SystemVerilog: time unit and time precision declaration 13 | timeunit 1ns; 14 | timeprecision 100ps; 15 | 16 | // SystemVerilog: always_ff 17 | always_ff @(posedge clk or negedge rst_) 18 | if (!rst_) 19 | count <= 0; 20 | else if (load) 21 | count <= data; 22 | else if (enable) 23 | // SystemVerilog: postincrement or assignment operator 24 | count <= count +1; //++; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab04-count/runlab4: -------------------------------------------------------------------------------- 1 | counter.sv 2 | counter_test.sv 3 | // +gui +access+rwc 4 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab05-ctrl/control.sv: -------------------------------------------------------------------------------- 1 | // Controller Module 2 | // SystemVerilog package covered in detail in day2 of the class 3 | import typedefs::*; 4 | 5 | module control ( 6 | output logic load_ac , 7 | output logic mem_rd , 8 | output logic mem_wr , 9 | output logic inc_pc , 10 | output logic load_pc , 11 | output logic load_ir , 12 | output logic halt , 13 | input opcode_t opcode , 14 | input zero , 15 | input clk , 16 | input rst_ 17 | ); 18 | // SystemVerilog: time units and time precision specification 19 | timeunit 1ns; 20 | timeprecision 100ps; 21 | 22 | // SystemVerilog: typedef and enumeration types declared in typedefs package 23 | //typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 24 | //typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 25 | // OP_ADDR, OP_FETCH, ALU_OP, STORE}state_t; 26 | 27 | state_t state; 28 | 29 | logic aluop; 30 | 31 | assign aluop = (opcode inside {ADD, AND, XOR, LDA}); 32 | 33 | always_ff @(posedge clk or negedge rst_) 34 | if (!rst_) 35 | state <= INST_ADDR; 36 | else 37 | state <= state.next(); 38 | 39 | always_comb begin 40 | // default assignments to outputs to avoid latches 41 | {mem_rd, load_ir, halt, inc_pc, load_ac, load_pc, mem_wr} = 7'b000_0000; 42 | unique case (state) 43 | INST_ADDR : ; 44 | INST_FETCH: mem_rd = 1; 45 | INST_LOAD : begin 46 | mem_rd = 1; 47 | load_ir = 1; 48 | end 49 | IDLE : begin 50 | mem_rd = 1; 51 | load_ir = 1; 52 | end 53 | OP_ADDR : begin 54 | inc_pc = 1; 55 | halt = (opcode == HLT); 56 | end 57 | OP_FETCH : mem_rd = aluop; 58 | ALU_OP : begin 59 | load_ac = aluop; 60 | mem_rd = aluop; 61 | inc_pc = ((opcode == SKZ) && zero); 62 | load_pc = ( opcode == JMP); 63 | end 64 | STORE : begin 65 | load_ac = aluop; 66 | mem_rd = aluop; 67 | inc_pc = (opcode == JMP); 68 | load_pc = ( opcode == JMP); 69 | mem_wr = ( opcode == STO); 70 | end 71 | endcase 72 | end 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab05-ctrl/runlab5: -------------------------------------------------------------------------------- 1 | typedefs.sv 2 | control.sv 3 | control_test.sv 4 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab05-ctrl/stimulus.pat: -------------------------------------------------------------------------------- 1 | //zero_opcode 2 | 0_000 3 | 0_001 4 | 0_010 5 | 0_011 6 | 0_100 7 | 0_101 8 | 0_110 9 | 0_111 10 | 1_000 11 | 1_001 12 | 1_010 13 | 1_011 14 | 1_100 15 | 1_101 16 | 1_110 17 | 1_111 18 | 0_000 19 | 0_001 20 | 0_010 21 | 0_011 22 | 0_100 23 | 0_101 24 | 0_110 25 | 0_111 26 | 1_000 27 | 1_001 28 | 1_010 29 | 1_011 30 | 1_100 31 | 1_101 32 | 1_110 33 | 1_111 34 | 0_000 35 | 0_001 36 | 0_010 37 | 0_011 38 | 0_100 39 | 0_101 40 | 0_110 41 | 0_111 42 | 1_000 43 | 1_001 44 | 1_010 45 | 1_011 46 | 1_100 47 | 1_101 48 | 1_110 49 | 1_111 50 | 0_000 51 | 0_001 52 | 0_010 53 | 0_011 54 | 0_100 55 | 0_101 56 | 0_110 57 | 0_111 58 | 1_000 59 | 1_001 60 | 1_010 61 | 1_011 62 | 1_100 63 | 1_101 64 | 1_110 65 | 1_111 66 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab05-ctrl/typedefs.sv: -------------------------------------------------------------------------------- 1 | package typedefs; 2 | //SystemVerilog: User-defined data types using enumerations 3 | // CPU Operations 4 | typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 5 | // Control Sequencer States 6 | typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 7 | OP_ADDR, OP_FETCH, ALU_OP, STORE}state_t; 8 | 9 | endpackage : typedefs 10 | 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab06-alu/alu.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog: import package with opcode_t enum type declaration 14 | import typedefs::*; 15 | module alu ( 16 | output logic [7:0] out , 17 | output logic zero , 18 | input logic clk , 19 | input logic [7:0] accum , 20 | input logic [7:0] data , 21 | input opcode_t opcode 22 | ); 23 | // SystemVerilog: time unit and time precision specification 24 | timeunit 1ns; 25 | timeprecision 100ps; 26 | 27 | // SystemVerilog: unique case synthesis intent specification 28 | always @(negedge clk) 29 | unique case ( opcode ) 30 | ADD : out <= accum + data; 31 | AND : out <= accum & data; 32 | XOR : out <= accum ^ data; 33 | LDA : out <= data; 34 | HLT, 35 | SKZ, 36 | JMP, 37 | STO : out <= accum; 38 | // default : out <= 8'bx; 39 | endcase 40 | 41 | // SystemVerilog: always_comb synthesis intent specification 42 | always_comb 43 | zero = ~(|accum); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab06-alu/alu_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu_test.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // package with opcode_t declaration 14 | import typedefs::*; 15 | 16 | module alu_test; 17 | // SystemVerilog: time unit and time precision specification 18 | timeunit 1ns; 19 | timeprecision 100ps; 20 | 21 | // SystemVerilog: logic and enumeration and user-defined data types 22 | logic [7:0] accum, data, out; 23 | logic zero; 24 | 25 | opcode_t opcode = HLT; 26 | 27 | // ---- clock generator code begin------ 28 | `define PERIOD 10 29 | logic clk = 1'b1; 30 | 31 | always 32 | #(`PERIOD/2)clk = ~clk; 33 | 34 | // ---- clock generator code end------ 35 | 36 | alu alu1 (.out(out), .zero(zero), .clk(clk), .accum(accum), .data(data), .opcode(opcode)); 37 | 38 | // Verify Response 39 | task checkit (input [8:0] expects ) ; 40 | begin 41 | $display ( "%t opcode=%s data=%h accum=%h | zero=%b out=%h", 42 | $time, opcode.name(), data, accum, zero, out); 43 | if ({zero, out} !== expects ) 44 | begin 45 | $display ( "zero:%b out:%b s/b:%b_%b", zero, out, 46 | expects[8], expects[7:0] ); 47 | $display ( "ALU TEST FAILED" ); 48 | $finish; 49 | end 50 | end 51 | endtask 52 | 53 | // Apply Stimulus 54 | initial 55 | begin 56 | @(posedge clk) 57 | { opcode, data, accum } = 19'h0_37_DA; @(posedge clk) checkit('h0_da); 58 | { opcode, data, accum } = 19'h1_37_DA; @(posedge clk) checkit('h0_da); 59 | { opcode, data, accum } = 19'h2_37_DA; @(posedge clk) checkit('h0_11); 60 | { opcode, data, accum } = 19'h3_37_DA; @(posedge clk) checkit('h0_12); 61 | { opcode, data, accum } = 19'h4_37_DA; @(posedge clk) checkit('h0_ed); 62 | { opcode, data, accum } = 19'h5_37_DA; @(posedge clk) checkit('h0_37); 63 | { opcode, data, accum } = 19'h6_37_DA; @(posedge clk) checkit('h0_da); 64 | { opcode, data, accum } = 19'h7_37_00; @(posedge clk) checkit('h1_00); 65 | { opcode, data, accum } = 19'h2_07_12; @(posedge clk) checkit('h0_19); 66 | { opcode, data, accum } = 19'h3_1F_35; @(posedge clk) checkit('h0_15); 67 | { opcode, data, accum } = 19'h4_1E_1D; @(posedge clk) checkit('h0_03); 68 | { opcode, data, accum } = 19'h5_72_00; @(posedge clk) checkit('h1_72); 69 | { opcode, data, accum } = 19'h6_00_10; @(posedge clk) checkit('h0_10); 70 | $display ( "ALU TEST PASSED" ); 71 | $finish; 72 | end 73 | 74 | initial 75 | begin 76 | $timeformat ( -9, 1, " ns", 9 ); 77 | // SystemVerilog: enhanced literal notation 78 | #2000ns 79 | $display ( "ALU TEST TIMEOUT" ); 80 | $finish; 81 | end 82 | endmodule 83 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab06-alu/runlab6: -------------------------------------------------------------------------------- 1 | typedefs.sv 2 | alu.sv 3 | alu_test.sv 4 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab06-alu/typedefs.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : typdefs.sv 5 | // Title : Opcode and state enum types 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the opcode and state type declarations 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | package typedefs; 14 | //SystemVerilog: User-defined data types using enumerations 15 | // CPU Operations 16 | typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 17 | // Control Sequencer States 18 | typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 19 | OP_ADDR, OP_FETCH, ALU_OP, STORE} state_t; 20 | 21 | endpackage : typedefs 22 | 23 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab07-mem/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | input clk, 22 | input read, 23 | input write, 24 | input logic [4:0] addr , 25 | input logic [7:0] data_in , 26 | output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge clk) 36 | if (write && !read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[addr] <= data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) 42 | data_out <= memory[addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab07-mem/runlab7: -------------------------------------------------------------------------------- 1 | mem.sv 2 | mem_test.sv 3 | top.sv 4 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab07-mem/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top module for Memory labs 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory labs 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | bit clk; 22 | wire read; 23 | wire write; 24 | wire [4:0] addr; 25 | 26 | wire [7:0] data_out; // data_from_mem 27 | wire [7:0] data_in; // data_to_mem 28 | 29 | // SYSTEMVERILOG:: implicit .* port connections 30 | mem_test test (.*); 31 | 32 | // SYSTEMVERILOG:: implicit .name port connections 33 | mem memory ( .clk, .read, .write, .addr, 34 | .data_in, .data_out 35 | ); 36 | 37 | always #5 clk = ~clk; 38 | endmodule 39 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/a_interface/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( input logic clk, 21 | mem_intf mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/a_interface/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | interface mem_intf(); 14 | //SYSTEMVERILOG: timeunit and timeprecision notation 15 | timeunit 1ns; 16 | timeprecision 100ps; 17 | 18 | //SYSTEMVERILOG: logic data types 19 | logic [7:0] data_in; 20 | logic [7:0] data_out; 21 | logic [4:0] addr; 22 | logic read; 23 | logic write; 24 | 25 | endinterface : mem_intf 26 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/a_interface/runlab8: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/a_interface/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | logic clk = 0; 22 | 23 | always #5 clk = ~clk; 24 | 25 | // SYSTEMVERILOG: interface instance 26 | mem_intf mbus (); 27 | 28 | mem_test mtest (.clk,.mbus); 29 | 30 | mem m1 ( .clk,.mbus); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/b_clkport/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface and clk port 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/b_clkport/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | endinterface : mem_intf 27 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/b_clkport/runlab8: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/b_clkport/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface and clk port 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | logic clk = 0; 22 | 23 | always #5 clk = ~clk; 24 | 25 | // SYSTEMVERILOG: interface instance 26 | mem_intf mbus (clk); 27 | 28 | mem_test mtest (.mbus); 29 | 30 | mem m1 (.mbus); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/c_modport/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port and modports 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | ////////////////////////////////////////////////////////////////////////// 19 | module mem ( 20 | mem_intf.mem mbus 21 | ); 22 | // SYSTEMVERILOG: timeunit and timeprecision specification 23 | timeunit 1ns; 24 | timeprecision 1ns; 25 | 26 | // SYSTEMVERILOG: logic data type 27 | logic [7:0] memory [0:31] ; 28 | 29 | always @(posedge mbus.clk) 30 | if (mbus.write && !mbus.read) 31 | // SYSTEMVERILOG: time literals 32 | #1 memory[mbus.addr] <= mbus.data_in; 33 | 34 | // SYSTEMVERILOG: always_ff and iff event control 35 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 36 | mbus.data_out <= memory[mbus.addr]; 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/c_modport/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clok port and modports 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | interface mem_intf(input logic clk); 14 | //SYSTEMVERILOG: timeunit and timeprecision notation 15 | timeunit 1ns; 16 | timeprecision 100ps; 17 | 18 | //SYSTEMVERILOG: logic data types 19 | logic [7:0] data_in; 20 | logic [7:0] data_out; 21 | logic [4:0] addr; 22 | logic read; 23 | logic write; 24 | 25 | // SYSTEMVERILOG: modports in an interface 26 | modport tb ( input data_out, clk, 27 | output data_in, addr, read, write ); 28 | modport mem ( output data_out, 29 | input clk, data_in, addr, read, write ); 30 | 31 | endinterface : mem_intf 32 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/c_modport/runlab8: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/c_modport/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port and modport 9 | // Notes : 10 | // Memory Lab - top-level 11 | // A top-level module which instantiates the memory and mem_test modules 12 | // 13 | /////////////////////////////////////////////////////////////////////////// 14 | 15 | module top; 16 | // SYSTEMVERILOG: timeunit and timeprecision specification 17 | timeunit 1ns; 18 | timeprecision 1ns; 19 | 20 | // SYSTEMVERILOG: logic and bit data types 21 | logic clk = 0; 22 | 23 | always #5 clk = ~clk; 24 | 25 | // SYSTEMVERILOG: interface instance 26 | mem_intf mbus (clk); 27 | 28 | mem_test mtest (.mbus(mbus.tb)); 29 | 30 | mem m1 (.mbus(mbus.mem)); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/d_methods/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/d_methods/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug = 0); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h", waddr, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug = 0); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h", raddr, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/d_methods/runlab8: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab08-intf/d_methods/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/dbrowser-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/dbrowser-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/schematic-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/schematic-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/source-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab09-cpu/.simvision/source-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/CPUtest1.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 1 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This diagnostic program tests the basic instruction set of the VeriRisc 6 | * system. If the system executes each instruction correctly, then it should 7 | * halt when the HLT instruction at address 17(hex) is executed. 8 | * 9 | * If the system halts at any other location, then an instruction did not 10 | * execute properly. Refer to the comments in this file to see which 11 | * instruction failed. 12 | *****************************************************************************/ 13 | 14 | //opcode_operand // addr assembly code 15 | //-------------- // ---- ----------------------------------------------- 16 | @00 111_11110 // 00 BEGIN: JMP TST_JMP 17 | 000_00000 // 01 HLT //JMP did not work at all 18 | 000_00000 // 02 HLT //JMP did not load PC, it skipped 19 | 101_11010 // 03 JMP_OK: LDA DATA_1 20 | 001_00000 // 04 SKZ 21 | 000_00000 // 05 HLT //SKZ or LDA did not work 22 | 101_11011 // 06 LDA DATA_2 23 | 001_00000 // 07 SKZ 24 | 111_01010 // 08 JMP SKZ_OK 25 | 000_00000 // 09 HLT //SKZ or LDA did not work 26 | 110_11100 // 0A SKZ_OK: STO TEMP //store non-zero value in TEMP 27 | 101_11010 // 0B LDA DATA_1 28 | 110_11100 // 0C STO TEMP //store zero value in TEMP 29 | 101_11100 // 0D LDA TEMP 30 | 001_00000 // 0E SKZ //check to see if STO worked 31 | 000_00000 // 0F HLT //STO did not work 32 | 100_11011 // 10 XOR DATA_2 33 | 001_00000 // 11 SKZ //check to see if XOR worked 34 | 111_10100 // 12 JMP XOR_OK 35 | 000_00000 // 13 HLT //XOR did not work at all 36 | 100_11011 // 14 XOR_OK: XOR DATA_2 37 | 001_00000 // 15 SKZ 38 | 000_00000 // 16 HLT //XOR did not switch all bits 39 | 000_00000 // 17 END: HLT //CONGRATULATIONS - TEST1 PASSED! 40 | 111_00000 // 18 JMP BEGIN //run test again 41 | 42 | @1A 00000000 // 1A DATA_1: //constant 00(hex) 43 | 11111111 // 1B DATA_2: //constant FF(hex) 44 | 10101010 // 1C TEMP: //variable - starts with AA(hex) 45 | 46 | @1E 111_00011 // 1E TST_JMP: JMP JMP_OK 47 | 000_00000 // 1F HLT //JMP is broken 48 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/CPUtest2.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 2 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This diagnostic program tests the advanced instruction set of the VeriRisc 6 | * system. If the system executes each instruction correctly, then it should 7 | * halt when the HLT instruction at address 10(hex) is executed. 8 | * 9 | * If the system halts at any other location, then an instruction did not 10 | * execute properly. Refer to the comments in this file to see which 11 | * instruction failed. 12 | * 13 | * WARNING: The CPUtest1 diagnostic program should be completed successfully 14 | * before this test is run. 15 | *****************************************************************************/ 16 | 17 | //opcode_operand // addr assembly code 18 | //-------------- // ---- ----------------------------------------------- 19 | @00 101_11011 // 00 BEGIN: LDA DATA_2 20 | 011_11100 // 01 AND DATA_3 21 | 100_11011 // 02 XOR DATA_2 22 | 001_00000 // 03 SKZ 23 | 000_00000 // 04 HLT //AND doesn't work 24 | 010_11010 // 05 ADD DATA_1 25 | 001_00000 // 06 SKZ 26 | 111_01001 // 07 JMP ADD_OK 27 | 000_00000 // 08 HLT //ADD doesn't work 28 | 100_11100 // 09 XOR DATA_3 29 | 010_11010 // 0A ADD DATA_1 //FF plus 1 makes -1 30 | 110_11101 // 0B STO TEMP 31 | 101_11010 // 0C LDA DATA_1 32 | 010_11101 // 0D ADD TEMP //-1 plus 1 should make zero 33 | 001_00000 // 0E SKZ 34 | 000_00000 // 0F HLT //ADD Doesn't work 35 | 000_00000 // 10 END: HLT //CONGRATULATIONS - TEST2 PASSED! 36 | 111_00000 // 11 JMP BEGIN //run test again 37 | 38 | @1A 00000001 // 1A DATA_1: //constant 1(hex) 39 | 10101010 // 1B DATA_2: //constant AA(hex) 40 | 11111111 // 1C DATA_3: //constant FF(hex) 41 | 00000000 // 1D TEMP: 42 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/CPUtest3.dat: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * Test program 3 for the VeriRisc CPU system, Verilog Training Course. 3 | * 4 | * 5 | * This is an actual program that calculates the Fibonacci number sequence 6 | * from 0 to 144. The Fibonacci number sequence is a series of numbers in 7 | * which each number in the sequence is the sum of the preceding two numbers 8 | * (i.e.: 0, 1, 1, 2, 3, 5, 8, 13 ...). This number sequence is often used 9 | * in financial analysis, and can also be found in the patterns of pineapple 10 | * shells and some flower petals. 11 | * 12 | * WARNING: Do not run this program before the CPUtest1 and CPUtest2 diagnostic 13 | * programs have completed successfully. Those who do are asking for 14 | endless heartache. 15 | *****************************************************************************/ 16 | 17 | //opcode_operand // addr assembly code 18 | //-------------- // ---- ---------------------------------------------------- 19 | 111_00011 // 00 JMP LOOP //jump to the address of LOOP 20 | @03 101_11011 // 03 LOOP: LDA FN2 //load value in FN2 into accum 21 | 110_11100 // 04 STO TEMP //store accumulator in TEMP 22 | 010_11010 // 05 ADD FN1 //add value in FN1 to accumulator 23 | 110_11011 // 06 STO FN2 //store result in FN2 24 | 101_11100 // 07 LDA TEMP //load TEMP into the accumulator 25 | 110_11010 // 08 STO FN1 //store accumulator in FN1 26 | 100_11101 // 09 XOR LIMIT //compare accumulator to LIMIT 27 | 001_00000 // 0A SKZ //if accum = 0, skip to DONE 28 | 111_00011 // 0B JMP LOOP //jump to address of LOOP 29 | 000_00000 // 0C DONE: HLT //end of program 30 | 101_11111 // 0D AGAIN: LDA ONE 31 | 110_11010 // 0E STO FN1 32 | 101_11110 // 0F LDA ZERO 33 | 110_11011 // 10 STO FN2 34 | 111_00011 // 11 JMP LOOP //jump to address of LOOP 35 | 36 | @1A 00000001 // 1A FN1: //data storage for 1st Fib. No. 37 | 00000000 // 1B FN2: //data storage for 2nd Fib. No. 38 | 00000000 // 1C TEMP: //temproray data storage 39 | 10010000 // 1D LIMIT: //max value to calculate 144(dec) 40 | 00000000 // 1E ZERO: //constant 0(decimal) 41 | 00000001 // 1F ONE: //constant 1(decimal) 42 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/alu.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog: import package with opcode_t enum type declaration 14 | import typedefs::*; 15 | module alu ( 16 | output logic [7:0] out , 17 | output logic zero , 18 | input logic clk , 19 | input logic [7:0] accum , 20 | input logic [7:0] data , 21 | input opcode_t opcode 22 | ); 23 | // SystemVerilog: time unit and time precision specification 24 | timeunit 1ns; 25 | timeprecision 100ps; 26 | 27 | // SystemVerilog: unique case synthesis intent specification 28 | always @(negedge clk) 29 | unique case ( opcode ) 30 | ADD : out <= accum + data; 31 | AND : out <= accum & data; 32 | XOR : out <= accum ^ data; 33 | LDA : out <= data; 34 | HLT, 35 | SKZ, 36 | JMP, 37 | STO : out <= accum; 38 | // default : out <= 8'bx; 39 | endcase 40 | 41 | // SystemVerilog: always_comb synthesis intent specification 42 | always_comb 43 | zero = ~(|accum); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/control.sv: -------------------------------------------------------------------------------- 1 | // Controller Module 2 | // SystemVerilog package covered in detail in day2 of the class 3 | import typedefs::*; 4 | 5 | module control ( 6 | output logic load_ac , 7 | output logic mem_rd , 8 | output logic mem_wr , 9 | output logic inc_pc , 10 | output logic load_pc , 11 | output logic load_ir , 12 | output logic halt , 13 | input opcode_t opcode , 14 | input zero , 15 | input clk , 16 | input rst_ 17 | ); 18 | // SystemVerilog: time units and time precision specification 19 | timeunit 1ns; 20 | timeprecision 100ps; 21 | 22 | // SystemVerilog: typedef and enumeration types declared in typedefs package 23 | //typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 24 | //typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 25 | // OP_ADDR, OP_FETCH, ALU_OP, STORE}state_t; 26 | 27 | state_t state; 28 | 29 | logic aluop; 30 | 31 | assign aluop = (opcode inside {ADD, AND, XOR, LDA}); 32 | 33 | always_ff @(posedge clk or negedge rst_) 34 | if (!rst_) 35 | state <= INST_ADDR; 36 | else 37 | state <= state.next(); 38 | 39 | always_comb begin 40 | // default assignments to outputs to avoid latches 41 | {mem_rd, load_ir, halt, inc_pc, load_ac, load_pc, mem_wr} = 7'b000_0000; 42 | unique case (state) 43 | INST_ADDR : ; 44 | INST_FETCH: mem_rd = 1; 45 | INST_LOAD : begin 46 | mem_rd = 1; 47 | load_ir = 1; 48 | end 49 | IDLE : begin 50 | mem_rd = 1; 51 | load_ir = 1; 52 | end 53 | OP_ADDR : begin 54 | inc_pc = 1; 55 | halt = (opcode == HLT); 56 | end 57 | OP_FETCH : mem_rd = aluop; 58 | ALU_OP : begin 59 | load_ac = aluop; 60 | mem_rd = aluop; 61 | inc_pc = ((opcode == SKZ) && zero); 62 | load_pc = ( opcode == JMP); 63 | end 64 | STORE : begin 65 | load_ac = aluop; 66 | mem_rd = aluop; 67 | inc_pc = (opcode == JMP); 68 | load_pc = ( opcode == JMP); 69 | mem_wr = ( opcode == STO); 70 | end 71 | endcase 72 | end 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/counter.sv: -------------------------------------------------------------------------------- 1 | timeunit 1ns; 2 | timeprecision 100ps; 3 | 4 | module counter ( input [4:0] data, 5 | input enable, load, clk, rst_, 6 | output logic [4:0] count); 7 | 8 | always_ff@(posedge clk iff (load == 1 || enable == 1) or negedge rst_ ) 9 | 10 | if (!rst_) 11 | count <= '0; 12 | else if (load) 13 | count <= data; 14 | else 15 | count <= count+1; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/cpu.sv: -------------------------------------------------------------------------------- 1 | module cpu ( 2 | output logic halt , 3 | output logic load_ir , 4 | input logic clk , 5 | input logic cntrl_clk , 6 | input logic alu_clk , 7 | input logic fetch , 8 | input logic rst_ 9 | ); 10 | //SystemVerilog: timeunit and timeprecision notation 11 | timeunit 1ns; 12 | timeprecision 100ps; 13 | 14 | import typedefs::*; 15 | 16 | logic [7:0] data_out, alu_out, accum, ir_out; 17 | logic [4:0] pc_addr, ir_addr, addr; 18 | opcode_t opcode; 19 | logic load_ac, mem_rd, mem_wr, inc_pc, load_pc, zero; 20 | 21 | //SystemVerilog: .name port connections 22 | register ac ( .out (accum ), 23 | .data (alu_out), 24 | .clk, 25 | .enable (load_ac), 26 | .rst_ 27 | ); 28 | 29 | register ir ( .out (ir_out), 30 | .data(data_out), 31 | .clk, 32 | .enable (load_ir), 33 | .rst_ 34 | ); 35 | 36 | assign opcode = opcode_t'(ir_out[7:5]); 37 | 38 | assign ir_addr = ir_out[4:0]; 39 | 40 | counter pc ( .count (pc_addr), 41 | .data (ir_addr), 42 | .clk (clk), 43 | .load (load_pc), 44 | .enable (inc_pc), 45 | .rst_ 46 | ); 47 | 48 | alu alu1 ( .out (alu_out), 49 | .zero, 50 | .clk (alu_clk), 51 | .accum, 52 | .data(data_out), 53 | .opcode 54 | ); 55 | 56 | scale_mux #5 smx( .out (addr), 57 | .in_a (pc_addr), 58 | .in_b (ir_addr), 59 | .sel_a (fetch) 60 | ); 61 | 62 | mem mem1 ( .clk(~cntrl_clk), 63 | .read (mem_rd), 64 | .write (mem_wr), 65 | .addr , 66 | .data_in(alu_out) , 67 | .data_out(data_out) 68 | ); 69 | 70 | 71 | control cntl ( .load_ac, 72 | .mem_rd, 73 | .mem_wr, 74 | .inc_pc, 75 | .load_pc, 76 | .load_ir, 77 | .halt, 78 | .opcode, 79 | .zero, 80 | .clk(cntrl_clk), 81 | .rst_ 82 | ); 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | input clk, 22 | input read, 23 | input write, 24 | input logic [4:0] addr , 25 | input logic [7:0] data_in , 26 | output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge clk) 36 | if (write && !read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[addr] <= data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) 42 | data_out <= memory[addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/register.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : register.sv 5 | // Title : Register Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the register module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module register ( 14 | // Verilog2001: port and variable declarations in module definition 15 | // SystemVerilog: logic data type 16 | output logic [7:0] out, 17 | input logic [7:0] data , 18 | input clk , 19 | input enable , 20 | input rst_ 21 | ); 22 | // SystemVerilog: time unit and time precision declaration 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | // SystemVerilog: always_ff - sequential behavior intent specification 27 | // SystemVerilog: iff conditional execution 28 | always_ff @(posedge clk iff (enable == 1) or negedge rst_) 29 | if (!rst_) 30 | out <= 0; 31 | else 32 | out <= data; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/runlab9: -------------------------------------------------------------------------------- 1 | typedefs.sv 2 | alu.sv 3 | control.sv 4 | counter.sv 5 | mem.sv 6 | register.sv 7 | scale_mux.sv 8 | cpu.sv 9 | cpu_test.sv 10 | -timescale 1ns/100ps 11 | +access+rwc 12 | //+gui 13 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/scale_mux.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : scale_mux.sv 5 | // Title : MUX Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module 9 | // Notes : 10 | // Scalable Mux - Specification: 11 | // when sel_a = 1, out = in_a 12 | // when sel_a = 0, out = in_b 13 | // when sel_a = x, out = x 14 | // 15 | /////////////////////////////////////////////////////////////////////////// 16 | 17 | module scale_mux #(WIDTH = 1) 18 | (output logic [WIDTH-1:0] out, 19 | input logic [WIDTH-1:0] in_a, 20 | input logic [WIDTH-1:0] in_b, 21 | input logic sel_a); 22 | 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | always_comb 27 | unique case (sel_a) 28 | 1'b1: out = in_a; 29 | 1'b0: out = in_b; 30 | default: out = 'x; 31 | endcase 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab09-cpu/typedefs.sv: -------------------------------------------------------------------------------- 1 | package typedefs; 2 | //SystemVerilog: User-defined data types using enumerations 3 | // CPU Operations 4 | typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 5 | // Control Sequencer States 6 | typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 7 | OP_ADDR, OP_FETCH, ALU_OP, STORE}state_t; 8 | 9 | endpackage : typedefs 10 | 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/.simvision/dbrowser-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab10-cb/.simvision/dbrowser-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/.simvision/schematic-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab10-cb/.simvision/schematic-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/.simvision/source-bookmarks: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab10-cb/.simvision/source-bookmarks -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/flipflop.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : flipflop.sv 5 | // Title : Flipflop Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Flipflop module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module flipflop (input logic clk, reset, 14 | input logic [7:0] qin, 15 | output logic [7:0] qout); 16 | timeunit 1ns; 17 | 18 | always @(posedge clk or posedge reset) 19 | if (reset) 20 | qout = '0; 21 | else 22 | qout = qin; 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/flipflop_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : flipflop_test.sv 5 | // Title : Flipflop Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Flipflop testbench module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module testflop (); 14 | timeunit 1ns; 15 | 16 | logic reset; 17 | logic [7:0] qin,qout; 18 | 19 | // ---- clock generator code begin------ 20 | `define PERIOD 10 21 | logic clk = 1'b1; 22 | 23 | always 24 | #(`PERIOD/2)clk = ~clk; 25 | 26 | // ---- clock generator code end------ 27 | 28 | 29 | flipflop DUV(.*); 30 | 31 | default clocking cb @(posedge clk); 32 | default input #1step output #4; 33 | input qout; 34 | output reset, qin; 35 | endclocking 36 | 37 | initial 38 | begin 39 | cb.qin <= '0; 40 | cb.reset <= 0; 41 | ##2 cb.reset <= 1; 42 | ##3 cb.reset <= 0; 43 | for (int i = 1; i < 8; i++) 44 | begin 45 | ##1 cb.qin <= i; 46 | end 47 | ##3; 48 | $finish(); 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab10-cb/runlab10: -------------------------------------------------------------------------------- 1 | flipflop.sv 2 | flipflop_test.sv 3 | -gui 4 | -access +rwc 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab11-memrnd/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab11-memrnd/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug ); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h %c", waddr, wdata, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug ); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h %c", raddr, rdata, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab11-memrnd/runlab11: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab11-memrnd/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab12-countclass/01_simple_class.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : 01_simple_class.sv 5 | // Title : Simple class 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Simple counter class 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module counterclass1; 14 | 15 | class counter; 16 | int count; 17 | 18 | function int getcount(); 19 | return (count); 20 | endfunction 21 | 22 | function void load(input int value); 23 | count = value; 24 | endfunction 25 | 26 | endclass 27 | 28 | int countval; 29 | 30 | counter c1 = new; 31 | 32 | 33 | initial 34 | begin 35 | 36 | countval = c1.getcount(); 37 | $display("getcount %0d", countval); 38 | c1.load(3); 39 | countval = c1.getcount(); 40 | $display("getcount %0d", countval); 41 | 42 | 43 | end 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab12-countclass/02_constructor.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : 02_constructor.sv 5 | // Title : Class with constructor 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Simple counter class with explcit constructor 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module counterclass2; 14 | 15 | class counter; 16 | int count; 17 | 18 | function new(input int start=0); 19 | count = start; 20 | endfunction 21 | 22 | function int getcount(); 23 | return (count); 24 | endfunction 25 | 26 | function void load(input int value); 27 | count = value; 28 | endfunction 29 | 30 | endclass 31 | 32 | int countval; 33 | 34 | counter c1 = new(6); 35 | 36 | initial 37 | begin 38 | 39 | countval = c1.getcount(); 40 | $display("getcount from constructor %0d", countval); 41 | c1.load(3); 42 | countval = c1.getcount(); 43 | $display("getcount from load %0d", countval); 44 | 45 | 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab12-countclass/03_derived_class.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : 03_derived.sv 5 | // Title : Class with inheritance 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Extended classes upcounter and downcounter 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module counterclass3; 14 | 15 | class counter; 16 | int count; 17 | 18 | function new(input int start); 19 | count = start; 20 | endfunction 21 | 22 | function int getcount(); 23 | return (count); 24 | endfunction 25 | 26 | function void load(input int value); 27 | count = value; 28 | endfunction 29 | 30 | endclass 31 | 32 | class upcounter extends counter; 33 | 34 | function new(input int start); 35 | super.new(start); 36 | endfunction 37 | 38 | function void next(); 39 | count++; 40 | $display("upcounter next %0d", count); 41 | endfunction 42 | 43 | endclass 44 | 45 | class downcounter extends counter; 46 | 47 | function new(input int start); 48 | super.new(start); 49 | endfunction 50 | 51 | function void next(); 52 | count--; 53 | $display("downcounter next %0d", count); 54 | endfunction 55 | 56 | endclass 57 | 58 | int countval; 59 | 60 | upcounter up1 = new(4); 61 | downcounter down2 = new(0); 62 | 63 | 64 | initial 65 | begin 66 | 67 | countval = up1.getcount(); 68 | $display("getcount from up1 constructor %0d", countval); 69 | 70 | up1.next(); 71 | 72 | countval = down2.getcount(); 73 | $display("getcount from down2 constructor %0d", countval); 74 | 75 | down2.next(); 76 | down2.next(); 77 | 78 | 79 | end 80 | 81 | endmodule 82 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab12-countclass/04_counter_limits.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : 04_counter_limits.sv 5 | // Title : Classes with count limits 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Max and min limits added to count class for upcounter and downcounter 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module counterclass4; 14 | 15 | class counter; 16 | int count; 17 | int max, min; 18 | 19 | function new(input int start, upper, lower); 20 | check_limits(upper, lower); 21 | check_set(start); 22 | endfunction 23 | 24 | function void check_limits (input int upper, lower); 25 | if (lower > upper) begin 26 | $display("lower bound %0d > upper bound %0d - bounds swapped", lower, upper); 27 | max = lower; 28 | min = upper; 29 | end 30 | else begin 31 | max = upper; 32 | min = lower; 33 | end 34 | endfunction 35 | 36 | function void check_set(input int set); 37 | if ((set < min) || (set > max)) 38 | begin 39 | $display("count set value %0d outside bounds %0d to %0d - set to min", set, min, max); 40 | count = min; 41 | end 42 | else 43 | count = set; 44 | endfunction 45 | 46 | function int getcount(); 47 | return (count); 48 | endfunction 49 | 50 | function void load(input int value); 51 | check_set(value); 52 | endfunction 53 | 54 | endclass 55 | 56 | class upcounter extends counter; 57 | 58 | function new(input int start, upper, lower); 59 | super.new(start, upper, lower); 60 | endfunction 61 | 62 | function void next(); 63 | if (count == max) 64 | count = min; 65 | else 66 | count++; 67 | $display("upcounter next %0d", count); 68 | endfunction 69 | 70 | endclass 71 | 72 | class downcounter extends counter; 73 | 74 | function new(input int start, upper, lower); 75 | super.new(start, upper, lower); 76 | endfunction 77 | 78 | function void next(); 79 | if (count == min) 80 | count = max; 81 | else 82 | count--; 83 | $display("downcounter next %0d", count); 84 | endfunction 85 | 86 | endclass 87 | 88 | int countval; 89 | 90 | upcounter up1 = new(4, 3, 1); // start outside bounds 91 | downcounter down2 = new(4, 2, 5); // upper < lower 92 | upcounter up3 = new(2, 3, 0); 93 | downcounter down4 = new(2, 3, 0); 94 | 95 | 96 | initial 97 | begin 98 | 99 | up3.next(); 100 | up3.next(); 101 | up3.next(); 102 | down4.next(); 103 | down4.next(); 104 | down4.next(); 105 | 106 | end 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab12-countclass/05_roll_over_under.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : 05_roll_over_under.sv 5 | // Title : Classes with count limits and roll over/under indication 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Properties added to extended classes 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module counterclass5; 14 | 15 | class counter; 16 | int count; 17 | int max, min; 18 | 19 | function new(input int start, upper, lower); 20 | check_limits(upper, lower); 21 | check_set(start); 22 | endfunction 23 | 24 | function void check_limits (input int upper, lower); 25 | if (lower > upper) begin 26 | $display("lower bound %0d > upper bound %0d - bounds swapped", lower, upper); 27 | max = lower; 28 | min = upper; 29 | end 30 | else begin 31 | max = upper; 32 | min = lower; 33 | end 34 | endfunction 35 | 36 | function void check_set(input int set); 37 | if ((set < min) || (set > max)) 38 | begin 39 | $display("count set value %0d outside bounds %0d to %0d - set to min", set, min, max); 40 | count = min; 41 | end 42 | else 43 | count = set; 44 | endfunction 45 | 46 | function int getcount(); 47 | return (count); 48 | endfunction 49 | 50 | function void load(input int value); 51 | check_set(value); 52 | endfunction 53 | 54 | endclass 55 | 56 | class upcounter extends counter; 57 | 58 | logic carry; 59 | 60 | function new(input int start, upper, lower); 61 | super.new(start, upper, lower); 62 | endfunction 63 | 64 | function void next(); 65 | if (count == max) begin 66 | carry = 1; 67 | count = min; 68 | end 69 | else begin 70 | carry = 0; 71 | count++; 72 | end 73 | $display("upcounter next %0d %0d", count, carry); 74 | endfunction 75 | 76 | endclass 77 | 78 | class downcounter extends counter; 79 | 80 | logic borrow; 81 | 82 | function new(input int start, upper, lower); 83 | super.new(start, upper, lower); 84 | endfunction 85 | 86 | function void next(); 87 | if (count == min) begin 88 | borrow = 1; 89 | count = max; 90 | end 91 | else begin 92 | borrow = 0; 93 | count--; 94 | end 95 | $display("downcounter next %0d %0d", count, borrow); 96 | endfunction 97 | 98 | endclass 99 | 100 | int countval; 101 | 102 | upcounter up1 = new(4, 3, 1); // start outside bounds 103 | downcounter down2 = new(4, 2, 5); // upper < lower 104 | upcounter up3 = new(2, 3, 0); 105 | downcounter down4 = new(2, 3, 0); 106 | 107 | 108 | initial 109 | begin 110 | 111 | up3.next(); 112 | up3.next(); 113 | up3.next(); 114 | down4.next(); 115 | down4.next(); 116 | down4.next(); 117 | down4.next(); 118 | 119 | end 120 | 121 | endmodule 122 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab14-memclass/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab14-memclass/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug ); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h %c", waddr, wdata, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug ); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h %c", raddr, rdata, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab14-memclass/runlab14: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab14-memclass/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug ); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h %c", waddr, wdata, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug ); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h %c", raddr, rdata, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/multmemrunlab13: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test_multmem.sv 4 | top_multmem.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/runlab15: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab15-memvif/top_multmem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus1 (clk); 29 | mem_intf mbus2 (clk); 30 | 31 | mem_test mtest (.mbus1(mbus1.tb), .mbus2(mbus2.tb)); 32 | 33 | mem m1 (.mbus(mbus1.mem)); 34 | mem m2 (.mbus(mbus2.mem)); 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/.imc.trace: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab16-memcov/.imc.trace -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/classcoveragerunlab14: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test_class_coverage.sv 4 | top.sv 5 | // coverage options 6 | -covdut mem_test 7 | -coverage U 8 | -covoverwrite 9 | -gui 10 | -access +rwc 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug ); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h %c", waddr, wdata, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug ); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h %c", raddr, rdata, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/runlab16: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test.sv 4 | top.sv 5 | // coverage options 6 | -covdut mem_test 7 | -coverage U 8 | -covoverwrite 9 | -gui 10 | -access +rwc 11 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab16-memcov/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab17-alucov/.imc.trace: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AbhishekTaur/System-Verilog-Practice/b76f4ee1481446e0b55cfcec008f8cb59463ec21/sv_design_verification_v20-3/solutions/lab17-alucov/.imc.trace -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab17-alucov/alu.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog: import package with opcode_t enum type declaration 14 | import typedefs::*; 15 | module alu ( 16 | output logic [7:0] out , 17 | output logic zero , 18 | input logic clk , 19 | input logic [7:0] accum , 20 | input logic [7:0] data , 21 | input opcode_t opcode 22 | ); 23 | // SystemVerilog: time unit and time precision specification 24 | timeunit 1ns; 25 | timeprecision 100ps; 26 | 27 | // SystemVerilog: unique case synthesis intent specification 28 | always @(negedge clk) 29 | unique case ( opcode ) 30 | ADD : out <= accum + data; 31 | AND : out <= accum & data; 32 | XOR : out <= accum ^ data; 33 | LDA : out <= data; 34 | HLT, 35 | SKZ, 36 | JMP, 37 | STO : out <= accum; 38 | // default : out <= 8'bx; 39 | endcase 40 | 41 | // SystemVerilog: always_comb synthesis intent specification 42 | always_comb 43 | zero = ~(|accum); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab17-alucov/runlab17: -------------------------------------------------------------------------------- 1 | typedefs.sv 2 | alu.sv 3 | alu_test.sv 4 | -covdut alu_test 5 | -coverage U 6 | -covoverwrite 7 | -gui 8 | -access +rwc 9 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab17-alucov/typedefs.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : typdefs.sv 5 | // Title : Opcode and state enum types 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the opcode and state type declarations 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | package typedefs; 14 | //SystemVerilog: User-defined data types using enumerations 15 | // CPU Operations 16 | typedef enum logic [2:0] {HLT, SKZ, ADD, AND, XOR, LDA, STO, JMP} opcode_t; 17 | // Control Sequencer States 18 | typedef enum logic [2:0] {INST_ADDR, INST_FETCH, INST_LOAD, IDLE, 19 | OP_ADDR, OP_FETCH, ALU_OP, STORE} state_t; 20 | 21 | endpackage : typedefs 22 | 23 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory module with interface, clk port, modport and methods 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | mem_intf.mem mbus 22 | ); 23 | // SYSTEMVERILOG: timeunit and timeprecision specification 24 | timeunit 1ns; 25 | timeprecision 1ns; 26 | 27 | // SYSTEMVERILOG: logic data type 28 | logic [7:0] memory [0:31] ; 29 | 30 | always @(posedge mbus.clk) 31 | if (mbus.write && !mbus.read) 32 | // SYSTEMVERILOG: time literals 33 | #1 memory[mbus.addr] <= mbus.data_in; 34 | 35 | // SYSTEMVERILOG: always_ff and iff event control 36 | always_ff @(posedge mbus.clk iff ((mbus.read == '1)&&(mbus.write == '0)) ) 37 | mbus.data_out <= memory[mbus.addr]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/mem_intf.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem_intf.sv 5 | // Title : Memory interface 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Memory interface with clk port, modport and 9 | // methods 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////////// 13 | 14 | interface mem_intf(input logic clk); 15 | //SYSTEMVERILOG: timeunit and timeprecision notation 16 | timeunit 1ns; 17 | timeprecision 100ps; 18 | 19 | //SYSTEMVERILOG: logic data types 20 | logic [7:0] data_in; 21 | logic [7:0] data_out; 22 | logic [4:0] addr; 23 | logic read; 24 | logic write; 25 | 26 | // SYSTEMVERILOG: modports in an interface 27 | modport tb ( input data_out, clk, 28 | output data_in, addr, read, write, 29 | import read_mem, write_mem ); 30 | 31 | modport mem ( output data_out, 32 | input clk, data_in, addr, read, write ); 33 | 34 | // SYSTEMVERILOG: default task input argument values 35 | task write_mem (input [4:0] waddr, input [7:0] wdata, input debug ); 36 | @(negedge clk); 37 | write <= 1; 38 | read <= 0; 39 | addr <= waddr; 40 | data_in <= wdata; 41 | @(negedge clk); 42 | write <= 0; 43 | if (debug == 1) 44 | $display("Write - Address:%d Data:%h %c", waddr, wdata, wdata); 45 | endtask 46 | 47 | // SYSTEMVERILOG: default task input argument values 48 | task read_mem (input [4:0] raddr, output [7:0] rdata, input debug ); 49 | @(negedge clk); 50 | write <= 0; 51 | read <= 1; 52 | addr <= raddr; 53 | @(negedge clk); 54 | read <= 0; 55 | rdata = data_out; 56 | if (debug == 1) 57 | $display("Read - Address:%d Data:%h %c", raddr, rdata, rdata); 58 | endtask 59 | 60 | endinterface : mem_intf 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/runassoc: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test_assoc.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/rundyn: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test_dynarr.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/runqueue: -------------------------------------------------------------------------------- 1 | mem_intf.sv 2 | mem.sv 3 | mem_test_queue.sv 4 | top.sv 5 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab18-memarr/top.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : top.sv 5 | // Title : top Module for memory 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the top module for memory with interface, clk port, 9 | // modport and methods 10 | // Notes : 11 | // Memory Lab - top-level 12 | // A top-level module which instantiates the memory and mem_test modules 13 | // 14 | /////////////////////////////////////////////////////////////////////////// 15 | 16 | 17 | module top; 18 | // SYSTEMVERILOG: timeunit and timeprecision specification 19 | timeunit 1ns; 20 | timeprecision 1ns; 21 | 22 | // SYSTEMVERILOG: logic and bit data types 23 | logic clk = 0; 24 | 25 | always #5 clk = ~clk; 26 | 27 | // SYSTEMVERILOG: interface instance 28 | mem_intf mbus (clk); 29 | 30 | mem_test mtest (.mbus(mbus.tb)); 31 | 32 | mem m1 (.mbus(mbus.mem)); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab19-svamux/mux.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux.sv 5 | // Title : MUX module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | `timescale 1 ns / 1 ns 13 | 14 | module mux 15 | ( 16 | input logic clock , 17 | input logic [3:0] ip1 , 18 | input logic [3:0] ip2 , 19 | input logic [3:0] ip3 , 20 | input logic sel1 , 21 | input logic sel2 , 22 | input logic sel3 , 23 | output logic [3:0] mux_op 24 | ) ; 25 | 26 | always @(posedge clock) 27 | if (sel1 == 1) 28 | mux_op <= ip1 ; 29 | else 30 | if (sel2 == 1) 31 | mux_op <= ip2 ; 32 | else 33 | if (sel3 == 1) 34 | mux_op <= ip3 ; 35 | 36 | // assertions go here 37 | //#### edit ### 38 | 39 | 40 | 41 | 42 | //#### end of edit ### 43 | endmodule 44 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab19-svamux/mux_asserted1.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux_asserted1.sv 5 | // Title : MUX module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module with initial (incorrect) assertions 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | `timescale 1 ns / 1 ns 14 | 15 | module mux 16 | ( 17 | input logic clock , 18 | input logic [3:0] ip1 , 19 | input logic [3:0] ip2 , 20 | input logic [3:0] ip3 , 21 | input logic sel1 , 22 | input logic sel2 , 23 | input logic sel3 , 24 | output logic [3:0] mux_op 25 | ) ; 26 | 27 | always @(posedge clock) 28 | if (sel1 == 1) 29 | mux_op <= ip1 ; 30 | else 31 | if (sel2 == 1) 32 | mux_op <= ip2 ; 33 | else 34 | if (sel3 == 1) 35 | mux_op <= ip3 ; 36 | 37 | // Assertions go here 38 | //#### EDIT ### 39 | default clocking defclk @(negedge clock) ; 40 | endclocking 41 | 42 | property SELECT1; 43 | @(negedge clock) (sel1 == 1'b1) |=> (mux_op == ip1); 44 | endproperty 45 | property SELECT2; 46 | @(negedge clock) (sel2 == 1'b1) |=> (mux_op == ip2); 47 | endproperty 48 | property SELECT3; 49 | @(negedge clock) (sel3 == 1'b1) |=> (mux_op == ip3); 50 | endproperty 51 | 52 | A1: assert property (SELECT1) ; 53 | A2: assert property (SELECT2) ; 54 | A3: assert property (SELECT3) ; 55 | //#### END OF EDIT ### 56 | endmodule 57 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab19-svamux/mux_asserted2.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux_asserted2.sv 5 | // Title : MUX module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module with final (correct) assertions 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | 14 | `timescale 1 ns / 1 ns 15 | 16 | module mux 17 | ( 18 | input logic clock , 19 | input logic [3:0] ip1 , 20 | input logic [3:0] ip2 , 21 | input logic [3:0] ip3 , 22 | input logic sel1 , 23 | input logic sel2 , 24 | input logic sel3 , 25 | output logic [3:0] mux_op 26 | ) ; 27 | 28 | always @(posedge clock) 29 | if (sel1 == 1) 30 | mux_op <= ip1 ; 31 | else 32 | if (sel2 == 1) 33 | mux_op <= ip2 ; 34 | else 35 | if (sel3 == 1) 36 | mux_op <= ip3 ; 37 | 38 | // Assertions go here 39 | //#### EDIT ### 40 | default clocking defclk @(negedge clock) ; 41 | endclocking 42 | 43 | property SELECT1; 44 | @(negedge clock) 45 | (sel1 == 1'b1) |=> (mux_op == ip1); 46 | endproperty 47 | property SELECT2; 48 | @(negedge clock) 49 | ((sel1 == 1'b0) & (sel2 == 1'b1)) |=> (mux_op == ip2); 50 | endproperty 51 | property SELECT3; 52 | @(negedge clock) 53 | ((sel1 == 1'b0) & (sel2 == 1'b0) & (sel3 == 1'b1)) |=> (mux_op == ip3); 54 | endproperty 55 | 56 | A1: assert property (SELECT1) ; 57 | A2: assert property (SELECT2) ; 58 | A3: assert property (SELECT3) ; 59 | //#### END OF EDIT ### 60 | endmodule 61 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab19-svamux/mux_test.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mux_test.sv 5 | // Title : MUX testbench 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux testbench 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | `timescale 1 ns / 1 ns 14 | 15 | module t_mux ; 16 | 17 | parameter PERIOD = 10 ; 18 | 19 | logic clock ; 20 | logic [3:0] ip1 ; 21 | logic [3:0] ip2 ; 22 | logic [3:0] ip3 ; 23 | logic [2:0] sel ; 24 | logic [3:0] mux_op ; 25 | 26 | 27 | mux mux1 28 | ( 29 | .clock ( clock ), 30 | .ip1 ( ip1 ), 31 | .ip2 ( ip2 ), 32 | .ip3 ( ip3 ), 33 | .sel1 ( sel[0] ), 34 | .sel2 ( sel[1] ), 35 | .sel3 ( sel[2] ), 36 | .mux_op ( mux_op ) 37 | ) ; 38 | 39 | always 40 | begin 41 | clock <= 0 ; 42 | #(PERIOD/2) ; 43 | clock <= 1 ; 44 | #(PERIOD/2) ; 45 | end 46 | 47 | initial 48 | begin : TEST 49 | @(posedge clock); 50 | #(PERIOD/4); // Keep changes away from clock edges 51 | ip1 <= 4'b0001 ; 52 | ip2 <= 4'b0010 ; 53 | ip3 <= 4'b0100 ; 54 | 55 | $display ("Starting 1st set of test vectors."); 56 | 57 | for (int i=0; i<=2; i++) 58 | begin 59 | sel <= 1<> e1 ; 39 | end : EMITTER_1 40 | 41 | /////////////////////////////////////////////////////// 42 | // TO DO PART 1 - REPLACE WITH NON-BLOCKING OPERATOR // 43 | /////////////////////////////////////////////////////// 44 | begin : EMITTER_2 45 | $display ( "%m emitting event e2" ) ; 46 | ->> e2 ; 47 | end : EMITTER_2 48 | 49 | ///////////////////////////////////////////////////////////// 50 | // TO DO PART 2 - REPLACE WITH WAIT FOR triggered PROPERTY // 51 | ///////////////////////////////////////////////////////////// 52 | begin : WAITER_2 53 | $display ( "%m waiting event e2" ) ; 54 | @ e2 55 | $display ( "%m received event e2" ) ; 56 | end : WAITER_2 57 | 58 | join_none 59 | #10ns; 60 | disable fork; 61 | $display("TEST COMPLETE"); 62 | $finish(0); 63 | end 64 | 65 | endmodule : event_m 66 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/solutions/lab24-event/event_m_1b.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2007 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : event_m_1.sv 5 | // Title : Event Testcase 1 6 | // Project : SystemVerilog Verify Training 7 | // Created : 2007-10-01 8 | // Description : Defines a race between a process triggering an event 9 | // and a process waiting for the event. 10 | // Notes : 11 | // 12 | /////////////////////////////////////////////////////////////////////// 13 | 14 | module event_m ; 15 | 16 | timeunit 1ns; 17 | timeprecision 1ns; 18 | 19 | event e1, e2 ; 20 | 21 | initial begin 22 | fork 23 | 24 | ///////////////////////////////////////////////////////////// 25 | // TO DO PART 2 - REPLACE WITH WAIT FOR triggered PROPERTY // 26 | ///////////////////////////////////////////////////////////// 27 | begin : WAITER_1 28 | $display ( "%m waiting event e1" ) ; 29 | wait ( e1.triggered ) ; 30 | $display ( "%m received event e1" ) ; 31 | end : WAITER_1 32 | 33 | /////////////////////////////////////////////////////// 34 | // TO DO PART 1 - REPLACE WITH NON-BLOCKING OPERATOR // 35 | /////////////////////////////////////////////////////// 36 | begin : EMITTER_1 37 | $display ( "%m emitting event e1" ) ; 38 | -> e1 ; 39 | end : EMITTER_1 40 | 41 | /////////////////////////////////////////////////////// 42 | // TO DO PART 1 - REPLACE WITH NON-BLOCKING OPERATOR // 43 | /////////////////////////////////////////////////////// 44 | begin : EMITTER_2 45 | $display ( "%m emitting event e2" ) ; 46 | -> e2 ; 47 | end : EMITTER_2 48 | 49 | ///////////////////////////////////////////////////////////// 50 | // TO DO PART 2 - REPLACE WITH WAIT FOR triggered PROPERTY // 51 | ///////////////////////////////////////////////////////////// 52 | begin : WAITER_2 53 | $display ( "%m waiting event e2" ) ; 54 | wait ( e2.triggered ) ; 55 | $display ( "%m received event e2" ) ; 56 | end : WAITER_2 57 | 58 | join_none 59 | #10ns; 60 | disable fork; 61 | $display("TEST COMPLETE"); 62 | $finish(0); 63 | end 64 | 65 | endmodule : event_m 66 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/alu.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : alu.sv 5 | // Title : ALU Testbench Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the ALU module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog: import package with opcode_t enum type declaration 14 | import typedefs::*; 15 | module alu ( 16 | output logic [7:0] out , 17 | output logic zero , 18 | input logic clk , 19 | input logic [7:0] accum , 20 | input logic [7:0] data , 21 | input opcode_t opcode 22 | ); 23 | // SystemVerilog: time unit and time precision specification 24 | timeunit 1ns; 25 | timeprecision 100ps; 26 | 27 | // SystemVerilog: unique case synthesis intent specification 28 | always @(negedge clk) 29 | unique case ( opcode ) 30 | ADD : out <= accum + data; 31 | AND : out <= accum & data; 32 | XOR : out <= accum ^ data; 33 | LDA : out <= data; 34 | HLT, 35 | SKZ, 36 | JMP, 37 | STO : out <= accum; 38 | // default : out <= 8'bx; 39 | endcase 40 | 41 | // SystemVerilog: always_comb synthesis intent specification 42 | always_comb 43 | zero = ~(|accum); 44 | 45 | endmodule 46 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/control.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : control.sv 5 | // Title : Control Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the Control module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // SystemVerilog package for opcode_t and state_t 14 | import typedefs::*; 15 | 16 | module control ( 17 | output logic load_ac , 18 | output logic mem_rd , 19 | output logic mem_wr , 20 | output logic inc_pc , 21 | output logic load_pc , 22 | output logic load_ir , 23 | output logic halt , 24 | input opcode_t opcode , 25 | input zero , 26 | input clk , 27 | input rst_ 28 | ); 29 | // SystemVerilog: time units and time precision specification 30 | timeunit 1ns; 31 | timeprecision 100ps; 32 | 33 | state_t state; 34 | 35 | logic aluop; 36 | 37 | assign aluop = (opcode inside {ADD, AND, XOR, LDA}); 38 | 39 | always_ff @(posedge clk or negedge rst_) 40 | if (!rst_) 41 | state <= INST_ADDR; 42 | else 43 | state <= state.next(); 44 | 45 | always_comb begin 46 | {mem_rd, load_ir, halt, inc_pc, load_ac, load_pc, mem_wr} = 7'b000_0000; 47 | unique case (state) 48 | INST_ADDR : ; 49 | INST_FETCH: mem_rd = 1; 50 | INST_LOAD : begin 51 | mem_rd = 1; 52 | load_ir = 1; 53 | end 54 | IDLE : begin 55 | mem_rd = 1; 56 | load_ir = 1; 57 | end 58 | OP_ADDR : begin 59 | inc_pc = 1; 60 | halt = (opcode == HLT); 61 | end 62 | OP_FETCH : mem_rd = aluop; 63 | ALU_OP : begin 64 | load_ac = aluop; 65 | mem_rd = aluop; 66 | inc_pc = ((opcode == SKZ) && zero); 67 | load_pc = ( opcode == JMP); 68 | end 69 | STORE : begin 70 | load_ac = aluop; 71 | mem_rd = aluop; 72 | inc_pc = (opcode == JMP || ((opcode == SKZ) && zero)); 73 | load_pc = ( opcode == JMP); 74 | mem_wr = ( opcode == STO); 75 | end 76 | endcase 77 | end 78 | 79 | endmodule 80 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/counter.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : counter.sv 5 | // Title : counter Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the counter module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | // Verilog2001: port and variable declarations in module definition 14 | module counter ( 15 | output logic [4:0] count, 16 | input logic [4:0] data , 17 | input clk , 18 | input load , 19 | input rst_ 20 | ); 21 | 22 | // SystemVerilog: time unit and time precision declaration 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | // SystemVerilog: always_ff 27 | always_ff @(posedge clk or negedge rst_) 28 | // SystemVerilog: priority if 29 | priority if (!rst_) 30 | count <= 0; 31 | else if (load) 32 | count <= data; 33 | // SystemVerilog: postincrement or assignment operator 34 | else count <= count +1; //++; 35 | // else count += 1; 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/mem.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : mem.sv 5 | // Title : Memory Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the memory module 9 | // Notes : 10 | // Synchronous 8x32 Memory Design 11 | // Specification: 12 | // Memory is 8-bits wide and address range is 0 to 31. 13 | // Memory access is synchronous. 14 | // Write data into the memory on posedge of clk when write=1 15 | // Place memory[addr] onto data bus on posedge of clk when read=1 16 | // The read and write signals should not be simultaneously high. 17 | // 18 | /////////////////////////////////////////////////////////////////////////// 19 | 20 | module mem ( 21 | input clk, 22 | input read, 23 | input write, 24 | input logic [4:0] addr , 25 | input logic [7:0] data_in , 26 | output logic [7:0] data_out 27 | ); 28 | // SYSTEMVERILOG: timeunit and timeprecision specification 29 | timeunit 1ns; 30 | timeprecision 1ns; 31 | 32 | // SYSTEMVERILOG: logic data type 33 | logic [7:0] memory [0:31] ; 34 | 35 | always @(posedge clk) 36 | if (write && !read) 37 | // SYSTEMVERILOG: time literals 38 | #1 memory[addr] <= data_in; 39 | 40 | // SYSTEMVERILOG: always_ff and iff event control 41 | always_ff @(posedge clk iff ((read == '1)&&(write == '0)) ) 42 | data_out <= memory[addr]; 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/register.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : register.sv 5 | // Title : Register Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the register module 9 | // Notes : 10 | // 11 | /////////////////////////////////////////////////////////////////////////// 12 | 13 | module register ( 14 | // Verilog2001: port and variable declarations in module definition 15 | // SystemVerilog: logic data type 16 | output logic [7:0] out, 17 | input logic [7:0] data , 18 | input clk , 19 | input enable , 20 | input rst_ 21 | ); 22 | // SystemVerilog: time unit and time precision declaration 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | // SystemVerilog: always_ff - sequential behavior intent specification 27 | // SystemVerilog: iff conditional execution 28 | always_ff @(posedge clk iff (enable == 1) or negedge rst_) 29 | if (!rst_) 30 | out <= 0; 31 | else 32 | out <= data; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /sv_design_verification_v20-3/sv_src/files/scale_mux.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////////////// 2 | // (c) Copyright 2013 Cadence Design Systems, Inc. All Rights Reserved. 3 | // 4 | // File name : scale_mux.sv 5 | // Title : MUX Module 6 | // Project : SystemVerilog Training 7 | // Created : 2013-4-8 8 | // Description : Defines the mux module 9 | // Notes : 10 | // Scalable Mux - Specification: 11 | // when sel_a = 1, out = in_a 12 | // when sel_a = 0, out = in_b 13 | // when sel_a = x, out = x 14 | // 15 | /////////////////////////////////////////////////////////////////////////// 16 | 17 | module scale_mux #(WIDTH = 1) 18 | (output logic [WIDTH-1:0] out, 19 | input logic [WIDTH-1:0] in_a, 20 | input logic [WIDTH-1:0] in_b, 21 | input logic sel_a); 22 | 23 | timeunit 1ns; 24 | timeprecision 100ps; 25 | 26 | always_comb 27 | unique case (sel_a) 28 | 1'b1: out = in_a; 29 | 1'b0: out = in_b; 30 | default: out = 'x; 31 | endcase 32 | 33 | endmodule 34 | --------------------------------------------------------------------------------