├── PIM_estimation_tables ├── 32nm_data │ ├── 32nm.table.yaml │ └── data │ │ ├── ADC.csv │ │ ├── DAC.csv │ │ ├── SRAM.csv │ │ ├── intadder.csv │ │ ├── intmac.csv │ │ ├── sample_and_hold.csv │ │ └── shift_and_add.csv └── memristor_data │ ├── data │ ├── ReRAMcell_compute.csv │ └── ReRAMcell_storage.csv │ └── memristor.table.yaml ├── README.md ├── arch ├── components │ ├── A2D_conversion_system.yaml │ ├── ADC_SimpleMulticast.yaml │ ├── D2A_conversion_system.yaml │ ├── DAC_SimpleMulticast.yaml │ ├── digital_accumulation_system.yaml │ ├── memcell_compute.yaml │ ├── smartbuffer_SRAM.yaml │ └── storage.yaml └── system_PIM.yaml ├── constraints └── constraints.yaml ├── example_layer.yaml ├── example_outputs ├── timeloop-mapper.ART.yaml ├── timeloop-mapper.ART_summary.yaml ├── timeloop-mapper.ERT.yaml ├── timeloop-mapper.ERT_summary.yaml ├── timeloop-mapper.accelergy.log ├── timeloop-mapper.flattened_architecture.yaml ├── timeloop-mapper.log ├── timeloop-mapper.map+stats.xml ├── timeloop-mapper.map.txt └── timeloop-mapper.stats.txt └── mapper └── mapper.yaml /PIM_estimation_tables/32nm_data/32nm.table.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/32nm.table.yaml -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/ADC.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/ADC.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/DAC.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/DAC.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/SRAM.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/SRAM.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/intadder.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/intadder.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/intmac.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/intmac.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/sample_and_hold.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/sample_and_hold.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/32nm_data/data/shift_and_add.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/32nm_data/data/shift_and_add.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/memristor_data/data/ReRAMcell_compute.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/memristor_data/data/ReRAMcell_compute.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/memristor_data/data/ReRAMcell_storage.csv: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/memristor_data/data/ReRAMcell_storage.csv -------------------------------------------------------------------------------- /PIM_estimation_tables/memristor_data/memristor.table.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/PIM_estimation_tables/memristor_data/memristor.table.yaml -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/README.md -------------------------------------------------------------------------------- /arch/components/A2D_conversion_system.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/A2D_conversion_system.yaml -------------------------------------------------------------------------------- /arch/components/ADC_SimpleMulticast.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/ADC_SimpleMulticast.yaml -------------------------------------------------------------------------------- /arch/components/D2A_conversion_system.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/D2A_conversion_system.yaml -------------------------------------------------------------------------------- /arch/components/DAC_SimpleMulticast.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/DAC_SimpleMulticast.yaml -------------------------------------------------------------------------------- /arch/components/digital_accumulation_system.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/digital_accumulation_system.yaml -------------------------------------------------------------------------------- /arch/components/memcell_compute.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/memcell_compute.yaml -------------------------------------------------------------------------------- /arch/components/smartbuffer_SRAM.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/smartbuffer_SRAM.yaml -------------------------------------------------------------------------------- /arch/components/storage.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/components/storage.yaml -------------------------------------------------------------------------------- /arch/system_PIM.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/arch/system_PIM.yaml -------------------------------------------------------------------------------- /constraints/constraints.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/constraints/constraints.yaml -------------------------------------------------------------------------------- /example_layer.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_layer.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.ART.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.ART.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.ART_summary.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.ART_summary.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.ERT.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.ERT.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.ERT_summary.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.ERT_summary.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.accelergy.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.accelergy.log -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.flattened_architecture.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.flattened_architecture.yaml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.log -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.map+stats.xml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.map+stats.xml -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.map.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.map.txt -------------------------------------------------------------------------------- /example_outputs/timeloop-mapper.stats.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/example_outputs/timeloop-mapper.stats.txt -------------------------------------------------------------------------------- /mapper/mapper.yaml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Accelergy-Project/processing-in-memory-design/HEAD/mapper/mapper.yaml --------------------------------------------------------------------------------