├── 0. Getting Started ├── 01_StepOne.v └── 02_OutputZero.v ├── 1. Verilog Language ├── 1. Basics │ ├── 01_SimpleWire.v │ ├── 02_FourWire.v │ ├── 03_Inverter.v │ ├── 04_ANDgate.v │ ├── 05_NORgate.v │ ├── 06_XNORgate.v │ ├── 07_DeclaringWires.v │ └── 08_7458chip.v ├── 2. Vectors │ ├── 01_Vectors.v │ ├── 02_VectorsInMoreDetail.v │ ├── 03_VectorPartSelect.v │ ├── 04_BitwiseOperators.v │ ├── 05_FourInputGates.v │ ├── 06_VectorConcatenationOperator.v │ ├── 07_VectorReversal1.v │ ├── 08_ReplicationOperator.v │ └── 09_MoreReplication.v ├── 3. Modules: Hierarchy │ ├── 01_Modules.v │ ├── 02_ConnectingPortsByPosition.v │ ├── 03_ConnectingPortsByName.v │ ├── 04_ThreeModules.v │ ├── 05_ModulesAndVectors.v │ ├── 06_Adder1.v │ ├── 07_Adder2.v │ ├── 08_CarrySelectAdder.v │ └── 09_AdderSubtractor.v ├── 4. Procedures │ ├── 01_AlwaysBlocks(Combinational).v │ ├── 02_AlwaysBlocks(Clocked).v │ ├── 03_IfStatement.v │ ├── 04_IfStatementLatches.v │ ├── 05_CaseStatement.v │ ├── 06_PriorityEncoder.v │ ├── 07_PriorityEncoderWithCasez.v │ └── 08_AvoidingLatches.v └── 5. More Verilog Features │ ├── 01_ConditionalTernaryOperator.v │ ├── 02_ReductionOperators.v │ ├── 03_Reduction:EvenWiderGates.v │ ├── 04_CombinationalFor-Loop:VectorReversal2.v │ ├── 05_CombinationalFor-loop:255BitPopulationCount.v │ ├── 06_GenerateForLoop100bitBinaryAdder2.v │ └── 07_GenerateFor-loop:100digitBCDAdder.v ├── 2. Circuits ├── 1. Combinational Logic │ ├── 1. Basic Gates │ │ ├── 01_Wire.v │ │ ├── 02_GND.v │ │ ├── 03_NOR.v │ │ ├── 04_AnotherGate.v │ │ ├── 05_TwoGates.v │ │ ├── 06_MoreLogicGates.v │ │ ├── 07_7420Chip.v │ │ ├── 08_TruthTables.v │ │ ├── 09_TwoBit Equality.v │ │ ├── 10_SimpleCircuitA.v │ │ ├── 11_SimpleCircuitB.v │ │ ├── 12_CombineCircuitA&B.v │ │ ├── 13_RingOrVibrate.v │ │ ├── 14_Thermostat.v │ │ ├── 15_3BitPopulationCount.v │ │ ├── 16_GatesAndVectors.v │ │ └── 17_EvenLongerVectors.v │ ├── 2. Multiplexers │ │ ├── 01_2to1Multiplexer.v │ │ ├── 02_2to1BusMultiplexer.v │ │ ├── 03_9to1Multiplexer.v │ │ ├── 04_256to1Multiplexer.v │ │ └── 05_256to1-4bitMultiplexer.v │ ├── 3. Arithmetic Circuits │ │ ├── 01_HalfAdder.v │ │ ├── 02_FullAdder.v │ │ ├── 03_3bitBinaryAdder.v │ │ ├── 04_Adder.v │ │ ├── 05_SignedAdditionOverflow.v │ │ ├── 06_100bitBinaryAdder.v │ │ └── 07_4digitBCDAdder.v │ └── 4. Karnaugh Map to Circuit │ │ ├── 01_3Variable.v │ │ ├── 02_4VariableKmap1.v │ │ ├── 03_4VariableKmap2.v │ │ ├── 04_4VariableKmap3.v │ │ ├── 05_MinimumSOP&POS.v │ │ ├── 06_KarnaughMap1.v │ │ ├── 07_KarnaughMap2.v │ │ └── 08_KmapWithMux.v ├── 2. Sequential Logic │ ├── 1. Latches and Flip-Flops │ │ ├── 01_DFLipFlop.v │ │ ├── 02_DFlipFlops.v │ │ ├── 03_DFFWithReset.v │ │ ├── 04_DFFwithResetValue.v │ │ ├── 05_DFFwithAsynchronousReset.v │ │ ├── 06_DFFwithByteEnable.v │ │ ├── 07_DLatch.v │ │ ├── 08_DFF1.v │ │ ├── 09_DFF2.v │ │ ├── 10_DFF+Gate.v │ │ ├── 11_MuxAndDFF1.v │ │ ├── 12_MuxAndDFF2.v │ │ ├── 13_DFFsAndGates.v │ │ ├── 14_CreateCircuitFromTruthTable.v │ │ ├── 15_DetectAnEdge.v │ │ ├── 16_DetectBothEdges.v │ │ ├── 17_EdgeCaptureRegister.v │ │ └── 18_DualEdgeTrigerredFlipFlop.v │ ├── 2. Counters │ │ ├── 01_FourBitBinaryCounter.v │ │ ├── 02_DecadeCounter.v │ │ ├── 03_DecadeCounterAgain.v │ │ ├── 04_SlowDecadeCounter.v │ │ ├── 05_Counter1-12.v │ │ ├── 06_Counter1000.v │ │ ├── 07_4digitDecimalCounter.v │ │ └── 08_12-hourClock.v │ ├── 3. Shift Registers │ │ ├── 01_4bitShiftRegister.v │ │ ├── 02_LeftRightRotator.v │ │ ├── 03_LeftRightArithematicShiftby1or8.v │ │ ├── 04_5-BitLFSR.v │ │ ├── 05_3-BitLFSR.v │ │ ├── 06_32-BitLFSR.v │ │ ├── 07_ShiftRegister1.v │ │ ├── 08_ShiftRegister2.v │ │ └── 09_3-inputLUT.v │ ├── 4. More Circuits │ │ ├── 01_Rule90.v │ │ ├── 02_Rule110.v │ │ └── 03_ConwaysGameofLife16x16.v │ └── 5. Finite State Machines │ │ ├── 01_SimpleFSM1(asynchronousReset).v │ │ ├── 02_SimpleFSM1(synchronousReset).v │ │ ├── 03_SimpleFSM2(asycnhronousReset).v │ │ ├── 04_SimpleFSM2(synchronousReset).v │ │ ├── 05_SimpleStateTransition3.v │ │ ├── 06_SimpleOneHotStateTransition3.v │ │ ├── 07_SimpleFSM3(asynchronousReset).v │ │ ├── 08_SimpleFSM3(synchronousReset).v │ │ ├── 09_DesignAMooreFSM.v │ │ ├── 10_Lemmings1.v │ │ ├── 11_Lemmings2.v │ │ ├── 12_Lemmings3.v │ │ ├── 13_Lemmings4.v │ │ ├── 14_OneHotFSM.v │ │ ├── 15_PS2PacketParser.v │ │ ├── 16_PS2PacketParserWithDataPath.v │ │ ├── 17_SerialReciever.v │ │ ├── 18_SerialRecieverWithDataPath.v │ │ ├── 19_SerialRecieverWithParityChecking.v │ │ ├── 20_SequenceRecognition.v │ │ ├── 21_Q8DesignMealyFSM.v │ │ ├── 22_Q5aSerialTwoComplementer(Moore).v │ │ ├── 23_Q5bSerialTwoComplementer(Mealy).v │ │ ├── 24_Q3aFSM.v │ │ ├── 25_Q3bFSM.v │ │ ├── 26_Q3cFSMLogic.v │ │ ├── 27_Q6b:FSMNextStateLogic.v │ │ ├── 28_Q6cOneHotNextStateLogic.v │ │ ├── 29_Q6:FSM.v │ │ ├── 30_Q2a:FSM.v │ │ ├── 31_Q2b:OneHotFSMEquations.v │ │ ├── 32_Q2a:FSM.v │ │ └── 33_Q2b:AnotherFSM.v └── 3. Building Larger Circuits │ ├── 01_CounterWith1000Period.v │ ├── 02_4BitShiftRegisterAnd DownCounter.v │ ├── 03_FSM:Sequence1101Recognizer.v │ ├── 04_FSM:EnableShiftRegister.v │ ├── 05_FSM:TheCompleteFSM.v │ ├── 06_TheCompleteTimer.v │ └── 07_OneHotLogicEquations.v ├── 3. Verification : Reading Simulations ├── 1. Finding bugs in code │ ├── 01_Mux.v │ ├── 02_NAND.v │ ├── 03_Mux.v │ ├── 04_AddSub.v │ └── 05_CaseStatement.v └── 2. Build a circuit from a simulation waveform │ ├── 01_CombinationalCircuit1.v │ ├── 02_CombinationalCircuit2.v │ ├── 03_CombinationalCircuit3.v │ ├── 04_CombinationalCircuit4.v │ ├── 05_CombinationalCircuit5.v │ ├── 06_CombinationalCircuit6.v │ ├── 07_SequentialCircuit7.v │ ├── 08_SequentialCircuit8.v │ ├── 09_SequentialCircuit9.v │ └── 10_SequentialCircuit10.v ├── 4. Verification : Writing Testbenches ├── 01_Clock.v ├── 02_Testbench1.v ├── 03_ANDGate.v ├── 04_Testbench2.v └── 05_Tflip-flop.v ├── 5. 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