├── 0. Getting Started ├── 01_StepOne.v └── 02_OutputZero.v ├── 1. Verilog Language ├── 1. Basics │ ├── 01_SimpleWire.v │ ├── 03_Inverter.v │ ├── 04_ANDgate.v │ ├── 05_NORgate.v │ ├── 06_XNORgate.v │ ├── 02_FourWire.v │ ├── 07_DeclaringWires.v │ └── 08_7458chip.v ├── 5. More Verilog Features │ ├── 02_ReductionOperators.v │ ├── 03_Reduction:EvenWiderGates.v │ ├── 01_ConditionalTernaryOperator.v │ ├── 04_CombinationalFor-Loop:VectorReversal2.v │ ├── 05_CombinationalFor-loop:255BitPopulationCount.v │ ├── 06_GenerateForLoop100bitBinaryAdder2.v │ └── 07_GenerateFor-loop:100digitBCDAdder.v ├── 2. Vectors │ ├── 08_ReplicationOperator.v │ ├── 07_VectorReversal1.v │ ├── 06_VectorConcatenationOperator.v │ ├── 02_VectorsInMoreDetail.v │ ├── 03_VectorPartSelect.v │ ├── 09_MoreReplication.v │ ├── 01_Vectors.v │ ├── 05_FourInputGates.v │ └── 04_BitwiseOperators.v ├── 3. Modules: Hierarchy │ ├── 01_Modules.v │ ├── 02_ConnectingPortsByPosition.v │ ├── 06_Adder1.v │ ├── 03_ConnectingPortsByName.v │ ├── 04_ThreeModules.v │ ├── 09_AdderSubtractor.v │ ├── 05_ModulesAndVectors.v │ ├── 07_Adder2.v │ └── 08_CarrySelectAdder.v └── 4. Procedures │ ├── 01_AlwaysBlocks(Combinational).v │ ├── 02_AlwaysBlocks(Clocked).v │ ├── 03_IfStatement.v │ ├── 08_AvoidingLatches.v │ ├── 07_PriorityEncoderWithCasez.v │ ├── 04_IfStatementLatches.v │ ├── 05_CaseStatement.v │ └── 06_PriorityEncoder.v ├── 2. Circuits ├── 1. Combinational Logic │ ├── 1. Basic Gates │ │ ├── 02_GND.v │ │ ├── 10_SimpleCircuitA.v │ │ ├── 11_SimpleCircuitB.v │ │ ├── 01_Wire.v │ │ ├── 12_CombineCircuitA&B.v │ │ ├── 03_NOR.v │ │ ├── 04_AnotherGate.v │ │ ├── 05_TwoGates.v │ │ ├── 09_TwoBit Equality.v │ │ ├── 08_TruthTables.v │ │ ├── 07_7420Chip.v │ │ ├── 13_RingOrVibrate.v │ │ ├── 15_3BitPopulationCount.v │ │ ├── 14_Thermostat.v │ │ ├── 17_EvenLongerVectors.v │ │ ├── 16_GatesAndVectors.v │ │ └── 06_MoreLogicGates.v │ ├── 2. Multiplexers │ │ ├── 01_2to1Multiplexer.v │ │ ├── 04_256to1Multiplexer.v │ │ ├── 02_2to1BusMultiplexer.v │ │ ├── 05_256to1-4bitMultiplexer.v │ │ └── 03_9to1Multiplexer.v │ ├── 3. Arithmetic Circuits │ │ ├── 04_Adder.v │ │ ├── 01_HalfAdder.v │ │ ├── 02_FullAdder.v │ │ ├── 06_100bitBinaryAdder.v │ │ ├── 05_SignedAdditionOverflow.v │ │ ├── 03_3bitBinaryAdder.v │ │ └── 07_4digitBCDAdder.v │ └── 4. Karnaugh Map to Circuit │ │ ├── 06_KarnaughMap1.v │ │ ├── 01_3Variable.v │ │ ├── 07_KarnaughMap2.v │ │ ├── 03_4VariableKmap2.v │ │ ├── 02_4VariableKmap1.v │ │ ├── 08_KmapWithMux.v │ │ ├── 05_MinimumSOP&POS.v │ │ └── 04_4VariableKmap3.v ├── 2. Sequential Logic │ ├── 1. Latches and Flip-Flops │ │ ├── 07_DLatch.v │ │ ├── 01_DFLipFlop.v │ │ ├── 02_DFlipFlops.v │ │ ├── 10_DFF+Gate.v │ │ ├── 09_DFF2.v │ │ ├── 08_DFF1.v │ │ ├── 11_MuxAndDFF1.v │ │ ├── 16_DetectBothEdges.v │ │ ├── 04_DFFwithResetValue.v │ │ ├── 03_DFFWithReset.v │ │ ├── 05_DFFwithAsynchronousReset.v │ │ ├── 12_MuxAndDFF2.v │ │ ├── 13_DFFsAndGates.v │ │ ├── 18_DualEdgeTrigerredFlipFlop.v │ │ ├── 14_CreateCircuitFromTruthTable.v │ │ ├── 17_EdgeCaptureRegister.v │ │ ├── 15_DetectAnEdge.v │ │ └── 06_DFFwithByteEnable.v │ ├── 2. Counters │ │ ├── 01_FourBitBinaryCounter.v │ │ ├── 02_DecadeCounter.v │ │ ├── 03_DecadeCounterAgain.v │ │ ├── 04_SlowDecadeCounter.v │ │ ├── 06_Counter1000.v │ │ ├── 05_Counter1-12.v │ │ ├── 07_4digitDecimalCounter.v │ │ └── 08_12-hourClock.v │ ├── 5. Finite State Machines │ │ ├── 28_Q6cOneHotNextStateLogic.v │ │ ├── 31_Q2b:OneHotFSMEquations.v │ │ ├── 06_SimpleOneHotStateTransition3.v │ │ ├── 05_SimpleStateTransition3.v │ │ ├── 23_Q5bSerialTwoComplementer(Mealy).v │ │ ├── 27_Q6b:FSMNextStateLogic.v │ │ ├── 03_SimpleFSM2(asycnhronousReset).v │ │ ├── 04_SimpleFSM2(synchronousReset).v │ │ ├── 26_Q3cFSMLogic.v │ │ ├── 02_SimpleFSM1(synchronousReset).v │ │ ├── 25_Q3bFSM.v │ │ ├── 08_SimpleFSM3(synchronousReset).v │ │ ├── 01_SimpleFSM1(asynchronousReset).v │ │ ├── 07_SimpleFSM3(asynchronousReset).v │ │ ├── 21_Q8DesignMealyFSM.v │ │ ├── 15_PS2PacketParser.v │ │ ├── 10_Lemmings1.v │ │ ├── 24_Q3aFSM.v │ │ ├── 14_OneHotFSM.v │ │ ├── 22_Q5aSerialTwoComplementer(Moore).v │ │ ├── 11_Lemmings2.v │ │ ├── 29_Q6:FSM.v │ │ ├── 30_Q2a:FSM.v │ │ ├── 16_PS2PacketParserWithDataPath.v │ │ ├── 20_SequenceRecognition.v │ │ ├── 17_SerialReciever.v │ │ ├── 32_Q2a:FSM.v │ │ ├── 09_DesignAMooreFSM.v │ │ ├── 18_SerialRecieverWithDataPath.v │ │ ├── 12_Lemmings3.v │ │ ├── 19_SerialRecieverWithParityChecking.v │ │ ├── 33_Q2b:AnotherFSM.v │ │ └── 13_Lemmings4.v │ ├── 3. Shift Registers │ │ ├── 04_5-BitLFSR.v │ │ ├── 06_32-BitLFSR.v │ │ ├── 02_LeftRightRotator.v │ │ ├── 05_3-BitLFSR.v │ │ ├── 07_ShiftRegister1.v │ │ ├── 01_4bitShiftRegister.v │ │ ├── 09_3-inputLUT.v │ │ ├── 08_ShiftRegister2.v │ │ └── 03_LeftRightArithematicShiftby1or8.v │ └── 4. More Circuits │ │ ├── 01_Rule90.v │ │ ├── 02_Rule110.v │ │ └── 03_ConwaysGameofLife16x16.v └── 3. Building Larger Circuits │ ├── 01_CounterWith1000Period.v │ ├── 02_4BitShiftRegisterAnd DownCounter.v │ ├── 04_FSM:EnableShiftRegister.v │ ├── 03_FSM:Sequence1101Recognizer.v │ ├── 07_OneHotLogicEquations.v │ ├── 05_FSM:TheCompleteFSM.v │ └── 06_TheCompleteTimer.v ├── 3. Verification : Reading Simulations ├── 1. Finding bugs in code │ ├── 02_NAND.v │ ├── 01_Mux.v │ ├── 03_Mux.v │ ├── 04_AddSub.v │ └── 05_CaseStatement.v └── 2. Build a circuit from a simulation waveform │ ├── 01_CombinationalCircuit1.v │ ├── 04_CombinationalCircuit4.v │ ├── 07_SequentialCircuit7.v │ ├── 03_CombinationalCircuit3.v │ ├── 02_CombinationalCircuit2.v │ ├── 08_SequentialCircuit8.v │ ├── 10_SequentialCircuit10.v │ ├── 09_SequentialCircuit9.v │ ├── 05_CombinationalCircuit5.v │ └── 06_CombinationalCircuit6.v ├── 4. Verification : Writing Testbenches ├── 01_Clock.v ├── 03_ANDGate.v ├── 02_Testbench1.v ├── 04_Testbench2.v └── 05_Tflip-flop.v ├── README.md ├── 5. CS450 ├── 01_Timer.v ├── 03_HistoryShift.v ├── 02_Counter2bc.v └── 04_GShare.v └── LICENSE /0. Getting Started/01_StepOne.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | output one 3 | ); 4 | 5 | assign one = 1; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /0. Getting Started/02_OutputZero.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | output zero 3 | ); 4 | 5 | assign zero = 0; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/01_SimpleWire.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | output out ); 4 | 5 | assign out = in; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/02_GND.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | output out 3 | ); 4 | 5 | assign out = 0; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/03_Inverter.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | output out 4 | ); 5 | 6 | assign out = ~in; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/10_SimpleCircuitA.v: -------------------------------------------------------------------------------- 1 | module top_module (input x, input y, output z); 2 | assign z = (x^y) & x; 3 | endmodule 4 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/11_SimpleCircuitB.v: -------------------------------------------------------------------------------- 1 | module top_module ( input x, input y, output z ); 2 | assign z = ~(x ^ y); 3 | endmodule 4 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/01_Wire.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in, 3 | output out 4 | ); 5 | 6 | assign out = in; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/04_ANDgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out 5 | ); 6 | 7 | assign out = a & b; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/05_NORgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out 5 | ); 6 | 7 | assign out = ~(a | b); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/06_XNORgate.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output out 5 | ); 6 | 7 | assign out = ~(a ^ b); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/02_ReductionOperators.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output parity 4 | ); 5 | 6 | assign parity = ^in; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/2. Multiplexers/01_2to1Multiplexer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, sel, 3 | output out 4 | ); 5 | 6 | assign out = sel ? b : a; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/08_ReplicationOperator.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output [31:0] out 4 | ); 5 | 6 | assign out = { { 24{in[7] } } , in[7:0] }; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/12_CombineCircuitA&B.v: -------------------------------------------------------------------------------- 1 | module top_module (input x, input y, output z); 2 | assign z = (((x ^ y) & x) | (~(x ^ y))) ^ (((x ^ y) & x) & (~(x ^ y))); 3 | endmodule 4 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/03_NOR.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | output out 5 | ); 6 | 7 | assign out = ~(in1 | in2); 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/04_AnotherGate.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | output out 5 | ); 6 | 7 | assign out = in1 & ~in2; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/02_FourWire.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a,b,c, 3 | output w,x,y,z ); 4 | 5 | assign w = a; 6 | assign x = b; 7 | assign y = b; 8 | assign z = c; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/07_VectorReversal1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output [7:0] out 4 | ); 5 | 6 | assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/04_Adder.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] x, 3 | input [3:0] y, 4 | output [4:0] sum 5 | ); 6 | 7 | assign sum = x + y; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/06_KarnaughMap1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:1] x, 3 | output f 4 | ); 5 | 6 | assign f = (x[3] & ~x[1]) | (~x[3] & x[1] & x[2]); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/06_VectorConcatenationOperator.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:0] a, b, c, d, e, f, 3 | output [7:0] w, x, y, z 4 | ); 5 | 6 | assign {w,x,y,z} = {a,b,c,d,e,f,2'b11}; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/01_HalfAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, 3 | output cout, sum 4 | ); 5 | 6 | assign sum = a ^ b; 7 | assign cout = a & b; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/2. Multiplexers/04_256to1Multiplexer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [255:0] in, 3 | input [7:0] sel, 4 | output out 5 | ); 6 | 7 | assign out = in[sel]; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/01_3Variable.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | output out 6 | ); 7 | 8 | assign out = a | b | c; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/1. Finding bugs in code/02_NAND.v: -------------------------------------------------------------------------------- 1 | module top_module (input a, input b, input c, output out); 2 | wire out_t; 3 | assign out = ~out_t; 4 | andgate inst1 ( out_t ,a, b, c,1,1); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/05_TwoGates.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input in1, 3 | input in2, 4 | input in3, 5 | output out 6 | ); 7 | 8 | assign out = in3 ^ ~(in1 ^ in2); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/2. Multiplexers/02_2to1BusMultiplexer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input sel, 4 | output [99:0] out 5 | ); 6 | 7 | assign out = sel ? b : a; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/01_Modules.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | output out 5 | ); 6 | 7 | mod_a inst( 8 | .out(out), 9 | .in1(a), 10 | .in2(b) 11 | ); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/07_KarnaughMap2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [4:1] x, 3 | output f 4 | ); 5 | 6 | assign f = (x[3] & ~x[1]) | (x[2] & x[3] & x[4]) | (~x[4] & ~x[2]); 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/07_DLatch.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input d, 3 | input ena, 4 | output q 5 | ); 6 | 7 | always@(*)begin 8 | if(ena) 9 | q <= d; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/01_CombinationalCircuit1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | output q 5 | ); 6 | 7 | assign q = a & b;\ 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/09_TwoBit Equality.v: -------------------------------------------------------------------------------- 1 | module top_module ( input [1:0] A, input [1:0] B, output z ); 2 | always @(*) 3 | begin 4 | if(A == B) 5 | z = 1; 6 | else 7 | z = 0; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/01_DFLipFlop.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | output reg q 5 | ); 6 | 7 | always@(posedge clk)begin 8 | q <= d; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/02_DFlipFlops.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] d, 4 | output [7:0] q 5 | ); 6 | always@(posedge clk)begin 7 | q <= d; 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/2. Multiplexers/05_256to1-4bitMultiplexer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [1023:0] in, 3 | input [7:0] sel, 4 | output [3:0] out 5 | ); 6 | 7 | assign out = in[4*sel + 3 -: 4]; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/1. Finding bugs in code/01_Mux.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input sel, 3 | input [7:0] a, 4 | input [7:0] b, 5 | output [7:0] out 6 | ); 7 | 8 | assign out = sel ? a : b ; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/08_TruthTables.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input x3, 3 | input x2, 4 | input x1, // three inputs 5 | output f // one output 6 | ); 7 | 8 | assign f = x1&x3 | ~x3&x2; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/02_FullAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, cin, 3 | output cout, sum 4 | ); 5 | 6 | assign sum = a ^ b ^ cin; 7 | assign cout = a & b | a & cin | b & cin; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/03_4VariableKmap2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out 7 | ); 8 | 9 | assign out = a | (c & ~b); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/10_DFF+Gate.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input in, 4 | output out 5 | ); 6 | 7 | always@(posedge clk)begin 8 | out <= out ^ in; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/06_100bitBinaryAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input cin, 4 | output cout, 5 | output [99:0] sum 6 | ); 7 | 8 | assign {cout,sum} = a + b + cin; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/04_CombinationalCircuit4.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q 7 | ); 8 | 9 | assign q = b | c; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /4. Verification : Writing Testbenches/01_Clock.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | module top_module (); 3 | reg clk; 4 | initial clk = 0; 5 | always begin 6 | #5 clk = ~clk; 7 | end 8 | 9 | dut u_dut( 10 | .clk(clk) 11 | ); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/07_SequentialCircuit7.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | output q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | q <= ~a; 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/02_4VariableKmap1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out 7 | ); 8 | 9 | assign out = (~b & ~c) | (~a & ~d) | (~a & b & c) | (a & c & d); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/02_VectorsInMoreDetail.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module top_module( 3 | input wire [15:0] in, 4 | output wire [7:0] out_hi, 5 | output wire [7:0] out_lo 6 | ); 7 | 8 | assign out_hi = in[15:8]; 9 | assign out_lo = in[7:0]; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/03_VectorPartSelect.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] in, 3 | output [31:0] out 4 | ); 5 | 6 | assign out[31:24] = in[7:0]; 7 | assign out[23:16] = in[15:8]; 8 | assign out[15:8] = in[23:16]; 9 | assign out[7:0] = in[31:24]; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/03_CombinationalCircuit3.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q 7 | ); 8 | 9 | assign q = (b & d) | (b & c) | (a & d) | (a & c); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/03_Reduction:EvenWiderGates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] in, 3 | output out_and, 4 | output out_or, 5 | output out_xor 6 | ); 7 | 8 | assign out_and = ∈ 9 | assign out_or = |in; 10 | assign out_xor = ^in; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/09_DFF2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | input r, 5 | output q 6 | ); 7 | always@(posedge clk)begin 8 | if(r) 9 | q <= 0; 10 | else 11 | q <= d; 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/01_AlwaysBlocks(Combinational).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | output wire out_assign, 5 | output reg out_alwaysblock 6 | ); 7 | 8 | assign out_assign = a & b; 9 | 10 | always @(*) 11 | out_alwaysblock = a & b; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/07_7420Chip.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input p1a, p1b, p1c, p1d, 3 | output p1y, 4 | input p2a, p2b, p2c, p2d, 5 | output p2y 6 | ); 7 | 8 | assign p1y = ~(p1a & p1b & p1c & p1d); 9 | assign p2y = ~(p2a & p2b & p2c & p2d); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/08_KmapWithMux.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input c, 3 | input d, 4 | output [3:0] mux_in 5 | ); 6 | 7 | assign mux_in[0] = c | d; 8 | assign mux_in[1] = 0; 9 | assign mux_in[2] = ~d; 10 | assign mux_in[3] = c & d; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/01_FourBitBinaryCounter.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [3:0] q 5 | ); 6 | 7 | always@(posedge clk)begin 8 | if(reset) 9 | q <= 0; 10 | else 11 | q <= q + 1'b1; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/28_Q6cOneHotNextStateLogic.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [6:1] y, 3 | input w, 4 | output Y2, 5 | output Y4 6 | ); 7 | 8 | assign Y2 = y[1] & (~w); 9 | assign Y4 = (y[2] & w) | (y[3] & w) | (y[5] & w) | (y[6] & w); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/05_SignedAdditionOverflow.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] a, 3 | input [7:0] b, 4 | output [7:0] s, 5 | output overflow 6 | ); 7 | 8 | assign s = a + b; 9 | assign overflow = (~(a[7] ^ b[7])) & (s[7] != a[7]); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/02_DecadeCounter.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [3:0] q 5 | ); 6 | 7 | always@(posedge clk) begin 8 | if(reset | q==9) 9 | q <= 0; 10 | else 11 | q <= q + 1'b1; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/09_MoreReplication.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, b, c, d, e, 3 | output [24:0] out 4 | ); 5 | 6 | wire [24:0] w1,w2; 7 | 8 | assign w1 = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}}; 9 | assign w2 = { { 5{a,b,c,d,e} } }; 10 | assign out = ~(w1 ^ w2); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/08_DFF1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | input ar, 5 | output q 6 | ); 7 | 8 | always@(posedge clk, posedge ar)begin 9 | if(ar) 10 | q <= 0; 11 | else 12 | q <= d; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/11_MuxAndDFF1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input L, 4 | input r_in, 5 | input q_in, 6 | output reg Q 7 | ); 8 | 9 | always @(posedge clk) begin 10 | if(L) 11 | Q <= r_in; 12 | else 13 | Q <= q_in; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/03_DecadeCounterAgain.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [3:0] q 5 | ); 6 | 7 | always@(posedge clk) begin 8 | if(reset | q==10) 9 | q <= 1'b1; 10 | else 11 | q <= q + 1'b1; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/31_Q2b:OneHotFSMEquations.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [5:0] y, 3 | input w, 4 | output Y1, 5 | output Y3 6 | ); 7 | 8 | assign Y1 = y[0] & w; 9 | assign Y3 = (y[1] & (~w)) | (y[2] & (~w)) | (y[4] & (~w)) | (y[5] & (~w)); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/02_CombinationalCircuit2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output q 7 | ); 8 | 9 | assign q = (a + b + c + d == 0 | a + b + c + d == 2 | a + b + c + d == 4); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/01_Vectors.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input wire [2:0] vec, 3 | output wire [2:0] outv, 4 | output wire o2, 5 | output wire o1, 6 | output wire o0 7 | ); 8 | 9 | assign outv = vec; 10 | assign o0 = vec[0]; 11 | assign o1 = vec[1]; 12 | assign o2 = vec[2]; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/13_RingOrVibrate.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input ring, 3 | input vibrate_mode, 4 | output ringer, // Make sound 5 | output motor // Vibrate 6 | ); 7 | assign ringer = ring & (~vibrate_mode); 8 | assign motor = ring & vibrate_mode; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/16_DetectBothEdges.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] in, 4 | output [7:0] anyedge 5 | ); 6 | 7 | reg [7:0] in_last; 8 | always @(posedge clk) begin 9 | in_last <= in; 10 | anyedge <= in ^ in_last; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/04_DFFwithResetValue.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | always@(negedge clk)begin 8 | if(reset) 9 | q <= 8'h34; 10 | else 11 | q <= d; 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/02_ConnectingPortsByPosition.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out1, 7 | output out2 8 | ); 9 | 10 | mod_a inst( 11 | out1, 12 | out2, 13 | a, 14 | b, 15 | c, 16 | d 17 | ); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/05_MinimumSOP&POS.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out_sop, 7 | output out_pos 8 | ); 9 | 10 | assign out_sop = (c & d) | (~a & ~b & c); 11 | assign out_pos = (c) & (~a | b) & (d | ~b); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/03_DFFWithReset.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | 8 | always@(posedge clk)begin 9 | if(reset) 10 | q <= 0; 11 | else 12 | q <= d; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/01_ConditionalTernaryOperator.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] a, b, c, d, 3 | output [7:0] min 4 | ); 5 | 6 | wire [7:0] w1, w2, w3; 7 | 8 | assign w1 = (a < b) ? a : b; 9 | assign w2 = (c < w1) ? c : w1; 10 | assign w3 = (d < w2) ? d : w2; 11 | assign min = w3; 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/04_5-BitLFSR.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, 4 | output [4:0] q 5 | ); 6 | always @(posedge clk) begin 7 | if(reset) 8 | q <= 5'h1; 9 | else 10 | q <= {q[0]^1'b0, q[4], q[3]^q[0], q[2], q[1]}; 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/4. Karnaugh Map to Circuit/04_4VariableKmap3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out 7 | ); 8 | 9 | assign out = (~a&b&~c&~d) | (a&~b&~c&~d) | (~a&~b&~c&d) | (a&b&~c&d) | (~a&b&c&d) | (a&~b&c&d) | (~a&~b&c&~d) | (a&b&c&~d); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/05_FourInputGates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [3:0] in, 3 | output out_and, 4 | output out_or, 5 | output out_xor 6 | ); 7 | 8 | assign out_and = (in[3] & in[2] & in[1] & in[0]); 9 | assign out_or = (in[3] | in[2] | in[1] | in[0]); 10 | assign out_xor = (in[3] ^ in[2] ^ in[1] ^ in[0]); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/05_DFFwithAsynchronousReset.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, 4 | input [7:0] d, 5 | output [7:0] q 6 | ); 7 | always@(posedge clk,posedge areset)begin 8 | if(areset) 9 | q <= 0; 10 | else 11 | q <= d; 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/07_DeclaringWires.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | module top_module( 3 | input a, 4 | input b, 5 | input c, 6 | input d, 7 | output out, 8 | output out_n 9 | ); 10 | wire w1,w2; 11 | 12 | assign w1 = a & b; 13 | assign w2 = c & d; 14 | assign out = w1 | w2; 15 | assign out_n = ~out; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/06_Adder1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | ); 6 | 7 | wire w1; 8 | reg x = 0; 9 | 10 | add16 inst0(.a(a[15:0]), .b(b[15:0]), .sum(sum[15:0]), .cin(x), .cout(w1)); 11 | add16 inst1(.a(a[31:16]), .b(b[31:16]), .sum(sum[31:16]), .cin(w1)); 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/01_CounterWith1000Period.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output [9:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if (reset) q <= 0; 9 | else begin 10 | if (q < 999) q <= q + 1'b1; 11 | else q <= 0; 12 | end 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/15_3BitPopulationCount.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] in, 3 | output [1:0] out 4 | ); 5 | 6 | integer i; 7 | 8 | always @(*) begin 9 | out = 2'b0; 10 | for(i = 0; i < 3; i ++) begin 11 | if(in[i]) 12 | out = out + 2'b1; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/12_MuxAndDFF2.v: -------------------------------------------------------------------------------- 1 | module top_module 2 | ( 3 | input clk, 4 | input w, R, E, L, 5 | output Q 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if(L) Q <= R; 10 | else begin 11 | if(E) Q <= w; 12 | else Q <= Q; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/4. More Circuits/01_Rule90.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [511:0] data, 5 | output [511:0] q 6 | ); 7 | 8 | always@(posedge clk) begin 9 | if(load) 10 | q <= data; 11 | else 12 | q <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0}; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/03_ConnectingPortsByName.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input a, 3 | input b, 4 | input c, 5 | input d, 6 | output out1, 7 | output out2 8 | ); 9 | 10 | mod_a inst( 11 | .out1(out1), 12 | .out2(out2), 13 | .in1(a), 14 | .in2(b), 15 | .in3(c), 16 | .in4(d) 17 | ); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/13_DFFsAndGates.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input x, 4 | output z 5 | ); 6 | 7 | reg [2:0] Q; 8 | always@(posedge clk)begin 9 | Q[0] <= Q[0] ^ x; 10 | Q[1] <= ~Q[1] & x; 11 | Q[2] <= ~Q[2] | x; 12 | end 13 | 14 | assign z = ~(| Q); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/06_32-BitLFSR.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, 4 | output [31:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if(reset) 9 | q <= 32'h1; 10 | else begin 11 | q <= {0^q[0], q[31:23], q[22]^q[0], q[21:3], q[2]^q[0], q[1]^q[0]}; 12 | end 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/08_SequentialCircuit8.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clock, 3 | input a, 4 | output p, 5 | output q ); 6 | 7 | always @(*) begin 8 | if(clock) p = a; 9 | end 10 | 11 | always @(negedge clock) begin 12 | q <= p; 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/10_SequentialCircuit10.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | input b, 5 | output q, 6 | output state 7 | ); 8 | 9 | always @ (posedge clk) begin 10 | if(a == b) 11 | state <= a; 12 | else 13 | state <= state; 14 | end 15 | assign q = (a == b) ? state : (~state); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/14_Thermostat.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input too_cold, 3 | input too_hot, 4 | input mode, 5 | input fan_on, 6 | output heater, 7 | output aircon, 8 | output fan 9 | ); 10 | 11 | assign heater = mode & too_cold; 12 | assign aircon = (~mode) & too_hot; 13 | assign fan = fan_on | (heater | aircon); 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /1. Verilog Language/2. Vectors/04_BitwiseOperators.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] a, 3 | input [2:0] b, 4 | output [2:0] out_or_bitwise, 5 | output out_or_logical, 6 | output [5:0] out_not 7 | ); 8 | 9 | assign out_or_bitwise = a | b; 10 | assign out_or_logical = a || b; 11 | assign out_not[5:3] = ~(b[2:0]); 12 | assign out_not[2:0] = ~(a[2:0]); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/17_EvenLongerVectors.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] in, 3 | output [98:0] out_both, 4 | output [99:1] out_any, 5 | output [99:0] out_different 6 | ); 7 | 8 | assign out_both = in[98:0] & in[99:1]; 9 | assign out_any = in[98:0] | in[99:1]; 10 | assign out_different = {(in[99] ^ in[0]), in[98:0] ^ in[99:1]}; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/04_SlowDecadeCounter.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input slowena, 4 | input reset, 5 | output [3:0] q 6 | ); 7 | 8 | always@(posedge clk)begin 9 | if(reset | (slowena & q==9)) 10 | q <= 0; 11 | else if(slowena) 12 | q <= q + 1'b1; 13 | else 14 | q <= q; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/09_SequentialCircuit9.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input a, 4 | output [3:0] q 5 | ); 6 | 7 | always @(posedge clk) begin 8 | if (a) q <= 4; 9 | else begin 10 | if (q < 6) q <= q + 1; 11 | else q <= 0; 12 | end 13 | end 14 | 15 | endmodule 16 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/18_DualEdgeTrigerredFlipFlop.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | output q 5 | ); 6 | 7 | reg [1:0] r; 8 | 9 | always @(posedge clk) begin 10 | r[0] <= d; 11 | end 12 | 13 | always @(negedge clk) begin 14 | r[1] <= d; 15 | end 16 | 17 | assign q = (clk) ? r[0] : r[1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/04_CombinationalFor-Loop:VectorReversal2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [99:0] in, 3 | output reg [99:0] out 4 | ); 5 | 6 | always @(*) begin 7 | for (int i=0 ; i < $bits(out) ; i++) // $bits() is a system function that returns the width of a signal. 8 | out[i] = in[$bits(out)-i-1]; // $bits(out) is 100 because out is 100 bits wide. 9 | end 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/05_CombinationalFor-loop:255BitPopulationCount.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [254:0] in, 3 | output [7:0] out 4 | ); 5 | 6 | always @(*) begin 7 | out = 0; 8 | for(int i = 0; i < $bits(in); i++) begin 9 | if(in[i]) 10 | out = out + 8'b1; 11 | else 12 | out = out + 8'b0; 13 | end 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/4. More Circuits/02_Rule110.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [511:0] data, 5 | output [511:0] q 6 | ); 7 | 8 | always @(posedge clk) begin 9 | if (load) begin 10 | q <= data; 11 | end 12 | else begin 13 | q <= (((q[511:0] ^ {q[510:0], 1'b0}) & q[511:1]) | ((q[511:0] | {q[510:0], 1'b0}) & (~q[511:1]))); 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /4. Verification : Writing Testbenches/03_ANDGate.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | module top_module(); 3 | reg [1:0] in; 4 | wire out; 5 | 6 | initial begin 7 | in = 2'b00; 8 | #10; 9 | in = 2'b01; 10 | #10; 11 | in = 2'b10; 12 | #10; 13 | in = 2'b11; 14 | end 15 | andgate u_andgate( 16 | .in(in), 17 | .out(out) 18 | ); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /1. Verilog Language/1. Basics/08_7458chip.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input p1a, p1b, p1c, p1d, p1e, p1f, 3 | output p1y, 4 | input p2a, p2b, p2c, p2d, 5 | output p2y 6 | ); 7 | 8 | wire w1,w2,w3,w4; 9 | 10 | assign w1 = p2a & p2b; 11 | assign w2 = p2c & p2d; 12 | assign w3 = p1a & p1b & p1c; 13 | assign w4 = p1d & p1e & p1f; 14 | assign p1y = w3 | w4; 15 | assign p2y = w1 | w2; 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/14_CreateCircuitFromTruthTable.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input j, 4 | input k, 5 | output Q); 6 | 7 | always @(posedge clk) begin 8 | case({j, k}) 9 | 2'b00 : Q <= Q; 10 | 2'b01 : Q <= 0; 11 | 2'b10 : Q <= 1; 12 | 2'b11 : Q <= ~Q; 13 | endcase 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/02_AlwaysBlocks(Clocked).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input a, 4 | input b, 5 | output wire out_assign, 6 | output reg out_always_comb, 7 | output reg out_always_ff 8 | ); 9 | 10 | assign out_assign = a ^ b; 11 | 12 | always@(*) 13 | out_always_comb = a ^ b; 14 | 15 | always@(posedge clk) 16 | out_always_ff = a ^ b; 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/03_IfStatement.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, 3 | input b, 4 | input sel_b1, 5 | input sel_b2, 6 | output wire out_assign, 7 | output reg out_always 8 | ); 9 | 10 | assign out_assign = (sel_b1 && sel_b2) ? b : a; 11 | 12 | always @(*) begin 13 | if(sel_b1 && sel_b2) 14 | out_always = b; 15 | else 16 | out_always = a; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/04_ThreeModules.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input d, 4 | output q 5 | ); 6 | 7 | wire w1,w2; 8 | 9 | my_dff inst1( 10 | .clk(clk), 11 | .d(d), 12 | .q(w1) 13 | ); 14 | 15 | my_dff inst2( 16 | .clk(clk), 17 | .d(w1), 18 | .q(w2) 19 | ); 20 | 21 | my_dff inst3( 22 | .clk(clk), 23 | .d(w2), 24 | .q(q) 25 | ); 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/17_EdgeCaptureRegister.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [31:0] in, 5 | output [31:0] out 6 | ); 7 | 8 | reg [31:0] in_last; 9 | 10 | always @(posedge clk) begin 11 | in_last <= in; 12 | if(reset) 13 | out <= 0; 14 | else begin 15 | out <= out | (in_last & ~in); 16 | end 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/02_LeftRightRotator.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [1:0] ena, 5 | input [99:0] data, 6 | output reg [99:0] q 7 | ); 8 | 9 | always@(posedge clk)begin 10 | if(load) q <= data; 11 | else begin 12 | if(ena == 2'b01) q <= {q[0], q[99:1]}; 13 | else if(ena == 2'b10) q<= {q[98:0], q[99]}; 14 | else q <= q; 15 | end 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/1. Finding bugs in code/03_Mux.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [1:0] sel, 3 | input [7:0] a, 4 | input [7:0] b, 5 | input [7:0] c, 6 | input [7:0] d, 7 | output [7:0] out ); // 8 | 9 | wire [7:0] mux0; 10 | wire [7:0] mux1; 11 | 12 | mux2 u_mux2_1 ( sel[0], a, b, mux0 ); 13 | mux2 u_mux2_2 ( sel[0], c, d, mux1 ); 14 | mux2 u_mux2_3 ( sel[1], mux0, mux1, out ); 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /4. Verification : Writing Testbenches/02_Testbench1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | module top_module ( output reg A, output reg B ); 3 | 4 | // generate input patterns here 5 | initial begin 6 | A = 0; 7 | B = 0; 8 | #10; 9 | A = 1; 10 | B = 0; 11 | #5; 12 | A = 1; 13 | B = 1; 14 | #5; 15 | A = 0; 16 | B = 1; 17 | #20; 18 | A = 0; 19 | B = 0; 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/1. Finding bugs in code/04_AddSub.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input do_sub, 3 | input [7:0] a, 4 | input [7:0] b, 5 | output reg [7:0] out, 6 | output reg result_is_zero 7 | ); 8 | 9 | always @(*) begin 10 | case (do_sub) 11 | 0: out = a+b; 12 | 1: out = a-b; 13 | endcase 14 | if (out == 0) 15 | result_is_zero = 1; 16 | else result_is_zero = 0; 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/05_CombinationalCircuit5.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] a, 3 | input [3:0] b, 4 | input [3:0] c, 5 | input [3:0] d, 6 | input [3:0] e, 7 | output [3:0] q 8 | ); 9 | 10 | always @(*) begin 11 | case (c) 12 | 0 : q = b; 13 | 1 : q = e; 14 | 2 : q = a; 15 | 3 : q = d; 16 | default : q = 4'hf; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/16_GatesAndVectors.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [3:0] in, 3 | output [2:0] out_both, 4 | output [3:1] out_any, 5 | output [3:0] out_different 6 | ); 7 | 8 | integer i; 9 | 10 | always @(*) 11 | begin 12 | out_different[3] = in[3] ^ in[0]; 13 | for(i=0; i<3; i++) 14 | begin 15 | out_both[i] = in[i] & in[i+1]; 16 | out_any[i+1] = in[i] | in[i+1]; 17 | out_different[i] = in[i] ^ in[i+1]; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/02_4BitShiftRegisterAnd DownCounter.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input shift_ena, 4 | input count_ena, 5 | input data, 6 | output [3:0] q 7 | ); 8 | 9 | reg [3:0] shift_temp; 10 | 11 | always @(posedge clk) begin 12 | if (shift_ena) begin 13 | shift_temp <= {shift_temp[2:0], data}; 14 | end 15 | else if (count_ena) begin 16 | shift_temp <= shift_temp - 1'b1; 17 | end 18 | end 19 | 20 | assign q = shift_temp; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/08_AvoidingLatches.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [15:0] scancode, 3 | output reg left, 4 | output reg down, 5 | output reg right, 6 | output reg up 7 | ); 8 | 9 | always @(*) begin 10 | left = 0; down = 0; right = 0; up = 0; 11 | case(scancode) 12 | 16'he06b : left = 1; 13 | 16'he072 : down = 1; 14 | 16'he074 : right = 1; 15 | 16'he075 : up = 1; 16 | default : ; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/05_3-BitLFSR.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [2:0] SW, 3 | input [1:0] KEY, 4 | output [2:0] LEDR 5 | ); 6 | 7 | wire L; 8 | wire clk; 9 | wire [2:0] R; 10 | reg [2:0] Q; 11 | 12 | assign R = SW; 13 | assign clk = KEY[0]; 14 | assign L = KEY[1]; 15 | 16 | always @(posedge clk) begin 17 | if(L) 18 | Q <= R; 19 | else 20 | Q <= {Q[2]^Q[1], Q[0], Q[2]}; 21 | end 22 | 23 | assign LEDR = Q; 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/07_ShiftRegister1.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, 4 | input in, 5 | output out 6 | ); 7 | 8 | reg [2:0] Q; 9 | 10 | always @(posedge clk) begin 11 | if(resetn) begin 12 | Q[0] <= in; 13 | Q[1] <= Q[0]; 14 | Q[2] <= Q[1]; 15 | out <= Q[2]; 16 | end 17 | else begin 18 | Q <= 3'b0; 19 | out <= 1'b0; 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/1. Basic Gates/06_MoreLogicGates.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input a, b, 3 | output out_and, 4 | output out_or, 5 | output out_xor, 6 | output out_nand, 7 | output out_nor, 8 | output out_xnor, 9 | output out_anotb 10 | ); 11 | 12 | assign out_and = a & b; 13 | assign out_or = a | b; 14 | assign out_xor = a ^ b; 15 | assign out_nand = ~(a & b); 16 | assign out_nor = ~(a | b); 17 | assign out_xnor = ~(a ^ b); 18 | assign out_anotb = a & ~b; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/06_Counter1000.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | output OneHertz, 5 | output [2:0] c_enable 6 | ); 7 | 8 | wire [3:0] q0, q1, q2; 9 | 10 | bcdcount counter0 (clk, reset, c_enable[0], q0); 11 | bcdcount counter1 (clk, reset, c_enable[1], q1); 12 | bcdcount counter2 (clk, reset, c_enable[2], q2); 13 | 14 | assign c_enable = {(q1 == 4'd9) & (q0 == 4'd9), q0 == 4'd9, 1'b1}; 15 | assign OneHertz = (q2 == 4'd9) & (q1 == 4'd9) & (q0 == 4'd9); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/09_AdderSubtractor.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | input sub, 5 | output [31:0] sum 6 | ); 7 | 8 | wire cout1, cout2; 9 | wire [15:0] sum1, sum2; 10 | wire [31:0] b_xor; 11 | 12 | assign b_xor = sub ? ~b : b; 13 | assign sum = {sum2, sum1}; 14 | 15 | add16 instance1(.a(a[15:0]), .b(b_xor[15:0]), .cin(sub), .cout(cout1), .sum(sum1)); 16 | add16 instance2(.a(a[31:16]), .b(b_xor[31:16]), .cin(cout1), .cout(cout2), .sum(sum2)); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/2. Build a circuit from a simulation waveform/06_CombinationalCircuit6.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [2:0] a, 3 | output reg [15:0] q 4 | ); 5 | 6 | always@(*)begin 7 | case(a) 8 | 0 : q = 16'h1232; 9 | 1 : q = 16'haee0; 10 | 2 : q = 16'h27d4; 11 | 3 : q = 16'h5a0e; 12 | 4 : q = 16'h2066; 13 | 5 : q = 16'h64ce; 14 | 6 : q = 16'hc526; 15 | 7 : q = 16'h2f19; 16 | endcase 17 | end 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/06_GenerateForLoop100bitBinaryAdder2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [99:0] a, b, 3 | input cin, 4 | output [99:0] cout, 5 | output [99:0] sum 6 | ); 7 | 8 | genvar i; 9 | 10 | assign sum[0] = a[0]^b[0]^cin; 11 | assign cout[0]=a[0]&b[0] | a[0]&cin | b[0]&cin; 12 | 13 | generate 14 | for(i=1; i<100 ; i=i+1)begin:FA 15 | assign sum[i] = a[i]^b[i]^cout[i-1]; 16 | assign cout[i] = a[i]&b[i] | a[i]&cout[i-1] | b[i]&cout[i-1]; 17 | end 18 | endgenerate 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/15_DetectAnEdge.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] in, 4 | output [7:0] pedge 5 | ); 6 | 7 | integer i; 8 | reg [7:0] in_tmp; 9 | always @(posedge clk) begin 10 | for(i = 0; i < 8; i = i + 1) begin 11 | if(in_tmp[i] != in[i] && in[i] == 1) begin 12 | pedge[i] = 1; 13 | end 14 | else begin 15 | pedge[i] = 0; 16 | end 17 | in_tmp[i] = in[i]; 18 | end 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/01_4bitShiftRegister.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | input load, 5 | input ena, 6 | input [3:0] data, 7 | output reg [3:0] q 8 | ); 9 | 10 | always@(posedge clk,posedge areset)begin 11 | if(areset) 12 | q <= 0; 13 | else begin 14 | if(load) 15 | q <= data; 16 | else if(ena) 17 | q <= {1'b0,q[3:1]}; 18 | else 19 | q <= q; 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/05_ModulesAndVectors.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [7:0] d, 4 | input [1:0] sel, 5 | output reg [7:0] q 6 | ); 7 | 8 | wire [7:0] w1,w2,w3; 9 | 10 | my_dff8(.clk(clk), .d(d), .q(w1)); 11 | my_dff8(.clk(clk), .d(w1), .q(w2)); 12 | my_dff8(.clk(clk), .d(w2), .q(w3)); 13 | 14 | always@(*)begin 15 | case(sel) 16 | 2'b00 : q <= d; 17 | 2'b01 : q <= w1; 18 | 2'b10 : q <= w2; 19 | 2'b11 : q <= w3; 20 | endcase 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/07_PriorityEncoderWithCasez.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] in, 3 | output reg [2:0] pos 4 | ); 5 | 6 | always @(*) begin 7 | casez(in) 8 | 8'bzzzzzzz1 : pos = 0; 9 | 8'bzzzzzz1z : pos = 1; 10 | 8'bzzzzz1zz : pos = 2; 11 | 8'bzzzz1zzz : pos = 3; 12 | 8'bzzz1zzzz : pos = 4; 13 | 8'bzz1zzzzz : pos = 5; 14 | 8'bz1zzzzzz : pos = 6; 15 | 8'b1zzzzzzz : pos = 7; 16 | default : pos = 0; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/04_IfStatementLatches.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input cpu_overheated, 3 | output reg shut_off_computer, 4 | input arrived, 5 | input gas_tank_empty, 6 | output reg keep_driving 7 | ); 8 | 9 | always @(*) begin 10 | if (cpu_overheated) 11 | shut_off_computer = 1; 12 | else 13 | shut_off_computer = 0; 14 | end 15 | 16 | always @(*) begin 17 | if (~arrived) 18 | keep_driving = ~gas_tank_empty; 19 | else 20 | keep_driving = 0; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/03_3bitBinaryAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [2:0] a, b, 3 | input cin, 4 | output [2:0] cout, 5 | output [2:0] sum 6 | ); 7 | 8 | integer i; 9 | assign sum[0] = a[0] ^ b[0] ^ cin; 10 | assign cout[0] = (a[0] & b[0]) | (a[0] & cin) | (b[0] & cin); 11 | always@(*) 12 | begin 13 | for(i=1; i<3; i++) 14 | begin 15 | sum[i] = a[i] ^ b[i] ^ cout[i-1]; 16 | cout[i] = (a[i] & b[i]) | (a[i] & cout[i-1]) | (b[i] & cout[i-1]); 17 | end 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/09_3-inputLUT.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input enable, 4 | input S, 5 | input A, B, C, 6 | output Z ); 7 | 8 | reg[7:0] q; 9 | 10 | always @(posedge clk) begin 11 | if(enable) 12 | q <= {q[6:0], S}; 13 | else 14 | q <= q; 15 | end 16 | 17 | always @(*) begin 18 | case({A, B, C}) 19 | 3'b000 : Z = q[0]; 20 | 3'b001 : Z = q[1]; 21 | 3'b010 : Z = q[2]; 22 | 3'b011 : Z = q[3]; 23 | 3'b100 : Z = q[4]; 24 | 3'b101 : Z = q[5]; 25 | 3'b110 : Z = q[6]; 26 | 3'b111 : Z = q[7]; 27 | endcase 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/2. Multiplexers/03_9to1Multiplexer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [15:0] a, b, c, d, e, f, g, h, i, 3 | input [3:0] sel, 4 | output [15:0] out 5 | ); 6 | 7 | always@(*)begin 8 | case(sel) 9 | 4'h0 : out = a; 10 | 4'h1 : out = b; 11 | 4'h2 : out = c; 12 | 4'h3 : out = d; 13 | 4'h4 : out = e; 14 | 4'h5 : out = f; 15 | 4'h6 : out = g; 16 | 4'h7 : out = h; 17 | 4'h8 : out = i; 18 | default : out = 16'hFFFF; 19 | endcase 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/1. Latches and Flip-Flops/06_DFFwithByteEnable.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, 4 | input [1:0] byteena, 5 | input [15:0] d, 6 | output [15:0] q 7 | ); 8 | always@(posedge clk)begin 9 | if(!resetn) 10 | q <= 0; 11 | else begin 12 | if(byteena[0]) 13 | q[7:0] <= d[7:0]; 14 | else 15 | q[7:0] <= q[7:0]; 16 | if(byteena[1]) 17 | q[15:8] <= d[15:8]; 18 | else 19 | q[15:8] <= q[15:8]; 20 | end 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/05_CaseStatement.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [2:0] sel, 3 | input [3:0] data0, 4 | input [3:0] data1, 5 | input [3:0] data2, 6 | input [3:0] data3, 7 | input [3:0] data4, 8 | input [3:0] data5, 9 | output reg [3:0] out 10 | ); 11 | 12 | always@(*) begin 13 | case(sel) 14 | 0 : out = data0; 15 | 1 : out = data1; 16 | 2 : out = data2; 17 | 3 : out = data3; 18 | 4 : out = data4; 19 | 5 : out = data5; 20 | default : out = 0; 21 | endcase 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /1. Verilog Language/4. Procedures/06_PriorityEncoder.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] in, 3 | output reg [1:0] pos 4 | ); 5 | 6 | always @(*) begin 7 | case (in) 8 | 4'h0: pos = 2'h0; 9 | 4'h1: pos = 2'h0; 10 | 4'h2: pos = 2'h1; 11 | 4'h3: pos = 2'h0; 12 | 4'h4: pos = 2'h2; 13 | 4'h5: pos = 2'h0; 14 | 4'h6: pos = 2'h1; 15 | 4'h7: pos = 2'h0; 16 | 4'h8: pos = 2'h3; 17 | 4'h9: pos = 2'h0; 18 | 4'ha: pos = 2'h1; 19 | 4'hb: pos = 2'h0; 20 | 4'hc: pos = 2'h2; 21 | 4'hd: pos = 2'h0; 22 | 4'he: pos = 2'h1; 23 | 4'hf: pos = 2'h0; 24 | default: pos = 2'b0; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/05_Counter1-12.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input enable, 5 | output [3:0] Q, 6 | output c_enable, 7 | output c_load, 8 | output [3:0] c_d 9 | ); 10 | 11 | initial Q <= 1; 12 | 13 | always @(posedge clk) begin 14 | if(reset | ((Q == 12) & enable)) Q <= 1; 15 | else Q <= (enable) ? Q + 1 : Q; 16 | end 17 | 18 | assign c_enable = enable; 19 | assign c_load = (reset | ((Q == 12) & enable)); 20 | assign c_d = c_load ? 1 : 0; 21 | 22 | count4 the_counter (clk, c_enable, c_load, c_d /*, ... */ ); 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |

HDLBits Verilog Solutions

2 |

3 | 4 | Logo 5 | 6 |

7 | 8 | This repository contains my solutions to all the problems of the HDL-Bits Verilog problem set.
9 | At the time of making this, the problem set had a total of 178 questions. 10 | 11 | ## Contributors 12 | Adarsh Pal - 13 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/06_SimpleOneHotStateTransition3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [3:0] state, 4 | output [3:0] next_state, 5 | output out 6 | ); 7 | 8 | parameter A=0, B=1, C=2, D=3; 9 | 10 | // State transition logic: Derive an equation for each state flip-flop. 11 | assign next_state[A] = (state[A] & ~in) | (state[C] & ~in); 12 | assign next_state[B] = (state[A] & in) | (state[B] & in) | (state[D] & in); 13 | assign next_state[C] = (state[B] & ~in) | (state[D] & ~in); 14 | assign next_state[D] = state[C] & in; 15 | 16 | // Output logic: 17 | assign out = (state[D]); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /5. CS450/01_Timer.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input [9:0] data, 5 | output reg tc 6 | ); 7 | 8 | reg [9:0] counter; 9 | 10 | always @(posedge clk) begin 11 | if(load) begin 12 | counter <= data; 13 | tc <= (data == 10'd0) ? 1'b1 : 1'b0; 14 | end 15 | else begin 16 | if(counter > 10'd1) begin 17 | counter <= counter - 1'd1; 18 | tc <= 1'b0; 19 | end 20 | else begin 21 | counter <= 10'd0; 22 | tc <= 1'b1; 23 | end 24 | end 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/07_Adder2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | ); 6 | 7 | wire cin1, cout1, cout2; 8 | wire [15:0] sum1, sum2; 9 | assign cin1 = 0; 10 | 11 | add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(cin1), .cout(cout1), .sum(sum1)); 12 | add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(cout1), .cout(cout2), .sum(sum2)); 13 | 14 | assign sum = {sum2, sum1}; 15 | 16 | endmodule 17 | 18 | module add1 ( 19 | input a, 20 | input b, 21 | input cin, 22 | output sum, 23 | output cout 24 | ); 25 | 26 | assign sum = a ^ b ^ cin; 27 | assign cout = a&b | a&cin | b&cin; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/05_SimpleStateTransition3.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [1:0] state, 4 | output [1:0] next_state, 5 | output out); // 6 | 7 | parameter A=0, B=1, C=2, D=3; 8 | 9 | // State transition logic: next_state = f(state, in) 10 | always @(*) begin 11 | case(state) 12 | A : next_state = (in == 1) ? B : A; 13 | B : next_state = (in == 1) ? B : C; 14 | C : next_state = (in == 1) ? D : A; 15 | D : next_state = (in == 1) ? B : C; 16 | endcase 17 | end 18 | 19 | // Output logic: out = f(state) for a Moore state machine 20 | assign out = (state == D); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /4. Verification : Writing Testbenches/04_Testbench2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 1ps 2 | module top_module(); 3 | 4 | reg clk; 5 | reg in; 6 | reg [2:0] s; 7 | wire out; 8 | 9 | q7 u_q7( 10 | .clk(clk), 11 | .in(in), 12 | .s(s), 13 | .out(out) 14 | ); 15 | 16 | initial begin 17 | clk = 0; 18 | in = 0; 19 | s = 2; 20 | #10; 21 | s = 6; 22 | #10; 23 | s = 2; 24 | in = 1; 25 | #10; 26 | s = 7; 27 | in = 0; 28 | #10; 29 | in = 1; 30 | s = 0; 31 | #30; 32 | in = 0; 33 | end 34 | 35 | always begin 36 | #5 clk = ~clk; 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /1. Verilog Language/5. More Verilog Features/07_GenerateFor-loop:100digitBCDAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [399:0] a, b, 3 | input cin, 4 | output cout, 5 | output [399:0] sum 6 | ); 7 | 8 | wire [99:0] cout_temp; 9 | 10 | bcd_fadd u_bcd_fadd( 11 | .a(a[3:0]), 12 | .b(b[3:0]), 13 | .cin(cin), 14 | .cout(cout_temp[0]), 15 | .sum(sum[3:0]) 16 | ); 17 | 18 | generate 19 | genvar i; 20 | for(i=1; i<100; i=i+1) 21 | begin : block1 22 | bcd_fadd u_bcd_fadd( 23 | .a(a[4*i+3 : 4*i]), 24 | .b(b[4*i+3 : 4*i]), 25 | .cin(cout_temp[i-1]), 26 | .cout(cout_temp[i]), 27 | .sum(sum[4*i+3 : 4*i]) 28 | ); 29 | end 30 | endgenerate 31 | 32 | assign cout = cout_temp[99]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/23_Q5bSerialTwoComplementer(Mealy).v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, 4 | input x, 5 | output z 6 | ); 7 | 8 | localparam [1:0] A = 2'b01, 9 | B = 2'b10; 10 | 11 | reg [1:0] state, next; 12 | 13 | always @(*) begin 14 | case (state) 15 | A : begin 16 | if (x) begin 17 | next = B; 18 | z =1; 19 | end 20 | else begin 21 | next = A; 22 | z = 0; 23 | end 24 | end 25 | B : begin 26 | next = B; 27 | z = (x) ? 1'b0 : 1'b1; 28 | end 29 | endcase 30 | end 31 | 32 | always @(posedge clk or posedge areset) begin 33 | if (areset) state <= A; 34 | else state <= next; 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /3. Verification : Reading Simulations/1. Finding bugs in code/05_CaseStatement.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [7:0] code, 3 | output reg [3:0] out, 4 | output reg valid 5 | ); 6 | 7 | always @(*) begin 8 | out = 0; 9 | valid = 1; 10 | case (code) 11 | 8'h45: out = 0; 12 | 8'h16: out = 1; 13 | 8'h1e: out = 2; 14 | 8'h26: out = 3; 15 | 8'h25: out = 4; 16 | 8'h2e: out = 5; 17 | 8'h36: out = 6; 18 | 8'h3d: out = 7; 19 | 8'h3e: out = 8; 20 | 8'h46: out = 9; 21 | default: valid = 0; 22 | endcase 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /5. CS450/03_HistoryShift.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | 5 | input predict_valid, 6 | input predict_taken, 7 | output reg [31:0] predict_history, 8 | 9 | input train_mispredicted, 10 | input train_taken, 11 | input reg [31:0] train_history 12 | ); 13 | 14 | always @(posedge clk or posedge areset) begin 15 | if(areset) 16 | predict_history <= 32'd0; 17 | else begin 18 | if(train_mispredicted) 19 | predict_history <= {train_history[30:0],train_taken}; 20 | else if(predict_valid) 21 | predict_history <= {predict_history[30:0],predict_taken}; 22 | end 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/27_Q6b:FSMNextStateLogic.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:1] y, 3 | input w, 4 | output Y2 5 | ); 6 | 7 | reg [3:1] Y; 8 | 9 | always @(*) begin 10 | case({y, w}) 11 | 4'b0000: Y = 3'b001; 12 | 4'b0001: Y = 3'b000; 13 | 4'b0010: Y = 3'b010; 14 | 4'b0011: Y = 3'b011; 15 | 4'b0100: Y = 3'b100; 16 | 4'b0101: Y = 3'b011; 17 | 4'b0110: Y = 3'b101; 18 | 4'b0111: Y = 3'b000; 19 | 4'b1000: Y = 3'b100; 20 | 4'b1001: Y = 3'b011; 21 | 4'b1010: Y = 3'b010; 22 | 4'b1011: Y = 3'b011; 23 | endcase 24 | end 25 | 26 | assign Y2 = Y[2]; 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /4. Verification : Writing Testbenches/05_Tflip-flop.v: -------------------------------------------------------------------------------- 1 | module top_module (); 2 | reg clk; 3 | reg reset; 4 | reg t; 5 | wire q; 6 | 7 | tff u_tff( 8 | .clk (clk ), 9 | .reset (reset ), 10 | .t (t ), 11 | .q (q ) 12 | ); 13 | 14 | initial begin 15 | clk=1'b0; 16 | forever 17 | #5 18 | clk=~clk; 19 | end 20 | 21 | initial begin 22 | reset = 1'b0; 23 | #3; 24 | reset = 1'b1; 25 | #10; 26 | reset = 1'b0; 27 | end 28 | 29 | always@(posedge clk)begin 30 | if(reset)begin 31 | t <= 1'b0; 32 | end 33 | else begin 34 | t <= 1'b1; 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/04_FSM:EnableShiftRegister.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | output shift_ena 5 | ); 6 | 7 | parameter S0=3'd0, S1=3'd1, S2=3'd2, S3=3'd3, S4=3'd4; 8 | reg [2:0] state, next_state; 9 | 10 | always@(*) begin 11 | case(state) 12 | S0: next_state = reset ? S1 : S0; 13 | S1: next_state = S2; 14 | S2: next_state = S3; 15 | S3: next_state = S4; 16 | S4: next_state = S0; 17 | endcase 18 | end 19 | 20 | always@(posedge clk) begin 21 | state <= next_state; 22 | end 23 | 24 | assign shift_ena = (state==S1 | state==S2 | state==S3 | state==S4); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/03_SimpleFSM2(asycnhronousReset).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | input j, 5 | input k, 6 | output out 7 | ); 8 | 9 | parameter OFF=0, ON=1; 10 | reg state, next_state; 11 | 12 | always @(*) begin 13 | // State transition logic 14 | case(state) 15 | OFF : next_state = (j == 1) ? ON : OFF; 16 | ON : next_state = (k == 1) ? OFF : ON; 17 | endcase 18 | end 19 | 20 | always @(posedge clk, posedge areset) begin 21 | // State flip-flops with asynchronous reset 22 | if(areset) state <= OFF; 23 | else state <= next_state; 24 | end 25 | 26 | // Output logic 27 | assign out = (state == ON); 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /2. Circuits/1. Combinational Logic/3. Arithmetic Circuits/07_4digitBCDAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [15:0] a, b, 3 | input cin, 4 | output cout, 5 | output [15:0] sum 6 | ); 7 | 8 | wire [3:0] cout_temp; 9 | 10 | bcd_fadd u_bcd_fadd( 11 | .a(a[3:0]), 12 | .b(b[3:0]), 13 | .cin(cin), 14 | .cout(cout_temp[0]), 15 | .sum(sum[3:0]) 16 | ); 17 | 18 | generate 19 | genvar i; 20 | for(i=1; i<4; i++) 21 | begin 22 | bcd_fadd u_bcd_fadd( 23 | .a(a[4*i+3 : 4*i]), 24 | .b(b[4*i+3 : 4*i]), 25 | .cin(cout_temp[i-1]), 26 | .cout(cout_temp[i]), 27 | .sum(sum[4*i+3 : 4*i]) 28 | ); 29 | end 30 | endgenerate 31 | 32 | assign cout = cout_temp[3]; 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/04_SimpleFSM2(synchronousReset).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Asynchronous reset to OFF 4 | input j, 5 | input k, 6 | output out); // 7 | 8 | parameter OFF=0, ON=1; 9 | reg state, next_state; 10 | 11 | always @(*) begin 12 | // State transition logic 13 | case(state) 14 | OFF : next_state = (j == 1) ? ON : OFF; 15 | ON : next_state = (k == 1) ? OFF : ON; 16 | endcase 17 | end 18 | 19 | always @(posedge clk) begin 20 | // State flip-flops with asynchronous reset 21 | if(reset) state <= OFF; 22 | else state <= next_state; 23 | end 24 | 25 | // Output logic 26 | assign out = (state == ON); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/26_Q3cFSMLogic.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input [2:0] y, 4 | input x, 5 | output Y0, 6 | output z 7 | ); 8 | 9 | reg [2:0] Y; 10 | 11 | always@(*) begin 12 | case({y, x}) 13 | 4'b0000: Y = 3'b000; 14 | 4'b0001: Y = 3'b001; 15 | 4'b0010: Y = 3'b001; 16 | 4'b0011: Y = 3'b100; 17 | 4'b0100: Y = 3'b010; 18 | 4'b0101: Y = 3'b001; 19 | 4'b0110: Y = 3'b001; 20 | 4'b0111: Y = 3'b010; 21 | 4'b1000: Y = 3'b011; 22 | 4'b1001: Y = 3'b100; 23 | endcase 24 | end 25 | 26 | assign z = (y == 3'b011 || y == 3'b100); 27 | assign Y0 = Y[0]; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/08_ShiftRegister2.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input [3:0] SW, 3 | input [3:0] KEY, 4 | output [3:0] LEDR 5 | ); 6 | 7 | MUXDFF ins0(SW[3], KEY[0], KEY[1], KEY[2], KEY[3], LEDR[3]); 8 | MUXDFF ins1(SW[2], KEY[0], KEY[1], KEY[2], LEDR[3], LEDR[2]); 9 | MUXDFF ins2(SW[1], KEY[0], KEY[1], KEY[2], LEDR[2], LEDR[1]); 10 | MUXDFF ins3(SW[0], KEY[0], KEY[1], KEY[2], LEDR[1], LEDR[0]); 11 | 12 | endmodule 13 | 14 | module MUXDFF ( 15 | input R, 16 | input clk, 17 | input E, 18 | input L, 19 | input w, 20 | output out 21 | ); 22 | wire [1:0] temp; 23 | assign temp[0] = E ? w : out; 24 | assign temp[1] = L ? R : temp[0]; 25 | 26 | always @(posedge clk) begin 27 | out <= temp[1]; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/03_FSM:Sequence1101Recognizer.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output start_shifting 6 | ); 7 | 8 | localparam [2:0] IDLE = 0, 9 | S1 = 1, 10 | S11 = 2, 11 | S110 = 3, 12 | S1101= 4; 13 | 14 | reg [2:0] state, next; 15 | 16 | always @(*) begin 17 | case (state) 18 | IDLE : next = (data) ? S1 : IDLE; 19 | S1 : next = (data) ? S11 : IDLE; 20 | S11 : next = (data) ? S11 : S110; 21 | S110 : next = (data) ? S1101: IDLE; 22 | S1101 : next = S1101; 23 | endcase 24 | end 25 | 26 | always @(posedge clk) begin 27 | if (reset) begin 28 | state <= IDLE; 29 | end 30 | else state <= next; 31 | end 32 | 33 | assign start_shifting = (state == S1101); 34 | endmodule 35 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/02_SimpleFSM1(synchronousReset).v: -------------------------------------------------------------------------------- 1 | // Note the Verilog-1995 module declaration syntax here: 2 | module top_module(clk, reset, in, out); 3 | input clk; 4 | input reset; // Synchronous reset to state B 5 | input in; 6 | output out;// 7 | 8 | // Fill in state name declarations 9 | parameter A = 0, B = 1; 10 | reg present_state, next_state; 11 | 12 | always @(posedge clk) begin 13 | if (reset) present_state <= B; 14 | else present_state <= next_state; 15 | end 16 | 17 | always @(*) begin 18 | case (present_state) 19 | B : next_state <= (in == 1) ? B : A; 20 | A : next_state <= (in == 1) ? A : B; 21 | endcase 22 | end 23 | 24 | assign out = (present_state == B); 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /1. Verilog Language/3. Modules: Hierarchy/08_CarrySelectAdder.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input [31:0] a, 3 | input [31:0] b, 4 | output [31:0] sum 5 | ); 6 | 7 | wire cin1, cout1, cin2, cout2, cin3, cout3; 8 | wire [15:0] sum1, sum2, sum3, sum_mux; 9 | assign cin1 = 0; 10 | assign cin2 = 0; 11 | assign cin3 = 1; 12 | 13 | add16 instance1(.a(a[15:0]), .b(b[15:0]), .cin(cin1), .cout(cout1), .sum(sum1)); 14 | add16 instance2(.a(a[31:16]), .b(b[31:16]), .cin(cin2), .cout(cout2), .sum(sum2)); 15 | add16 instance3(.a(a[31:16]), .b(b[31:16]), .cin(cin3), .cout(cout3), .sum(sum3)); 16 | 17 | always @(*) begin 18 | case(cout1) 19 | 0 : sum_mux = sum2; 20 | 1 : sum_mux = sum3; 21 | endcase 22 | end 23 | 24 | assign sum = {sum_mux, sum1}; 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/25_Q3bFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input x, 5 | output z 6 | ); 7 | 8 | parameter a = 0, b = 1, c = 2, d = 3, e = 4; 9 | reg [2:0] state, next_state; 10 | 11 | always @(*) begin 12 | case (state) 13 | a: next_state = x ? b : a; 14 | b: next_state = x ? e : b; 15 | c: next_state = x ? b : c; 16 | d: next_state = x ? c : b; 17 | e: next_state = x ? e : d; 18 | endcase 19 | end 20 | 21 | always @(posedge clk) begin 22 | if (reset) begin 23 | state <= a; 24 | end 25 | else begin 26 | state <= next_state; 27 | end 28 | end 29 | 30 | assign z = (state == d || state == e); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /5. CS450/02_Counter2bc.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | input train_valid, 5 | input train_taken, 6 | output reg [1:0] state 7 | ); 8 | localparam SNT = 2'b00, 9 | WNT = 2'b01, 10 | WT = 2'b10, 11 | ST = 2'b11; 12 | 13 | reg [1:0] next; 14 | 15 | always @(*) begin 16 | case(state) 17 | SNT: next = train_taken ? WNT : SNT; 18 | WNT: next = train_taken ? WT : SNT; 19 | WT: next = train_taken ? ST : WNT; 20 | ST: next = train_taken ? ST : WT; 21 | default: next = WNT; 22 | endcase 23 | end 24 | 25 | always @(posedge clk or posedge areset) begin 26 | if(areset) state <= WNT; 27 | else state <= train_valid ? next : state; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/08_SimpleFSM3(synchronousReset).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, 5 | output out 6 | ); 7 | 8 | reg [2:0] state, next_state; 9 | parameter A = 1, B = 2, C = 3, D = 4; 10 | 11 | // State transition logic 12 | always @(*) begin 13 | case(state) 14 | A : next_state = (in == 1) ? B : A; 15 | B : next_state = (in == 1) ? B : C; 16 | C : next_state = (in == 1) ? D : A; 17 | D : next_state = (in == 1) ? B : C; 18 | endcase 19 | end 20 | 21 | // State flip-flops with asynchronous reset 22 | always @(posedge clk) begin 23 | if(reset) state <= A; 24 | else state <= next_state; 25 | end 26 | 27 | // Output logic 28 | assign out = (state == D); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/01_SimpleFSM1(asynchronousReset).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Asynchronous reset to state B 4 | input in, 5 | output out 6 | ); 7 | 8 | parameter A=0, B=1; 9 | reg state, next_state; 10 | 11 | always @(*) begin // This is a combinational always block 12 | // State transition logic 13 | case(state) 14 | A : next_state = (in == 1) ? A : B; 15 | B : next_state = (in == 1) ? B : A; 16 | endcase 17 | end 18 | 19 | always @(posedge clk, posedge areset) begin // This is a sequential always block 20 | // State flip-flops with asynchronous reset 21 | if(areset) state <= B; 22 | else state <= next_state; 23 | end 24 | 25 | // Output logic 26 | assign out = (state == B); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/07_SimpleFSM3(asynchronousReset).v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input areset, 5 | output out 6 | ); 7 | 8 | reg [2:0] state, next_state; 9 | parameter A = 1, B = 2, C = 3, D = 4; 10 | 11 | // State transition logic 12 | always @(*) begin 13 | case(state) 14 | A : next_state = (in == 1) ? B : A; 15 | B : next_state = (in == 1) ? B : C; 16 | C : next_state = (in == 1) ? D : A; 17 | D : next_state = (in == 1) ? B : C; 18 | endcase 19 | end 20 | 21 | // State flip-flops with asynchronous reset 22 | always @(posedge clk or posedge areset) begin 23 | if(areset) state <= A; 24 | else state <= next_state; 25 | end 26 | 27 | // Output logic 28 | assign out = (state == D); 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/21_Q8DesignMealyFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input aresetn, // Asynchronous active-low reset 4 | input x, 5 | output z ); 6 | 7 | localparam [1:0] IDLE = 0, 8 | ONE = 1, 9 | ONE_ZERO = 2; 10 | 11 | reg [1:0] state, next; 12 | 13 | always @(*) begin 14 | case (state) 15 | IDLE : begin 16 | next = (x) ? ONE : IDLE; 17 | z = 0; 18 | end 19 | ONE : begin 20 | next = (x) ? ONE : ONE_ZERO; 21 | z = 0; 22 | end 23 | ONE_ZERO : begin 24 | if (x) begin 25 | next = ONE; 26 | z = 1; 27 | end 28 | else begin 29 | next = IDLE; 30 | z = 0; 31 | end 32 | end 33 | endcase 34 | end 35 | 36 | always @(posedge clk or negedge aresetn) begin 37 | if (~aresetn) state <= IDLE; 38 | else state <= next; 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/15_PS2PacketParser.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input [7:0] in, 4 | input reset, // Synchronous reset 5 | output done 6 | ); 7 | 8 | localparam [1:0] BYTE1 = 2'b00, 9 | BYTE2 = 2'b01, 10 | BYTE3 = 2'b10, 11 | DONE = 2'b11; 12 | 13 | reg [1:0] state, next; 14 | 15 | // State transition logic (combinational) 16 | always @(*) begin 17 | case(state) 18 | BYTE1 : next = (in[3]) ? BYTE2 : BYTE1; 19 | BYTE2 : next = BYTE3; 20 | BYTE3 : next = DONE; 21 | DONE : next = (in[3]) ? BYTE2 : BYTE1; 22 | endcase 23 | end 24 | 25 | // State flip-flops (sequential) 26 | always @(posedge clk) begin 27 | if(reset) state <= BYTE1; 28 | else state <= next; 29 | end 30 | 31 | // Output logic 32 | assign done = (state == DONE); 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/3. Shift Registers/03_LeftRightArithematicShiftby1or8.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if(load) q <= data; 12 | else begin 13 | if(ena) begin 14 | if(amount == 2'b00) 15 | q <= (q << 1); 16 | else if(amount == 2'b01) 17 | q <= (q << 8); 18 | else if(amount == 2'b10) begin 19 | if(q[63] == 0) 20 | q <= (q >> 1); 21 | else begin 22 | q <= (q >> 1); 23 | q[63] <= 1'b1; 24 | end 25 | end 26 | else begin 27 | if(q[63] == 0) 28 | q <= (q >> 8); 29 | else begin 30 | q <= (q >> 8); 31 | q[63:56] <= {8{1'b1}}; 32 | end 33 | end 34 | end 35 | end 36 | end 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/10_Lemmings1.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | output walk_left, 7 | output walk_right); // 8 | 9 | parameter LEFT = 0, RIGHT = 1; 10 | reg state, next_state; 11 | 12 | always @(*) begin 13 | // State transition logic 14 | case(state) 15 | LEFT : next_state = (bump_left) ? RIGHT : LEFT; 16 | RIGHT : next_state = (bump_right) ? LEFT : RIGHT; 17 | endcase 18 | end 19 | 20 | always @(posedge clk, posedge areset) begin 21 | // State flip-flops with asynchronous reset 22 | if(areset) state <= LEFT; 23 | else begin 24 | state <= next_state; 25 | end 26 | end 27 | 28 | // Output logic 29 | assign walk_left = (state == LEFT); 30 | assign walk_right = (state == RIGHT); 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/07_OneHotLogicEquations.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input d, 3 | input done_counting, 4 | input ack, 5 | input [9:0] state, // 10-bit one-hot current state 6 | output B3_next, 7 | output S_next, 8 | output S1_next, 9 | output Count_next, 10 | output Wait_next, 11 | output done, 12 | output counting, 13 | output shift_ena 14 | ); 15 | 16 | parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9; 17 | 18 | assign B3_next = state[B2]; 19 | assign S_next = (state[S] & (~d)) | (state[S1] & (~d)) | (state[S110] & (~d)) | (state[Wait] & ack); 20 | assign S1_next = state[S] & d; 21 | assign Count_next = state[B3] | (state[Count] & (~done_counting)); 22 | assign Wait_next = (state[Count] & (done_counting)) | (state[Wait] & (~ack)); 23 | assign done = state[Wait]; 24 | assign counting = state[Count]; 25 | assign shift_ena = state[B0] | state[B1] | state[B2] | state[B3]; 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/24_Q3aFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input s, 5 | input w, 6 | output z 7 | ); 8 | parameter A = 0, B = 1; 9 | 10 | reg state, next; 11 | reg [1:0] count; 12 | reg [1:0] count1; 13 | 14 | always @(*) begin 15 | case(state) 16 | A : next = (s) ? B : A; 17 | B : next = B; 18 | endcase 19 | end 20 | 21 | always @(posedge clk) begin 22 | if (reset) begin 23 | state <= A; 24 | count=0; 25 | count1=0; 26 | end 27 | else begin 28 | state <= next; 29 | 30 | if(state==B) 31 | begin 32 | if(count1==3)begin 33 | count=0; 34 | count1=0; 35 | end 36 | if(w==1) count=count+1; 37 | 38 | count1=count1+1; 39 | 40 | end 41 | end 42 | end 43 | 44 | 45 | 46 | assign z = ((count == 2) & (count1 == 3) ); 47 | endmodule 48 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/14_OneHotFSM.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input in, 3 | input [9:0] state, 4 | output [9:0] next_state, 5 | output out1, 6 | output out2 7 | ); 8 | 9 | localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, 10 | S5 = 5, S6 = 6, S7 = 7, S8 = 8, S9 = 9; 11 | 12 | //states 13 | assign next_state[S0] = (state[S0] & !in) | (state[S1] & !in) | (state[S2] & !in) | (state[S3] & !in) | 14 | (state[S4] & !in) | (state[S7] & !in) | (state[S8] & !in) | (state[S9] & !in); 15 | assign next_state[S1] = (state[S0] & in) | (state[S8] & in) | (state[S9] & in); 16 | assign next_state[S2] = state[S1] & in; 17 | assign next_state[S3] = state[S2] & in; 18 | assign next_state[S4] = state[S3] & in; 19 | assign next_state[S5] = state[S4] & in; 20 | assign next_state[S6] = state[S5] & in; 21 | assign next_state[S7] = (state[S6] & in) | (state[7] & in); 22 | assign next_state[S8] = state[S5] & !in; 23 | assign next_state[S9] = state[S6] & !in; 24 | 25 | //output 26 | assign out1 = state[8] | state[9]; 27 | assign out2 = state[7] | state[9]; 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 Adarsh Pal 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/07_4digitDecimalCounter.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous active-high reset 4 | output [3:1] ena, 5 | output [15:0] q); 6 | 7 | always @(posedge clk) begin 8 | if(reset) begin 9 | q = 0; 10 | ena = 0; 11 | end 12 | else begin 13 | q[3:0] = q[3:0] + 1; 14 | ena[1] = (q[3:0] == 9) ? 1 : 0; 15 | if(q[3:0] == 10) begin 16 | q[3:0] = 0; 17 | q[7:4] = q[7:4] + 1; 18 | end 19 | ena[2] = ((q[7:4] == 9) && (q[3:0] == 9)) ? 1 : 0; 20 | if(q[7:4] == 10) begin 21 | q[7:4] = 0; 22 | q[11:8] = q[11:8] + 1; 23 | end 24 | ena[3] = ((q[11:8] == 9) && (q[7:4] == 9) && (q[3:0] == 9)) ? 1 : 0; 25 | if(q[11:8] == 10) begin 26 | q[11:8] = 0; 27 | q[15:12] = q[15:12] + 1; 28 | end 29 | if(q[15:12] == 10) begin 30 | q = 0; 31 | end 32 | end 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/22_Q5aSerialTwoComplementer(Moore).v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input areset, 4 | input x, 5 | output z 6 | ); 7 | 8 | parameter A=2'b00, B=2'b01, C=2'b10; 9 | reg [1:0] state, state_next; 10 | 11 | always @(posedge clk or posedge areset) 12 | begin 13 | if (areset) 14 | state <= A; 15 | else 16 | state <= state_next; 17 | end 18 | 19 | always @(*) 20 | begin 21 | case (state) 22 | A: begin 23 | if (x) state_next <= B; 24 | else state_next <= A; 25 | end 26 | B: begin 27 | if (x) state_next <= C; 28 | else state_next <= B; 29 | end 30 | C: begin 31 | if (x) state_next <= C; 32 | else state_next <= B; 33 | end 34 | default: state_next <= A; 35 | endcase 36 | end 37 | 38 | assign z = (state == B); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/11_Lemmings2.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | output walk_left, 8 | output walk_right, 9 | output aaah 10 | ); 11 | 12 | localparam [1:0] WALK_L = 2'b00, 13 | WALK_R = 2'b01, 14 | FALL_L = 2'b10, 15 | FALL_R = 2'b11; 16 | 17 | reg [1:0] state, next; 18 | 19 | always @(posedge clk or posedge areset) begin 20 | if(areset) state <= WALK_L; 21 | else begin 22 | state <= next; 23 | end 24 | end 25 | 26 | always @(*) begin 27 | case(state) 28 | WALK_L : next = (ground == 0) ? FALL_L : ((bump_left == 1) ? WALK_R : WALK_L); 29 | WALK_R : next = (ground == 0) ? FALL_R : ((bump_right == 1) ? WALK_L : WALK_R); 30 | FALL_L : next = (ground == 1) ? WALK_L : FALL_L; 31 | FALL_R : next = (ground == 1) ? WALK_R : FALL_R; 32 | endcase 33 | end 34 | 35 | assign walk_left = (state == WALK_L); 36 | assign walk_right = (state == WALK_R); 37 | assign aaah = ((state == FALL_L) || (state == FALL_R)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/29_Q6:FSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // synchronous reset 4 | input w, 5 | output z 6 | ); 7 | 8 | parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011, e=3'b100, f=3'b101; 9 | reg [2:0] state, next_state; 10 | 11 | always@(*) begin 12 | case({state, w}) 13 | {a, 1'b0}: next_state = b; 14 | {a, 1'b1}: next_state = a; 15 | {b, 1'b0}: next_state = c; 16 | {b, 1'b1}: next_state = d; 17 | {c, 1'b0}: next_state = e; 18 | {c, 1'b1}: next_state = d; 19 | {d, 1'b0}: next_state = f; 20 | {d, 1'b1}: next_state = a; 21 | {e, 1'b0}: next_state = e; 22 | {e, 1'b1}: next_state = d; 23 | {f, 1'b0}: next_state = c; 24 | {f, 1'b1}: next_state = d; 25 | default : next_state = a; 26 | endcase 27 | end 28 | 29 | always@(posedge clk) begin 30 | if(reset) 31 | state <= a; 32 | else 33 | state <= next_state; 34 | end 35 | 36 | assign z = (state == e || state == f); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/30_Q2a:FSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // synchronous reset 4 | input w, 5 | output z 6 | ); 7 | 8 | parameter a=3'b000, b=3'b001, c=3'b010, d=3'b011, e=3'b100, f=3'b101; 9 | reg [2:0] state, next_state; 10 | 11 | always@(*) begin 12 | case({state, w}) 13 | {a, 1'b0}: next_state = a; 14 | {a, 1'b1}: next_state = b; 15 | {b, 1'b0}: next_state = d; 16 | {b, 1'b1}: next_state = c; 17 | {c, 1'b0}: next_state = d; 18 | {c, 1'b1}: next_state = e; 19 | {d, 1'b0}: next_state = a; 20 | {d, 1'b1}: next_state = f; 21 | {e, 1'b0}: next_state = d; 22 | {e, 1'b1}: next_state = e; 23 | {f, 1'b0}: next_state = d; 24 | {f, 1'b1}: next_state = c; 25 | default : next_state = a; 26 | endcase 27 | end 28 | 29 | always@(posedge clk) begin 30 | if(reset) 31 | state <= a; 32 | else 33 | state <= next_state; 34 | end 35 | 36 | assign z = (state == e || state == f); 37 | 38 | endmodule 39 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/16_PS2PacketParserWithDataPath.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input [7:0] in, 4 | input reset, // Synchronous reset 5 | output [23:0] out_bytes, 6 | output done); // 7 | 8 | localparam [1:0] BYTE1 = 2'b00, 9 | BYTE2 = 2'b01, 10 | BYTE3 = 2'b10, 11 | DONE = 2'b11; 12 | 13 | reg [1:0] state, next; 14 | reg [23:0] data; 15 | 16 | // State transition logic (combinational) 17 | always @(*) begin 18 | case(state) 19 | BYTE1 : next = (in[3]) ? BYTE2 : BYTE1; 20 | BYTE2 : next = BYTE3; 21 | BYTE3 : next = DONE; 22 | DONE : next = (in[3]) ? BYTE2 : BYTE1; 23 | endcase 24 | end 25 | 26 | // State flip-flops (sequential) 27 | always @(posedge clk) begin 28 | if(reset) state <= BYTE1; 29 | else state <= next; 30 | end 31 | 32 | // New: Datapath to store incoming bytes. 33 | always @(posedge clk) begin 34 | if (reset) data <= 24'b0; 35 | else data <= {data[15:8], data[7:0], in}; 36 | end 37 | 38 | // Output logic 39 | assign done = (state == DONE); 40 | assign out_bytes = (done) ? data : 24'b0; 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/20_SequenceRecognition.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input in, 5 | output disc, 6 | output flag, 7 | output err 8 | ); 9 | 10 | localparam [3:0] NONE = 0, 11 | ONE = 1, 12 | TWO = 2, 13 | THREE= 3, 14 | FOUR = 4, 15 | FIVE = 5, 16 | SIX = 6, 17 | DISC = 7, 18 | FLAG = 8, 19 | ERR = 9; 20 | 21 | reg [3:0] state, next; 22 | 23 | always @(*) begin 24 | case (state) 25 | NONE : next = (in) ? ONE : NONE; 26 | ONE : next = (in) ? TWO : NONE; 27 | TWO : next = (in) ? THREE : NONE; 28 | THREE: next = (in) ? FOUR : NONE; 29 | FOUR : next = (in) ? FIVE : NONE; 30 | FIVE : next = (in) ? SIX : DISC; 31 | SIX : next = (in) ? ERR : FLAG; 32 | DISC : next = (in) ? ONE : NONE; 33 | FLAG : next = (in) ? ONE : NONE; 34 | ERR : next = (in) ? ERR : NONE; 35 | endcase 36 | end 37 | 38 | always @(posedge clk) begin 39 | if (reset) 40 | state <= NONE; 41 | else 42 | state <= next; 43 | end 44 | 45 | assign disc = (state == DISC); 46 | assign flag = (state == FLAG); 47 | assign err = (state == ERR); 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/17_SerialReciever.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output done 6 | ); 7 | 8 | localparam [2:0] IDLE = 3'b000, 9 | START = 3'b001, 10 | RECEIVE = 3'b010, 11 | WAIT = 3'b011, 12 | STOP = 3'b100; 13 | 14 | reg [2:0] state, next; 15 | reg [3:0] i; 16 | 17 | always @(*) begin 18 | case(state) 19 | IDLE : next = (in) ? IDLE : START; 20 | START : next = RECEIVE; 21 | RECEIVE : begin 22 | if (i == 8) begin 23 | if (in) next = STOP; 24 | else next = WAIT; 25 | end 26 | else next = RECEIVE; 27 | end 28 | WAIT : next = (in) ? IDLE : WAIT; 29 | STOP : next = (in) ? IDLE : START; 30 | endcase 31 | end 32 | 33 | always @(posedge clk) begin 34 | if(reset) state <= IDLE; 35 | else state <= next; 36 | end 37 | 38 | always @(posedge clk) begin 39 | if (reset) begin 40 | done <= 0; 41 | i <= 0; 42 | end 43 | else begin 44 | case(next) 45 | RECEIVE : begin 46 | done <= 0; 47 | i = i + 1; 48 | end 49 | STOP : begin 50 | done <= 1; 51 | i <= 0; 52 | end 53 | default : begin 54 | done <= 0; 55 | i <= 0; 56 | end 57 | endcase 58 | end 59 | end 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/05_FSM:TheCompleteFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output shift_ena, 6 | output counting, 7 | input done_counting, 8 | output done, 9 | input ack 10 | ); 11 | 12 | localparam [3:0] IDLE = 0, 13 | S1 = 1, 14 | S11 = 2, 15 | S110 = 3, 16 | S1101 = 4, //'S1101' and 'SHIFT0' can be regarded as one state. 17 | SHIFT1 = 5, 18 | SHIFT2 = 6, 19 | SHIFT3 = 7, 20 | COUNT = 8, 21 | DONE = 9; 22 | reg [3:0] state, next; 23 | 24 | always @(*) begin 25 | case (state) 26 | IDLE : next = (data) ? S1 : IDLE; 27 | S1 : next = (data) ? S11 : IDLE; 28 | S11 : next = (data) ? S11 : S110; 29 | S110 : next = (data) ? S1101 : IDLE; 30 | S1101 : next = SHIFT1; 31 | SHIFT1: next = SHIFT2; 32 | SHIFT2: next = SHIFT3; 33 | SHIFT3: next = COUNT; 34 | COUNT : next = (done_counting) ? DONE : COUNT; 35 | DONE : next = (ack) ? IDLE : DONE; 36 | endcase 37 | end 38 | 39 | always @(posedge clk) begin 40 | if (reset) state <= IDLE; 41 | else state <= next; 42 | end 43 | 44 | assign shift_ena = ((state == S1101) | (state == SHIFT1) | (state == SHIFT2) | (state == SHIFT3)); 45 | assign counting = (state == COUNT); 46 | assign done = (state == DONE); 47 | endmodule 48 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/32_Q2a:FSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, // active-low synchronous reset 4 | input [3:1] r, // request 5 | output [3:1] g // grant 6 | ); 7 | 8 | parameter a=2'd0, b=2'd1, c=2'd2, d=2'd3; 9 | reg [1:0] state, next_state; 10 | 11 | always@(*) begin 12 | case(state) 13 | a: begin 14 | if(r[1]) next_state = b; 15 | else if(~r[1] & r[2]) next_state = c; 16 | else if(~r[1] & ~r[2] & r[3]) next_state = d; 17 | else next_state = a; 18 | end 19 | b: begin 20 | if(r[1]) next_state = b; 21 | else next_state = a; 22 | end 23 | c: begin 24 | if(r[2]) next_state = c; 25 | else next_state = a; 26 | end 27 | d: begin 28 | if(r[3]) next_state = d; 29 | else next_state = a; 30 | end 31 | endcase 32 | end 33 | 34 | always@(posedge clk) begin 35 | if(~resetn) 36 | state <= a; 37 | else 38 | state <= next_state; 39 | end 40 | 41 | assign g[1] = (state == b); 42 | assign g[2] = (state == c); 43 | assign g[3] = (state == d); 44 | 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/09_DesignAMooreFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, 4 | input [3:1] s, 5 | output fr3, 6 | output fr2, 7 | output fr1, 8 | output dfr 9 | ); 10 | 11 | localparam [2:0] A = 3'd0, //water level:below s1 12 | B0 = 3'd1, //s1~s2, and previous level is higher 13 | B1 = 3'd2, //s1~s2, and previous level is lower 14 | C0 = 3'd3, //s2~s3, and previous level is higher 15 | C1 = 3'd4, //s2~s3, and previous level is lower 16 | D = 3'd5; //above s3 17 | 18 | reg [2:0] state, next_state; 19 | 20 | always @(posedge clk) begin 21 | if(reset) state <= A; 22 | else state <= next_state; 23 | end 24 | 25 | always @(*) begin 26 | case(state) 27 | A : next_state = (s[1]) ? B1 : A; 28 | B0 : next_state = (s[2]) ? C1 : ((s[1]) ? B0 : A); 29 | B1 : next_state = (s[2]) ? C1 : ((s[1]) ? B1 : A); 30 | C0 : next_state = (s[3]) ? D : ((s[2]) ? C0 : B0); 31 | C1 : next_state = (s[3]) ? D : ((s[2]) ? C1 : B0); 32 | D : next_state = (s[3]) ? D : C0; 33 | default : next_state = 3'bxxx; 34 | endcase 35 | end 36 | 37 | always @(*) begin 38 | case(state) 39 | A : {fr3, fr2, fr1, dfr} = 4'b1111; 40 | B0 : {fr3, fr2, fr1, dfr} = 4'b0111; 41 | B1 : {fr3, fr2, fr1, dfr} = 4'b0110; 42 | C0 : {fr3, fr2, fr1, dfr} = 4'b0011; 43 | C1 : {fr3, fr2, fr1, dfr} = 4'b0010; 44 | D : {fr3, fr2, fr1, dfr} = 4'b0000; 45 | default : {fr3, fr2, fr1, dfr} = 4'bxxxx; 46 | endcase 47 | end 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/18_SerialRecieverWithDataPath.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output [7:0] out_byte, 6 | output done 7 | ); 8 | 9 | // Use FSM from Fsm_serial 10 | localparam [2:0] IDLE = 3'b000, 11 | START = 3'b001, 12 | RECEIVE = 3'b010, 13 | WAIT = 3'b011, 14 | STOP = 3'b100; 15 | 16 | reg [2:0] state, next; 17 | reg [3:0] i; 18 | reg [7:0] out; 19 | 20 | always @(*) begin 21 | case(state) 22 | IDLE : next = (in) ? IDLE : START; 23 | START : next = RECEIVE; 24 | RECEIVE : begin 25 | if (i == 8) begin 26 | if (in) next = STOP; 27 | else next = WAIT; 28 | end 29 | else next = RECEIVE; 30 | end 31 | WAIT : next = (in) ? IDLE : WAIT; 32 | STOP : next = (in) ? IDLE : START; 33 | endcase 34 | end 35 | 36 | always @(posedge clk) begin 37 | if(reset) state <= IDLE; 38 | else state <= next; 39 | end 40 | 41 | always @(posedge clk) begin 42 | if (reset) begin 43 | done <= 0; 44 | i <= 0; 45 | end 46 | else begin 47 | case(next) 48 | RECEIVE : begin 49 | done <= 0; 50 | i = i + 4'h1; 51 | end 52 | STOP : begin 53 | done <= 1; 54 | i <= 0; 55 | end 56 | default : begin 57 | done <= 0; 58 | i <= 0; 59 | end 60 | endcase 61 | end 62 | end 63 | 64 | // New: Datapath to latch input bits. 65 | always @(posedge clk) begin 66 | if (reset) out <= 0; 67 | else if (next == RECEIVE) 68 | out[i] <= in; 69 | end 70 | 71 | assign out_byte = (done) ? out : 8'b0; 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /2. Circuits/3. Building Larger Circuits/06_TheCompleteTimer.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input reset, // Synchronous reset 4 | input data, 5 | output [3:0] count, 6 | output counting, 7 | output done, 8 | input ack 9 | ); 10 | 11 | localparam [3:0] IDLE = 0, 12 | S1 = 1, 13 | S11 = 2, 14 | S110 = 3, 15 | S1101 = 4, //'S1101' and 'SHIFT0' can be regarded as one state. 16 | SHIFT1 = 5, 17 | SHIFT2 = 6, 18 | SHIFT3 = 7, 19 | COUNT = 8, 20 | DONE = 9; 21 | 22 | reg [3:0] state, next; 23 | reg [9:0] count_1000; 24 | 25 | always @(*) begin 26 | case (state) 27 | IDLE : next = (data) ? S1 : IDLE; 28 | S1 : next = (data) ? S11 : IDLE; 29 | S11 : next = (data) ? S11 : S110; 30 | S110 : next = (data) ? S1101 : IDLE; 31 | S1101 : next = SHIFT1; 32 | SHIFT1: next = SHIFT2; 33 | SHIFT2: next = SHIFT3; 34 | SHIFT3: next = COUNT; 35 | COUNT : next = (count == 0 & count_1000 == 999) ? DONE : COUNT; 36 | DONE : next = (ack) ? IDLE : DONE; 37 | endcase 38 | end 39 | 40 | //state transition 41 | always @(posedge clk) begin 42 | if (reset) state <= IDLE; 43 | else state <= next; 44 | end 45 | 46 | //shift in and then down count. 47 | always @(posedge clk) begin 48 | case (state) 49 | S1101 : count[3] <= data; 50 | SHIFT1: count[2] <= data; 51 | SHIFT2: count[1] <= data; 52 | SHIFT3: count[0] <= data; 53 | COUNT : begin 54 | if (count >= 0) begin 55 | if (count_1000 < 999) 56 | count_1000 <= count_1000 + 1'b1; 57 | else begin 58 | count <= count - 1'b1; 59 | count_1000 <= 0; 60 | end 61 | end 62 | end 63 | default : count_1000 <= 0; 64 | endcase 65 | end 66 | 67 | assign counting = (state == COUNT); 68 | assign done = (state == DONE); 69 | 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /5. CS450/04_GShare.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, 4 | 5 | input predict_valid, 6 | input [6:0] predict_pc, 7 | output reg predict_taken, 8 | output reg [6:0] predict_history, 9 | 10 | input train_valid, 11 | input train_taken, 12 | input train_mispredicted, 13 | input [6:0] train_history, 14 | input [6:0] train_pc 15 | ); 16 | 17 | localparam SNT = 2'd0, WNT = 2'd1, WT = 2'd2, ST = 2'd3; 18 | 19 | reg [1:0] PHT [0:127]; 20 | reg [6:0] GHR; 21 | 22 | wire [6:0] predict_index = predict_pc ^ GHR; 23 | 24 | always @(*) begin 25 | if(predict_valid) begin 26 | predict_taken = (PHT[predict_index] >= WT); 27 | predict_history = GHR; 28 | end else begin 29 | predict_taken = 1'b0; 30 | predict_history = 7'd0; 31 | end 32 | end 33 | 34 | wire [6:0] train_index = train_pc ^ train_history; 35 | 36 | integer i; 37 | always @(posedge clk or posedge areset) begin 38 | if(areset) begin 39 | GHR <= 7'd0; 40 | for(i = 0; i < 128; i = i+1) 41 | PHT[i] <= WNT; 42 | end 43 | else begin 44 | if(train_valid) begin 45 | case(PHT[train_index]) 46 | SNT: PHT[train_index] <= train_taken ? WNT : SNT; 47 | WNT: PHT[train_index] <= train_taken ? WT : SNT; 48 | WT: PHT[train_index] <= train_taken ? ST : WNT; 49 | ST: PHT[train_index] <= train_taken ? ST : WT; 50 | endcase 51 | end 52 | if (train_valid && train_mispredicted) begin 53 | GHR <= {train_history[5:0], train_taken}; 54 | end else if (!(train_valid && train_mispredicted) && predict_valid) begin 55 | GHR <= {GHR[5:0], predict_taken}; 56 | end 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/4. More Circuits/03_ConwaysGameofLife16x16.v: -------------------------------------------------------------------------------- 1 | module rule ( 2 | input [7:0] neigh, 3 | input current, 4 | output next ); 5 | 6 | wire [2:0] pop; 7 | assign pop = {2'b00, neigh[0]} + 8 | {2'b00, neigh[1]} + 9 | {2'b00, neigh[2]} + 10 | {2'b00, neigh[3]} + 11 | {2'b00, neigh[4]} + 12 | {2'b00, neigh[5]} + 13 | {2'b00, neigh[6]} + 14 | {2'b00, neigh[7]}; 15 | 16 | reg tmp; 17 | assign next = tmp; 18 | 19 | always @(*) begin 20 | case (pop) 21 | 2: tmp = current; 22 | 3: tmp = 1; 23 | default: tmp = 0; 24 | endcase 25 | end 26 | endmodule 27 | 28 | module top_module( 29 | input clk, 30 | input load, 31 | input [255:0] data, 32 | output [255:0] q ); 33 | 34 | wire [255:0] next; 35 | 36 | genvar x, y; 37 | generate 38 | for (x=0; x<=15; x=x+1) begin : gen_x 39 | for (y=0; y<=15; y=y+1) begin : gen_y 40 | rule fate ( 41 | .neigh({q[(x==0 ? 15 : x-1) + (y==0 ? 15 : y-1)*16], 42 | q[(x==0 ? 15 : x-1) + y *16], 43 | q[(x==0 ? 15 : x-1) + (y==15 ? 0 : y+1)*16], 44 | q[x + (y==0 ? 15 : y-1)*16], 45 | q[x + (y==15 ? 0 : y+1)*16], 46 | q[(x==15 ? 0 : x+1) + (y==0 ? 15 : y-1)*16], 47 | q[(x==15 ? 0 : x+1) + y *16], 48 | q[(x==15 ? 0 : x+1) + (y==15 ? 0 : y+1)*16]}), 49 | .current(q[(x + y*16)]), 50 | .next(next[(x + y*16)]) 51 | ); 52 | end 53 | end 54 | endgenerate 55 | 56 | always @(posedge clk) begin 57 | if (load) begin 58 | q <= data; 59 | end else begin 60 | q <= next; 61 | end 62 | end 63 | endmodule 64 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/12_Lemmings3.v: -------------------------------------------------------------------------------- 1 | odule top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | input dig, 8 | output walk_left, 9 | output walk_right, 10 | output aaah, 11 | output digging 12 | ); 13 | 14 | localparam [2:0] WALK_L = 3'b000, 15 | WALK_R = 3'b001, 16 | FALL_L = 3'b010, 17 | FALL_R = 3'b011, 18 | DIG_L = 3'b100, 19 | DIG_R = 3'b101; 20 | 21 | reg [2:0] state, next; 22 | 23 | always @(posedge clk or posedge areset) begin 24 | if(areset) state <= WALK_L; 25 | else state <= next; 26 | end 27 | 28 | always @(*) begin 29 | case(state) 30 | WALK_L : begin 31 | if(!ground) next = FALL_L; 32 | else begin 33 | if(dig) next = DIG_L; 34 | else begin 35 | if(bump_left) next = WALK_R; 36 | else next = WALK_L; 37 | end 38 | end 39 | end 40 | WALK_R : begin 41 | if(!ground) next = FALL_R; 42 | else begin 43 | if(dig) next = DIG_R; 44 | else begin 45 | if(bump_right) next = WALK_L; 46 | else next = WALK_R; 47 | end 48 | end 49 | end 50 | FALL_L : next = (ground) ? WALK_L : FALL_L; 51 | FALL_R : next = (ground) ? WALK_R : FALL_R; 52 | DIG_L : next = (ground) ? DIG_L : FALL_L; 53 | DIG_R : next = (ground) ? DIG_R : FALL_R; 54 | endcase 55 | end 56 | 57 | assign walk_left = (state == WALK_L); 58 | assign walk_right = (state == WALK_R); 59 | assign aaah = ((state == FALL_L) || (state == FALL_R)); 60 | assign digging = ((state == DIG_L) || (state == DIG_R)); 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/19_SerialRecieverWithParityChecking.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input in, 4 | input reset, // Synchronous reset 5 | output [7:0] out_byte, 6 | output done 7 | ); 8 | 9 | // Use FSM from Fsm_serial 10 | localparam [2:0] IDLE = 3'b000, 11 | START = 3'b001, 12 | RECEIVE = 3'b010, 13 | WAIT = 3'b011, 14 | STOP = 3'b100, 15 | CHECK = 3'b101; 16 | 17 | reg [2:0] state, next; 18 | reg [3:0] i; 19 | reg [7:0] out; 20 | reg odd_reset; 21 | reg odd_reg; 22 | wire odd; 23 | 24 | 25 | always @(*) begin 26 | case(state) 27 | IDLE : next = (in) ? IDLE : START; 28 | START : next = RECEIVE; 29 | RECEIVE : next = (i == 8) ? CHECK : RECEIVE; 30 | CHECK : next = (in) ? STOP : WAIT; 31 | WAIT : next = (in) ? IDLE : WAIT; 32 | STOP : next = (in) ? IDLE : START; 33 | endcase 34 | end 35 | 36 | always @(posedge clk) begin 37 | if(reset) state <= IDLE; 38 | else state <= next; 39 | end 40 | 41 | always @(posedge clk) begin 42 | if (reset) begin 43 | i <= 0; 44 | end 45 | else begin 46 | case(next) 47 | RECEIVE : begin 48 | i = i + 4'h1; 49 | end 50 | STOP : begin 51 | i <= 0; 52 | end 53 | default : begin 54 | i <= 0; 55 | end 56 | endcase 57 | end 58 | end 59 | 60 | // New: Datapath to latch input bits. 61 | always @(posedge clk) begin 62 | if (reset) out <= 0; 63 | else if (next == RECEIVE) 64 | out[i] <= in; 65 | end 66 | 67 | // New: Add parity checking. 68 | parity u_parity( 69 | .clk(clk), 70 | .reset(reset | odd_reset), 71 | .in(in), 72 | .odd(odd)); 73 | 74 | always @(posedge clk) begin 75 | if(reset) odd_reg <= 0; 76 | else odd_reg <= odd; 77 | end 78 | 79 | always @(posedge clk) begin 80 | case(next) 81 | IDLE : odd_reset <= 1; 82 | STOP : odd_reset <= 1; 83 | default : odd_reset <= 0; 84 | endcase 85 | end 86 | 87 | assign done = ((state == STOP) && odd_reg); 88 | assign out_byte = (done) ? out : 8'b0; 89 | 90 | endmodule 91 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/2. Counters/08_12-hourClock.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input reset, 4 | input ena, 5 | output pm, 6 | output [7:0] hh, 7 | output [7:0] mm, 8 | output [7:0] ss); 9 | 10 | reg [2:0] ena_hms; //determine when will "ss","mm" and "hh" need to be increased 11 | assign ena_hms = {(ena && (mm == 8'h59) && (ss == 8'h59)), (ena && (ss == 8'h59)), ena}; 12 | 13 | count60 count_ss( 14 | .clk(clk), 15 | .reset(reset), 16 | .ena(ena_hms[0]), 17 | .q(ss) 18 | ); 19 | count60 count_mm( 20 | .clk(clk), 21 | .reset(reset), 22 | .ena(ena_hms[1]), 23 | .q(mm) 24 | ); 25 | 26 | always @(posedge clk) begin 27 | if(reset) begin 28 | hh <= 8'h12; //hh=12 29 | pm <= 0; 30 | end 31 | else begin 32 | if(ena_hms[2] && (mm == 8'h59) && (ss == 8'h59)) begin //if mm=59 and ss=59 33 | if(hh == 8'h12) hh <= 8'h1; //hh changes:12AM->1AM or 12PM->1PM 34 | else if(hh == 8'h11) begin //if hh=11, PM->AM or AM->PM 35 | hh[3:0] <= hh[3:0] + 1'h1; //hh=12 36 | pm <= ~pm; 37 | end 38 | else begin 39 | if(hh[3:0] == 4'h9) begin 40 | hh[3:0] <= 4'h0; 41 | hh[7:4] <= hh[7:4] + 1'h1; 42 | end 43 | else hh[3:0] = hh[3:0] + 1'h1; 44 | end 45 | end 46 | else hh <= hh; 47 | end 48 | end 49 | 50 | endmodule 51 | 52 | module count60( 53 | input clk, 54 | input reset, 55 | input ena, 56 | output [7:0] q 57 | ); 58 | always @(posedge clk) begin 59 | if(reset) q <= 8'h0; 60 | else begin 61 | if(ena) begin 62 | if(q[3:0] == 4'h9) begin 63 | if(q[7:4] == 4'h5) q <= 8'h0; 64 | else begin 65 | q[7:4] <= q[7:4] + 1'h1; 66 | q[3:0] <= 4'h0; 67 | end 68 | end 69 | else q[3:0] <= q[3:0] + 1'h1; 70 | end 71 | else q <= q; 72 | end 73 | end 74 | endmodule 75 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/33_Q2b:AnotherFSM.v: -------------------------------------------------------------------------------- 1 | module top_module ( 2 | input clk, 3 | input resetn, // active-low synchronous reset 4 | input x, 5 | input y, 6 | output reg f, 7 | output reg g 8 | ); 9 | 10 | parameter A=4'd0, f1=4'd1, tmp0=4'd2, tmp1=4'd3, tmp2=4'd4, g1=4'd5, g1p=4'd6, tmp3=4'd7, g0p=4'd8; 11 | reg [3:0] state, next_state; 12 | 13 | always@(*) begin 14 | case(state) 15 | A: begin 16 | if(resetn) 17 | next_state = f1; 18 | else 19 | next_state = A; 20 | end 21 | f1: next_state = tmp0; 22 | tmp0: begin 23 | if(x) 24 | next_state = tmp1; 25 | else 26 | next_state = tmp0; 27 | end 28 | tmp1: begin 29 | if(~x) 30 | next_state = tmp2; 31 | else 32 | next_state = tmp1; 33 | end 34 | tmp2: begin 35 | if(x) 36 | next_state = g1; 37 | else 38 | next_state = tmp0; 39 | end 40 | g1: begin 41 | if(y) 42 | next_state = g1p; 43 | else 44 | next_state = tmp3; 45 | end 46 | tmp3: begin 47 | if(y) 48 | next_state = g1p; 49 | else 50 | next_state = g0p; 51 | end 52 | g1p: begin 53 | if(~resetn) 54 | next_state = A; 55 | else 56 | next_state = g1p; 57 | end 58 | g0p: begin 59 | if(~resetn) 60 | next_state = A; 61 | else 62 | next_state = g0p; 63 | end 64 | endcase 65 | end 66 | 67 | always@(posedge clk) begin 68 | if(~resetn) 69 | state <= A; 70 | else 71 | state <= next_state; 72 | end 73 | 74 | always@(posedge clk) begin 75 | case(next_state) 76 | f1: f <= 1'b1; 77 | g1: g <= 1'b1; 78 | tmp3: g <= 1'b1; 79 | g1p: g <= 1'b1; 80 | g0p: g <= 1'b0; 81 | default: begin 82 | f <= 1'b0; 83 | g <= 1'b0; 84 | end 85 | endcase 86 | end 87 | 88 | endmodule 89 | -------------------------------------------------------------------------------- /2. Circuits/2. Sequential Logic/5. Finite State Machines/13_Lemmings4.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input areset, // Freshly brainwashed Lemmings walk left. 4 | input bump_left, 5 | input bump_right, 6 | input ground, 7 | input dig, 8 | output walk_left, 9 | output walk_right, 10 | output aaah, 11 | output digging 12 | ); 13 | 14 | localparam [2:0] WALK_L = 3'b000, 15 | WALK_R = 3'b001, 16 | FALL_L = 3'b010, 17 | FALL_R = 3'b011, 18 | DIG_L = 3'b100, 19 | DIG_R = 3'b101, 20 | SPLATTER = 3'b110; 21 | 22 | reg [2:0] state, next; 23 | reg [6:0] count; 24 | 25 | always @(posedge clk or posedge areset) begin 26 | if(areset) state <= WALK_L; 27 | else if(state == FALL_R || state == FALL_L) begin 28 | count <= count + 1; 29 | state <= next; 30 | end 31 | else begin 32 | state <= next; 33 | count <= 0; 34 | end 35 | end 36 | 37 | always @(*) begin 38 | case(state) 39 | WALK_L : begin 40 | if(!ground) next = FALL_L; 41 | else begin 42 | if(dig) next = DIG_L; 43 | else begin 44 | if(bump_left) next = WALK_R; 45 | else next = WALK_L; 46 | end 47 | end 48 | end 49 | WALK_R : begin 50 | if(!ground) next = FALL_R; 51 | else begin 52 | if(dig) next = DIG_R; 53 | else begin 54 | if(bump_right) next = WALK_L; 55 | else next = WALK_R; 56 | end 57 | end 58 | end 59 | FALL_L : begin 60 | if(ground) begin 61 | if(count > 19) next = SPLATTER; 62 | else next = WALK_L; 63 | end 64 | else next = FALL_L; 65 | end 66 | FALL_R : begin 67 | if(ground) begin 68 | if(count > 19) next = SPLATTER; 69 | else next = WALK_R; 70 | end 71 | else next = FALL_R; 72 | end 73 | DIG_L : next = (ground) ? DIG_L : FALL_L; 74 | DIG_R : next = (ground) ? DIG_R : FALL_R; 75 | SPLATTER : next = SPLATTER; 76 | endcase 77 | end 78 | 79 | assign walk_left = (state == WALK_L); 80 | assign walk_right = (state == WALK_R); 81 | assign aaah = ((state == FALL_L) || (state == FALL_R)); 82 | assign digging = ((state == DIG_L) || (state == DIG_R)); 83 | 84 | endmodule 85 | --------------------------------------------------------------------------------