├── .gitignore ├── C910_RTL_FACTORY ├── gen_rtl │ ├── biu │ │ └── rtl │ │ │ ├── ct_biu_csr_req_arbiter.sv │ │ │ ├── ct_biu_lowpower.sv │ │ │ ├── ct_biu_other_io_sync.sv │ │ │ ├── ct_biu_read_channel.sv │ │ │ ├── ct_biu_req_arbiter.sv │ │ │ ├── ct_biu_snoop_channel.sv │ │ │ ├── ct_biu_top.sv │ │ │ └── ct_biu_write_channel.sv │ ├── ciu │ │ └── rtl │ │ │ ├── ct_ciu_apbif.sv │ │ │ ├── ct_ciu_bmbif.sv │ │ │ ├── ct_ciu_bmbif_kid.sv │ │ │ ├── ct_ciu_ctcq.sv │ │ │ ├── ct_ciu_ctcq_reqq_entry.sv │ │ │ ├── ct_ciu_ctcq_respq_entry.sv │ │ │ ├── ct_ciu_ebiuif.sv │ │ │ ├── ct_ciu_l2cif.sv │ │ │ ├── ct_ciu_ncq.sv │ │ │ ├── ct_ciu_ncq_gm.sv │ │ │ ├── ct_ciu_regs.sv │ │ │ ├── ct_ciu_regs_kid.sv │ │ │ ├── ct_ciu_snb.sv │ │ │ ├── ct_ciu_snb_arb.sv │ │ │ ├── ct_ciu_snb_dp_sel.sv │ │ │ ├── ct_ciu_snb_dp_sel_16.sv │ │ │ ├── ct_ciu_snb_dp_sel_8.sv │ │ │ ├── ct_ciu_snb_sab.sv │ │ │ ├── ct_ciu_snb_sab_entry.sv │ │ │ ├── ct_ciu_top.sv │ │ │ ├── ct_ciu_vb.sv │ │ │ ├── ct_ciu_vb_aw_entry.sv │ │ │ ├── ct_ebiu_cawt_entry.sv │ │ │ ├── ct_ebiu_lowpower.sv │ │ │ ├── ct_ebiu_ncwt_entry.sv │ │ │ ├── ct_ebiu_read_channel.sv │ │ │ ├── ct_ebiu_snoop_channel_dummy.sv │ │ │ ├── ct_ebiu_top.sv │ │ │ ├── ct_ebiu_write_channel.sv │ │ │ ├── ct_fifo.sv │ │ │ ├── ct_piu_other_io.sv │ │ │ ├── ct_piu_other_io_dummy.sv │ │ │ ├── ct_piu_other_io_sync.sv │ │ │ ├── ct_piu_top.sv │ │ │ ├── ct_piu_top_dummy.sv │ │ │ ├── ct_piu_top_dummy_device.sv │ │ │ └── ct_prio.sv │ ├── clint │ │ └── rtl │ │ │ ├── ct_clint_func.sv │ │ │ └── ct_clint_top.sv │ ├── clk │ │ └── rtl │ │ │ ├── ct_clk_top.sv │ │ │ ├── ct_mp_clk_top.sv │ │ │ └── gated_clk_cell.sv │ ├── common │ │ └── rtl │ │ │ ├── BUFGCE.sv │ │ │ ├── booth_code.sv │ │ │ ├── booth_code_v1.sv │ │ │ ├── compressor_32.sv │ │ │ ├── compressor_42.sv │ │ │ ├── sync_level2level.sv │ │ │ └── sync_level2pulse.sv │ ├── cp0 │ │ └── rtl │ │ │ ├── ct_cp0_iui.sv │ │ │ ├── ct_cp0_lpmd.sv │ │ │ ├── ct_cp0_regs.sv │ │ │ └── ct_cp0_top.sv │ ├── cpu │ │ └── rtl │ │ │ ├── cpu_cfig.h │ │ │ ├── ct_core.sv │ │ │ ├── ct_rmu_top_dummy.sv │ │ │ ├── ct_sysio_kid.sv │ │ │ ├── ct_sysio_top.sv │ │ │ ├── ct_top.sv │ │ │ ├── mp_top_golden_port.sv │ │ │ ├── openC910.sv │ │ │ └── top_golden_port.sv │ ├── filelists │ │ └── C910_asic_rtl.fl │ ├── fpga │ │ └── rtl │ │ │ ├── ct_f_spsram_1024x128.sv │ │ │ ├── ct_f_spsram_1024x144.sv │ │ │ ├── ct_f_spsram_1024x32.sv │ │ │ ├── ct_f_spsram_1024x59.sv │ │ │ ├── ct_f_spsram_1024x64.sv │ │ │ ├── ct_f_spsram_1024x92.sv │ │ │ ├── ct_f_spsram_128x104.sv │ │ │ ├── ct_f_spsram_128x144.sv │ │ │ ├── ct_f_spsram_128x16.sv │ │ │ ├── ct_f_spsram_16384x128.sv │ │ │ ├── ct_f_spsram_2048x128.sv │ │ │ ├── ct_f_spsram_2048x144.sv │ │ │ ├── ct_f_spsram_2048x32.sv │ │ │ ├── ct_f_spsram_2048x59.sv │ │ │ ├── ct_f_spsram_2048x88.sv │ │ │ ├── ct_f_spsram_256x100.sv │ │ │ ├── ct_f_spsram_256x144.sv │ │ │ ├── ct_f_spsram_256x196.sv │ │ │ ├── ct_f_spsram_256x23.sv │ │ │ ├── ct_f_spsram_256x52.sv │ │ │ ├── ct_f_spsram_256x54.sv │ │ │ ├── ct_f_spsram_256x59.sv │ │ │ ├── ct_f_spsram_256x7.sv │ │ │ ├── ct_f_spsram_256x84.sv │ │ │ ├── ct_f_spsram_32768x128.sv │ │ │ ├── ct_f_spsram_4096x128.sv │ │ │ ├── ct_f_spsram_4096x144.sv │ │ │ ├── ct_f_spsram_4096x32.sv │ │ │ ├── ct_f_spsram_4096x84.sv │ │ │ ├── ct_f_spsram_512x144.sv │ │ │ ├── ct_f_spsram_512x22.sv │ │ │ ├── ct_f_spsram_512x44.sv │ │ │ ├── ct_f_spsram_512x52.sv │ │ │ ├── ct_f_spsram_512x54.sv │ │ │ ├── ct_f_spsram_512x59.sv │ │ │ ├── ct_f_spsram_512x7.sv │ │ │ ├── ct_f_spsram_512x96.sv │ │ │ ├── ct_f_spsram_64x108.sv │ │ │ ├── ct_f_spsram_65536x128.sv │ │ │ ├── ct_f_spsram_8192x128.sv │ │ │ ├── ct_f_spsram_8192x32.sv │ │ │ └── fpga_ram.sv │ ├── had │ │ └── rtl │ │ │ ├── ct_had_bkpt.sv │ │ │ ├── ct_had_common_dbg_info.sv │ │ │ ├── ct_had_common_regs.sv │ │ │ ├── ct_had_common_top.sv │ │ │ ├── ct_had_ctrl.sv │ │ │ ├── ct_had_dbg_info.sv │ │ │ ├── ct_had_ddc_ctrl.sv │ │ │ ├── ct_had_ddc_dp.sv │ │ │ ├── ct_had_etm.sv │ │ │ ├── ct_had_etm_if.sv │ │ │ ├── ct_had_event.sv │ │ │ ├── ct_had_io.sv │ │ │ ├── ct_had_ir.sv │ │ │ ├── ct_had_nirv_bkpt.sv │ │ │ ├── ct_had_pcfifo.sv │ │ │ ├── ct_had_private_ir.sv │ │ │ ├── ct_had_private_top.sv │ │ │ ├── ct_had_regs.sv │ │ │ ├── ct_had_serial.sv │ │ │ ├── ct_had_sm.sv │ │ │ ├── ct_had_sync_3flop.sv │ │ │ └── ct_had_trace.sv │ ├── idu │ │ └── rtl │ │ │ ├── ct_idu_dep_reg_entry.sv │ │ │ ├── ct_idu_dep_reg_src2_entry.sv │ │ │ ├── ct_idu_dep_vreg_entry.sv │ │ │ ├── ct_idu_dep_vreg_srcv2_entry.sv │ │ │ ├── ct_idu_id_ctrl.sv │ │ │ ├── ct_idu_id_decd.sv │ │ │ ├── ct_idu_id_decd_special.sv │ │ │ ├── ct_idu_id_dp.sv │ │ │ ├── ct_idu_id_fence.sv │ │ │ ├── ct_idu_id_split_long.sv │ │ │ ├── ct_idu_id_split_short.sv │ │ │ ├── ct_idu_ir_ctrl.sv │ │ │ ├── ct_idu_ir_decd.sv │ │ │ ├── ct_idu_ir_dp.sv │ │ │ ├── ct_idu_ir_frt.sv │ │ │ ├── ct_idu_ir_rt.sv │ │ │ ├── ct_idu_ir_vrt.sv │ │ │ ├── ct_idu_is_aiq0.sv │ │ │ ├── ct_idu_is_aiq0_entry.sv │ │ │ ├── ct_idu_is_aiq1.sv │ │ │ ├── ct_idu_is_aiq1_entry.sv │ │ │ ├── ct_idu_is_aiq_lch_rdy_1.sv │ │ │ ├── ct_idu_is_aiq_lch_rdy_2.sv │ │ │ ├── ct_idu_is_aiq_lch_rdy_3.sv │ │ │ ├── ct_idu_is_biq.sv │ │ │ ├── ct_idu_is_biq_entry.sv │ │ │ ├── ct_idu_is_ctrl.sv │ │ │ ├── ct_idu_is_dp.sv │ │ │ ├── ct_idu_is_lsiq.sv │ │ │ ├── ct_idu_is_lsiq_entry.sv │ │ │ ├── ct_idu_is_pipe_entry.sv │ │ │ ├── ct_idu_is_sdiq.sv │ │ │ ├── ct_idu_is_sdiq_entry.sv │ │ │ ├── ct_idu_is_viq0.sv │ │ │ ├── ct_idu_is_viq0_entry.sv │ │ │ ├── ct_idu_is_viq1.sv │ │ │ ├── ct_idu_is_viq1_entry.sv │ │ │ ├── ct_idu_rf_ctrl.sv │ │ │ ├── ct_idu_rf_dp.sv │ │ │ ├── ct_idu_rf_fwd.sv │ │ │ ├── ct_idu_rf_fwd_preg.sv │ │ │ ├── ct_idu_rf_fwd_vreg.sv │ │ │ ├── ct_idu_rf_pipe0_decd.sv │ │ │ ├── ct_idu_rf_pipe1_decd.sv │ │ │ ├── ct_idu_rf_pipe2_decd.sv │ │ │ ├── ct_idu_rf_pipe3_decd.sv │ │ │ ├── ct_idu_rf_pipe4_decd.sv │ │ │ ├── ct_idu_rf_pipe6_decd.sv │ │ │ ├── ct_idu_rf_pipe7_decd.sv │ │ │ ├── ct_idu_rf_prf_eregfile.sv │ │ │ ├── ct_idu_rf_prf_fregfile.sv │ │ │ ├── ct_idu_rf_prf_gated_ereg.sv │ │ │ ├── ct_idu_rf_prf_gated_preg.sv │ │ │ ├── ct_idu_rf_prf_gated_vreg.sv │ │ │ ├── ct_idu_rf_prf_pregfile.sv │ │ │ ├── ct_idu_rf_prf_vregfile.sv │ │ │ └── ct_idu_top.sv │ ├── ifu │ │ └── rtl │ │ │ ├── ct_ifu_addrgen.sv │ │ │ ├── ct_ifu_bht.sv │ │ │ ├── ct_ifu_bht_pre_array.sv │ │ │ ├── ct_ifu_bht_sel_array.sv │ │ │ ├── ct_ifu_btb.sv │ │ │ ├── ct_ifu_btb_data_array.sv │ │ │ ├── ct_ifu_btb_tag_array.sv │ │ │ ├── ct_ifu_debug.sv │ │ │ ├── ct_ifu_decd_normal.sv │ │ │ ├── ct_ifu_ibctrl.sv │ │ │ ├── ct_ifu_ibdp.sv │ │ │ ├── ct_ifu_ibuf.sv │ │ │ ├── ct_ifu_ibuf_entry.sv │ │ │ ├── ct_ifu_icache_data_array0.sv │ │ │ ├── ct_ifu_icache_data_array1.sv │ │ │ ├── ct_ifu_icache_if.sv │ │ │ ├── ct_ifu_icache_predecd_array0.sv │ │ │ ├── ct_ifu_icache_predecd_array1.sv │ │ │ ├── ct_ifu_icache_tag_array.sv │ │ │ ├── ct_ifu_ifctrl.sv │ │ │ ├── ct_ifu_ifdp.sv │ │ │ ├── ct_ifu_ind_btb.sv │ │ │ ├── ct_ifu_ind_btb_array.sv │ │ │ ├── ct_ifu_ipb.sv │ │ │ ├── ct_ifu_ipctrl.sv │ │ │ ├── ct_ifu_ipdecode.sv │ │ │ ├── ct_ifu_ipdp.sv │ │ │ ├── ct_ifu_l0_btb.sv │ │ │ ├── ct_ifu_l0_btb_entry.sv │ │ │ ├── ct_ifu_l1_refill.sv │ │ │ ├── ct_ifu_lbuf.sv │ │ │ ├── ct_ifu_lbuf_entry.sv │ │ │ ├── ct_ifu_pcfifo_if.sv │ │ │ ├── ct_ifu_pcgen.sv │ │ │ ├── ct_ifu_precode.sv │ │ │ ├── ct_ifu_ras.sv │ │ │ ├── ct_ifu_sfp.sv │ │ │ ├── ct_ifu_sfp_entry.sv │ │ │ ├── ct_ifu_top.sv │ │ │ ├── ct_ifu_vector.sv │ │ │ ├── ct_spsram_1024x59.sv │ │ │ ├── ct_spsram_1024x64.sv │ │ │ ├── ct_spsram_128x16.sv │ │ │ ├── ct_spsram_2048x32_split.sv │ │ │ ├── ct_spsram_2048x59.sv │ │ │ ├── ct_spsram_256x23.sv │ │ │ ├── ct_spsram_256x59.sv │ │ │ ├── ct_spsram_512x22.sv │ │ │ ├── ct_spsram_512x44.sv │ │ │ └── ct_spsram_512x59.sv │ ├── iu │ │ └── rtl │ │ │ ├── ct_iu_alu.sv │ │ │ ├── ct_iu_bju.sv │ │ │ ├── ct_iu_bju_pcfifo.sv │ │ │ ├── ct_iu_bju_pcfifo_entry.sv │ │ │ ├── ct_iu_bju_pcfifo_read_entry.sv │ │ │ ├── ct_iu_cbus.sv │ │ │ ├── ct_iu_div.sv │ │ │ ├── ct_iu_div_entry.sv │ │ │ ├── ct_iu_div_srt_radix16.sv │ │ │ ├── ct_iu_mult.sv │ │ │ ├── ct_iu_rbus.sv │ │ │ ├── ct_iu_special.sv │ │ │ ├── ct_iu_top.sv │ │ │ └── multiplier_65x65_3_stage.sv │ ├── l2c │ │ └── rtl │ │ │ ├── ct_l2c_cmp.sv │ │ │ ├── ct_l2c_data.sv │ │ │ ├── ct_l2c_icc.sv │ │ │ ├── ct_l2c_prefetch.sv │ │ │ ├── ct_l2c_sub_bank.sv │ │ │ ├── ct_l2c_tag.sv │ │ │ ├── ct_l2c_tag_ecc.sv │ │ │ ├── ct_l2c_top.sv │ │ │ ├── ct_l2c_wb.sv │ │ │ ├── ct_l2cache_data_array.sv │ │ │ ├── ct_l2cache_dirty_array_16way.sv │ │ │ ├── ct_l2cache_tag_array_16way.sv │ │ │ ├── ct_l2cache_top.sv │ │ │ ├── ct_spsram_1024x128.sv │ │ │ ├── ct_spsram_1024x144.sv │ │ │ ├── ct_spsram_1024x92.sv │ │ │ ├── ct_spsram_128x104.sv │ │ │ ├── ct_spsram_128x144.sv │ │ │ ├── ct_spsram_16384x128.sv │ │ │ ├── ct_spsram_2048x128.sv │ │ │ ├── ct_spsram_2048x144.sv │ │ │ ├── ct_spsram_2048x88.sv │ │ │ ├── ct_spsram_256x100.sv │ │ │ ├── ct_spsram_256x144.sv │ │ │ ├── ct_spsram_32768x128.sv │ │ │ ├── ct_spsram_4096x128.sv │ │ │ ├── ct_spsram_4096x144.sv │ │ │ ├── ct_spsram_4096x84.sv │ │ │ ├── ct_spsram_512x144.sv │ │ │ ├── ct_spsram_512x96.sv │ │ │ ├── ct_spsram_64x108.sv │ │ │ ├── ct_spsram_65536x128.sv │ │ │ └── ct_spsram_8192x128.sv │ ├── lsu │ │ └── rtl │ │ │ ├── ct_lsu_amr.sv │ │ │ ├── ct_lsu_bus_arb.sv │ │ │ ├── ct_lsu_cache_buffer.sv │ │ │ ├── ct_lsu_ctrl.sv │ │ │ ├── ct_lsu_dcache_arb.sv │ │ │ ├── ct_lsu_dcache_data_array.sv │ │ │ ├── ct_lsu_dcache_dirty_array.sv │ │ │ ├── ct_lsu_dcache_info_update.sv │ │ │ ├── ct_lsu_dcache_ld_tag_array.sv │ │ │ ├── ct_lsu_dcache_tag_array.sv │ │ │ ├── ct_lsu_dcache_top.sv │ │ │ ├── ct_lsu_icc.sv │ │ │ ├── ct_lsu_idfifo_8.sv │ │ │ ├── ct_lsu_idfifo_entry.sv │ │ │ ├── ct_lsu_ld_ag.sv │ │ │ ├── ct_lsu_ld_da.sv │ │ │ ├── ct_lsu_ld_dc.sv │ │ │ ├── ct_lsu_ld_wb.sv │ │ │ ├── ct_lsu_lfb.sv │ │ │ ├── ct_lsu_lfb_addr_entry.sv │ │ │ ├── ct_lsu_lfb_data_entry.sv │ │ │ ├── ct_lsu_lm.sv │ │ │ ├── ct_lsu_lq.sv │ │ │ ├── ct_lsu_lq_entry.sv │ │ │ ├── ct_lsu_mcic.sv │ │ │ ├── ct_lsu_pfu.sv │ │ │ ├── ct_lsu_pfu_gpfb.sv │ │ │ ├── ct_lsu_pfu_gsdb.sv │ │ │ ├── ct_lsu_pfu_pfb_entry.sv │ │ │ ├── ct_lsu_pfu_pfb_l1sm.sv │ │ │ ├── ct_lsu_pfu_pfb_l2sm.sv │ │ │ ├── ct_lsu_pfu_pfb_tsm.sv │ │ │ ├── ct_lsu_pfu_pmb_entry.sv │ │ │ ├── ct_lsu_pfu_sdb_cmp.sv │ │ │ ├── ct_lsu_pfu_sdb_entry.sv │ │ │ ├── ct_lsu_rb.sv │ │ │ ├── ct_lsu_rb_entry.sv │ │ │ ├── ct_lsu_rot_data.sv │ │ │ ├── ct_lsu_sd_ex1.sv │ │ │ ├── ct_lsu_snoop_ctcq.sv │ │ │ ├── ct_lsu_snoop_ctcq_entry.sv │ │ │ ├── ct_lsu_snoop_req_arbiter.sv │ │ │ ├── ct_lsu_snoop_resp.sv │ │ │ ├── ct_lsu_snoop_snq.sv │ │ │ ├── ct_lsu_snoop_snq_entry.sv │ │ │ ├── ct_lsu_spec_fail_predict.sv │ │ │ ├── ct_lsu_sq.sv │ │ │ ├── ct_lsu_sq_entry.sv │ │ │ ├── ct_lsu_st_ag.sv │ │ │ ├── ct_lsu_st_da.sv │ │ │ ├── ct_lsu_st_dc.sv │ │ │ ├── ct_lsu_st_wb.sv │ │ │ ├── ct_lsu_top.sv │ │ │ ├── ct_lsu_vb.sv │ │ │ ├── ct_lsu_vb_addr_entry.sv │ │ │ ├── ct_lsu_vb_sdb_data.sv │ │ │ ├── ct_lsu_vb_sdb_data_entry.sv │ │ │ ├── ct_lsu_wmb.sv │ │ │ ├── ct_lsu_wmb_ce.sv │ │ │ ├── ct_lsu_wmb_entry.sv │ │ │ ├── ct_spsram_1024x32.sv │ │ │ ├── ct_spsram_2048x32.sv │ │ │ ├── ct_spsram_256x52.sv │ │ │ ├── ct_spsram_256x54.sv │ │ │ ├── ct_spsram_256x7.sv │ │ │ ├── ct_spsram_4096x32.sv │ │ │ ├── ct_spsram_512x52.sv │ │ │ ├── ct_spsram_512x54.sv │ │ │ ├── ct_spsram_512x7.sv │ │ │ └── ct_spsram_8192x32.sv │ ├── mmu │ │ └── rtl │ │ │ ├── ct_mmu_arb.sv │ │ │ ├── ct_mmu_dplru.sv │ │ │ ├── ct_mmu_dutlb.sv │ │ │ ├── ct_mmu_dutlb_entry.sv │ │ │ ├── ct_mmu_dutlb_huge_entry.sv │ │ │ ├── ct_mmu_dutlb_read.sv │ │ │ ├── ct_mmu_iplru.sv │ │ │ ├── ct_mmu_iutlb.sv │ │ │ ├── ct_mmu_iutlb_entry.sv │ │ │ ├── ct_mmu_iutlb_fst_entry.sv │ │ │ ├── ct_mmu_jtlb.sv │ │ │ ├── ct_mmu_jtlb_data_array.sv │ │ │ ├── ct_mmu_jtlb_tag_array.sv │ │ │ ├── ct_mmu_ptw.sv │ │ │ ├── ct_mmu_regs.sv │ │ │ ├── ct_mmu_sysmap.sv │ │ │ ├── ct_mmu_sysmap_hit.sv │ │ │ ├── ct_mmu_tlboper.sv │ │ │ ├── ct_mmu_top.sv │ │ │ ├── ct_spsram_256x196.sv │ │ │ ├── ct_spsram_256x84.sv │ │ │ └── sysmap.h │ ├── plic │ │ └── rtl │ │ │ ├── csky_apb_1tox_matrix.sv │ │ │ ├── plic_32to1_arb.sv │ │ │ ├── plic_arb_ctrl.sv │ │ │ ├── plic_ctrl.sv │ │ │ ├── plic_granu2_arb.sv │ │ │ ├── plic_granu_arb.sv │ │ │ ├── plic_hart_arb.sv │ │ │ ├── plic_hreg_busif.sv │ │ │ ├── plic_int_kid.sv │ │ │ ├── plic_kid_busif.sv │ │ │ └── plic_top.sv │ ├── pmp │ │ └── rtl │ │ │ ├── ct_pmp_acc.sv │ │ │ ├── ct_pmp_comp_hit.sv │ │ │ ├── ct_pmp_regs.sv │ │ │ └── ct_pmp_top.sv │ ├── pmu │ │ └── rtl │ │ │ ├── ct_hpcp_adder_sel.sv │ │ │ ├── ct_hpcp_cnt.sv │ │ │ ├── ct_hpcp_cntinten_reg.sv │ │ │ ├── ct_hpcp_cntof_reg.sv │ │ │ ├── ct_hpcp_event.sv │ │ │ └── ct_hpcp_top.sv │ ├── rst │ │ └── rtl │ │ │ ├── ct_mp_rst_top.sv │ │ │ └── ct_rst_top.sv │ ├── rtu │ │ └── rtl │ │ │ ├── ct_rtu_compare_iid.sv │ │ │ ├── ct_rtu_encode_32.sv │ │ │ ├── ct_rtu_encode_64.sv │ │ │ ├── ct_rtu_encode_8.sv │ │ │ ├── ct_rtu_encode_96.sv │ │ │ ├── ct_rtu_expand_32.sv │ │ │ ├── ct_rtu_expand_64.sv │ │ │ ├── ct_rtu_expand_8.sv │ │ │ ├── ct_rtu_expand_96.sv │ │ │ ├── ct_rtu_pst_ereg.sv │ │ │ ├── ct_rtu_pst_ereg_entry.sv │ │ │ ├── ct_rtu_pst_preg.sv │ │ │ ├── ct_rtu_pst_preg_entry.sv │ │ │ ├── ct_rtu_pst_vreg.sv │ │ │ ├── ct_rtu_pst_vreg_dummy.sv │ │ │ ├── ct_rtu_pst_vreg_entry.sv │ │ │ ├── ct_rtu_retire.sv │ │ │ ├── ct_rtu_rob.sv │ │ │ ├── ct_rtu_rob_entry.sv │ │ │ ├── ct_rtu_rob_expt.sv │ │ │ ├── ct_rtu_rob_rt.sv │ │ │ └── ct_rtu_top.sv │ ├── vfalu │ │ └── rtl │ │ │ ├── ct_fadd_close_s0_d.sv │ │ │ ├── ct_fadd_close_s0_h.sv │ │ │ ├── ct_fadd_close_s1_d.sv │ │ │ ├── ct_fadd_close_s1_h.sv │ │ │ ├── ct_fadd_ctrl.sv │ │ │ ├── ct_fadd_double_dp.sv │ │ │ ├── ct_fadd_half_dp.sv │ │ │ ├── ct_fadd_onehot_sel_d.sv │ │ │ ├── ct_fadd_onehot_sel_h.sv │ │ │ ├── ct_fadd_scalar_dp.sv │ │ │ ├── ct_fadd_top.sv │ │ │ ├── ct_fcnvt_ctrl.sv │ │ │ ├── ct_fcnvt_double_dp.sv │ │ │ ├── ct_fcnvt_dtoh_sh.sv │ │ │ ├── ct_fcnvt_dtos_sh.sv │ │ │ ├── ct_fcnvt_ftoi_sh.sv │ │ │ ├── ct_fcnvt_htos_sh.sv │ │ │ ├── ct_fcnvt_itof_sh.sv │ │ │ ├── ct_fcnvt_scalar_dp.sv │ │ │ ├── ct_fcnvt_stod_sh.sv │ │ │ ├── ct_fcnvt_stoh_sh.sv │ │ │ ├── ct_fcnvt_top.sv │ │ │ ├── ct_fspu_ctrl.sv │ │ │ ├── ct_fspu_double.sv │ │ │ ├── ct_fspu_dp.sv │ │ │ ├── ct_fspu_half.sv │ │ │ ├── ct_fspu_single.sv │ │ │ ├── ct_fspu_top.sv │ │ │ ├── ct_vfalu_dp_pipe6.sv │ │ │ ├── ct_vfalu_dp_pipe7.sv │ │ │ ├── ct_vfalu_top_pipe6.sv │ │ │ └── ct_vfalu_top_pipe7.sv │ ├── vfdsu │ │ └── rtl │ │ │ ├── ct_vfdsu_ctrl.sv │ │ │ ├── ct_vfdsu_double.sv │ │ │ ├── ct_vfdsu_ff1.sv │ │ │ ├── ct_vfdsu_pack.sv │ │ │ ├── ct_vfdsu_prepare.sv │ │ │ ├── ct_vfdsu_round.sv │ │ │ ├── ct_vfdsu_scalar_dp.sv │ │ │ ├── ct_vfdsu_srt.sv │ │ │ ├── ct_vfdsu_srt_radix16_bound_table.sv │ │ │ ├── ct_vfdsu_srt_radix16_only_div.sv │ │ │ ├── ct_vfdsu_srt_radix16_with_sqrt.sv │ │ │ └── ct_vfdsu_top.sv │ ├── vfmau │ │ └── rtl │ │ │ ├── ct_vfmau_ctrl.sv │ │ │ ├── ct_vfmau_dp.sv │ │ │ ├── ct_vfmau_ff1_10bit.sv │ │ │ ├── ct_vfmau_lza.sv │ │ │ ├── ct_vfmau_lza_32.sv │ │ │ ├── ct_vfmau_lza_42.sv │ │ │ ├── ct_vfmau_lza_simd_half.sv │ │ │ ├── ct_vfmau_mult1.sv │ │ │ ├── ct_vfmau_mult_compressor.sv │ │ │ ├── ct_vfmau_mult_simd_half.sv │ │ │ └── ct_vfmau_top.sv │ └── vfpu │ │ └── rtl │ │ ├── ct_vfpu_cbus.sv │ │ ├── ct_vfpu_ctrl.sv │ │ ├── ct_vfpu_dp.sv │ │ ├── ct_vfpu_rbus.sv │ │ └── ct_vfpu_top.sv └── setup │ └── setup.csh ├── README.md ├── doc ├── openc910_datasheet.pdf ├── 玄铁C910用户手册.pdf └── 玄铁C910集成手册.pdf ├── smart_run ├── Makefile ├── impl │ ├── mem_icg_test │ │ ├── README │ │ ├── cpu_bht_mem_test_tb.sv │ │ ├── cpu_btb_mem_test_tb.sv │ │ ├── cpu_dmem_test_tb.sv │ │ ├── cpu_icg_test_tb.sv │ │ ├── cpu_ifupred_mem_test_tb.sv │ │ ├── cpu_imem_test_tb.sv │ │ ├── cpu_l2_mem_test_tb.sv │ │ ├── cpu_mem_icg_check_top.sv │ │ ├── cpu_mmu_mem_test_tb.sv │ │ ├── filelist_mem_icg_test │ │ ├── mem_icg_check_top.sv │ │ └── run_mem_icg_test │ ├── memlist │ │ └── memlist.pl │ ├── sdc │ │ ├── ct_top.sdc │ │ └── openC910.sdc │ └── upf │ │ └── example_cpu_power_spec.upf ├── lint │ └── Makefile ├── logical │ ├── ahb │ │ ├── ahb.sv │ │ └── ahb2apb.sv │ ├── apb │ │ ├── apb.sv │ │ └── apb_bridge.sv │ ├── axi │ │ ├── axi2ahb.sv │ │ ├── axi_err128.sv │ │ ├── axi_fifo.sv │ │ ├── axi_fifo_entry.sv │ │ ├── axi_interconnect128.sv │ │ └── axi_slave128.sv │ ├── common │ │ ├── BUFGCE.sv │ │ ├── clk_gen.sv │ │ ├── cpu_sub_system_axi.sv │ │ ├── err_gen.sv │ │ ├── fifo_counter.sv │ │ ├── fpga_clk_gen.sv │ │ ├── rv_integration_platform.sv │ │ ├── soc.sv │ │ ├── timer.sv │ │ ├── wid_entry.sv │ │ └── wid_for_axi4.sv │ ├── filelists │ │ ├── ip.fl │ │ ├── sim.fl │ │ ├── sim_verilator.fl │ │ ├── smart.fl │ │ ├── tb.fl │ │ └── tb_verilator.fl │ ├── gpio │ │ ├── gpio.sv │ │ ├── gpio_apbif.sv │ │ └── gpio_ctrl.sv │ ├── mem │ │ ├── f_spsram_32768x128.sv │ │ ├── f_spsram_large.sv │ │ ├── mem_ctrl.sv │ │ └── ram.sv │ ├── pmu │ │ ├── pmu.sv │ │ ├── px_had_sync.sv │ │ ├── sync.sv │ │ └── tap2_sm.sv │ ├── tb │ │ ├── Makefile_obj │ │ ├── int_mnt.sv │ │ ├── sim_main1.cpp │ │ ├── tb.sv │ │ └── tb_verilator.sv │ └── uart │ │ ├── uart.sv │ │ ├── uart_apb_reg.sv │ │ ├── uart_baud_gen.sv │ │ ├── uart_ctrl.sv │ │ ├── uart_receive.sv │ │ └── uart_trans.sv ├── setup │ ├── env_check.mk │ ├── example_setup.csh │ ├── nc.tcl │ └── smart_cfg.mk ├── spyglass │ ├── README │ ├── c910_test.sgdc │ └── c910_test.tcl ├── tests │ ├── bin │ │ └── Srec2vmem │ ├── cases │ │ ├── ISA │ │ │ ├── ISA_AMO │ │ │ │ └── ct_lsu_amo_basic_smart.s │ │ │ ├── ISA_BARRIER │ │ │ │ └── ct_lsu_barrier_smart.s │ │ │ ├── ISA_FP │ │ │ │ └── ct_fpu_smoke.s │ │ │ ├── ISA_IMAC │ │ │ │ └── ct_imac_smoke.s │ │ │ └── ISA_THEAD │ │ │ │ └── isa_thead_smoke.s │ │ ├── MMU │ │ │ └── ct_mmu_basic.s │ │ ├── cache │ │ │ └── idcache_oper │ │ │ │ └── ct_idcache_oper.s │ │ ├── coremark │ │ │ ├── core_list_join.c │ │ │ ├── core_main.c │ │ │ ├── core_matrix.c │ │ │ ├── core_portme.c │ │ │ ├── core_portme.h │ │ │ ├── core_state.c │ │ │ ├── core_util.c │ │ │ ├── coremark.h │ │ │ └── cvt.c │ │ ├── csr │ │ │ └── ct_csr_operate.s │ │ ├── debug │ │ │ ├── debug_gpr │ │ │ │ ├── debug_read_write_gpr.s │ │ │ │ ├── debug_read_write_gpr.sv │ │ │ │ └── had_drv.vh │ │ │ ├── debug_memory │ │ │ │ ├── debug_read_write_memory.s │ │ │ │ ├── debug_read_write_memory.sv │ │ │ │ └── had_drv.vh │ │ │ ├── debug_stim.sv │ │ │ ├── debug_stim_gpr.sv │ │ │ └── debug_stim_memory.sv │ │ ├── exception │ │ │ └── ct_expt_smoke.s │ │ ├── hello_world │ │ │ └── hello_world.c │ │ ├── interrupt │ │ │ ├── int_hw_smoke │ │ │ │ ├── ct_plic_int_smoke_hw.s │ │ │ │ └── ct_plic_int_smoke_hw.sv │ │ │ └── int_smoke │ │ │ │ ├── ct_plic_int_smoke.s │ │ │ │ └── ct_plic_int_smoke_hw.sv │ │ ├── sleep │ │ │ ├── sleep_test.c │ │ │ └── sleep_test.vh │ │ └── smoke │ │ │ └── bus_smoke │ │ │ └── ct_bus_smoke.s │ ├── lib │ │ ├── Makefile │ │ ├── clib │ │ │ ├── config.h │ │ │ ├── datatype.h │ │ │ ├── fputc.c │ │ │ ├── intc.c │ │ │ ├── timer.h │ │ │ ├── uart.c │ │ │ ├── uart.h │ │ │ ├── vtimer.c │ │ │ └── vtimer.h │ │ ├── core_init.h │ │ ├── core_lsu.s │ │ ├── crt0.s │ │ ├── linker.lcf │ │ └── newlib_wrap │ │ │ ├── __thead_printf.c │ │ │ ├── printf.c │ │ │ └── vasprintf.c │ └── regress │ │ ├── regress_report │ │ ├── regress_result │ │ ├── ISA_AMO.report │ │ ├── ISA_BARRIER.report │ │ ├── ISA_IMAC.report │ │ ├── ISA_THEAD.report │ │ ├── MMU.report │ │ ├── cache_op.report │ │ ├── coremark.report │ │ ├── csr.report │ │ ├── hello_world.report │ │ ├── sleep.report │ │ └── smoke_bus.report │ │ └── report_gen.pl └── work │ ├── .gitignore │ └── workdir └── spec_doc ├── profiles.pdf ├── riscv-iommu.pdf ├── riscv-privileged-20211203.pdf ├── riscv-spec-20191213.pdf └── riscv-trace-spec.pdf /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Advanced-Microelectronics-Group/OpenC910_Modified/4fdaaec88852c040fd01809ab2ca0e5f12e4e15f/.gitignore -------------------------------------------------------------------------------- /C910_RTL_FACTORY/gen_rtl/ciu/rtl/ct_prio.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module ct_prio( 17 | clk, 18 | rst_b, 19 | valid, 20 | clr, 21 | sel 22 | ); 23 | parameter NUM =2; 24 | 25 | input clk; 26 | input rst_b; 27 | input [NUM-1:0] valid; 28 | input clr; 29 | output [NUM-1:0] sel; 30 | 31 | reg [NUM-1:0] prio [NUM-1:0]; 32 | reg [NUM-1:0] unused [NUM-1:0]; 33 | wire [NUM-1:0] sel; 34 | wire [NUM-1:0] clr_bus; 35 | 36 | assign clr_bus[NUM-1:0] = {NUM{clr}} & sel[NUM-1:0]; 37 | 38 | genvar i; 39 | generate 40 | for(i=0; i", $fl_wr_path) 23 | or die " Failed to touch $fl_wr_path ... Terminated ..."; 24 | 25 | my @a_memlist; 26 | my %h_memlist; 27 | while(my $line = ) { 28 | $line =~ s/.*, (.*)$/$1/g; 29 | chomp($line); 30 | $h_memlist{$line}++; 31 | } 32 | 33 | @a_memlist = keys %h_memlist; 34 | 35 | foreach my $elem (@a_memlist) { 36 | print "$elem\n"; 37 | # print "$elem : $h_memlist{$elem}\n"; 38 | print FL_WR "$elem\n"; 39 | } 40 | 41 | -------------------------------------------------------------------------------- /smart_run/lint/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Advanced-Microelectronics-Group/OpenC910_Modified/4fdaaec88852c040fd01809ab2ca0e5f12e4e15f/smart_run/lint/Makefile -------------------------------------------------------------------------------- /smart_run/logical/axi/axi_fifo_entry.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | module axi_fifo_entry( 35 | create_en, 36 | data_in, 37 | data_out, 38 | entry_clk, 39 | entry_rst_b 40 | ); 41 | 42 | 43 | input create_en; 44 | input [70:0] data_in; 45 | input entry_clk; 46 | input entry_rst_b; 47 | output [70:0] data_out; 48 | 49 | 50 | reg [70:0] data_out; 51 | 52 | 53 | wire create_en; 54 | wire [70:0] data_in; 55 | wire entry_clk; 56 | wire entry_rst_b; 57 | 58 | 59 | always @(posedge entry_clk or negedge entry_rst_b) 60 | begin 61 | if (!entry_rst_b) 62 | data_out[70:0] <= 71'b0; 63 | else if (create_en) 64 | data_out[70:0] <= data_in[70:0]; 65 | else 66 | data_out[70:0] <= data_out[70:0]; 67 | end 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | endmodule 76 | 77 | 78 | -------------------------------------------------------------------------------- /smart_run/logical/common/BUFGCE.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module BUFGCE( 16 | I, 17 | CE, 18 | O 19 | ); 20 | 21 | input I; 22 | input CE; 23 | output O; 24 | 25 | wire clk_in; 26 | wire external_en; 27 | 28 | assign clk_in = I; 29 | assign external_en = CE; 30 | 31 | reg clk_en_af_latch; 32 | always @(clk_in or external_en) 33 | begin 34 | if(!clk_in) 35 | clk_en_af_latch <= external_en; 36 | end 37 | 38 | reg clk_en ; 39 | always @ (clk_en_af_latch ) 40 | begin 41 | clk_en <= clk_en_af_latch; 42 | end 43 | assign O = clk_in && clk_en ; 44 | 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /smart_run/logical/common/err_gen.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | module err_gen( 38 | hburst_s3, 39 | hmastlock, 40 | hprot_s3, 41 | hrdata_s3, 42 | hready_s3, 43 | hresp_s3, 44 | hsel_s3, 45 | hsize_s3, 46 | htrans_s3, 47 | hwdata_s3, 48 | hwrite_s3, 49 | pad_cpu_rst_b, 50 | pll_core_cpuclk 51 | ); 52 | 53 | 54 | input [2 :0] hburst_s3; 55 | input hmastlock; 56 | input [3 :0] hprot_s3; 57 | input hsel_s3; 58 | input [2 :0] hsize_s3; 59 | input [1 :0] htrans_s3; 60 | input [127:0] hwdata_s3; 61 | input hwrite_s3; 62 | input pad_cpu_rst_b; 63 | input pll_core_cpuclk; 64 | output [127:0] hrdata_s3; 65 | output hready_s3; 66 | output [1 :0] hresp_s3; 67 | 68 | 69 | reg hready_s3; 70 | 71 | 72 | wire [127:0] hrdata_s3; 73 | wire [1 :0] hresp_s3; 74 | wire hsel_s3; 75 | wire pad_cpu_rst_b; 76 | wire pll_core_cpuclk; 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | assign hresp_s3[1:0] = 2'b01 ; 98 | 99 | always @(posedge pll_core_cpuclk or negedge pad_cpu_rst_b) 100 | begin 101 | if(!pad_cpu_rst_b) 102 | begin 103 | hready_s3 <= 1'b0; 104 | end 105 | else if(hsel_s3) 106 | begin 107 | hready_s3 <= 1'b0; 108 | end 109 | else 110 | begin 111 | hready_s3 <= 1'b1; 112 | end 113 | end 114 | 115 | 116 | 117 | 118 | 119 | 120 | assign hrdata_s3[127:0] = 128'b0; 121 | 122 | endmodule 123 | 124 | 125 | -------------------------------------------------------------------------------- /smart_run/logical/common/fifo_counter.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | module fifo_counter( 35 | counter_done, 36 | counter_en, 37 | counter_load, 38 | cpu_clk, 39 | cpu_rst_b 40 | ); 41 | 42 | 43 | input counter_en; 44 | input [31:0] counter_load; 45 | input cpu_clk; 46 | input cpu_rst_b; 47 | output counter_done; 48 | 49 | 50 | reg [31:0] counter; 51 | reg counter_en_ff; 52 | 53 | 54 | wire counter_done; 55 | wire counter_en; 56 | wire [31:0] counter_load; 57 | wire cpu_clk; 58 | wire cpu_rst_b; 59 | wire load_cnt_en; 60 | 61 | 62 | always @(posedge cpu_clk or negedge cpu_rst_b) 63 | begin 64 | if(!cpu_rst_b) 65 | begin 66 | counter_en_ff <= 1'b0; 67 | end 68 | else 69 | begin 70 | counter_en_ff <=counter_en ; 71 | end 72 | end 73 | 74 | assign load_cnt_en= (counter_en && !counter_en_ff); 75 | 76 | 77 | always @(posedge cpu_clk or negedge cpu_rst_b) 78 | begin 79 | if(!cpu_rst_b) 80 | begin 81 | counter[31:0] <= 32'h0; 82 | end 83 | else if (load_cnt_en) 84 | begin 85 | counter[31:0] <= counter_load[31:0]; 86 | end 87 | else if (counter_done) 88 | counter[31:0] <= 32'b0; 89 | else 90 | counter[31:0] <= counter[31:0] -1'b1; 91 | end 92 | 93 | assign counter_done = (counter[31:0] == 32'b0) ; 94 | 95 | 96 | endmodule 97 | 98 | 99 | -------------------------------------------------------------------------------- /smart_run/logical/common/fpga_clk_gen.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module fpga_clk_gen( 16 | clk_en, 17 | clkrst_b, 18 | i_pad_clk, 19 | pad_biu_clkratio, 20 | penable, 21 | per_clk, 22 | prdata, 23 | psel, 24 | pwdata, 25 | pwrite 26 | ); 27 | 28 | 29 | input clkrst_b; 30 | input i_pad_clk; 31 | input penable; 32 | input psel; 33 | input [2 :0] pwdata; 34 | input pwrite; 35 | output clk_en; 36 | output [2 :0] pad_biu_clkratio; 37 | output per_clk; 38 | output [31:0] prdata; 39 | 40 | 41 | reg [2 :0] input_clkratio; 42 | reg [31:0] prdata; 43 | 44 | 45 | wire clk_en; 46 | wire clkrst_b; 47 | wire i_pad_clk; 48 | wire [2 :0] pad_biu_clkratio; 49 | wire penable; 50 | wire per_clk; 51 | wire psel; 52 | wire [2 :0] pwdata; 53 | wire pwrite; 54 | 55 | 56 | always@(posedge per_clk or negedge clkrst_b) 57 | begin 58 | if (!clkrst_b) 59 | input_clkratio[2:0] <= 3'b0; 60 | else if(psel && pwrite && penable) 61 | input_clkratio[2:0] <= pwdata[2:0]; 62 | end 63 | 64 | 65 | always @( input_clkratio[2:0] 66 | or psel 67 | or pwrite) 68 | begin 69 | if(psel && !pwrite) 70 | begin 71 | prdata[31:0] <= {29'b0,input_clkratio[2:0]}; 72 | end 73 | 74 | end 75 | 76 | assign per_clk = i_pad_clk; 77 | 78 | assign clk_en = 1'b1; 79 | assign pad_biu_clkratio[2:0] = input_clkratio[2:0]; 80 | 81 | 82 | 83 | 84 | 85 | endmodule 86 | 87 | 88 | -------------------------------------------------------------------------------- /smart_run/logical/common/wid_entry.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module wid_entry( 17 | biu_pad_awid, 18 | pad_cpu_rst_b, 19 | per_clk, 20 | wid, 21 | wid_entry_push 22 | ); 23 | 24 | 25 | input [7:0] biu_pad_awid; 26 | input pad_cpu_rst_b; 27 | input per_clk; 28 | input wid_entry_push; 29 | output [7:0] wid; 30 | 31 | 32 | reg [7:0] wid_f; 33 | 34 | 35 | wire [7:0] biu_pad_awid; 36 | wire pad_cpu_rst_b; 37 | wire per_clk; 38 | wire [7:0] wid; 39 | wire wid_entry_push; 40 | 41 | 42 | always@(posedge per_clk or negedge pad_cpu_rst_b) 43 | begin 44 | if (!pad_cpu_rst_b) 45 | wid_f[7:0] <= 8'b0; 46 | else if (wid_entry_push) 47 | wid_f[7:0] <= biu_pad_awid[7:0]; 48 | end 49 | 50 | assign wid[7:0] = wid_entry_push ? biu_pad_awid[7:0] : wid_f[7:0]; 51 | 52 | 53 | endmodule 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/ip.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | -f ${CODE_BASE_PATH}/gen_rtl/filelists/C910_asic_rtl.fl 16 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/sim.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | -f ../logical/filelists/ip.fl 16 | -f ../logical/filelists/smart.fl 17 | -f ../logical/filelists/tb.fl 18 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/sim_verilator.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | -f ../logical/filelists/ip.fl 16 | -f ../logical/filelists/smart.fl 17 | -f ../logical/filelists/tb_verilator.fl 18 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/smart.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | +libext+.v+.h+.V+.sv+ 16 | 17 | -y ../logical/ahb 18 | -y ../logical/apb 19 | -y ../logical/axi 20 | # -y ../logical/bus 21 | # -y ../logical/clk 22 | -y ../logical/common 23 | -y ../logical/gpio 24 | -y ../logical/mem 25 | -y ../logical/uart 26 | -y ../logical/pmu 27 | 28 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/tb.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | +libext+.v+.h+.V+.sv+ 16 | 17 | +incdir+../logical/tb+ 18 | 19 | -y ../logical/tb 20 | ../logical/tb/tb.sv 21 | 22 | -------------------------------------------------------------------------------- /smart_run/logical/filelists/tb_verilator.fl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | +libext+.v+.h+.V+.sv+ 16 | 17 | +incdir+../logical/tb+ 18 | 19 | -y ../logical/tb 20 | ../logical/tb/tb_verilator.sv 21 | ../logical/tb/sim_main1.cpp 22 | 23 | -------------------------------------------------------------------------------- /smart_run/logical/mem/ram.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module ram( 16 | PortAClk, 17 | PortAAddr, 18 | PortADataIn, 19 | PortAWriteEnable, 20 | 21 | PortADataOut 22 | ); 23 | 24 | parameter DATAWIDTH = 2; 25 | parameter ADDRWIDTH = 2; 26 | 27 | input PortAClk; 28 | input [(ADDRWIDTH-1):0] PortAAddr; 29 | input [(DATAWIDTH-1):0] PortADataIn; 30 | input PortAWriteEnable; 31 | 32 | output [(DATAWIDTH-1):0] PortADataOut; 33 | 34 | parameter MEMDEPTH = 2**(ADDRWIDTH); 35 | 36 | reg [(DATAWIDTH-1):0] mem [(MEMDEPTH-1):0]; 37 | reg [(DATAWIDTH-1):0] PortADataOut; 38 | 39 | always @(posedge PortAClk) 40 | begin 41 | if(PortAWriteEnable) 42 | begin 43 | mem[PortAAddr] <= PortADataIn; 44 | end 45 | else 46 | begin 47 | PortADataOut <= mem[PortAAddr]; 48 | end 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /smart_run/logical/pmu/px_had_sync.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module px_had_sync( 16 | clk1, 17 | clk2, 18 | rst1_b, 19 | rst2_b, 20 | sync_in, 21 | sync_out 22 | ); 23 | 24 | // &Ports; @22 25 | input clk1; 26 | input clk2; 27 | input rst1_b; 28 | input rst2_b; 29 | input sync_in; 30 | output sync_out; 31 | 32 | // &Regs; @23 33 | reg sync_ff1_clk1; 34 | reg sync_ff2_clk1; 35 | reg sync_ff3_clk1; 36 | reg sync_ff_clk2; 37 | 38 | // &Wires; @24 39 | wire clk1; 40 | wire clk2; 41 | wire rst1_b; 42 | wire rst2_b; 43 | wire sync_in; 44 | wire sync_out; 45 | 46 | 47 | 48 | //============================================================================== 49 | // sync logic from clk2 to clk1 50 | // step 1. flop once in clk2 domain 51 | // step 2. flop twice in clk1 domain 52 | // result: a pulse signal in clk1 domain 53 | // constraint: slow clock --> fast clock 54 | //============================================================================== 55 | 56 | always @(posedge clk2 or negedge rst2_b) 57 | begin 58 | if (!rst2_b) 59 | sync_ff_clk2 <= 1'b0; 60 | else 61 | sync_ff_clk2 <= sync_in; 62 | end 63 | 64 | always @(posedge clk1 or negedge rst1_b) 65 | begin 66 | if (!rst1_b) begin 67 | sync_ff1_clk1 <= 1'b0; 68 | sync_ff2_clk1 <= 1'b0; 69 | end 70 | else begin 71 | sync_ff1_clk1 <= sync_ff_clk2; 72 | sync_ff2_clk1 <= sync_ff1_clk1; 73 | end 74 | end 75 | 76 | // generates a pulse signal in clk1 domain 77 | always @(posedge clk1 or negedge rst1_b) 78 | begin 79 | if (!rst1_b) 80 | sync_ff3_clk1 <= 1'b0; 81 | else 82 | sync_ff3_clk1 <= sync_ff2_clk1; 83 | end 84 | 85 | assign sync_out = !sync_ff3_clk1 && sync_ff2_clk1; 86 | 87 | // &ModuleEnd; @66 88 | endmodule 89 | 90 | 91 | 92 | -------------------------------------------------------------------------------- /smart_run/logical/pmu/sync.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | // * Non-Disclosure Agreement (NDA). * 17 | // * * 18 | // ***************************************************************************** 19 | // FILE NAME : sync.vp 20 | // AUTHOR : Tao Jiang 21 | // ORIGINAL TIME : 2017.06.02 22 | // FUNCTION : sync signal 23 | // : 24 | // : 25 | // : 26 | // RESET : Async reset 27 | // DFT : 28 | // DFP : 29 | // VERIFICATION : 30 | // RELEASE HISTORY : 31 | // ***************************************************************************** 32 | 33 | 34 | // &ModuleBeg; @20 35 | module sync( 36 | fast_clk, 37 | in, 38 | out, 39 | pad_cpu_rst_b, 40 | slow_clk 41 | ); 42 | 43 | // &Ports; @21 44 | input fast_clk; 45 | input in; 46 | input pad_cpu_rst_b; 47 | input slow_clk; 48 | output out; 49 | 50 | // &Regs; @22 51 | reg input_lv; 52 | reg reg_clr; 53 | 54 | // &Wires; @23 55 | wire fast_clk; 56 | wire in; 57 | wire input_vld; 58 | wire out; 59 | wire pad_cpu_rst_b; 60 | wire slow_clk; 61 | 62 | 63 | 64 | 65 | assign input_vld = in ; 66 | 67 | 68 | always@(posedge fast_clk or negedge pad_cpu_rst_b ) 69 | begin 70 | if (!pad_cpu_rst_b) 71 | input_lv <= 1'b0; 72 | else if (input_vld) 73 | input_lv <= 1'b1; 74 | else if (reg_clr) 75 | input_lv <= 1'b0; 76 | end 77 | 78 | always@(posedge slow_clk or negedge pad_cpu_rst_b ) 79 | begin 80 | if (!pad_cpu_rst_b) 81 | reg_clr <= 1'b0; 82 | else 83 | reg_clr <= 1'b1; 84 | end 85 | 86 | 87 | assign out = input_lv; 88 | // &ModuleEnd; @50 89 | endmodule 90 | 91 | 92 | 93 | 94 | 95 | -------------------------------------------------------------------------------- /smart_run/logical/tb/Makefile_obj: -------------------------------------------------------------------------------- 1 | # -*- Makefile -*- 2 | ####################################################################### 3 | # 4 | # DESCRIPTION: Verilator Example: Makefile for inside object directory 5 | # 6 | # This is executed in the object directory, and called by ../Makefile 7 | # 8 | # This file ONLY is placed under the Creative Commons Public Domain, for 9 | # any use, without warranty, 2020 by Wilson Snyder. 10 | # SPDX-License-Identifier: CC0-1.0 11 | # 12 | ####################################################################### 13 | 14 | default: Vtop 15 | 16 | # Include the rules made by Verilator 17 | include Vtop.mk 18 | 19 | # Use OBJCACHE (ccache) if using gmake and its installed 20 | COMPILE.cc = $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c 21 | #CXX = clang 22 | 23 | ####################################################################### 24 | # Compile flags 25 | 26 | # Turn on creating .d make dependency files 27 | CPPFLAGS += -MMD -MP #-fPIE 28 | 29 | # Compile in Verilator runtime debugging, so +verilator+debug works 30 | CPPFLAGS += -DVL_DEBUG=1 31 | 32 | # Turn on some more compiler lint flags (when configured appropriately) 33 | # For testing inside Verilator, "configure --enable-ccwarn" will do this 34 | # automatically; otherwise you may want this unconditionally enabled 35 | ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users 36 | USER_CPPFLAGS_WALL += -W -Werror -Wall 37 | endif 38 | 39 | # See the benchmarking section of bin/verilator. 40 | # Support class optimizations. This includes the tracing and symbol table. 41 | # SystemC takes minutes to optimize, thus it is off by default. 42 | OPT_SLOW = 43 | 44 | # Fast path optimizations. Most time is spent in these classes. 45 | OPT_FAST = -Os -fstrict-aliasing 46 | #OPT_FAST = -O 47 | #OPT_FAST = 48 | 49 | ###################################################################### 50 | ###################################################################### 51 | # Automatically understand dependencies 52 | 53 | DEPS := $(wildcard *.d) 54 | ifneq ($(DEPS),) 55 | include $(DEPS) 56 | endif 57 | -------------------------------------------------------------------------------- /smart_run/logical/tb/int_mnt.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module int_mnt(); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /smart_run/setup/env_check.mk: -------------------------------------------------------------------------------- 1 | #/*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | # 3 | #Licensed under the Apache License, Version 2.0 (the "License"); 4 | #you may not use this file except in compliance with the License. 5 | #You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | #Unless required by applicable law or agreed to in writing, software 10 | #distributed under the License is distributed on an "AS IS" BASIS, 11 | #WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | #See the License for the specific language governing permissions and 13 | #limitations under the License. 14 | #*/ 15 | 16 | tool-chain-chk: 17 | ifndef TOOL_EXTENSION 18 | $(warning \ 19 | $(newline) The environment varialble $$TOOL_EXTENSION must be set to specify the GNU \ 20 | $(newline) toolchains to compile .c/.s smart test cases. \ 21 | $(newline) $$TOOL_EXTENSION must be set as shown in ./setup/example_setup.csh, and the \ 22 | $(newline) suggested steps are: \ 23 | $(newline) 1. vim ./setup/example_setup.csh \ 24 | $(newline) 2. Modify the example_setup.csh with the real toolchain path according \ 25 | $(newline) to your environment. \ 26 | $(newline) 3. source ./setup/example_setup.csh ) 27 | else 28 | @echo " Toolchain path: ${TOOL_EXTENSION}" 29 | endif 30 | 31 | -------------------------------------------------------------------------------- /smart_run/setup/example_setup.csh: -------------------------------------------------------------------------------- 1 | #Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | # 3 | #Licensed under the Apache License, Version 2.0 (the "License"); 4 | #you may not use this file except in compliance with the License. 5 | #You may obtain a copy of the License at 6 | # 7 | # http://www.apache.org/licenses/LICENSE-2.0 8 | # 9 | #Unless required by applicable law or agreed to in writing, software 10 | #distributed under the License is distributed on an "AS IS" BASIS, 11 | #WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | #See the License for the specific language governing permissions and 13 | #limitations under the License. 14 | 15 | 16 | #!/bin/csh 17 | 18 | setenv TOOL_EXTENSION ../../Xuantie-900-gcc-elf-newlib-x86_64-V2.8.1/bin 19 | echo 'Toolchain path($TOOL_EXTENSION):' 20 | echo " $TOOL_EXTENSION" 21 | 22 | 23 | -------------------------------------------------------------------------------- /smart_run/setup/nc.tcl: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | set probe_packed_limit 65536 16 | set probe_unpacked_limit 300000 17 | 18 | run 19 | 20 | -------------------------------------------------------------------------------- /smart_run/spyglass/README: -------------------------------------------------------------------------------- 1 | spyglass -tcl c910_test.tcl 2 | 3 | -------------------------------------------------------------------------------- /smart_run/spyglass/c910_test.sgdc: -------------------------------------------------------------------------------- 1 | current_design cpu_sub_system_axi 2 | sdc_data -file ../impl/sdc/openC910.sdc 3 | 4 | -------------------------------------------------------------------------------- /smart_run/spyglass/c910_test.tcl: -------------------------------------------------------------------------------- 1 | 2 | set_option top cpu_sub_system_axi 3 | set_option sdc2sgdc yes 4 | set_option enableSV yes 5 | set_option language_mode mixed 6 | read_file -type sourcelist ../logical/filelists/ip.fl 7 | read_file -type sourcelist ../logical/filelists/smart.fl 8 | read_file -type sourcelist ../logical/filelists/tb.fl 9 | read_file -type sgdc ./c910_test.sgdc 10 | current_goal Design_Read -top cpu_sub_system_axi 11 | link_design -force 12 | set_option designread_enable_synthesis yes 13 | compile_design -force 14 | 15 | 16 | -------------------------------------------------------------------------------- /smart_run/tests/bin/Srec2vmem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Advanced-Microelectronics-Group/OpenC910_Modified/4fdaaec88852c040fd01809ab2ca0e5f12e4e15f/smart_run/tests/bin/Srec2vmem -------------------------------------------------------------------------------- /smart_run/tests/cases/coremark/cvt.c: -------------------------------------------------------------------------------- 1 | #include 2 | #define CVTBUFSIZE 80 3 | static char CVTBUF[CVTBUFSIZE]; 4 | 5 | static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag) 6 | { 7 | int r2; 8 | double fi, fj; 9 | char *p, *p1; 10 | 11 | if (ndigits < 0) ndigits = 0; 12 | if (ndigits >= CVTBUFSIZE - 1) ndigits = CVTBUFSIZE - 2; 13 | r2 = 0; 14 | *sign = 0; 15 | p = &buf[0]; 16 | if (arg < 0) 17 | { 18 | *sign = 1; 19 | arg = -arg; 20 | } 21 | arg = modf(arg, &fi); 22 | p1 = &buf[CVTBUFSIZE]; 23 | 24 | if (fi != 0) 25 | { 26 | p1 = &buf[CVTBUFSIZE]; 27 | while (fi != 0) 28 | { 29 | fj = modf(fi / 10, &fi); 30 | *--p1 = (int)((fj + .03) * 10) + '0'; 31 | r2++; 32 | } 33 | while (p1 < &buf[CVTBUFSIZE]) *p++ = *p1++; 34 | } 35 | else if (arg > 0) 36 | { 37 | while ((fj = arg * 10) < 1) 38 | { 39 | arg = fj; 40 | r2--; 41 | } 42 | } 43 | p1 = &buf[ndigits]; 44 | if (eflag == 0) p1 += r2; 45 | *decpt = r2; 46 | if (p1 < &buf[0]) 47 | { 48 | buf[0] = '\0'; 49 | return buf; 50 | } 51 | while (p <= p1 && p < &buf[CVTBUFSIZE]) 52 | { 53 | arg *= 10; 54 | arg = modf(arg, &fj); 55 | *p++ = (int) fj + '0'; 56 | } 57 | if (p1 >= &buf[CVTBUFSIZE]) 58 | { 59 | buf[CVTBUFSIZE - 1] = '\0'; 60 | return buf; 61 | } 62 | p = p1; 63 | *p1 += 5; 64 | while (*p1 > '9') 65 | { 66 | *p1 = '0'; 67 | if (p1 > buf) 68 | ++*--p1; 69 | else 70 | { 71 | *p1 = '1'; 72 | (*decpt)++; 73 | if (eflag == 0) 74 | { 75 | if (p > buf) *p = '0'; 76 | p++; 77 | } 78 | } 79 | } 80 | *p = '\0'; 81 | return buf; 82 | } 83 | 84 | char *ecvt(double arg, int ndigits, int *decpt, int *sign) 85 | { 86 | return cvt(arg, ndigits, decpt, sign, CVTBUF, 1); 87 | } 88 | 89 | char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf) 90 | { 91 | return cvt(arg, ndigits, decpt, sign, buf, 1); 92 | } 93 | 94 | char *fcvt(double arg, int ndigits, int *decpt, int *sign) 95 | { 96 | return cvt(arg, ndigits, decpt, sign, CVTBUF, 0); 97 | } 98 | 99 | char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf) 100 | { 101 | return cvt(arg, ndigits, decpt, sign, buf, 0); 102 | } 103 | -------------------------------------------------------------------------------- /smart_run/tests/cases/csr/ct_csr_operate.s: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #************************************************************ 16 | #* Target file generated by rangen * 17 | #************************************************************ 18 | #* * 19 | #************************************************************ 20 | 21 | #*************Following is the generated instructions***************** 22 | 23 | .text 24 | .align 6 25 | .global main 26 | main: 27 | 28 | .option norvc 29 | .global reg_access 30 | reg_access: 31 | li x1,0xffffffff 32 | #read to x10 & write x1 to csr 33 | csrrw x10,mstatus,x1 34 | #read to x10 & set x1 bit to csr 35 | csrrs x10,mstatus,x1 36 | #read to x10 & clr x1 bit to csr 37 | csrrc x10,mstatus,x1 38 | #read to x10 39 | csrr x10,mstatus 40 | # write x1 to csr 41 | csrw mstatus,x1 42 | #set x1 bit to csr 43 | csrs mstatus,x1 44 | #clr x1 bit to csr 45 | csrc mstatus,x1 46 | .global imm_access 47 | imm_access: 48 | #read to x10 & write imm to csr 49 | csrrwi x10,mstatus,0x3 50 | #read to x10 & set imm bit to csr 51 | csrrsi x10,mstatus,0x3 52 | #read to x10 & clr imm bit to csr 53 | csrrci x10,mstatus,0x3 54 | #write imm bit to csr 55 | csrs mstatus,0x1 56 | #set imm bit to csr 57 | csrs mstatus,0x1 58 | #clr imm bit to csr 59 | csrc mstatus,0x1 60 | .global TEST_EXIT 61 | TEST_EXIT: 62 | la x1,__exit 63 | jr x1 64 | .global TEST_FAIL 65 | TEST_FAIL: 66 | la x1,__fail 67 | jr x1 68 | .global TEST_WFI 69 | TEST_WFI: 70 | wfi 71 | .option rvc 72 | #******this region is added by generator****** 73 | 74 | -------------------------------------------------------------------------------- /smart_run/tests/cases/debug/debug_gpr/debug_read_write_gpr.s: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | .global main 17 | 18 | main: 19 | 20 | # #read to x10 & set imm bit to csr 21 | # csrrsi x10,mstatus,0x8 22 | # # csrrsi mstatus, 0x8 23 | # csrci mhcr, 0x1 24 | # csrci mhcr, 0x2 25 | 26 | .global LOOP 27 | LOOP: 28 | c.j LOOP 29 | 30 | 31 | -------------------------------------------------------------------------------- /smart_run/tests/cases/debug/debug_memory/debug_read_write_memory.s: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | .global main 17 | 18 | main: 19 | 20 | # #read to x10 & set imm bit to csr 21 | # csrrsi x10,mstatus,0x8 22 | # # csrrsi mstatus, 0x8 23 | # csrci mhcr, 0x1 24 | # csrci mhcr, 0x2 25 | 26 | .global LOOP 27 | LOOP: 28 | c.j LOOP 29 | 30 | 31 | -------------------------------------------------------------------------------- /smart_run/tests/cases/debug/debug_stim.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | module debug_stim(); 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /smart_run/tests/cases/hello_world/hello_world.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #include "stdio.h" 16 | 17 | int main (void) 18 | { 19 | 20 | //Section 1: Hello World! 21 | printf("\nHello Friend!\n"); 22 | printf("Welcome to T-HEAD World!\n"); 23 | 24 | //Section 2: Embeded ASM in C 25 | int a; 26 | int b; 27 | int c; 28 | a=1; 29 | b=2; 30 | c=0; 31 | printf("\na is %d!\n",a); 32 | printf("b is %d!\n",b); 33 | printf("c is %d!\n",c); 34 | 35 | asm( 36 | "mv x5,%[a]\n" 37 | "mv x6,%[b]\n" 38 | "label_add:" 39 | "add %[c],x5,x6\n" 40 | :[c]"=r"(c) 41 | :[a]"r"(a),[b]"r"(b) 42 | :"x5","x6" 43 | ); 44 | 45 | if(c == 3) 46 | printf("!!! PASS !!!"); 47 | else 48 | printf("!!! FAIL !!!"); 49 | printf("after ASM c is changed to %d!\n",c); 50 | 51 | return 0; 52 | } 53 | 54 | -------------------------------------------------------------------------------- /smart_run/tests/cases/interrupt/int_hw_smoke/ct_plic_int_smoke_hw.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module int_mnt(); 17 | `define CPU_TOP tb.x_soc.x_cpu_sub_system_axi.x_rv_integration_platform.x_cpu_top 18 | `define INTINCFG `CPU_TOP.pad_plic_int_cfg[63:0] 19 | `define INTINVLD `CPU_TOP.pad_plic_int_vld[63:0] 20 | `define FLUSH `CPU_TOP.core0_pad_flush 21 | `define core0_retire0_pc `CPU_TOP.core0_pad_retire0_pc[39:0] 22 | 23 | initial 24 | begin 25 | //cfg 1 pulse cfg 0 level 26 | force `INTINCFG = 64'h0; 27 | //iid 16 28 | force `INTINVLD = 64'h1; 29 | 30 | wait (`core0_retire0_pc == 40'he0) 31 | release `INTINVLD; 32 | release `INTINCFG; 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /smart_run/tests/cases/interrupt/int_smoke/ct_plic_int_smoke_hw.sv: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | module int_mnt(); 17 | `define CPU_TOP tb.x_soc.x_cpu_sub_system_axi.x_rv_integration_platform.x_cpu_top 18 | `define INTINCFG `CPU_TOP.pad_plic_int_cfg[63:0] 19 | `define INTINVLD `CPU_TOP.pad_plic_int_vld[63:0] 20 | `define FLUSH `CPU_TOP.core0_pad_flush 21 | `define core0_retire0_pc `CPU_TOP.core0_pad_retire0_pc[39:0] 22 | `define core0_lpmd_b `CPU_TOP.core0_pad_lpmd_b 23 | 24 | initial 25 | begin 26 | 27 | #5000ns; 28 | wait(`core0_lpmd_b != 3'b11) 29 | #5000ns; 30 | 31 | //cfg 1 pulse cfg 0 level 32 | force `INTINCFG = 64'h1; 33 | //iid 16 34 | force `INTINVLD = 64'h1; 35 | 36 | #500ns; 37 | 38 | // wait (`core0_retire0_pc == 40'he0) 39 | release `INTINVLD; 40 | release `INTINCFG; 41 | 42 | #5000ns; 43 | 44 | end 45 | endmodule 46 | 47 | -------------------------------------------------------------------------------- /smart_run/tests/cases/sleep/sleep_test.vh: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | `define PMU_LP_MODE_TEST 17 | 18 | -------------------------------------------------------------------------------- /smart_run/tests/lib/clib/datatype.h: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #ifndef __DATATYPE_H__ 16 | #define __DATATYPE_H__ 17 | 18 | typedef unsigned char uint8_t; 19 | typedef unsigned short uint16_t; 20 | typedef unsigned int uint32_t; 21 | typedef unsigned long uint64_t; 22 | //typedef unsigned int uintptr_t; 23 | typedef signed char int8_t; 24 | typedef signed short int16_t; 25 | typedef signed int int32_t; 26 | typedef signed long int64_t; 27 | //typedef unsigned int size_t; 28 | typedef volatile unsigned char reg8_t; 29 | typedef volatile unsigned short reg16_t; 30 | typedef volatile unsigned int reg32_t; 31 | 32 | #ifndef SUCCESS 33 | #define SUCCESS 0 34 | #endif 35 | 36 | #endif 37 | 38 | -------------------------------------------------------------------------------- /smart_run/tests/lib/clib/fputc.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #include 16 | 17 | #define C9xx_LOG_PRINT_ADDR ((int *)0x01fffff0) 18 | 19 | int fputc(int ch, FILE *stream) 20 | { 21 | volatile int* addr_ptr; 22 | addr_ptr = C9xx_LOG_PRINT_ADDR; 23 | *(addr_ptr) = ch; 24 | 25 | // asm volatile ( 26 | // "li x13, 0x01fffff0 \n\t" 27 | // "sw %0, 0(x13) \n\t" 28 | // : :"r" (ch): "x13", "memory"); 29 | } 30 | 31 | void os_critical_enter(void) 32 | { 33 | } 34 | 35 | void os_critical_exit(void) 36 | { 37 | } 38 | 39 | -------------------------------------------------------------------------------- /smart_run/tests/lib/clib/intc.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #include "datatype.h" 16 | #include "uart.h" 17 | #include "stdio.h" 18 | 19 | #define APB_BASE 0x10000000 20 | #define INTC_BASE 0x10010000 21 | 22 | //config the interrupt controller 23 | void ck_intc_init() 24 | { 25 | int *picr = APB_BASE; 26 | *picr = 0x0; 27 | 28 | // Write NIER 29 | int *piser = INTC_BASE + 0x10; 30 | *piser = 0x3f; 31 | } 32 | -------------------------------------------------------------------------------- /smart_run/tests/lib/clib/vtimer.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | 16 | int get_vtimer() 17 | { 18 | volatile unsigned int LoadCount; 19 | asm ("csrr %[LoadCount], time\n" 20 | :[LoadCount]"=r"(LoadCount) 21 | : 22 | : 23 | ); 24 | //LoadCount = *TIMER_ADDR; 25 | return LoadCount; 26 | } 27 | 28 | void sim_end() 29 | { 30 | int *END_ADDR; 31 | END_ADDR = 0xA001FF48; 32 | unsigned int END_DATA; 33 | // END_DATA= 0xFFF; 34 | END_DATA= 0x444333222; 35 | *END_ADDR = END_DATA; 36 | } 37 | -------------------------------------------------------------------------------- /smart_run/tests/lib/clib/vtimer.h: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | /* 16 | * timer.h -- The interface functions and Mcros for SMART 17 | * 18 | */ 19 | 20 | int get_vtimer(); 21 | 22 | void sim_end(); 23 | -------------------------------------------------------------------------------- /smart_run/tests/lib/linker.lcf: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | MEMORY 16 | { 17 | MEM1(RWX) : ORIGIN = 0x00000000, LENGTH = 0x40000 18 | MEM2(RWX) : ORIGIN = 0x00040000, LENGTH = 0xc0000 19 | } 20 | __kernel_stack = 0xee000 ; 21 | 22 | ENTRY(__start) 23 | 24 | SECTIONS { 25 | .text : 26 | { 27 | crt0.o (.text) 28 | *(.text*) 29 | } >MEM1 30 | 31 | .rodata : { *( .rodata* ) 32 | *(.srodata) 33 | *(.srodata.*) 34 | *(.srodata.cst4*) 35 | *(.srodata.cst8*) 36 | } >MEM1 37 | 38 | .data : 39 | { 40 | *(.data*) 41 | *(.sdata*) 42 | } >MEM2 43 | .bss : 44 | { 45 | *(.bss) *.(COMMON) *(.sbss) 46 | } >MEM2 47 | end = .; 48 | } 49 | -------------------------------------------------------------------------------- /smart_run/tests/lib/newlib_wrap/__thead_printf.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #include 16 | #include 17 | 18 | int __thead_vprintfsprintf(char *str, FILE *stream, const char *format, va_list arg_ptr) 19 | { 20 | return 0; 21 | } 22 | 23 | int __thead_vprintfprintf(FILE *stream, const char *format, va_list arg_ptr) 24 | { 25 | return 0; 26 | } 27 | 28 | #undef stdout 29 | int stdout() 30 | { 31 | return 0; 32 | } 33 | -------------------------------------------------------------------------------- /smart_run/tests/lib/newlib_wrap/vasprintf.c: -------------------------------------------------------------------------------- 1 | /*Copyright 2019-2021 T-Head Semiconductor Co., Ltd. 2 | 3 | Licensed under the Apache License, Version 2.0 (the "License"); 4 | you may not use this file except in compliance with the License. 5 | You may obtain a copy of the License at 6 | 7 | http://www.apache.org/licenses/LICENSE-2.0 8 | 9 | Unless required by applicable law or agreed to in writing, software 10 | distributed under the License is distributed on an "AS IS" BASIS, 11 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 | See the License for the specific language governing permissions and 13 | limitations under the License. 14 | */ 15 | #include 16 | #include 17 | #include 18 | #include 19 | #include 20 | 21 | 22 | #define CHUNKSIZE (256) 23 | 24 | int vasprintf(char **ret, const char *fmt, va_list ap) 25 | { 26 | size_t chunks; 27 | size_t buflen; 28 | char * buf; 29 | int len; 30 | 31 | chunks = ((strlen(fmt) + 1) / CHUNKSIZE) + 1; 32 | buflen = chunks * CHUNKSIZE; 33 | 34 | *ret = NULL; 35 | for (;;) { 36 | buf = malloc(buflen); 37 | if (buf == NULL) { 38 | return -ENOMEM; 39 | } 40 | len = vsnprintf(buf, buflen, fmt, ap); 41 | 42 | if (len >= 0 && (size_t)len < buflen - 1) { 43 | break; 44 | } 45 | free(buf); 46 | buflen = (++chunks) * CHUNKSIZE; 47 | 48 | /* 49 | * len >= 0 is required for vsnprintf implementations that 50 | * return -1 for insufficient buffer 51 | */ 52 | 53 | if (len >= 0 && buflen <= (size_t)len) { 54 | buflen = len + 1; 55 | } 56 | } 57 | 58 | if (len > 0 && buf != NULL) { 59 | // strip the string 60 | *ret = strdup(buf); 61 | if (*ret != NULL) 62 | free(buf); 63 | else 64 | *ret = buf; 65 | } 66 | 67 | return len; 68 | } 69 | 70 | int asprintf(char **buf, const char *fmt, ...) 71 | { 72 | va_list args; 73 | int i; 74 | 75 | va_start(args, fmt); 76 | i = vasprintf(buf, fmt, args); 77 | va_end(args); 78 | return i; 79 | } 80 | -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_report: -------------------------------------------------------------------------------- 1 | 2 | Block Pattern Result 3 | --------------------------------------------- 4 | 0 ISA_AMO PASS 5 | 1 smoke_bus PASS 6 | 2 ISA_THEAD PASS 7 | 3 cache_op PASS 8 | 4 ISA_IMAC =>FAIL 9 | 5 coremark PASS 10 | 6 hello_world PASS 11 | 7 MMU PASS 12 | 8 csr PASS 13 | 9 ISA_BARRIER PASS 14 | 10 sleep PASS 15 | --------------------------------------------- 16 | Not run Pass Fail Total 17 | 0 10 1 11 18 | -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/ISA_AMO.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/ISA_BARRIER.report: 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-------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/coremark.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/csr.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/hello_world.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/sleep.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/tests/regress/regress_result/smoke_bus.report: -------------------------------------------------------------------------------- 1 | TEST PASS -------------------------------------------------------------------------------- /smart_run/work/.gitignore: -------------------------------------------------------------------------------- 1 | * 2 | !.gitignore 3 | -------------------------------------------------------------------------------- /smart_run/work/workdir: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Advanced-Microelectronics-Group/OpenC910_Modified/4fdaaec88852c040fd01809ab2ca0e5f12e4e15f/smart_run/work/workdir -------------------------------------------------------------------------------- /spec_doc/profiles.pdf: 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