├── Day_30 └── Factorial.md ├── Day3 ├── Binary_to_gray.md └── Gray_to_binary.md ├── Day1 ├── Half_Adder.md └── Full Adder.md ├── Day_14 └── Mod_N_Counter.md ├── Day_15 └── gray counter.md ├── Day_27 └── Frequency Divider by Even Numbers.md ├── Day_23 └── PWM (Pulse Width Modulation) generator.md ├── Day_16 └── Booth multiplication.md ├── Day_28 └── Traffic Light Controller.md ├── Day_10 └── Comparator.md ├── Day_17 └── 1-Bit RAM Cell.md ├── Day_26 └── Pseudorandom number generator.md ├── Day_21 └── 1101 Moore Sequence Detector.md ├── Day_13 └── Counters.md ├── Day8 └── SR & D Latch.md ├── Day2 └── Ripple_Carry_Adder.md ├── Day6 └── Encoders.md ├── Day_22 └── 1010 Mealy Sequence Detector.md ├── Day_11 └── Shift_Registers_1.md ├── README.md ├── Day_24 └── Fixed Priority Arbiter.md ├── Day_29 └── Elevator Controller.md ├── Day_19 └── ROM.md ├── Day_12 └── Shift_Registers_2.md ├── Day7 └── Decoders.md ├── Day5 └── Demultiplexer.md ├── Day_18 └── 4-BIT & 8-BIT RAM.md ├── Day_20 └── 8-BIT ALU.md ├── Day4 └── Multiplexers.md ├── Day_25 └── Round-Robin Arbiter.md └── Day9 └── FLIP-FLOPS.md /Day_30/Factorial.md: -------------------------------------------------------------------------------- 1 | # Factorial: 2 | 3 | The factorial of a number is the product of all positive integers from 1 to that number, denoted as "n!" (n factorial). 4 | 5 | ```verilog 6 | 7 | module factorial( 8 | input [7:0] num, 9 | output reg [31:0] result 10 | ); 11 | 12 | integer i; 13 | 14 | always @(*) begin 15 | result = 1; 16 | for (i=1; i<=num; i=i+1) 17 | result = result * i; 18 | end 19 | 20 | endmodule 21 | ``` 22 | 23 | # Factorial Test Bench: 24 | 25 | ```verilog 26 | module testbench; 27 | reg [7:0] num; 28 | wire [31:0] result; 29 | 30 | factorial dut(.num(num), .result(result)); 31 | 32 | initial begin 33 | num = 5; #10; 34 | num = 7; #10; 35 | end 36 | 37 | initial begin 38 | $monitor("num = %0d, result = %0d", num, result); 39 | end 40 | 41 | endmodule 42 | ``` 43 | 44 | ## Schematics 45 | ![Alt Text](https://i.ibb.co/FxpZLYf/fact.png) 46 | 47 | ## Simulation 48 | ![Alt Text](https://i.ibb.co/n7Pmb3w/fact-tb.png) 49 | -------------------------------------------------------------------------------- /Day3/Binary_to_gray.md: -------------------------------------------------------------------------------- 1 | # Binary to Gray code conversion: 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module binary_to_gray(bin,gray); 6 | input[3:0]bin; 7 | output[3:0]gray; 8 | assign gray[3]=bin[3]; 9 | assign gray[2]=bin[3]^bin[2]; 10 | assign gray[1]=bin[2]^bin[1]; 11 | assign gray[0]=bin[1]^bin[0]; 12 | endmodule 13 | ``` 14 | # Binary to gray conversion 15 | 16 | ![Alt Text](https://media.geeksforgeeks.org/wp-content/uploads/20220420085103/Screenshot695-300x191.png) 17 | 18 | # Binary to Gray code conversion: Testbench 19 | 20 | ```verilog 21 | `timescale 1ns / 1ps 22 | 23 | module testbench_binary_to_gray; 24 | reg [3:0] bin; 25 | wire [3:0] gray; 26 | integer i; 27 | binary_to_gray dut (.bin(bin),.gray(gray)); 28 | 29 | initial begin 30 | bin = 4'b0000; 31 | $display("Input (Binary) | Output (Gray)"); 32 | for (i = 0; i < 16; i = i + 1) begin 33 | $display("%4b | %4b", bin, gray); 34 | bin = bin + 1; 35 | #10; 36 | end 37 | $finish; 38 | end 39 | 40 | endmodule 41 | ``` 42 | 43 | ## Schematics 44 | ![Alt Text](https://i.ibb.co/g9X3fjc/bin_to_gray.png) 45 | 46 | ## Simulation 47 | ![Alt Text](https://i.ibb.co/hyMRGr6/Bin_to_gray_simu.png) 48 | -------------------------------------------------------------------------------- /Day1/Half_Adder.md: -------------------------------------------------------------------------------- 1 | # Half Adder using Dataflow modeling 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module half_adder_dataflow( input A,B, output Sum,Carry); 6 | 7 | assign Sum = A^B; 8 | assign Carry = A&B; 9 | 10 | endmodule 11 | ``` 12 | 13 | # truthtable 14 | 15 | | Input | | Output | | 16 | |-------|---|---------|-----------| 17 | | A | B | S (Sum) | C (Carry) | 18 | | 0 | 0 | 0 | 0 | 19 | | 0 | 1 | 1 | 0 | 20 | | 1 | 0 | 1 | 0 | 21 | | 1 | 1 | 0 | 1 | 22 | 23 | 24 | # half adder Testbench (dataflow model) 25 | 26 | ```verilog 27 | `timescale 1ns / 1ps 28 | 29 | module half_adder_dataflow_tb; 30 | reg A_tb; 31 | reg B_tb; 32 | 33 | wire Carry_tb; 34 | wire Sum_tb; 35 | half_adder_dataflow dut (.A(A_tb), .B(B_tb), .Sum(Sum_tb), .Carry(Carry_tb)); 36 | 37 | initial begin 38 | A_tb = 1'b0; B_tb = 1'b0; 39 | #10 A_tb = 1'b0; B_tb = 1'b1; 40 | #10 A_tb = 1'b1; B_tb = 1'b0; 41 | #10 A_tb = 1'b1; B_tb = 1'b1; 42 | #10$stop; 43 | 44 | end 45 | 46 | endmodule 47 | 48 | ``` 49 | 50 | ## Schematics 51 | ![Alt Text](https://i.ibb.co/CJ91XVS/Half_Adder.png) 52 | 53 | ## Simulation 54 | ![Alt Text](https://i.ibb.co/tLLPdM8/Half_adder_sim.png) 55 | -------------------------------------------------------------------------------- /Day3/Gray_to_binary.md: -------------------------------------------------------------------------------- 1 | # Gray to binary code conversion: 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module gray_to_binary(gray, bin); 6 | input [3:0] gray; 7 | output reg [3:0] bin; 8 | 9 | always @(gray) begin 10 | bin[3] = gray[3]; 11 | bin[2] = gray[3] ^ gray[2]; 12 | bin[1] = bin[2] ^ gray[1]; 13 | bin[0] = bin[1] ^ gray[0]; 14 | end 15 | endmodule 16 | ``` 17 | # Gray to Binary conversion 18 | 19 | ![Alt Text](https://media.geeksforgeeks.org/wp-content/uploads/20220420085103/Screenshot696-300x206.png) 20 | 21 | # Gray to Binary code conversion: Testbench 22 | 23 | ```verilog 24 | `timescale 1ns / 1ps 25 | 26 | module testbench_gray_to_binary; 27 | 28 | reg [3:0] gray; 29 | wire [3:0] bin; 30 | integer i; 31 | gray_to_binary dut (.gray(gray),.bin(bin)); 32 | initial begin 33 | $display("Input (Gray) | Output (Binary)"); 34 | 35 | for (i = 0; i < 16; i = i + 1) begin 36 | gray = i; 37 | 38 | $display("%4b | %4b", gray, bin); 39 | #10; 40 | end 41 | $finish; 42 | end 43 | 44 | endmodule 45 | ``` 46 | 47 | ## Schematics 48 | ![Alt Text](https://i.ibb.co/KXvyssC/gray_to_bin.png) 49 | 50 | ## Simulation 51 | ![Alt Text](https://i.ibb.co/FqDkBLC/gray_to_bin_simu.png) 52 | -------------------------------------------------------------------------------- /Day_14/Mod_N_Counter.md: -------------------------------------------------------------------------------- 1 | # Mod-N Counter: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module modn_counter #(parameter N = 15, parameter Width = 4)( 7 | input clk, 8 | input rstn, 9 | output reg [Width-1:0] out ); 10 | 11 | always @(posedge clk)begin 12 | 13 | if(!rstn) 14 | begin 15 | out <= 0; 16 | end 17 | else begin 18 | if (out == N-1) 19 | out <= 0; 20 | 21 | else 22 | out <= out + 1; 23 | 24 | end 25 | end 26 | 27 | endmodule 28 | ``` 29 | 30 | # Mod-N Counter Test Bench: 31 | 32 | ```verilog 33 | `timescale 1ns / 1ps 34 | 35 | module testbench; 36 | parameter N = 15; 37 | parameter Width = 4; 38 | 39 | reg clk; 40 | reg rstn; 41 | wire [Width-1:0] out; 42 | 43 | modn_counter dut (.clk(clk), .rstn(rstn), .out(out)); 44 | 45 | always #10 clk = ~clk; 46 | 47 | initial begin 48 | {clk, rstn} <= 0; 49 | 50 | $monitor("T=%0t rstn=%0b out=0x%0h", $time, rstn, out); 51 | repeat(2) @(posedge clk); 52 | rstn <= 1; 53 | repeat (20) @ (posedge clk); 54 | $finish; 55 | end 56 | 57 | endmodule 58 | ``` 59 | 60 | ## Schematics 61 | ![Alt Text](https://i.ibb.co/44X9b5n/Mod-N-Counter.png) 62 | 63 | ## Simulation 64 | ![Alt Text](https://i.ibb.co/hW3R9mw/Mod-N-Counter-TB.png) 65 | -------------------------------------------------------------------------------- /Day_15/gray counter.md: -------------------------------------------------------------------------------- 1 | # Gray Counter: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module gray_counter( 7 | input clk,rst, 8 | output reg [3:0] gray_count 9 | ); 10 | 11 | reg [3:0] bin_count; 12 | 13 | always@(posedge clk) 14 | begin 15 | if(rst) 16 | begin 17 | gray_count=4'b0000; 18 | bin_count=4'b0000; 19 | end 20 | else 21 | begin 22 | bin_count = bin_count + 1; 23 | gray_count = {bin_count[3],bin_count[3]^bin_count[2], 24 | bin_count[2]^bin_count[1],bin_count[1]^bin_count[0]}; 25 | end 26 | end 27 | endmodule 28 | ``` 29 | 30 | # Gray Counter Test Bench: 31 | 32 | ```verilog 33 | `timescale 1ns / 1ps 34 | 35 | module testbench; 36 | 37 | reg clk,reset; 38 | wire [3:0] gray_count; 39 | 40 | gray_counter dut(clk, reset, gray_count); 41 | 42 | initial begin 43 | clk= 1'b0; 44 | forever #5 clk= ~clk; 45 | end 46 | 47 | initial begin 48 | reset= 1'b1; 49 | #10; 50 | reset= 1'b0; 51 | end 52 | 53 | initial begin 54 | $monitor("\t\t counter: %d", gray_count); 55 | #175 $finish; 56 | end 57 | endmodule 58 | ``` 59 | 60 | ## Schematics 61 | ![Alt Text](https://i.ibb.co/JmsBT0c/gray-counter.png) 62 | 63 | ## Simulation 64 | ![Alt Text](https://i.ibb.co/R9Mx6XH/gray-counter-tb.png) 65 | -------------------------------------------------------------------------------- /Day_27/Frequency Divider by Even Numbers.md: -------------------------------------------------------------------------------- 1 | # Frequency Divider by Even Numbers: 2 | 3 | - Even Freq/Clk divider: 4 | - Divide the input clock by an even integer (2, 4, 6, etc) 5 | - Output clock toggles when the counter reaches exactly divisor/2 6 | - Gives 50% duty cycle output clock 7 | 8 | ```verilog 9 | module clk_divider( 10 | input clk_in, 11 | input [7:0] divisor, 12 | output reg clk_out 13 | ); 14 | 15 | reg [7:0] counter = 8'd0; 16 | 17 | always @(posedge clk_in) begin 18 | counter <= counter + 1; 19 | if (counter >= (divisor - 1)) begin 20 | counter <= 0; 21 | end 22 | clk_out <= (counter < (divisor/2))?1'b1:1'b0; 23 | end 24 | 25 | endmodule 26 | ``` 27 | 28 | # Frequency Divider by Even Numbers Test Bench: 29 | 30 | ```verilog 31 | `timescale 1ns / 1ps 32 | 33 | module clk_divider_tb; 34 | 35 | reg clk_in; 36 | reg [7:0] divisor; 37 | wire clk_out; 38 | 39 | clk_divider dut ( .clk_in(clk_in), .divisor(divisor), .clk_out(clk_out) ); 40 | 41 | initial begin 42 | clk_in = 1'b0; 43 | divisor = 8'd4; 44 | #10; 45 | repeat (20) begin 46 | #5 clk_in = ~clk_in; 47 | end 48 | #10 $finish; 49 | end 50 | 51 | always @(posedge clk_out) begin 52 | $display("clk_out = %b", clk_out); 53 | end 54 | 55 | endmodule 56 | ``` 57 | 58 | ## Schematics 59 | ![Alt Text](https://i.ibb.co/59Sz1qV/freq-divide.png) 60 | 61 | ## Simulation 62 | ![Alt Text](https://i.ibb.co/b2KZ7ZF/freq-divide-tb.png) 63 | -------------------------------------------------------------------------------- /Day_23/PWM (Pulse Width Modulation) generator.md: -------------------------------------------------------------------------------- 1 | # PWM (Pulse Width Modulation) generator: 2 | 3 | A PWM (Pulse Width Modulation) generator is a circuit that produces a digital signal with a varying pulse width. It is commonly used in applications such as motor speed control, LED dimming, and audio synthesis. 4 | 5 | The percentage of time in which the PWM signal remains HIGH (on time) is called as duty cycle. If the signal is always ON it is in 100% duty cycle and if it is always off it is 0% duty cycle. 6 | 7 | **`Duty Cycle =Turn ON time/ (Turn ON time + Turn OFF time)`** 8 | 9 | ```verilog 10 | `timescale 1ns / 1ps 11 | 12 | module PWM( 13 | input clk, 14 | output [3:0] out ); 15 | 16 | reg [7:0] count = 0 ; 17 | 18 | always@(posedge clk ) begin 19 | 20 | if (count < 100) count <= count + 1; 21 | else count <=0; 22 | 23 | end 24 | 25 | assign out[0] = (count < 20) ? 1:0; 26 | assign out[1] = (count < 40) ? 1:0; 27 | assign out[2] = (count < 60) ? 1:0; 28 | assign out[3] = (count < 80) ? 1:0; 29 | 30 | endmodule 31 | ``` 32 | 33 | # PWM Generator Test Bench: 34 | 35 | ```verilog 36 | `timescale 1ns / 1ps 37 | 38 | module Testbench; 39 | 40 | reg clk; 41 | wire [3:0] out; 42 | 43 | PWM dut (.clk(clk), .out(out)); 44 | 45 | always begin 46 | clk=1; 47 | forever #5 clk= ~clk; 48 | end 49 | endmodule 50 | ``` 51 | 52 | ## Schematics 53 | ![Alt Text](https://i.ibb.co/PctsFSh/pwm.png) 54 | 55 | ## Simulation 56 | ![Alt Text](https://i.ibb.co/86GT3HQ/pwm-tb.png) 57 | -------------------------------------------------------------------------------- /Day_16/Booth multiplication.md: -------------------------------------------------------------------------------- 1 | # Booth_Multiplier: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module Booth_Multiplier(A, B, PRODUCT); 7 | input signed [3:0] A, B; 8 | output reg signed [7:0] PRODUCT; 9 | 10 | reg [1:0] temp; 11 | integer i; 12 | reg e; 13 | reg [3:0] B1; 14 | 15 | always @(A,B) 16 | begin 17 | PRODUCT = 8'd0; 18 | e = 1'b0; 19 | B1 = -B; 20 | 21 | for (i=0; i<4; i=i+1) 22 | begin 23 | temp = { A[i], e }; 24 | case(temp) 25 | 2'd2 : PRODUCT[7:4] = PRODUCT[7:4] + B1; 26 | 2'd1 : PRODUCT[7:4] = PRODUCT[7:4] + B; 27 | endcase 28 | PRODUCT = PRODUCT >> 1; 29 | PRODUCT[7] = PRODUCT[6]; 30 | e=A[i]; 31 | 32 | end 33 | end 34 | 35 | endmodule 36 | ``` 37 | 38 | # Booth Multiplication Test Bench: 39 | 40 | ```verilog 41 | `timescale 1ns / 1ps 42 | 43 | module testbench; 44 | 45 | reg signed [3:0] A; 46 | reg signed [3:0] B; 47 | 48 | wire signed [7:0] PRODUCT; 49 | 50 | Booth_Multiplier dut ( .A(A), .B(B), .PRODUCT(PRODUCT) ); 51 | 52 | reg clk = 0; 53 | 54 | always begin 55 | #5 clk = ~clk; 56 | end 57 | 58 | initial begin 59 | A = 4'b0110; 60 | B = 4'b0011; 61 | #10; 62 | $display("A = %d, B = %d, PRODUCT = %d", A, B, PRODUCT); 63 | if (PRODUCT === (A * B)) 64 | $display("Test Case 1 PASSED"); 65 | else 66 | $display("Test Case 1 FAILED"); 67 | 68 | $finish; 69 | end 70 | always begin 71 | #5 clk = ~clk; 72 | end 73 | 74 | endmodule 75 | ``` 76 | 77 | ## Schematics 78 | ![Alt Text](https://i.ibb.co/GvNVY0t/booth-mul.png) 79 | 80 | ## Simulation 81 | ![Alt Text](https://i.ibb.co/7gtScHz/booth-mul-tb.png) 82 | -------------------------------------------------------------------------------- /Day_28/Traffic Light Controller.md: -------------------------------------------------------------------------------- 1 | # Traffic Light Controller: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module traffic_light_controller( 7 | input clk, reset, 8 | output reg red, yellow, green ); 9 | 10 | localparam RED = 3'b001; 11 | localparam YELLOW = 3'b010; 12 | localparam GREEN = 3'b100; 13 | 14 | reg [2:0] state; 15 | 16 | always @(posedge clk) 17 | begin 18 | if (reset) 19 | state <= RED; 20 | else 21 | case (state) 22 | RED: begin 23 | red <= 1'b1; 24 | yellow <= 1'b0; 25 | green <= 1'b0; 26 | state <= YELLOW; 27 | end 28 | 29 | YELLOW: begin 30 | red <= 1'b0; 31 | yellow <= 1'b1; 32 | green <= 1'b0; 33 | state <= GREEN; 34 | end 35 | 36 | GREEN: begin 37 | red <= 1'b0; 38 | yellow <= 1'b0; 39 | green <= 1'b1; 40 | state <= RED; 41 | end 42 | endcase 43 | end 44 | 45 | endmodule 46 | ``` 47 | 48 | # Traffic Light Controller Test Bench: 49 | 50 | ```verilog 51 | `timescale 1ns / 1ps 52 | 53 | module traffic_light_tb(); 54 | 55 | reg clk; 56 | reg reset; 57 | 58 | wire red; 59 | wire yellow; 60 | wire green; 61 | 62 | traffic_light_controller dut( .clk(clk), .reset(reset), .red(red), .yellow(yellow), 63 | .green(green) ); 64 | 65 | always #5 clk = ~clk; 66 | 67 | initial begin 68 | clk = 0; 69 | reset = 1; 70 | #10 reset = 0; 71 | 72 | #100 $finish; 73 | end 74 | 75 | always @(posedge clk) begin 76 | $display("RED=%b YELLOW=%b GREEN=%b", red, yellow, green); 77 | end 78 | 79 | endmodule 80 | ``` 81 | 82 | ## Schematics 83 | ![Alt Text](https://i.ibb.co/BwJVGVg/traffic.png) 84 | 85 | ## Simulation 86 | ![Alt Text](https://i.ibb.co/3NfyC6v/traffic-tb.png) 87 | -------------------------------------------------------------------------------- /Day1/Full Adder.md: -------------------------------------------------------------------------------- 1 | # Full Adder using Dataflow modeling 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module Full_Adder_DF( 6 | input A,B,Cin, 7 | output Sum,Carry 8 | ); 9 | assign Sum = A^B^Cin; 10 | assign Carry = (A&B) | Cin & (A^B); 11 | endmodule 12 | ``` 13 | 14 | # truthtable 15 | 16 | | Inputs | | | Outputs | | 17 | |--------|---|-----|---------|--------------| 18 | | A | B | Cin | S (Sum) | Cout (Carry) | 19 | | 0 | 0 | 0 | 0 | 0 | 20 | | 0 | 0 | 1 | 1 | 0 | 21 | | 0 | 1 | 0 | 1 | 0 | 22 | | 0 | 1 | 1 | 0 | 1 | 23 | | 1 | 0 | 0 | 1 | 0 | 24 | | 1 | 0 | 1 | 0 | 1 | 25 | | 1 | 1 | 0 | 0 | 1 | 26 | | 1 | 1 | 1 | 1 | 1 | 27 | 28 | 29 | # Full adder Testbench (dataflow model) 30 | 31 | ```verilog 32 | `timescale 1ns / 1ps 33 | 34 | module full_adder_tb; 35 | 36 | reg A_tb,B_tb,Cin_tb; 37 | wire Sum_tb,Carry_tb; 38 | 39 | Full_Adder_DF dut (.A(A_tb), .B(B_tb), .Cin(Cin_tb), .Sum(Sum_tb), .Carry(Carry_tb) ); 40 | 41 | initial begin 42 | 43 | A_tb = 1'b0; B_tb = 1'b0; Cin_tb = 1'b0; 44 | #10 A_tb = 1'b0; B_tb = 1'b0; Cin_tb = 1'b1; 45 | #10 A_tb = 1'b0; B_tb = 1'b1; Cin_tb = 1'b0; 46 | #10 A_tb = 1'b0; B_tb = 1'b1; Cin_tb = 1'b1; 47 | #10 A_tb = 1'b1; B_tb = 1'b0; Cin_tb = 1'b0; 48 | #10 A_tb = 1'b1; B_tb = 1'b0; Cin_tb = 1'b1; 49 | #10 A_tb = 1'b1; B_tb = 1'b1; Cin_tb = 1'b0; 50 | #10 A_tb = 1'b1; B_tb = 1'b1; Cin_tb = 1'b1; 51 | #10 $stop; 52 | end 53 | 54 | endmodule 55 | 56 | ``` 57 | 58 | ## Schematics 59 | ![Alt Text](https://i.ibb.co/hgQ01V1/FA.png) 60 | 61 | ## Simulation 62 | ![Alt Text](https://i.ibb.co/6BF4BMC/FA_Sim.png) 63 | -------------------------------------------------------------------------------- /Day_10/Comparator.md: -------------------------------------------------------------------------------- 1 | # Custom Comparator: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module custom_compare(input [3:0] input_a, input_b, 7 | output reg equal, less_than, greater_than); 8 | 9 | always @(input_a, input_b) begin 10 | if (input_a == input_b) begin 11 | equal = 1'b1; 12 | less_than = 1'b0; 13 | greater_than = 1'b0; 14 | end 15 | else if (input_a > input_b) begin 16 | equal = 1'b0; 17 | less_than = 1'b0; 18 | greater_than = 1'b1; 19 | end 20 | else begin 21 | equal = 1'b0; 22 | less_than = 1'b1; 23 | greater_than = 1'b0; 24 | end 25 | end 26 | endmodule 27 | ``` 28 | 29 | # Custom Comparator Test Bench: 30 | 31 | ```verilog 32 | `timescale 1ns / 1ps 33 | 34 | module tb_custom_compare(); 35 | 36 | reg [3:0] a, b; 37 | wire equal, less_than, greater_than; 38 | 39 | custom_compare dut ( .input_a(a), .input_b(b), .equal(equal), .less_than(less_than), 40 | .greater_than(greater_than) ); 41 | 42 | reg clk; 43 | always begin 44 | #5 clk = ~clk; 45 | end 46 | 47 | initial begin 48 | clk = 0; 49 | a = 4'b0000; 50 | b = 4'b0000; 51 | #10; 52 | 53 | a = 4'b0101; 54 | b = 4'b0010; 55 | #10; 56 | 57 | a = 4'b0010; 58 | b = 4'b0110; 59 | #10; 60 | 61 | $finish; 62 | end 63 | 64 | always @(posedge clk) begin 65 | $display("a = %b, b = %b", a, b); 66 | $display("Equal: %b, Less Than: %b, Greater Than: %b", 67 | equal, less_than, greater_than); 68 | end 69 | 70 | endmodule 71 | ``` 72 | 73 | ## Schematics 74 | ![Alt Text](https://i.ibb.co/BBMXRxK/comparator.png) 75 | 76 | ## Simulation 77 | ![Alt Text](https://i.ibb.co/JCMB15S/comparator-Tb.png) 78 | -------------------------------------------------------------------------------- /Day_17/1-Bit RAM Cell.md: -------------------------------------------------------------------------------- 1 | # 1-Bit RAM Cell: 2 | A 1-bit RAM cell is the fundamental building block of memory in digital circuits. It stores a single binary value (0 or 1) and supports read and write operations controlled by write and read enable signals. 3 | This essential component plays a crucial role in creating larger memory arrays and sequential logic circuits. 4 | 5 | 6 | ```verilog 7 | `timescale 1ns / 1ps 8 | 9 | module RAM_Cell( 10 | input wire write_enable, write_data, read_enable, 11 | output reg read_data ); 12 | 13 | reg memory_bit; 14 | 15 | always @(posedge write_enable or posedge read_enable) 16 | begin 17 | if (write_enable) 18 | memory_bit <= write_data; 19 | else if (read_enable) 20 | read_data <= memory_bit; 21 | end 22 | 23 | endmodule 24 | ``` 25 | 26 | # 1-Bit RAM Cell Test Bench: 27 | 28 | ```verilog 29 | `timescale 1ns / 1ps 30 | 31 | module RAM_Cell_Testbench; 32 | 33 | reg write_enable; 34 | reg write_data; 35 | reg read_enable; 36 | wire read_data; 37 | 38 | RAM_Cell uut ( .write_enable(write_enable), .write_data(write_data), 39 | .read_enable(read_enable), .read_data(read_data) ); 40 | 41 | reg clock = 0; 42 | 43 | always #5 clock = ~clock; 44 | 45 | initial begin 46 | 47 | write_enable = 0; 48 | write_data = 0; 49 | read_enable = 0; 50 | 51 | write_enable = 1; write_data = 1; #10; 52 | 53 | write_enable = 0; read_enable = 1; #10; 54 | 55 | if (read_data === 1) 56 | $display("Test Passed: Read Data is Correct"); 57 | else 58 | $display("Test Failed: Read Data is Incorrect"); 59 | 60 | $finish; 61 | end 62 | 63 | endmodule 64 | ``` 65 | 66 | ## Schematics 67 | ![Alt Text](https://i.ibb.co/S6pYVtK/1-bit-ram-cell.png) 68 | 69 | ## Simulation 70 | ![Alt Text](https://i.ibb.co/pWjctH0/1-bit-ram-cell-tb.png) 71 | -------------------------------------------------------------------------------- /Day_26/Pseudorandom number generator.md: -------------------------------------------------------------------------------- 1 | # Pseudorandom number generator: 2 | 3 | **Pseudorandom number generators (PRNGs)** are algorithms or hardware circuits that produce sequences of numbers that appear random but are generated using a deterministic process, making them suitable for various applications in simulations, cryptography, and randomization. 4 | 5 | - Use shift registers and XOR feedback. 6 | - Generate seemingly random but deterministic sequences. 7 | - Common in cryptography, data manipulation, and testing. 8 | - Require an initial seed to start. 9 | - Sequence length is determined by register size. 10 | - Efficient and simple in hardware. 11 | - Not suitable for strong cryptography alone. 12 | 13 | ```verilog 14 | `timescale 1ns / 1ps 15 | 16 | module lfsr_prng( 17 | input wire clk, rst, 18 | output wire [3:0] rand_out ); 19 | 20 | reg [3:0] lfsr_state; // 4-bit LFSR state register 21 | 22 | always @(posedge clk or posedge rst) begin 23 | if (rst) begin 24 | lfsr_state <= 4'b1001; // Initial state (can be any non-zero value) 25 | end else begin 26 | // XOR taps for a 4-bit LFSR: 4, 3 27 | lfsr_state <= {lfsr_state[2:0], lfsr_state[3] ^ lfsr_state[0]}; 28 | end 29 | end 30 | 31 | assign rand_out = lfsr_state; 32 | 33 | endmodule 34 | ``` 35 | 36 | # Pseudorandom number generator Test Bench: 37 | 38 | ```verilog 39 | `timescale 1ns / 1ps 40 | 41 | module testbench_lfsr_prng(); 42 | 43 | reg clk; 44 | reg rst; 45 | wire [3:0] rand_out; 46 | 47 | lfsr_prng Dut( .clk(clk), .rst(rst), .rand_out(rand_out) ); 48 | 49 | always begin 50 | #5 clk = ~clk; 51 | end 52 | 53 | initial begin 54 | clk = 0; 55 | rst = 0; 56 | 57 | rst = 1; 58 | #10 rst = 0; 59 | 60 | $monitor("Time %t\t Output %b", $time, rand_out); 61 | 62 | #100 $finish; 63 | end 64 | 65 | endmodule 66 | ``` 67 | 68 | ## Schematics 69 | ![Alt Text](https://i.ibb.co/r5sXdCc/random-num.png) 70 | 71 | ## Simulation 72 | ![Alt Text](https://i.ibb.co/QrMQ1NV/random-num-tb.png) 73 | -------------------------------------------------------------------------------- /Day_21/1101 Moore Sequence Detector.md: -------------------------------------------------------------------------------- 1 | # 1101 Moore Sequence Detector: 2 | 3 | In Moore machine, output only depends on the present state. It is independent of current input. 4 | 5 | ```verilog 6 | module FSM_Moore_Detector( 7 | input Din, 8 | input Clock, 9 | input Reset, 10 | output reg Y ); 11 | 12 | parameter SIN = 3'd0, S1 = 3'd1, S11 = 3'd2, S110 = 3'd3, S1101 = 3'd4; 13 | 14 | reg [2:0] state, next_state; 15 | 16 | always @(posedge Clock, posedge Reset) begin 17 | if(Reset) 18 | state <= SIN; 19 | else 20 | state <= next_state; 21 | end 22 | 23 | always @(*) begin 24 | case(state) 25 | SIN: begin 26 | next_state = Din ? S1 : SIN; 27 | Y = 1'b0; 28 | end 29 | 30 | S1: begin 31 | next_state = Din ? S11 : SIN; 32 | Y = 1'b0; 33 | end 34 | 35 | S11: begin 36 | next_state = Din ? S11 : S110; 37 | Y = 1'b0; 38 | end 39 | 40 | S110: begin 41 | next_state = Din ? S1101 : SIN; 42 | Y = 1'b0; 43 | end 44 | 45 | S1101: begin 46 | next_state = Din ? S11 : SIN; 47 | Y = 1'b1; 48 | end 49 | endcase 50 | end 51 | 52 | endmodule 53 | ``` 54 | 55 | # 1101 Moore Sequence Detector Test Bench: 56 | 57 | ```verilog 58 | `timescale 1ns / 1ps 59 | 60 | module tb_FSM_Moore_Detector(); 61 | 62 | reg Din, Clock, Reset; 63 | wire Y; 64 | 65 | FSM_Moore_Detector dut( .Din(Din), .Clock(Clock), .Reset(Reset), .Y(Y) ); 66 | 67 | always #5 Clock = ~Clock; 68 | 69 | initial begin 70 | Clock = 0; 71 | Reset = 1; 72 | #10 Reset = 0; 73 | 74 | // Input sequence 75 | Din = 1; #10 76 | Din = 0; #10 77 | Din = 1; #10 78 | Din = 1; #10 79 | Din = 0; #10 80 | Din = 1; #10 81 | 82 | #100 83 | $finish; 84 | end 85 | 86 | initial begin 87 | $monitor("Time=%0t Din=%b State=%b Y=%b", $time, Din, dut.state, Y); 88 | end 89 | 90 | endmodule 91 | ``` 92 | 93 | ## Schematics 94 | ![Alt Text](https://i.ibb.co/GWLb9LQ/moore.png) 95 | 96 | ## Simulation 97 | ![Alt Text](https://i.ibb.co/kxFPgHj/moore-tb.png) 98 | -------------------------------------------------------------------------------- /Day_13/Counters.md: -------------------------------------------------------------------------------- 1 | # Ring Counter: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module ring_counter( 7 | input clk, reset, 8 | output reg [3:0] q 9 | ); 10 | 11 | always @(posedge clk or posedge reset) begin 12 | if(reset) 13 | q <= 4'b1000; 14 | else 15 | q <= {q[2:0], q[3]}; 16 | end 17 | 18 | 19 | endmodule 20 | ``` 21 | 22 | # Ring Counter Test Bench: 23 | 24 | ```verilog 25 | `timescale 1ns / 1ps 26 | 27 | module ring_counter_tb(); 28 | 29 | reg clk; 30 | reg reset; 31 | wire [3:0] q; 32 | 33 | ring_counter dut( .clk(clk), .reset(reset), .q(q) ); 34 | 35 | initial begin 36 | clk = 0; 37 | forever #5 clk = ~clk; 38 | end 39 | 40 | initial begin 41 | reset = 1; 42 | #10 reset = 0; 43 | #200 $finish; 44 | end 45 | 46 | initial begin 47 | $monitor("%d : q = %b", $time, q); 48 | end 49 | 50 | endmodule 51 | ``` 52 | ## Schematics 53 | ![Alt Text](https://i.ibb.co/FVV4czS/Ring-Counter.png) 54 | 55 | ## Simulation 56 | ![Alt Text](https://i.ibb.co/KstdGrn/Ring-counter-TB.png) 57 | 58 | # Johnson Counter: 59 | 60 | ```verilog 61 | module johnson_counter( 62 | input clk, 63 | input rst, 64 | output [3:0] q 65 | ); 66 | 67 | reg [3:0] q_reg; 68 | 69 | always @(posedge clk or posedge rst) begin 70 | if (rst) 71 | q_reg <= 4'b0000; 72 | else 73 | q_reg <= {q_reg[2:0], ~q_reg[3]}; 74 | end 75 | 76 | assign q = q_reg; 77 | 78 | endmodule 79 | ``` 80 | 81 | # Johnson Counter Test Bench: 82 | 83 | ```verilog 84 | `timescale 1ns / 1ps 85 | 86 | module johnson_counter_tb; 87 | 88 | reg clk; 89 | reg rst; 90 | 91 | wire [3:0] q; 92 | 93 | johnson_counter dut ( .clk(clk), .rst(rst), .q(q) ); 94 | 95 | always #5 clk = ~clk; 96 | 97 | initial begin 98 | clk = 0; 99 | rst = 1; 100 | 101 | #15; 102 | rst = 0; 103 | 104 | #200; 105 | 106 | $finish; 107 | end 108 | 109 | always @(posedge clk) begin 110 | $display("At time %t, q = %b", $time, q); 111 | end 112 | 113 | endmodule 114 | ``` 115 | 116 | ## Schematics 117 | ![Alt Text](https://i.ibb.co/z63B6j9/johnson-counter.png) 118 | 119 | ## Simulation 120 | ![Alt Text](https://i.ibb.co/QDzPMVc/johnson-counter-tb.png) 121 | -------------------------------------------------------------------------------- /Day8/SR & D Latch.md: -------------------------------------------------------------------------------- 1 | # SR Latch 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module sr_latch ( 6 | input S, 7 | input R, 8 | output Q, 9 | output Qbar 10 | ); 11 | 12 | reg Q, Qbar; 13 | 14 | always @(S, R) begin 15 | if (R == 1'b1) begin 16 | Q <= 1'b0; 17 | Qbar <= 1'b1; 18 | end else if (S == 1'b1) begin 19 | Q <= 1'b1; 20 | Qbar <= 1'b0; 21 | end 22 | end 23 | 24 | endmodule 25 | ``` 26 | 27 | # SR Latch Test Bench: 28 | 29 | ```verilog 30 | `timescale 1ns / 1ps 31 | 32 | module testbench_sr_latch; 33 | 34 | reg S; 35 | reg R; 36 | 37 | wire Q; 38 | wire Qbar; 39 | 40 | sr_latch dut ( .S(S), .R(R), .Q(Q), .Qbar(Qbar) ); 41 | 42 | initial begin 43 | S = 0; 44 | R = 0; 45 | 46 | $monitor(" %0d S %b R %b Q %b Qbar %b", $time, S, R, Q, Qbar); 47 | 48 | S = 0;R = 0; #10; 49 | S = 1;R = 0; #10; 50 | S = 0;R = 1; #10; 51 | S = 0;R = 0; #10; 52 | 53 | 54 | $finish; 55 | end 56 | 57 | endmodule 58 | ``` 59 | 60 | ## Schematics 61 | ![Alt Text](https://i.ibb.co/3zWwBkP/SR-Latch.png) 62 | 63 | ## Simulation 64 | ![Alt Text](https://i.ibb.co/FHqnxMg/SR-Latch-simu.png) 65 | 66 | 67 | # D Latch: 68 | ```verilog 69 | `timescale 1ns / 1ps 70 | 71 | module D_Latch ( 72 | input D, 73 | input EN, 74 | output reg Q, 75 | output Qbar 76 | ); 77 | 78 | assign Qbar = ~Q; 79 | 80 | always @(D, EN) 81 | begin 82 | if (EN) 83 | Q <= D; 84 | end 85 | 86 | endmodule 87 | ``` 88 | 89 | # D Latch Test Bench: 90 | 91 | ```verilog 92 | `timescale 1ns / 1ps 93 | 94 | module testbench; 95 | 96 | reg D; 97 | reg EN; 98 | wire Q; 99 | wire Qbar; 100 | 101 | D_Latch dut ( .D(D), .EN(EN), .Q(Q), .Qbar(Qbar) ); 102 | 103 | initial begin 104 | D = 0; 105 | EN = 0; 106 | 107 | $display("Time D EN Q Qbar"); 108 | $monitor("%d %b %b %b %b", $time, D, EN, Q, Qbar); 109 | 110 | EN = 1; 111 | D = 1; #10; 112 | D = 0; #10; 113 | 114 | EN = 0; 115 | D = 1; #10; 116 | D = 0; #10; 117 | $finish; 118 | end 119 | 120 | endmodule 121 | ``` 122 | 123 | ## Schematics 124 | ![Alt Text](https://i.ibb.co/GWzg2J4/D-Latch.png) 125 | 126 | ## Simulation 127 | ![Alt Text](https://i.ibb.co/SQLxn7F/D-Latch-simu.png) 128 | -------------------------------------------------------------------------------- /Day2/Ripple_Carry_Adder.md: -------------------------------------------------------------------------------- 1 | # Ripple Carry Adder 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module ripple_carry_adder_4bit( 6 | input[3:0] a, 7 | input[3:0] b, 8 | input cin, 9 | output[3:0] sum, 10 | output cout 11 | ); 12 | wire[2:0] w; 13 | 14 | full_adder a1(.A(a[0]), .B(b[0]), .Cin(cin), .Carry(w0), .Sum(sum[0])); 15 | full_adder a2(.A(a[1]), .B(b[1]), .Cin(w0), .Carry(w1), .Sum(sum[1])); 16 | full_adder a3(.A(a[2]), .B(b[2]), .Cin(w1), .Carry(w2), .Sum(sum[2])); 17 | full_adder a4(.A(a[3]), .B(b[3]), .Cin(w2), .Carry(cout), .Sum(sum[3])); 18 | 19 | endmodule 20 | 21 | module full_adder(A,B,Cin,Carry,Sum); 22 | 23 | input A,B,Cin; 24 | output Carry,Sum; 25 | 26 | assign Sum = A^B^Cin; 27 | assign Carry = (A&B) | Cin & (A^B); 28 | 29 | endmodule 30 | ``` 31 | 32 | # truthtable 33 | 34 | | A1 | A2 | A3 | A4 | B4 | B3 | B2 | B1 | S4 | S3 | S2 | S1 | Carry | 35 | |----|----|----|----|----|----|----|----|----|----|----|----|-------| 36 | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 37 | | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 38 | | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 39 | | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 40 | | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 41 | | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 42 | | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 43 | 44 | 45 | # Ripple Carry Adder Testbench 46 | 47 | ```verilog 48 | `timescale 1ns / 1ps 49 | 50 | module tb_ripple_carry_adder_4bit(); 51 | 52 | reg [3:0] a, b; 53 | reg cin; 54 | wire [3:0] sum; 55 | wire cout; 56 | 57 | ripple_carry_adder_4bit dut( 58 | .a(a), 59 | .b(b), 60 | .cin(cin), 61 | .sum(sum), 62 | .cout(cout) 63 | ); 64 | 65 | initial begin 66 | cin = 0; 67 | a = 4'b0000; b = 4'b0000; 68 | #10; 69 | a = 4'b0001; b = 4'b0001; 70 | #10; 71 | a = 4'b0010; b = 4'b0011; 72 | #10; 73 | a = 4'b0001; b = 4'b0110; 74 | #10; 75 | 76 | $display("SUM = %b, COUT = %b", sum, cout); 77 | $finish; 78 | end 79 | 80 | endmodule 81 | ``` 82 | 83 | ## Schematics 84 | ![Alt Text](https://i.ibb.co/SsMw5sH/Ripple_Carry_Adder.png) 85 | 86 | ## Simulation 87 | ![Alt Text](https://i.ibb.co/0FnvV5h/Ripple_Adder_simu.png) 88 | -------------------------------------------------------------------------------- /Day6/Encoders.md: -------------------------------------------------------------------------------- 1 | # 4 to 2 Encoder: 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module encoder_4_2( 6 | input [3:0] in, 7 | output reg [1:0] out 8 | ); 9 | 10 | always @(*) begin 11 | case(in) 12 | 4'b0001 : out = 2'b00; 13 | 4'b0010 : out = 2'b01; 14 | 4'b0100 : out = 2'b10; 15 | 4'b1000 : out = 2'b11; 16 | default : out = 2'bxx; 17 | endcase 18 | end 19 | 20 | endmodule 21 | ``` 22 | 23 | # 4 to 2 Encoder Test Bench: 24 | 25 | ```verilog 26 | module testbench; 27 | 28 | reg [3:0] in; 29 | wire [1:0] out; 30 | 31 | encoder_4_2 dut(.in(in), .out(out) ); 32 | 33 | initial begin 34 | $monitor("in = %b, out = %b", in, out); 35 | in = 4'b0001; #10; 36 | in = 4'b0010; #10; 37 | in = 4'b0100; #10; 38 | in = 4'b1000; #10; 39 | in = 4'b1111; #10; 40 | end 41 | 42 | endmodule 43 | ``` 44 | 45 | ## Schematics 46 | ![Alt Text](https://i.ibb.co/vktjZ64/4-to-2-encoder.png) 47 | 48 | ## Simulation 49 | ![Alt Text](https://i.ibb.co/rsrJvVT/4-to-2-encoder-simu.png) 50 | 51 | 52 | # Octal to Binary Encoder (8 to 3 Encoder) 53 | ```verilog 54 | `timescale 1ns / 1ps 55 | 56 | module octal_to_binary_encoder ( 57 | input [7:0] octal, 58 | output reg [2:0] binary 59 | ); 60 | 61 | always @(*) begin 62 | case(octal) 63 | 8'b0000_0001 : binary = 3'b000; 64 | 8'b0000_0010 : binary = 3'b001; 65 | 8'b0000_0100 : binary = 3'b010; 66 | 8'b0000_1000 : binary = 3'b011; 67 | 8'b0001_0000 : binary = 3'b100; 68 | 8'b0010_0000 : binary = 3'b101; 69 | 8'b0100_0000 : binary = 3'b110; 70 | 8'b1000_0000 : binary = 3'b111; 71 | default: binary = 3'bxxx; 72 | endcase 73 | end 74 | 75 | endmodule 76 | ``` 77 | 78 | # Octal to Binary Encoder (8 to 3 Encoder) Test Bench 79 | 80 | ```verilog 81 | `timescale 1ns / 1ps 82 | 83 | module testbench; 84 | 85 | reg [7:0] octal; 86 | wire [2:0] binary; 87 | 88 | octal_to_binary_encoder dut ( .octal(octal), .binary(binary) ); 89 | 90 | initial begin 91 | $monitor("octal = %b, binary = %b", octal, binary); 92 | 93 | octal = 8'b0000_0001; #10; 94 | octal = 8'b0000_0010; #10; 95 | octal = 8'b0000_0100; #10; 96 | octal = 8'b0000_1000; #10; 97 | octal = 8'b0001_0000; #10; 98 | octal = 8'b0010_0000; #10; 99 | octal = 8'b0100_0000; #10; 100 | octal = 8'b1000_0000; #10; 101 | octal = 8'bXXXX_XXXX; #10; 102 | end 103 | 104 | endmodule 105 | 106 | ``` 107 | 108 | ## Schematics 109 | ![Alt Text](https://i.ibb.co/wYNS9Np/8-to-3-encoder.png) 110 | 111 | ## Simulation 112 | ![Alt Text](https://i.ibb.co/nz2g3C9/8-to-3-encoder-simu.png) 113 | 114 | -------------------------------------------------------------------------------- /Day_22/1010 Mealy Sequence Detector.md: -------------------------------------------------------------------------------- 1 | # 1010 Mealy Sequence Detector: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module mealy_fsm_1010( 7 | input din, clk, rst, 8 | output reg dout ); 9 | reg [1:0] current_state, next_state; 10 | 11 | parameter S0 = 2'b00, 12 | S1 = 2'b01, 13 | S2 = 2'b10, 14 | S3 = 2'b11; 15 | 16 | always @(posedge clk) begin 17 | if (rst == 1) begin 18 | current_state <= S0; 19 | end else begin 20 | current_state <= next_state; 21 | end 22 | end 23 | 24 | always @(current_state or din) begin 25 | case (current_state) 26 | S0: begin 27 | if (din == 1) begin 28 | next_state = S1; 29 | dout = 1'b0; 30 | end else begin 31 | next_state = S0; 32 | dout = 1'b0; 33 | end 34 | end 35 | 36 | S1: begin 37 | if (din == 0) begin 38 | next_state = S2; 39 | dout = 1'b0; 40 | end else begin 41 | next_state = S1; 42 | dout = 1'b0; 43 | end 44 | end 45 | 46 | S2: begin 47 | if (din == 1) begin 48 | next_state = S3; 49 | dout = 1'b0; 50 | end else begin 51 | next_state = S0; 52 | dout = 1'b0; 53 | end 54 | end 55 | 56 | S3: begin 57 | if (din == 0) begin 58 | next_state = S0; 59 | dout = 1'b1; 60 | end else begin 61 | next_state = S1; 62 | dout = 1'b0; 63 | end 64 | end 65 | 66 | default: next_state = S0; 67 | endcase 68 | end 69 | 70 | endmodule 71 | ``` 72 | 73 | # 1010 Mealy Sequence Detector Test Bench: 74 | 75 | ```verilog 76 | `timescale 1ns / 1ps 77 | 78 | module mealy_fsm_tb; 79 | 80 | reg din; 81 | reg clk; 82 | reg rst; 83 | 84 | wire dout; 85 | 86 | mealy_fsm_1010 dut ( .din(din), .clk(clk), .rst(rst), .dout(dout) ); 87 | 88 | always begin 89 | #5 clk = ~clk; 90 | end 91 | 92 | initial begin 93 | 94 | din = 0; 95 | clk = 0; 96 | rst = 1; 97 | #10 rst = 0; 98 | 99 | din = 1; #10; 100 | din = 0; #10; 101 | din = 1; #10; 102 | din = 0; #10; 103 | din = 1; #10; 104 | 105 | $finish; 106 | end 107 | 108 | always @(posedge clk) begin 109 | $monitor("Time=%t, din=%b, dout=%b", $time, din, dout); 110 | end 111 | 112 | endmodule 113 | ``` 114 | 115 | ## Schematics 116 | ![Alt Text](https://i.ibb.co/m9vnz8g/mealy.png) 117 | 118 | ## Simulation 119 | ![Alt Text](https://i.ibb.co/wMVj0wv/mealy-tb.png) 120 | -------------------------------------------------------------------------------- /Day_11/Shift_Registers_1.md: -------------------------------------------------------------------------------- 1 | # Serial in Serial Out (SISO) Shift Register: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module siso_shift_reg ( 7 | input clk, 8 | input serial_in, 9 | output serial_out ); 10 | 11 | reg [3:0] shift_reg; 12 | 13 | always @(posedge clk) begin 14 | shift_reg[0] <= serial_in; // Shift data in from the right 15 | shift_reg[1] <= shift_reg[0]; 16 | shift_reg[2] <= shift_reg[1]; 17 | shift_reg[3] <= shift_reg[2]; 18 | end 19 | 20 | assign serial_out = shift_reg[3]; 21 | 22 | endmodule 23 | ``` 24 | 25 | # SISO Shift Register Test Bench: 26 | 27 | ```verilog 28 | `timescale 1ns / 1ps 29 | 30 | module testbench; 31 | 32 | reg clk; 33 | reg serial_in; 34 | wire serial_out; 35 | 36 | siso_shift_reg dut ( .clk(clk), .serial_in(serial_in), .serial_out(serial_out) ); 37 | 38 | always begin 39 | #5 clk = ~clk; 40 | end 41 | 42 | initial begin 43 | clk = 0; 44 | serial_in = 0; 45 | 46 | $display("Time\tSerial_In\tSerial_Out"); 47 | $monitor("%d\t%d\t%d", $time, serial_in, serial_out); 48 | 49 | serial_in = 1; 50 | #10; 51 | serial_in = 0; 52 | #10; 53 | serial_in = 1; 54 | #10; 55 | serial_in = 0; 56 | #10; 57 | 58 | $finish; 59 | end 60 | 61 | endmodule 62 | ``` 63 | 64 | ## Schematics 65 | ![Alt Text](https://i.ibb.co/Tg3xnyS/SISO.png) 66 | 67 | ## Simulation 68 | ![Alt Text](https://i.ibb.co/1qf4fvm/SISO-TB.png) 69 | 70 | # Serial in Parallel Out (SIPO) Shift Register: 71 | 72 | ```verilog 73 | `timescale 1ns / 1ps 74 | 75 | module sipo_shift_reg ( 76 | input clk, reset, serial_in, 77 | output [3:0] parallel_out 78 | ); 79 | 80 | reg [3:0] shift_reg; 81 | 82 | always @(posedge clk or posedge reset) begin 83 | if (reset) begin 84 | shift_reg <= 4'b0000; 85 | end else begin 86 | shift_reg[0] <= serial_in; 87 | shift_reg[1] <= shift_reg[0]; 88 | shift_reg[2] <= shift_reg[1]; 89 | shift_reg[3] <= shift_reg[2]; 90 | end 91 | end 92 | 93 | assign parallel_out = shift_reg; 94 | 95 | endmodule 96 | ``` 97 | 98 | # SIPO Shift Register Test Bench: 99 | 100 | ```verilog 101 | `timescale 1ns / 1ps 102 | 103 | module sipo_shift_reg_tb; 104 | 105 | reg clk; 106 | reg reset; 107 | reg serial_in; 108 | wire [3:0] parallel_out; 109 | 110 | sipo_shift_reg dut ( .clk(clk), .reset(reset), .serial_in(serial_in), 111 | .parallel_out(parallel_out) ); 112 | 113 | always begin 114 | #5 clk = ~clk; 115 | end 116 | 117 | initial begin 118 | clk = 0; 119 | reset = 0; 120 | serial_in = 0; 121 | 122 | $display("Time\tSerial_In\tParallel_Out"); 123 | $monitor("%d\t%d\t%d", $time, serial_in, parallel_out); 124 | 125 | serial_in = 1; 126 | #10; 127 | serial_in = 0; 128 | #10; 129 | serial_in = 1; 130 | #10; 131 | serial_in = 0; 132 | #10; 133 | 134 | $finish; 135 | end 136 | 137 | endmodule 138 | ``` 139 | 140 | ## Schematics 141 | ![Alt Text](https://i.ibb.co/FhFtQCD/SIPO.png) 142 | 143 | ## Simulation 144 | ![Alt Text](https://i.ibb.co/kKBFxc5/SIPO-TB.png) 145 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # 30 Days of Verilog 2 | 3 | ### Repo was not updated daily. I posted consistently on Linkedin 4 | 5 |

6 | Embark on a journey through 30 days of Verilog exploration! 🌟 7 |

8 | 9 | Welcome to my personal project: **30 Days of Verilog**. Over the next 30 days, I'll be taking a deep dive into the world of digital circuits and Verilog programming. My goal is to create and showcase 30 different digital circuits, each implemented using Verilog HDL. 10 | 11 | ## About the Project 12 | 13 | The aim of this project is to: 14 | 15 | - **Learn Verilog**: Gain a solid understanding of Verilog and its applications. 16 | - **Explore Digital Circuits**: Create a variety of digital circuits to explore different concepts. 17 | - **Document Progress**: Document my journey, challenges, and solutions for each circuit. 18 | - **Share with the Community**: Provide a resource for others interested in Verilog and digital design. 19 | 20 | ## Repository Structure 21 | 22 | Each day, I will add a new folder from **Day 1** to **Day 30**, containing: 23 | 24 | - **Verilog Code**: Implementation of the day's digital circuit in Verilog. 25 | - **README**: Explanation of the circuit, its purpose, and my approach. 26 | - **Simulation**: Simulation results, waveforms, and test benches (if applicable). 27 | - **Reflections**: Insights and lessons learned during the implementation. 28 | 29 | Feel free to follow along, offer suggestions, or learn from my progress! 30 | 31 | ## Table of Contents 32 | 33 | - [Day 1: Half Adder & Full Adder](./Day1) 34 | - [Day 2: Ripple Carry Adder](./Day2) 35 | - [Day 3: Code Conversion(Gray & Binary)](./Day3) 36 | - [Day 4: Multiplexers](./Day4) 37 | - [Day 5: Demultiplexers](./Day5) 38 | - [Day 6: Encoders](./Day6) 39 | - [Day 7: Decoders](./Day7) 40 | - [Day 8: Latches](./Day8) 41 | - [Day 9: Flip-flops](./Day9) 42 | - [Day 10: Comparators](./Day_10) 43 | - [Day 11: Shift Registers (1)](./Day_11) 44 | - [Day 12: Shift Registers (2)](./Day_12) 45 | - [Day 13: Counters](./Day_13) 46 | - [Day 14: MOD-N Counter](./Day_14) 47 | - [Day 15: Gray Counter](./Day_15) 48 | - [Day 16: Booth Multiplier](./Day_16) 49 | - [Day 17: 1-bit RAM cell](./Day_17) 50 | - [Day 18: 4-Bit & 8-Bit RAM](./Day_18) 51 | - [Day 19: 1,4,8-Bit ROM](./Day_19) 52 | - [Day 20: 8-Bit ALU](./Day_20) 53 | - [Day 21: 1101 Moore Sequence Detector](./Day_21) 54 | - [Day 22: 1010 Mealy Sequence Detector](./Day_22) 55 | - [Day 23: PWM (Pulse Width Modulation) generator](./Day_23) 56 | - [Day 24: Fixed Priority Arbiter](./Day_24) 57 | - [Day 25: Round-Robin Arbiter](./Day_25) 58 | - [Day 26: Pseudorandom number generator](./Day_26) 59 | - [Day 27: Frequency Divider by Even Numbers](./Day_27) 60 | - [Day 28: Traffic Light Controller](./Day_28) 61 | - [Day 29: Elevator Controller](./Day_29) 62 | - [Day 30: Factorial](./Day_30) 63 | 64 | ## Let's Connect 65 | 66 | I'd love to share my journey with you and connect with fellow Verilog enthusiasts: 67 | 68 | - Follow me on [GitHub](https://github.com/akashtailor-exe) to stay updated. 69 | - Connect on [LinkedIn](https://www.linkedin.com/in/akash-tailor) for more discussions. 70 | - Reach out via email at [tailorakash2320@gmail.com](mailto:tailorakash2320@gmail.com). 71 | 72 | ## Stay Tuned 73 | 74 | Join me as I explore the world of Verilog programming and digital circuits over the next 30 days. Let's explore, create, and learn together! 75 | 76 |

77 | Happy Verilog coding! 💻 78 |

79 | -------------------------------------------------------------------------------- /Day_24/Fixed Priority Arbiter.md: -------------------------------------------------------------------------------- 1 | # Fixed Priority Arbiter: 2 | 3 | - An **arbiter** is hardware logic that **selects one request from multiple competing requests** to be granted access to a shared resource. commonly used to manage access to shared interconnects, memory buses, caches, and other multi-master systems. 4 | - A **fixed priority arbiter prioritizes requests** based on a pre-determined static **priority ordering**. The highest priority request is granted access first. If multiple requests of the same priority arrive, the numerically lower or earlier request is given priority. 5 | - Fixed priority arbiters are useful when the relative importance of requests is known in advance. Critical traffic like interrupts can be assigned highest priority to minimize latency. **Lower priority requests may experience higher latencies or starvation.** 6 | 7 | ```verilog 8 | `timescale 1ns / 1ps 9 | 10 | module fixed_priority_arbiter( 11 | input clk, reset, 12 | input [7:0] req, 13 | output reg [7:0] grant); 14 | 15 | // grant[0] is the highest priority and grant[7] is the lowest priority. 16 | 17 | always @(posedge clk or posedge reset) begin 18 | 19 | if(reset) grant <= 8'b00000000; 20 | else begin 21 | 22 | if (req[0]) 23 | grant <= 8'b00000001; 24 | 25 | else if (req[1]) 26 | grant <= 8'b00000010; 27 | 28 | else if (req[2]) 29 | grant <= 8'b00000100; 30 | 31 | else if (req[3]) 32 | grant <= 8'b00001000; 33 | 34 | else if (req[4]) 35 | grant <= 8'b00010000; 36 | 37 | else if (req[5]) 38 | grant <= 8'b00100000; 39 | 40 | else if (req[6]) 41 | grant <= 8'b01000000; 42 | 43 | else if (req[7]) 44 | grant <= 8'b10000000; 45 | 46 | else 47 | grant <= 8'b00000000; 48 | 49 | end 50 | end 51 | endmodule 52 | ``` 53 | 54 | # Fixed Priority Arbiter Test Bench: 55 | 56 | ```verilog 57 | `timescale 1ns / 1ps 58 | 59 | module testbench; 60 | 61 | reg clk; 62 | reg reset; 63 | reg [7:0] req; 64 | wire [7:0] grant; 65 | 66 | fixed_priority_arbiter dut (.clk(clk), .reset(reset), .req(req), .grant(grant)); 67 | 68 | initial begin 69 | clk = 0; 70 | forever #5 clk = ~clk; 71 | end 72 | 73 | initial begin 74 | 75 | reset = 1; 76 | req = 0; 77 | 78 | #10 reset = 0; 79 | 80 | #10 req = 8'b11110000; 81 | 82 | #10 req = 8'b00001111; 83 | 84 | #10 req = 8'b10101010; 85 | 86 | #10 req = 0; 87 | 88 | #10 $finish; 89 | 90 | end 91 | 92 | endmodule 93 | ``` 94 | 95 | ## Schematics 96 | ![Alt Text](https://i.ibb.co/Q9xYqch/fixed-priority-arbiter.png) 97 | 98 | ## Simulation 99 | ![Alt Text](https://i.ibb.co/Q8bQMrf/fixed-priority-arbiter-tb.png) 100 | 101 | ### **Advantages:** 102 | 103 | - Simple priority logic - easy to implement in hardware 104 | - Predictable behavior - priority order is fixed and will not change dynamically 105 | - Low latency for high priority requests - highest priority granted first 106 | - Prevent starvation of highest priority requests 107 | 108 | ### **Disadvantages:** 109 | 110 | - Lower priority requests may experience high latency or starvation 111 | - Priority order cannot be changed dynamically based on current needs 112 | - Priority conflicts may occur if multiple high priority requests arrive together 113 | - Does not account for priority inversion - a high priority request may get blocked by a lower priority one 114 | 115 | ## More complex schemes like round-robin can be better when priorities are dynamic. 116 | -------------------------------------------------------------------------------- /Day_29/Elevator Controller.md: -------------------------------------------------------------------------------- 1 | # Elevator Controller: 2 | 3 | A basic elevator controller using a finite state machine to handle floor requests and elevator movement. It includes states such as IDLE, MOVING_UP, MOVING_DOWN, and STOPPED to control elevator behavior. 4 | 5 | ```verilog 6 | module elevator( 7 | input clk, reset, 8 | input [4:0] floor_req, // floor request signals 9 | output reg [4:0] floor_pos // signal indicating elevator position 10 | ); 11 | 12 | parameter IDLE = 3'b000; 13 | parameter MOVING_UP = 3'b001; 14 | parameter MOVING_DOWN = 3'b010; 15 | parameter STOPPED = 3'b011; 16 | 17 | reg [2:0] state; 18 | reg [4:0] floor_req_reg; // register to hold floor requests 19 | reg [4:0] floor_pos_reg; // register to hold elevator position 20 | 21 | always @(posedge clk, posedge reset) begin 22 | if (reset) begin 23 | state <= IDLE; // reset to idle state 24 | floor_req_reg <= 5'b00000; 25 | floor_pos_reg <= 5'b00000; 26 | floor_pos <= floor_pos_reg; 27 | end else begin 28 | case (state) 29 | IDLE: begin 30 | if (floor_req != 5'b00000) begin 31 | if (floor_req > floor_pos_reg) begin 32 | state <= MOVING_UP; // move up to requested floor 33 | end else if (floor_req < floor_pos_reg) begin 34 | state <= MOVING_DOWN; // move down to requested floor 35 | end else begin 36 | state <= STOPPED; // already at requested floor 37 | end 38 | end 39 | end 40 | MOVING_UP: begin 41 | if (floor_pos_reg == floor_req) begin 42 | state <= STOPPED; // reached requested floor 43 | end else begin 44 | floor_pos_reg <= floor_pos_reg + 1; // move up one floor 45 | end 46 | end 47 | MOVING_DOWN: begin 48 | if (floor_pos_reg == floor_req) begin 49 | state <= STOPPED; // reached requested floor 50 | end else begin 51 | floor_pos_reg <= floor_pos_reg - 1; // move down one floor 52 | end 53 | end 54 | STOPPED: begin 55 | floor_req_reg[floor_pos_reg] <= 1'b0; // clear request for current floor 56 | if (floor_req != 5'b00000) begin 57 | if (floor_req > floor_pos_reg) begin 58 | state <= MOVING_UP; // move up to requested floor 59 | end else if (floor_req < floor_pos_reg) begin 60 | state <= MOVING_DOWN; // move down to requested floor 61 | end else begin 62 | state <= STOPPED; // already at requested floor 63 | end 64 | end else begin 65 | state <= IDLE; // no more requests, go back to idle state 66 | end 67 | end 68 | endcase 69 | floor_pos <= floor_pos_reg; 70 | floor_req_reg[floor_req] <= 1'b1; // set request for requested floor 71 | end 72 | end 73 | 74 | endmodule 75 | ``` 76 | 77 | # Elevator Controller Test Bench: 78 | 79 | ```verilog 80 | module elevator_tb; 81 | 82 | reg clk; 83 | reg reset; 84 | reg [4:0] floor_req; 85 | wire [4:0] floor_pos; 86 | 87 | elevator dut ( .clk(clk), .reset(reset), .floor_req(floor_req), .floor_pos(floor_pos)); 88 | 89 | initial begin 90 | clk = 1'b0; 91 | reset = 1'b1; 92 | floor_req = 5'b00000; 93 | #10 reset = 1'b0; 94 | #10 floor_req = 5'b00100; // request floor 3 95 | #100 floor_req = 5'b00010; // request floor 2 96 | #100 floor_req = 5'b01000; // request floor 4 97 | #100 floor_req = 5'b00001; // request floor 1 98 | #100 floor_req = 5'b01010; // request floor 5 99 | #100 $finish; 100 | end 101 | 102 | always #5 clk = ~clk; 103 | 104 | endmodule 105 | ``` 106 | ## Schematics 107 | ![Alt Text](https://i.ibb.co/ZMkvcBw/elevator.png) 108 | 109 | ## Simulation 110 | ![Alt Text](https://i.ibb.co/7XLDJCK/elevator-tb.png) 111 | -------------------------------------------------------------------------------- /Day_19/ROM.md: -------------------------------------------------------------------------------- 1 | # 1-Bit ROM: 2 | 3 | ROM stands for Read-Only Memory. It is a type of non-volatile memory that is used to store data and programs that are not expected to change over time. As the name suggests, data can be read from a ROM, but it cannot be modified or written after it has been programmed. 4 | 5 | ```verilog 6 | `timescale 1ns / 1ps 7 | 8 | module ROM_1Bit( 9 | input wire [1:0] addr, 10 | output wire data ); 11 | 12 | assign data = (addr == 2'b00) ? 1'b0 : // Define data for each memory location 13 | (addr == 2'b01) ? 1'b1 : 14 | (addr == 2'b10) ? 1'b0 : 15 | (addr == 2'b11) ? 1'b1 : 1'b0; // Default value for invalid addresses 16 | 17 | endmodule 18 | ``` 19 | 20 | # 1-Bit ROM Test Bench: 21 | 22 | ```verilog 23 | `timescale 1ns / 1ps 24 | 25 | module ROM_1Bit_Testbench; 26 | 27 | reg [1:0] address; 28 | wire data; 29 | 30 | ROM_1Bit dut ( .addr(addr), .data(data) ); 31 | 32 | initial begin 33 | 34 | addr = 2'b00; 35 | #10; 36 | 37 | addr = 2'b01; 38 | #10; 39 | 40 | if (data === 1'b1) 41 | $display("Test Passed: Read Data is Correct"); 42 | else 43 | $display("Test Failed: Read Data is Incorrect"); 44 | 45 | $finish; 46 | end 47 | 48 | endmodule 49 | ``` 50 | 51 | ## Schematics 52 | ![Alt Text](https://i.ibb.co/2d8yvcZ/1-bit-rom.png) 53 | 54 | ## Simulation 55 | ![Alt Text](https://i.ibb.co/cvj3WgS/1-bit-rom-tb.png) 56 | 57 | # 4-Bit ROM: 58 | 59 | ```verilog 60 | `timescale 1ns / 1ps 61 | 62 | module ROM_4Bit( 63 | input wire [1:0] addr, 64 | output wire [3:0] data ); 65 | 66 | assign data = (addr == 2'b00) ? 4'b0000 : // Define data for each memory location 67 | (addr == 2'b01) ? 4'b1100 : 68 | (addr == 2'b10) ? 4'b0011 : 69 | (addr == 2'b11) ? 4'b1111 : 4'b0000; // Default value for invalid addresses 70 | 71 | endmodule 72 | ``` 73 | 74 | # 4-Bit ROM Test Bench: 75 | 76 | ```verilog 77 | `timescale 1ns / 1ps 78 | 79 | module ROM_4Bit_Testbench; 80 | 81 | reg [1:0] address; 82 | wire [3:0] data; 83 | 84 | ROM_4Bit dut ( .addr(address), .data(data) ); 85 | 86 | initial begin 87 | address = 2'b00; 88 | #10; 89 | 90 | address = 2'b10; 91 | #10; 92 | 93 | if (data === 4'b0011) 94 | $display("Test Passed: Read Data is Correct"); 95 | else 96 | $display("Test Failed: Read Data is Incorrect"); 97 | 98 | $finish; 99 | end 100 | 101 | endmodule 102 | ``` 103 | 104 | ## Schematics 105 | ![Alt Text](https://i.ibb.co/gWHpK84/4-bit-rom.png) 106 | 107 | ## Simulation 108 | ![Alt Text](https://i.ibb.co/nm7458F/4-bit-rom-tb.png) 109 | 110 | # 8-Bit ROM: 111 | 112 | ```verilog 113 | `timescale 1ns / 1ps 114 | 115 | module ROM_8Bit( 116 | input wire [2:0] addr, 117 | output wire [7:0] data ); 118 | 119 | assign data = (addr == 3'b000) ? 8'b00110011 : // Define data for each memory location 120 | (addr == 3'b001) ? 8'b11001100 : 121 | (addr == 3'b010) ? 8'b01010101 : 122 | (addr == 3'b011) ? 8'b10101010 : 123 | (addr == 3'b100) ? 8'b11110000 : 124 | (addr == 3'b101) ? 8'b00001111 : 125 | (addr == 3'b110) ? 8'b10000001 : 126 | (addr == 3'b111) ? 8'b01111110 : 8'b00000000; // Default value for invalid addresses 127 | 128 | endmodule 129 | ``` 130 | 131 | # 8-Bit ROM Test Bench: 132 | 133 | ```verilog 134 | `timescale 1ns / 1ps 135 | 136 | module ROM_8Bit_Testbench; 137 | 138 | reg [2:0] address; 139 | wire [7:0] data; 140 | 141 | ROM_8Bit dut ( .addr(address), .data(data) ); 142 | 143 | initial begin 144 | 145 | address = 3'b000; 146 | #10; 147 | 148 | address = 3'b010; 149 | #10; 150 | 151 | if (data === 8'b01010101) 152 | $display("Test Passed: Read Data is Correct"); 153 | else 154 | $display("Test Failed: Read Data is Incorrect"); 155 | 156 | $finish; 157 | end 158 | 159 | endmodule 160 | ``` 161 | 162 | ## Schematics 163 | ![Alt Text](https://i.ibb.co/93f6p3H/8-bit-rom.png) 164 | 165 | ## Simulation 166 | ![Alt Text](https://i.ibb.co/4mVJYw6/8-bit-rom-tb.png) 167 | -------------------------------------------------------------------------------- /Day_12/Shift_Registers_2.md: -------------------------------------------------------------------------------- 1 | # Parallel In Serial Out shift register: 2 | 3 | ```verilog 4 | `timescale 1ns / 1ps 5 | 6 | module PISO_shift_register ( 7 | input wire clk, reset, parallel_in, 8 | output wire serial_out ); 9 | 10 | reg [3:0] shift_reg; 11 | 12 | always @(posedge clk or posedge reset) begin 13 | if (reset) begin 14 | shift_reg <= 4'b0000; 15 | end else begin 16 | shift_reg[0] <= parallel_in; 17 | shift_reg[1] <= shift_reg[0]; 18 | shift_reg[2] <= shift_reg[1]; 19 | shift_reg[3] <= shift_reg[2]; 20 | end 21 | end 22 | 23 | assign serial_out = shift_reg[3]; 24 | 25 | endmodule 26 | ``` 27 | 28 | # Parallel In Serial Out shift register Test Bench: 29 | 30 | ```verilog 31 | `timescale 1ns / 1ps 32 | 33 | module PISO_shift_register_tb; 34 | reg clk; 35 | reg reset; 36 | reg parallel_in; 37 | 38 | wire serial_out; 39 | 40 | PISO_shift_register dut ( .clk(clk), .reset(reset), .parallel_in(parallel_in), .serial_out(serial_out) ); 41 | 42 | always begin 43 | #5 clk = ~clk; 44 | end 45 | 46 | initial begin 47 | clk = 0; 48 | reset = 0; 49 | parallel_in = 0; 50 | 51 | parallel_in = 1; 52 | #10 parallel_in = 0; 53 | #10 parallel_in = 1; 54 | #10 parallel_in = 0; 55 | #50 $finish; 56 | end 57 | 58 | always @(posedge clk) begin 59 | $display("Serial Out = %b", serial_out); 60 | end 61 | 62 | endmodule 63 | ``` 64 | 65 | ## Schematics 66 | ![Alt Text](https://i.ibb.co/fDvrTzg/PISO.png) 67 | 68 | ## Simulation 69 | ![Alt Text](https://i.ibb.co/tz6yGwj/PISO-TB.png) 70 | 71 | # Parallel In parallel Out shift register: 72 | 73 | ```verilog 74 | module pipo(din,clk,dout); 75 | input wire [3:0] din; 76 | input wire clk; 77 | output reg [3:0] dout; 78 | 79 | always @(posedge clk) 80 | begin 81 | dout <= din; 82 | end 83 | endmodule 84 | ``` 85 | 86 | # Parallel In parallel Out shift register Test Bench: 87 | 88 | ```verilog 89 | `timescale 1ns / 1ps 90 | 91 | module testbench; 92 | 93 | reg clk; 94 | reg [3:0] din; 95 | wire [3:0] dout; 96 | 97 | pipo dut (.clk(clk), .din(din), .dout(dout)); 98 | 99 | initial begin 100 | clk = 0; 101 | forever #5 clk = ~clk; 102 | end 103 | 104 | initial begin 105 | 106 | $monitor("Input=%b, output=%b",din,dout); 107 | 108 | din = 4'b0000; #10; 109 | din = 4'b0110; #10; 110 | din = 4'b0011; #10; 111 | din = 4'b1100; #10; 112 | din = 4'b1010; #10; 113 | din = 4'b0101; #10; 114 | #50 115 | $stop; 116 | 117 | end 118 | 119 | endmodule 120 | ``` 121 | 122 | ## Schematics 123 | ![Alt Text](https://i.ibb.co/Y7YLFwB/PIPO.png) 124 | 125 | ## Simulation 126 | ![Alt Text](https://i.ibb.co/jvw4Hpd/PIPO-TB.png) 127 | 128 | # Bidirectional Shift Register: 129 | 130 | ```verilog 131 | module shift_reg #(parameter MSB = 8) ( input d, clk, en, dir, rstn, 132 | 133 | output reg [MSB-1:0] out ); 134 | 135 | 136 | always @ (posedge clk) 137 | 138 | if (!rstn) 139 | 140 | out <= 0; 141 | 142 | else begin 143 | 144 | if (en) 145 | 146 | case (dir) 147 | 148 | 0 : out <= {out[MSB-2:0], d}; 149 | 150 | 1 : out <= {d, out[MSB-1:1]}; 151 | 152 | endcase 153 | 154 | else 155 | 156 | out <= out; 157 | 158 | end 159 | 160 | endmodule 161 | ``` 162 | 163 | # Bidirectional Shift Register Test Bench: 164 | 165 | ```verilog 166 | `timescale 1ns / 1ps 167 | 168 | module shift_reg_tb; 169 | 170 | parameter MSB = 8; 171 | 172 | reg d; 173 | reg clk; 174 | reg en; 175 | reg dir; 176 | reg rstn; 177 | 178 | wire [MSB-1:0] out; 179 | 180 | shift_reg #(MSB) dut ( .d(d), .clk(clk), .en(en), .dir(dir), .rstn(rstn), .out(out)); 181 | 182 | always #5 clk = ~clk; 183 | 184 | initial begin 185 | clk = 0; 186 | rstn = 1; 187 | en = 1; 188 | dir = 0; 189 | 190 | rstn = 0; 191 | #10; 192 | rstn = 1; 193 | 194 | repeat (8) begin 195 | d = $random; 196 | #10; 197 | end 198 | 199 | dir = 1; 200 | 201 | repeat (8) begin 202 | d = 0; 203 | #10; 204 | end 205 | $monitor("d=%b en=%b dir=%b rstn=%b out=%b", d, en, dir, rstn, out); 206 | 207 | #100; 208 | $finish; 209 | 210 | end 211 | endmodule 212 | ``` 213 | 214 | ## Schematics 215 | ![Alt Text](https://i.ibb.co/vPsnygG/Bi-dir-shift-reg.png) 216 | 217 | ## Simulation 218 | ![Alt Text](https://i.ibb.co/HdjSxxw/Bi-dir-shift-reg-TB.png) 219 | -------------------------------------------------------------------------------- /Day7/Decoders.md: -------------------------------------------------------------------------------- 1 | # 2 to 4 Decoder: 2 | ```verilog 3 | `timescale 1ns / 1ps 4 | 5 | module decoder_2to4 ( 6 | input [1:0] in, 7 | output reg [3:0] out 8 | ); 9 | 10 | always @(*) begin 11 | case(in) 12 | 2'b00: out = 4'b0001; 13 | 2'b01: out = 4'b0010; 14 | 2'b10: out = 4'b0100; 15 | 2'b11: out = 4'b1000; 16 | default: out = 4'b0000; 17 | endcase 18 | end 19 | 20 | endmodule 21 | ``` 22 | 23 | # 2 to 4 Decoder Test Bench: 24 | 25 | ```verilog 26 | `timescale 1ns / 1ps 27 | 28 | module testbench; 29 | 30 | reg [1:0] in; 31 | wire [3:0] out; 32 | 33 | decoder_2to4 dut (.in(in), .out(out)); 34 | 35 | initial begin 36 | 37 | in = 2'b00; #10; 38 | in = 2'b01; #10; 39 | in = 2'b10; #10; 40 | in = 2'b11; #10; 41 | end 42 | 43 | endmodule 44 | ``` 45 | 46 | ## Schematics 47 | ![Alt Text](https://i.ibb.co/yXC4t2y/2-to-4-Decoder.png) 48 | 49 | ## Simulation 50 | ![Alt Text](https://i.ibb.co/5FmzGpQ/2-to-4-Decoder-simu.png) 51 | 52 | 53 | # 3 to 8 Decoder: 54 | ```verilog 55 | `timescale 1ns / 1ps 56 | 57 | module decoder_3to8 ( 58 | input [2:0] in, 59 | output reg [7:0] out 60 | ); 61 | integer i; 62 | always @(*) begin 63 | out = 8'b00000000; 64 | for (i = 0; i < 8; i = i + 1) begin 65 | if (i == in) begin 66 | out[i] = 1'b1; 67 | end 68 | end 69 | end 70 | 71 | endmodule 72 | ``` 73 | 74 | # 3 to 8 Decoder Test Bench: 75 | 76 | ```verilog 77 | `timescale 1ns / 1ps 78 | 79 | module testbench; 80 | 81 | reg [2:0] in; 82 | wire [7:0] out; 83 | 84 | decoder_3to8 dut ( .in(in), .out(out) ); 85 | 86 | initial begin 87 | in = 3'b000; #10; 88 | $display("Input = %b, Output = %b", in, out); 89 | in = 3'b001; #10; 90 | $display("Input = %b, Output = %b", in, out); 91 | in = 3'b010; #10; 92 | $display("Input = %b, Output = %b", in, out); 93 | in = 3'b011; #10; 94 | $display("Input = %b, Output = %b", in, out); 95 | in = 3'b100; #10; 96 | $display("Input = %b, Output = %b", in, out); 97 | in = 3'b101; #10; 98 | $display("Input = %b, Output = %b", in, out); 99 | in = 3'b110; #10; 100 | $display("Input = %b, Output = %b", in, out); 101 | in = 3'b111; #10; 102 | $display("Input = %b, Output = %b", in, out); 103 | 104 | $finish; 105 | end 106 | 107 | endmodule 108 | ``` 109 | 110 | ## Schematics 111 | ![Alt Text](https://i.ibb.co/XytTMLt/3-to-8-Decoder.png) 112 | 113 | ## Simulation 114 | ![Alt Text](https://i.ibb.co/2t089ph/3-to-8-Decoder-simu.png) 115 | 116 | 117 | # 4 to 16 decoder: 118 | ```verilog 119 | `timescale 1ns / 1ps 120 | 121 | module decoder_4to16 ( 122 | input [3:0] in, 123 | output [15:0] out 124 | ); 125 | 126 | assign out[0] = (in == 4'b0000) ? 1'b1 : 1'b0; 127 | assign out[1] = (in == 4'b0001) ? 1'b1 : 1'b0; 128 | assign out[2] = (in == 4'b0010) ? 1'b1 : 1'b0; 129 | assign out[3] = (in == 4'b0011) ? 1'b1 : 1'b0; 130 | assign out[4] = (in == 4'b0100) ? 1'b1 : 1'b0; 131 | assign out[5] = (in == 4'b0101) ? 1'b1 : 1'b0; 132 | assign out[6] = (in == 4'b0110) ? 1'b1 : 1'b0; 133 | assign out[7] = (in == 4'b0111) ? 1'b1 : 1'b0; 134 | assign out[8] = (in == 4'b1000) ? 1'b1 : 1'b0; 135 | assign out[9] = (in == 4'b1001) ? 1'b1 : 1'b0; 136 | assign out[10] = (in == 4'b1010) ? 1'b1 : 1'b0; 137 | assign out[11] = (in == 4'b1011) ? 1'b1 : 1'b0; 138 | assign out[12] = (in == 4'b1100) ? 1'b1 : 1'b0; 139 | assign out[13] = (in == 4'b1101) ? 1'b1 : 1'b0; 140 | assign out[14] = (in == 4'b1110) ? 1'b1 : 1'b0; 141 | assign out[15] = (in == 4'b1111) ? 1'b1 : 1'b0; 142 | 143 | endmodule 144 | ``` 145 | 146 | # 4 to 16 decoder Test Bench: 147 | 148 | ```verilog 149 | `timescale 1ns / 1ps 150 | 151 | module tb_decoder_4to16; 152 | 153 | reg [3:0] in; 154 | wire [15:0] out; 155 | 156 | decoder_4to16 dut ( .in(in), .out(out) ); 157 | 158 | initial begin 159 | 160 | in = 4'b0000;#10; 161 | 162 | in = 4'b0001;#10; 163 | 164 | in = 4'b0010;#10; 165 | 166 | in = 4'b0011;#10; 167 | 168 | in = 4'b1111;#10; 169 | 170 | $finish; 171 | end 172 | 173 | always @(out) begin 174 | $display("Input: %b, Output: %b", in, out); 175 | end 176 | 177 | endmodule 178 | 179 | ``` 180 | 181 | ## Schematics 182 | ![Alt Text](https://i.ibb.co/cvW1YVX/4-to-16-decoder.png) 183 | 184 | ## Simulation 185 | ![Alt Text](https://i.ibb.co/M5bKp69/4-to-16-decoder-simu.png) 186 | -------------------------------------------------------------------------------- /Day5/Demultiplexer.md: -------------------------------------------------------------------------------- 1 | # 1 X 2 Demux: 2 | ```verilog 3 | module demux_1x2 ( 4 | input wire din, 5 | input wire sel, 6 | output wire dout_0, 7 | output wire dout_1 8 | ); 9 | 10 | assign dout_0 = (sel) ? 1'b0 : din; 11 | assign dout_1 = (sel) ? din : 1'b0; 12 | 13 | endmodule 14 | ``` 15 | 16 | # 1 X 2 Demux Testbench 17 | 18 | ```verilog 19 | module testbench_demux_1x2; 20 | 21 | reg din; 22 | reg sel; 23 | wire dout_0; 24 | wire dout_1; 25 | 26 | demux_1x2 dut ( .din(din), .sel(sel), .dout_0(dout_0), .dout_1(dout_1) ); 27 | 28 | initial begin 29 | din = 1'b0; sel = 0; 30 | #10; 31 | din = 1'b1; sel = 0; 32 | #10; 33 | din = 1'b1; sel = 1; 34 | #10; 35 | din = 1'b0; sel = 1; 36 | #10; 37 | $finish; 38 | end 39 | always @(dout_0, dout_1) begin 40 | $display("sel = %b, din = %b, dout_0 = %b, dout_1 = %b", sel, din, dout_0, dout_1); 41 | end 42 | endmodule 43 | ``` 44 | 45 | ## Schematics 46 | ![Alt Text](https://i.ibb.co/vCW1r3K/Demux_1X2.png) 47 | 48 | ## Simulation 49 | ![Alt Text](https://i.ibb.co/wyksGxV/Demux_1X2_Simu.png) 50 | 51 | 52 | # 1 X 4 Demux: 53 | ```verilog 54 | module demux_1x4 ( 55 | input wire din, 56 | input wire [1:0] sel, 57 | output wire dout_0, 58 | output wire dout_1, 59 | output wire dout_2, 60 | output wire dout_3 ); 61 | 62 | assign dout_0 = (sel == 2'b00) ? din : 1'b0; 63 | assign dout_1 = (sel == 2'b01) ? din : 1'b0; 64 | assign dout_2 = (sel == 2'b10) ? din : 1'b0; 65 | assign dout_3 = (sel == 2'b11) ? din : 1'b0; 66 | 67 | endmodule 68 | ``` 69 | 70 | # 1 X 4 Demux Test Bench: 71 | 72 | ```verilog 73 | module testbench_demux_1x4; 74 | 75 | reg din; 76 | reg [1:0] sel; 77 | wire dout_0; 78 | wire dout_1; 79 | wire dout_2; 80 | wire dout_3; 81 | 82 | demux_1x4 uut ( .din(din), .sel(sel), .dout_0(dout_0), .dout_1(dout_1), .dout_2(dout_2), 83 | .dout_3(dout_3) ); 84 | 85 | initial begin 86 | din = 1'b0; sel = 2'b00; #10; 87 | 88 | din = 1'b1; sel = 2'b00; #10; 89 | 90 | din = 1'b1; sel = 2'b01; #10; 91 | 92 | din = 1'b0; sel = 2'b10; #10; 93 | 94 | din = 1'b1; sel = 2'b11; #10; 95 | $finish; 96 | end 97 | 98 | always @(dout_0, dout_1, dout_2, dout_3) begin 99 | $display("sel = %b, din = %b, dout_0 = %b, dout_1 = %b, dout_2 = %b, dout_3 = %b", 100 | sel, din, dout_0, dout_1, dout_2, dout_3); 101 | end 102 | 103 | endmodule 104 | ``` 105 | 106 | ## Schematics 107 | ![Alt Text](https://i.ibb.co/N9VD11h/Demux_1X4.png) 108 | 109 | ## Simulation 110 | ![Alt Text](https://i.ibb.co/8zrrXCH/Demux_1X4_Simu.png) 111 | 112 | 113 | # 1 X 8 Demux: 114 | ```verilog 115 | module demux_1x8 ( 116 | input wire din, 117 | input wire [2:0] sel, 118 | output wire dout_0, 119 | output wire dout_1, 120 | output wire dout_2, 121 | output wire dout_3, 122 | output wire dout_4, 123 | output wire dout_5, 124 | output wire dout_6, 125 | output wire dout_7 126 | ); 127 | 128 | assign dout_0 = (sel == 3'b000) ? din : 1'b0; 129 | assign dout_1 = (sel == 3'b001) ? din : 1'b0; 130 | assign dout_2 = (sel == 3'b010) ? din : 1'b0; 131 | assign dout_3 = (sel == 3'b011) ? din : 1'b0; 132 | assign dout_4 = (sel == 3'b100) ? din : 1'b0; 133 | assign dout_5 = (sel == 3'b101) ? din : 1'b0; 134 | assign dout_6 = (sel == 3'b110) ? din : 1'b0; 135 | assign dout_7 = (sel == 3'b111) ? din : 1'b0; 136 | 137 | endmodule 138 | ``` 139 | 140 | # 1 X 8 Demux TestBench: 141 | 142 | ```verilog 143 | module testbench_demux_1x8; 144 | 145 | reg din; 146 | reg [2:0] sel; 147 | wire dout_0; 148 | wire dout_1; 149 | wire dout_2; 150 | wire dout_3; 151 | wire dout_4; 152 | wire dout_5; 153 | wire dout_6; 154 | wire dout_7; 155 | 156 | demux_1x8 dut ( .din(din), .sel(sel), .dout_0(dout_0), .dout_1(dout_1), .dout_2(dout_2), 157 | .dout_3(dout_3), .dout_4(dout_4), .dout_5(dout_5), .dout_6(dout_6), .dout_7(dout_7)); 158 | 159 | initial begin 160 | din = 1'b0; sel = 3'b000; #10; 161 | 162 | din = 1'b1; sel = 3'b000; #10; 163 | 164 | din = 1'b1; sel = 3'b001; #10; 165 | 166 | din = 1'b0; sel = 3'b010; #10; 167 | 168 | din = 1'b1; sel = 3'b111; #10; 169 | 170 | $finish; 171 | end 172 | 173 | always @(dout_0, dout_1, dout_2, dout_3, dout_4, dout_5, dout_6, dout_7) begin 174 | $display("sel = %b, din = %b, dout_0 = %b, dout_1 = %b, dout_2 = %b, dout_3 = %b, dout_4 = %b, dout_5 = %b, dout_6 = %b, dout_7 = %b", sel, din, dout_0, dout_1, dout_2, dout_3, dout_4, dout_5, dout_6, dout_7); 175 | end 176 | 177 | endmodule 178 | ``` 179 | 180 | ## Schematics 181 | ![Alt Text](https://i.ibb.co/F3CdXzs/Demux_1X8.png) 182 | 183 | ## Simulation 184 | ![Alt Text](https://i.ibb.co/qJSWSzy/Demux_1X8_Simu.png) 185 | -------------------------------------------------------------------------------- /Day_18/4-BIT & 8-BIT RAM.md: -------------------------------------------------------------------------------- 1 | # 4-Bit RAM: 2 | 3 | A 4-Bit RAM module is a digital memory component capable of storing and retrieving 4 bits of binary data. It typically has 16 memory locations, each capable of holding a 4-bit binary value. It supports read and write operations controlled by address selection and write/read enable signals, making it suitable for various applications requiring moderate storage capacity. 4 | 5 | ```verilog 6 | `timescale 1ns / 1ps 7 | 8 | module RAM_4Bit( 9 | input wire [3:0] address, 10 | input wire write_enable, 11 | input wire [3:0] write_data, 12 | input wire read_enable, 13 | output reg [3:0] read_data 14 | ); 15 | 16 | reg [3:0] memory [0:15]; 17 | 18 | always @(posedge write_enable or posedge read_enable) 19 | begin 20 | if (write_enable) 21 | memory[address] <= write_data; 22 | else if (read_enable) 23 | read_data <= memory[address]; 24 | end 25 | 26 | endmodule 27 | ``` 28 | 29 | # 4-Bit RAM Test Bench: 30 | 31 | ```verilog 32 | `timescale 1ns / 1ps 33 | 34 | module RAM_4Bit_Testbench; 35 | 36 | reg [3:0] address; 37 | reg write_enable; 38 | reg [3:0] write_data; 39 | reg read_enable; 40 | wire [3:0] read_data; 41 | 42 | RAM_4Bit dut ( .address(address), .write_enable(write_enable), 43 | .write_data(write_data), .read_enable(read_enable), .read_data(read_data) ); 44 | 45 | reg clock = 0; 46 | 47 | always #5 clock = ~clock; 48 | 49 | initial begin 50 | address = 0; 51 | write_enable = 0; 52 | write_data = 4'b0000; 53 | read_enable = 0; 54 | 55 | write_enable = 1; 56 | address = 2; 57 | write_data = 4'b1101; 58 | #10; 59 | 60 | write_enable = 0; 61 | read_enable = 1; 62 | address = 2; 63 | #10; 64 | 65 | if (read_data === 4'b1101) 66 | $display("Test Passed: Read Data is Correct"); 67 | else 68 | $display("Test Failed: Read Data is Incorrect"); 69 | 70 | $finish; 71 | end 72 | 73 | endmodule 74 | ``` 75 | 76 | ## Schematics 77 | ![Alt Text](https://i.ibb.co/ggxD6S5/4-bit-ram.png) 78 | 79 | ## Simulation 80 | ![Alt Text](https://i.ibb.co/DpzS3BN/4-bit-ram-tb.png) 81 | 82 | # 8-Bit RAM: 83 | 84 | An 8-Bit RAM module is an expanded version of a digital memory unit, capable of storing and retrieving 8 bits of binary data. It offers a larger memory space with 256 memory locations, each accommodating an 8-bit binary value. Similar to the 4-bit RAM, it supports read and write operations, making it suitable for applications requiring greater storage capacity, such as microcontrollers and data storage systems. 85 | 86 | ```verilog 87 | `timescale 1ns / 1ps 88 | 89 | module RAM_8Bit( 90 | input wire [7:0] address, 91 | input wire write_enable, 92 | input wire [7:0] write_data, 93 | input wire read_enable, 94 | output reg [7:0] read_data ); 95 | 96 | reg [7:0] memory [0:255]; 97 | 98 | always @(posedge write_enable or posedge read_enable) 99 | begin 100 | if (write_enable) 101 | memory[address] <= write_data; 102 | else if (read_enable) 103 | read_data <= memory[address]; 104 | end 105 | 106 | endmodule 107 | ``` 108 | 109 | # 8-Bit RAM Test Bench: 110 | 111 | ```verilog 112 | `timescale 1ns / 1ps 113 | 114 | module RAM_8Bit_Testbench; 115 | 116 | reg [7:0] address; 117 | reg write_enable; 118 | reg [7:0] write_data; 119 | reg read_enable; 120 | wire [7:0] read_data; 121 | 122 | RAM_8Bit dut ( .address(address), .write_enable(write_enable), 123 | .write_data(write_data), .read_enable(read_enable), .read_data(read_data) ); 124 | 125 | reg clock = 0; 126 | 127 | always #5 clock = ~clock; 128 | 129 | initial begin 130 | address = 8'b0000_0000; 131 | write_enable = 0; 132 | write_data = 8'b0000_0000; 133 | read_enable = 0; 134 | 135 | write_enable = 1; 136 | address = 8'b0000_0010; 137 | write_data = 8'b1101_1010; 138 | #10; 139 | 140 | write_enable = 0; 141 | read_enable = 1; 142 | address = 8'b0000_0010; 143 | #10; 144 | 145 | if (read_data === 8'b1101_1010) 146 | $display("Test Passed: Read Data is Correct"); 147 | else 148 | $display("Test Failed: Read Data is Incorrect"); 149 | 150 | $finish; 151 | end 152 | 153 | endmodule 154 | ``` 155 | 156 | ## Schematics 157 | ![Alt Text](https://i.ibb.co/TLSrdH8/8-bit-ram.png) 158 | 159 | ## Simulation 160 | ![Alt Text](https://i.ibb.co/g9bGfNs/8-bit-ram-tb.png) 161 | -------------------------------------------------------------------------------- /Day_20/8-BIT ALU.md: -------------------------------------------------------------------------------- 1 | # 8-BIT ALU: 2 | 3 | An 8-bit ALU is a core component of a processor. It handles arithmetic and logic operations on two 8-bit inputs (Operand1 and Operand2) using an opcode to determine the operation. The ALU produces a 16-bit Result and sets flags for carry-out (flagC) and zero result (flagZ). 4 | 5 | ```verilog 6 | module ALU_8bit ( 7 | input [2:0] operation, 8 | input [7:0] operand_A, 9 | input [7:0] operand_B, 10 | output reg [15:0] result = 16'b0, 11 | output reg carry_flag = 1'b0, 12 | output reg zero_flag = 1'b0 13 | ); 14 | 15 | parameter [2:0] ADD = 3'b000, 16 | SUB = 3'b001, 17 | MUL = 3'b010, 18 | AND = 3'b011, 19 | OR = 3'b100, 20 | NAND = 3'b101, 21 | NOR = 3'b110, 22 | XOR = 3'b111; 23 | 24 | always @ (operation or operand_A or operand_B) 25 | begin 26 | case (operation) 27 | ADD: begin 28 | result = operand_A + operand_B; 29 | carry_flag = result[8]; 30 | zero_flag = (result == 16'b0); 31 | end 32 | 33 | SUB: begin 34 | result = operand_A - operand_B; 35 | carry_flag = result[8]; 36 | zero_flag = (result == 16'b0); 37 | end 38 | 39 | MUL: begin 40 | result = operand_A * operand_B; 41 | zero_flag = (result == 16'b0); 42 | end 43 | 44 | AND: begin 45 | result = operand_A & operand_B; 46 | zero_flag = (result == 16'b0); 47 | end 48 | 49 | OR: begin 50 | result = operand_A | operand_B; 51 | zero_flag = (result == 16'b0); 52 | end 53 | 54 | NAND: begin 55 | result = ~(operand_A & operand_B); 56 | zero_flag = (result == 16'b0); 57 | end 58 | 59 | NOR: begin 60 | result = ~(operand_A | operand_B); 61 | zero_flag = (result == 16'b0); 62 | end 63 | 64 | XOR: begin 65 | result = operand_A ^ operand_B; 66 | zero_flag = (result == 16'b0); 67 | end 68 | 69 | default: begin 70 | result = 16'b0; 71 | carry_flag = 1'b0; 72 | zero_flag = 1'b0; 73 | end 74 | endcase 75 | end 76 | 77 | endmodule 78 | ``` 79 | 80 | # 8-Bit ALU Test Bench: 81 | 82 | ```verilog 83 | `timescale 1ns / 1ps 84 | 85 | module ALU_8bit_tb; 86 | 87 | // Inputs 88 | reg [2:0] operation; 89 | reg [7:0] operand_A; 90 | reg [7:0] operand_B; 91 | 92 | // Outputs 93 | wire [15:0] result; 94 | wire carry_flag; 95 | wire zero_flag; 96 | 97 | ALU_8bit dut ( 98 | .operation(operation), .operand_A(operand_A), .operand_B(operand_B), 99 | .result(result), .carry_flag(carry_flag), .zero_flag(zero_flag) ); 100 | 101 | reg clk = 0; 102 | always begin 103 | #5 clk = ~clk; 104 | end 105 | 106 | initial begin 107 | // Test ADD operation 108 | operation = 3'b000; 109 | operand_A = 8'b11011010; 110 | operand_B = 8'b00100111; 111 | #10; 112 | $display("ADD Result: %b, Carry: %b, Zero: %b", result, carry_flag, zero_flag); 113 | 114 | // Test SUB operation 115 | operation = 3'b001; 116 | operand_A = 8'b11011010; 117 | operand_B = 8'b00100111; 118 | #10; 119 | $display("SUB Result: %b, Carry: %b, Zero: %b", result, carry_flag, zero_flag); 120 | 121 | // Test MUL operation 122 | operation = 3'b010; 123 | operand_A = 8'b11011010; 124 | operand_B = 8'b00100111; 125 | #10; 126 | $display("MUL Result: %b, Zero: %b", result, zero_flag); 127 | 128 | // Test AND operation 129 | operation = 3'b011; 130 | operand_A = 8'b11011010; 131 | operand_B = 8'b00100111; 132 | #10; 133 | $display("AND Result: %b, Zero: %b", result, zero_flag); 134 | 135 | // Test OR operation 136 | operation = 3'b100; 137 | operand_A = 8'b11011010; 138 | operand_B = 8'b00100111; 139 | #10; 140 | $display("OR Result: %b, Zero: %b", result, zero_flag); 141 | 142 | // Test NAND operation 143 | operation = 3'b101; 144 | operand_A = 8'b11011010; 145 | operand_B = 8'b00100111; 146 | #10; 147 | $display("NAND Result: %b, Zero: %b", result, zero_flag); 148 | 149 | // Test NOR operation 150 | operation = 3'b110; 151 | operand_A = 8'b11011010; 152 | operand_B = 8'b00100111; 153 | #10; 154 | $display("NOR Result: %b, Zero: %b", result, zero_flag); 155 | 156 | // Test XOR operation 157 | operation = 3'b111; 158 | operand_A = 8'b11011010; 159 | operand_B = 8'b00100111; 160 | #10; 161 | $display("XOR Result: %b, Zero: %b", result, zero_flag); 162 | 163 | $finish; 164 | end 165 | 166 | endmodule 167 | ``` 168 | 169 | ## Schematics 170 | ![Alt Text](https://i.ibb.co/6Y3KHSK/alu.png) 171 | 172 | ## Simulation 173 | ![Alt Text](https://i.ibb.co/Q96XcXx/alu-tb.png) 174 | -------------------------------------------------------------------------------- /Day4/Multiplexers.md: -------------------------------------------------------------------------------- 1 | # 2 X 1 Mux: 2 | ```verilog 3 | 4 | `timescale 1ns / 1ps 5 | 6 | module mux21 (input i0,i1,sel, output reg out); 7 | always @(*) begin 8 | if(sel) 9 | out = i1; 10 | else 11 | out = i0; 12 | end 13 | endmodule 14 | 15 | ``` 16 | 17 | # 2 X 1 Mux Testbench 18 | 19 | ```verilog 20 | 21 | `timescale 1ns / 1ps 22 | 23 | module testbench_mux_2_X_1; 24 | reg i0, i1, sel; 25 | wire out; 26 | 27 | mux21 dut ( .i0(i0), .i1(i1), .sel(sel), .out(out) ); 28 | 29 | initial begin 30 | i0 = 0; 31 | i1 = 1; 32 | sel = 0; 33 | 34 | $display("i0 = %b, i1 = %b, sel = %b, out = %b", i0, i1, sel, out); 35 | 36 | sel = 0; 37 | #10; 38 | $display("i0 = %b, i1 = %b, sel = %b, out = %b", i0, i1, sel, out); 39 | 40 | sel = 1; 41 | #10; 42 | $display("i0 = %b, i1 = %b, sel = %b, out = %b", i0, i1, sel, out); 43 | 44 | $finish; 45 | end 46 | 47 | endmodule 48 | 49 | ``` 50 | 51 | ## Schematics 52 | ![Alt Text](https://i.ibb.co/59y1PBg/2X1_Mux.png) 53 | 54 | ## Simulation 55 | ![Alt Text](https://i.ibb.co/6BvbVgs/2X1_Mux_Tb.png) 56 | 57 | 58 | # 4 X 1 Mux: 59 | ```verilog 60 | 61 | `timescale 1ns / 1ps 62 | 63 | module mux41 ( 64 | input wire [3:0] data_in, 65 | input wire [1:0] sel, 66 | output wire data_out 67 | ); 68 | 69 | assign data_out = (sel == 2'b00) ? data_in[0] : 70 | (sel == 2'b01) ? data_in[1] : 71 | (sel == 2'b10) ? data_in[2] : 72 | data_in[3]; 73 | 74 | endmodule 75 | 76 | ``` 77 | 78 | # 4 X 1 Mux Test Bench: 79 | 80 | ```verilog 81 | 82 | `timescale 1ns / 1ps 83 | 84 | module mux41_tb; 85 | 86 | reg [3:0] data_in; 87 | reg [1:0] sel; 88 | wire data_out; 89 | 90 | mux41 dut ( .data_in(data_in), .sel(sel), .data_out(data_out) ); 91 | 92 | initial begin 93 | 94 | data_in = 4'b0000; 95 | sel = 2'b00; 96 | 97 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 98 | 99 | sel = 2'b00; 100 | #10; 101 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 102 | 103 | sel = 2'b01; 104 | data_in = 4'b1010; 105 | #10; 106 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 107 | 108 | sel = 2'b10; 109 | data_in = 4'b1100; 110 | #10; 111 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 112 | 113 | sel = 2'b11; 114 | data_in = 4'b1111; 115 | #10; 116 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 117 | 118 | $finish; 119 | end 120 | 121 | endmodule 122 | 123 | ``` 124 | 125 | ## Schematics 126 | ![Alt Text](https://i.ibb.co/2kYgpMz/4X1_Mux.png) 127 | 128 | ## Simulation 129 | ![Alt Text](https://i.ibb.co/fdkGCLd/4X1_Mux_Tb.png) 130 | 131 | 132 | # 8 X 1 Mux 133 | ```verilog 134 | 135 | `timescale 1ns / 1ps 136 | 137 | module mux81 ( 138 | input wire [7:0] data_in, 139 | input wire [2:0] sel, 140 | output wire data_out 141 | ); 142 | 143 | assign data_out = (sel == 3'b000) ? data_in[0] : 144 | (sel == 3'b001) ? data_in[1] : 145 | (sel == 3'b010) ? data_in[2] : 146 | (sel == 3'b011) ? data_in[3] : 147 | (sel == 3'b100) ? data_in[4] : 148 | (sel == 3'b101) ? data_in[5] : 149 | (sel == 3'b110) ? data_in[6] : 150 | data_in[7]; 151 | 152 | endmodule 153 | 154 | ``` 155 | 156 | # 8 X 1 Mux TestBench 157 | 158 | ```verilog 159 | 160 | `timescale 1ns / 1ps 161 | 162 | module mux81_tb ; 163 | 164 | reg [7:0] data_in; 165 | reg [2:0] sel; 166 | wire data_out; 167 | 168 | mux81 dut ( .data_in(data_in), .sel(sel), .data_out(data_out) ); 169 | 170 | initial begin 171 | data_in = 8'b00000000; 172 | sel = 3'b000; 173 | 174 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 175 | 176 | sel = 3'b000; 177 | #10; 178 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 179 | 180 | sel = 3'b001; 181 | data_in = 8'b11011011; 182 | #10; 183 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 184 | 185 | sel = 3'b010; 186 | data_in = 8'b10101010; 187 | #10; 188 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 189 | 190 | 191 | sel = 3'b111; 192 | data_in = 8'b11111111; 193 | #10; 194 | $display("data_in = %b, sel = %b, data_out = %b", data_in, sel, data_out); 195 | 196 | $finish; 197 | end 198 | 199 | endmodule 200 | 201 | ``` 202 | 203 | ## Schematics 204 | ![Alt Text](https://i.ibb.co/Lv4qQ2h/8X1_Mux.png) 205 | 206 | ## Simulation 207 | ![Alt Text](https://i.ibb.co/cy6mcJZ/8X1_Mux_Tb.png) 208 | -------------------------------------------------------------------------------- /Day_25/Round-Robin Arbiter.md: -------------------------------------------------------------------------------- 1 | # Round-Robin Arbiter: 2 | 3 | - A round robin arbiter allows each requesting input an equal share of access to a shared resource by cycling through the requests in a circular order. 4 | - It allocates access to each requesting party in a cyclic manner, ensuring fairness by granting each party a turn in a sequential order, regardless of the priority or timing of their requests. 5 | - Round-robin arbiter prevents starvation by fairly granting access to the shared resource in a circular fashion. It ensures that no request is consistently denied access, promoting statistical fairness among competing requests. 6 | 7 | ```verilog 8 | `timescale 1ns / 1ps 9 | 10 | module round_robin_arbiter( 11 | input clk, rst, 12 | input [3:0] req_sigs, 13 | output reg [3:0] grant_sigs ); 14 | 15 | reg [2:0] curr_state; 16 | reg [2:0] next_state; 17 | 18 | parameter [2:0] IDLE = 3'b000; 19 | parameter [2:0] STATE_0 = 3'b001; 20 | parameter [2:0] STATE_1 = 3'b010; 21 | parameter [2:0] STATE_2 = 3'b011; 22 | parameter [2:0] STATE_3 = 3'b100; 23 | 24 | 25 | always @(posedge clk or posedge rst) begin 26 | if(rst) 27 | curr_state <= IDLE; 28 | else 29 | curr_state <= next_state; 30 | end 31 | 32 | always @(*) begin 33 | 34 | case(curr_state) 35 | 36 | IDLE: begin 37 | if(req_sigs[0]) 38 | next_state = STATE_0; 39 | else if(req_sigs[1]) 40 | next_state = STATE_1; 41 | else if(req_sigs[2]) 42 | next_state = STATE_2; 43 | else if(req_sigs[3]) 44 | next_state = STATE_3; 45 | else 46 | next_state = IDLE; 47 | end 48 | 49 | STATE_0: begin 50 | if(req_sigs[1]) 51 | next_state = STATE_1; 52 | else if(req_sigs[2]) 53 | next_state = STATE_2; 54 | else if(req_sigs[3]) 55 | next_state = STATE_3; 56 | else if(req_sigs[0]) 57 | next_state = STATE_0; 58 | else 59 | next_state = IDLE; 60 | end 61 | 62 | STATE_1: begin 63 | if(req_sigs[2]) 64 | next_state = STATE_2; 65 | else if(req_sigs[3]) 66 | next_state = STATE_3; 67 | else if(req_sigs[0]) 68 | next_state = STATE_0; 69 | else if(req_sigs[1]) 70 | next_state = STATE_1; 71 | else 72 | next_state = IDLE; 73 | end 74 | 75 | STATE_2: begin 76 | if(req_sigs[3]) 77 | next_state = STATE_3; 78 | else if(req_sigs[0]) 79 | next_state = STATE_0; 80 | else if(req_sigs[1]) 81 | next_state = STATE_1; 82 | else if(req_sigs[2]) 83 | next_state = STATE_2; 84 | else 85 | next_state = IDLE; 86 | end 87 | 88 | STATE_3: begin 89 | if(req_sigs[0]) 90 | next_state = STATE_0; 91 | else if(req_sigs[1]) 92 | next_state = STATE_1; 93 | else if(req_sigs[2]) 94 | next_state = STATE_2; 95 | else if(req_sigs[3]) 96 | next_state = STATE_3; 97 | else 98 | next_state = IDLE; 99 | end 100 | 101 | default: begin 102 | if(req_sigs[0]) 103 | next_state = STATE_0; 104 | else if(req_sigs[1]) 105 | next_state = STATE_1; 106 | else if(req_sigs[2]) 107 | next_state = STATE_2; 108 | else if(req_sigs[3]) 109 | next_state = STATE_3; 110 | else 111 | next_state = IDLE; 112 | end 113 | 114 | endcase 115 | end 116 | 117 | always @(*) begin 118 | 119 | case(curr_state) 120 | 121 | STATE_0 : grant_sigs = 4'b0001; 122 | STATE_1 : grant_sigs = 4'b0010; 123 | STATE_2 : grant_sigs = 4'b0100; 124 | STATE_3 : grant_sigs = 4'b1000; 125 | 126 | default : grant_sigs = 4'b0000; 127 | 128 | endcase 129 | 130 | end 131 | 132 | endmodule 133 | 134 | ``` 135 | 136 | # Round-Robin Arbiter Test Bench: 137 | 138 | ```verilog 139 | `timescale 1ns / 1ps 140 | 141 | module round_robin_arbiter_tb(); 142 | 143 | reg clk; 144 | reg rst; 145 | reg [3:0] req_sigs; 146 | wire [3:0] grant_sigs; 147 | 148 | round_robin_arbiter dut ( .clk(clk), .rst(rst), .req_sigs(req_sigs), 149 | .grant_sigs(grant_sigs) ); 150 | 151 | always #5 clk = ~clk; 152 | 153 | initial begin 154 | clk = 0; 155 | rst = 0; 156 | req_sigs = 0; 157 | 158 | req_sigs = 4'b1011; 159 | #20; 160 | req_sigs = 4'b1111; 161 | #20; 162 | req_sigs = 4'b1000; 163 | #20; 164 | req_sigs = 4'b1001; 165 | #20; 166 | req_sigs = 4'b1100; 167 | #20; 168 | $finish; 169 | end 170 | 171 | initial begin 172 | $monitor("req_sigs = %b, grant_sigs = %b", req_sigs, grant_sigs); 173 | end 174 | 175 | endmodule 176 | ``` 177 | 178 | ## Schematics 179 | ![Alt Text](https://i.ibb.co/WfK5F7G/RR-Arbiter.png) 180 | 181 | ## Simulation 182 | ![Alt Text](https://i.ibb.co/qMpNjb8/RR-Arbiter-tb.png) 183 | -------------------------------------------------------------------------------- /Day9/FLIP-FLOPS.md: -------------------------------------------------------------------------------- 1 | # SR Flip Flop 2 | 3 | | Clock Edge | S | R | Q | Description | 4 | | --- | --- | --- | --- | --- | 5 | | ↓ | X | X | Q | No Change (Store previous input) | 6 | | ↑ | 0 | 0 | Q | No Change (Store previous input) | 7 | | ↑ | 1 | 0 | 1 | Set Q to 1 | 8 | | ↑ | 0 | 1 | 0 | Reset Q to 0 | 9 | | ↑ | 1 | 1 | X | Invalid state | 10 | 11 | ```verilog 12 | module sr_ff_sync_reset ( 13 | input clk, 14 | input reset, 15 | input s, 16 | input r, 17 | output reg q 18 | ); 19 | 20 | always @(posedge clk) begin 21 | if (reset) 22 | q <= 1'b0; 23 | else 24 | case ({s,r}) 25 | 2'b10: q <= 1'b1; 26 | 2'b01: q <= 1'b0; 27 | default: q <= q; 28 | endcase 29 | end 30 | 31 | endmodule 32 | ``` 33 | 34 | # SR Flip Flop Test Bench: 35 | 36 | ```verilog 37 | `timescale 1ns/1ps 38 | 39 | module sr_ff_sync_reset_tb(); 40 | 41 | reg clk; 42 | reg reset; 43 | reg s; 44 | reg r; 45 | wire q; 46 | 47 | sr_ff_sync_reset dut (.clk(clk), .reset(reset), .s(s), .r(r), .q(q) ); 48 | 49 | initial begin 50 | clk = 0; 51 | forever #5 clk = ~clk; 52 | end 53 | 54 | initial begin 55 | reset = 1; s = 0; r = 0; 56 | #15 reset = 0; 57 | #10 s = 1; r = 0; 58 | #10 s = 0; r = 1; 59 | #10 s = 0; r = 0; 60 | #10 $finish; 61 | end 62 | 63 | initial begin 64 | $monitor("At %t: s = %b, r = %b, reset = %b, q = %b", $time, s, r, reset, q); 65 | end 66 | 67 | endmodule 68 | ``` 69 | 70 | ## Schematics 71 | ![Alt Text](https://i.ibb.co/YT1ZgDF/SR-FF.png) 72 | 73 | ## Simulation 74 | ![Alt Text](https://i.ibb.co/pZgX1gp/SR-FF-TB.png) 75 | 76 | 77 | # JK Flip Flop: 78 | 79 | | J | K | Q(n+1) | State | 80 | | --- | --- | --- | --- | 81 | | 0 | 0 | Qn | No Change | 82 | | 0 | 1 | 0 | RESET | 83 | | 1 | 0 | 1 | SET | 84 | | 1 | 1 | Qn’ | TOGGLE | 85 | 86 | ```verilog 87 | module jk_ff( 88 | input clk, 89 | input j, 90 | input k, 91 | output reg q 92 | ); 93 | 94 | always @(posedge clk) begin 95 | case ({j,k}) 96 | 2'b00: q <= q; 97 | 2'b01: q <= 1'b0; 98 | 2'b10: q <= 1'b1; 99 | 2'b11: q <= ~q; 100 | endcase 101 | end 102 | 103 | endmodule 104 | ``` 105 | 106 | # JK Flip Flop Test Bench: 107 | 108 | ```verilog 109 | `timescale 1ns/1ps 110 | 111 | module jk_ff_tb; 112 | 113 | reg clk; 114 | reg j; 115 | reg k; 116 | wire q; 117 | 118 | jk_ff dut (.clk(clk), .j(j), .k(k), .q(q)); 119 | 120 | always #5 clk = ~clk; 121 | 122 | initial begin 123 | clk = 0; 124 | j = 0; k = 0; #10; 125 | j = 0; k = 1; #10; 126 | j = 1; k = 0; #10; 127 | j = 1; k = 1; #10; 128 | 129 | $finish; 130 | end 131 | 132 | initial begin 133 | $monitor("At %t: j = %b, k = %b, q = %b", $time, j, k, q); 134 | end 135 | 136 | endmodule 137 | ``` 138 | 139 | ## Schematics 140 | ![Alt Text](https://i.ibb.co/hFNCF77/JK-FF-TB.png) 141 | ## Simulation 142 | ![Alt Text](https://i.ibb.co/pLShQ6r/JK-FF.png) 143 | 144 | 145 | # D Flip Flop: 146 | 147 | | CLOCK | D | Q | Qbar | 148 | | --- | --- | --- | --- | 149 | | 0 | 0 | NO CHANGE | NO CHANGE | 150 | | 0 | 1 | NO CHANGE | NO CHANGE | 151 | | 1 | 0 | 0 | 1 | 152 | | 1 | 1 | 1 | 0 | 153 | 154 | ```verilog 155 | module d_ff ( 156 | input clk, 157 | input d, 158 | output reg q, 159 | output qbar 160 | ); 161 | 162 | always @(posedge clk) begin 163 | q <= d; 164 | end 165 | 166 | assign qbar = ~q; 167 | 168 | endmodule 169 | ``` 170 | 171 | # D Flip Flop Test Bench: 172 | 173 | ```verilog 174 | `timescale 1ns/1ps 175 | 176 | module d_ff_tb; 177 | 178 | reg clk; 179 | reg d; 180 | wire q; 181 | wire qbar; 182 | 183 | d_ff dut ( .clk(clk), .d(d), .q(q), .qbar(qbar) ); 184 | 185 | always #5 clk = ~clk; 186 | 187 | initial begin 188 | clk = 0; 189 | d = 0; #10; 190 | d = 1; #10; 191 | d = 0; #10; 192 | d = 1; #10; 193 | 194 | $finish; 195 | end 196 | 197 | initial begin 198 | $monitor("At %t: d = %b, q = %b, qbar = %b", $time, d, q, qbar); 199 | end 200 | 201 | endmodule 202 | ``` 203 | ## Schematics 204 | ![Alt Text](https://i.ibb.co/DRkY2WL/D-FF.png) 205 | ## Simulation 206 | ![Alt Text](https://i.ibb.co/f931Q7H/D-FF-TB.png) 207 | 208 | # T Flip Flop: 209 | 210 | | T | Qn | Qn+1 | | 211 | | --- | --- | --- | --- | 212 | | 0 | 0 | 0 | Unchanged/hold | 213 | | 0 | 1 | 1 | Unchanged/hold | 214 | | 1 | 0 | 1 | Toggle | 215 | | 1 | 1 | 0 | Toggle | 216 | 217 | ```verilog 218 | module t_ff_sync_reset ( 219 | input clk, 220 | input reset, 221 | input t, 222 | output reg q 223 | ); 224 | 225 | always @(posedge clk) begin 226 | if (reset) 227 | q <= 1'b0; 228 | else 229 | q <= ~q; 230 | 231 | if (t) 232 | q <= ~q; 233 | end 234 | 235 | endmodule 236 | ``` 237 | # T Flip Flop Test Bench: 238 | 239 | ```verilog 240 | 241 | `timescale 1ns / 1ps 242 | 243 | module t_flipflop_tb; 244 | 245 | reg T; 246 | reg clk; 247 | reg rst; 248 | wire Q; 249 | 250 | t_flipflop dut ( .T(T), .clk(clk), .rst(rst), .Q(Q) ); 251 | 252 | always begin 253 | clk = 0; 254 | #5; 255 | clk = 1; 256 | #5; 257 | end 258 | 259 | initial begin 260 | T = 0; 261 | rst = 0; 262 | 263 | rst = 1; 264 | #10; 265 | rst = 0; 266 | $display("Time T clk rst Q"); 267 | $monitor("%2t %b %b %b %b", $time, T, clk, rst, Q); 268 | 269 | T = 1; #10; 270 | T = 0; #10; 271 | 272 | rst = 1; #10; 273 | rst = 0; 274 | 275 | T = 1; #10; 276 | T = 0; #10; 277 | 278 | $finish; 279 | end 280 | 281 | endmodule 282 | ``` 283 | 284 | ## Schematics 285 | ![Alt Text](https://i.ibb.co/KwNW7kr/T-FF.png) 286 | ## Simulation 287 | ![Alt Text](https://i.ibb.co/ZVgQFd3/T-FF-TB.png) 288 | --------------------------------------------------------------------------------