├── LICENSE ├── Makefile ├── README.md ├── progmem.c └── rtl └── cpu ├── alu.v ├── branch.v ├── bus_arbiter.v ├── clk_div.v ├── control_unit.v ├── cpu.v ├── csrs.v ├── decode.v ├── defines.v ├── execute.v ├── fetch.v ├── hazard.v ├── imm.v ├── mem.v ├── opcodes.vh ├── ram.v ├── regs.v ├── sync.v ├── timer.v ├── top.v └── uart.v /LICENSE: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/LICENSE -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/Makefile -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/README.md -------------------------------------------------------------------------------- /progmem.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/progmem.c -------------------------------------------------------------------------------- /rtl/cpu/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/alu.v -------------------------------------------------------------------------------- /rtl/cpu/branch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/branch.v -------------------------------------------------------------------------------- /rtl/cpu/bus_arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/bus_arbiter.v -------------------------------------------------------------------------------- /rtl/cpu/clk_div.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/clk_div.v -------------------------------------------------------------------------------- /rtl/cpu/control_unit.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/control_unit.v -------------------------------------------------------------------------------- /rtl/cpu/cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/cpu.v -------------------------------------------------------------------------------- /rtl/cpu/csrs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/csrs.v -------------------------------------------------------------------------------- /rtl/cpu/decode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/decode.v -------------------------------------------------------------------------------- /rtl/cpu/defines.v: -------------------------------------------------------------------------------- 1 | `define FLASH 2 | -------------------------------------------------------------------------------- /rtl/cpu/execute.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/execute.v -------------------------------------------------------------------------------- /rtl/cpu/fetch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/fetch.v -------------------------------------------------------------------------------- /rtl/cpu/hazard.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/hazard.v -------------------------------------------------------------------------------- /rtl/cpu/imm.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/imm.v -------------------------------------------------------------------------------- /rtl/cpu/mem.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/mem.v -------------------------------------------------------------------------------- /rtl/cpu/opcodes.vh: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/opcodes.vh -------------------------------------------------------------------------------- /rtl/cpu/ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/ram.v -------------------------------------------------------------------------------- /rtl/cpu/regs.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/regs.v -------------------------------------------------------------------------------- /rtl/cpu/sync.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/sync.v -------------------------------------------------------------------------------- /rtl/cpu/timer.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/timer.v -------------------------------------------------------------------------------- /rtl/cpu/top.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/top.v -------------------------------------------------------------------------------- /rtl/cpu/uart.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AleksandarKostovic/Riscy-SoC/HEAD/rtl/cpu/uart.v --------------------------------------------------------------------------------