├── LICENSE ├── README.md ├── VERSION ├── extras ├── modelsim_windows │ ├── uc_top_wrap_64.dll │ ├── uc_top_wrap_dpi.sv │ ├── uc_top_wrap_dpi.svh │ ├── xlr8_atmega328clone.sv │ ├── xlr8_board.v │ ├── xlr8_sim_support.sv │ └── xlr8_tb.sv ├── quartus │ ├── altera_modular_adc_control.sdc │ ├── altera_onchip_flash.sdc │ ├── hinj_atmega328clone_16MHz.qxp │ ├── hinj_atmega328clone_32MHz.qxp │ ├── hinj_atmega328clone_64MHz.qxp │ ├── hinj_c16_i0_oDefault_x00.sof │ ├── hinj_top.sdc │ ├── hinj_top_core.qsf │ ├── sno_atmega328clone_16MHz.qxp │ ├── sno_atmega328clone_32MHz.qxp │ ├── sno_atmega328clone_64MHz.qxp │ ├── sno_c16_i0_oDefault_x00.sof │ ├── sno_top.sdc │ ├── sno_top_core.qsf │ ├── snoedge50_atmega328clone_16MHz.qxp │ ├── snoedge50_atmega328clone_32MHz.qxp │ ├── snoedge50_atmega328clone_64MHz.qxp │ ├── snoedge50_c16_i0_oDefault_x00.sof │ ├── snoedge50_top.sdc │ ├── snoedge50_top_core.qsf │ ├── snoedge_atmega328clone_16MHz.qxp │ ├── snoedge_atmega328clone_32MHz.qxp │ ├── snoedge_atmega328clone_64MHz.qxp │ ├── snoedge_c16_i0_oDefault_x00.sof │ ├── snoedge_top.sdc │ ├── snoedge_top_core.qsf │ ├── snom2_atmega328clone_16MHz.qxp │ ├── snom2_atmega328clone_32MHz.qxp │ ├── snom2_atmega328clone_64MHz.qxp │ ├── snom2_c16_i0_oDefault_x00.sof │ ├── snom2_top.sdc │ ├── snom2_top_core.qsf │ ├── xlr8_atmega328clone.qarlog │ ├── xlr8_atmega328clone.qxp │ ├── xlr8_atmega328clone_16MHz.qxp │ ├── xlr8_atmega328clone_32MHz.qxp │ ├── xlr8_atmega328clone_64MHz.qxp │ ├── xlr8_base.qsf │ ├── xlr8_c16_i0_oDefault_x00.sof │ ├── xlr8_i2c_64MHz.qxp │ ├── xlr8_spi_64MHz.qarlog │ ├── xlr8_spi_64MHz.qxp │ ├── xlr8_top.sdc │ ├── xlr8_top_32MHz.sdc │ ├── xlr8_top_core.qsf │ ├── xlr8_top_core.tcl │ └── xlr8_usart_64MHz.qxp └── rtl │ ├── avr_adr_pack.vh │ ├── avr_port.v │ ├── hinj_adr_pack.vh │ ├── ip │ ├── int_osc │ │ ├── .qsys_edit │ │ │ ├── filters.xml │ │ │ ├── int_osc.xml │ │ │ ├── int_osc_schematic.nlv │ │ │ └── preferences.xml │ │ ├── int_osc.BAK.qsys │ │ ├── int_osc.qsys │ │ ├── int_osc.sopcinfo │ │ └── int_osc │ │ │ ├── greybox │ │ │ └── int_osc.v │ │ │ ├── int_osc.bsf │ │ │ ├── int_osc.cmp │ │ │ ├── int_osc.csv │ │ │ ├── int_osc.html │ │ │ ├── int_osc.ppf │ │ │ ├── int_osc.spd │ │ │ ├── int_osc.xml │ │ │ ├── int_osc_bb.v │ │ │ ├── int_osc_generation.rpt │ │ │ ├── int_osc_generation_previous.rpt │ │ │ ├── int_osc_inst.v │ │ │ ├── int_osc_inst.vhd │ │ │ ├── simulation │ │ │ ├── aldec │ │ │ │ └── rivierapro_setup.tcl │ │ │ ├── cadence │ │ │ │ ├── cds.lib │ │ │ │ ├── cds_libs │ │ │ │ │ └── int_osc_0.cds.lib │ │ │ │ ├── hdl.var │ │ │ │ └── ncsim_setup.sh │ │ │ ├── int_osc.sip │ │ │ ├── int_osc.v │ │ │ ├── mentor │ │ │ │ └── msim_setup.tcl │ │ │ ├── submodules │ │ │ │ ├── altera_int_osc.sdc │ │ │ │ └── altera_int_osc.v │ │ │ └── synopsys │ │ │ │ ├── vcs │ │ │ │ └── vcs_setup.sh │ │ │ │ └── vcsmx │ │ │ │ ├── synopsys_sim.setup │ │ │ │ └── vcsmx_setup.sh │ │ │ └── synthesis │ │ │ ├── int_osc.debuginfo │ │ │ ├── int_osc.qip │ │ │ ├── int_osc.v │ │ │ └── submodules │ │ │ ├── altera_int_osc.sdc │ │ │ └── altera_int_osc.v │ ├── pll16 │ │ ├── pll16.ppf │ │ ├── pll16.qip │ │ ├── pll16.v │ │ ├── pll16.vh │ │ └── pll16_bb.v │ ├── ram2p16384x16 │ │ ├── ram2p16384x16.qip │ │ ├── ram2p16384x16.v │ │ ├── ram2p16384x16_bb.v │ │ ├── ram2p16384x16_inst.v │ │ └── ram2p16384x16_syn.v │ └── ram2p32768x16 │ │ ├── ram2932768x16.qip │ │ ├── ram2p32768x16.qip │ │ ├── ram2p32768x16.v │ │ ├── ram2p32768x16_bb.v │ │ ├── ram2p32768x16_inst.v │ │ └── ram2p32768x16_syn.v │ ├── openxlr8_module_io.vh │ ├── sno_adr_pack.vh │ ├── snoedge_adr_pack.vh │ ├── snom2_adr_pack.vh │ ├── synch.v │ ├── synth_ctrl_pack.vh │ ├── xlr8_alorium_top.v │ ├── xlr8_alorium_top_io_hinj.vh │ ├── xlr8_alorium_top_io_snoedge.vh │ ├── xlr8_alorium_top_io_snom2.vh │ ├── xlr8_avr_port.v │ ├── xlr8_clocks.v │ ├── xlr8_d_mem.v │ ├── xlr8_gpio.v │ ├── xlr8_hinj_bixb.v │ ├── xlr8_hinj_gpio.v │ ├── xlr8_iomux328.v │ ├── xlr8_irq.v │ ├── xlr8_p_mem.v │ ├── xlr8_pcint.v │ ├── xlr8_portmux.v │ ├── xlr8_snoedge_gpio.sv │ └── xlr8_xb_pinmux.v ├── keywords.txt ├── library.properties └── src └── XLR8Core.h /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2017 Alorium Technology 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # XLR8Core 2 | OpenXLR8 Core components allow users to integrate their own designs into XLR8 platform 3 | -------------------------------------------------------------------------------- /VERSION: -------------------------------------------------------------------------------- 1 | SVN: 3323 2 | GitHub: 1.4.4 3 | -------------------------------------------------------------------------------- /extras/modelsim_windows/uc_top_wrap_64.dll: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/modelsim_windows/uc_top_wrap_64.dll -------------------------------------------------------------------------------- /extras/modelsim_windows/uc_top_wrap_dpi.svh: -------------------------------------------------------------------------------- 1 | //================================================================= 2 | // Copyright(c) Superion Technology Group Inc., 2016 3 | // ALL RIGHTS RESERVED 4 | // $Id: $ 5 | //================================================================= 6 | // 7 | // File name: : uc_top_wrap_dpi.sv 8 | // Author : Stephen Fraleigh 9 | // Description : 10 | // Header for the top-most verilog representation of the Verilated AVR core. 11 | // This describes the interface to the C model. 12 | // 13 | //================================================================= 14 | /////////////////////////////////////////////////////////////////// 15 | 16 | `ifndef UC_TOP_WRP_DPI_SVH 17 | `define UC_TOP_WRP_DPI_SVH 18 | 19 | typedef struct { 20 | 21 | byte unsigned nrst; 22 | byte unsigned clk; 23 | int unsigned param_app_xb0_enable; 24 | byte unsigned en16mhz; 25 | byte unsigned en128khz; 26 | byte unsigned clk_adcref; 27 | byte unsigned locked_adcref; 28 | byte unsigned pwr_on_nrst; 29 | 30 | //byte unsigned boot_restore_n; 31 | byte unsigned portb_pinx; 32 | byte unsigned portc_pinx; 33 | byte unsigned portd_pinx; 34 | byte unsigned T0_pin; 35 | byte unsigned T1_pin; 36 | byte unsigned ICP1_pin; 37 | byte unsigned rxd; 38 | byte unsigned misoi; 39 | byte unsigned mosii; 40 | byte unsigned scki; 41 | byte unsigned ss_b; 42 | byte unsigned sdain; 43 | byte unsigned sclin; 44 | int unsigned pcint_rcv; 45 | byte unsigned xlr8_irq; 46 | shortint unsigned pm_rd_data; 47 | shortint unsigned pm_core_rd_data; 48 | byte unsigned dm_din; 49 | byte unsigned stgi_xf_io_slv_dbusout; 50 | byte unsigned stgi_xf_io_slv_out_en; 51 | 52 | } uc_wrap_inputs_sv_t; 53 | 54 | 55 | typedef struct { 56 | 57 | byte unsigned core_rstn; // includes all reset sources 58 | byte unsigned rst_flash_n; // reset domain for flash+pmem 59 | byte unsigned portb_portx; 60 | byte unsigned portb_ddrx; 61 | byte unsigned portc_portx; 62 | byte unsigned portc_ddrx; 63 | byte unsigned portd_portx; 64 | byte unsigned portd_ddrx; 65 | byte unsigned ADCD; 66 | byte unsigned ANA_UP; 67 | byte unsigned OC0A_pin; 68 | byte unsigned OC0B_pin; 69 | byte unsigned OC1A_pin; 70 | byte unsigned OC1B_pin; 71 | byte unsigned OC2A_pin; 72 | byte unsigned OC2B_pin; 73 | byte unsigned OC0A_enable; 74 | byte unsigned OC0B_enable; 75 | byte unsigned OC1A_enable; 76 | byte unsigned OC1B_enable; 77 | byte unsigned OC2A_enable; 78 | byte unsigned OC2B_enable; 79 | byte unsigned uart_rx_en; 80 | byte unsigned txd; 81 | byte unsigned uart_tx_en; 82 | byte unsigned misoo; 83 | byte unsigned mosio; 84 | byte unsigned scko; 85 | byte unsigned spe; 86 | byte unsigned spimaster; 87 | byte unsigned twen; 88 | byte unsigned sdaout; 89 | byte unsigned sclout; 90 | shortint unsigned core_reg_z; 91 | int unsigned pcmsk; 92 | byte unsigned pcie; 93 | byte unsigned eimsk; 94 | byte unsigned xlr8_irq_ack; 95 | byte unsigned pm_ce; 96 | byte unsigned pm_wr; 97 | shortint unsigned pm_wr_data; 98 | shortint unsigned pm_addr; 99 | shortint unsigned pm_core_rd_addr; 100 | shortint unsigned dm_adr; 101 | byte unsigned dm_dout; 102 | byte unsigned dm_ce; 103 | byte unsigned dm_we; 104 | byte unsigned dm_dout_rg; 105 | byte unsigned core_ramadr_lo8; 106 | byte unsigned core_ramre; 107 | byte unsigned core_ramwe; 108 | byte unsigned core_dm_sel; 109 | byte unsigned io_arb_mux_adr; 110 | byte unsigned io_arb_mux_iore; 111 | byte unsigned io_arb_mux_iowe; 112 | byte unsigned io_arb_mux_dbusout; 113 | byte unsigned msts_dbusout; 114 | int unsigned gprf0; // Inside the model, this is an array of 8 32-bit values 115 | int unsigned gprf1; 116 | int unsigned gprf2; 117 | int unsigned gprf3; 118 | int unsigned gprf4; 119 | int unsigned gprf5; 120 | int unsigned gprf6; 121 | int unsigned gprf7; 122 | int unsigned debug_bus; 123 | 124 | } uc_wrap_outputs_sv_t; 125 | 126 | 127 | import "DPI-C" function void uc_top_wrap_wrap_init(); 128 | import "DPI-C" function void uc_top_wrap_wrap_run( input uc_wrap_inputs_sv_t inputs, output uc_wrap_outputs_sv_t outputs ); 129 | import "DPI-C" function void uc_top_wrap_wrap_final(); 130 | 131 | `endif // `ifndef UC_TOP_WRP_DPI_SVH 132 | -------------------------------------------------------------------------------- /extras/modelsim_windows/xlr8_board.v: -------------------------------------------------------------------------------- 1 | //================================================================= 2 | // Copyright(c) Alorium Technology Group Inc., 2016 3 | // ALL RIGHTS RESERVED 4 | // $Id: $ 5 | //================================================================= 6 | // 7 | // File name: : xlr8_top.v 8 | // Author : Matt Weber 9 | // Contact : support@aloriumtech.com 10 | // Description : Simulation model of components on the XLR8 11 | // board that we'd like to simulate, most importantly 12 | // the XLR8 chip, but also various pullups and 13 | // enables 14 | // 15 | //================================================================= 16 | /////////////////////////////////////////////////////////////////// 17 | 18 | module xlr8_board 19 | #( 20 | parameter DESIGN_CONFIG = 21 | {25'd0, // [31:14] : reserved 22 | 8'h8, // [13:6] : MAX10 Size, ex: 0x8 = M08, 0x32 = M50 23 | 1'b0, // [5] : ADC_SWIZZLE, 0 = XLR8, 1 = Sno 24 | 1'b0, // [4] : PLL Speed, 0 = 16MHz PLL, 1 = 50Mhz PLL 25 | 1'b1, // [3] : PMEM Size, 0 = 8K (Sim Kludge), 1 = 16K 26 | 2'd0, // [2:1] : Clock Speed, 0 = 16MHZ, 1 = 32MHz, 2 = 64MHz, 3=na 27 | 1'b0 // [0] : FPGA Image, 0 = CFM Application, 1 = CFM Factory 28 | }, 29 | parameter DMEM_SIZE = 4, // Size of DMEM in KB 30 | parameter APP_XB0_ENABLE = 32'hffff_ffff // for APPLICATION design, each bit [i] enables XB[i] 31 | //sjp parameter APP_XB0_ENABLE = 32'h0 // for APPLICATION design, each bit [i] enables XB[i] 32 | ) 33 | ( 34 | //Clock and Reset 35 | input Clock, // 16MHz 36 | input RESET_N, 37 | //Arduino I/Os 38 | inout wire SCL, 39 | inout wire SDA, 40 | inout [13:0] Digital, // Name to match names in original testbench 41 | inout [5:0] Ana_Dig // Name to match names in original testbench 42 | ); 43 | 44 | wire PIN13LED; 45 | // We can disconnect Ana_Dig from ADC inputs if necessary (don't know if it is) by driving 46 | // OE low. Else leave OE as high-Z (don't drive it high). 47 | wire [5:0] DIG_IO; 48 | wire [5:0] DIG_IO_OE; 49 | wire ANA_UP; // Choose ADC ref between AREF pin and regulated 3.3V 50 | wire I2C_ENABLE; // More importantly; disable pullups when doing analog read on A4/A5 51 | // JTAG connector reused as digial IO. On that connector, pin 4 is power, pins 2&10 are ground 52 | // and pin 8 selects between gpio (low) and jtag (high) modes and has a pulldown. 53 | `ifdef JTAG_PIN_SHARE 54 | wire JT9; // external pullup. JTAG function is TDI 55 | wire JT7; // no JTAG function 56 | wire JT6; // no JTAG function 57 | wire JT5; // external pullup. JTAG function is TMS 58 | wire JT3; // JTAG function TDO 59 | wire JT1; // external pulldown, JTAG function is TCK 60 | `else 61 | // For now, we haven't enabled JTAG pin sharing, so JTAGEN is available as a GPIO and JT7 and 62 | // JT6 are the only other pins available 63 | wire JTAGEN; // not being used for JTAG function 64 | wire JT7; // no JTAG function 65 | wire JT6; // no JTAG function 66 | //wire JT67; // Use JT6 and JT7 as differential pair? 67 | `endif // !`ifdef JTAG_PIN_SHARE 68 | // Interface to EEPROM or other device in SOIC-8 spot on the board 69 | wire SOIC7; // WP in the case of an 24AA128SM EEPROM 70 | wire SOIC6; // SCL in the case of an 24AA128SM EEPROM 71 | wire SOIC5; // SDA in the case of an 24AA128SM EEPROM 72 | wire SOIC3; // A2 in the case of an 24AA128SM EEPROM 73 | wire SOIC2; // A1 in the case of an 24AA128SM EEPROM 74 | wire SOIC1; // A0 in the case of an 24AA128SM EEPROM 75 | 76 | /* xlr8_top AUTO_TEMPLATE (.D\([0-9]*\) (Digital[\1]), 77 | .TX (Digital[1]), 78 | .RX (Digital[0]), 79 | .A\([0-9]*\) (DIG_IO[\1]), 80 | );*/ 81 | 82 | xlr8_alorium_top #(/*AUTOINSTPARAM*/ 83 | // Parameters 84 | .DESIGN_CONFIG (DESIGN_CONFIG), 85 | .DMEM_SIZE (DMEM_SIZE), 86 | .APP_XB0_ENABLE (APP_XB0_ENABLE)) 87 | xlr8_top_inst ( 88 | `ifdef JTAG_PIN_SHARE 89 | .JT9 (JT9), 90 | .JT7 (JT7), 91 | .JT6 (JT6), 92 | .JT5 (JT5), 93 | .JT3 (JT3), 94 | .JT1 (JT1), 95 | `else 96 | .JTAGEN (JTAGEN), 97 | .JT7 (JT7), 98 | .JT6 (JT6), 99 | `endif 100 | /*AUTOINST*/ 101 | // Outputs 102 | .PIN13LED (PIN13LED), 103 | .ANA_UP (ANA_UP), 104 | .I2C_ENABLE (I2C_ENABLE), 105 | // Inouts 106 | .SCL (SCL), 107 | .SDA (SDA), 108 | .D13 (Digital[13]), // Templated 109 | .D12 (Digital[12]), // Templated 110 | .D11 (Digital[11]), // Templated 111 | .D10 (Digital[10]), // Templated 112 | .D9 (Digital[9]), // Templated 113 | .D8 (Digital[8]), // Templated 114 | .D7 (Digital[7]), // Templated 115 | .D6 (Digital[6]), // Templated 116 | .D5 (Digital[5]), // Templated 117 | .D4 (Digital[4]), // Templated 118 | .D3 (Digital[3]), // Templated 119 | .D2 (Digital[2]), // Templated 120 | .TX (Digital[1]), // Templated 121 | .RX (Digital[0]), // Templated 122 | .A5 (DIG_IO[5]), // Templated 123 | .A4 (DIG_IO[4]), // Templated 124 | .A3 (DIG_IO[3]), // Templated 125 | .A2 (DIG_IO[2]), // Templated 126 | .A1 (DIG_IO[1]), // Templated 127 | .A0 (DIG_IO[0]), // Templated 128 | .DIG_IO_OE (DIG_IO_OE[5:0]), 129 | .SOIC7 (SOIC7), 130 | .SOIC6 (SOIC6), 131 | .SOIC5 (SOIC5), 132 | .SOIC3 (SOIC3), 133 | .SOIC2 (SOIC2), 134 | .SOIC1 (SOIC1), 135 | // Inputs 136 | .Clock (Clock), 137 | .RESET_N (RESET_N)); 138 | 139 | // The digital I/Os will likely always have pullups, either 140 | // on the board (current plan) or in the chip (green board 141 | // prototypes). 142 | pullup(Digital[13]); 143 | pullup(Digital[12]); 144 | pullup(Digital[11]); 145 | pullup(Digital[10]); 146 | pullup(Digital[9]); 147 | pullup(Digital[8]); 148 | pullup(Digital[7]); 149 | pullup(Digital[6]); 150 | pullup(Digital[5]); 151 | pullup(Digital[4]); 152 | pullup(Digital[3]); 153 | pullup(Digital[2]); 154 | pullup(Digital[1]); 155 | pullup(Digital[0]); 156 | // The SDA/SCL pullups can be enabled/disabled 157 | // when I2C_ENABLE is high, we should get pullups, 158 | // when it is low, we should just set high-Z on 159 | // SDA/SCL 160 | rnmos Q19a (SDA,1'b1,I2C_ENABLE); // (r)esistive version of nmos 161 | rnmos Q19b (SCL,1'b1,I2C_ENABLE); // should reduce 1'b1 to pull strength 162 | // DIG_IO_OE are used to disconnect the digital I/O 163 | // side of A5..A0 from the analog input side 164 | // When DIG_IO_OE is 0 they are disconnected, when 165 | // it is high-Z they are connected, when it is a 166 | // 1 they are also connected, but bad, or at least 167 | // unintended things, could happen in the circuits 168 | // because the pullups are to 5V 169 | pullup(DIG_IO_OE[5]); 170 | pullup(DIG_IO_OE[4]); 171 | pullup(DIG_IO_OE[3]); 172 | pullup(DIG_IO_OE[2]); 173 | pullup(DIG_IO_OE[1]); 174 | pullup(DIG_IO_OE[0]); 175 | tranif1(Ana_Dig[0],DIG_IO[0],DIG_IO_OE[0]); 176 | tranif1(Ana_Dig[1],DIG_IO[1],DIG_IO_OE[1]); 177 | tranif1(Ana_Dig[2],DIG_IO[2],DIG_IO_OE[2]); 178 | tranif1(Ana_Dig[3],DIG_IO[3],DIG_IO_OE[3]); 179 | tranif1(Ana_Dig[4],DIG_IO[4],DIG_IO_OE[4]); 180 | tranif1(Ana_Dig[5],DIG_IO[5],DIG_IO_OE[5]); 181 | 182 | endmodule: xlr8_board 183 | // Local Variables: 184 | // verilog-library-flags:("-y ../../../rtl/") 185 | // End: 186 | 187 | -------------------------------------------------------------------------------- /extras/modelsim_windows/xlr8_sim_support.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////// 2 | //================================================================= 3 | // Copyright(c) Superion Technology Group Inc., 2015 4 | // ALL RIGHTS RESERVED 5 | // $Id: $ 6 | //================================================================= 7 | // 8 | // File name: : xlr8_sim_support.sv 9 | // Author : Stephen Fraleigh 10 | // Description : Works with Arduino software library XLR8SimSupport to 11 | // print messages and get control info. 12 | // This is intended to be bound to an instance of xlr8_gpio. 13 | // 14 | // This implements the following: 15 | // 1. SW writes messages one character at a time to GPIOR2. 16 | // $display them into the transcript/log. 17 | // 2. SW writes an end of transaction identifier to GPIOR1. 18 | // bit 7 means end of sim. Other bits carry error count. 19 | // 20 | // It would also be possible to pass data the 21 | // other direction, which could be useful for simulation-only 22 | // testing but not obvious what to do when running the SW on 23 | // on the board. We'd have to revise the protocol to do this. 24 | // 25 | //================================================================= 26 | /////////////////////////////////////////////////////////////////// 27 | 28 | `ifndef XLR8_SIM_SUPPORT_SV 29 | `define XLR8_SIM_SUPPORT_SV 30 | 31 | module xlr8_sim_support 32 | 33 | (// clks/resets - - - - - - 34 | input clk, 35 | input rstn, 36 | input clken, // used to power off the function 37 | // Register access for registers in first 64 38 | input [5:0] adr, 39 | input [7:0] dbus_in, 40 | input iore, 41 | input iowe, 42 | // Register access for registers not in first 64 43 | input [7:0] ramadr, 44 | input ramre, 45 | input ramwe, 46 | input dm_sel, 47 | 48 | // 49 | // Internals of xlr8_gpio 50 | // 51 | input [7:0] GPIOR0, 52 | input gpior1_we, 53 | input gpior2_we 54 | ); 55 | 56 | 57 | 58 | // initial begin 59 | // // tell xlr8 register that we are in simulation mode. 60 | // // Software can read this reg during setup to detect if 61 | // // it is running in a simulation (1) or on the hardware (0). 62 | // force GPIOR0[0] = 1'b1; 63 | // end 64 | 65 | always @(posedge clk) begin 66 | if (clken && gpior2_we) begin 67 | $write("%s", dbus_in); 68 | end 69 | end 70 | 71 | always @(posedge clk) begin 72 | if (clken && gpior1_we) begin : end_test 73 | bit end_sim; 74 | bit [6:0] err_code; 75 | { end_sim, err_code } = dbus_in; 76 | 77 | if( end_sim ) begin 78 | if( err_code ) begin 79 | $display("test_done. Test ***failed*** with error code %d", err_code); 80 | end 81 | else begin 82 | $display("test_done. Test passed with code %d", err_code ); 83 | end 84 | #10; 85 | $finish; 86 | end 87 | else begin 88 | $display("GPIOR1 written with value %d", dbus_in); 89 | end 90 | end 91 | end 92 | 93 | 94 | endmodule // xlr8_sim_support 95 | 96 | `endif 97 | -------------------------------------------------------------------------------- /extras/modelsim_windows/xlr8_tb.sv: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////// 2 | //================================================================= 3 | // Copyright(c) Superion Technology Group Inc., 2016 4 | // ALL RIGHTS RESERVED 5 | // $Id: $ 6 | //================================================================= 7 | // 8 | // File name: : xlr8_tb.sv 9 | // Author : Stephen Fraleigh 10 | // 11 | //================================================================= 12 | /////////////////////////////////////////////////////////////////// 13 | 14 | // Top-level testbench for XLR8 board. 15 | 16 | module xlr8_tb; 17 | 18 | //------------------------------------------------------- 19 | // Local Parameters 20 | //------------------------------------------------------- 21 | `include "avr_adr_pack.vh" 22 | 23 | //------------------------------------------------------- 24 | // Reg/Wire Declarations 25 | //------------------------------------------------------- 26 | wire [13:0] Digital; 27 | wire [5:0] Ana_Dig; 28 | wire A_Result; // from analog compare 29 | wire RXD; 30 | wire TXD; 31 | wire SDA; 32 | wire SCL; 33 | reg RESET_N; // To xlr8_inst0 of top.v 34 | reg Clock; 35 | 36 | 37 | //------------------------------------------------------- 38 | // save simulation time by not doing boot restore 39 | //------------------------------------------------------- 40 | initial force xlr8_inst0.xlr8_top_inst.uc_top_wrp_vlog_inst.boot_restore_n = 1'b1; 41 | 42 | //------------------------------------------------------- 43 | // Generate clock 44 | //------------------------------------------------------- 45 | initial begin 46 | Clock = 1'b0; 47 | forever begin 48 | #31.25; // 16MHz 49 | Clock = !Clock; 50 | end 51 | end 52 | 53 | //------------------------------------------------------- 54 | // Drive reset 55 | //------------------------------------------------------- 56 | initial begin 57 | RESET_N = 1'b0; 58 | repeat(5) @(posedge Clock); 59 | RESET_N = 1'b1; 60 | end 61 | 62 | //------------------------------------------------------- 63 | // flash initialization 64 | //------------------------------------------------------- 65 | `ifdef STRINGIFY 66 | `undef STRINGIFY 67 | `endif 68 | `define STRINGIFY(str) `"str`" 69 | 70 | `ifdef USE_AVR_C_MODEL 71 | // C model gets the program directly from sketch.dat and isn't able to have different inst0 vs inst1 72 | `else 73 | defparam xlr8_inst0.xlr8_top_inst.uc_top_wrp_vlog_inst.flashload_inst.flash_inst.onchip_flash_0.INIT_FILENAME_SIM = `STRINGIFY(`FLASH0_UFM_DAT); 74 | initial begin 75 | $display("INFO %m @ %t: Loading %s into flash",$time, `STRINGIFY(`FLASH0_UFM_DAT)); 76 | end 77 | `endif 78 | 79 | //------------------------------------------------------- 80 | // Instantiate DUT 81 | //------------------------------------------------------- 82 | 83 | // Initial release only supports simulation of one configuration: 16MHz core, factory image. 84 | localparam INST0_DESIGN_CONFIG = {25'd0, // [31:14] : reserved 85 | 8'h8, // [13:6] : MAX10 Size, ex: 0x8 = M08, 0x32 = M50 86 | 1'b0, // [5] : ADC_SWIZZLE, 0 = XLR8, 1 = Sno 87 | 1'b0, // [4] : PLL Speed, 0 = 16MHz PLL, 1 = 50Mhz PLL 88 | 1'b1, // [3] : PMEM Size, 0 = 8K (Sim Kludge), 1 = 16K 89 | 2'b0, // [2:1] : Clock Speed, 0 = 16MHZ, 1 = 32MHz, 2 = 64MHz, 3=na 90 | 1'b0 // [0] : FPGA Image, 0 = CFM Application, 1 = CFM Factory 91 | }; 92 | 93 | xlr8_board #(// Parameters 94 | .DESIGN_CONFIG (INST0_DESIGN_CONFIG) ) 95 | xlr8_inst0 96 | (.Digital (Digital), 97 | .Ana_Dig (Ana_Dig), 98 | // Inouts 99 | .SDA (SDA), 100 | .SCL (SCL), 101 | .RESET_N (RESET_N), 102 | .Clock (Clock) 103 | ); 104 | 105 | //------------------------------------------------------- 106 | // Bind the simulation support module to the GPIO registers 107 | //------------------------------------------------------- 108 | bind xlr8_gpio xlr8_sim_support xlr8_sim_support_inst(.*); 109 | // tell xlr8 register that we are in simulation mode. 110 | // Software can read this reg to detect if 111 | // it is running in a simulation (1) or on the hardware (0). 112 | initial force xlr8_inst0.xlr8_top_inst.gpio_inst.GPIOR0[0] = 1'b1; 113 | 114 | endmodule // xlr8_tb 115 | -------------------------------------------------------------------------------- /extras/quartus/altera_modular_adc_control.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2015 Altera Corporation. All rights reserved. 2 | # Your use of Altera Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Altera Program License Subscription 7 | # Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Altera and sold by 10 | # Altera or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | #************************************************************** 15 | # Set False Path - ADC Hard to/from Soft Logic is asynchronous 16 | #************************************************************** 17 | ## EOC - Automatically covered in reset_synchronizer SDC 18 | ## CLK_DFT - Automatically covered in reset_synchronizer SDC 19 | 20 | ## DOUT 21 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[0]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[0]}] 22 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[1]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[1]}] 23 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[2]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[2]}] 24 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[3]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[3]}] 25 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[4]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[4]}] 26 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[5]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[5]}] 27 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[6]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[6]}] 28 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[7]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[7]}] 29 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[8]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[8]}] 30 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[9]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[9]}] 31 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[10]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[10]}] 32 | set_false_path -from [get_keepers {*fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|wire_from_adc_dout[11]}] -to [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|dout_flp[11]}] 33 | 34 | ## CHSEL 35 | set_false_path -from [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|chsel[*]}] -to [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|chsel[*]}] 36 | 37 | ## SOC 38 | set_false_path -from [get_registers {*altera_modular_adc_control_fsm:u_control_fsm|soc}] -to [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|soc}] 39 | 40 | 41 | #****************************************************************************************************************** 42 | # Set Net Delay - ADC Hard to/from Soft Logic is constrained to be max data delay of 5ns and min data delay of 0ns 43 | #****************************************************************************************************************** 44 | 45 | ## EOC 46 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|eoc}] -max 5 47 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|eoc}] -min 0 48 | 49 | ## CLK_DFT 50 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|clk_dft}] -max 5 51 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|clk_dft}] -min 0 52 | 53 | ## DOUT 54 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[0]}] -max 5 55 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[1]}] -max 5 56 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[2]}] -max 5 57 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[3]}] -max 5 58 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[4]}] -max 5 59 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[5]}] -max 5 60 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[6]}] -max 5 61 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[7]}] -max 5 62 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[8]}] -max 5 63 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[9]}] -max 5 64 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[10]}] -max 5 65 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[11]}] -max 5 66 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[0]}] -min 0 67 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[1]}] -min 0 68 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[2]}] -min 0 69 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[3]}] -min 0 70 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[4]}] -min 0 71 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[5]}] -min 0 72 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[6]}] -min 0 73 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[7]}] -min 0 74 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[8]}] -min 0 75 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[9]}] -min 0 76 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[10]}] -min 0 77 | set_net_delay -from [get_pins -compatibility_mode {*|adc_inst|adcblock_instance|primitive_instance|dout[11]}] -min 0 78 | 79 | ## CHSEL 80 | set_net_delay -from [get_pins -compatibility_mode {*|u_control_fsm|chsel[*]|q}] -max 5 81 | set_net_delay -from [get_pins -compatibility_mode {*|u_control_fsm|chsel[*]|q}] -min 0 82 | 83 | ## SOC 84 | set_net_delay -from [get_pins -compatibility_mode {*|u_control_fsm|soc|q}] -max 5 85 | set_net_delay -from [get_pins -compatibility_mode {*|u_control_fsm|soc|q}] -min 0 86 | 87 | -------------------------------------------------------------------------------- /extras/quartus/altera_onchip_flash.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2015 Altera Corporation. All rights reserved. 2 | # Your use of Altera Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Altera Program License Subscription 7 | # Agreement, Altera MegaCore Function License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Altera and sold by 10 | # Altera or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | 15 | #************************************************************** 16 | # Time Information 17 | #************************************************************** 18 | 19 | 20 | 21 | #************************************************************** 22 | # Create Clock 23 | #************************************************************** 24 | 25 | 26 | 27 | #************************************************************** 28 | # Create Generated Clock 29 | #************************************************************** 30 | 31 | 32 | 33 | #************************************************************** 34 | # Set Clock Latency 35 | #************************************************************** 36 | 37 | 38 | 39 | #************************************************************** 40 | # Set Clock Uncertainty 41 | #************************************************************** 42 | 43 | 44 | 45 | #************************************************************** 46 | # Set Input Delay 47 | #************************************************************** 48 | 49 | 50 | 51 | #************************************************************** 52 | # Set Output Delay 53 | #************************************************************** 54 | 55 | 56 | 57 | #************************************************************** 58 | # Set Clock Groups 59 | #************************************************************** 60 | 61 | 62 | 63 | #************************************************************** 64 | # Set False Path 65 | #************************************************************** 66 | 67 | set_false_path -to [get_registers {*|flash_busy_reg}] 68 | set_false_path -to [get_registers {*|flash_busy_clear_reg}] 69 | 70 | 71 | #************************************************************** 72 | # Set Multicycle Path 73 | #************************************************************** 74 | 75 | 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-------------------------------------------------------------------------------- /extras/quartus/xlr8_atmega328clone.qarlog: -------------------------------------------------------------------------------- 1 | 2 | 3 | ******* Archived project restoration attempt on Thu May 26 07:56:13 2016 4 | Source archive file: C:/Users/User/Documents/Arduino/libraries/XLR8Core/extras/quartus/xlr8_atmega328clone.qxp 5 | Archive was extracted into C:/Users/User/Documents/Arduino/libraries/XLR8Build/extras/quartus/db/xlr8_top_tmp_qic_import/ 6 | - successfully. 7 | -------------------------------------------------------------------------------- /extras/quartus/xlr8_atmega328clone.qxp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/quartus/xlr8_atmega328clone.qxp -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /extras/quartus/xlr8_base.qsf: -------------------------------------------------------------------------------- 1 | #============================================================================== 2 | # Copyright (c) 2016 Alorium Technology. All right reserved. 3 | #============================================================================== 4 | # 5 | # File Name : xlr8_base.qsf 6 | # Author : Steve Phillips 7 | # Contact : support@aloriumtech.com 8 | # Description: 9 | # This file is used by all Openxlr8 builds. Its is called from the 10 | # [board]_[clock].qsf file in the XLR8Build quartus directory. It 11 | # pulls in some verilog files used in all builds and then call the 12 | # openxlr8 qsf files. 13 | # 14 | 15 | # The following list shows the settings files in the order they are 16 | # read. Indentation indicates which files are sources by parent 17 | # files. The [board]_[clock].qsf file is called automatically based on 18 | # the design revision selected in Quartus. Use the menu item 19 | # Project->Revisions to selct a revision. 20 | # 21 | # +- XLR8Build/extras/quartus/[board]_[clock].qsf 22 | # +- XLR8Core/extras/quartus/[board]_top_core.qsf 23 | # | +- XLR8Core/extras/quartus/xlr8_top_core.tcl 24 | # | +- XLR8Core/extras/quartus/xlr8_top.sdc 25 | # +- XLR8Core/extras/quartus/xlr8_base.qsf 26 | # +- XLR8Build/extras/quartus/openxlr8.qsf 27 | # +- XLR8Build/extras/quartus/openxlr8_builtin.qsf 28 | 29 | 30 | # Quartus settings for XLR8 project 31 | # http://www.aloriumtech.com/xlr8 32 | # https://github.com/AloriumTechnology 33 | #============================================================================== 34 | 35 | # Top level rtl, etc. 36 | set_global_assignment -name SEARCH_PATH ../../../XLR8Core/extras/rtl 37 | set_global_assignment -name SYSTEMVERILOG_FILE ../../../XLR8Core/extras/rtl/xlr8_alorium_top.v 38 | set_global_assignment -name SYSTEMVERILOG_FILE ../../../XLR8Build/extras/rtl/openxlr8.v 39 | set_global_assignment -name SYSTEMVERILOG_FILE ../../../XLR8Build/extras/rtl/xb_info.sv 40 | set_global_assignment -name SYSTEMVERILOG_FILE ../../../XLR8Build/extras/rtl/pll16.vh 41 | set_global_assignment -name TOP_LEVEL_ENTITY xlr8_alorium_top 42 | # SDC file now read in by the BRD_top_core.qsf file 43 | #set_global_assignment -name SDC_FILE ../../../XLR8Core/extras/quartus/xlr8_top.sdc 44 | 45 | 46 | #------------------------------------------------------------------------------ 47 | # Load settings file specific to this OpenXLR8 module 48 | source ../../../XLR8Build/extras/quartus/openxlr8.qsf 49 | source ../../../XLR8Build/extras/quartus/openxlr8_builtin.qsf 50 | 51 | 52 | # Simulation setup 53 | set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER OFF 54 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 55 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation 56 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 57 | set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation 58 | set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH xlr8_tb -section_id eda_simulation 59 | set_global_assignment -name EDA_TEST_BENCH_NAME xlr8_tb -section_id eda_simulation 60 | set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id xlr8_tb 61 | set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME xlr8_tb -section_id xlr8_tb 62 | set_global_assignment -name EDA_EXTRA_ELAB_OPTION "modelsim=-sv_lib ../../../../../XLR8Core/extras/modelsim_windows/uc_top_wrap_64" -section_id eda_simulation 63 | set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE "12.5 %" 64 | set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" 65 | set_global_assignment -name POWER_USE_PVA OFF 66 | set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/rtl/avr_adr_pack.vh -section_id xlr8_tb 67 | set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/modelsim_windows/xlr8_board.v -section_id xlr8_tb 68 | set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/modelsim_windows/xlr8_sim_support.sv -section_id xlr8_tb 69 | set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/modelsim_windows/xlr8_tb.sv -section_id xlr8_tb 70 | set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/modelsim_windows/uc_top_wrap_dpi.sv -section_id xlr8_tb 71 | # set_global_assignment -name EDA_TEST_BENCH_FILE ../../../XLR8Core/extras/modelsim_windows/xlr8_atmega328clone.sv -section_id xlr8_t 72 | 73 | 74 | 75 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 76 | -------------------------------------------------------------------------------- /extras/quartus/xlr8_c16_i0_oDefault_x00.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/quartus/xlr8_c16_i0_oDefault_x00.sof -------------------------------------------------------------------------------- /extras/quartus/xlr8_i2c_64MHz.qxp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/quartus/xlr8_i2c_64MHz.qxp -------------------------------------------------------------------------------- /extras/quartus/xlr8_spi_64MHz.qarlog: -------------------------------------------------------------------------------- 1 | 2 | 3 | ******* Archived project restoration attempt on Fri Sep 16 14:50:27 2022 4 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 5 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/xlr8_c16_i0_oDefault_u16_x00_tmp_qic_import/ 6 | - successfully. 7 | 8 | 9 | ******* Archived project restoration attempt on Fri Sep 16 15:24:58 2022 10 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 11 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/sno_c16_i0_oDefault_u16_x00_tmp_qic_import/ 12 | - successfully. 13 | 14 | 15 | ******* Archived project restoration attempt on Fri Sep 16 15:40:23 2022 16 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 17 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/hinj_c16_i0_oDefault_u16_x00_tmp_qic_import/ 18 | - successfully. 19 | 20 | 21 | ******* Archived project restoration attempt on Fri Sep 16 16:01:00 2022 22 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 23 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/snoedge50_c16_i0_oDefault_u16_x00_tmp_qic_import/ 24 | - successfully. 25 | 26 | 27 | ******* Archived project restoration attempt on Fri Sep 16 16:13:35 2022 28 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 29 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/snoedge_c16_i0_oDefault_u16_x00_tmp_qic_import/ 30 | - successfully. 31 | 32 | 33 | ******* Archived project restoration attempt on Fri Sep 16 16:27:29 2022 34 | Source archive file: /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/library/XLR8Core/extras/quartus/xlr8_spi_64MHz.qxp 35 | Archive was extracted into /scratch/u/steve/r7107/view_svn3249/trunk/atmega328clone/quartus_alorium/db/snom2_c16_i0_oDefault_u16_x00_tmp_qic_import/ 36 | - successfully. 37 | -------------------------------------------------------------------------------- /extras/quartus/xlr8_spi_64MHz.qxp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/quartus/xlr8_spi_64MHz.qxp -------------------------------------------------------------------------------- /extras/quartus/xlr8_top_32MHz.sdc: -------------------------------------------------------------------------------- 1 | # Just set the clock speed, then use the default sdc file for the rest 2 | set base_clk_period 31.25 3 | source ../quartus/xlr8_top.sdc 4 | -------------------------------------------------------------------------------- /extras/quartus/xlr8_top_core.tcl: -------------------------------------------------------------------------------- 1 | # Copyright (c) 2016 Alorium Technology. All right reserved. 2 | # 3 | # Quartus settings for XLR8 project 4 | # http://www.aloriumtech.com/xlr8 5 | # https://github.com/AloriumTechnology 6 | # 7 | # This isn't the complete list of all settings needed for the 8 | # xlr8 project, it is just the settings that are common for 9 | # most/all configurations. This file should be sourced by a 10 | # higher level qsf file that has the rest of the settings needed 11 | 12 | if {![info exists COREDIR]} {set COREDIR ../../../XLR8Core/extras} 13 | 14 | set_global_assignment -name SEARCH_PATH $COREDIR/rtl 15 | set_global_assignment -name QIP_FILE $COREDIR/rtl/ip/int_osc/int_osc/synthesis/int_osc.qip 16 | set_global_assignment -name SIP_FILE $COREDIR/rtl/ip/int_osc/int_osc/simulation/int_osc.sip 17 | set_global_assignment -name QIP_FILE $COREDIR/rtl/ip/pll16/pll16.qip 18 | set_global_assignment -name QIP_FILE $COREDIR/rtl/ip/ram2p16384x16/ram2p16384x16.qip 19 | set_global_assignment -name QIP_FILE $COREDIR/rtl/ip/ram2p32768x16/ram2p32768x16.qip 20 | set_global_assignment -name SDC_FILE $COREDIR/quartus/altera_modular_adc_control.sdc 21 | set_global_assignment -name SDC_FILE $COREDIR/quartus/altera_onchip_flash.sdc 22 | # End of xlr8_top_core.tcl 23 | -------------------------------------------------------------------------------- /extras/quartus/xlr8_usart_64MHz.qxp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AloriumTechnology/XLR8Core/559248ac6731b8cb333d3d0f250a4e63495294b2/extras/quartus/xlr8_usart_64MHz.qxp -------------------------------------------------------------------------------- /extras/rtl/avr_port.v: -------------------------------------------------------------------------------- 1 | /////////////////////////////////////////////////////////////////// 2 | //================================================================= 3 | // Copyright(c) Superion Technology Group Inc., 2015 4 | // ALL RIGHTS RESERVED 5 | // $Id: $ 6 | //================================================================= 7 | // 8 | // File name: : avr_port.v 9 | // Author : Matt Weber 10 | // Description : I/O port based on ATmega328p 11 | // 12 | //================================================================= 13 | /////////////////////////////////////////////////////////////////// 14 | 15 | module avr_port(/*AUTOARG*/ 16 | // Outputs 17 | dbus_out, io_out_en, portx, ddrx, 18 | // Inputs 19 | rstn, clk, clken, adr, dbus_in, iore, iowe, ramadr, ramre, ramwe, dm_sel, 20 | pinx 21 | ); 22 | parameter PORTX_ADDR = 0; 23 | parameter DDRX_ADDR = 0; 24 | parameter PINX_ADDR = 0; 25 | parameter WIDTH = 8; 26 | 27 | // Clock and Reset 28 | input rstn; 29 | input clk; 30 | input clken; 31 | // I/O 32 | input [5:0] adr; 33 | input [7:0] dbus_in; 34 | output [7:0] dbus_out; 35 | input iore; 36 | input iowe; 37 | output io_out_en; 38 | // DM 39 | input [7:0] ramadr; 40 | input ramre; 41 | input ramwe; 42 | input dm_sel; 43 | // External connection 44 | output [WIDTH-1:0] portx; 45 | output [WIDTH-1:0] ddrx; 46 | input [WIDTH-1:0] pinx; 47 | 48 | localparam PORTX_DM_LOC = (PORTX_ADDR >= 16'h60) ? 1 : 0; 49 | localparam DDRX_DM_LOC = (DDRX_ADDR >= 16'h60) ? 1 : 0; 50 | localparam PINX_DM_LOC = (PINX_ADDR >= 16'h60) ? 1 : 0; 51 | 52 | logic portx_sel; 53 | logic ddrx_sel ; 54 | logic pinx_sel ; 55 | logic portx_we; 56 | logic ddrx_we ; 57 | logic pinx_we ; 58 | logic portx_re; 59 | logic ddrx_re ; 60 | logic pinx_re ; 61 | logic [WIDTH-1:0] pinx_sync; 62 | logic [WIDTH-1:0] pinx_sync_no_x; 63 | logic [WIDTH-1:0] portx; 64 | logic [WIDTH-1:0] ddrx; 65 | 66 | //%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% 67 | 68 | assign portx_sel = PORTX_DM_LOC ? (dm_sel && ramadr == PORTX_ADDR ) : (adr[5:0] == PORTX_ADDR ); 69 | assign ddrx_sel = DDRX_DM_LOC ? (dm_sel && ramadr == DDRX_ADDR ) : (adr[5:0] == DDRX_ADDR ); 70 | assign pinx_sel = PINX_DM_LOC ? (dm_sel && ramadr == PINX_ADDR ) : (adr[5:0] == PINX_ADDR ); 71 | assign portx_we = portx_sel && (PORTX_DM_LOC ? ramwe : iowe); 72 | assign ddrx_we = ddrx_sel && (DDRX_DM_LOC ? ramwe : iowe); 73 | assign pinx_we = pinx_sel && (PINX_DM_LOC ? ramwe : iowe); 74 | assign portx_re = portx_sel && (PORTX_DM_LOC ? ramre : iore); 75 | assign ddrx_re = ddrx_sel && (DDRX_DM_LOC ? ramre : iore); 76 | assign pinx_re = pinx_sel && (PINX_DM_LOC ? ramre : iore); 77 | assign dbus_out = ({8{portx_sel}} & portx) | 78 | ({8{ddrx_sel}} & ddrx) | 79 | ({8{pinx_sel}} & pinx_sync_no_x); 80 | assign io_out_en = portx_re || 81 | ddrx_re || 82 | pinx_re; 83 | 84 | always @(posedge clk or negedge rstn) begin 85 | if (!rstn) begin 86 | /*AUTORESET*/ 87 | // Beginning of autoreset for uninitialized flops 88 | ddrx <= {WIDTH{1'b0}}; 89 | // End of automatics 90 | end else if (clken && ddrx_we) begin 91 | ddrx <= dbus_in[WIDTH-1:0]; 92 | end 93 | end // always @ (posedge clk or negedge rstn) 94 | always @(posedge clk or negedge rstn) begin 95 | if (!rstn) begin 96 | /*AUTORESET*/ 97 | // Beginning of autoreset for uninitialized flops 98 | portx <= {WIDTH{1'b0}}; 99 | // End of automatics 100 | end else if (clken && portx_we) begin 101 | portx <= dbus_in[WIDTH-1:0]; 102 | end else if (clken && pinx_we) begin // toggle function from spec 14.2.2 103 | portx <= portx ^ dbus_in[WIDTH-1:0]; 104 | end 105 | end // always @ (posedge clk or negedge rstn) 106 | 107 | // Synchronizer is latch followed by flop as shown in ATmega328p spec figures 14-2 and 14-5 108 | // Our device doesn't have latches, so we instead use negedge flop followed by posedge flop 109 | // and that should have the same timing. 110 | synch Tn_sync[WIDTH-1:0] (.dout (pinx_sync), 111 | .clk (clk), 112 | .din (pinx)); 113 | // It is entirely reasonable (typical even) to run with some IOs unconnected. When reading 114 | // the pin register for IOs that are being used, the unconnected ones that don't have 115 | // pullups would be X in simulation and cause assertion failures. Work around that by 116 | // converting Xs to random values. 117 | always @(pinx_sync or pinx_re) begin 118 | int i; 119 | for (i=0;i 2 | 3 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/.qsys_edit/int_osc_schematic.nlv: -------------------------------------------------------------------------------- 1 | # # File gsaved with Nlview version 6.3.8 2013-12-19 bk=1.2992 VDI=34 GEI=35 2 | # 3 | preplace inst unsaved.int_osc_0 -pg 1 -lvl 1 -y 30 4 | preplace inst unsaved -pg 1 -lvl 1 -y 40 -regy -20 5 | preplace netloc EXPORTunsaved(MASTER)unsaved.clkout,(MASTER)int_osc_0.clkout) 1 1 1 NJ 6 | preplace netloc EXPORTunsaved(SLAVE)unsaved.oscena,(SLAVE)int_osc_0.oscena) 1 0 1 NJ 7 | levelinfo -pg 1 0 50 280 8 | levelinfo -hier unsaved 60 90 210 9 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/.qsys_edit/preferences.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc.BAK.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc.qsys: -------------------------------------------------------------------------------- 1 | 2 | 3 | 10 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/greybox/int_osc.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and its AMPP partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details. 14 | 15 | // VENDOR "Altera" 16 | // PROGRAM "Quartus Prime" 17 | // VERSION "Version 17.1.0 Build 590 10/25/2017 SJ Standard Edition" 18 | 19 | // DATE "02/25/2018 18:49:19" 20 | 21 | // 22 | // Device: Altera 10M08SAU169C8G Package UFBGA169 23 | // 24 | 25 | // 26 | // This greybox netlist file is for third party Synthesis Tools 27 | // for timing and resource estimation only. 28 | // 29 | 30 | 31 | module int_osc ( 32 | clkout, 33 | oscena)/* synthesis synthesis_greybox=0 */; 34 | output clkout; 35 | input oscena; 36 | 37 | wire gnd; 38 | wire vcc; 39 | wire unknown; 40 | 41 | assign gnd = 1'b0; 42 | assign vcc = 1'b1; 43 | // unknown value (1'bx) is not needed for this tool. Default to 1'b0 44 | assign unknown = 1'b0; 45 | 46 | wire \int_osc_0|wire_clkout ; 47 | wire \oscena~_wirecell_combout ; 48 | wire \oscena~input_o ; 49 | 50 | 51 | int_osc_altera_int_osc int_osc_0( 52 | .clkout(\int_osc_0|wire_clkout ), 53 | .oscena(\oscena~_wirecell_combout )); 54 | 55 | fiftyfivenm_lcell_comb \oscena~_wirecell ( 56 | .dataa(\oscena~input_o ), 57 | .datab(gnd), 58 | .datac(gnd), 59 | .datad(gnd), 60 | .cin(gnd), 61 | .combout(\oscena~_wirecell_combout ), 62 | .cout()); 63 | defparam \oscena~_wirecell .lut_mask = 16'h5555; 64 | defparam \oscena~_wirecell .sum_lutc_input = "datac"; 65 | 66 | assign \oscena~input_o = oscena; 67 | 68 | assign clkout = \int_osc_0|wire_clkout ; 69 | 70 | endmodule 71 | 72 | module int_osc_altera_int_osc ( 73 | clkout, 74 | oscena)/* synthesis synthesis_greybox=0 */; 75 | output clkout; 76 | input oscena; 77 | 78 | wire gnd; 79 | wire vcc; 80 | wire unknown; 81 | 82 | assign gnd = 1'b0; 83 | assign vcc = 1'b1; 84 | // unknown value (1'bx) is not needed for this tool. Default to 1'b0 85 | assign unknown = 1'b0; 86 | 87 | 88 | 89 | fiftyfivenm_oscillator oscillator_dut( 90 | .oscena(!oscena), 91 | .clkout(clkout), 92 | .clkout1()); 93 | defparam oscillator_dut.clock_frequency = "116"; 94 | defparam oscillator_dut.device_id = "08"; 95 | 96 | endmodule 97 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.bsf: -------------------------------------------------------------------------------- 1 | /* 2 | WARNING: Do NOT edit the input and output ports in this file in a text 3 | editor if you plan to continue editing the block that represents it in 4 | the Block Editor! File corruption is VERY likely to occur. 5 | */ 6 | /* 7 | Copyright (C) 2017 Intel Corporation. All rights reserved. 8 | Your use of Intel Corporation's design tools, logic functions 9 | and other software and tools, and its AMPP partner logic 10 | functions, and any output files from any of the foregoing 11 | (including device programming or simulation files), and any 12 | associated documentation or information are expressly subject 13 | to the terms and conditions of the Intel Program License 14 | Subscription Agreement, the Intel Quartus Prime License Agreement, 15 | the Intel FPGA IP License Agreement, or other applicable license 16 | agreement, including, without limitation, that your use is for 17 | the sole purpose of programming logic devices manufactured by 18 | Intel and sold by Intel or its authorized distributors. Please 19 | refer to the applicable agreement for further details. 20 | */ 21 | (header "symbol" (version "1.1")) 22 | (symbol 23 | (rect 0 0 160 104) 24 | (text "int_osc" (rect 59 -1 87 11)(font "Arial" (font_size 10))) 25 | (text "inst" (rect 8 88 20 100)(font "Arial" )) 26 | (port 27 | (pt 0 72) 28 | (input) 29 | (text "oscena" (rect 0 0 28 12)(font "Arial" (font_size 8))) 30 | (text "oscena" (rect 4 61 40 72)(font "Arial" (font_size 8))) 31 | (line (pt 0 72)(pt 48 72)(line_width 1)) 32 | ) 33 | (port 34 | (pt 160 72) 35 | (output) 36 | (text "clkout" (rect 0 0 22 12)(font "Arial" (font_size 8))) 37 | (text "clkout" (rect 130 61 166 72)(font "Arial" (font_size 8))) 38 | (line (pt 160 72)(pt 112 72)(line_width 1)) 39 | ) 40 | (drawing 41 | (text "clkout" (rect 113 43 262 99)(font "Arial" (color 128 0 0)(font_size 9))) 42 | (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) 43 | (text "oscena" (rect 8 43 52 99)(font "Arial" (color 128 0 0)(font_size 9))) 44 | (text "oscena" (rect 53 67 142 144)(font "Arial" (color 0 0 0))) 45 | (text " int_osc " (rect 126 88 306 186)(font "Arial" )) 46 | (line (pt 48 32)(pt 112 32)(line_width 1)) 47 | (line (pt 112 32)(pt 112 88)(line_width 1)) 48 | (line (pt 48 88)(pt 112 88)(line_width 1)) 49 | (line (pt 48 32)(pt 48 88)(line_width 1)) 50 | (line (pt 111 52)(pt 111 76)(line_width 1)) 51 | (line (pt 110 52)(pt 110 76)(line_width 1)) 52 | (line (pt 49 52)(pt 49 76)(line_width 1)) 53 | (line (pt 50 52)(pt 50 76)(line_width 1)) 54 | (line (pt 0 0)(pt 160 0)(line_width 1)) 55 | (line (pt 160 0)(pt 160 104)(line_width 1)) 56 | (line (pt 0 104)(pt 160 104)(line_width 1)) 57 | (line (pt 0 0)(pt 0 104)(line_width 1)) 58 | ) 59 | ) 60 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.cmp: -------------------------------------------------------------------------------- 1 | component int_osc is 2 | port ( 3 | clkout : out std_logic; -- clk 4 | oscena : in std_logic := 'X' -- oscena 5 | ); 6 | end component int_osc; 7 | 8 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.csv: -------------------------------------------------------------------------------- 1 | # system info int_osc on 2018.02.21.14:48:30 2 | system_info: 3 | name,value 4 | DEVICE,10M08SAU169C8G 5 | DEVICE_FAMILY,MAX 10 6 | GENERATION_ID,1519246110 7 | # 8 | # 9 | # Files generated for int_osc on 2018.02.21.14:48:30 10 | files: 11 | filepath,kind,attributes,module,is_top 12 | simulation/int_osc.v,VERILOG,,int_osc,true 13 | simulation/submodules/altera_int_osc.v,VERILOG,,altera_int_osc,false 14 | simulation/submodules/altera_int_osc.sdc,SDC,,altera_int_osc,false 15 | # 16 | # Map from instance-path to kind of module 17 | instances: 18 | instancePath,module 19 | int_osc.int_osc_0,altera_int_osc 20 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | datasheet for int_osc 6 | 57 | 58 | 59 | 60 | 61 | 62 | 66 | 67 |
int_osc 63 |
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2018.02.21.14:48:32Datasheet
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Overview
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Memory Map
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int_osc_0

altera_int_osc v17.1 99 |
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Parameters

106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 |
INFORMATIONThe output frequency for 10M02, 10M04, 10M08, 10M16, and 10M25 devices is 55~116MHz <br>The output frequency for 10M40, and 10M50 devices is 35~77MHz <br>
DEVICE_FAMILYMAX10FPGA
PART_NAME10M08SAU169C8G
DEVICE_ID08
CLOCK_FREQUENCY_1116
CLOCK_FREQUENCY_277
CLOCK_FREQUENCY116
CBX_AUTO_BLACKBOXALL
deviceFamilyUNKNOWN
generateLegacySimfalse
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Software Assignments

(none)
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generation took 0.00 secondsrendering took 0.01 seconds
164 | 165 | 166 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.ppf: -------------------------------------------------------------------------------- 1 | 2 | 7 | 8 | 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.spd: -------------------------------------------------------------------------------- 1 | 2 | 3 | 7 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc.xml: -------------------------------------------------------------------------------- 1 | 2 | 5 | 6 | 12 | 18 | 24 | 30 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 66 | 67 | 68 | 72 | 76 | 77 | 78 | 80 | 81 | 82 | 84 | 85 | 86 | queue size: 0 starting:int_osc "int_osc" 87 | 88 | 89 | 90 | Transform: CustomInstructionTransform 91 | No custom instruction connections, skipping transform 92 | 1 modules, 0 connections]]> 93 | Transform: MMTransform 94 | Transform: InterruptMapperTransform 95 | Transform: InterruptSyncTransform 96 | Transform: InterruptFanoutTransform 97 | Transform: AvalonStreamingTransform 98 | Transform: ResetAdaptation 99 | int_osc" reuses altera_int_osc "submodules/altera_int_osc"]]> 100 | queue size: 0 starting:altera_int_osc "submodules/altera_int_osc" 101 | Generating top-level entity altera_int_osc. 102 | int_osc" instantiated altera_int_osc "int_osc_0"]]> 103 | 104 | 105 | 112 | 113 | 114 | 115 | 116 | 119 | 120 | 121 | 122 | 123 | 127 | 131 | 132 | 133 | 134 | 136 | 137 | 138 | 139 | 140 | queue size: 0 starting:altera_int_osc "submodules/altera_int_osc" 141 | Generating top-level entity altera_int_osc. 142 | int_osc" instantiated altera_int_osc "int_osc_0"]]> 143 | 144 | 145 | 146 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc_bb.v: -------------------------------------------------------------------------------- 1 | 2 | module int_osc ( 3 | oscena, 4 | clkout); 5 | 6 | input oscena; 7 | output clkout; 8 | endmodule 9 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc_generation.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create simulation model 2 | Info: qsys-generate /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc.qsys --simulation=VERILOG --allow-mixed-language-simulation --output-directory=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation --family="MAX 10" --part=10M08SAU169C8G 3 | Progress: Loading int_osc/int_osc.qsys 4 | Progress: Reading input file 5 | Progress: Adding int_osc_0 [altera_int_osc 17.1] 6 | Progress: Parameterizing module int_osc_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | Info: int_osc: Generating int_osc "int_osc" for SIM_VERILOG 12 | Info: int_osc_0: Generating top-level entity altera_int_osc. 13 | Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0" 14 | Info: int_osc: Done "int_osc" with 2 modules, 3 files 15 | Info: qsys-generate succeeded. 16 | Info: Finished: Create simulation model 17 | Info: Starting: Create Modelsim Project. 18 | Info: sim-script-gen --spd=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/int_osc.spd --output-directory=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ --use-relative-paths=true 19 | Info: Doing: ip-make-simscript --spd=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/int_osc.spd --output-directory=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ --use-relative-paths=true 20 | Info: Generating the following file(s) for MODELSIM simulator in /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 21 | Info: mentor/msim_setup.tcl 22 | Info: Generating the following file(s) for VCS simulator in /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 23 | Info: synopsys/vcs/vcs_setup.sh 24 | Info: Generating the following file(s) for VCSMX simulator in /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 25 | Info: synopsys/vcsmx/synopsys_sim.setup 26 | Info: synopsys/vcsmx/vcsmx_setup.sh 27 | Info: Generating the following file(s) for NCSIM simulator in /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 28 | Info: cadence/cds.lib 29 | Info: cadence/hdl.var 30 | Info: cadence/ncsim_setup.sh 31 | Info: 1 .cds.lib files in cadence/cds_libs/ directory 32 | Info: Generating the following file(s) for RIVIERA simulator in /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 33 | Info: aldec/rivierapro_setup.tcl 34 | Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/simulation/. 35 | Info: Regenerate these scripts whenever you make any change to any Quartus-generated IP in your project. 36 | Info: Finished: Create Modelsim Project. 37 | Info: Starting: Create block symbol file (.bsf) 38 | Info: qsys-generate /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc.qsys --block-symbol-file --output-directory=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc --family="MAX 10" --part=10M08SAU169C8G 39 | Progress: Loading int_osc/int_osc.qsys 40 | Progress: Reading input file 41 | Progress: Adding int_osc_0 [altera_int_osc 17.1] 42 | Progress: Parameterizing module int_osc_0 43 | Progress: Building connections 44 | Progress: Parameterizing connections 45 | Progress: Validating 46 | Progress: Done reading input file 47 | Info: qsys-generate succeeded. 48 | Info: Finished: Create block symbol file (.bsf) 49 | Info: 50 | Info: Starting: Create HDL design files for synthesis 51 | Info: qsys-generate /scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc.qsys --synthesis=VERILOG --output-directory=/scratch/u/steve/r7107/view_current/trunk/atmega328clone/ip/int_osc/int_osc/synthesis --family="MAX 10" --part=10M08SAU169C8G 52 | Progress: Loading int_osc/int_osc.qsys 53 | Progress: Reading input file 54 | Progress: Adding int_osc_0 [altera_int_osc 17.1] 55 | Progress: Parameterizing module int_osc_0 56 | Progress: Building connections 57 | Progress: Parameterizing connections 58 | Progress: Validating 59 | Progress: Done reading input file 60 | Info: int_osc: Generating int_osc "int_osc" for QUARTUS_SYNTH 61 | Info: int_osc_0: Generating top-level entity altera_int_osc. 62 | Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0" 63 | Info: int_osc: Done "int_osc" with 2 modules, 3 files 64 | Info: qsys-generate succeeded. 65 | Info: Finished: Create HDL design files for synthesis 66 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc_generation_previous.rpt: -------------------------------------------------------------------------------- 1 | Info: Starting: Create simulation model 2 | Info: qsys-generate /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc.qsys --simulation=VERILOG --output-directory=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation --family="MAX 10" --part=10M08SAU169C8G 3 | Progress: Loading int_osc/int_osc.qsys 4 | Progress: Reading input file 5 | Progress: Adding int_osc_0 [altera_int_osc 15.1] 6 | Progress: Parameterizing module int_osc_0 7 | Progress: Building connections 8 | Progress: Parameterizing connections 9 | Progress: Validating 10 | Progress: Done reading input file 11 | Info: int_osc: Generating int_osc "int_osc" for SIM_VERILOG 12 | Info: int_osc_0: Generating top-level entity altera_int_osc. 13 | Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0" 14 | Info: int_osc: Done "int_osc" with 2 modules, 3 files 15 | Info: qsys-generate succeeded. 16 | Info: Finished: Create simulation model 17 | Info: Starting: Create Modelsim Project. 18 | Info: sim-script-gen --spd=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/int_osc.spd --output-directory=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ --use-relative-paths=true 19 | Info: Doing: ip-make-simscript --spd=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/int_osc.spd --output-directory=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ --use-relative-paths=true 20 | Info: Generating the following file(s) for MODELSIM simulator in /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 21 | Info: mentor/msim_setup.tcl 22 | Info: Generating the following file(s) for VCS simulator in /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 23 | Info: synopsys/vcs/vcs_setup.sh 24 | Info: Generating the following file(s) for VCSMX simulator in /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 25 | Info: synopsys/vcsmx/synopsys_sim.setup 26 | Info: synopsys/vcsmx/vcsmx_setup.sh 27 | Info: Generating the following file(s) for NCSIM simulator in /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 28 | Info: cadence/cds.lib 29 | Info: cadence/hdl.var 30 | Info: cadence/ncsim_setup.sh 31 | Info: 1 .cds.lib files in cadence/cds_libs/ directory 32 | Info: Generating the following file(s) for RIVIERA simulator in /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/ directory: 33 | Info: aldec/rivierapro_setup.tcl 34 | Info: For information on how to simulate your IP, see the explanatory comments in the simulator-specific subdirectories under /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/simulation/. 35 | Info: Finished: Create Modelsim Project. 36 | Info: 37 | Info: Starting: Create HDL design files for synthesis 38 | Info: qsys-generate /pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc.qsys --synthesis=VERILOG --output-directory=/pro/r7107/work/matt/trunk/atmega328clone/ip/int_osc/int_osc/synthesis --family="MAX 10" --part=10M08SAU169C8G 39 | Progress: Loading int_osc/int_osc.qsys 40 | Progress: Reading input file 41 | Progress: Adding int_osc_0 [altera_int_osc 15.1] 42 | Progress: Parameterizing module int_osc_0 43 | Progress: Building connections 44 | Progress: Parameterizing connections 45 | Progress: Validating 46 | Progress: Done reading input file 47 | Info: int_osc: Generating int_osc "int_osc" for QUARTUS_SYNTH 48 | Info: int_osc_0: Generating top-level entity altera_int_osc. 49 | Info: int_osc_0: "int_osc" instantiated altera_int_osc "int_osc_0" 50 | Info: int_osc: Done "int_osc" with 2 modules, 3 files 51 | Info: qsys-generate succeeded. 52 | Info: Finished: Create HDL design files for synthesis 53 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc_inst.v: -------------------------------------------------------------------------------- 1 | int_osc u0 ( 2 | .oscena (), // oscena.oscena 3 | .clkout () // clkout.clk 4 | ); 5 | 6 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/int_osc_inst.vhd: -------------------------------------------------------------------------------- 1 | component int_osc is 2 | port ( 3 | oscena : in std_logic := 'X'; -- oscena 4 | clkout : out std_logic -- clk 5 | ); 6 | end component int_osc; 7 | 8 | u0 : component int_osc 9 | port map ( 10 | oscena => CONNECTED_TO_oscena, -- oscena.oscena 11 | clkout => CONNECTED_TO_clkout -- clkout.clk 12 | ); 13 | 14 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/cadence/cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./libraries/work/ 12 | DEFINE int_osc_0 ./libraries/int_osc_0/ 13 | DEFINE altera_ver ./libraries/altera_ver/ 14 | DEFINE lpm_ver ./libraries/lpm_ver/ 15 | DEFINE sgate_ver ./libraries/sgate_ver/ 16 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/ 17 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/ 18 | DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/ 19 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/cadence/cds_libs/int_osc_0.cds.lib: -------------------------------------------------------------------------------- 1 | 2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/ 3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/ 4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/ 5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/ 6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/ 7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/ 8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/ 9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/ 10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/ 11 | DEFINE work ./../libraries/work/ 12 | DEFINE altera_ver ./../libraries/altera_ver/ 13 | DEFINE lpm_ver ./../libraries/lpm_ver/ 14 | DEFINE sgate_ver ./../libraries/sgate_ver/ 15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/ 16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/ 17 | DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/ 18 | DEFINE int_osc_0 ./../libraries/int_osc_0/ 19 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/cadence/hdl.var: -------------------------------------------------------------------------------- 1 | 2 | DEFINE WORK work 3 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/int_osc.sip: -------------------------------------------------------------------------------- 1 | set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_NAME "Qsys" 2 | set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_VERSION "17.1" 3 | set_global_assignment -entity "int_osc" -library "lib_int_osc" -name IP_TOOL_ENV "Qsys" 4 | set_global_assignment -library "lib_int_osc" -name SPD_FILE [file join $::quartus(sip_path) "../int_osc.spd"] 5 | set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "../../int_osc.qsys"] 6 | 7 | set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "int_osc.v"] 8 | set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_int_osc.v"] 9 | set_global_assignment -library "lib_int_osc" -name MISC_FILE [file join $::quartus(sip_path) "submodules/altera_int_osc.sdc"] 10 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/int_osc.v: -------------------------------------------------------------------------------- 1 | // int_osc.v 2 | 3 | // Generated using ACDS version 17.1 590 4 | 5 | `timescale 1 ps / 1 ps 6 | module int_osc ( 7 | output wire clkout, // clkout.clk 8 | input wire oscena // oscena.oscena 9 | ); 10 | 11 | altera_int_osc #( 12 | .DEVICE_FAMILY ("MAX 10"), 13 | .DEVICE_ID ("08"), 14 | .CLOCK_FREQUENCY ("116") 15 | ) int_osc_0 ( 16 | .oscena (oscena), // oscena.oscena 17 | .clkout (clkout) // clkout.clk 18 | ); 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/submodules/altera_int_osc.sdc: -------------------------------------------------------------------------------- 1 | # (C) 2001-2017 Intel Corporation. All rights reserved. 2 | # Your use of Intel Corporation's design tools, logic functions and other 3 | # software and tools, and its AMPP partner logic functions, and any output 4 | # files from any of the foregoing (including device programming or simulation 5 | # files), and any associated documentation or information are expressly subject 6 | # to the terms and conditions of the Intel Program License Subscription 7 | # Agreement, Intel FPGA IP License Agreement, or other applicable 8 | # license agreement, including, without limitation, that your use is for the 9 | # sole purpose of programming logic devices manufactured by Intel and sold by 10 | # Intel or its authorized distributors. Please refer to the applicable 11 | # agreement for further details. 12 | 13 | 14 | # Create clock for internal oscillator clock 15 | create_clock -name int_osc_clk -period 8.62 [get_pins -compatibility_mode {*oscillator_dut|clkout}] 16 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/submodules/altera_int_osc.v: -------------------------------------------------------------------------------- 1 | // (C) 2001-2017 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions and other 3 | // software and tools, and its AMPP partner logic functions, and any output 4 | // files from any of the foregoing (including device programming or simulation 5 | // files), and any associated documentation or information are expressly subject 6 | // to the terms and conditions of the Intel Program License Subscription 7 | // Agreement, Intel FPGA IP License Agreement, or other applicable 8 | // license agreement, including, without limitation, that your use is for the 9 | // sole purpose of programming logic devices manufactured by Intel and sold by 10 | // Intel or its authorized distributors. Please refer to the applicable 11 | // agreement for further details. 12 | 13 | 14 | //////////////////////////////////////////////////////////////////// 15 | // 16 | // ALTERA_INT_OSC 17 | // 18 | // Copyright (C) 1991-2013 Altera Corporation 19 | // Your use of Altera Corporation's design tools, logic functions 20 | // and other software and tools, and its AMPP partner logic 21 | // functions, and any output files from any of the foregoing 22 | // (including device programming or simulation files), and any 23 | // associated documentation or information are expressly subject 24 | // to the terms and conditions of the Altera Program License 25 | // Subscription Agreement, Altera MegaCore Function License 26 | // Agreement, or other applicable license agreement, including, 27 | // without limitation, that your use is for the sole purpose of 28 | // programming logic devices manufactured by Altera and sold by 29 | // Altera or its authorized distributors. Please refer to the 30 | // applicable agreement for further details. 31 | // 32 | //////////////////////////////////////////////////////////////////// 33 | 34 | // synthesis VERILOG_INPUT_VERSION VERILOG_2001 35 | 36 | `timescale 1 ps / 1 ps 37 | 38 | module altera_int_osc 39 | ( 40 | clkout, 41 | oscena); 42 | 43 | parameter DEVICE_FAMILY = "MAX 10"; 44 | parameter DEVICE_ID = "08"; 45 | parameter CLOCK_FREQUENCY = "dummy"; 46 | 47 | output clkout; 48 | input oscena; 49 | 50 | wire wire_clkout; 51 | 52 | assign clkout = wire_clkout; 53 | 54 | // ------------------------------------------------------------------- 55 | // Instantiate wysiwyg for chipidblock according to device family 56 | // ------------------------------------------------------------------- 57 | generate 58 | if (DEVICE_FAMILY == "MAX 10") begin 59 | fiftyfivenm_oscillator # ( //MAX 10 60 | .device_id(DEVICE_ID), 61 | .clock_frequency(CLOCK_FREQUENCY) 62 | ) oscillator_dut ( 63 | .clkout(wire_clkout), 64 | .clkout1(), 65 | .oscena(oscena)); 66 | end 67 | endgenerate 68 | 69 | endmodule //altera_int_osc 70 | //VALID FILE 71 | -------------------------------------------------------------------------------- /extras/rtl/ip/int_osc/int_osc/simulation/synopsys/vcs/vcs_setup.sh: -------------------------------------------------------------------------------- 1 | 2 | # (C) 2001-2018 Altera Corporation. All rights reserved. 3 | # Your use of Altera Corporation's design tools, logic functions and 4 | # other software and tools, and its AMPP partner logic functions, and 5 | # any output files any of the foregoing (including device programming 6 | # or simulation files), and any associated documentation or information 7 | # are expressly subject to the terms and conditions of the Altera 8 | # Program License Subscription Agreement, Altera MegaCore Function 9 | # License Agreement, or other applicable license agreement, including, 10 | # without limitation, that your use is for the sole purpose of 11 | # programming logic devices manufactured by Altera and sold by Altera 12 | # or its authorized distributors. Please refer to the applicable 13 | # agreement for further details. 14 | 15 | # ACDS 17.1 590 linux 2018.02.21.14:48:31 16 | 17 | # ---------------------------------------- 18 | # vcs - auto-generated simulation script 19 | 20 | # ---------------------------------------- 21 | # This script provides commands to simulate the following IP detected in 22 | # your Quartus project: 23 | # int_osc 24 | # 25 | # Altera recommends that you source this Quartus-generated IP simulation 26 | # script from your own customized top-level script, and avoid editing this 27 | # generated script. 28 | # 29 | # To write a top-level shell script that compiles Altera simulation libraries 30 | # and the Quartus-generated IP in your project, along with your design and 31 | # testbench files, follow the guidelines below. 32 | # 33 | # 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section 34 | # below into a new file, e.g. named "vcs_sim.sh". 35 | # 36 | # 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into 37 | # a separate file, e.g. named "filelist.f". 38 | # 39 | # ---------------------------------------- 40 | # # TOP-LEVEL TEMPLATE - BEGIN 41 | # # 42 | # # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to 43 | # # set the top-level simulation or testbench module/entity name. 44 | # # 45 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to 46 | # # construct paths to the files required to simulate the IP in your Quartus 47 | # # project. By default, the IP script assumes that you are launching the 48 | # # simulator from the IP script location. If launching from another 49 | # # location, set QSYS_SIMDIR to the output directory you specified when you 50 | # # generated the IP script, relative to the directory from which you launch 51 | # # the simulator. 52 | # # 53 | # # Source the Quartus-generated IP simulation script and do the following: 54 | # # - Compile the Quartus EDA simulation library and IP simulation files. 55 | # # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR. 56 | # # - Compile the design and top-level simulation module/entity using 57 | # # information specified in "filelist.f". 58 | # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run 59 | # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="". 60 | # # - Run the simulation. 61 | # # 62 | # source