├── .gitignore ├── CAN.qpf ├── CAN.qsf ├── CAN.qws ├── CAN_description.txt ├── Custom_Can └── simulation │ └── qsim │ ├── CAN.sft │ ├── CAN.vo │ └── CAN_modelsim.xrf ├── Waveform1.vwf ├── baud_rate.v ├── baud_rate.v.bak ├── can_clk.v ├── can_clk.v.bak ├── can_crc.v ├── can_crc.v.bak ├── can_rx.v ├── can_rx.v.bak ├── can_test.v ├── can_top.sdc ├── can_top.v ├── can_top.v.bak ├── can_top_inst.v ├── can_tx.v ├── can_tx.v.bak ├── db ├── .cmp.kpt ├── CAN.(0).cnf.cdb ├── CAN.(0).cnf.hdb ├── CAN.(1).cnf.cdb ├── CAN.(1).cnf.hdb ├── CAN.(10).cnf.cdb ├── CAN.(10).cnf.hdb ├── CAN.(2).cnf.cdb ├── CAN.(2).cnf.hdb ├── CAN.(3).cnf.cdb ├── CAN.(3).cnf.hdb ├── CAN.(4).cnf.cdb ├── CAN.(4).cnf.hdb ├── CAN.(5).cnf.cdb ├── CAN.(5).cnf.hdb ├── CAN.(6).cnf.cdb ├── CAN.(6).cnf.hdb ├── CAN.(7).cnf.cdb ├── CAN.(7).cnf.hdb ├── CAN.(8).cnf.cdb ├── CAN.(8).cnf.hdb ├── CAN.(9).cnf.cdb ├── CAN.(9).cnf.hdb ├── CAN.ace_cmp.bpm ├── CAN.ace_cmp.cdb ├── CAN.ace_cmp.hdb ├── CAN.ae.hdb ├── CAN.asm.qmsg ├── CAN.asm.rdb ├── CAN.asm_labs.ddb ├── CAN.cbx.xml ├── CAN.cmp.bpm ├── CAN.cmp.cdb ├── CAN.cmp.hdb ├── CAN.cmp.idb ├── CAN.cmp.logdb ├── CAN.cmp.rdb ├── CAN.cmp_merge.kpt ├── CAN.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd ├── CAN.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd ├── CAN.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd ├── CAN.db_info ├── CAN.eco.cdb ├── CAN.eda.qmsg ├── CAN.fit.qmsg ├── CAN.hier_info ├── CAN.hif ├── CAN.lpc.html ├── CAN.lpc.rdb ├── CAN.lpc.txt ├── CAN.map.ammdb ├── CAN.map.bpm ├── CAN.map.cdb ├── CAN.map.hdb ├── CAN.map.kpt ├── CAN.map.logdb ├── CAN.map.qmsg ├── CAN.map.rdb ├── CAN.map_bb.cdb ├── CAN.map_bb.hdb ├── CAN.map_bb.logdb ├── CAN.pplq.rdb ├── CAN.pre_map.cdb ├── CAN.pre_map.hdb ├── CAN.root_partition.map.reg_db.cdb ├── CAN.routing.rdb ├── CAN.rtlv.hdb ├── CAN.rtlv_sg.cdb ├── CAN.rtlv_sg_swap.cdb ├── CAN.sld_design_entry.sci ├── CAN.sld_design_entry_dsc.sci ├── CAN.smart_action.txt ├── CAN.smp_dump.txt ├── CAN.sta.qmsg ├── CAN.sta.rdb ├── CAN.sta_cmp.8_slow_1200mv_85c.tdb ├── CAN.tis_db_list.ddb ├── CAN.tiscmp.fast_1200mv_0c.ddb ├── CAN.tiscmp.fastest_slow_1200mv_0c.ddb ├── CAN.tiscmp.fastest_slow_1200mv_85c.ddb ├── CAN.tiscmp.slow_1200mv_0c.ddb ├── CAN.tiscmp.slow_1200mv_85c.ddb ├── CAN.vpr.ammdb ├── CAN_partition_pins.json └── prev_cmp_CAN.qmsg ├── incremental_db ├── README └── compiled_partitions │ ├── CAN.db_info │ ├── CAN.root_partition.cmp.ammdb │ ├── CAN.root_partition.cmp.cdb │ ├── CAN.root_partition.cmp.dfp │ ├── CAN.root_partition.cmp.hdb │ ├── CAN.root_partition.cmp.logdb │ ├── CAN.root_partition.cmp.rcfdb │ ├── CAN.root_partition.map.cdb │ ├── CAN.root_partition.map.dpi │ ├── CAN.root_partition.map.hbdb.cdb │ ├── CAN.root_partition.map.hbdb.hb_info │ ├── CAN.root_partition.map.hbdb.hdb │ ├── CAN.root_partition.map.hbdb.sig │ ├── CAN.root_partition.map.hdb │ ├── CAN.root_partition.map.kpt │ └── CAN.rrp.hdb ├── output_files ├── CAN.asm.rpt ├── CAN.cdf ├── CAN.done ├── CAN.eda.rpt ├── CAN.fit.rpt ├── CAN.fit.smsg ├── CAN.fit.summary ├── CAN.flow.rpt ├── CAN.jdi ├── CAN.map.rpt ├── CAN.map.smsg ├── CAN.map.summary ├── CAN.pin ├── CAN.sld ├── CAN.sof ├── CAN.sta.rpt └── CAN.sta.summary ├── pmramif.v └── simulation └── qsim ├── .gitignore ├── CAN.do ├── CAN.msim.vcd ├── CAN.sft ├── CAN.vo ├── CAN_modelsim.xrf ├── Waveform.vwf.vt ├── Waveform1.vwf.vt ├── transcript ├── vwf_sim_transcript └── work ├── _info ├── _lib.qdb ├── _lib1_115.qdb ├── _lib1_115.qpg ├── _lib1_115.qtl └── _vmake /.gitignore: -------------------------------------------------------------------------------- 1 | *.bak -------------------------------------------------------------------------------- /CAN.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 22 | # Date created = 16:41:34 September 25, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | 26 | QUARTUS_VERSION = "20.1" 27 | DATE = "16:41:34 September 25, 2020" 28 | 29 | # Revisions 30 | 31 | PROJECT_REVISION = "CAN" 32 | -------------------------------------------------------------------------------- /CAN.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2020 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and any partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details, at 16 | # https://fpgasoftware.intel.com/eula. 17 | # 18 | # -------------------------------------------------------------------------- # 19 | # 20 | # Quartus Prime 21 | # Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 22 | # Date created = 16:41:34 September 25, 2020 23 | # 24 | # -------------------------------------------------------------------------- # 25 | # 26 | # Notes: 27 | # 28 | # 1) The default values for assignments are stored in the file: 29 | # CAN_assignment_defaults.qdf 30 | # If this file doesn't exist, see file: 31 | # assignment_defaults.qdf 32 | # 33 | # 2) Altera recommends that you do not modify this file. This 34 | # file is updated automatically by the Quartus Prime software 35 | # and any changes you make may be lost or overwritten. 36 | # 37 | # -------------------------------------------------------------------------- # 38 | 39 | 40 | set_global_assignment -name FAMILY "Cyclone IV E" 41 | set_global_assignment -name DEVICE EP4CE6E22C8 42 | set_global_assignment -name TOP_LEVEL_ENTITY can_test 43 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0 44 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:41:34 SEPTEMBER 25, 2020" 45 | set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition" 46 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 47 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 48 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 49 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 50 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 51 | set_global_assignment -name VERILOG_FILE can_top.v 52 | set_global_assignment -name VERILOG_FILE baud_rate.v 53 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf 54 | set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf 55 | set_global_assignment -name VERILOG_FILE can_tx.v 56 | set_global_assignment -name VERILOG_FILE output_files/can_rx.v 57 | set_location_assignment PIN_23 -to clk_i 58 | set_location_assignment PIN_25 -to rst_i 59 | set_location_assignment PIN_28 -to tx_o 60 | set_global_assignment -name VERILOG_FILE can_crc.v 61 | set_global_assignment -name VERILOG_FILE can_clk.v 62 | set_location_assignment PIN_31 -to test_rx_rx 63 | set_location_assignment PIN_30 -to rx_i 64 | set_location_assignment PIN_33 -to test_sample 65 | set_global_assignment -name VERILOG_FILE can_rx.v 66 | set_location_assignment PIN_32 -to rx_busy 67 | set_global_assignment -name VERILOG_FILE can_test.v 68 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 69 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 70 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to tx_o 72 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rst_i 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk_i 74 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to test_rx_rx 75 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rx_i 76 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_sample 77 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to rx_busy 78 | set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to test_clk_can 79 | set_global_assignment -name VERILOG_FILE pmramif.v 80 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /CAN.qws: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/CAN.qws -------------------------------------------------------------------------------- /CAN_description.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/CAN_description.txt -------------------------------------------------------------------------------- /Custom_Can/simulation/qsim/CAN.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | -------------------------------------------------------------------------------- /baud_rate.v: -------------------------------------------------------------------------------- 1 | module baud_rate 2 | #( 3 | parameter FREQ_I = 50_000_000, 4 | parameter FREQ_O = 50_000, 5 | 6 | parameter END_COUNT = FREQ_I/(FREQ_O*2) - 1 7 | )( 8 | input rst_i, 9 | input clk_i, 10 | 11 | output baud_clk_o 12 | ); 13 | 14 | 15 | reg baud_clk_o_reg = 1'b0; 16 | reg [9:0] count = 10'd0; 17 | 18 | assign baud_clk_o = baud_clk_o_reg; 19 | 20 | always @(posedge clk_i) begin 21 | if (rst_i == 1) begin 22 | count <= 10'd0; 23 | end 24 | else if (count == END_COUNT) begin 25 | count <= 10'd0; 26 | baud_clk_o_reg <= ~baud_clk_o_reg; 27 | end else begin 28 | count <= count + 10'd1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /baud_rate.v.bak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/baud_rate.v.bak -------------------------------------------------------------------------------- /can_clk.v: -------------------------------------------------------------------------------- 1 | module can_clk 2 | #( 3 | parameter FREQ_I = 50_000_000, 4 | parameter FREQ_O = 1_000_000, 5 | parameter END_COUNT = FREQ_I/(FREQ_O*2) - 1 6 | )( 7 | input rst_i, 8 | input clk_i, 9 | input sync_i, 10 | 11 | output can_clk_o 12 | ); 13 | 14 | reg [11:0] count; 15 | reg can_clk_o_reg; 16 | 17 | assign can_clk_o = can_clk_o_reg; 18 | 19 | always @( posedge clk_i or negedge rst_i ) begin 20 | if ( rst_i == 1'b0 ) begin 21 | can_clk_o_reg <= 1'b1; 22 | count <= 12'd0; 23 | end else begin 24 | if ( sync_i ) begin 25 | count <= 12'd0; 26 | can_clk_o_reg <= 1'b1; 27 | end else if ( count == END_COUNT ) begin 28 | count <= 12'd0; 29 | can_clk_o_reg <= ~can_clk_o_reg; 30 | end else begin 31 | count <= count + 1'b1; 32 | end 33 | end 34 | end 35 | 36 | endmodule -------------------------------------------------------------------------------- /can_clk.v.bak: -------------------------------------------------------------------------------- 1 | module can_clk 2 | #( 3 | parameter FREQ_I = 50_000_000, 4 | parameter FREQ_O = 50_000, 5 | 6 | parameter END_COUNT = FREQ_I/(FREQ_O*2) - 1 7 | )( 8 | input rst_i, 9 | input clk_i, 10 | 11 | output baud_clk_o 12 | ); 13 | 14 | 15 | reg baud_clk_o_reg = 1'b0; 16 | reg [9:0] count = 10'd0; 17 | 18 | assign baud_clk_o = baud_clk_o_reg; 19 | 20 | always @(posedge clk_i) begin 21 | if (rst_i == 1) begin 22 | count <= 10'd0; 23 | end 24 | else if (count == END_COUNT) begin 25 | count <= 10'd0; 26 | baud_clk_o_reg <= ~baud_clk_o_reg; 27 | end else begin 28 | count <= count + 10'd1; 29 | end 30 | end 31 | 32 | endmodule -------------------------------------------------------------------------------- /can_crc.v: -------------------------------------------------------------------------------- 1 | module can_crc 2 | ( 3 | input crc_clk_i, 4 | input rst_i, 5 | input en_i, 6 | input data_i, 7 | input crc_rst_i, 8 | output reg [14:0] crc_reg_o 9 | 10 | ); 11 | 12 | wire crc_next; 13 | wire [14:0] crc_tmp; 14 | assign crc_next = data_i ^ crc_reg_o[14]; 15 | assign crc_tmp = {crc_reg_o[13:0], 1'b0}; 16 | 17 | always @( posedge crc_clk_i or negedge rst_i or posedge crc_rst_i ) begin 18 | if ( rst_i == 1'b0 || crc_rst_i == 1'b1 ) begin 19 | crc_reg_o <= 15'h0; 20 | end else begin 21 | if ( en_i ) begin 22 | if ( crc_next ) begin 23 | crc_reg_o <= crc_tmp ^ 15'h4599; 24 | end else begin 25 | crc_reg_o <= crc_tmp; 26 | end 27 | end 28 | end 29 | end 30 | 31 | endmodule -------------------------------------------------------------------------------- /can_crc.v.bak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/can_crc.v.bak -------------------------------------------------------------------------------- /can_test.v: -------------------------------------------------------------------------------- 1 | module can_test 2 | ( 3 | input clk_i, 4 | input rx_i, 5 | input rst_i, 6 | output tx_o, 7 | 8 | output tx_busy, 9 | output rx_busy, 10 | 11 | 12 | output test_rx_rx, 13 | output test_sample 14 | 15 | ); 16 | 17 | reg tx_send = 1'b1; 18 | 19 | reg [63:0] tx_data = 64'b0011000100110010001100110011010000110101001101100011011100111000; 20 | 21 | 22 | can_top can_top_inst 23 | ( 24 | .rst_i (rst_i), 25 | .clk_i (clk_i), 26 | 27 | .rx_i (rx_i), 28 | .rx_busy (rx_busy), 29 | 30 | .tx_o (tx_o), 31 | .tx_busy (tx_busy), 32 | .tx_send_i (1'b1), 33 | 34 | 35 | .tx_data_i (tx_data), 36 | 37 | 38 | .data_wr (data_wr), 39 | .addr_wr (addr_wr), 40 | .wr_en (wr_en), 41 | .wr_done (wr_done), 42 | .wr_busy (wr_busy) 43 | ); 44 | 45 | localparam addr_width = 20; 46 | localparam data_width = 32; 47 | 48 | localparam [19:0] addr_data_send = 20'hA0001; 49 | localparam [19:0] addr_setting_send = 20'hA0002; 50 | 51 | 52 | PMRAMIF # ( 53 | .DATA_WIDTH (data_width), 54 | .ADDR_WIDTH (addr_width), 55 | .CLK_FREQUENCY (50_000_000), 56 | .OP_CYCLE_NS (35) 57 | ) PMRAMIF_inst 58 | ( 59 | .clk (clk_i), 60 | .rst (rst_i), 61 | 62 | .data_wr (), 63 | .addr_wr (), 64 | .wr_en (), 65 | .wr_done (), 66 | .wr_busy (), 67 | 68 | .data_rd (), 69 | .addr_rd (), 70 | .rd_en (), 71 | .rd_done (), 72 | .rd_busy () 73 | ); 74 | 75 | endmodule 76 | 77 | -------------------------------------------------------------------------------- /can_top.sdc: -------------------------------------------------------------------------------- 1 | create_clock -period 20.000 -name osc_clk osc_clk 2 | derrive_pll_clocks 3 | derrive_clock_uncertainty 4 | set_false_path -from {get_ports button[0]} 5 | set_false_path -to {get_ports led*} -------------------------------------------------------------------------------- /can_top.v: -------------------------------------------------------------------------------- 1 | // Extended CAN format 2 | // 1(SOF)+11(Arb1)+2(SRR,IDE)+11(Arb2)+1(RTR)+1(r1)+1(r0)+4(Control)+64(Data)+15(CRC Field)+1(CRC Delimeter)+2(Ack)+7(EoF)+3(Idle) 3 | module can_top 4 | #( 5 | parameter CLK_FREQ = 50_000_000, 6 | parameter CAN_CLK_FREQ = 100_000, 7 | 8 | // DMA 9 | parameter DATA_WIDTH = 32, 10 | parameter ADDR_WIDTH = 20, 11 | parameter CLK_FREQUENCY = 200_000_000, 12 | parameter OP_CYCLE_NS = 35, 13 | 14 | // 15 | parameter [5:0] LOCAL_ADDRESS = 6'b000101, 16 | 17 | parameter [19:0] ADDR_SETTING_SEND = 20'hA0001, 18 | parameter [19:0] ADDR_DATA_SEND_1 = 20'hA0002, 19 | parameter [19:0] ADDR_DATA_SEND_2 = 20'hA0003, 20 | 21 | parameter [19:0] addr_setting_recieved = 20'hB0001, 22 | parameter [19:0] addr_data_recieved_1 = 20'hB0002, 23 | parameter [19:0] addr_data_recieved_2 = 20'hB0003 24 | )( 25 | input rst_i, 26 | input clk_i, 27 | 28 | input rx_i, 29 | output rx_busy, 30 | output rx_received, 31 | 32 | output tx_o, 33 | output tx_busy, 34 | input tx_send_i, 35 | 36 | // 37 | output reg [DATA_WIDTH-1 : 0] data_wr, 38 | output reg [ADDR_WIDTH-1 : 0] addr_wr, 39 | output reg wr_en, 40 | input wr_done, 41 | input wr_busy, 42 | 43 | input [DATA_WIDTH-1 : 0] data_rd, 44 | output reg [ADDR_WIDTH-1 : 0] addr_rd, 45 | output reg rd_en, 46 | input rd_done, 47 | input rd_busy, 48 | // 49 | 50 | // tx fields 51 | //input tx_message_type, 52 | //input [5:0] tx_address_remote, 53 | 54 | input [63:0] tx_data_i, 55 | 56 | // - output CAN frame LLC/DLC data 57 | 58 | // 59 | output test_clk_can, 60 | output [2:0] test_can_state, 61 | output [7:0] test_can_tx_state, 62 | output [7:0] test_bit_count, 63 | output [3:0] test_bit_pol_count, 64 | output reg bit_stuffed, 65 | output test_last_bit, 66 | 67 | output [7:0] test_rx_state, 68 | output [11:0] test_rx_quant_count, 69 | output [7:0] test_rx_bit_count, 70 | output [3:0] test_rx_bit_pol_count, 71 | output test_rx_bit_stuffed, 72 | output [6:0] test_rx_count, 73 | output test_rx_rx, 74 | output test_sample 75 | // 76 | ); 77 | 78 | // 79 | wire test_arbi; 80 | reg count_rst; 81 | assign test_sample = ( CAN_STATE == CAN_PAUSE ) ? 1'b0 : 1'b1; 82 | assign test_can_state = CAN_STATE; 83 | // 84 | 85 | wire clk_can; 86 | reg [63:0] data_to_send; 87 | 88 | // 89 | reg tx_message_type = 1'b0; 90 | reg [5:0] local_address = 6'b000101;//6'h2A; 91 | reg [5:0] remote_address = 6'b100010; 92 | reg [1:0] tx_handshake = 2'b10; 93 | reg [1:0] tx_atribute = 2'b10; 94 | reg [3:0] tx_expand_count = 4'b1011; 95 | reg [7:0] tx_cmd_data_sign = 8'b1111_0101; 96 | reg [3:0] tx_dlc = 4'b1001; 97 | 98 | reg [63:0] tx_data; 99 | reg [31:0] can_send_setting; 100 | // 101 | 102 | // 103 | reg [63:0] rx_data_reg; 104 | wire [63:0] rx_data; 105 | // 106 | 107 | reg tx_start; 108 | reg rx_start; 109 | reg tx_pending; 110 | reg init; 111 | 112 | wire tx_o_tx; 113 | wire tx_o_rx; 114 | 115 | wire frame_sent; 116 | wire can_is_free; 117 | wire rx_frame_ready; 118 | 119 | 120 | 121 | // 122 | assign tx_o = CAN_STATE == CAN_TX ? tx_o_tx : 123 | ( CAN_STATE == CAN_RX ? tx_o_rx : 1'b1 ); 124 | 125 | localparam CAN_START_INIT = 0; 126 | localparam CAN_INIT = 1; 127 | localparam CAN_IDLE = 2; 128 | localparam CAN_PAUSE = 3; 129 | localparam CAN_START_RX = 4; 130 | localparam CAN_RX = 5; 131 | localparam CAN_START_TX = 6; 132 | localparam CAN_TX = 7; 133 | localparam CAN_TEST_START = 8; 134 | localparam CAN_TEST = 9; 135 | 136 | reg [3:0] CAN_STATE; 137 | reg [10:0] count; 138 | 139 | always @( posedge clk_can or negedge rst_i ) begin 140 | if ( rst_i == 1'b0 ) begin 141 | 142 | end else begin 143 | if ( count_rst == 1'b1 ) begin 144 | count <= 11'd0; 145 | end else begin 146 | count <= count + 1'b1; 147 | end 148 | end 149 | end 150 | 151 | always @( posedge clk_i or negedge rst_i ) begin 152 | if ( rst_i == 1'b0 ) begin 153 | CAN_STATE <= CAN_IDLE; 154 | tx_start <= 1'b0; 155 | rx_start <= 1'b0; 156 | count_rst <= 1'b0; 157 | init <= 1'b0; 158 | end else begin 159 | case ( CAN_STATE ) 160 | CAN_START_INIT: begin 161 | init <= 1'b1; 162 | CAN_STATE <= CAN_INIT; 163 | end 164 | CAN_INIT: begin 165 | init <= 1'b0; 166 | CAN_STATE <= CAN_IDLE; 167 | end 168 | CAN_IDLE: begin 169 | if ( tx_pending == 1'b1 ) begin 170 | CAN_STATE <= CAN_START_TX; 171 | tx_start <= 1'b1; 172 | rx_start <= 1'b0; 173 | end else begin 174 | CAN_STATE <= CAN_START_RX; 175 | rx_start <= 1'b1; 176 | end 177 | end 178 | CAN_PAUSE: begin 179 | if ( tx_pending == 1'b1 ) begin 180 | if ( tx_lost_arbitrage == 1'b1 ) begin 181 | if ( count == 11'd11 ) begin 182 | count_rst <= 1'b1; 183 | CAN_STATE <= CAN_START_TX; 184 | end 185 | end else begin 186 | if ( count == 11'd2 ) begin 187 | count_rst <= 1'b1; 188 | CAN_STATE <= CAN_START_TX; 189 | end 190 | end 191 | end else begin 192 | if ( count == 11'd2 ) begin 193 | CAN_STATE <= CAN_START_RX; 194 | end 195 | end 196 | end 197 | CAN_START_RX: begin 198 | if ( rx_busy == 1'b1 ) begin 199 | CAN_STATE <= CAN_RX; 200 | end else begin 201 | CAN_STATE <= CAN_IDLE; 202 | end 203 | end 204 | CAN_RX: begin 205 | if ( rx_busy == 1'b0 ) begin 206 | rx_start <= 1'b0; 207 | count_rst <= 1'b0; 208 | CAN_STATE <= CAN_PAUSE; 209 | end 210 | end 211 | CAN_START_TX: begin 212 | if ( tx_busy == 1'b1 ) begin 213 | CAN_STATE <= CAN_TX; 214 | end 215 | end 216 | CAN_TX: begin 217 | if ( frame_sent == 1'b1 ) begin 218 | tx_start <= 1'b0; 219 | count_rst <= 1'b1; 220 | CAN_STATE <= CAN_PAUSE; 221 | end 222 | end 223 | CAN_TEST_START: begin 224 | tx_start <= 1'b1; 225 | if ( rx_busy == 1'b1 ) begin 226 | CAN_STATE <= CAN_TEST; 227 | end 228 | end 229 | CAN_TEST: begin 230 | tx_start <= 1'b0; 231 | if ( rx_busy == 0 ) begin 232 | rx_start <= 1'b0; 233 | end 234 | end 235 | endcase 236 | end 237 | end 238 | // 239 | 240 | // 241 | localparam TX_READ_IDLE = 0; 242 | localparam TX_START_READ_SETTING = 1; 243 | localparam TX_READ_SETTING = 2; 244 | localparam TX_START_READ_DATA_1 = 3; 245 | localparam TX_READ_DATA_1 = 4; 246 | localparam TX_START_READ_DATA_2 = 5; 247 | localparam TX_READ_DATA_2 = 6; 248 | localparam TX_START_SEND_DATA = 7; 249 | localparam TX_SEND_DATA = 8; 250 | 251 | reg [3:0] TX_DMA_STATE; 252 | 253 | always @( posedge clk_i or negedge rst_i ) begin 254 | if ( rst_i == 1'b0 ) begin 255 | can_send_setting <= 32'd0; 256 | tx_data <= 64'h0; 257 | tx_pending <= 1'b0; 258 | end else begin 259 | case ( TX_DMA_STATE ) 260 | TX_READ_IDLE: begin 261 | if ( tx_send_i == 1'b1 ) begin 262 | TX_DMA_STATE <= TX_START_READ_SETTING; 263 | end 264 | end 265 | TX_START_READ_SETTING: begin 266 | addr_rd <= ADDR_SETTING_SEND; 267 | can_send_setting <= data_rd; 268 | rd_en <= 1'b1; 269 | TX_DMA_STATE <= TX_READ_SETTING; 270 | end 271 | TX_READ_SETTING: begin 272 | rd_en <= 1'b0; 273 | TX_DMA_STATE <= TX_START_READ_DATA_1; 274 | end 275 | TX_START_READ_DATA_1: begin 276 | addr_rd <= ADDR_DATA_SEND_1; 277 | tx_data[63:32] <= data_rd; 278 | rd_en <= 1'b1; 279 | TX_DMA_STATE <= TX_READ_DATA_1; 280 | end 281 | TX_READ_DATA_1: begin 282 | rd_en <= 1'b0; 283 | TX_DMA_STATE <= TX_START_READ_DATA_2; 284 | end 285 | TX_START_READ_DATA_2: begin 286 | addr_rd <= ADDR_DATA_SEND_2; 287 | tx_data[31:0] <= data_rd; 288 | rd_en <= 1'b1; 289 | TX_DMA_STATE <= TX_START_READ_DATA_2; 290 | end 291 | TX_READ_DATA_2: begin 292 | rd_en <= 1'b0; 293 | TX_DMA_STATE <= TX_START_SEND_DATA; 294 | end 295 | TX_START_SEND_DATA: begin 296 | tx_pending <= 1'b1; 297 | TX_DMA_STATE <= TX_SEND_DATA; 298 | end 299 | TX_SEND_DATA: begin 300 | if ( tx_busy ) begin 301 | tx_pending <= 1'b0; 302 | TX_DMA_STATE <= TX_READ_IDLE; 303 | end 304 | end 305 | endcase 306 | end 307 | end 308 | // 309 | 310 | // 311 | localparam RX_WRITE_IDLE = 0; 312 | localparam RX_START_WRITE_SETTING = 1; 313 | localparam RX_WRITE_SETTING = 2; 314 | localparam RX_START_WRITE_DATA_1 = 3; 315 | localparam RX_WRITE_DATA_1 = 4; 316 | localparam RX_START_WRITE_DATA_2 = 5; 317 | localparam RX_WRITE_DATA_2 = 6; 318 | localparam RX_START_SEND_DATA = 7; 319 | localparam RX_SEND_DATA = 8; 320 | 321 | reg [3:0] RX_DMA_STATE; 322 | 323 | always @( posedge clk_i or negedge rst_i ) begin 324 | if ( rst_i == 1'b0 ) begin 325 | rx_data_reg <= 64'h0; 326 | end else begin 327 | case ( TX_DMA_STATE ) 328 | RX_WRITE_IDLE: begin 329 | if ( tx_send_i == 1'b1 ) begin 330 | RX_DMA_STATE <= RX_START_READ_SETTING; 331 | end 332 | end 333 | RX_START_WRITE_SETTING: begin 334 | addr_rd <= ADDR_SETTING_SEND; 335 | can_send_setting <= data_rd; 336 | rd_en <= 1'b1; 337 | RX_DMA_STATE <= RX_READ_SETTING; 338 | end 339 | RX_WRITE_SETTING: begin 340 | rd_en <= 1'b0; 341 | RX_DMA_STATE <= RX_START_READ_DATA_1; 342 | end 343 | RX_START_WRITE_DATA_1: begin 344 | addr_rd <= ADDR_DATA_SEND_1; 345 | tx_data[63:32] <= data_rd; 346 | rd_en <= 1'b1; 347 | RX_DMA_STATE <= RX_READ_DATA_1; 348 | end 349 | RX_WRITE_DATA_1: begin 350 | rd_en <= 1'b0; 351 | RX_DMA_STATE <= RX_START_READ_DATA_2; 352 | end 353 | RX_START_WRITE_DATA_2: begin 354 | addr_rd <= ADDR_DATA_SEND_2; 355 | tx_data[31:0] <= data_rd; 356 | rd_en <= 1'b1; 357 | RX_DMA_STATE <= RX_START_READ_DATA_2; 358 | end 359 | RX_WRITE_DATA_2: begin 360 | rd_en <= 1'b0; 361 | RX_DMA_STATE <= RX_START_SEND_DATA; 362 | end 363 | 364 | endcase 365 | 366 | end 367 | end 368 | // 369 | 370 | can_tx #( 371 | .CLK_FREQ (CLK_FREQ), 372 | .CAN_CLK_FREQ (CAN_CLK_FREQ) 373 | )can_tx_instance 374 | ( 375 | .rst_i (rst_i), 376 | .clk_i (clk_i), 377 | .clk_can_i (clk_can), 378 | .tx_start_i (tx_start), 379 | .tx_lost_arbitrage_o (tx_lost_arbitrage), 380 | .tx_acknowledged_o (tx_acknowledged), 381 | .frame_sent_o (frame_sent), 382 | 383 | .rx_i (rx_i), 384 | .tx_o (tx_o_tx), 385 | .tx_busy_o (tx_busy), 386 | 387 | .message_type (tx_message_type), 388 | .local_address (local_address), 389 | .remote_address (remote_address), 390 | .handshake (tx_handshake), 391 | .expand_count (tx_expand_count), 392 | .cmd_data_sign (tx_cmd_data_sign), 393 | .dlc (tx_dlc), 394 | .tx_data (tx_data), 395 | 396 | //test 397 | .test_tx_state (test_can_tx_state), 398 | .test_bit_count (test_bit_count), 399 | .test_bit_pol_count (test_bit_pol_count), 400 | .test_arbi (test_arbi) 401 | 402 | ); 403 | 404 | can_rx #( 405 | .CLK_FREQ (CLK_FREQ), 406 | .CAN_CLK_FREQ (CAN_CLK_FREQ) 407 | ) can_rx_instance 408 | ( 409 | .rst_i (rst_i), 410 | .rx_i (rx_i), 411 | .tx_o (tx_o_rx), 412 | .clk_i (clk_i), 413 | .clk_can_i (clk_can), 414 | .can_clk_sync_o (can_clk_sync), 415 | .rx_start_i (rx_start), 416 | .rx_busy_o (rx_busy), 417 | .init_i (init), 418 | .rx_frame_ready_o (rx_frame_ready), 419 | 420 | .local_address (LOCAL_ADDRESS), 421 | 422 | 423 | // 424 | .rx_data (rx_data), 425 | 426 | // 427 | 428 | //test 429 | .test_rx_state (test_rx_state), 430 | .test_quant_count (test_rx_quant_count), 431 | .test_bit_count (test_rx_bit_count), 432 | .test_bit_pol_count (test_rx_bit_pol_count), 433 | .test_rx_bit_stuffed (test_rx_bit_stuffed), 434 | .test_rx_count (test_rx_count), 435 | .test_rx_rx (test_rx_rx) 436 | //.test_sample_1 (test_sample) 437 | ); 438 | 439 | can_clk #( 440 | .FREQ_I (CLK_FREQ), 441 | .FREQ_O (CAN_CLK_FREQ) 442 | ) can_clk_instance 443 | ( 444 | .rst_i (rst_i), 445 | .clk_i (clk_i), 446 | .sync_i (can_clk_sync), 447 | .can_clk_o (clk_can) 448 | ); 449 | 450 | endmodule 451 | -------------------------------------------------------------------------------- /can_top.v.bak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/can_top.v.bak -------------------------------------------------------------------------------- /can_top_inst.v: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and any partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details, at 14 | // https://fpgasoftware.intel.com/eula. 15 | 16 | 17 | // Generated by Quartus Prime Version 20.1 (Build Build 711 06/05/2020) 18 | // Created on Mon Sep 28 17:48:38 2020 19 | 20 | can_top can_top_inst 21 | ( 22 | .rst_i(rst_i_sig) , // input rst_i_sig 23 | .clk_i(clk_i_sig) , // input clk_i_sig 24 | .rx_i(rx_i_sig) , // input rx_i_sig 25 | .rx_busy(rx_busy_sig) , // output rx_busy_sig 26 | .tx_o(tx_o_sig) , // output tx_o_sig 27 | .tx_busy(tx_busy_sig) , // output tx_busy_sig 28 | .data_i(data_i_sig) , // input [7:0] data_i_sig 29 | .data_o(data_o_sig) // output [7:0] data_o_sig 30 | ); 31 | 32 | -------------------------------------------------------------------------------- /can_tx.v: -------------------------------------------------------------------------------- 1 | module can_tx 2 | #( 3 | parameter CLK_FREQ = 50_000_000, 4 | parameter CAN_CLK_FREQ = 1_000_000, 5 | parameter QUANTS = CLK_FREQ/CAN_CLK_FREQ 6 | )( 7 | input rst_i, 8 | input clk_can_i, 9 | input clk_i, 10 | input tx_start_i, 11 | 12 | output reg frame_sent_o, 13 | output reg tx_lost_arbitrage_o, 14 | output tx_acknowledged_o, 15 | 16 | input message_type, 17 | input [5:0] local_address, 18 | input [5:0] remote_address, 19 | input [1:0] handshake, 20 | input [3:0] expand_count, 21 | input [7:0] cmd_data_sign, 22 | input [3:0] dlc, 23 | input [63:0] tx_data, 24 | 25 | input rx_i, 26 | output tx_o, 27 | output reg tx_busy_o, 28 | 29 | //test 30 | output [7:0] test_tx_state, 31 | output [7:0] test_bit_count, 32 | output [2:0] test_bit_pol_count, 33 | output reg test_arbi 34 | ); 35 | // 36 | assign test_tx_state = TX_STATE; 37 | assign test_bit_count = bit_count_reg; 38 | assign test_bit_pol_count = bit_pol_count; 39 | // 40 | 41 | reg [6:0] count; 42 | reg [11:0] quant_count; 43 | 44 | // 45 | wire [14:0] crc; 46 | wire crc_en; 47 | assign crc_en = ( TX_STATE == TX_IDLE || 48 | TX_STATE == TX_START_OF_FRAME || 49 | TX_STATE == TX_BIT_STUFF || 50 | TX_STATE == TX_CRC ) ? 1'b0 : 1'b1; 51 | 52 | reg crc_rst_i; 53 | can_crc can_crc_instance 54 | ( 55 | .crc_clk_i (clk_can_i), 56 | .rst_i (rst_i), 57 | .data_i (tx_o), 58 | .en_i (crc_en), 59 | .crc_reg_o (crc), 60 | .crc_rst_i (crc_rst_i) 61 | ); 62 | // 63 | 64 | // 65 | reg [7:0] bit_count_reg; 66 | reg [2:0] bit_pol_count; 67 | reg last_bit; 68 | reg bit_stuff_bit; 69 | // 70 | 71 | // 72 | 73 | // 74 | 75 | // 0xAx - MAC, 0xB-x - LLC 76 | localparam TX_IDLE = 8'h00; 77 | localparam TX_BIT_STUFF = 8'h0B; 78 | 79 | localparam TX_START_OF_FRAME = 8'hA1; 80 | localparam TX_MESSAGE_TYPE = 8'hB1; 81 | localparam TX_ADDRESS_LOCAL = 8'hB2; 82 | localparam TX_ADDRESS_REMOTE = 8'hB3; 83 | localparam TX_SRR = 8'hA2; 84 | localparam TX_IDE = 8'hA3; 85 | localparam TX_HANDSHAKING_P = 8'hB4; 86 | localparam TX_ATRIBUTE_RESERVED = 8'hB5; 87 | localparam TX_EXPAND_COUNT = 8'hB6; 88 | localparam TX_CMD_DATA_SIGN = 8'hB7; 89 | localparam TX_RTR = 8'hA4; 90 | localparam TX_RESERVED = 8'hA5; 91 | localparam TX_DLC = 8'hB8; 92 | localparam TX_DATA = 8'hB9; 93 | localparam TX_CRC = 8'hA6; 94 | localparam TX_CRC_DELIMITER = 8'hA7; 95 | localparam TX_ACK_SLOT = 8'hA8; 96 | localparam TX_ACK_DELIMITER = 8'hA9; 97 | localparam TX_END_OF_FRAME = 8'hAA; 98 | 99 | reg[7:0] TX_STATE = TX_IDLE; 100 | reg[7:0] NEXT_TX_STATE; 101 | 102 | always @( posedge clk_can_i or negedge rst_i ) begin 103 | if ( rst_i == 1'b0 ) begin 104 | TX_STATE <= 8'h0; 105 | NEXT_TX_STATE <= TX_IDLE; 106 | 107 | bit_count_reg <= 8'd0; 108 | count <= 7'd0; 109 | bit_pol_count <= 3'd1; 110 | bit_stuff_bit <= 1'b0; 111 | last_bit <= 1'b1; 112 | crc_rst_i <= 1'b0; 113 | tx_busy_o <= 1'b0; 114 | frame_sent_o <= 1'b0; 115 | end else begin 116 | if ( TX_STATE != TX_IDLE ) begin 117 | last_bit <= tx_o; 118 | bit_count_reg <= bit_count_reg + 1'b1; 119 | end 120 | case ( TX_STATE ) 121 | TX_IDLE: begin 122 | if ( tx_start_i ) begin 123 | tx_busy_o <= 1'b1; 124 | 125 | count <= 7'd0; 126 | bit_count_reg <= 8'd0; 127 | frame_sent_o <= 1'b0; 128 | TX_STATE <= TX_START_OF_FRAME; 129 | end 130 | end 131 | // 132 | 133 | // every 5 consequent same polarity bit add one reversed(not for CRC delimiter, ACK field and EOF) 134 | // 1 bit 135 | TX_BIT_STUFF: begin 136 | TX_STATE <= NEXT_TX_STATE; 137 | end 138 | // 1 bit 139 | TX_START_OF_FRAME: begin 140 | TX_STATE <= TX_MESSAGE_TYPE; 141 | NEXT_TX_STATE <= TX_MESSAGE_TYPE; 142 | crc_rst_i <= 1'b0; 143 | end 144 | 145 | // IDE and SRR are placed between 18 and 17 bit of 29 bit extended arbitration field 146 | // 1 bit 147 | TX_SRR: begin 148 | TX_STATE <= TX_IDE; 149 | NEXT_TX_STATE <= TX_IDE; 150 | end 151 | // 1 bit 152 | TX_IDE: begin 153 | TX_STATE <= TX_ADDRESS_REMOTE; 154 | NEXT_TX_STATE <= TX_ADDRESS_REMOTE; 155 | end 156 | // -- RTR-bit is 0 in the Data Frame, in the Remote Frame is 1 there and there is no Data Field 157 | // in Remote Frame The DLC field indicates the data length of the requested message (not the transmitted one) 158 | // 1 bit 159 | TX_RTR: begin 160 | TX_STATE <= TX_RESERVED; 161 | NEXT_TX_STATE <= TX_RESERVED; 162 | end 163 | // -- r1, r0 Reserved bits which must be set dominant (0), but accepted as either dominant or recessive 164 | TX_RESERVED: begin 165 | if ( count == 7'd1 ) begin 166 | count <= 7'd0; 167 | TX_STATE <= TX_DLC; 168 | NEXT_TX_STATE <= TX_DLC; 169 | end else begin 170 | count <= count + 1'b1; 171 | end 172 | end 173 | // -- exclude start of the frame bit 174 | // 15 bit 175 | TX_CRC: begin 176 | if ( count == 7'd14 ) begin 177 | count <= 7'd0; 178 | TX_STATE <= TX_CRC_DELIMITER; 179 | crc_rst_i <= 1'b1; 180 | end else begin 181 | count <= count + 1'b1; 182 | end 183 | end 184 | // -- must be 1 185 | // 1 bit 186 | TX_CRC_DELIMITER: begin 187 | TX_STATE <= TX_ACK_SLOT; 188 | end 189 | // -- Each node that receives the frame, without an error, transmits a 0 and thus overrides the 1 of the transmitter. 190 | // If a transmitter detects a recessive level in the ACK slot, it knows that no receiver found a valid frame. 191 | // A receiving node may transmit a recessive to indicate that it did not receive a valid frame, 192 | // but another node that did receive a valid frame may override this with a dominant. 193 | // 1 bit 194 | TX_ACK_SLOT: begin 195 | TX_STATE <= TX_ACK_DELIMITER; 196 | end 197 | // 1 bit(1) 198 | TX_ACK_DELIMITER: begin 199 | TX_STATE <= TX_END_OF_FRAME; 200 | end 201 | // 7 bits(1) 202 | TX_END_OF_FRAME: begin 203 | if ( count == 7'd6 ) begin 204 | count <= 7'd0; 205 | TX_STATE <= TX_IDLE; 206 | frame_sent_o <= 1'b1; 207 | tx_busy_o <= 1'b0; 208 | end else begin 209 | count <= count + 1'b1; 210 | end 211 | end 212 | // 213 | 214 | // 215 | // 216 | // C/D 1 bit 217 | TX_MESSAGE_TYPE: begin 218 | TX_STATE <= TX_ADDRESS_LOCAL; 219 | NEXT_TX_STATE <= TX_ADDRESS_LOCAL; 220 | end 221 | // Address local 6 bit 222 | TX_ADDRESS_LOCAL: begin 223 | if ( count == 7'd5 ) begin 224 | count <= 7'd0; 225 | TX_STATE <= TX_ADDRESS_REMOTE; 226 | NEXT_TX_STATE <= TX_ADDRESS_REMOTE; 227 | end else begin 228 | count <= count + 1'b1; 229 | end 230 | end 231 | // Address remote 6 bit 232 | TX_ADDRESS_REMOTE: begin 233 | if ( count == 7'd5 ) begin 234 | count <= 7'd0; 235 | TX_STATE <= TX_HANDSHAKING_P; 236 | NEXT_TX_STATE <= TX_HANDSHAKING_P; 237 | end else begin 238 | if ( count == 7'd3 ) begin 239 | count <= count + 1'b1; 240 | TX_STATE <= TX_SRR; 241 | NEXT_TX_STATE <= TX_SRR; 242 | end else begin 243 | count <= count + 1'b1; 244 | end 245 | end 246 | end 247 | // 248 | // 249 | // DataFrame: pointer, CommandFrame: handshaking 2 bit 250 | TX_HANDSHAKING_P: begin 251 | if ( count == 7'd1 ) begin 252 | count <= 7'd0; 253 | TX_STATE <= TX_ATRIBUTE_RESERVED; 254 | NEXT_TX_STATE <= TX_ATRIBUTE_RESERVED; 255 | end else begin 256 | count <= count + 1'b1; 257 | end 258 | end 259 | // DataFrame: reserved 2'b00, CommandFrame: 2'b10 2 bit 260 | TX_ATRIBUTE_RESERVED:begin 261 | if ( count == 7'd1 ) begin 262 | count <= 7'd0; 263 | TX_STATE <= TX_EXPAND_COUNT; 264 | NEXT_TX_STATE <= TX_EXPAND_COUNT; 265 | end else begin 266 | count <= count + 1'b1; 267 | end 268 | end 269 | // DataFrame: frame count, CommandFrame: expand command field 4 bit 270 | TX_EXPAND_COUNT: begin 271 | if ( count == 7'd3 ) begin 272 | count <= 7'd0; 273 | TX_STATE <= TX_CMD_DATA_SIGN; 274 | NEXT_TX_STATE <= TX_CMD_DATA_SIGN; 275 | end else begin 276 | count <= count + 1'b1; 277 | end 278 | end 279 | // DataFrame: type of data, CommandFrame: type of command 8 bit 280 | TX_CMD_DATA_SIGN: begin 281 | if ( count == 7'd7 ) begin 282 | count <= 7'd0; 283 | TX_STATE <= TX_RTR; 284 | NEXT_TX_STATE <= TX_RTR; 285 | end else begin 286 | count <= count + 1'b1; 287 | end 288 | end 289 | // DLC 4 bit 290 | TX_DLC: begin 291 | if ( count == 7'd3 ) begin 292 | count <= 7'd0; 293 | TX_STATE <= TX_DATA; 294 | NEXT_TX_STATE <= TX_DATA; 295 | end else begin 296 | count <= count + 1'b1; 297 | end 298 | end 299 | // Data 0 or 64 bit 300 | TX_DATA: begin 301 | if ( count == 7'd63 ) begin 302 | count <= 7'd0; 303 | TX_STATE <= TX_CRC; 304 | NEXT_TX_STATE <= TX_CRC; 305 | end else begin 306 | count <= count + 1'b1; 307 | end 308 | end 309 | // 310 | endcase 311 | 312 | // 313 | if ( TX_STATE != TX_IDLE && 314 | TX_STATE != TX_CRC_DELIMITER && 315 | TX_STATE != TX_ACK_SLOT && 316 | TX_STATE != TX_ACK_DELIMITER && 317 | TX_STATE != TX_END_OF_FRAME ) begin 318 | if ( tx_o == last_bit ) begin 319 | bit_pol_count <= bit_pol_count + 1'b1; 320 | if ( bit_pol_count == 3'd5 ) begin 321 | if ( tx_o == 1'b0 ) begin 322 | bit_stuff_bit <= 1'b1; 323 | end else begin 324 | bit_stuff_bit <= 1'b0; 325 | end 326 | bit_pol_count <= 3'd1; 327 | TX_STATE <= TX_BIT_STUFF; 328 | end 329 | end else begin 330 | bit_pol_count <= 3'd2; 331 | end 332 | end 333 | // 334 | if ( TX_STATE != TX_IDLE && 335 | TX_STATE != TX_ACK_SLOT ) begin 336 | if ( tx_o != rx_i ) begin 337 | //tx_lost_arbitrage_o <= 1'b1; 338 | //TX_STATE <= TX_IDLE; 339 | end 340 | end 341 | end 342 | end 343 | 344 | // 345 | reg tx_acknowledged_o_reg; 346 | assign tx_acknowledged_o = tx_acknowledged_o_reg; 347 | 348 | always @( posedge clk_can_i or negedge rst_i ) begin 349 | if ( rst_i == 1'b0 ) begin 350 | tx_acknowledged_o_reg <= 1'b0; 351 | end else begin 352 | if ( TX_STATE == TX_ACK_SLOT ) begin 353 | if ( rx_i == 1'b0 ) begin 354 | tx_acknowledged_o_reg <= 1'b1; 355 | end 356 | end 357 | end 358 | end 359 | // 360 | 361 | localparam SAMPLE = QUANTS/2; 362 | localparam STATE_RES = 12'd0; 363 | 364 | // 365 | always @( posedge clk_i or negedge rst_i ) begin 366 | if ( rst_i == 1'b0 ) begin 367 | tx_lost_arbitrage_o <= 1'b0; 368 | end else begin 369 | if ( TX_STATE == TX_IDLE ) begin 370 | quant_count <= STATE_RES; 371 | tx_lost_arbitrage_o <= 1'b0; 372 | end else begin 373 | quant_count <= quant_count + 1'b1; 374 | if ( quant_count == SAMPLE ) begin 375 | test_arbi <= rx_i; 376 | if ( TX_STATE != TX_ACK_SLOT ) begin 377 | if ( tx_o != rx_i ) begin 378 | tx_lost_arbitrage_o <= 1'b1; 379 | end 380 | end 381 | end else begin 382 | if ( quant_count == QUANTS ) begin 383 | quant_count <= STATE_RES; 384 | end 385 | end 386 | end 387 | end 388 | end 389 | // 390 | 391 | localparam [1:0] atribute = 2'b10; 392 | localparam rtr = 1'b0; 393 | assign tx_o = TX_STATE == TX_START_OF_FRAME ? 1'b0 : 394 | ( TX_STATE == TX_MESSAGE_TYPE ? message_type : 395 | ( TX_STATE == TX_ADDRESS_LOCAL ? local_address [7'd5 - count] : 396 | ( TX_STATE == TX_ADDRESS_REMOTE ? remote_address [7'd5 - count] : 397 | ( TX_STATE == TX_SRR ? 1'b1 : 398 | ( TX_STATE == TX_IDE ? 1'b1 : 399 | ( TX_STATE == TX_HANDSHAKING_P ? handshake [7'd1 - count] : 400 | ( TX_STATE == TX_ATRIBUTE_RESERVED ? atribute [7'd1 - count] : 401 | ( TX_STATE == TX_EXPAND_COUNT ? expand_count [7'd3 - count] : 402 | ( TX_STATE == TX_CMD_DATA_SIGN ? cmd_data_sign [7'd7 - count] : 403 | ( TX_STATE == TX_RTR ? rtr : 404 | ( TX_STATE == TX_RESERVED ? 1'b0 : 405 | ( TX_STATE == TX_DLC ? dlc [7'd3 - count] : 406 | ( TX_STATE == TX_DATA ? tx_data [7'd63 - count] : 407 | ( TX_STATE == TX_CRC ? crc [7'd14 - count] : 408 | ( TX_STATE == TX_CRC_DELIMITER ? 1'b1 : 409 | ( TX_STATE == TX_ACK_SLOT ? 1'b1 : 410 | ( TX_STATE == TX_ACK_DELIMITER ? 1'b1 : 411 | ( TX_STATE == TX_END_OF_FRAME ? 1'b1 : 412 | ( TX_STATE == TX_BIT_STUFF ? bit_stuff_bit : 413 | ( TX_STATE == TX_IDLE ? 1'b1 : 414 | 1'b1 )))))))))))))))))))); 415 | 416 | endmodule -------------------------------------------------------------------------------- /can_tx.v.bak: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/can_tx.v.bak -------------------------------------------------------------------------------- /db/.cmp.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/.cmp.kpt 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"*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1604668657670 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1604668657671 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 06 16:17:37 2020 " "Processing started: Fri Nov 06 16:17:37 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1604668657671 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1604668657671 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off CAN -c CAN " "Command: quartus_asm --read_settings_files=off --write_settings_files=off CAN -c CAN" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1604668657671 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1604668657920 ""} 5 | { "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1604668658172 ""} 6 | { "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1604668658188 ""} 7 | { "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4681 " "Peak virtual memory: 4681 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1604668658371 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 06 16:17:38 2020 " "Processing ended: Fri Nov 06 16:17:38 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1604668658371 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1604668658371 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1604668658371 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1604668658371 ""} 8 | -------------------------------------------------------------------------------- /db/CAN.asm.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.asm.rdb -------------------------------------------------------------------------------- /db/CAN.asm_labs.ddb: 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-------------------------------------------------------------------------------- /db/CAN.cmp.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.cmp.hdb -------------------------------------------------------------------------------- /db/CAN.cmp.idb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.cmp.idb -------------------------------------------------------------------------------- /db/CAN.cmp.logdb: -------------------------------------------------------------------------------- 1 | v1 2 | IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, 3 | IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, 4 | IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,PASS,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,0 such failures found.,,I/O,, 5 | IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, 6 | IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, 7 | IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, 8 | IO_RULES,CHECK_UNAVAILABLE_LOC,PASS,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,0 such failures found.,,I/O,, 9 | IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, 10 | IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, 11 | IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, 12 | IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, 13 | IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, 14 | IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, 15 | IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, 16 | IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, 17 | IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, 18 | IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,, 19 | IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,, 20 | IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, 21 | IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, 22 | IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, 23 | IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,, 24 | IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,, 25 | IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, 26 | IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, 27 | IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,, 28 | IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,, 29 | IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,, 30 | IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, 31 | IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, 32 | IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,, 33 | IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042, 34 | IO_RULES_MATRIX,Total Pass,7;0;7;0;0;8;7;0;8;8;0;1;0;0;3;0;1;3;0;0;0;1;0;0;0;0;0;8;0;0, 35 | IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, 36 | IO_RULES_MATRIX,Total Inapplicable,1;8;1;8;8;0;1;8;0;0;8;7;8;8;5;8;7;5;8;8;8;7;8;8;8;8;8;0;8;8, 37 | IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, 38 | IO_RULES_MATRIX,tx_o,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 39 | IO_RULES_MATRIX,tx_busy,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 40 | IO_RULES_MATRIX,rx_busy,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 41 | IO_RULES_MATRIX,test_rx_rx,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 42 | IO_RULES_MATRIX,test_sample,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 43 | IO_RULES_MATRIX,clk_i,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 44 | IO_RULES_MATRIX,rst_i,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 45 | IO_RULES_MATRIX,rx_i,Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable, 46 | IO_RULES_SUMMARY,Total I/O Rules,30, 47 | IO_RULES_SUMMARY,Number of I/O Rules Passed,12, 48 | IO_RULES_SUMMARY,Number of I/O Rules Failed,0, 49 | IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, 50 | IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,18, 51 | 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Version_Index = 520275712 3 | Creation_Time = Thu Nov 05 13:18:20 2020 4 | -------------------------------------------------------------------------------- /db/CAN.eco.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.eco.cdb -------------------------------------------------------------------------------- /db/CAN.eda.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1603449625530 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 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All rights reserved. " "Copyright (C) 2020 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and any partner logic " "and other software and tools, and any partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details, at " "refer to the applicable agreement for further details, at" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "https://fpgasoftware.intel.com/eula. " "https://fpgasoftware.intel.com/eula." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 23 13:40:25 2020 " "Processing started: Fri Oct 23 13:40:25 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1603449625530 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1603449625530 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/hdl_projects/Can/simulation/qsim/ CAN -c CAN " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/hdl_projects/Can/simulation/qsim/ CAN -c CAN" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1603449625530 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1603449625777 ""} 5 | { "Info" "IWSC_DONE_HDL_GENERATION" "CAN.vo C:/hdl_projects/Can/simulation/qsim// simulation " "Generated file CAN.vo in folder \"C:/hdl_projects/Can/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1603449625951 ""} 6 | { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4638 " "Peak virtual memory: 4638 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1603449625995 ""} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 23 13:40:25 2020 " "Processing ended: Fri Oct 23 13:40:25 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1603449625995 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1603449625995 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1603449625995 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1603449625995 ""} 7 | -------------------------------------------------------------------------------- /db/CAN.hif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.hif -------------------------------------------------------------------------------- /db/CAN.lpc.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 |
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
PMRAMIF_inst2000000000000
can_top_inst|can_clk_instance3000100000000
can_top_inst|can_rx_instance|can_crc_instance50001500000000
can_top_inst|can_rx_instance1270710877700000
can_top_inst|can_tx_instance|can_crc_instance50001500000000
can_top_inst|can_tx_instance100340342534343400000
can_top_inst70188018812418818818800000
131 | -------------------------------------------------------------------------------- /db/CAN.lpc.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.lpc.rdb -------------------------------------------------------------------------------- /db/CAN.lpc.txt: -------------------------------------------------------------------------------- 1 | +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ 2 | ; Legal Partition Candidates ; 3 | +-----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 4 | ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; 5 | +-----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 6 | ; PMRAMIF_inst ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 | ; can_top_inst|can_clk_instance ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 8 | ; can_top_inst|can_rx_instance|can_crc_instance ; 5 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 9 | ; can_top_inst|can_rx_instance ; 12 ; 7 ; 0 ; 7 ; 108 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 10 | ; can_top_inst|can_tx_instance|can_crc_instance ; 5 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 | ; can_top_inst|can_tx_instance ; 100 ; 34 ; 0 ; 34 ; 25 ; 34 ; 34 ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 | ; can_top_inst ; 70 ; 188 ; 0 ; 188 ; 124 ; 188 ; 188 ; 188 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 | +-----------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ 14 | -------------------------------------------------------------------------------- /db/CAN.map.ammdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.map.ammdb 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https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.pre_map.cdb -------------------------------------------------------------------------------- /db/CAN.pre_map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.pre_map.hdb -------------------------------------------------------------------------------- /db/CAN.root_partition.map.reg_db.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.root_partition.map.reg_db.cdb -------------------------------------------------------------------------------- /db/CAN.routing.rdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.routing.rdb -------------------------------------------------------------------------------- /db/CAN.rtlv.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.rtlv.hdb -------------------------------------------------------------------------------- /db/CAN.rtlv_sg.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.rtlv_sg.cdb -------------------------------------------------------------------------------- /db/CAN.rtlv_sg_swap.cdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.rtlv_sg_swap.cdb -------------------------------------------------------------------------------- /db/CAN.sld_design_entry.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.sld_design_entry.sci -------------------------------------------------------------------------------- /db/CAN.sld_design_entry_dsc.sci: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/db/CAN.sld_design_entry_dsc.sci -------------------------------------------------------------------------------- /db/CAN.smart_action.txt: -------------------------------------------------------------------------------- 1 | DONE 2 | -------------------------------------------------------------------------------- /db/CAN.smp_dump.txt: -------------------------------------------------------------------------------- 1 | 2 | State Machine - |can_test|PMRAMIF:PMRAMIF_inst|STATE 3 | Name STATE.IDLE STATE.MRAM_READ STATE.MRAM_WRITE 4 | STATE.IDLE 0 0 0 5 | STATE.MRAM_WRITE 1 0 1 6 | STATE.MRAM_READ 1 1 0 7 | 8 | State Machine - |can_test|can_top:can_top_inst|TX_DMA_STATE 9 | Name TX_DMA_STATE.TX_START_SEND_DATA TX_DMA_STATE.TX_READ_DATA_2 TX_DMA_STATE.TX_START_READ_DATA_2 TX_DMA_STATE.TX_READ_DATA_1 TX_DMA_STATE.TX_START_READ_DATA_1 TX_DMA_STATE.TX_READ_SETTING TX_DMA_STATE.TX_START_READ_SETTING TX_DMA_STATE.TX_READ_IDLE TX_DMA_STATE.TX_SEND_DATA 10 | TX_DMA_STATE.TX_READ_IDLE 0 0 0 0 0 0 0 0 0 11 | TX_DMA_STATE.TX_START_READ_SETTING 0 0 0 0 0 0 1 1 0 12 | TX_DMA_STATE.TX_READ_SETTING 0 0 0 0 0 1 0 1 0 13 | TX_DMA_STATE.TX_START_READ_DATA_1 0 0 0 0 1 0 0 1 0 14 | TX_DMA_STATE.TX_READ_DATA_1 0 0 0 1 0 0 0 1 0 15 | TX_DMA_STATE.TX_START_READ_DATA_2 0 0 1 0 0 0 0 1 0 16 | TX_DMA_STATE.TX_READ_DATA_2 0 1 0 0 0 0 0 1 0 17 | TX_DMA_STATE.TX_START_SEND_DATA 1 0 0 0 0 0 0 1 0 18 | TX_DMA_STATE.TX_SEND_DATA 0 0 0 0 0 0 0 1 1 19 | 20 | State Machine - |can_test|can_top:can_top_inst|CAN_STATE 21 | Name CAN_STATE.CAN_TEST CAN_STATE.CAN_TEST_START CAN_STATE.CAN_TX CAN_STATE.CAN_START_TX CAN_STATE.CAN_RX CAN_STATE.CAN_START_RX CAN_STATE.CAN_PAUSE CAN_STATE.CAN_START_INIT CAN_STATE.CAN_INIT CAN_STATE.CAN_IDLE 22 | CAN_STATE.CAN_IDLE 0 0 0 0 0 0 0 0 0 0 23 | CAN_STATE.CAN_INIT 0 0 0 0 0 0 0 0 1 1 24 | CAN_STATE.CAN_START_INIT 0 0 0 0 0 0 0 1 0 1 25 | CAN_STATE.CAN_PAUSE 0 0 0 0 0 0 1 0 0 1 26 | CAN_STATE.CAN_START_RX 0 0 0 0 0 1 0 0 0 1 27 | CAN_STATE.CAN_RX 0 0 0 0 1 0 0 0 0 1 28 | CAN_STATE.CAN_START_TX 0 0 0 1 0 0 0 0 0 1 29 | CAN_STATE.CAN_TX 0 0 1 0 0 0 0 0 0 1 30 | CAN_STATE.CAN_TEST_START 0 1 0 0 0 0 0 0 0 1 31 | CAN_STATE.CAN_TEST 1 0 0 0 0 0 0 0 0 1 32 | 33 | State Machine - |can_test|can_top:can_top_inst|can_rx:can_rx_instance|NEXT_RX_STATE 34 | Name NEXT_RX_STATE.RX_DATA NEXT_RX_STATE.RX_DLC NEXT_RX_STATE.RX_CMD_DATA_SIGN NEXT_RX_STATE.RX_EXPAND_COUNT NEXT_RX_STATE.RX_ATRIBUTE_RESERVED NEXT_RX_STATE.RX_HANDSHAKING_P NEXT_RX_STATE.RX_ADDRESS_REMOTE NEXT_RX_STATE.RX_ADDRESS_LOCAL NEXT_RX_STATE.RX_MESSAGE_TYPE NEXT_RX_STATE.RX_CRC NEXT_RX_STATE.RX_RESERVED NEXT_RX_STATE.RX_RTR NEXT_RX_STATE.RX_IDE NEXT_RX_STATE.RX_SRR NEXT_RX_STATE.RX_IDLE 35 | NEXT_RX_STATE.RX_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 | NEXT_RX_STATE.RX_SRR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 37 | NEXT_RX_STATE.RX_IDE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 38 | NEXT_RX_STATE.RX_RTR 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 39 | NEXT_RX_STATE.RX_RESERVED 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 40 | NEXT_RX_STATE.RX_CRC 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 41 | NEXT_RX_STATE.RX_MESSAGE_TYPE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 42 | NEXT_RX_STATE.RX_ADDRESS_LOCAL 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 43 | NEXT_RX_STATE.RX_ADDRESS_REMOTE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 44 | NEXT_RX_STATE.RX_HANDSHAKING_P 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 45 | NEXT_RX_STATE.RX_ATRIBUTE_RESERVED 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 46 | NEXT_RX_STATE.RX_EXPAND_COUNT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 47 | NEXT_RX_STATE.RX_CMD_DATA_SIGN 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 48 | NEXT_RX_STATE.RX_DLC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 49 | NEXT_RX_STATE.RX_DATA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 50 | 51 | State Machine - |can_test|can_top:can_top_inst|can_rx:can_rx_instance|RX_STATE 52 | Name RX_STATE.RX_DATA RX_STATE.RX_DLC RX_STATE.RX_CMD_DATA_SIGN RX_STATE.RX_EXPAND_COUNT RX_STATE.RX_ATRIBUTE_RESERVED RX_STATE.RX_HANDSHAKING_P RX_STATE.RX_ADDRESS_REMOTE RX_STATE.RX_ADDRESS_LOCAL RX_STATE.RX_MESSAGE_TYPE RX_STATE.RX_END_OF_FRAME RX_STATE.RX_ACK_DELIMITER RX_STATE.RX_ACK_SLOT RX_STATE.RX_CRC_DELIMITER RX_STATE.RX_CRC RX_STATE.RX_RESERVED RX_STATE.RX_RTR RX_STATE.RX_IDE RX_STATE.RX_SRR RX_STATE.RX_START_OF_FRAME RX_STATE.RX_BIT_STUFF RX_STATE.RX_IDLE 53 | RX_STATE.RX_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 54 | RX_STATE.RX_BIT_STUFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 55 | RX_STATE.RX_START_OF_FRAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 56 | RX_STATE.RX_SRR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 57 | RX_STATE.RX_IDE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 58 | RX_STATE.RX_RTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 59 | RX_STATE.RX_RESERVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 60 | RX_STATE.RX_CRC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 61 | RX_STATE.RX_CRC_DELIMITER 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 62 | RX_STATE.RX_ACK_SLOT 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 63 | RX_STATE.RX_ACK_DELIMITER 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 64 | RX_STATE.RX_END_OF_FRAME 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 65 | RX_STATE.RX_MESSAGE_TYPE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 66 | RX_STATE.RX_ADDRESS_LOCAL 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 67 | RX_STATE.RX_ADDRESS_REMOTE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 68 | RX_STATE.RX_HANDSHAKING_P 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 69 | RX_STATE.RX_ATRIBUTE_RESERVED 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 70 | RX_STATE.RX_EXPAND_COUNT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 71 | RX_STATE.RX_CMD_DATA_SIGN 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 72 | RX_STATE.RX_DLC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 73 | RX_STATE.RX_DATA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 74 | 75 | State Machine - |can_test|can_top:can_top_inst|can_tx:can_tx_instance|NEXT_TX_STATE 76 | Name NEXT_TX_STATE.TX_DATA NEXT_TX_STATE.TX_DLC NEXT_TX_STATE.TX_CMD_DATA_SIGN NEXT_TX_STATE.TX_EXPAND_COUNT NEXT_TX_STATE.TX_ATRIBUTE_RESERVED NEXT_TX_STATE.TX_HANDSHAKING_P NEXT_TX_STATE.TX_ADDRESS_REMOTE NEXT_TX_STATE.TX_ADDRESS_LOCAL NEXT_TX_STATE.TX_MESSAGE_TYPE NEXT_TX_STATE.TX_CRC NEXT_TX_STATE.TX_RESERVED NEXT_TX_STATE.TX_RTR NEXT_TX_STATE.TX_IDE NEXT_TX_STATE.TX_SRR NEXT_TX_STATE.TX_IDLE 77 | NEXT_TX_STATE.TX_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78 | NEXT_TX_STATE.TX_SRR 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 79 | NEXT_TX_STATE.TX_IDE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 80 | NEXT_TX_STATE.TX_RTR 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 81 | NEXT_TX_STATE.TX_RESERVED 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 82 | NEXT_TX_STATE.TX_CRC 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 83 | NEXT_TX_STATE.TX_MESSAGE_TYPE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 84 | NEXT_TX_STATE.TX_ADDRESS_LOCAL 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 85 | NEXT_TX_STATE.TX_ADDRESS_REMOTE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 86 | NEXT_TX_STATE.TX_HANDSHAKING_P 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 87 | NEXT_TX_STATE.TX_ATRIBUTE_RESERVED 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 88 | NEXT_TX_STATE.TX_EXPAND_COUNT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 89 | NEXT_TX_STATE.TX_CMD_DATA_SIGN 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 90 | NEXT_TX_STATE.TX_DLC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 91 | NEXT_TX_STATE.TX_DATA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 92 | 93 | State Machine - |can_test|can_top:can_top_inst|can_tx:can_tx_instance|TX_STATE 94 | Name TX_STATE.TX_DATA TX_STATE.TX_DLC TX_STATE.TX_CMD_DATA_SIGN TX_STATE.TX_EXPAND_COUNT TX_STATE.TX_ATRIBUTE_RESERVED TX_STATE.TX_HANDSHAKING_P TX_STATE.TX_ADDRESS_REMOTE TX_STATE.TX_ADDRESS_LOCAL TX_STATE.TX_MESSAGE_TYPE TX_STATE.TX_END_OF_FRAME TX_STATE.TX_ACK_DELIMITER TX_STATE.TX_ACK_SLOT TX_STATE.TX_CRC_DELIMITER TX_STATE.TX_CRC TX_STATE.TX_RESERVED TX_STATE.TX_RTR TX_STATE.TX_IDE TX_STATE.TX_SRR TX_STATE.TX_START_OF_FRAME TX_STATE.TX_BIT_STUFF TX_STATE.TX_IDLE 95 | TX_STATE.TX_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 96 | TX_STATE.TX_BIT_STUFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 97 | TX_STATE.TX_START_OF_FRAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 98 | TX_STATE.TX_SRR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 99 | TX_STATE.TX_IDE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 100 | TX_STATE.TX_RTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 101 | TX_STATE.TX_RESERVED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 102 | TX_STATE.TX_CRC 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 103 | TX_STATE.TX_CRC_DELIMITER 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 104 | TX_STATE.TX_ACK_SLOT 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 105 | TX_STATE.TX_ACK_DELIMITER 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 106 | TX_STATE.TX_END_OF_FRAME 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 107 | TX_STATE.TX_MESSAGE_TYPE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 108 | TX_STATE.TX_ADDRESS_LOCAL 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 109 | TX_STATE.TX_ADDRESS_REMOTE 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 110 | TX_STATE.TX_HANDSHAKING_P 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 111 | TX_STATE.TX_ATRIBUTE_RESERVED 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 112 | TX_STATE.TX_EXPAND_COUNT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 113 | TX_STATE.TX_CMD_DATA_SIGN 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 114 | TX_STATE.TX_DLC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 115 | TX_STATE.TX_DATA 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 116 | -------------------------------------------------------------------------------- /db/CAN.sta.rdb: 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-------------------------------------------------------------------------------- 1 | { 2 | "partitions" : [ 3 | { 4 | "name" : "Top", 5 | "pins" : [ 6 | { 7 | "name" : "tx_o", 8 | "strict" : false 9 | }, 10 | { 11 | "name" : "tx_busy", 12 | "strict" : false 13 | }, 14 | { 15 | "name" : "rx_busy", 16 | "strict" : false 17 | }, 18 | { 19 | "name" : "clk_i", 20 | "strict" : false 21 | }, 22 | { 23 | "name" : "rst_i", 24 | "strict" : false 25 | }, 26 | { 27 | "name" : "rx_i", 28 | "strict" : false 29 | } 30 | ] 31 | } 32 | ] 33 | } -------------------------------------------------------------------------------- /db/prev_cmp_CAN.qmsg: -------------------------------------------------------------------------------- 1 | { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1604666446056 ""} 2 | { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition " "Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1604666446056 ""} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 06 15:40:45 2020 " "Processing started: Fri Nov 06 15:40:45 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1604666446056 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666446056 ""} 3 | { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CAN -c CAN " "Command: quartus_map --read_settings_files=on --write_settings_files=off CAN -c CAN" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666446056 ""} 4 | { "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1604666447151 ""} 5 | { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1604666447151 ""} 6 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "LOCAL_ADDRESS local_address can_top.v(15) " "Verilog HDL Declaration information at can_top.v(15): object \"LOCAL_ADDRESS\" differs only in case from object \"local_address\" in the same scope" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 15 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457945 ""} 7 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_top.v 1 1 " "Found 1 design units, including 1 entities, in source file can_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_top " "Found entity 1: can_top" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457951 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457951 ""} 8 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_rate.v 1 1 " "Found 1 design units, including 1 entities, in source file baud_rate.v" { { "Info" "ISGN_ENTITY_NAME" "1 baud_rate " "Found entity 1: baud_rate" { } { { "baud_rate.v" "" { Text "C:/hdl_projects/CAN/baud_rate.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457956 ""} 9 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "tx_data TX_DATA can_tx.v(23) " "Verilog HDL Declaration information at can_tx.v(23): object \"tx_data\" differs only in case from object \"TX_DATA\" in the same scope" { } { { "can_tx.v" "" { Text "C:/hdl_projects/CAN/can_tx.v" 23 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457963 ""} 10 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file can_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_tx " "Found entity 1: can_tx" { } { { "can_tx.v" "" { Text "C:/hdl_projects/CAN/can_tx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457963 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457963 ""} 11 | { "Warning" "WSGN_FILE_IS_MISSING" "output_files/can_rx.v " "Can't analyze file -- file output_files/can_rx.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1604666457967 ""} 12 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_crc.v 1 1 " "Found 1 design units, including 1 entities, in source file can_crc.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_crc " "Found entity 1: can_crc" { } { { "can_crc.v" "" { Text "C:/hdl_projects/CAN/can_crc.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457972 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457972 ""} 13 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_clk.v 1 1 " "Found 1 design units, including 1 entities, in source file can_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_clk " "Found entity 1: can_clk" { } { { "can_clk.v" "" { Text "C:/hdl_projects/CAN/can_clk.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457977 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457977 ""} 14 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_message_type RX_MESSAGE_TYPE can_rx.v(151) " "Verilog HDL Declaration information at can_rx.v(151): object \"rx_message_type\" differs only in case from object \"RX_MESSAGE_TYPE\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 151 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457984 ""} 15 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_address_local RX_ADDRESS_LOCAL can_rx.v(152) " "Verilog HDL Declaration information at can_rx.v(152): object \"rx_address_local\" differs only in case from object \"RX_ADDRESS_LOCAL\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 152 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457984 ""} 16 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_address_remote RX_ADDRESS_REMOTE can_rx.v(153) " "Verilog HDL Declaration information at can_rx.v(153): object \"rx_address_remote\" differs only in case from object \"RX_ADDRESS_REMOTE\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 153 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 17 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_handshaking_p RX_HANDSHAKING_P can_rx.v(154) " "Verilog HDL Declaration information at can_rx.v(154): object \"rx_handshaking_p\" differs only in case from object \"RX_HANDSHAKING_P\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 154 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 18 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_atribute_reserved RX_ATRIBUTE_RESERVED can_rx.v(155) " "Verilog HDL Declaration information at can_rx.v(155): object \"rx_atribute_reserved\" differs only in case from object \"RX_ATRIBUTE_RESERVED\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 155 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 19 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_expand_count RX_EXPAND_COUNT can_rx.v(156) " "Verilog HDL Declaration information at can_rx.v(156): object \"rx_expand_count\" differs only in case from object \"RX_EXPAND_COUNT\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 156 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 20 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_cmd_data_sign RX_CMD_DATA_SIGN can_rx.v(157) " "Verilog HDL Declaration information at can_rx.v(157): object \"rx_cmd_data_sign\" differs only in case from object \"RX_CMD_DATA_SIGN\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 157 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 21 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_dlc RX_DLC can_rx.v(158) " "Verilog HDL Declaration information at can_rx.v(158): object \"rx_dlc\" differs only in case from object \"RX_DLC\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 158 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 22 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_data RX_DATA can_rx.v(26) " "Verilog HDL Declaration information at can_rx.v(26): object \"rx_data\" differs only in case from object \"RX_DATA\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 26 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 23 | { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "rx_crc RX_CRC can_rx.v(159) " "Verilog HDL Declaration information at can_rx.v(159): object \"rx_crc\" differs only in case from object \"RX_CRC\" in the same scope" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 159 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1604666457985 ""} 24 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file can_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_rx " "Found entity 1: can_rx" { } { { "can_rx.v" "" { Text "C:/hdl_projects/CAN/can_rx.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457987 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457987 ""} 25 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "can_test.v 1 1 " "Found 1 design units, including 1 entities, in source file can_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 can_test " "Found entity 1: can_test" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457992 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457992 ""} 26 | { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pmramif.v 1 1 " "Found 1 design units, including 1 entities, in source file pmramif.v" { { "Info" "ISGN_ENTITY_NAME" "1 PMRAMIF " "Found entity 1: PMRAMIF" { } { { "pmramif.v" "" { Text "C:/hdl_projects/CAN/pmramif.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1604666457999 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666457999 ""} 27 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "tx_lost_arbitrage can_top.v(329) " "Verilog HDL Implicit Net warning at can_top.v(329): created implicit net for \"tx_lost_arbitrage\"" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 329 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 28 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "tx_acknowledged can_top.v(330) " "Verilog HDL Implicit Net warning at can_top.v(330): created implicit net for \"tx_acknowledged\"" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 330 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 29 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "can_clk_sync can_top.v(364) " "Verilog HDL Implicit Net warning at can_top.v(364): created implicit net for \"can_clk_sync\"" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 364 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 30 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "data_wr can_test.v(38) " "Verilog HDL Implicit Net warning at can_test.v(38): created implicit net for \"data_wr\"" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 38 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 31 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "addr_wr can_test.v(39) " "Verilog HDL Implicit Net warning at can_test.v(39): created implicit net for \"addr_wr\"" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 39 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 32 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wr_en can_test.v(40) " "Verilog HDL Implicit Net warning at can_test.v(40): created implicit net for \"wr_en\"" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 40 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 33 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wr_done can_test.v(41) " "Verilog HDL Implicit Net warning at can_test.v(41): created implicit net for \"wr_done\"" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 41 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 34 | { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "wr_busy can_test.v(42) " "Verilog HDL Implicit Net warning at can_test.v(42): created implicit net for \"wr_busy\"" { } { { "can_test.v" "" { Text "C:/hdl_projects/CAN/can_test.v" 42 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1604666458000 ""} 35 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "addr_rd can_top.v(262) " "Verilog HDL Procedural Assignment error at can_top.v(262): object \"addr_rd\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 262 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458002 ""} 36 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(264) " "Verilog HDL Procedural Assignment error at can_top.v(264): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 264 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 37 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(268) " "Verilog HDL Procedural Assignment error at can_top.v(268): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 268 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 38 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "addr_rd can_top.v(272) " "Verilog HDL Procedural Assignment error at can_top.v(272): object \"addr_rd\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 272 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 39 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(274) " "Verilog HDL Procedural Assignment error at can_top.v(274): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 274 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 40 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(278) " "Verilog HDL Procedural Assignment error at can_top.v(278): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 278 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 41 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "addr_rd can_top.v(282) " "Verilog HDL Procedural Assignment error at can_top.v(282): object \"addr_rd\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 282 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 42 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(284) " "Verilog HDL Procedural Assignment error at can_top.v(284): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 284 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 43 | { "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "rd_en can_top.v(288) " "Verilog HDL Procedural Assignment error at can_top.v(288): object \"rd_en\" on left-hand side of assignment must have a variable data type" { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 288 0 0 } } } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 44 | { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "TX_START_SEND_DATA can_top.v(289) " "Verilog HDL error at can_top.v(289): object \"TX_START_SEND_DATA\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 289 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 45 | { "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "TX_START_SEND_DATA can_top.v(291) " "Verilog HDL error at can_top.v(291): object \"TX_START_SEND_DATA\" is not declared. Verify the object name is correct. If the name is correct, declare the object." { } { { "can_top.v" "" { Text "C:/hdl_projects/CAN/can_top.v" 291 0 0 } } } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared. Verify the object name is correct. If the name is correct, declare the object." 0 0 "Analysis & Synthesis" 0 -1 1604666458003 ""} 46 | { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/hdl_projects/CAN/output_files/CAN.map.smsg " "Generated suppressed messages file C:/hdl_projects/CAN/output_files/CAN.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666458044 ""} 47 | { "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 11 s 10 s Quartus Prime " "Quartus Prime Analysis & Synthesis was unsuccessful. 11 errors, 10 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4698 " "Peak virtual memory: 4698 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1604666458126 ""} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 06 15:40:58 2020 " "Processing ended: Fri Nov 06 15:40:58 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1604666458126 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:13 " "Elapsed time: 00:00:13" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1604666458126 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1604666458126 ""} } { } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666458126 ""} 48 | { "Error" "EFLOW_ERROR_COUNT" "Full Compilation 13 s 10 s " "Quartus Prime Full Compilation was unsuccessful. 13 errors, 10 warnings" { } { } 0 293001 "Quartus Prime %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1604666458811 ""} 49 | -------------------------------------------------------------------------------- /incremental_db/README: -------------------------------------------------------------------------------- 1 | This folder contains data for incremental compilation. 2 | 3 | The compiled_partitions sub-folder contains previous compilation results for each partition. 4 | As long as this folder is preserved, incremental compilation results from earlier compiles 5 | can be re-used. To perform a clean compilation from source files for all partitions, both 6 | the db and incremental_db folder should be removed. 7 | 8 | The imported_partitions sub-folder contains the last imported QXP for each imported partition. 9 | As long as this folder is preserved, imported partitions will be automatically re-imported 10 | when the db or incremental_db/compiled_partitions folders are removed. 11 | 12 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.db_info: -------------------------------------------------------------------------------- 1 | Quartus_Version = Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 2 | Version_Index = 520275712 3 | Creation_Time = Mon Sep 28 17:50:51 2020 4 | -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.root_partition.cmp.ammdb: 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-------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.root_partition.map.hbdb.sig: -------------------------------------------------------------------------------- 1 | c5eb7f6cdd530884c3b884e0a3668ea4 -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.root_partition.map.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/incremental_db/compiled_partitions/CAN.root_partition.map.hdb -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.root_partition.map.kpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/incremental_db/compiled_partitions/CAN.root_partition.map.kpt -------------------------------------------------------------------------------- /incremental_db/compiled_partitions/CAN.rrp.hdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/incremental_db/compiled_partitions/CAN.rrp.hdb -------------------------------------------------------------------------------- /output_files/CAN.asm.rpt: -------------------------------------------------------------------------------- 1 | Assembler report for CAN 2 | Fri Nov 06 16:17:38 2020 3 | Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Assembler Summary 11 | 3. Assembler Settings 12 | 4. Assembler Generated Files 13 | 5. Assembler Device Options: C:/hdl_projects/CAN/output_files/CAN.sof 14 | 6. Assembler Messages 15 | 16 | 17 | 18 | ---------------- 19 | ; Legal Notice ; 20 | ---------------- 21 | Copyright (C) 2020 Intel Corporation. All rights reserved. 22 | Your use of Intel Corporation's design tools, logic functions 23 | and other software and tools, and any partner logic 24 | functions, and any output files from any of the foregoing 25 | (including device programming or simulation files), and any 26 | associated documentation or information are expressly subject 27 | to the terms and conditions of the Intel Program License 28 | Subscription Agreement, the Intel Quartus Prime License Agreement, 29 | the Intel FPGA IP License Agreement, or other applicable license 30 | agreement, including, without limitation, that your use is for 31 | the sole purpose of programming logic devices manufactured by 32 | Intel and sold by Intel or its authorized distributors. Please 33 | refer to the applicable agreement for further details, at 34 | https://fpgasoftware.intel.com/eula. 35 | 36 | 37 | 38 | +---------------------------------------------------------------+ 39 | ; Assembler Summary ; 40 | +-----------------------+---------------------------------------+ 41 | ; Assembler Status ; Successful - Fri Nov 06 16:17:38 2020 ; 42 | ; Revision Name ; CAN ; 43 | ; Top-level Entity Name ; can_test ; 44 | ; Family ; Cyclone IV E ; 45 | ; Device ; EP4CE6E22C8 ; 46 | +-----------------------+---------------------------------------+ 47 | 48 | 49 | +----------------------------------+ 50 | ; Assembler Settings ; 51 | +--------+---------+---------------+ 52 | ; Option ; Setting ; Default Value ; 53 | +--------+---------+---------------+ 54 | 55 | 56 | +------------------------------------------+ 57 | ; Assembler Generated Files ; 58 | +------------------------------------------+ 59 | ; File Name ; 60 | +------------------------------------------+ 61 | ; C:/hdl_projects/CAN/output_files/CAN.sof ; 62 | +------------------------------------------+ 63 | 64 | 65 | +--------------------------------------------------------------------+ 66 | ; Assembler Device Options: C:/hdl_projects/CAN/output_files/CAN.sof ; 67 | +----------------+---------------------------------------------------+ 68 | ; Option ; Setting ; 69 | +----------------+---------------------------------------------------+ 70 | ; JTAG usercode ; 0x000CF43D ; 71 | ; Checksum ; 0x000CF43D ; 72 | +----------------+---------------------------------------------------+ 73 | 74 | 75 | +--------------------+ 76 | ; Assembler Messages ; 77 | +--------------------+ 78 | Info: ******************************************************************* 79 | Info: Running Quartus Prime Assembler 80 | Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 81 | Info: Processing started: Fri Nov 06 16:17:37 2020 82 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off CAN -c CAN 83 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 84 | Info (115031): Writing out detailed assembly data for power analysis 85 | Info (115030): Assembler is generating device programming files 86 | Info: Quartus Prime Assembler was successful. 0 errors, 1 warning 87 | Info: Peak virtual memory: 4681 megabytes 88 | Info: Processing ended: Fri Nov 06 16:17:38 2020 89 | Info: Elapsed time: 00:00:01 90 | Info: Total CPU time (on all processors): 00:00:01 91 | 92 | 93 | -------------------------------------------------------------------------------- /output_files/CAN.cdf: -------------------------------------------------------------------------------- 1 | /* Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition */ 2 | JedecChain; 3 | FileRevision(JESD32A); 4 | DefaultMfr(6E); 5 | 6 | P ActionCode(Cfg) 7 | Device PartName(EP4CE6E22) Path("C:/hdl_projects/CAN/output_files/") File("CAN.sof") MfrSpec(OpMask(1)); 8 | 9 | ChainEnd; 10 | 11 | AlteraBegin; 12 | ChainType(JTAG); 13 | AlteraEnd; 14 | -------------------------------------------------------------------------------- /output_files/CAN.done: -------------------------------------------------------------------------------- 1 | Fri Nov 06 16:17:42 2020 2 | -------------------------------------------------------------------------------- /output_files/CAN.eda.rpt: -------------------------------------------------------------------------------- 1 | EDA Netlist Writer report for CAN 2 | Fri Oct 23 13:40:25 2020 3 | Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. EDA Netlist Writer Summary 11 | 3. Simulation Settings 12 | 4. Simulation Generated Files 13 | 5. EDA Netlist Writer Messages 14 | 15 | 16 | 17 | ---------------- 18 | ; Legal Notice ; 19 | ---------------- 20 | Copyright (C) 2020 Intel Corporation. All rights reserved. 21 | Your use of Intel Corporation's design tools, logic functions 22 | and other software and tools, and any partner logic 23 | functions, and any output files from any of the foregoing 24 | (including device programming or simulation files), and any 25 | associated documentation or information are expressly subject 26 | to the terms and conditions of the Intel Program License 27 | Subscription Agreement, the Intel Quartus Prime License Agreement, 28 | the Intel FPGA IP License Agreement, or other applicable license 29 | agreement, including, without limitation, that your use is for 30 | the sole purpose of programming logic devices manufactured by 31 | Intel and sold by Intel or its authorized distributors. Please 32 | refer to the applicable agreement for further details, at 33 | https://fpgasoftware.intel.com/eula. 34 | 35 | 36 | 37 | +-------------------------------------------------------------------+ 38 | ; EDA Netlist Writer Summary ; 39 | +---------------------------+---------------------------------------+ 40 | ; EDA Netlist Writer Status ; Successful - Fri Oct 23 13:40:25 2020 ; 41 | ; Revision Name ; CAN ; 42 | ; Top-level Entity Name ; can_top ; 43 | ; Family ; Cyclone IV E ; 44 | ; Simulation Files Creation ; Successful ; 45 | +---------------------------+---------------------------------------+ 46 | 47 | 48 | +-------------------------------------------------------------------------------------------------------------------------------+ 49 | ; Simulation Settings ; 50 | +---------------------------------------------------------------------------------------------------+---------------------------+ 51 | ; Option ; Setting ; 52 | +---------------------------------------------------------------------------------------------------+---------------------------+ 53 | ; Tool Name ; ModelSim-Altera (Verilog) ; 54 | ; Generate functional simulation netlist ; On ; 55 | ; Truncate long hierarchy paths ; Off ; 56 | ; Map illegal HDL characters ; Off ; 57 | ; Flatten buses into individual nodes ; Off ; 58 | ; Maintain hierarchy ; Off ; 59 | ; Bring out device-wide set/reset signals as ports ; Off ; 60 | ; Enable glitch filtering ; Off ; 61 | ; Do not write top level VHDL entity ; Off ; 62 | ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; 63 | ; Architecture name in VHDL output netlist ; structure ; 64 | ; Generate third-party EDA tool command script for RTL functional simulation ; Off ; 65 | ; Generate third-party EDA tool command script for gate-level simulation ; Off ; 66 | +---------------------------------------------------------------------------------------------------+---------------------------+ 67 | 68 | 69 | +---------------------------------------------+ 70 | ; Simulation Generated Files ; 71 | +---------------------------------------------+ 72 | ; Generated Files ; 73 | +---------------------------------------------+ 74 | ; C:/hdl_projects/Can/simulation/qsim//CAN.vo ; 75 | +---------------------------------------------+ 76 | 77 | 78 | +-----------------------------+ 79 | ; EDA Netlist Writer Messages ; 80 | +-----------------------------+ 81 | Info: ******************************************************************* 82 | Info: Running Quartus Prime EDA Netlist Writer 83 | Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 84 | Info: Copyright (C) 2020 Intel Corporation. All rights reserved. 85 | Info: Your use of Intel Corporation's design tools, logic functions 86 | Info: and other software and tools, and any partner logic 87 | Info: functions, and any output files from any of the foregoing 88 | Info: (including device programming or simulation files), and any 89 | Info: associated documentation or information are expressly subject 90 | Info: to the terms and conditions of the Intel Program License 91 | Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 92 | Info: the Intel FPGA IP License Agreement, or other applicable license 93 | Info: agreement, including, without limitation, that your use is for 94 | Info: the sole purpose of programming logic devices manufactured by 95 | Info: Intel and sold by Intel or its authorized distributors. Please 96 | Info: refer to the applicable agreement for further details, at 97 | Info: https://fpgasoftware.intel.com/eula. 98 | Info: Processing started: Fri Oct 23 13:40:25 2020 99 | Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/hdl_projects/Can/simulation/qsim/ CAN -c CAN 100 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 101 | Info (204019): Generated file CAN.vo in folder "C:/hdl_projects/Can/simulation/qsim//" for EDA simulation tool 102 | Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning 103 | Info: Peak virtual memory: 4638 megabytes 104 | Info: Processing ended: Fri Oct 23 13:40:25 2020 105 | Info: Elapsed time: 00:00:00 106 | Info: Total CPU time (on all processors): 00:00:01 107 | 108 | 109 | -------------------------------------------------------------------------------- /output_files/CAN.fit.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/output_files/CAN.fit.rpt -------------------------------------------------------------------------------- /output_files/CAN.fit.smsg: -------------------------------------------------------------------------------- 1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments 2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments 3 | Extra Info (176236): Started Fast Input/Output/OE register processing 4 | Extra Info (176237): Finished Fast Input/Output/OE register processing 5 | Extra Info (176238): Start inferring scan chains for DSP blocks 6 | Extra Info (176239): Inferring scan chains for DSP blocks is complete 7 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density 8 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks 9 | -------------------------------------------------------------------------------- /output_files/CAN.fit.summary: -------------------------------------------------------------------------------- 1 | Fitter Status : Successful - Fri Nov 06 16:17:36 2020 2 | Quartus Prime Version : 20.1.0 Build 711 06/05/2020 SJ Lite Edition 3 | Revision Name : CAN 4 | Top-level Entity Name : can_test 5 | Family : Cyclone IV E 6 | Device : EP4CE6E22C8 7 | Timing Models : Final 8 | Total logic elements : 411 / 6,272 ( 7 % ) 9 | Total combinational functions : 406 / 6,272 ( 6 % ) 10 | Dedicated logic registers : 160 / 6,272 ( 3 % ) 11 | Total registers : 160 12 | Total pins : 8 / 92 ( 9 % ) 13 | Total virtual pins : 0 14 | Total memory bits : 0 / 276,480 ( 0 % ) 15 | Embedded Multiplier 9-bit elements : 0 / 30 ( 0 % ) 16 | Total PLLs : 0 / 2 ( 0 % ) 17 | -------------------------------------------------------------------------------- /output_files/CAN.flow.rpt: -------------------------------------------------------------------------------- 1 | Flow report for CAN 2 | Fri Nov 06 16:17:41 2020 3 | Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 4 | 5 | 6 | --------------------- 7 | ; Table of Contents ; 8 | --------------------- 9 | 1. Legal Notice 10 | 2. Flow Summary 11 | 3. Flow Settings 12 | 4. Flow Non-Default Global Settings 13 | 5. Flow Elapsed Time 14 | 6. Flow OS Summary 15 | 7. Flow Log 16 | 8. Flow Messages 17 | 9. Flow Suppressed Messages 18 | 19 | 20 | 21 | ---------------- 22 | ; Legal Notice ; 23 | ---------------- 24 | Copyright (C) 2020 Intel Corporation. All rights reserved. 25 | Your use of Intel Corporation's design tools, logic functions 26 | and other software and tools, and any partner logic 27 | functions, and any output files from any of the foregoing 28 | (including device programming or simulation files), and any 29 | associated documentation or information are expressly subject 30 | to the terms and conditions of the Intel Program License 31 | Subscription Agreement, the Intel Quartus Prime License Agreement, 32 | the Intel FPGA IP License Agreement, or other applicable license 33 | agreement, including, without limitation, that your use is for 34 | the sole purpose of programming logic devices manufactured by 35 | Intel and sold by Intel or its authorized distributors. Please 36 | refer to the applicable agreement for further details, at 37 | https://fpgasoftware.intel.com/eula. 38 | 39 | 40 | 41 | +----------------------------------------------------------------------------------+ 42 | ; Flow Summary ; 43 | +------------------------------------+---------------------------------------------+ 44 | ; Flow Status ; Successful - Fri Nov 06 16:17:38 2020 ; 45 | ; Quartus Prime Version ; 20.1.0 Build 711 06/05/2020 SJ Lite Edition ; 46 | ; Revision Name ; CAN ; 47 | ; Top-level Entity Name ; can_test ; 48 | ; Family ; Cyclone IV E ; 49 | ; Device ; EP4CE6E22C8 ; 50 | ; Timing Models ; Final ; 51 | ; Total logic elements ; 411 / 6,272 ( 7 % ) ; 52 | ; Total combinational functions ; 406 / 6,272 ( 6 % ) ; 53 | ; Dedicated logic registers ; 160 / 6,272 ( 3 % ) ; 54 | ; Total registers ; 160 ; 55 | ; Total pins ; 8 / 92 ( 9 % ) ; 56 | ; Total virtual pins ; 0 ; 57 | ; Total memory bits ; 0 / 276,480 ( 0 % ) ; 58 | ; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 59 | ; Total PLLs ; 0 / 2 ( 0 % ) ; 60 | +------------------------------------+---------------------------------------------+ 61 | 62 | 63 | +-----------------------------------------+ 64 | ; Flow Settings ; 65 | +-------------------+---------------------+ 66 | ; Option ; Setting ; 67 | +-------------------+---------------------+ 68 | ; Start date & time ; 11/06/2020 16:17:19 ; 69 | ; Main task ; Compilation ; 70 | ; Revision Name ; CAN ; 71 | +-------------------+---------------------+ 72 | 73 | 74 | +-------------------------------------------------------------------------------------------------------------------------+ 75 | ; Flow Non-Default Global Settings ; 76 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 77 | ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; 78 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 79 | ; COMPILER_SIGNATURE_ID ; 30902513708070.160466863911164 ; -- ; -- ; -- ; 80 | ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; 81 | ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; 82 | ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; can_test ; Top ; 83 | ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; can_test ; Top ; 84 | ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; can_test ; Top ; 85 | ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; 86 | ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; 87 | ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; 88 | ; TOP_LEVEL_ENTITY ; can_test ; CAN ; -- ; -- ; 89 | +-------------------------------------+----------------------------------------+---------------+-------------+------------+ 90 | 91 | 92 | +--------------------------------------------------------------------------------------------------------------------------+ 93 | ; Flow Elapsed Time ; 94 | +----------------------+--------------+-------------------------+---------------------+------------------------------------+ 95 | ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; 96 | +----------------------+--------------+-------------------------+---------------------+------------------------------------+ 97 | ; Analysis & Synthesis ; 00:00:10 ; 1.0 ; 4764 MB ; 00:00:16 ; 98 | ; Fitter ; 00:00:07 ; 1.0 ; 5506 MB ; 00:00:06 ; 99 | ; Assembler ; 00:00:01 ; 1.0 ; 4680 MB ; 00:00:01 ; 100 | ; Timing Analyzer ; 00:00:02 ; 1.0 ; 4760 MB ; 00:00:01 ; 101 | ; Total ; 00:00:20 ; -- ; -- ; 00:00:24 ; 102 | +----------------------+--------------+-------------------------+---------------------+------------------------------------+ 103 | 104 | 105 | +------------------------------------------------------------------------------------+ 106 | ; Flow OS Summary ; 107 | +----------------------+------------------+------------+------------+----------------+ 108 | ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; 109 | +----------------------+------------------+------------+------------+----------------+ 110 | ; Analysis & Synthesis ; DESKTOP-N4TIN40 ; Windows 10 ; 10.0 ; x86_64 ; 111 | ; Fitter ; DESKTOP-N4TIN40 ; Windows 10 ; 10.0 ; x86_64 ; 112 | ; Assembler ; DESKTOP-N4TIN40 ; Windows 10 ; 10.0 ; x86_64 ; 113 | ; Timing Analyzer ; DESKTOP-N4TIN40 ; Windows 10 ; 10.0 ; x86_64 ; 114 | +----------------------+------------------+------------+------------+----------------+ 115 | 116 | 117 | ------------ 118 | ; Flow Log ; 119 | ------------ 120 | quartus_map --read_settings_files=on --write_settings_files=off CAN -c CAN 121 | quartus_fit --read_settings_files=off --write_settings_files=off CAN -c CAN 122 | quartus_asm --read_settings_files=off --write_settings_files=off CAN -c CAN 123 | quartus_sta CAN -c CAN 124 | 125 | 126 | 127 | -------------------------------------------------------------------------------- /output_files/CAN.jdi: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | -------------------------------------------------------------------------------- /output_files/CAN.map.smsg: -------------------------------------------------------------------------------- 1 | Info (10281): Verilog HDL Declaration information at can_top.v(15): object "LOCAL_ADDRESS" differs only in case from object "local_address" in the same scope File: C:/hdl_projects/CAN/can_top.v Line: 15 2 | Info (10281): Verilog HDL Declaration information at can_tx.v(23): object "tx_data" differs only in case from object "TX_DATA" in the same scope File: C:/hdl_projects/CAN/can_tx.v Line: 23 3 | Info (10281): Verilog HDL Declaration information at can_rx.v(151): object "rx_message_type" differs only in case from object "RX_MESSAGE_TYPE" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 151 4 | Info (10281): Verilog HDL Declaration information at can_rx.v(152): object "rx_address_local" differs only in case from object "RX_ADDRESS_LOCAL" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 152 5 | Info (10281): Verilog HDL Declaration information at can_rx.v(153): object "rx_address_remote" differs only in case from object "RX_ADDRESS_REMOTE" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 153 6 | Info (10281): Verilog HDL Declaration information at can_rx.v(154): object "rx_handshaking_p" differs only in case from object "RX_HANDSHAKING_P" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 154 7 | Info (10281): Verilog HDL Declaration information at can_rx.v(155): object "rx_atribute_reserved" differs only in case from object "RX_ATRIBUTE_RESERVED" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 155 8 | Info (10281): Verilog HDL Declaration information at can_rx.v(156): object "rx_expand_count" differs only in case from object "RX_EXPAND_COUNT" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 156 9 | Info (10281): Verilog HDL Declaration information at can_rx.v(157): object "rx_cmd_data_sign" differs only in case from object "RX_CMD_DATA_SIGN" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 157 10 | Info (10281): Verilog HDL Declaration information at can_rx.v(158): object "rx_dlc" differs only in case from object "RX_DLC" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 158 11 | Info (10281): Verilog HDL Declaration information at can_rx.v(26): object "rx_data" differs only in case from object "RX_DATA" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 26 12 | Info (10281): Verilog HDL Declaration information at can_rx.v(159): object "rx_crc" differs only in case from object "RX_CRC" in the same scope File: C:/hdl_projects/CAN/can_rx.v Line: 159 13 | -------------------------------------------------------------------------------- /output_files/CAN.map.summary: -------------------------------------------------------------------------------- 1 | Analysis & Synthesis Status : Successful - Fri Nov 06 16:17:28 2020 2 | Quartus Prime Version : 20.1.0 Build 711 06/05/2020 SJ Lite Edition 3 | Revision Name : CAN 4 | Top-level Entity Name : can_test 5 | Family : Cyclone IV E 6 | Total logic elements : 417 7 | Total combinational functions : 406 8 | Dedicated logic registers : 160 9 | Total registers : 160 10 | Total pins : 8 11 | Total virtual pins : 0 12 | Total memory bits : 0 13 | Embedded Multiplier 9-bit elements : 0 14 | Total PLLs : 0 15 | -------------------------------------------------------------------------------- /output_files/CAN.pin: -------------------------------------------------------------------------------- 1 | -- Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | -- Your use of Intel Corporation's design tools, logic functions 3 | -- and other software and tools, and any partner logic 4 | -- functions, and any output files from any of the foregoing 5 | -- (including device programming or simulation files), and any 6 | -- associated documentation or information are expressly subject 7 | -- to the terms and conditions of the Intel Program License 8 | -- Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | -- the Intel FPGA IP License Agreement, or other applicable license 10 | -- agreement, including, without limitation, that your use is for 11 | -- the sole purpose of programming logic devices manufactured by 12 | -- Intel and sold by Intel or its authorized distributors. Please 13 | -- refer to the applicable agreement for further details, at 14 | -- https://fpgasoftware.intel.com/eula. 15 | -- 16 | -- This is a Quartus Prime output file. It is for reporting purposes only, and is 17 | -- not intended for use as a Quartus Prime input file. This file cannot be used 18 | -- to make Quartus Prime pin assignments - for instructions on how to make pin 19 | -- assignments, please see Quartus Prime help. 20 | --------------------------------------------------------------------------------- 21 | 22 | 23 | 24 | --------------------------------------------------------------------------------- 25 | -- NC : No Connect. This pin has no internal connection to the device. 26 | -- DNU : Do Not Use. This pin MUST NOT be connected. 27 | -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). 28 | -- VCCIO : Dedicated power pin, which MUST be connected to VCC 29 | -- of its bank. 30 | -- Bank 1: 3.3V 31 | -- Bank 2: 3.3V 32 | -- Bank 3: 2.5V 33 | -- Bank 4: 2.5V 34 | -- Bank 5: 2.5V 35 | -- Bank 6: 2.5V 36 | -- Bank 7: 2.5V 37 | -- Bank 8: 2.5V 38 | -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. 39 | -- It can also be used to report unused dedicated pins. The connection 40 | -- on the board for unused dedicated pins depends on whether this will 41 | -- be used in a future design. One example is device migration. When 42 | -- using device migration, refer to the device pin-tables. If it is a 43 | -- GND pin in the pin table or if it will not be used in a future design 44 | -- for another purpose the it MUST be connected to GND. If it is an unused 45 | -- dedicated pin, then it can be connected to a valid signal on the board 46 | -- (low, high, or toggling) if that signal is required for a different 47 | -- revision of the design. 48 | -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. 49 | -- This pin should be connected to GND. It may also be connected to a 50 | -- valid signal on the board (low, high, or toggling) if that signal 51 | -- is required for a different revision of the design. 52 | -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND 53 | -- or leave it unconnected. 54 | -- RESERVED : Unused I/O pin, which MUST be left unconnected. 55 | -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. 56 | -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. 57 | -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. 58 | -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. 59 | --------------------------------------------------------------------------------- 60 | 61 | 62 | 63 | --------------------------------------------------------------------------------- 64 | -- Pin directions (input, output or bidir) are based on device operating in user mode. 65 | --------------------------------------------------------------------------------- 66 | 67 | Quartus Prime Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 68 | CHIP "CAN" ASSIGNED TO AN: EP4CE6E22C8 69 | 70 | Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment 71 | ------------------------------------------------------------------------------------------------------------- 72 | RESERVED_INPUT_WITH_WEAK_PULLUP : 1 : : : : 1 : 73 | RESERVED_INPUT_WITH_WEAK_PULLUP : 2 : : : : 1 : 74 | RESERVED_INPUT_WITH_WEAK_PULLUP : 3 : : : : 1 : 75 | GND : 4 : gnd : : : : 76 | VCCINT : 5 : power : : 1.2V : : 77 | ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 6 : input : 3.3-V LVTTL : : 1 : N 78 | RESERVED_INPUT_WITH_WEAK_PULLUP : 7 : : : : 1 : 79 | ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 8 : input : 3.3-V LVTTL : : 1 : N 80 | nSTATUS : 9 : : : : 1 : 81 | RESERVED_INPUT_WITH_WEAK_PULLUP : 10 : : : : 1 : 82 | RESERVED_INPUT_WITH_WEAK_PULLUP : 11 : : : : 1 : 83 | ~ALTERA_DCLK~ : 12 : output : 3.3-V LVTTL : : 1 : N 84 | ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : 13 : input : 3.3-V LVTTL : : 1 : N 85 | nCONFIG : 14 : : : : 1 : 86 | TDI : 15 : input : : : 1 : 87 | TCK : 16 : input : : : 1 : 88 | VCCIO1 : 17 : power : : 3.3V : 1 : 89 | TMS : 18 : input : : : 1 : 90 | GND : 19 : gnd : : : : 91 | TDO : 20 : output : : : 1 : 92 | nCE : 21 : : : : 1 : 93 | GND : 22 : gnd : : : : 94 | clk_i : 23 : input : 3.3-V LVTTL : : 1 : Y 95 | GND+ : 24 : : : : 2 : 96 | rst_i : 25 : input : 3.3-V LVCMOS : : 2 : Y 97 | VCCIO2 : 26 : power : : 3.3V : 2 : 98 | GND : 27 : gnd : : : : 99 | tx_o : 28 : output : 3.3-V LVCMOS : : 2 : Y 100 | VCCINT : 29 : power : : 1.2V : : 101 | rx_i : 30 : input : 3.3-V LVCMOS : : 2 : Y 102 | test_rx_rx : 31 : output : 3.3-V LVTTL : : 2 : Y 103 | rx_busy : 32 : output : 3.3-V LVCMOS : : 2 : Y 104 | test_sample : 33 : output : 3.3-V LVCMOS : : 2 : Y 105 | RESERVED_INPUT_WITH_WEAK_PULLUP : 34 : : : : 2 : 106 | VCCA1 : 35 : power : : 2.5V : : 107 | GNDA1 : 36 : gnd : : : : 108 | VCCD_PLL1 : 37 : power : : 1.2V : : 109 | RESERVED_INPUT_WITH_WEAK_PULLUP : 38 : : : : 3 : 110 | RESERVED_INPUT_WITH_WEAK_PULLUP : 39 : : : : 3 : 111 | VCCIO3 : 40 : power : : 2.5V : 3 : 112 | GND : 41 : gnd : : : : 113 | RESERVED_INPUT_WITH_WEAK_PULLUP : 42 : : : : 3 : 114 | RESERVED_INPUT_WITH_WEAK_PULLUP : 43 : : : : 3 : 115 | RESERVED_INPUT_WITH_WEAK_PULLUP : 44 : : : : 3 : 116 | VCCINT : 45 : power : : 1.2V : : 117 | RESERVED_INPUT_WITH_WEAK_PULLUP : 46 : : : : 3 : 118 | VCCIO3 : 47 : power : : 2.5V : 3 : 119 | GND : 48 : gnd : : : : 120 | RESERVED_INPUT_WITH_WEAK_PULLUP : 49 : : : : 3 : 121 | RESERVED_INPUT_WITH_WEAK_PULLUP : 50 : : : : 3 : 122 | RESERVED_INPUT_WITH_WEAK_PULLUP : 51 : : : : 3 : 123 | RESERVED_INPUT_WITH_WEAK_PULLUP : 52 : : : : 3 : 124 | RESERVED_INPUT_WITH_WEAK_PULLUP : 53 : : : : 3 : 125 | RESERVED_INPUT_WITH_WEAK_PULLUP : 54 : : : : 4 : 126 | RESERVED_INPUT_WITH_WEAK_PULLUP : 55 : : : : 4 : 127 | VCCIO4 : 56 : power : : 2.5V : 4 : 128 | GND : 57 : gnd : : : : 129 | RESERVED_INPUT_WITH_WEAK_PULLUP : 58 : : : : 4 : 130 | RESERVED_INPUT_WITH_WEAK_PULLUP : 59 : : : : 4 : 131 | RESERVED_INPUT_WITH_WEAK_PULLUP : 60 : : : : 4 : 132 | VCCINT : 61 : power : : 1.2V : : 133 | VCCIO4 : 62 : power : : 2.5V : 4 : 134 | GND : 63 : gnd : : : : 135 | tx_busy : 64 : output : 2.5 V : : 4 : N 136 | RESERVED_INPUT_WITH_WEAK_PULLUP : 65 : : : : 4 : 137 | RESERVED_INPUT_WITH_WEAK_PULLUP : 66 : : : : 4 : 138 | RESERVED_INPUT_WITH_WEAK_PULLUP : 67 : : : : 4 : 139 | RESERVED_INPUT_WITH_WEAK_PULLUP : 68 : : : : 4 : 140 | RESERVED_INPUT_WITH_WEAK_PULLUP : 69 : : : : 4 : 141 | RESERVED_INPUT_WITH_WEAK_PULLUP : 70 : : : : 4 : 142 | RESERVED_INPUT_WITH_WEAK_PULLUP : 71 : : : : 4 : 143 | RESERVED_INPUT_WITH_WEAK_PULLUP : 72 : : : : 4 : 144 | RESERVED_INPUT_WITH_WEAK_PULLUP : 73 : : : : 5 : 145 | RESERVED_INPUT_WITH_WEAK_PULLUP : 74 : : : : 5 : 146 | RESERVED_INPUT_WITH_WEAK_PULLUP : 75 : : : : 5 : 147 | RESERVED_INPUT_WITH_WEAK_PULLUP : 76 : : : : 5 : 148 | RESERVED_INPUT_WITH_WEAK_PULLUP : 77 : : : : 5 : 149 | VCCINT : 78 : power : : 1.2V : : 150 | GND : 79 : gnd : : : : 151 | RESERVED_INPUT_WITH_WEAK_PULLUP : 80 : : : : 5 : 152 | VCCIO5 : 81 : power : : 2.5V : 5 : 153 | GND : 82 : gnd : : : : 154 | RESERVED_INPUT_WITH_WEAK_PULLUP : 83 : : : : 5 : 155 | RESERVED_INPUT_WITH_WEAK_PULLUP : 84 : : : : 5 : 156 | RESERVED_INPUT_WITH_WEAK_PULLUP : 85 : : : : 5 : 157 | RESERVED_INPUT_WITH_WEAK_PULLUP : 86 : : : : 5 : 158 | RESERVED_INPUT_WITH_WEAK_PULLUP : 87 : : : : 5 : 159 | GND+ : 88 : : : : 5 : 160 | GND+ : 89 : : : : 5 : 161 | GND+ : 90 : : : : 6 : 162 | GND+ : 91 : : : : 6 : 163 | CONF_DONE : 92 : : : : 6 : 164 | VCCIO6 : 93 : power : : 2.5V : 6 : 165 | MSEL0 : 94 : : : : 6 : 166 | GND : 95 : gnd : : : : 167 | MSEL1 : 96 : : : : 6 : 168 | MSEL2 : 97 : : : : 6 : 169 | RESERVED_INPUT_WITH_WEAK_PULLUP : 98 : : : : 6 : 170 | RESERVED_INPUT_WITH_WEAK_PULLUP : 99 : : : : 6 : 171 | RESERVED_INPUT_WITH_WEAK_PULLUP : 100 : : : : 6 : 172 | ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : 101 : output : 2.5 V : : 6 : N 173 | VCCINT : 102 : power : : 1.2V : : 174 | RESERVED_INPUT_WITH_WEAK_PULLUP : 103 : : : : 6 : 175 | RESERVED_INPUT_WITH_WEAK_PULLUP : 104 : : : : 6 : 176 | RESERVED_INPUT_WITH_WEAK_PULLUP : 105 : : : : 6 : 177 | RESERVED_INPUT_WITH_WEAK_PULLUP : 106 : : : : 6 : 178 | VCCA2 : 107 : power : : 2.5V : : 179 | GNDA2 : 108 : gnd : : : : 180 | VCCD_PLL2 : 109 : power : : 1.2V : : 181 | RESERVED_INPUT_WITH_WEAK_PULLUP : 110 : : : : 7 : 182 | RESERVED_INPUT_WITH_WEAK_PULLUP : 111 : : : : 7 : 183 | RESERVED_INPUT_WITH_WEAK_PULLUP : 112 : : : : 7 : 184 | RESERVED_INPUT_WITH_WEAK_PULLUP : 113 : : : : 7 : 185 | RESERVED_INPUT_WITH_WEAK_PULLUP : 114 : : : : 7 : 186 | RESERVED_INPUT_WITH_WEAK_PULLUP : 115 : : : : 7 : 187 | VCCINT : 116 : power : : 1.2V : : 188 | VCCIO7 : 117 : power : : 2.5V : 7 : 189 | GND : 118 : gnd : : : : 190 | RESERVED_INPUT_WITH_WEAK_PULLUP : 119 : : : : 7 : 191 | RESERVED_INPUT_WITH_WEAK_PULLUP : 120 : : : : 7 : 192 | RESERVED_INPUT_WITH_WEAK_PULLUP : 121 : : : : 7 : 193 | VCCIO7 : 122 : power : : 2.5V : 7 : 194 | GND : 123 : gnd : : : : 195 | RESERVED_INPUT_WITH_WEAK_PULLUP : 124 : : : : 7 : 196 | RESERVED_INPUT_WITH_WEAK_PULLUP : 125 : : : : 7 : 197 | RESERVED_INPUT_WITH_WEAK_PULLUP : 126 : : : : 7 : 198 | RESERVED_INPUT_WITH_WEAK_PULLUP : 127 : : : : 7 : 199 | RESERVED_INPUT_WITH_WEAK_PULLUP : 128 : : : : 8 : 200 | RESERVED_INPUT_WITH_WEAK_PULLUP : 129 : : : : 8 : 201 | VCCIO8 : 130 : power : : 2.5V : 8 : 202 | GND : 131 : gnd : : : : 203 | RESERVED_INPUT_WITH_WEAK_PULLUP : 132 : : : : 8 : 204 | RESERVED_INPUT_WITH_WEAK_PULLUP : 133 : : : : 8 : 205 | VCCINT : 134 : power : : 1.2V : : 206 | RESERVED_INPUT_WITH_WEAK_PULLUP : 135 : : : : 8 : 207 | RESERVED_INPUT_WITH_WEAK_PULLUP : 136 : : : : 8 : 208 | RESERVED_INPUT_WITH_WEAK_PULLUP : 137 : : : : 8 : 209 | RESERVED_INPUT_WITH_WEAK_PULLUP : 138 : : : : 8 : 210 | VCCIO8 : 139 : power : : 2.5V : 8 : 211 | GND : 140 : gnd : : : : 212 | RESERVED_INPUT_WITH_WEAK_PULLUP : 141 : : : : 8 : 213 | RESERVED_INPUT_WITH_WEAK_PULLUP : 142 : : : : 8 : 214 | RESERVED_INPUT_WITH_WEAK_PULLUP : 143 : : : : 8 : 215 | RESERVED_INPUT_WITH_WEAK_PULLUP : 144 : : : : 8 : 216 | GND : EPAD : : : : : 217 | -------------------------------------------------------------------------------- /output_files/CAN.sld: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /output_files/CAN.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/output_files/CAN.sof -------------------------------------------------------------------------------- /output_files/CAN.sta.summary: -------------------------------------------------------------------------------- 1 | ------------------------------------------------------------ 2 | Timing Analyzer Summary 3 | ------------------------------------------------------------ 4 | 5 | Type : Slow 1200mV 85C Model Setup 'clk_i' 6 | Slack : -5.287 7 | TNS : -320.248 8 | 9 | Type : Slow 1200mV 85C Model Setup 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 10 | Slack : -5.006 11 | TNS : -241.470 12 | 13 | Type : Slow 1200mV 85C Model Hold 'clk_i' 14 | Slack : 0.431 15 | TNS : 0.000 16 | 17 | Type : Slow 1200mV 85C Model Hold 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 18 | Slack : 0.435 19 | TNS : 0.000 20 | 21 | Type : Slow 1200mV 85C Model Recovery 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 22 | Slack : -1.148 23 | TNS : -16.894 24 | 25 | Type : Slow 1200mV 85C Model Removal 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 26 | Slack : 1.488 27 | TNS : 0.000 28 | 29 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'clk_i' 30 | Slack : -3.000 31 | TNS : -135.343 32 | 33 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 34 | Slack : -1.487 35 | TNS : -105.577 36 | 37 | Type : Slow 1200mV 0C Model Setup 'clk_i' 38 | Slack : -4.871 39 | TNS : -293.527 40 | 41 | Type : Slow 1200mV 0C Model Setup 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 42 | Slack : -4.651 43 | TNS : -221.327 44 | 45 | Type : Slow 1200mV 0C Model Hold 'clk_i' 46 | Slack : 0.381 47 | TNS : 0.000 48 | 49 | Type : Slow 1200mV 0C Model Hold 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 50 | Slack : 0.387 51 | TNS : 0.000 52 | 53 | Type : Slow 1200mV 0C Model Recovery 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 54 | Slack : -0.983 55 | TNS : -14.369 56 | 57 | Type : Slow 1200mV 0C Model Removal 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 58 | Slack : 1.368 59 | TNS : 0.000 60 | 61 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'clk_i' 62 | Slack : -3.000 63 | TNS : -135.343 64 | 65 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 66 | Slack : -1.487 67 | TNS : -105.577 68 | 69 | Type : Fast 1200mV 0C Model Setup 'clk_i' 70 | Slack : -1.635 71 | TNS : -89.785 72 | 73 | Type : Fast 1200mV 0C Model Setup 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 74 | Slack : -1.587 75 | TNS : -63.235 76 | 77 | Type : Fast 1200mV 0C Model Hold 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 78 | Slack : 0.176 79 | TNS : 0.000 80 | 81 | Type : Fast 1200mV 0C Model Hold 'clk_i' 82 | Slack : 0.177 83 | TNS : 0.000 84 | 85 | Type : Fast 1200mV 0C Model Recovery 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 86 | Slack : 0.039 87 | TNS : 0.000 88 | 89 | Type : Fast 1200mV 0C Model Removal 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 90 | Slack : 0.629 91 | TNS : 0.000 92 | 93 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'clk_i' 94 | Slack : -3.000 95 | TNS : -119.608 96 | 97 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'can_top:can_top_inst|can_clk:can_clk_instance|can_clk_o_reg' 98 | Slack : -1.000 99 | TNS : -71.000 100 | 101 | ------------------------------------------------------------ 102 | -------------------------------------------------------------------------------- /pmramif.v: -------------------------------------------------------------------------------- 1 | module PMRAMIF 2 | #( 3 | parameter DATA_WIDTH = 32, 4 | parameter ADDR_WIDTH = 20, 5 | parameter CLK_FREQUENCY = 200_000_000, 6 | parameter OP_CYCLE_NS = 35 7 | )( 8 | input clk, 9 | input rst, 10 | 11 | input [DATA_WIDTH-1 : 0] data_wr, 12 | input [ADDR_WIDTH-1 : 0] addr_wr, 13 | input wr_en, 14 | output reg wr_done, 15 | output reg wr_busy, 16 | 17 | output reg [DATA_WIDTH-1 : 0] data_rd, 18 | input [ADDR_WIDTH-1 : 0] addr_rd, 19 | input rd_en, 20 | output reg rd_done, 21 | output reg rd_busy, 22 | 23 | 24 | inout [DATA_WIDTH-1 : 0] mram_data, 25 | output reg [ADDR_WIDTH-1 : 0] mram_addr, 26 | output reg mram_ng, 27 | output reg mram_nw, 28 | output reg mram_nce 29 | ); 30 | 31 | function integer clog2; 32 | input integer value; 33 | begin 34 | value = value-1; 35 | for ( clog2 = 0; value > 0; clog2 = clog2+1 ) begin 36 | value = value >> 1; 37 | end 38 | end 39 | endfunction 40 | 41 | 42 | 43 | 44 | localparam CLK_PERIOD_NS = 1_000_000_000 / CLK_FREQUENCY; 45 | localparam OP_CLK_CYCLES = (OP_CYCLE_NS + CLK_PERIOD_NS - 1) / CLK_PERIOD_NS; 46 | localparam OP_COUNTER_WIDTH = clog2(OP_CLK_CYCLES + 1); 47 | 48 | 49 | 50 | 51 | wire op_done; 52 | wire begin_op; 53 | 54 | 55 | 56 | 57 | reg [DATA_WIDTH-1 : 0] data_wr_reg; 58 | reg [ADDR_WIDTH-1 : 0] addr_wr_reg; 59 | reg [ADDR_WIDTH-1 : 0] addr_rd_reg; 60 | 61 | reg [OP_COUNTER_WIDTH-1 : 0] op_counter = 0; 62 | reg op_counter_en = 1'b0; 63 | 64 | 65 | 66 | 67 | assign mram_data = mram_nw ? { DATA_WIDTH {1'bz} } : data_wr_reg; 68 | 69 | assign op_done = (op_counter == OP_CLK_CYCLES); 70 | assign begin_op = (op_counter == 0); 71 | 72 | 73 | 74 | 75 | always @( posedge clk ) begin 76 | if ( op_counter_en ) begin 77 | if ( op_counter < OP_CLK_CYCLES ) begin 78 | op_counter <= op_counter + 1'b1; 79 | end else begin 80 | op_counter <= 0; 81 | end 82 | end else begin 83 | op_counter <= 0; 84 | end 85 | end 86 | 87 | always @( posedge clk ) begin 88 | case (STATE) 89 | IDLE : begin 90 | mram_nce <= 1'b1; 91 | mram_nw <= 1'b1; 92 | mram_ng <= 1'b1; 93 | end 94 | 95 | MRAM_WRITE : begin 96 | if ( begin_op ) begin 97 | mram_addr <= addr_wr_reg; 98 | 99 | mram_nce <= 1'b0; 100 | mram_ng <= 1'b1; 101 | mram_nw <= 1'b0; 102 | end else begin 103 | if ( op_done ) begin 104 | mram_ng <= 1'b1; 105 | mram_nw <= 1'b1; 106 | end 107 | end 108 | end 109 | 110 | MRAM_READ : begin 111 | if ( begin_op ) begin 112 | mram_addr <= addr_rd_reg; 113 | 114 | mram_nce <= 1'b0; 115 | mram_ng <= 1'b0; 116 | mram_nw <= 1'b1; 117 | end else begin 118 | if ( op_done ) begin 119 | mram_nce <= 1'b1; 120 | mram_ng <= 1'b1; 121 | end 122 | end 123 | end 124 | default: begin 125 | mram_nce <= 1'b1; 126 | mram_nw <= 1'b1; 127 | mram_ng <= 1'b1; 128 | end 129 | endcase 130 | end 131 | 132 | 133 | 134 | 135 | 136 | 137 | localparam IDLE = 0; 138 | localparam MRAM_WRITE = 1; 139 | localparam MRAM_READ = 2; 140 | 141 | reg [1:0] STATE; 142 | 143 | always @( posedge clk ) begin 144 | if ( rst ) begin 145 | STATE <= IDLE; 146 | end else begin 147 | case (STATE) 148 | IDLE : begin 149 | if ( wr_en ) begin 150 | data_wr_reg <= data_wr; 151 | addr_wr_reg <= addr_wr; 152 | wr_busy <= 1'b1; 153 | 154 | op_counter_en <= 1'b1; 155 | STATE <= MRAM_WRITE; 156 | end else begin 157 | if ( rd_en ) begin 158 | addr_rd_reg <= addr_rd; 159 | rd_busy <= 1'b1; 160 | 161 | op_counter_en <= 1'b1; 162 | STATE <= MRAM_READ; 163 | end else begin 164 | wr_done <= 1'b0; 165 | rd_done <= 1'b0; 166 | op_counter_en <= 1'b0; 167 | wr_busy <= 1'b0; 168 | rd_busy <= 1'b0; 169 | data_wr_reg <= 0; 170 | addr_wr_reg <= 0; 171 | addr_rd_reg <= 0; 172 | end 173 | end 174 | end 175 | 176 | MRAM_WRITE: begin 177 | if ( op_done ) begin 178 | wr_done <= 1'b1; 179 | wr_busy <= 1'b0; 180 | 181 | op_counter_en <= 1'b0; 182 | if ( rd_en ) begin 183 | addr_rd_reg <= addr_rd; 184 | rd_busy <= 1'b1; 185 | 186 | op_counter_en <= 1'b1; 187 | STATE <= MRAM_READ; 188 | end else begin 189 | STATE <= IDLE; 190 | end 191 | end 192 | rd_done <= 1'b0; 193 | end 194 | 195 | MRAM_READ: begin 196 | if ( op_done ) begin 197 | rd_done <= 1'b1; 198 | rd_busy <= 1'b0; 199 | data_rd <= mram_data; 200 | 201 | op_counter_en <= 1'b0; 202 | if ( wr_en ) begin 203 | data_wr_reg <= data_wr; 204 | addr_wr_reg <= addr_wr; 205 | wr_busy <= 1'b1; 206 | 207 | op_counter_en <= 1'b1; 208 | STATE <= MRAM_WRITE; 209 | end else begin 210 | STATE <= IDLE; 211 | end 212 | end 213 | wr_done <= 1'b0; 214 | end 215 | default: begin 216 | STATE <= IDLE; 217 | end 218 | endcase 219 | end 220 | end 221 | 222 | 223 | 224 | 225 | endmodule 226 | 227 | -------------------------------------------------------------------------------- /simulation/qsim/.gitignore: -------------------------------------------------------------------------------- 1 | *.vwf -------------------------------------------------------------------------------- /simulation/qsim/CAN.do: -------------------------------------------------------------------------------- 1 | onerror {exit -code 1} 2 | vlib work 3 | vlog -work work CAN.vo 4 | vlog -work work Waveform1.vwf.vt 5 | vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.can_top_vlg_vec_tst 6 | vcd file -direction CAN.msim.vcd 7 | vcd add -internal can_top_vlg_vec_tst/* 8 | vcd add -internal can_top_vlg_vec_tst/i1/* 9 | proc simTimestamp {} { 10 | echo "Simulation time: $::now ps" 11 | if { [string equal running [runStatus]] } { 12 | after 2500 simTimestamp 13 | } 14 | } 15 | after 2500 simTimestamp 16 | run -all 17 | quit -f 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /simulation/qsim/CAN.sft: -------------------------------------------------------------------------------- 1 | set tool_name "ModelSim-Altera (Verilog)" 2 | -------------------------------------------------------------------------------- /simulation/qsim/Waveform.vwf.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and any partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details, at 14 | // https://fpgasoftware.intel.com/eula. 15 | 16 | // ***************************************************************************** 17 | // This file contains a Verilog test bench with test vectors .The test vectors 18 | // are exported from a vector file in the Quartus Waveform Editor and apply to 19 | // the top level entity of the current Quartus project .The user can use this 20 | // testbench to simulate his design using a third-party simulation tool . 21 | // ***************************************************************************** 22 | // Generated on "10/06/2020 18:54:53" 23 | 24 | // Verilog Test Bench (with test vectors) for design : can_top 25 | // 26 | // Simulation tool : 3rd Party 27 | // 28 | 29 | `timescale 1 ps/ 1 ps 30 | module can_top_vlg_vec_tst(); 31 | // constants 32 | // general purpose registers 33 | reg [5:0] address_recipient; 34 | reg [5:0] address_sender; 35 | reg clk_i; 36 | reg command_or_data; 37 | reg [63:0] data_b_i; 38 | reg [3:0] data_l_i; 39 | reg rst_i; 40 | reg rx_i; 41 | reg [1:0] sign; 42 | reg type; 43 | // wires 44 | wire [7:0] bit_count; 45 | wire bit_stuffed; 46 | wire [7:0] data_o; 47 | wire rx_busy; 48 | wire [3:0] test_bit_pol_count; 49 | wire [2:0] test_can_state; 50 | wire [7:0] test_can_tx_state; 51 | wire test_clk_can; 52 | wire test_last_bit; 53 | wire tx_busy; 54 | wire tx_o; 55 | 56 | // assign statements (if any) 57 | can_top i1 ( 58 | // port map - connection between master ports and signals/registers 59 | .address_recipient(address_recipient), 60 | .address_sender(address_sender), 61 | .bit_count(bit_count), 62 | .bit_stuffed(bit_stuffed), 63 | .clk_i(clk_i), 64 | .command_or_data(command_or_data), 65 | .data_b_i(data_b_i), 66 | .data_l_i(data_l_i), 67 | .data_o(data_o), 68 | .rst_i(rst_i), 69 | .rx_busy(rx_busy), 70 | .rx_i(rx_i), 71 | .sign(sign), 72 | .test_bit_pol_count(test_bit_pol_count), 73 | .test_can_state(test_can_state), 74 | .test_can_tx_state(test_can_tx_state), 75 | .test_clk_can(test_clk_can), 76 | .test_last_bit(test_last_bit), 77 | .tx_busy(tx_busy), 78 | .tx_o(tx_o), 79 | .\type (type) 80 | ); 81 | initial 82 | begin 83 | #1000000 $finish; 84 | end 85 | // address_recipient[ 5 ] 86 | initial 87 | begin 88 | address_recipient[5] = 1'b0; 89 | end 90 | // address_recipient[ 4 ] 91 | initial 92 | begin 93 | address_recipient[4] = 1'b0; 94 | end 95 | // address_recipient[ 3 ] 96 | initial 97 | begin 98 | address_recipient[3] = 1'b0; 99 | end 100 | // address_recipient[ 2 ] 101 | initial 102 | begin 103 | address_recipient[2] = 1'b0; 104 | end 105 | // address_recipient[ 1 ] 106 | initial 107 | begin 108 | address_recipient[1] = 1'b0; 109 | end 110 | // address_recipient[ 0 ] 111 | initial 112 | begin 113 | address_recipient[0] = 1'b0; 114 | end 115 | // address_sender[ 5 ] 116 | initial 117 | begin 118 | address_sender[5] = 1'b0; 119 | end 120 | // address_sender[ 4 ] 121 | initial 122 | begin 123 | address_sender[4] = 1'b0; 124 | end 125 | // address_sender[ 3 ] 126 | initial 127 | begin 128 | address_sender[3] = 1'b0; 129 | end 130 | // address_sender[ 2 ] 131 | initial 132 | begin 133 | address_sender[2] = 1'b0; 134 | end 135 | // address_sender[ 1 ] 136 | initial 137 | begin 138 | address_sender[1] = 1'b0; 139 | end 140 | // address_sender[ 0 ] 141 | initial 142 | begin 143 | address_sender[0] = 1'b0; 144 | end 145 | 146 | // clk_i 147 | always 148 | begin 149 | clk_i = 1'b0; 150 | clk_i = #50 1'b1; 151 | #50; 152 | end 153 | 154 | // command_or_data 155 | initial 156 | begin 157 | command_or_data = 1'b0; 158 | end 159 | // data_b_i[ 63 ] 160 | initial 161 | begin 162 | data_b_i[63] = 1'b0; 163 | end 164 | // data_b_i[ 62 ] 165 | initial 166 | begin 167 | data_b_i[62] = 1'b0; 168 | end 169 | // data_b_i[ 61 ] 170 | initial 171 | begin 172 | data_b_i[61] = 1'b0; 173 | end 174 | // data_b_i[ 60 ] 175 | initial 176 | begin 177 | data_b_i[60] = 1'b0; 178 | end 179 | // data_b_i[ 59 ] 180 | initial 181 | begin 182 | data_b_i[59] = 1'b0; 183 | end 184 | // data_b_i[ 58 ] 185 | initial 186 | begin 187 | data_b_i[58] = 1'b0; 188 | end 189 | // data_b_i[ 57 ] 190 | initial 191 | begin 192 | data_b_i[57] = 1'b0; 193 | end 194 | // data_b_i[ 56 ] 195 | initial 196 | begin 197 | data_b_i[56] = 1'b0; 198 | end 199 | // data_b_i[ 55 ] 200 | initial 201 | begin 202 | data_b_i[55] = 1'b0; 203 | end 204 | // data_b_i[ 54 ] 205 | initial 206 | begin 207 | data_b_i[54] = 1'b0; 208 | end 209 | // data_b_i[ 53 ] 210 | initial 211 | begin 212 | data_b_i[53] = 1'b0; 213 | end 214 | // data_b_i[ 52 ] 215 | initial 216 | begin 217 | data_b_i[52] = 1'b0; 218 | end 219 | // data_b_i[ 51 ] 220 | initial 221 | begin 222 | data_b_i[51] = 1'b0; 223 | end 224 | // data_b_i[ 50 ] 225 | initial 226 | begin 227 | data_b_i[50] = 1'b0; 228 | end 229 | // data_b_i[ 49 ] 230 | initial 231 | begin 232 | data_b_i[49] = 1'b0; 233 | end 234 | // data_b_i[ 48 ] 235 | initial 236 | begin 237 | data_b_i[48] = 1'b0; 238 | end 239 | // data_b_i[ 47 ] 240 | initial 241 | begin 242 | data_b_i[47] = 1'b0; 243 | end 244 | // data_b_i[ 46 ] 245 | initial 246 | begin 247 | data_b_i[46] = 1'b0; 248 | end 249 | // data_b_i[ 45 ] 250 | initial 251 | begin 252 | data_b_i[45] = 1'b0; 253 | end 254 | // data_b_i[ 44 ] 255 | initial 256 | begin 257 | data_b_i[44] = 1'b0; 258 | end 259 | // data_b_i[ 43 ] 260 | initial 261 | begin 262 | data_b_i[43] = 1'b0; 263 | end 264 | // data_b_i[ 42 ] 265 | initial 266 | begin 267 | data_b_i[42] = 1'b0; 268 | end 269 | // data_b_i[ 41 ] 270 | initial 271 | begin 272 | data_b_i[41] = 1'b0; 273 | end 274 | // data_b_i[ 40 ] 275 | initial 276 | begin 277 | data_b_i[40] = 1'b0; 278 | end 279 | // data_b_i[ 39 ] 280 | initial 281 | begin 282 | data_b_i[39] = 1'b0; 283 | end 284 | // data_b_i[ 38 ] 285 | initial 286 | begin 287 | data_b_i[38] = 1'b0; 288 | end 289 | // data_b_i[ 37 ] 290 | initial 291 | begin 292 | data_b_i[37] = 1'b0; 293 | end 294 | // data_b_i[ 36 ] 295 | initial 296 | begin 297 | data_b_i[36] = 1'b0; 298 | end 299 | // data_b_i[ 35 ] 300 | initial 301 | begin 302 | data_b_i[35] = 1'b0; 303 | end 304 | // data_b_i[ 34 ] 305 | initial 306 | begin 307 | data_b_i[34] = 1'b0; 308 | end 309 | // data_b_i[ 33 ] 310 | initial 311 | begin 312 | data_b_i[33] = 1'b0; 313 | end 314 | // data_b_i[ 32 ] 315 | initial 316 | begin 317 | data_b_i[32] = 1'b0; 318 | end 319 | // data_b_i[ 31 ] 320 | initial 321 | begin 322 | data_b_i[31] = 1'b0; 323 | end 324 | // data_b_i[ 30 ] 325 | initial 326 | begin 327 | data_b_i[30] = 1'b0; 328 | end 329 | // data_b_i[ 29 ] 330 | initial 331 | begin 332 | data_b_i[29] = 1'b0; 333 | end 334 | // data_b_i[ 28 ] 335 | initial 336 | begin 337 | data_b_i[28] = 1'b0; 338 | end 339 | // data_b_i[ 27 ] 340 | initial 341 | begin 342 | data_b_i[27] = 1'b0; 343 | end 344 | // data_b_i[ 26 ] 345 | initial 346 | begin 347 | data_b_i[26] = 1'b0; 348 | end 349 | // data_b_i[ 25 ] 350 | initial 351 | begin 352 | data_b_i[25] = 1'b0; 353 | end 354 | // data_b_i[ 24 ] 355 | initial 356 | begin 357 | data_b_i[24] = 1'b0; 358 | end 359 | // data_b_i[ 23 ] 360 | initial 361 | begin 362 | data_b_i[23] = 1'b0; 363 | end 364 | // data_b_i[ 22 ] 365 | initial 366 | begin 367 | data_b_i[22] = 1'b0; 368 | end 369 | // data_b_i[ 21 ] 370 | initial 371 | begin 372 | data_b_i[21] = 1'b0; 373 | end 374 | // data_b_i[ 20 ] 375 | initial 376 | begin 377 | data_b_i[20] = 1'b0; 378 | end 379 | // data_b_i[ 19 ] 380 | initial 381 | begin 382 | data_b_i[19] = 1'b0; 383 | end 384 | // data_b_i[ 18 ] 385 | initial 386 | begin 387 | data_b_i[18] = 1'b0; 388 | end 389 | // data_b_i[ 17 ] 390 | initial 391 | begin 392 | data_b_i[17] = 1'b0; 393 | end 394 | // data_b_i[ 16 ] 395 | initial 396 | begin 397 | data_b_i[16] = 1'b0; 398 | end 399 | // data_b_i[ 15 ] 400 | initial 401 | begin 402 | data_b_i[15] = 1'b0; 403 | end 404 | // data_b_i[ 14 ] 405 | initial 406 | begin 407 | data_b_i[14] = 1'b0; 408 | end 409 | // data_b_i[ 13 ] 410 | initial 411 | begin 412 | data_b_i[13] = 1'b0; 413 | end 414 | // data_b_i[ 12 ] 415 | initial 416 | begin 417 | data_b_i[12] = 1'b0; 418 | end 419 | // data_b_i[ 11 ] 420 | initial 421 | begin 422 | data_b_i[11] = 1'b0; 423 | end 424 | // data_b_i[ 10 ] 425 | initial 426 | begin 427 | data_b_i[10] = 1'b0; 428 | end 429 | // data_b_i[ 9 ] 430 | initial 431 | begin 432 | data_b_i[9] = 1'b0; 433 | end 434 | // data_b_i[ 8 ] 435 | initial 436 | begin 437 | data_b_i[8] = 1'b0; 438 | end 439 | // data_b_i[ 7 ] 440 | initial 441 | begin 442 | data_b_i[7] = 1'b0; 443 | end 444 | // data_b_i[ 6 ] 445 | initial 446 | begin 447 | data_b_i[6] = 1'b0; 448 | end 449 | // data_b_i[ 5 ] 450 | initial 451 | begin 452 | data_b_i[5] = 1'b0; 453 | end 454 | // data_b_i[ 4 ] 455 | initial 456 | begin 457 | data_b_i[4] = 1'b0; 458 | end 459 | // data_b_i[ 3 ] 460 | initial 461 | begin 462 | data_b_i[3] = 1'b0; 463 | end 464 | // data_b_i[ 2 ] 465 | initial 466 | begin 467 | data_b_i[2] = 1'b0; 468 | end 469 | // data_b_i[ 1 ] 470 | initial 471 | begin 472 | data_b_i[1] = 1'b0; 473 | end 474 | // data_b_i[ 0 ] 475 | initial 476 | begin 477 | data_b_i[0] = 1'b0; 478 | end 479 | // data_l_i[ 3 ] 480 | initial 481 | begin 482 | data_l_i[3] = 1'b0; 483 | end 484 | // data_l_i[ 2 ] 485 | initial 486 | begin 487 | data_l_i[2] = 1'b0; 488 | end 489 | // data_l_i[ 1 ] 490 | initial 491 | begin 492 | data_l_i[1] = 1'b0; 493 | end 494 | // data_l_i[ 0 ] 495 | initial 496 | begin 497 | data_l_i[0] = 1'b0; 498 | end 499 | 500 | // rst_i 501 | initial 502 | begin 503 | rst_i = 1'b1; 504 | rst_i = #20000 1'b0; 505 | end 506 | 507 | // rx_i 508 | initial 509 | begin 510 | rx_i = 1'b0; 511 | end 512 | // sign[ 1 ] 513 | initial 514 | begin 515 | sign[1] = 1'b0; 516 | end 517 | // sign[ 0 ] 518 | initial 519 | begin 520 | sign[0] = 1'b0; 521 | end 522 | 523 | // type 524 | initial 525 | begin 526 | type = 1'b0; 527 | end 528 | endmodule 529 | 530 | -------------------------------------------------------------------------------- /simulation/qsim/Waveform1.vwf.vt: -------------------------------------------------------------------------------- 1 | // Copyright (C) 2020 Intel Corporation. All rights reserved. 2 | // Your use of Intel Corporation's design tools, logic functions 3 | // and other software and tools, and any partner logic 4 | // functions, and any output files from any of the foregoing 5 | // (including device programming or simulation files), and any 6 | // associated documentation or information are expressly subject 7 | // to the terms and conditions of the Intel Program License 8 | // Subscription Agreement, the Intel Quartus Prime License Agreement, 9 | // the Intel FPGA IP License Agreement, or other applicable license 10 | // agreement, including, without limitation, that your use is for 11 | // the sole purpose of programming logic devices manufactured by 12 | // Intel and sold by Intel or its authorized distributors. Please 13 | // refer to the applicable agreement for further details, at 14 | // https://fpgasoftware.intel.com/eula. 15 | 16 | // ***************************************************************************** 17 | // This file contains a Verilog test bench with test vectors .The test vectors 18 | // are exported from a vector file in the Quartus Waveform Editor and apply to 19 | // the top level entity of the current Quartus project .The user can use this 20 | // testbench to simulate his design using a third-party simulation tool . 21 | // ***************************************************************************** 22 | // Generated on "10/23/2020 13:40:24" 23 | 24 | // Verilog Test Bench (with test vectors) for design : can_top 25 | // 26 | // Simulation tool : 3rd Party 27 | // 28 | 29 | `timescale 1 ps/ 1 ps 30 | module can_top_vlg_vec_tst(); 31 | // constants 32 | // general purpose registers 33 | reg clk_i; 34 | reg rst_i; 35 | reg rx_i; 36 | // wires 37 | wire bit_stuffed; 38 | wire rx_busy; 39 | wire [7:0] test_bit_count; 40 | wire [3:0] test_bit_pol_count; 41 | wire [2:0] test_can_state; 42 | wire [7:0] test_can_tx_state; 43 | wire test_clk_can; 44 | wire test_last_bit; 45 | wire [7:0] test_rx_bit_count; 46 | wire [3:0] test_rx_bit_pol_count; 47 | wire test_rx_bit_stuffed; 48 | wire [6:0] test_rx_count; 49 | wire [11:0] test_rx_quant_count; 50 | wire test_rx_rx; 51 | wire [7:0] test_rx_state; 52 | wire test_sample; 53 | wire tx_busy; 54 | wire tx_o; 55 | 56 | // assign statements (if any) 57 | can_top i1 ( 58 | // port map - connection between master ports and signals/registers 59 | .bit_stuffed(bit_stuffed), 60 | .clk_i(clk_i), 61 | .rst_i(rst_i), 62 | .rx_busy(rx_busy), 63 | .rx_i(rx_i), 64 | .test_bit_count(test_bit_count), 65 | .test_bit_pol_count(test_bit_pol_count), 66 | .test_can_state(test_can_state), 67 | .test_can_tx_state(test_can_tx_state), 68 | .test_clk_can(test_clk_can), 69 | .test_last_bit(test_last_bit), 70 | .test_rx_bit_count(test_rx_bit_count), 71 | .test_rx_bit_pol_count(test_rx_bit_pol_count), 72 | .test_rx_bit_stuffed(test_rx_bit_stuffed), 73 | .test_rx_count(test_rx_count), 74 | .test_rx_quant_count(test_rx_quant_count), 75 | .test_rx_rx(test_rx_rx), 76 | .test_rx_state(test_rx_state), 77 | .test_sample(test_sample), 78 | .tx_busy(tx_busy), 79 | .tx_o(tx_o) 80 | ); 81 | initial 82 | begin 83 | #1000000 $finish; 84 | end 85 | 86 | // clk_i 87 | always 88 | begin 89 | clk_i = 1'b0; 90 | clk_i = #250 1'b1; 91 | #250; 92 | end 93 | 94 | // rst_i 95 | initial 96 | begin 97 | rst_i = 1'b1; 98 | rst_i = #20000 1'b0; 99 | end 100 | endmodule 101 | 102 | -------------------------------------------------------------------------------- /simulation/qsim/transcript: -------------------------------------------------------------------------------- 1 | # do CAN.do 2 | # ** Warning: (vlib-34) Library already exists at "work". 3 | # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 4 | # Start time: 13:40:27 on Oct 23,2020 5 | # vlog -work work CAN.vo 6 | # -- Compiling module can_top 7 | # -- Compiling module hard_block 8 | # 9 | # Top level modules: 10 | # can_top 11 | # End time: 13:40:27 on Oct 23,2020, Elapsed time: 0:00:00 12 | # Errors: 0, Warnings: 0 13 | # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 14 | # Start time: 13:40:27 on Oct 23,2020 15 | # vlog -work work Waveform1.vwf.vt 16 | # -- Compiling module can_top_vlg_vec_tst 17 | # 18 | # Top level modules: 19 | # can_top_vlg_vec_tst 20 | # End time: 13:40:27 on Oct 23,2020, Elapsed time: 0:00:00 21 | # Errors: 0, Warnings: 0 22 | # vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.can_top_vlg_vec_tst 23 | # Start time: 13:40:27 on Oct 23,2020 24 | # Loading work.can_top_vlg_vec_tst 25 | # Loading work.can_top 26 | # Loading work.hard_block 27 | # Loading cycloneive_ver.cycloneive_io_obuf 28 | # Loading cycloneive_ver.cycloneive_io_ibuf 29 | # Loading cycloneive_ver.cycloneive_clkctrl 30 | # Loading cycloneive_ver.cycloneive_mux41 31 | # Loading cycloneive_ver.cycloneive_ena_reg 32 | # Loading cycloneive_ver.cycloneive_lcell_comb 33 | # Loading altera_ver.dffeas 34 | # Loading altera_ver.PRIM_GDFF_LOW 35 | # after#26 36 | # ** Note: $finish : Waveform1.vwf.vt(83) 37 | # Time: 1 us Iteration: 0 Instance: /can_top_vlg_vec_tst 38 | # End time: 13:40:28 on Oct 23,2020, Elapsed time: 0:00:01 39 | # Errors: 0, Warnings: 0 40 | -------------------------------------------------------------------------------- /simulation/qsim/vwf_sim_transcript: -------------------------------------------------------------------------------- 1 | Determining the location of the ModelSim executable... 2 | 3 | Using: C:\intelFPGA\20.1\modelsim_ase\win32aloem 4 | 5 | To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options 6 | Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. 7 | 8 | **** Generating the ModelSim Testbench **** 9 | 10 | quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CAN -c CAN --vector_source="C:/hdl_projects/Can/Waveform1.vwf" --testbench_file=""C:/hdl_projects/Can/simulation/qsim/Waveform1.vwf.vt" 11 | 12 | Info: ******************************************************************* 13 | Info: Running Quartus Prime EDA Netlist Writer 14 | Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 15 | Info: Copyright (C) 2020 Intel Corporation. All rights reserved. 16 | Info: Your use of Intel Corporation's design tools, logic functions 17 | Info: and other software and tools, and any partner logic 18 | Info: functions, and any output files from any of the foregoing 19 | Info: (including device programming or simulation files), and any 20 | Info: associated documentation or information are expressly subject 21 | Info: to the terms and conditions of the Intel Program License 22 | Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 23 | Info: the Intel FPGA IP License Agreement, or other applicable license 24 | Info: agreement, including, without limitation, that your use is for 25 | Info: the sole purpose of programming logic devices manufactured by 26 | Info: Intel and sold by Intel or its authorized distributors. Please 27 | Info: refer to the applicable agreement for further details, at 28 | Info: https://fpgasoftware.intel.com/eula. 29 | Info: Processing started: Fri Oct 23 13:40:24 2020 30 | Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off CAN -c CAN --vector_source=C:/hdl_projects/Can/Waveform1.vwf --testbench_file=C:/hdl_projects/Can/simulation/qsim/Waveform1.vwf.vt 31 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 32 | 33 | pol_count[3]" in vector source file when writing test bench files 34 | 35 | Completed successfully. 36 | 37 | Completed successfully. 38 | 39 | **** Generating the functional simulation netlist **** 40 | 41 | quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/hdl_projects/Can/simulation/qsim/" CAN -c CAN 42 | 43 | Info: ******************************************************************* 44 | Info: Running Quartus Prime EDA Netlist Writer 45 | Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition 46 | Info: Copyright (C) 2020 Intel Corporation. All rights reserved. 47 | Info: Your use of Intel Corporation's design tools, logic functions 48 | Info: and other software and tools, and any partner logic 49 | Info: functions, and any output files from any of the foregoing 50 | Info: (including device programming or simulation files), and any 51 | Info: associated documentation or information are expressly subject 52 | Info: to the terms and conditions of the Intel Program License 53 | Info: Subscription Agreement, the Intel Quartus Prime License Agreement, 54 | Info: the Intel FPGA IP License Agreement, or other applicable license 55 | Info: agreement, including, without limitation, that your use is for 56 | Info: the sole purpose of programming logic devices manufactured by 57 | Info: Intel and sold by Intel or its authorized distributors. Please 58 | Info: refer to the applicable agreement for further details, at 59 | Info: https://fpgasoftware.intel.com/eula. 60 | Info: Processing started: Fri Oct 23 13:40:25 2020 61 | Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory=C:/hdl_projects/Can/simulation/qsim/ CAN -c CAN 62 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. 63 | Info (204019): Generated file CAN.vo in folder "C:/hdl_projects/Can/simulation/qsim//" for EDA simulation tool 64 | Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning 65 | Info: Peak virtual memory: 4638 megabytes 66 | Info: Processing ended: Fri Oct 23 13:40:25 2020 67 | Info: Elapsed time: 00:00:00 68 | Info: Total CPU time (on all processors): 00:00:01 69 | 70 | Completed successfully. 71 | 72 | **** Generating the ModelSim .do script **** 73 | 74 | C:/hdl_projects/CAN/simulation/qsim/CAN.do generated. 75 | 76 | Completed successfully. 77 | 78 | **** Running the ModelSim simulation **** 79 | 80 | C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do CAN.do 81 | 82 | Reading pref.tcl 83 | 84 | # 2020.1 85 | 86 | # do CAN.do 87 | 88 | # ** Warning: (vlib-34) Library already exists at "work". 89 | 90 | # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 91 | # Start time: 13:40:27 on Oct 23,2020 92 | # vlog -work work CAN.vo 93 | 94 | # -- Compiling module can_top 95 | 96 | # -- Compiling module hard_block 97 | # 98 | # Top level modules: 99 | # can_top 100 | 101 | # End time: 13:40:27 on Oct 23,2020, Elapsed time: 0:00:00 102 | # Errors: 0, Warnings: 0 103 | # Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020 104 | # Start time: 13:40:27 on Oct 23,2020 105 | # vlog -work work Waveform1.vwf.vt 106 | 107 | # -- Compiling module can_top_vlg_vec_tst 108 | # 109 | # Top level modules: 110 | # can_top_vlg_vec_tst 111 | # End time: 13:40:27 on Oct 23,2020, Elapsed time: 0:00:00 112 | # Errors: 0, Warnings: 0 113 | 114 | # vsim -c -t 1ps -L cycloneive_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.can_top_vlg_vec_tst 115 | # Start time: 13:40:27 on Oct 23,2020 116 | # Loading work.can_top_vlg_vec_tst 117 | # Loading work.can_top 118 | # Loading work.hard_block 119 | # Loading cycloneive_ver.cycloneive_io_obuf 120 | # Loading cycloneive_ver.cycloneive_io_ibuf 121 | # Loading cycloneive_ver.cycloneive_clkctrl 122 | # Loading cycloneive_ver.cycloneive_mux41 123 | # Loading cycloneive_ver.cycloneive_ena_reg 124 | # Loading cycloneive_ver.cycloneive_lcell_comb 125 | # Loading altera_ver.dffeas 126 | # Loading altera_ver.PRIM_GDFF_LOW 127 | # after#26 128 | # ** Note: $finish : Waveform1.vwf.vt(83) 129 | # Time: 1 us Iteration: 0 Instance: /can_top_vlg_vec_tst 130 | # End time: 13:40:28 on Oct 23,2020, Elapsed time: 0:00:01 131 | # Errors: 0, Warnings: 0 132 | 133 | Completed successfully. 134 | 135 | **** Converting ModelSim VCD to vector waveform **** 136 | 137 | Reading C:/hdl_projects/CAN/Waveform1.vwf... 138 | 139 | Reading C:/hdl_projects/CAN/simulation/qsim/CAN.msim.vcd... 140 | 141 | Processing channel transitions... 142 | 143 | Writing the resulting VWF to C:/hdl_projects/CAN/simulation/qsim/CAN_20201023134028.sim.vwf 144 | 145 | Finished VCD to VWF conversion. 146 | 147 | Completed successfully. 148 | 149 | All completed. -------------------------------------------------------------------------------- /simulation/qsim/work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | !s11f vlog 2020.1 2020.02, Feb 28 2020 5 | 13 6 | !s112 1.1 7 | !i10d 8192 8 | !i10e 25 9 | !i10f 100 10 | cModel Technology 11 | dC:/hdl_projects/Can/Custom_Can/simulation/qsim 12 | vcan_top 13 | Z0 !s110 1603449627 14 | !i10b 1 15 | !s100 EX389_gX^NhHm5fFj<14?2 16 | Z1 !s11b Dg1SIo80bB@j0V0VzS_@n1 17 | I;Wc=ZBbc3Jn3WQ[O<>[ST2 18 | Z2 VDg1SIo80bB@j0V0VzS_@n1 19 | Z3 dC:/hdl_projects/CAN/simulation/qsim 20 | Z4 w1603449625 21 | Z5 8CAN.vo 22 | Z6 FCAN.vo 23 | !i122 230 24 | L0 32 13899 25 | Z7 OV;L;2020.1;71 26 | r1 27 | !s85 0 28 | 31 29 | Z8 !s108 1603449627.000000 30 | Z9 !s107 CAN.vo| 31 | Z10 !s90 -work|work|CAN.vo| 32 | !i113 1 33 | Z11 o-work work 34 | Z12 tCvgOpt 0 35 | vcan_top_vlg_vec_tst 36 | R0 37 | !i10b 1 38 | !s100 47`Ll4YUQN4Z:CTKBmG@E0 39 | R1 40 | I0oN;8E029<0SOcZZ24ecL1 41 | R2 42 | R3 43 | R4 44 | 8Waveform1.vwf.vt 45 | FWaveform1.vwf.vt 46 | !i122 231 47 | L0 30 71 48 | R7 49 | r1 50 | !s85 0 51 | 31 52 | R8 53 | !s107 Waveform1.vwf.vt| 54 | !s90 -work|work|Waveform1.vwf.vt| 55 | !i113 1 56 | R11 57 | R12 58 | vhard_block 59 | R0 60 | !i10b 1 61 | !s100 ^cG;SIB?3fXWX_lOEcGIG3 62 | R1 63 | IcWF2eTH]1=hVcKOioK;7Z0 64 | R2 65 | R3 66 | R4 67 | R5 68 | R6 69 | !i122 230 70 | L0 13932 34 71 | R7 72 | r1 73 | !s85 0 74 | 31 75 | R8 76 | R9 77 | R10 78 | !i113 1 79 | R11 80 | R12 81 | -------------------------------------------------------------------------------- /simulation/qsim/work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/simulation/qsim/work/_lib.qdb -------------------------------------------------------------------------------- /simulation/qsim/work/_lib1_115.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/simulation/qsim/work/_lib1_115.qdb -------------------------------------------------------------------------------- /simulation/qsim/work/_lib1_115.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/simulation/qsim/work/_lib1_115.qpg -------------------------------------------------------------------------------- /simulation/qsim/work/_lib1_115.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AlxyF/CAN-fpga/5e1142bb666b6cf0cac55b2ec1d5b34538b0e3b0/simulation/qsim/work/_lib1_115.qtl -------------------------------------------------------------------------------- /simulation/qsim/work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | --------------------------------------------------------------------------------