├── .gitattributes ├── BUFFER.v ├── BitwiseG.v ├── BitwiseP.v ├── BlackCell.v ├── BrentKung32Bit.v ├── BrentKung32Bit_tb.v ├── CIA32Bit.v ├── CIA32Bit_tb.v ├── CIA8Bit.v ├── CIA8Bit_tb.v ├── CLA32Bit.v ├── CLA32Bit_tb.v ├── CSKA32Bit.v ├── CSKA32Bit_tb.v ├── CSKA4Bit.v ├── CSKA4Bit_tb.v ├── CSLA32Bit.v ├── CSLA32Bit_tb.v ├── CSLA4Bit.v ├── CSLA4Bit_tb.v ├── CarryGen.v ├── FullAdder.v ├── FullAdder_P.v ├── FullAdder_P_tb.v ├── FullAdder_tb.v ├── GrayCell.v ├── HA.v ├── HalfAdder_tb.v ├── KoggeStone32Bit.v ├── KoggeStone32Bit_tb.v ├── MUX2x1.v ├── RCA32Bit.v ├── RCA32Bit_tb.v ├── RCA4Bit.v ├── RCA4Bit_tb.v ├── RCA8bit.v ├── RCA8bit_tb.v ├── README.md ├── SUM_PROPAGATE.v ├── Sklansky32Bit.v ├── Sklansky32Bit_tb.v ├── SumGen.v ├── Valency4BlackDot.v └── test_Sklansky32Bit_tb.v /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Ams0x57/Digital_Adders_Verilog/HEAD/.gitattributes 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