├── README.md ├── cmsis_boot ├── startup │ └── startup_stm32f0xx.s ├── stm32f0xx.h ├── stm32f0xx_conf.h ├── system_stm32f0xx.h └── system_stm32f0xx_temp.c ├── cmsis_core ├── core_cm0.h ├── core_cmFunc.h └── core_cmInstr.h ├── dmx512.c ├── dmx512.h ├── main.c ├── stm32_lib ├── inc │ ├── stm32f0xx_dma.h │ ├── stm32f0xx_exti.h │ ├── stm32f0xx_gpio.h │ ├── stm32f0xx_misc.h │ ├── stm32f0xx_rcc.h │ ├── stm32f0xx_syscfg.h │ ├── stm32f0xx_tim.h │ └── stm32f0xx_usart.h └── src │ ├── stm32f0xx_dma.c │ ├── stm32f0xx_exti.c │ ├── stm32f0xx_gpio.c │ ├── stm32f0xx_misc.c │ ├── stm32f0xx_rcc.c │ ├── stm32f0xx_syscfg.c │ ├── stm32f0xx_tim.c │ └── stm32f0xx_usart.c ├── stm32f0_ws2812b_dmx512.cogui ├── stm32f0_ws2812b_dmx512.comarker ├── stm32f0_ws2812b_dmx512.coproj ├── ws2812b.c └── ws2812b.h /README.md: -------------------------------------------------------------------------------- 1 | # STM32F030 DMX512 WS2812B driver 2 | 3 | This code drives eight parallel strings of WS2812B LED's (connected to GPIOA pins 0-7) based on DMX512 packets fed to USART1. 4 | 5 | The WS2812B library is a port of Elia's code at [devtrash/0xWS2812](https://github.com/devthrash/0xWS2812) 6 | -------------------------------------------------------------------------------- /cmsis_boot/startup/startup_stm32f0xx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f0xx.s 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 31-July-2013 7 | * @brief STM32F0xx Medium-density devices vector table for RIDE7 toolchain. 8 | * This module performs: 9 | * - Set the initial SP 10 | * - Set the initial PC == Reset_Handler, 11 | * - Set the vector table entries with the exceptions ISR address 12 | * - Configure the system clock 13 | * - Branches to main in the C library (which eventually 14 | * calls main()). 15 | * After Reset the Cortex-M0 processor is in Thread mode, 16 | * priority is Privileged, and the Stack is set to Main. 17 | ****************************************************************************** 18 | * @attention 19 | * 20 | *

© COPYRIGHT 2013 STMicroelectronics

21 | * 22 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 23 | * You may not use this file except in compliance with the License. 24 | * You may obtain a copy of the License at: 25 | * 26 | * http://www.st.com/software_license_agreement_liberty_v2 27 | * 28 | * Unless required by applicable law or agreed to in writing, software 29 | * distributed under the License is distributed on an "AS IS" BASIS, 30 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 31 | * See the License for the specific language governing permissions and 32 | * limitations under the License. 33 | * 34 | ****************************************************************************** 35 | */ 36 | 37 | .syntax unified 38 | .cpu cortex-m0 39 | .fpu softvfp 40 | .thumb 41 | 42 | .global g_pfnVectors 43 | .global Default_Handler 44 | 45 | /* start address for the initialization values of the .data section. 46 | defined in linker script */ 47 | .word _sidata 48 | /* start address for the .data section. defined in linker script */ 49 | .word _sdata 50 | /* end address for the .data section. defined in linker script */ 51 | .word _edata 52 | /* start address for the .bss section. defined in linker script */ 53 | .word _sbss 54 | /* end address for the .bss section. defined in linker script */ 55 | .word _ebss 56 | 57 | .equ BootRAM, 0xF108F85F 58 | /** 59 | * @brief This is the code that gets called when the processor first 60 | * starts execution following a reset event. Only the absolutely 61 | * necessary set is performed, after which the application 62 | * supplied main() routine is called. 63 | * @param None 64 | * @retval : None 65 | */ 66 | 67 | .section .text.Reset_Handler 68 | .weak Reset_Handler 69 | .type Reset_Handler, %function 70 | Reset_Handler: 71 | ldr r0, =_eram 72 | mov sp, r0 /* set stack pointer */ 73 | 74 | /* Copy the data segment initializers from flash to SRAM */ 75 | movs r1, #0 76 | b LoopCopyDataInit 77 | 78 | CopyDataInit: 79 | ldr r3, =_sidata 80 | ldr r3, [r3, r1] 81 | str r3, [r0, r1] 82 | adds r1, r1, #4 83 | 84 | LoopCopyDataInit: 85 | ldr r0, =_sdata 86 | ldr r3, =_edata 87 | adds r2, r0, r1 88 | cmp r2, r3 89 | bcc CopyDataInit 90 | ldr r2, =_sbss 91 | b LoopFillZerobss 92 | /* Zero fill the bss segment. */ 93 | FillZerobss: 94 | movs r3, #0 95 | str r3, [r2] 96 | adds r2, r2, #4 97 | 98 | 99 | LoopFillZerobss: 100 | ldr r3, = _ebss 101 | cmp r2, r3 102 | bcc FillZerobss 103 | 104 | /* Call the clock system intitialization function.*/ 105 | bl SystemInit 106 | 107 | /* Call the application's entry point.*/ 108 | bl main 109 | 110 | LoopForever: 111 | b LoopForever 112 | 113 | 114 | .size Reset_Handler, .-Reset_Handler 115 | 116 | /** 117 | * @brief This is the code that gets called when the processor receives an 118 | * unexpected interrupt. This simply enters an infinite loop, preserving 119 | * the system state for examination by a debugger. 120 | * 121 | * @param None 122 | * @retval : None 123 | */ 124 | .section .text.Default_Handler,"ax",%progbits 125 | Default_Handler: 126 | Infinite_Loop: 127 | b Infinite_Loop 128 | .size Default_Handler, .-Default_Handler 129 | /****************************************************************************** 130 | * 131 | * The minimal vector table for a Cortex M0. Note that the proper constructs 132 | * must be placed on this to ensure that it ends up at physical address 133 | * 0x0000.0000. 134 | * 135 | ******************************************************************************/ 136 | .section .isr_vector,"a",%progbits 137 | .type g_pfnVectors, %object 138 | .size g_pfnVectors, .-g_pfnVectors 139 | 140 | 141 | g_pfnVectors: 142 | .word _eram 143 | .word Reset_Handler 144 | .word NMI_Handler 145 | .word HardFault_Handler 146 | .word 0 147 | .word 0 148 | .word 0 149 | .word 0 150 | .word 0 151 | .word 0 152 | .word 0 153 | .word SVC_Handler 154 | .word 0 155 | .word 0 156 | .word PendSV_Handler 157 | .word SysTick_Handler 158 | .word WWDG_IRQHandler 159 | .word PVD_IRQHandler 160 | .word RTC_IRQHandler 161 | .word FLASH_IRQHandler 162 | .word RCC_IRQHandler 163 | .word EXTI0_1_IRQHandler 164 | .word EXTI2_3_IRQHandler 165 | .word EXTI4_15_IRQHandler 166 | .word TS_IRQHandler 167 | .word DMA1_Channel1_IRQHandler 168 | .word DMA1_Channel2_3_IRQHandler 169 | .word DMA1_Channel4_5_IRQHandler 170 | .word ADC1_COMP_IRQHandler 171 | .word TIM1_BRK_UP_TRG_COM_IRQHandler 172 | .word TIM1_CC_IRQHandler 173 | .word TIM2_IRQHandler 174 | .word TIM3_IRQHandler 175 | .word TIM6_DAC_IRQHandler 176 | .word 0 177 | .word TIM14_IRQHandler 178 | .word TIM15_IRQHandler 179 | .word TIM16_IRQHandler 180 | .word TIM17_IRQHandler 181 | .word I2C1_IRQHandler 182 | .word I2C2_IRQHandler 183 | .word SPI1_IRQHandler 184 | .word SPI2_IRQHandler 185 | .word USART1_IRQHandler 186 | .word USART2_IRQHandler 187 | .word 0 188 | .word CEC_IRQHandler 189 | .word 0 190 | .word BootRAM /* @0x108. This is for boot in RAM mode for 191 | STM32F0xx devices. */ 192 | 193 | /******************************************************************************* 194 | * 195 | * Provide weak aliases for each Exception handler to the Default_Handler. 196 | * As they are weak aliases, any function with the same name will override 197 | * this definition. 198 | * 199 | *******************************************************************************/ 200 | 201 | .weak NMI_Handler 202 | .thumb_set NMI_Handler,Default_Handler 203 | 204 | .weak HardFault_Handler 205 | .thumb_set HardFault_Handler,Default_Handler 206 | 207 | .weak SVC_Handler 208 | .thumb_set SVC_Handler,Default_Handler 209 | 210 | .weak PendSV_Handler 211 | .thumb_set PendSV_Handler,Default_Handler 212 | 213 | .weak SysTick_Handler 214 | .thumb_set SysTick_Handler,Default_Handler 215 | 216 | .weak WWDG_IRQHandler 217 | .thumb_set WWDG_IRQHandler,Default_Handler 218 | 219 | .weak PVD_IRQHandler 220 | .thumb_set PVD_IRQHandler,Default_Handler 221 | 222 | .weak RTC_IRQHandler 223 | .thumb_set RTC_IRQHandler,Default_Handler 224 | 225 | .weak FLASH_IRQHandler 226 | .thumb_set FLASH_IRQHandler,Default_Handler 227 | 228 | .weak RCC_IRQHandler 229 | .thumb_set RCC_IRQHandler,Default_Handler 230 | 231 | .weak EXTI0_1_IRQHandler 232 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 233 | 234 | .weak EXTI2_3_IRQHandler 235 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 236 | 237 | .weak EXTI4_15_IRQHandler 238 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 239 | 240 | .weak TS_IRQHandler 241 | .thumb_set TS_IRQHandler,Default_Handler 242 | 243 | .weak DMA1_Channel1_IRQHandler 244 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 245 | 246 | .weak DMA1_Channel2_3_IRQHandler 247 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 248 | 249 | .weak DMA1_Channel4_5_IRQHandler 250 | .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler 251 | 252 | .weak ADC1_COMP_IRQHandler 253 | .thumb_set ADC1_COMP_IRQHandler,Default_Handler 254 | 255 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 256 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 257 | 258 | .weak TIM1_CC_IRQHandler 259 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 260 | 261 | .weak TIM2_IRQHandler 262 | .thumb_set TIM2_IRQHandler,Default_Handler 263 | 264 | .weak TIM3_IRQHandler 265 | .thumb_set TIM3_IRQHandler,Default_Handler 266 | 267 | .weak TIM6_DAC_IRQHandler 268 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 269 | 270 | .weak TIM14_IRQHandler 271 | .thumb_set TIM14_IRQHandler,Default_Handler 272 | 273 | .weak TIM15_IRQHandler 274 | .thumb_set TIM15_IRQHandler,Default_Handler 275 | 276 | .weak TIM16_IRQHandler 277 | .thumb_set TIM16_IRQHandler,Default_Handler 278 | 279 | .weak TIM17_IRQHandler 280 | .thumb_set TIM17_IRQHandler,Default_Handler 281 | 282 | .weak I2C1_IRQHandler 283 | .thumb_set I2C1_IRQHandler,Default_Handler 284 | 285 | .weak I2C2_IRQHandler 286 | .thumb_set I2C2_IRQHandler,Default_Handler 287 | 288 | .weak SPI1_IRQHandler 289 | .thumb_set SPI1_IRQHandler,Default_Handler 290 | 291 | .weak SPI2_IRQHandler 292 | .thumb_set SPI2_IRQHandler,Default_Handler 293 | 294 | .weak USART1_IRQHandler 295 | .thumb_set USART1_IRQHandler,Default_Handler 296 | 297 | .weak USART2_IRQHandler 298 | .thumb_set USART2_IRQHandler,Default_Handler 299 | 300 | .weak CEC_IRQHandler 301 | .thumb_set CEC_IRQHandler,Default_Handler 302 | 303 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 304 | 305 | -------------------------------------------------------------------------------- /cmsis_boot/stm32f0xx_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32F0xx_conf.h 4 | * @author MCD Application Team 5 | * @version V1.0.0 6 | * @date 23-March-2012 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2012 STMicroelectronics

© COPYRIGHT 2013 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32f0xx_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32F0XX_H 40 | #define __SYSTEM_STM32F0XX_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32F0xx_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32F0xx_System_Exported_types 56 | * @{ 57 | */ 58 | 59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32F0xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32F0xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32F0xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*__SYSTEM_STM32F0XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 105 | -------------------------------------------------------------------------------- /cmsis_boot/system_stm32f0xx_temp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.c 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 01-August-2013 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 8 | * This file contains the system clock configuration for STM32F0xx devices, 9 | * and is generated by the clock configuration tool 10 | * STM32F0xx_Clock_Configuration_V1.0.0.xls 11 | * 12 | * 1. This file provides two functions and one global variable to be called from 13 | * user application: 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), 16 | * depending on the configuration made in the clock xls tool. 17 | * This function is called at startup just after reset and 18 | * before branch to main program. This call is made inside 19 | * the "startup_stm32f0xx.s" file. 20 | * 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 22 | * by the user application to setup the SysTick 23 | * timer or configure other parameters. 24 | * 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 26 | * be called whenever the core clock is changed 27 | * during program execution. 28 | * 29 | * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. 30 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to 31 | * configure the system clock before to branch to main program. 32 | * 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 34 | * function will do nothing and HSI still used as system clock source. User can 35 | * add some code to deal with this issue inside the SetSysClock() function. 36 | * 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 38 | * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or 39 | * through PLL, and you are using different crystal you have to adapt the HSE 40 | * value to your own configuration. 41 | * 42 | * 5. This file configures the system clock as follows: 43 | *============================================================================= 44 | * System Clock Configuration 45 | *============================================================================= 46 | * System Clock source | PLL(HSE) 47 | *----------------------------------------------------------------------------- 48 | * SYSCLK | 48000000 Hz 49 | *----------------------------------------------------------------------------- 50 | * HCLK | 48000000 Hz 51 | *----------------------------------------------------------------------------- 52 | * AHB Prescaler | 1 53 | *----------------------------------------------------------------------------- 54 | * APB1 Prescaler | 1 55 | *----------------------------------------------------------------------------- 56 | * APB2 Prescaler | 1 57 | *----------------------------------------------------------------------------- 58 | * HSE Frequency | 8000000 Hz 59 | *----------------------------------------------------------------------------- 60 | * PLL MUL | 6 61 | *----------------------------------------------------------------------------- 62 | * VDD | 3.3 V 63 | *----------------------------------------------------------------------------- 64 | * Flash Latency | 1 WS 65 | *----------------------------------------------------------------------------- 66 | *============================================================================= 67 | ****************************************************************************** 68 | * @attention 69 | * 70 | *

© COPYRIGHT 2013 STMicroelectronics

71 | * 72 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 73 | * You may not use this file except in compliance with the License. 74 | * You may obtain a copy of the License at: 75 | * 76 | * http://www.st.com/software_license_agreement_liberty_v2 77 | * 78 | * Unless required by applicable law or agreed to in writing, software 79 | * distributed under the License is distributed on an "AS IS" BASIS, 80 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 81 | * See the License for the specific language governing permissions and 82 | * limitations under the License. 83 | * 84 | ****************************************************************************** 85 | */ 86 | 87 | /** @addtogroup CMSIS 88 | * @{ 89 | */ 90 | 91 | /** @addtogroup stm32f0xx_system 92 | * @{ 93 | */ 94 | 95 | /** @addtogroup STM32F0xx_System_Private_Includes 96 | * @{ 97 | */ 98 | 99 | #include "stm32f0xx.h" 100 | 101 | #define WEAK __attribute__ ((weak)) 102 | 103 | void WEAK SystemInit(void); 104 | void WEAK SystemCoreClockUpdate(void); 105 | void WEAK SetSysClock(void); 106 | //uint32_t WEAK SystemCoreClock; 107 | //__I uint8_t WEAK AHBPrescTable[16]; 108 | 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 115 | * @{ 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @addtogroup STM32F0xx_System_Private_Defines 123 | * @{ 124 | */ 125 | /** 126 | * @} 127 | */ 128 | 129 | /** @addtogroup STM32F0xx_System_Private_Macros 130 | * @{ 131 | */ 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @addtogroup STM32F0xx_System_Private_Variables 138 | * @{ 139 | */ 140 | uint32_t WEAK SystemCoreClock = 48000000; 141 | __I uint8_t WEAK AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 142 | 143 | /** 144 | * @} 145 | */ 146 | 147 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 148 | * @{ 149 | */ 150 | 151 | static void SetSysClock1(void); 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | /** @addtogroup STM32F0xx_System_Private_Functions 158 | * @{ 159 | */ 160 | 161 | /** 162 | * @brief Setup the microcontroller system. 163 | * Initialize the Embedded Flash Interface, the PLL and update the 164 | * SystemCoreClock variable. 165 | * @param None 166 | * @retval None 167 | */ 168 | void SystemInit1 (void) 169 | { 170 | /* Set HSION bit */ 171 | RCC->CR |= (uint32_t)0x00000001; 172 | 173 | #if defined (STM32F0XX_MD) || defined (STM32F030X8) 174 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */ 175 | RCC->CFGR &= (uint32_t)0xF8FFB80C; 176 | #else 177 | /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */ 178 | RCC->CFGR &= (uint32_t)0x08FFB80C; 179 | #endif /* STM32F0XX_MD or STM32F030X8 */ 180 | 181 | /* Reset HSEON, CSSON and PLLON bits */ 182 | RCC->CR &= (uint32_t)0xFEF6FFFF; 183 | 184 | /* Reset HSEBYP bit */ 185 | RCC->CR &= (uint32_t)0xFFFBFFFF; 186 | 187 | /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */ 188 | RCC->CFGR &= (uint32_t)0xFFC0FFFF; 189 | 190 | /* Reset PREDIV1[3:0] bits */ 191 | RCC->CFGR2 &= (uint32_t)0xFFFFFFF0; 192 | 193 | /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */ 194 | RCC->CFGR3 &= (uint32_t)0xFFFFFEAC; 195 | 196 | /* Reset HSI14 bit */ 197 | RCC->CR2 &= (uint32_t)0xFFFFFFFE; 198 | 199 | /* Disable all interrupts */ 200 | RCC->CIR = 0x00000000; 201 | 202 | /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ 203 | SetSysClock(); 204 | } 205 | 206 | /** 207 | * @brief Update SystemCoreClock according to Clock Register Values 208 | * The SystemCoreClock variable contains the core clock (HCLK), it can 209 | * be used by the user application to setup the SysTick timer or configure 210 | * other parameters. 211 | * 212 | * @note Each time the core clock (HCLK) changes, this function must be called 213 | * to update SystemCoreClock variable value. Otherwise, any configuration 214 | * based on this variable will be incorrect. 215 | * 216 | * @note - The system frequency computed by this function is not the real 217 | * frequency in the chip. It is calculated based on the predefined 218 | * constant and the selected clock source: 219 | * 220 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 221 | * 222 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 223 | * 224 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 225 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 226 | * 227 | * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value 228 | * 8 MHz) but the real value may vary depending on the variations 229 | * in voltage and temperature. 230 | * 231 | * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value 232 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 233 | * frequency of the crystal used. Otherwise, this function may 234 | * have wrong result. 235 | * 236 | * - The result of this function could be not correct when using fractional 237 | * value for HSE crystal. 238 | * @param None 239 | * @retval None 240 | */ 241 | void SystemCoreClockUpdate1 (void) 242 | { 243 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; 244 | 245 | /* Get SYSCLK source -------------------------------------------------------*/ 246 | tmp = RCC->CFGR & RCC_CFGR_SWS; 247 | 248 | switch (tmp) 249 | { 250 | case 0x00: /* HSI used as system clock */ 251 | SystemCoreClock = HSI_VALUE; 252 | break; 253 | case 0x04: /* HSE used as system clock */ 254 | SystemCoreClock = HSE_VALUE; 255 | break; 256 | case 0x08: /* PLL used as system clock */ 257 | /* Get PLL clock source and multiplication factor ----------------------*/ 258 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 259 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 260 | pllmull = ( pllmull >> 18) + 2; 261 | 262 | if (pllsource == 0x00) 263 | { 264 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 265 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 266 | } 267 | else 268 | { 269 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 270 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 271 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 272 | } 273 | break; 274 | default: /* HSI used as system clock */ 275 | SystemCoreClock = HSI_VALUE; 276 | break; 277 | } 278 | /* Compute HCLK clock frequency ----------------*/ 279 | /* Get HCLK prescaler */ 280 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 281 | /* HCLK clock frequency */ 282 | SystemCoreClock >>= tmp; 283 | } 284 | 285 | /** 286 | * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash 287 | * settings. 288 | * @note This function should be called only once the RCC clock configuration 289 | * is reset to the default reset state (done in SystemInit() function). 290 | * @param None 291 | * @retval None 292 | */ 293 | static void SetSysClock1(void) 294 | { 295 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 296 | 297 | /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ 298 | /* Enable HSE */ 299 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 300 | 301 | /* Wait till HSE is ready and if Time out is reached exit */ 302 | do 303 | { 304 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 305 | StartUpCounter++; 306 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 307 | 308 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 309 | { 310 | HSEStatus = (uint32_t)0x01; 311 | } 312 | else 313 | { 314 | HSEStatus = (uint32_t)0x00; 315 | } 316 | 317 | if (HSEStatus == (uint32_t)0x01) 318 | { 319 | /* Enable Prefetch Buffer and set Flash Latency */ 320 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 321 | 322 | /* HCLK = SYSCLK */ 323 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 324 | 325 | /* PCLK = HCLK */ 326 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 327 | 328 | /* PLL configuration = HSE * 6 = 48 MHz */ 329 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 330 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); 331 | 332 | /* Enable PLL */ 333 | RCC->CR |= RCC_CR_PLLON; 334 | 335 | /* Wait till PLL is ready */ 336 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 337 | { 338 | } 339 | 340 | /* Select PLL as system clock source */ 341 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 342 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 343 | 344 | /* Wait till PLL is used as system clock source */ 345 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 346 | { 347 | } 348 | } 349 | else 350 | { /* If HSE fails to start-up, the application will have wrong clock 351 | configuration. User can add here some code to deal with this error */ 352 | } 353 | } 354 | 355 | 356 | #pragma weak SetSysClock = SetSysClock1 357 | #pragma weak SystemCoreClockUpdate = SystemCoreClockUpdate1 358 | #pragma weak SystemInit = SystemInit1 359 | 360 | //#pragma weak SystemCoreClock = SystemCoreClock1 361 | //#pragma weak AHBPrescTable = AHBPrescTable1 362 | 363 | 364 | /** 365 | * @} 366 | */ 367 | 368 | /** 369 | * @} 370 | */ 371 | 372 | /** 373 | * @} 374 | */ 375 | 376 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 377 | -------------------------------------------------------------------------------- /cmsis_core/core_cmFunc.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmFunc.h 3 | * @brief CMSIS Cortex-M Core Function Access Header File 4 | * @version V3.01 5 | * @date 06. March 2012 6 | * 7 | * @note 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 9 | * 10 | * @par 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 | * processor based microcontrollers. This file can be freely distributed 13 | * within development tools that are supporting such ARM based processors. 14 | * 15 | * @par 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 | * 22 | ******************************************************************************/ 23 | 24 | #ifndef __CORE_CMFUNC_H 25 | #define __CORE_CMFUNC_H 26 | 27 | 28 | /* ########################### Core Function Access ########################### */ 29 | /** \ingroup CMSIS_Core_FunctionInterface 30 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 31 | @{ 32 | */ 33 | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 35 | /* ARM armcc specific functions */ 36 | 37 | #if (__ARMCC_VERSION < 400677) 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 39 | #endif 40 | 41 | /* intrinsic void __enable_irq(); */ 42 | /* intrinsic void __disable_irq(); */ 43 | 44 | /** \brief Get Control Register 45 | 46 | This function returns the content of the Control Register. 47 | 48 | \return Control Register value 49 | */ 50 | __STATIC_INLINE uint32_t __get_CONTROL(void) 51 | { 52 | register uint32_t __regControl __ASM("control"); 53 | return(__regControl); 54 | } 55 | 56 | 57 | /** \brief Set Control Register 58 | 59 | This function writes the given value to the Control Register. 60 | 61 | \param [in] control Control Register value to set 62 | */ 63 | __STATIC_INLINE void __set_CONTROL(uint32_t control) 64 | { 65 | register uint32_t __regControl __ASM("control"); 66 | __regControl = control; 67 | } 68 | 69 | 70 | /** \brief Get IPSR Register 71 | 72 | This function returns the content of the IPSR Register. 73 | 74 | \return IPSR Register value 75 | */ 76 | __STATIC_INLINE uint32_t __get_IPSR(void) 77 | { 78 | register uint32_t __regIPSR __ASM("ipsr"); 79 | return(__regIPSR); 80 | } 81 | 82 | 83 | /** \brief Get APSR Register 84 | 85 | This function returns the content of the APSR Register. 86 | 87 | \return APSR Register value 88 | */ 89 | __STATIC_INLINE uint32_t __get_APSR(void) 90 | { 91 | register uint32_t __regAPSR __ASM("apsr"); 92 | return(__regAPSR); 93 | } 94 | 95 | 96 | /** \brief Get xPSR Register 97 | 98 | This function returns the content of the xPSR Register. 99 | 100 | \return xPSR Register value 101 | */ 102 | __STATIC_INLINE uint32_t __get_xPSR(void) 103 | { 104 | register uint32_t __regXPSR __ASM("xpsr"); 105 | return(__regXPSR); 106 | } 107 | 108 | 109 | /** \brief Get Process Stack Pointer 110 | 111 | This function returns the current value of the Process Stack Pointer (PSP). 112 | 113 | \return PSP Register value 114 | */ 115 | __STATIC_INLINE uint32_t __get_PSP(void) 116 | { 117 | register uint32_t __regProcessStackPointer __ASM("psp"); 118 | return(__regProcessStackPointer); 119 | } 120 | 121 | 122 | /** \brief Set Process Stack Pointer 123 | 124 | This function assigns the given value to the Process Stack Pointer (PSP). 125 | 126 | \param [in] topOfProcStack Process Stack Pointer value to set 127 | */ 128 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 129 | { 130 | register uint32_t __regProcessStackPointer __ASM("psp"); 131 | __regProcessStackPointer = topOfProcStack; 132 | } 133 | 134 | 135 | /** \brief Get Main Stack Pointer 136 | 137 | This function returns the current value of the Main Stack Pointer (MSP). 138 | 139 | \return MSP Register value 140 | */ 141 | __STATIC_INLINE uint32_t __get_MSP(void) 142 | { 143 | register uint32_t __regMainStackPointer __ASM("msp"); 144 | return(__regMainStackPointer); 145 | } 146 | 147 | 148 | /** \brief Set Main Stack Pointer 149 | 150 | This function assigns the given value to the Main Stack Pointer (MSP). 151 | 152 | \param [in] topOfMainStack Main Stack Pointer value to set 153 | */ 154 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 155 | { 156 | register uint32_t __regMainStackPointer __ASM("msp"); 157 | __regMainStackPointer = topOfMainStack; 158 | } 159 | 160 | 161 | /** \brief Get Priority Mask 162 | 163 | This function returns the current state of the priority mask bit from the Priority Mask Register. 164 | 165 | \return Priority Mask value 166 | */ 167 | __STATIC_INLINE uint32_t __get_PRIMASK(void) 168 | { 169 | register uint32_t __regPriMask __ASM("primask"); 170 | return(__regPriMask); 171 | } 172 | 173 | 174 | /** \brief Set Priority Mask 175 | 176 | This function assigns the given value to the Priority Mask Register. 177 | 178 | \param [in] priMask Priority Mask 179 | */ 180 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 181 | { 182 | register uint32_t __regPriMask __ASM("primask"); 183 | __regPriMask = (priMask); 184 | } 185 | 186 | 187 | #if (__CORTEX_M >= 0x03) 188 | 189 | /** \brief Enable FIQ 190 | 191 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. 192 | Can only be executed in Privileged modes. 193 | */ 194 | #define __enable_fault_irq __enable_fiq 195 | 196 | 197 | /** \brief Disable FIQ 198 | 199 | This function disables FIQ interrupts by setting the F-bit in the CPSR. 200 | Can only be executed in Privileged modes. 201 | */ 202 | #define __disable_fault_irq __disable_fiq 203 | 204 | 205 | /** \brief Get Base Priority 206 | 207 | This function returns the current value of the Base Priority register. 208 | 209 | \return Base Priority register value 210 | */ 211 | __STATIC_INLINE uint32_t __get_BASEPRI(void) 212 | { 213 | register uint32_t __regBasePri __ASM("basepri"); 214 | return(__regBasePri); 215 | } 216 | 217 | 218 | /** \brief Set Base Priority 219 | 220 | This function assigns the given value to the Base Priority register. 221 | 222 | \param [in] basePri Base Priority value to set 223 | */ 224 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 225 | { 226 | register uint32_t __regBasePri __ASM("basepri"); 227 | __regBasePri = (basePri & 0xff); 228 | } 229 | 230 | 231 | /** \brief Get Fault Mask 232 | 233 | This function returns the current value of the Fault Mask register. 234 | 235 | \return Fault Mask register value 236 | */ 237 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) 238 | { 239 | register uint32_t __regFaultMask __ASM("faultmask"); 240 | return(__regFaultMask); 241 | } 242 | 243 | 244 | /** \brief Set Fault Mask 245 | 246 | This function assigns the given value to the Fault Mask register. 247 | 248 | \param [in] faultMask Fault Mask value to set 249 | */ 250 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 251 | { 252 | register uint32_t __regFaultMask __ASM("faultmask"); 253 | __regFaultMask = (faultMask & (uint32_t)1); 254 | } 255 | 256 | #endif /* (__CORTEX_M >= 0x03) */ 257 | 258 | 259 | #if (__CORTEX_M == 0x04) 260 | 261 | /** \brief Get FPSCR 262 | 263 | This function returns the current value of the Floating Point Status/Control register. 264 | 265 | \return Floating Point Status/Control register value 266 | */ 267 | __STATIC_INLINE uint32_t __get_FPSCR(void) 268 | { 269 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 270 | register uint32_t __regfpscr __ASM("fpscr"); 271 | return(__regfpscr); 272 | #else 273 | return(0); 274 | #endif 275 | } 276 | 277 | 278 | /** \brief Set FPSCR 279 | 280 | This function assigns the given value to the Floating Point Status/Control register. 281 | 282 | \param [in] fpscr Floating Point Status/Control value to set 283 | */ 284 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 285 | { 286 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 287 | register uint32_t __regfpscr __ASM("fpscr"); 288 | __regfpscr = (fpscr); 289 | #endif 290 | } 291 | 292 | #endif /* (__CORTEX_M == 0x04) */ 293 | 294 | 295 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 296 | /* IAR iccarm specific functions */ 297 | 298 | #include 299 | 300 | 301 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 302 | /* TI CCS specific functions */ 303 | 304 | #include 305 | 306 | 307 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 308 | /* GNU gcc specific functions */ 309 | 310 | /** \brief Enable IRQ Interrupts 311 | 312 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. 313 | Can only be executed in Privileged modes. 314 | */ 315 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) 316 | { 317 | __ASM volatile ("cpsie i"); 318 | } 319 | 320 | 321 | /** \brief Disable IRQ Interrupts 322 | 323 | This function disables IRQ interrupts by setting the I-bit in the CPSR. 324 | Can only be executed in Privileged modes. 325 | */ 326 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) 327 | { 328 | __ASM volatile ("cpsid i"); 329 | } 330 | 331 | 332 | /** \brief Get Control Register 333 | 334 | This function returns the content of the Control Register. 335 | 336 | \return Control Register value 337 | */ 338 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) 339 | { 340 | uint32_t result; 341 | 342 | __ASM volatile ("MRS %0, control" : "=r" (result) ); 343 | return(result); 344 | } 345 | 346 | 347 | /** \brief Set Control Register 348 | 349 | This function writes the given value to the Control Register. 350 | 351 | \param [in] control Control Register value to set 352 | */ 353 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) 354 | { 355 | __ASM volatile ("MSR control, %0" : : "r" (control) ); 356 | } 357 | 358 | 359 | /** \brief Get IPSR Register 360 | 361 | This function returns the content of the IPSR Register. 362 | 363 | \return IPSR Register value 364 | */ 365 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) 366 | { 367 | uint32_t result; 368 | 369 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 370 | return(result); 371 | } 372 | 373 | 374 | /** \brief Get APSR Register 375 | 376 | This function returns the content of the APSR Register. 377 | 378 | \return APSR Register value 379 | */ 380 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) 381 | { 382 | uint32_t result; 383 | 384 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 385 | return(result); 386 | } 387 | 388 | 389 | /** \brief Get xPSR Register 390 | 391 | This function returns the content of the xPSR Register. 392 | 393 | \return xPSR Register value 394 | */ 395 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) 396 | { 397 | uint32_t result; 398 | 399 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 400 | return(result); 401 | } 402 | 403 | 404 | /** \brief Get Process Stack Pointer 405 | 406 | This function returns the current value of the Process Stack Pointer (PSP). 407 | 408 | \return PSP Register value 409 | */ 410 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) 411 | { 412 | register uint32_t result; 413 | 414 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); 415 | return(result); 416 | } 417 | 418 | 419 | /** \brief Set Process Stack Pointer 420 | 421 | This function assigns the given value to the Process Stack Pointer (PSP). 422 | 423 | \param [in] topOfProcStack Process Stack Pointer value to set 424 | */ 425 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 426 | { 427 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); 428 | } 429 | 430 | 431 | /** \brief Get Main Stack Pointer 432 | 433 | This function returns the current value of the Main Stack Pointer (MSP). 434 | 435 | \return MSP Register value 436 | */ 437 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) 438 | { 439 | register uint32_t result; 440 | 441 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); 442 | return(result); 443 | } 444 | 445 | 446 | /** \brief Set Main Stack Pointer 447 | 448 | This function assigns the given value to the Main Stack Pointer (MSP). 449 | 450 | \param [in] topOfMainStack Main Stack Pointer value to set 451 | */ 452 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 453 | { 454 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); 455 | } 456 | 457 | 458 | /** \brief Get Priority Mask 459 | 460 | This function returns the current state of the priority mask bit from the Priority Mask Register. 461 | 462 | \return Priority Mask value 463 | */ 464 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) 465 | { 466 | uint32_t result; 467 | 468 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); 469 | return(result); 470 | } 471 | 472 | 473 | /** \brief Set Priority Mask 474 | 475 | This function assigns the given value to the Priority Mask Register. 476 | 477 | \param [in] priMask Priority Mask 478 | */ 479 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 480 | { 481 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); 482 | } 483 | 484 | 485 | #if (__CORTEX_M >= 0x03) 486 | 487 | /** \brief Enable FIQ 488 | 489 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. 490 | Can only be executed in Privileged modes. 491 | */ 492 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) 493 | { 494 | __ASM volatile ("cpsie f"); 495 | } 496 | 497 | 498 | /** \brief Disable FIQ 499 | 500 | This function disables FIQ interrupts by setting the F-bit in the CPSR. 501 | Can only be executed in Privileged modes. 502 | */ 503 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) 504 | { 505 | __ASM volatile ("cpsid f"); 506 | } 507 | 508 | 509 | /** \brief Get Base Priority 510 | 511 | This function returns the current value of the Base Priority register. 512 | 513 | \return Base Priority register value 514 | */ 515 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) 516 | { 517 | uint32_t result; 518 | 519 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 520 | return(result); 521 | } 522 | 523 | 524 | /** \brief Set Base Priority 525 | 526 | This function assigns the given value to the Base Priority register. 527 | 528 | \param [in] basePri Base Priority value to set 529 | */ 530 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) 531 | { 532 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); 533 | } 534 | 535 | 536 | /** \brief Get Fault Mask 537 | 538 | This function returns the current value of the Fault Mask register. 539 | 540 | \return Fault Mask register value 541 | */ 542 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) 543 | { 544 | uint32_t result; 545 | 546 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 547 | return(result); 548 | } 549 | 550 | 551 | /** \brief Set Fault Mask 552 | 553 | This function assigns the given value to the Fault Mask register. 554 | 555 | \param [in] faultMask Fault Mask value to set 556 | */ 557 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 558 | { 559 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); 560 | } 561 | 562 | #endif /* (__CORTEX_M >= 0x03) */ 563 | 564 | 565 | #if (__CORTEX_M == 0x04) 566 | 567 | /** \brief Get FPSCR 568 | 569 | This function returns the current value of the Floating Point Status/Control register. 570 | 571 | \return Floating Point Status/Control register value 572 | */ 573 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) 574 | { 575 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 576 | uint32_t result; 577 | 578 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 579 | return(result); 580 | #else 581 | return(0); 582 | #endif 583 | } 584 | 585 | 586 | /** \brief Set FPSCR 587 | 588 | This function assigns the given value to the Floating Point Status/Control register. 589 | 590 | \param [in] fpscr Floating Point Status/Control value to set 591 | */ 592 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 593 | { 594 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 595 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); 596 | #endif 597 | } 598 | 599 | #endif /* (__CORTEX_M == 0x04) */ 600 | 601 | 602 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 603 | /* TASKING carm specific functions */ 604 | 605 | /* 606 | * The CMSIS functions have been implemented as intrinsics in the compiler. 607 | * Please use "carm -?i" to get an up to date list of all instrinsics, 608 | * Including the CMSIS ones. 609 | */ 610 | 611 | #endif 612 | 613 | /*@} end of CMSIS_Core_RegAccFunctions */ 614 | 615 | 616 | #endif /* __CORE_CMFUNC_H */ 617 | -------------------------------------------------------------------------------- /cmsis_core/core_cmInstr.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file core_cmInstr.h 3 | * @brief CMSIS Cortex-M Core Instruction Access Header File 4 | * @version V3.01 5 | * @date 06. March 2012 6 | * 7 | * @note 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 9 | * 10 | * @par 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M 12 | * processor based microcontrollers. This file can be freely distributed 13 | * within development tools that are supporting such ARM based processors. 14 | * 15 | * @par 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 21 | * 22 | ******************************************************************************/ 23 | 24 | #ifndef __CORE_CMINSTR_H 25 | #define __CORE_CMINSTR_H 26 | 27 | 28 | /* ########################## Core Instruction Access ######################### */ 29 | /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 30 | Access to dedicated instructions 31 | @{ 32 | */ 33 | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 35 | /* ARM armcc specific functions */ 36 | 37 | #if (__ARMCC_VERSION < 400677) 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 39 | #endif 40 | 41 | 42 | /** \brief No Operation 43 | 44 | No Operation does nothing. This instruction can be used for code alignment purposes. 45 | */ 46 | #define __NOP __nop 47 | 48 | 49 | /** \brief Wait For Interrupt 50 | 51 | Wait For Interrupt is a hint instruction that suspends execution 52 | until one of a number of events occurs. 53 | */ 54 | #define __WFI __wfi 55 | 56 | 57 | /** \brief Wait For Event 58 | 59 | Wait For Event is a hint instruction that permits the processor to enter 60 | a low-power state until one of a number of events occurs. 61 | */ 62 | #define __WFE __wfe 63 | 64 | 65 | /** \brief Send Event 66 | 67 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. 68 | */ 69 | #define __SEV __sev 70 | 71 | 72 | /** \brief Instruction Synchronization Barrier 73 | 74 | Instruction Synchronization Barrier flushes the pipeline in the processor, 75 | so that all instructions following the ISB are fetched from cache or 76 | memory, after the instruction has been completed. 77 | */ 78 | #define __ISB() __isb(0xF) 79 | 80 | 81 | /** \brief Data Synchronization Barrier 82 | 83 | This function acts as a special kind of Data Memory Barrier. 84 | It completes when all explicit memory accesses before this instruction complete. 85 | */ 86 | #define __DSB() __dsb(0xF) 87 | 88 | 89 | /** \brief Data Memory Barrier 90 | 91 | This function ensures the apparent order of the explicit memory operations before 92 | and after the instruction, without ensuring their completion. 93 | */ 94 | #define __DMB() __dmb(0xF) 95 | 96 | 97 | /** \brief Reverse byte order (32 bit) 98 | 99 | This function reverses the byte order in integer value. 100 | 101 | \param [in] value Value to reverse 102 | \return Reversed value 103 | */ 104 | #define __REV __rev 105 | 106 | 107 | /** \brief Reverse byte order (16 bit) 108 | 109 | This function reverses the byte order in two unsigned short values. 110 | 111 | \param [in] value Value to reverse 112 | \return Reversed value 113 | */ 114 | __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) 115 | { 116 | rev16 r0, r0 117 | bx lr 118 | } 119 | 120 | 121 | /** \brief Reverse byte order in signed short value 122 | 123 | This function reverses the byte order in a signed short value with sign extension to integer. 124 | 125 | \param [in] value Value to reverse 126 | \return Reversed value 127 | */ 128 | __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) 129 | { 130 | revsh r0, r0 131 | bx lr 132 | } 133 | 134 | 135 | /** \brief Rotate Right in unsigned value (32 bit) 136 | 137 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 138 | 139 | \param [in] value Value to rotate 140 | \param [in] value Number of Bits to rotate 141 | \return Rotated value 142 | */ 143 | #define __ROR __ror 144 | 145 | 146 | #if (__CORTEX_M >= 0x03) 147 | 148 | /** \brief Reverse bit order of value 149 | 150 | This function reverses the bit order of the given value. 151 | 152 | \param [in] value Value to reverse 153 | \return Reversed value 154 | */ 155 | #define __RBIT __rbit 156 | 157 | 158 | /** \brief LDR Exclusive (8 bit) 159 | 160 | This function performs a exclusive LDR command for 8 bit value. 161 | 162 | \param [in] ptr Pointer to data 163 | \return value of type uint8_t at (*ptr) 164 | */ 165 | #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) 166 | 167 | 168 | /** \brief LDR Exclusive (16 bit) 169 | 170 | This function performs a exclusive LDR command for 16 bit values. 171 | 172 | \param [in] ptr Pointer to data 173 | \return value of type uint16_t at (*ptr) 174 | */ 175 | #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) 176 | 177 | 178 | /** \brief LDR Exclusive (32 bit) 179 | 180 | This function performs a exclusive LDR command for 32 bit values. 181 | 182 | \param [in] ptr Pointer to data 183 | \return value of type uint32_t at (*ptr) 184 | */ 185 | #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) 186 | 187 | 188 | /** \brief STR Exclusive (8 bit) 189 | 190 | This function performs a exclusive STR command for 8 bit values. 191 | 192 | \param [in] value Value to store 193 | \param [in] ptr Pointer to location 194 | \return 0 Function succeeded 195 | \return 1 Function failed 196 | */ 197 | #define __STREXB(value, ptr) __strex(value, ptr) 198 | 199 | 200 | /** \brief STR Exclusive (16 bit) 201 | 202 | This function performs a exclusive STR command for 16 bit values. 203 | 204 | \param [in] value Value to store 205 | \param [in] ptr Pointer to location 206 | \return 0 Function succeeded 207 | \return 1 Function failed 208 | */ 209 | #define __STREXH(value, ptr) __strex(value, ptr) 210 | 211 | 212 | /** \brief STR Exclusive (32 bit) 213 | 214 | This function performs a exclusive STR command for 32 bit values. 215 | 216 | \param [in] value Value to store 217 | \param [in] ptr Pointer to location 218 | \return 0 Function succeeded 219 | \return 1 Function failed 220 | */ 221 | #define __STREXW(value, ptr) __strex(value, ptr) 222 | 223 | 224 | /** \brief Remove the exclusive lock 225 | 226 | This function removes the exclusive lock which is created by LDREX. 227 | 228 | */ 229 | #define __CLREX __clrex 230 | 231 | 232 | /** \brief Signed Saturate 233 | 234 | This function saturates a signed value. 235 | 236 | \param [in] value Value to be saturated 237 | \param [in] sat Bit position to saturate to (1..32) 238 | \return Saturated value 239 | */ 240 | #define __SSAT __ssat 241 | 242 | 243 | /** \brief Unsigned Saturate 244 | 245 | This function saturates an unsigned value. 246 | 247 | \param [in] value Value to be saturated 248 | \param [in] sat Bit position to saturate to (0..31) 249 | \return Saturated value 250 | */ 251 | #define __USAT __usat 252 | 253 | 254 | /** \brief Count leading zeros 255 | 256 | This function counts the number of leading zeros of a data value. 257 | 258 | \param [in] value Value to count the leading zeros 259 | \return number of leading zeros in value 260 | */ 261 | #define __CLZ __clz 262 | 263 | #endif /* (__CORTEX_M >= 0x03) */ 264 | 265 | 266 | 267 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 268 | /* IAR iccarm specific functions */ 269 | 270 | #include 271 | 272 | 273 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 274 | /* TI CCS specific functions */ 275 | 276 | #include 277 | 278 | 279 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 280 | /* GNU gcc specific functions */ 281 | 282 | /** \brief No Operation 283 | 284 | No Operation does nothing. This instruction can be used for code alignment purposes. 285 | */ 286 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) 287 | { 288 | __ASM volatile ("nop"); 289 | } 290 | 291 | 292 | /** \brief Wait For Interrupt 293 | 294 | Wait For Interrupt is a hint instruction that suspends execution 295 | until one of a number of events occurs. 296 | */ 297 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) 298 | { 299 | __ASM volatile ("wfi"); 300 | } 301 | 302 | 303 | /** \brief Wait For Event 304 | 305 | Wait For Event is a hint instruction that permits the processor to enter 306 | a low-power state until one of a number of events occurs. 307 | */ 308 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) 309 | { 310 | __ASM volatile ("wfe"); 311 | } 312 | 313 | 314 | /** \brief Send Event 315 | 316 | Send Event is a hint instruction. It causes an event to be signaled to the CPU. 317 | */ 318 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) 319 | { 320 | __ASM volatile ("sev"); 321 | } 322 | 323 | 324 | /** \brief Instruction Synchronization Barrier 325 | 326 | Instruction Synchronization Barrier flushes the pipeline in the processor, 327 | so that all instructions following the ISB are fetched from cache or 328 | memory, after the instruction has been completed. 329 | */ 330 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) 331 | { 332 | __ASM volatile ("isb"); 333 | } 334 | 335 | 336 | /** \brief Data Synchronization Barrier 337 | 338 | This function acts as a special kind of Data Memory Barrier. 339 | It completes when all explicit memory accesses before this instruction complete. 340 | */ 341 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) 342 | { 343 | __ASM volatile ("dsb"); 344 | } 345 | 346 | 347 | /** \brief Data Memory Barrier 348 | 349 | This function ensures the apparent order of the explicit memory operations before 350 | and after the instruction, without ensuring their completion. 351 | */ 352 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) 353 | { 354 | __ASM volatile ("dmb"); 355 | } 356 | 357 | 358 | /** \brief Reverse byte order (32 bit) 359 | 360 | This function reverses the byte order in integer value. 361 | 362 | \param [in] value Value to reverse 363 | \return Reversed value 364 | */ 365 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) 366 | { 367 | uint32_t result; 368 | 369 | __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); 370 | return(result); 371 | } 372 | 373 | 374 | /** \brief Reverse byte order (16 bit) 375 | 376 | This function reverses the byte order in two unsigned short values. 377 | 378 | \param [in] value Value to reverse 379 | \return Reversed value 380 | */ 381 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) 382 | { 383 | uint32_t result; 384 | 385 | __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); 386 | return(result); 387 | } 388 | 389 | 390 | /** \brief Reverse byte order in signed short value 391 | 392 | This function reverses the byte order in a signed short value with sign extension to integer. 393 | 394 | \param [in] value Value to reverse 395 | \return Reversed value 396 | */ 397 | __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) 398 | { 399 | uint32_t result; 400 | 401 | __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); 402 | return(result); 403 | } 404 | 405 | 406 | /** \brief Rotate Right in unsigned value (32 bit) 407 | 408 | This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. 409 | 410 | \param [in] value Value to rotate 411 | \param [in] value Number of Bits to rotate 412 | \return Rotated value 413 | */ 414 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 415 | { 416 | 417 | __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); 418 | return(op1); 419 | } 420 | 421 | 422 | #if (__CORTEX_M >= 0x03) 423 | 424 | /** \brief Reverse bit order of value 425 | 426 | This function reverses the bit order of the given value. 427 | 428 | \param [in] value Value to reverse 429 | \return Reversed value 430 | */ 431 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) 432 | { 433 | uint32_t result; 434 | 435 | __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 436 | return(result); 437 | } 438 | 439 | 440 | /** \brief LDR Exclusive (8 bit) 441 | 442 | This function performs a exclusive LDR command for 8 bit value. 443 | 444 | \param [in] ptr Pointer to data 445 | \return value of type uint8_t at (*ptr) 446 | */ 447 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) 448 | { 449 | uint8_t result; 450 | 451 | __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); 452 | return(result); 453 | } 454 | 455 | 456 | /** \brief LDR Exclusive (16 bit) 457 | 458 | This function performs a exclusive LDR command for 16 bit values. 459 | 460 | \param [in] ptr Pointer to data 461 | \return value of type uint16_t at (*ptr) 462 | */ 463 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) 464 | { 465 | uint16_t result; 466 | 467 | __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); 468 | return(result); 469 | } 470 | 471 | 472 | /** \brief LDR Exclusive (32 bit) 473 | 474 | This function performs a exclusive LDR command for 32 bit values. 475 | 476 | \param [in] ptr Pointer to data 477 | \return value of type uint32_t at (*ptr) 478 | */ 479 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) 480 | { 481 | uint32_t result; 482 | 483 | __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); 484 | return(result); 485 | } 486 | 487 | 488 | /** \brief STR Exclusive (8 bit) 489 | 490 | This function performs a exclusive STR command for 8 bit values. 491 | 492 | \param [in] value Value to store 493 | \param [in] ptr Pointer to location 494 | \return 0 Function succeeded 495 | \return 1 Function failed 496 | */ 497 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 498 | { 499 | uint32_t result; 500 | 501 | __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 502 | return(result); 503 | } 504 | 505 | 506 | /** \brief STR Exclusive (16 bit) 507 | 508 | This function performs a exclusive STR command for 16 bit values. 509 | 510 | \param [in] value Value to store 511 | \param [in] ptr Pointer to location 512 | \return 0 Function succeeded 513 | \return 1 Function failed 514 | */ 515 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 516 | { 517 | uint32_t result; 518 | 519 | __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 520 | return(result); 521 | } 522 | 523 | 524 | /** \brief STR Exclusive (32 bit) 525 | 526 | This function performs a exclusive STR command for 32 bit values. 527 | 528 | \param [in] value Value to store 529 | \param [in] ptr Pointer to location 530 | \return 0 Function succeeded 531 | \return 1 Function failed 532 | */ 533 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 534 | { 535 | uint32_t result; 536 | 537 | __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); 538 | return(result); 539 | } 540 | 541 | 542 | /** \brief Remove the exclusive lock 543 | 544 | This function removes the exclusive lock which is created by LDREX. 545 | 546 | */ 547 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) 548 | { 549 | __ASM volatile ("clrex"); 550 | } 551 | 552 | 553 | /** \brief Signed Saturate 554 | 555 | This function saturates a signed value. 556 | 557 | \param [in] value Value to be saturated 558 | \param [in] sat Bit position to saturate to (1..32) 559 | \return Saturated value 560 | */ 561 | #define __SSAT(ARG1,ARG2) \ 562 | ({ \ 563 | uint32_t __RES, __ARG1 = (ARG1); \ 564 | __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 565 | __RES; \ 566 | }) 567 | 568 | 569 | /** \brief Unsigned Saturate 570 | 571 | This function saturates an unsigned value. 572 | 573 | \param [in] value Value to be saturated 574 | \param [in] sat Bit position to saturate to (0..31) 575 | \return Saturated value 576 | */ 577 | #define __USAT(ARG1,ARG2) \ 578 | ({ \ 579 | uint32_t __RES, __ARG1 = (ARG1); \ 580 | __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ 581 | __RES; \ 582 | }) 583 | 584 | 585 | /** \brief Count leading zeros 586 | 587 | This function counts the number of leading zeros of a data value. 588 | 589 | \param [in] value Value to count the leading zeros 590 | \return number of leading zeros in value 591 | */ 592 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) 593 | { 594 | uint8_t result; 595 | 596 | __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); 597 | return(result); 598 | } 599 | 600 | #endif /* (__CORTEX_M >= 0x03) */ 601 | 602 | 603 | 604 | 605 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 606 | /* TASKING carm specific functions */ 607 | 608 | /* 609 | * The CMSIS functions have been implemented as intrinsics in the compiler. 610 | * Please use "carm -?i" to get an up to date list of all intrinsics, 611 | * Including the CMSIS ones. 612 | */ 613 | 614 | #endif 615 | 616 | /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 617 | 618 | #endif /* __CORE_CMINSTR_H */ 619 | -------------------------------------------------------------------------------- /dmx512.c: -------------------------------------------------------------------------------- 1 | /* 2 | * STM32F030 DMX512 library 3 | * 4 | * Copyright (c) 2015 Antti Nykanen 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | */ 24 | 25 | #include "dmx512.h" 26 | 27 | #include "stm32f0xx_dma.h" 28 | #include "stm32f0xx_gpio.h" 29 | #include "stm32f0xx_misc.h" 30 | #include "stm32f0xx_rcc.h" 31 | #include "stm32f0xx_syscfg.h" 32 | #include "stm32f0xx_tim.h" 33 | #include "stm32f0xx_usart.h" 34 | 35 | /* 36 | * Local function definitions 37 | */ 38 | void DMX512_Init_RCC(void); 39 | void DMX512_Init_GPIO(void); 40 | void DMX512_Init_USART(void); 41 | void DMX512_Init_DMA(void); 42 | void DMX512_Init_Timer(void); 43 | 44 | void DMX512_Set_State(DMX512_State_TypeDef state); 45 | void DMX512_Set_State_USART(DMX512_State_TypeDef state); 46 | void DMX512_Set_State_Timer(DMX512_State_TypeDef state); 47 | /* -- */ 48 | 49 | /* Internal state variable */ 50 | __IO DMX512_State_TypeDef DMX512_State = DMX512_STATE_OFF; 51 | 52 | /* Shared NVIC initialization structure */ 53 | static NVIC_InitTypeDef NVIC_InitStructure; 54 | 55 | void DMX512_Init(void) 56 | { 57 | DMX512_Init_RCC(); 58 | DMX512_Init_GPIO(); 59 | DMX512_Init_USART(); 60 | DMX512_Init_DMA(); 61 | DMX512_Init_Timer(); 62 | 63 | DMX512_Set_State(DMX512_STATE_COMPLETE); 64 | } 65 | 66 | void DMX512_Init_RCC(void) 67 | { 68 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1 | RCC_AHBPeriph_GPIOA, ENABLE); 69 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE); 70 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | RCC_APB2Periph_USART1, ENABLE); 71 | } 72 | 73 | void DMX512_Init_GPIO(void) 74 | { 75 | GPIO_InitTypeDef GPIO_InitStructure; 76 | 77 | /* Configure GPIO pin 10 */ 78 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 79 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 80 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 81 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; 82 | GPIO_Init(GPIOA, &GPIO_InitStructure); 83 | 84 | /* Enable GPIO pin 10 alternate function */ 85 | GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1); 86 | } 87 | 88 | void DMX512_Init_USART(void) 89 | { 90 | USART_InitTypeDef USART_InitStructure; 91 | /* Shared NVIC_InitStructure */ 92 | 93 | USART_InitStructure.USART_BaudRate = 250000; 94 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 95 | USART_InitStructure.USART_Mode = USART_Mode_Rx; 96 | USART_InitStructure.USART_Parity = USART_Parity_No; 97 | USART_InitStructure.USART_StopBits = 2; 98 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 99 | USART_Init(USART1, &USART_InitStructure); 100 | 101 | NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn; 102 | NVIC_InitStructure.NVIC_IRQChannelPriority = 1; 103 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 104 | NVIC_Init(&NVIC_InitStructure); 105 | 106 | USART_Cmd(USART1, ENABLE); 107 | USART_DMACmd(USART1, USART_DMAReq_Rx, ENABLE); 108 | } 109 | 110 | void DMX512_Init_DMA(void) 111 | { 112 | DMA_InitTypeDef DMA_InitStructure; 113 | /* Shared NVIC_InitStructure */ 114 | 115 | /* Remap USART1 Rx to DMA1 Channel5 */ 116 | SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_USART1Rx, ENABLE); 117 | 118 | DMA_InitStructure.DMA_BufferSize = (uint32_t)DMX512_DATA_LENGTH; 119 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 120 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 121 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)DMX512_Data; 122 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 123 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 124 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; 125 | DMA_InitStructure.DMA_PeripheralBaseAddr = ((uint32_t)&(USART1->RDR)); 126 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; 127 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 128 | DMA_InitStructure.DMA_Priority = DMA_Priority_High; 129 | DMA_Init(DMA1_Channel5, &DMA_InitStructure); 130 | 131 | NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel4_5_IRQn; 132 | NVIC_InitStructure.NVIC_IRQChannelPriority = 1; 133 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 134 | NVIC_Init(&NVIC_InitStructure); 135 | } 136 | 137 | void DMX512_Init_Timer(void) 138 | { 139 | TIM_TimeBaseInitTypeDef TIM_InitStructure; 140 | /* Shared NVIC_InitStructure */ 141 | 142 | /* Assuming 8MHz clock */ 143 | TIM_InitStructure.TIM_ClockDivision = 0; 144 | TIM_InitStructure.TIM_CounterMode = TIM_CounterMode_Up; 145 | TIM_InitStructure.TIM_Prescaler = 11; 146 | TIM_InitStructure.TIM_Period = 0xFFFF; 147 | TIM_InitStructure.TIM_RepetitionCounter = 0; 148 | TIM_TimeBaseInit(TIM14, &TIM_InitStructure); 149 | 150 | NVIC_InitStructure.NVIC_IRQChannel = TIM14_IRQn; 151 | NVIC_InitStructure.NVIC_IRQChannelPriority = 3; 152 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 153 | NVIC_Init(&NVIC_InitStructure); 154 | } 155 | 156 | DMX512_State_TypeDef DMX512_Get_State(void) 157 | { 158 | return DMX512_State; 159 | } 160 | 161 | void DMX512_Set_State(DMX512_State_TypeDef state) 162 | { 163 | DMX512_State = state; 164 | 165 | DMX512_Set_State_USART(state); 166 | DMX512_Set_State_Timer(state); 167 | } 168 | 169 | void DMX512_Set_State_USART(DMX512_State_TypeDef state) 170 | { 171 | if (state == DMX512_STATE_IN_DATA) { 172 | USART_ITConfig(USART1, USART_IT_RXNE, DISABLE); 173 | 174 | DMA_ClearFlag(DMA1_FLAG_TC5 | DMA1_FLAG_HT5 | DMA1_FLAG_GL5 | DMA1_FLAG_TE5); 175 | DMA_ITConfig(DMA1_Channel5, DMA_IT_TC, ENABLE); 176 | 177 | DMA_SetCurrDataCounter(DMA1_Channel5, (uint16_t)DMX512_DATA_LENGTH); 178 | DMA_Cmd(DMA1_Channel5, ENABLE); 179 | } else { 180 | DMA_Cmd(DMA1_Channel5, DISABLE); 181 | 182 | if (state == DMX512_STATE_IDLE) { 183 | USART_ITConfig(USART1, USART_IT_ERR, ENABLE); 184 | USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); 185 | } else if (state == DMX512_STATE_IN_BREAK) { 186 | USART_ITConfig(USART1, USART_IT_ERR, DISABLE); 187 | } 188 | } 189 | } 190 | 191 | void DMX512_Set_State_Timer(DMX512_State_TypeDef state) 192 | { 193 | if (state == DMX512_STATE_IN_DATA) { 194 | TIM14->SR = 0; 195 | TIM_SetCounter(TIM14, 0); 196 | TIM_ITConfig(TIM14, TIM_IT_Update, ENABLE); 197 | TIM_Cmd(TIM14, ENABLE); 198 | } else { 199 | TIM_ITConfig(TIM14, TIM_IT_Update, DISABLE); 200 | TIM_Cmd(TIM14, DISABLE); 201 | } 202 | } 203 | 204 | void DMX512_Receive(void) 205 | { 206 | if (DMX512_State != DMX512_STATE_IDLE) 207 | DMX512_Set_State(DMX512_STATE_IDLE); 208 | } 209 | 210 | void USART1_IRQHandler(void) 211 | { 212 | uint8_t data; 213 | 214 | data = (uint8_t)(USART_ReceiveData(USART1) & 0xFF); 215 | 216 | if (USART_GetITStatus(USART1, USART_IT_FE)) { 217 | if (data == 0x00 && DMX512_State == DMX512_STATE_IDLE) 218 | DMX512_Set_State(DMX512_STATE_IN_BREAK); 219 | 220 | USART_ClearFlag(USART1, USART_FLAG_FE); 221 | } else if (DMX512_State == DMX512_STATE_IN_BREAK && !USART_GetFlagStatus(USART1, USART_FLAG_FE)) { 222 | DMX512_Set_State(DMX512_STATE_IN_DATA); 223 | } 224 | 225 | USART_ClearFlag(USART1, USART_FLAG_NE | USART_FLAG_FE | USART_FLAG_ORE | USART_FLAG_RXNE); 226 | USART_ClearITPendingBit(USART1, USART_IT_RXNE); 227 | USART_ClearITPendingBit(USART1, USART_IT_FE); 228 | } 229 | 230 | void TIM14_IRQHandler(void) 231 | { 232 | TIM_ClearITPendingBit(TIM14, TIM_IT_Update); 233 | DMX512_Set_State(DMX512_STATE_ERROR); 234 | } 235 | 236 | void DMA1_Channel4_5_IRQHandler(void) 237 | { 238 | DMA_ClearITPendingBit(DMA1_IT_TC5); 239 | DMX512_Set_State(DMX512_STATE_COMPLETE); 240 | } 241 | -------------------------------------------------------------------------------- /dmx512.h: -------------------------------------------------------------------------------- 1 | /* 2 | * STM32F030 DMX512 library 3 | * 4 | * Copyright (c) 2015 Antti Nykanen 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | */ 24 | 25 | #ifndef __DMX512_H 26 | #define __DMX512_H 27 | 28 | #include "stm32f0xx.h" 29 | 30 | /* Initial 0 + SC + 512 bytes of data */ 31 | #define DMX512_DATA_LENGTH 512 32 | __IO uint8_t DMX512_Data[DMX512_DATA_LENGTH]; 33 | 34 | typedef enum { 35 | DMX512_STATE_OFF, // Uninitialized 36 | DMX512_STATE_COMPLETE, // Data complete or nothing has been done yet 37 | DMX512_STATE_IDLE, // Waiting for break 38 | DMX512_STATE_IN_BREAK, 39 | DMX512_STATE_IN_DATA, // Data is being received 40 | DMX512_STATE_ERROR // Error 41 | } DMX512_State_TypeDef; 42 | 43 | DMX512_State_TypeDef DMX512_Get_State(void); 44 | 45 | void DMX512_Init(void); 46 | void DMX512_Receive(void); 47 | 48 | uint8_t DMX512_Get_Channel(uint16_t channel); 49 | 50 | void USART1_IRQHandler(void); 51 | void DMA1_Channel4_5_IRQHandler(void); 52 | void TIM14_IRQHandler(void); 53 | 54 | #endif /* __DMX512_H */ 55 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * STM32F030 DMX512 WS2812B driver 3 | * 4 | * Copyright (c) 2015 Antti Nykanen 5 | * 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy 7 | * of this software and associated documentation files (the "Software"), to deal 8 | * in the Software without restriction, including without limitation the rights 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 | * copies of the Software, and to permit persons to whom the Software is 11 | * furnished to do so, subject to the following conditions: 12 | 13 | * The above copyright notice and this permission notice shall be included in 14 | * all copies or substantial portions of the Software. 15 | 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 | * THE SOFTWARE. 23 | */ 24 | 25 | #include "dmx512.h" 26 | #include "ws2812b.h" 27 | 28 | int main(void) 29 | { 30 | uint8_t i; 31 | DMX512_Init(); 32 | 33 | WS2812B_Init_GPIO(); 34 | WS2812B_Init_Timer(); 35 | WS2812B_Init_DMA(); 36 | 37 | while(1) { 38 | while (!WS2812B_Get_TC()); 39 | 40 | if (DMX512_Get_State() == DMX512_STATE_COMPLETE) { 41 | for (i = 0; i < 10; i++) 42 | WS2812B_Set_Pixel(0, i, DMX512_Data[i*3+1], DMX512_Data[i*3+2], DMX512_Data[i*3+3]); 43 | WS2812B_Send_Buffer(); 44 | } 45 | 46 | if (DMX512_Get_State() == DMX512_STATE_COMPLETE || DMX512_Get_State() == DMX512_STATE_ERROR) 47 | DMX512_Receive(); 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /stm32_lib/inc/stm32f0xx_dma.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_dma.h 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 01-August-2013 7 | * @brief This file contains all the functions prototypes for the DMA firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_RCC_H 31 | #define __STM32F0XX_RCC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup RCC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | typedef struct 51 | { 52 | uint32_t SYSCLK_Frequency; 53 | uint32_t HCLK_Frequency; 54 | uint32_t PCLK_Frequency; 55 | uint32_t ADCCLK_Frequency; 56 | uint32_t CECCLK_Frequency; 57 | uint32_t I2C1CLK_Frequency; 58 | uint32_t USART1CLK_Frequency; 59 | }RCC_ClocksTypeDef; 60 | 61 | /* Exported constants --------------------------------------------------------*/ 62 | 63 | /** @defgroup RCC_Exported_Constants 64 | * @{ 65 | */ 66 | 67 | /** @defgroup RCC_HSE_configuration 68 | * @{ 69 | */ 70 | 71 | #define RCC_HSE_OFF ((uint8_t)0x00) 72 | #define RCC_HSE_ON ((uint8_t)0x01) 73 | #define RCC_HSE_Bypass ((uint8_t)0x05) 74 | #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 75 | ((HSE) == RCC_HSE_Bypass)) 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @defgroup RCC_PLL_Clock_Source 82 | * @{ 83 | */ 84 | 85 | #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2 86 | #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1 87 | 88 | #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 89 | ((SOURCE) == RCC_PLLSource_PREDIV1)) 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup RCC_PLL_Multiplication_Factor 95 | * @{ 96 | */ 97 | 98 | #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2 99 | #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3 100 | #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4 101 | #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5 102 | #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6 103 | #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7 104 | #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8 105 | #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9 106 | #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10 107 | #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11 108 | #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12 109 | #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13 110 | #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14 111 | #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15 112 | #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16 113 | #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 114 | ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 115 | ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 116 | ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 117 | ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 118 | ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 119 | ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 120 | ((MUL) == RCC_PLLMul_16)) 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup RCC_PREDIV1_division_factor 126 | * @{ 127 | */ 128 | #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1 129 | #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2 130 | #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3 131 | #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4 132 | #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5 133 | #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6 134 | #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7 135 | #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8 136 | #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9 137 | #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10 138 | #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11 139 | #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12 140 | #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13 141 | #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14 142 | #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15 143 | #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16 144 | 145 | #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ 146 | ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ 147 | ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ 148 | ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ 149 | ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ 150 | ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ 151 | ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ 152 | ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) 153 | /** 154 | * @} 155 | */ 156 | 157 | /** @defgroup RCC_System_Clock_Source 158 | * @{ 159 | */ 160 | 161 | #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI 162 | #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE 163 | #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL 164 | #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 165 | ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 166 | ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 167 | /** 168 | * @} 169 | */ 170 | 171 | /** @defgroup RCC_AHB_Clock_Source 172 | * @{ 173 | */ 174 | 175 | #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1 176 | #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2 177 | #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4 178 | #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8 179 | #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16 180 | #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64 181 | #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128 182 | #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256 183 | #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512 184 | #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 185 | ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 186 | ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 187 | ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 188 | ((HCLK) == RCC_SYSCLK_Div512)) 189 | /** 190 | * @} 191 | */ 192 | 193 | /** @defgroup RCC_APB_Clock_Source 194 | * @{ 195 | */ 196 | 197 | #define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1 198 | #define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2 199 | #define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4 200 | #define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8 201 | #define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16 202 | #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 203 | ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 204 | ((PCLK) == RCC_HCLK_Div16)) 205 | /** 206 | * @} 207 | */ 208 | 209 | /** @defgroup RCC_ADC_clock_source 210 | * @{ 211 | */ 212 | 213 | #define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000) 214 | #define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000) 215 | #define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000) 216 | 217 | #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \ 218 | ((ADCCLK) == RCC_ADCCLK_PCLK_Div4)) 219 | 220 | /** 221 | * @} 222 | */ 223 | 224 | /** @defgroup RCC_CEC_clock_source 225 | * @{ 226 | */ 227 | 228 | #define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000) 229 | #define RCC_CECCLK_LSE RCC_CFGR3_CECSW 230 | 231 | #define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE)) 232 | 233 | /** 234 | * @} 235 | */ 236 | 237 | /** @defgroup RCC_I2C_clock_source 238 | * @{ 239 | */ 240 | 241 | #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000) 242 | #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW 243 | 244 | #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK)) 245 | 246 | /** 247 | * @} 248 | */ 249 | 250 | /** @defgroup RCC_USART_clock_source 251 | * @{ 252 | */ 253 | 254 | #define RCC_USART1CLK_PCLK ((uint32_t)0x00000000) 255 | #define RCC_USART1CLK_SYSCLK RCC_CFGR3_USART1SW_0 256 | #define RCC_USART1CLK_LSE RCC_CFGR3_USART1SW_1 257 | #define RCC_USART1CLK_HSI RCC_CFGR3_USART1SW 258 | 259 | #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \ 260 | ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI)) 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | /** @defgroup RCC_Interrupt_Source 267 | * @{ 268 | */ 269 | 270 | #define RCC_IT_LSIRDY ((uint8_t)0x01) 271 | #define RCC_IT_LSERDY ((uint8_t)0x02) 272 | #define RCC_IT_HSIRDY ((uint8_t)0x04) 273 | #define RCC_IT_HSERDY ((uint8_t)0x08) 274 | #define RCC_IT_PLLRDY ((uint8_t)0x10) 275 | #define RCC_IT_HSI14RDY ((uint8_t)0x20) 276 | #define RCC_IT_CSS ((uint8_t)0x80) 277 | 278 | #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) 279 | 280 | #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 281 | ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 282 | ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \ 283 | ((IT) == RCC_IT_CSS)) 284 | 285 | #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) 286 | 287 | /** 288 | * @} 289 | */ 290 | 291 | /** @defgroup RCC_LSE_Configuration 292 | * @{ 293 | */ 294 | 295 | #define RCC_LSE_OFF ((uint32_t)0x00000000) 296 | #define RCC_LSE_ON RCC_BDCR_LSEON 297 | #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP)) 298 | #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 299 | ((LSE) == RCC_LSE_Bypass)) 300 | /** 301 | * @} 302 | */ 303 | 304 | /** @defgroup RCC_RTC_Clock_Source 305 | * @{ 306 | */ 307 | 308 | #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE 309 | #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI 310 | #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE 311 | 312 | #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 313 | ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 314 | ((SOURCE) == RCC_RTCCLKSource_HSE_Div32)) 315 | /** 316 | * @} 317 | */ 318 | 319 | /** @defgroup RCC_LSE_Drive_Configuration 320 | * @{ 321 | */ 322 | 323 | #define RCC_LSEDrive_Low ((uint32_t)0x00000000) 324 | #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0 325 | #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1 326 | #define RCC_LSEDrive_High RCC_BDCR_LSEDRV 327 | #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ 328 | ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) 329 | /** 330 | * @} 331 | */ 332 | 333 | /** @defgroup RCC_AHB_Peripherals 334 | * @{ 335 | */ 336 | 337 | #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN 338 | #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN 339 | #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN 340 | #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN 341 | #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN 342 | #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN 343 | #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN 344 | #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN 345 | #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN 346 | #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN 347 | 348 | #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00)) 349 | #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00)) 350 | 351 | /** 352 | * @} 353 | */ 354 | 355 | /** @defgroup RCC_APB2_Peripherals 356 | * @{ 357 | */ 358 | 359 | #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN 360 | #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN 361 | #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN 362 | #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN 363 | #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN 364 | #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN 365 | #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN 366 | #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN 367 | #define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN 368 | 369 | #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00)) 370 | 371 | /** 372 | * @} 373 | */ 374 | 375 | /** @defgroup RCC_APB1_Peripherals 376 | * @{ 377 | */ 378 | 379 | #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN 380 | #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN 381 | #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN 382 | #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN 383 | #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN 384 | #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN 385 | #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN 386 | #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN 387 | #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN 388 | #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN 389 | #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN 390 | #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN 391 | 392 | #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00)) 393 | /** 394 | * @} 395 | */ 396 | 397 | /** @defgroup RCC_MCO_Clock_Source 398 | * @{ 399 | */ 400 | 401 | #define RCC_MCOSource_NoClock ((uint8_t)0x00) 402 | #define RCC_MCOSource_HSI14 ((uint8_t)0x01) 403 | #define RCC_MCOSource_LSI ((uint8_t)0x02) 404 | #define RCC_MCOSource_LSE ((uint8_t)0x03) 405 | #define RCC_MCOSource_SYSCLK ((uint8_t)0x04) 406 | #define RCC_MCOSource_HSI ((uint8_t)0x05) 407 | #define RCC_MCOSource_HSE ((uint8_t)0x06) 408 | #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07) 409 | 410 | #if defined (STM32F0XX_MD) || defined (STM32F030X8) 411 | #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ 412 | ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ 413 | ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ 414 | ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE)) 415 | #else 416 | #define RCC_MCOSource_PLLCLK ((uint8_t)0x87) 417 | 418 | #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \ 419 | ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \ 420 | ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \ 421 | ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \ 422 | ((SOURCE) == RCC_MCOSource_PLLCLK)) 423 | #endif /* STM32F0XX_MD or STM32F030X8 */ 424 | /** 425 | * @} 426 | */ 427 | 428 | /** @defgroup RCC_MCOPrescaler 429 | * @{ 430 | */ 431 | #if !defined (STM32F0XX_MD) && !defined (STM32F030X8) 432 | #define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1 433 | #define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2 434 | #define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4 435 | #define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8 436 | #define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16 437 | #define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32 438 | #define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64 439 | #define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128 440 | 441 | #define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \ 442 | ((PRESCALER) == RCC_MCOPrescaler_2) || \ 443 | ((PRESCALER) == RCC_MCOPrescaler_4) || \ 444 | ((PRESCALER) == RCC_MCOPrescaler_8) || \ 445 | ((PRESCALER) == RCC_MCOPrescaler_16) || \ 446 | ((PRESCALER) == RCC_MCOPrescaler_32) || \ 447 | ((PRESCALER) == RCC_MCOPrescaler_64) || \ 448 | ((PRESCALER) == RCC_MCOPrescaler_128)) 449 | #endif /* STM32F0XX_MD or STM32F030X8 */ 450 | /** 451 | * @} 452 | */ 453 | 454 | 455 | /** @defgroup RCC_Flag 456 | * @{ 457 | */ 458 | #define RCC_FLAG_HSIRDY ((uint8_t)0x01) 459 | #define RCC_FLAG_HSERDY ((uint8_t)0x11) 460 | #define RCC_FLAG_PLLRDY ((uint8_t)0x19) 461 | #define RCC_FLAG_LSERDY ((uint8_t)0x21) 462 | #define RCC_FLAG_LSIRDY ((uint8_t)0x41) 463 | #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57) 464 | #define RCC_FLAG_OBLRST ((uint8_t)0x59) 465 | #define RCC_FLAG_PINRST ((uint8_t)0x5A) 466 | #define RCC_FLAG_PORRST ((uint8_t)0x5B) 467 | #define RCC_FLAG_SFTRST ((uint8_t)0x5C) 468 | #define RCC_FLAG_IWDGRST ((uint8_t)0x5D) 469 | #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) 470 | #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) 471 | #define RCC_FLAG_HSI14RDY ((uint8_t)0x61) 472 | 473 | #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 474 | ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 475 | ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \ 476 | ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ 477 | ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ 478 | ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ 479 | ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_V18PWRRSTF)) 480 | 481 | #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 482 | #define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 483 | 484 | /** 485 | * @} 486 | */ 487 | 488 | /** 489 | * @} 490 | */ 491 | 492 | /* Exported macro ------------------------------------------------------------*/ 493 | /* Exported functions ------------------------------------------------------- */ 494 | 495 | /* Function used to set the RCC clock configuration to the default reset state */ 496 | void RCC_DeInit(void); 497 | 498 | /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ 499 | void RCC_HSEConfig(uint8_t RCC_HSE); 500 | ErrorStatus RCC_WaitForHSEStartUp(void); 501 | void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 502 | void RCC_HSICmd(FunctionalState NewState); 503 | void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue); 504 | void RCC_HSI14Cmd(FunctionalState NewState); 505 | void RCC_HSI14ADCRequestCmd(FunctionalState NewState); 506 | void RCC_LSEConfig(uint32_t RCC_LSE); 507 | void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive); 508 | void RCC_LSICmd(FunctionalState NewState); 509 | void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 510 | void RCC_PLLCmd(FunctionalState NewState); 511 | void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div); 512 | void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 513 | #if defined (STM32F0XX_MD) || defined (STM32F030X8) 514 | void RCC_MCOConfig(uint8_t RCC_MCOSource); 515 | #else 516 | void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler); 517 | #endif /* STM32F0XX_MD or STM32F030X8 */ 518 | 519 | /* System, AHB and APB busses clocks configuration functions ******************/ 520 | void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 521 | uint8_t RCC_GetSYSCLKSource(void); 522 | void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 523 | void RCC_PCLKConfig(uint32_t RCC_HCLK); 524 | void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); 525 | void RCC_CECCLKConfig(uint32_t RCC_CECCLK); 526 | void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK); 527 | void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK); 528 | void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 529 | 530 | /* Peripheral clocks configuration functions **********************************/ 531 | void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 532 | void RCC_RTCCLKCmd(FunctionalState NewState); 533 | void RCC_BackupResetCmd(FunctionalState NewState); 534 | 535 | void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 536 | void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 537 | void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 538 | 539 | void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 540 | void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 541 | void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 542 | 543 | /* Interrupts and flags management functions **********************************/ 544 | void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 545 | FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 546 | void RCC_ClearFlag(void); 547 | ITStatus RCC_GetITStatus(uint8_t RCC_IT); 548 | void RCC_ClearITPendingBit(uint8_t RCC_IT); 549 | 550 | #ifdef __cplusplus 551 | } 552 | #endif 553 | 554 | #endif /* __STM32F0XX_RCC_H */ 555 | 556 | /** 557 | * @} 558 | */ 559 | 560 | /** 561 | * @} 562 | */ 563 | 564 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 565 | -------------------------------------------------------------------------------- /stm32_lib/inc/stm32f0xx_syscfg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_syscfg.h 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 01-August-2013 7 | * @brief This file contains all the functions prototypes for the SYSCFG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2013 STMicroelectronics

49 | * 50 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 51 | * You may not use this file except in compliance with the License. 52 | * You may obtain a copy of the License at: 53 | * 54 | * http://www.st.com/software_license_agreement_liberty_v2 55 | * 56 | * Unless required by applicable law or agreed to in writing, software 57 | * distributed under the License is distributed on an "AS IS" BASIS, 58 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 59 | * See the License for the specific language governing permissions and 60 | * limitations under the License. 61 | * 62 | ****************************************************************************** 63 | */ 64 | 65 | /* Includes ------------------------------------------------------------------*/ 66 | #include "stm32f0xx_exti.h" 67 | 68 | /** @addtogroup STM32F0xx_StdPeriph_Driver 69 | * @{ 70 | */ 71 | 72 | /** @defgroup EXTI 73 | * @brief EXTI driver modules 74 | * @{ 75 | */ 76 | 77 | /* Private typedef -----------------------------------------------------------*/ 78 | /* Private define ------------------------------------------------------------*/ 79 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 80 | 81 | /* Private macro -------------------------------------------------------------*/ 82 | /* Private variables ---------------------------------------------------------*/ 83 | /* Private function prototypes -----------------------------------------------*/ 84 | /* Private functions ---------------------------------------------------------*/ 85 | 86 | /** @defgroup EXTI_Private_Functions 87 | * @{ 88 | */ 89 | 90 | /** @defgroup EXTI_Group1 Initialization and Configuration functions 91 | * @brief Initialization and Configuration functions 92 | * 93 | @verbatim 94 | ============================================================================== 95 | ##### Initialization and Configuration functions ##### 96 | ============================================================================== 97 | 98 | @endverbatim 99 | * @{ 100 | */ 101 | 102 | /** 103 | * @brief Deinitializes the EXTI peripheral registers to their default reset 104 | * values. 105 | * @param None 106 | * @retval None 107 | */ 108 | void EXTI_DeInit(void) 109 | { 110 | EXTI->IMR = 0x0F940000; 111 | EXTI->EMR = 0x00000000; 112 | EXTI->RTSR = 0x00000000; 113 | EXTI->FTSR = 0x00000000; 114 | EXTI->PR = 0x006BFFFF; 115 | } 116 | 117 | /** 118 | * @brief Initializes the EXTI peripheral according to the specified 119 | * parameters in the EXTI_InitStruct. 120 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 121 | * contains the configuration information for the EXTI peripheral. 122 | * @retval None 123 | */ 124 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 125 | { 126 | uint32_t tmp = 0; 127 | 128 | /* Check the parameters */ 129 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 130 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 131 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 132 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 133 | 134 | tmp = (uint32_t)EXTI_BASE; 135 | 136 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 137 | { 138 | /* Clear EXTI line configuration */ 139 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 140 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 141 | 142 | tmp += EXTI_InitStruct->EXTI_Mode; 143 | 144 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 145 | 146 | /* Clear Rising Falling edge configuration */ 147 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 148 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 149 | 150 | /* Select the trigger for the selected interrupts */ 151 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 152 | { 153 | /* Rising Falling edge */ 154 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 155 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 156 | } 157 | else 158 | { 159 | tmp = (uint32_t)EXTI_BASE; 160 | tmp += EXTI_InitStruct->EXTI_Trigger; 161 | 162 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 163 | } 164 | } 165 | else 166 | { 167 | tmp += EXTI_InitStruct->EXTI_Mode; 168 | 169 | /* Disable the selected external lines */ 170 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 171 | } 172 | } 173 | 174 | /** 175 | * @brief Fills each EXTI_InitStruct member with its reset value. 176 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 177 | * be initialized. 178 | * @retval None 179 | */ 180 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 181 | { 182 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 183 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 184 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 185 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 186 | } 187 | 188 | /** 189 | * @brief Generates a Software interrupt on selected EXTI line. 190 | * @param EXTI_Line: specifies the EXTI line on which the software interrupt 191 | * will be generated. 192 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 193 | * @retval None 194 | */ 195 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 196 | { 197 | /* Check the parameters */ 198 | assert_param(IS_EXTI_LINE(EXTI_Line)); 199 | 200 | EXTI->SWIER |= EXTI_Line; 201 | } 202 | 203 | /** 204 | * @} 205 | */ 206 | 207 | /** @defgroup EXTI_Group2 Interrupts and flags management functions 208 | * @brief Interrupts and flags management functions 209 | * 210 | @verbatim 211 | ============================================================================== 212 | ##### Interrupts and flags management functions ##### 213 | ============================================================================== 214 | 215 | @endverbatim 216 | * @{ 217 | */ 218 | 219 | /** 220 | * @brief Checks whether the specified EXTI line flag is set or not. 221 | * @param EXTI_Line: specifies the EXTI line flag to check. 222 | * This parameter can be EXTI_Linex where x can be (0..27). 223 | * @retval The new state of EXTI_Line (SET or RESET). 224 | */ 225 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 226 | { 227 | FlagStatus bitstatus = RESET; 228 | /* Check the parameters */ 229 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 230 | 231 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 232 | { 233 | bitstatus = SET; 234 | } 235 | else 236 | { 237 | bitstatus = RESET; 238 | } 239 | return bitstatus; 240 | } 241 | 242 | /** 243 | * @brief Clears the EXTI's line pending flags. 244 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 245 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 246 | * @retval None 247 | */ 248 | void EXTI_ClearFlag(uint32_t EXTI_Line) 249 | { 250 | /* Check the parameters */ 251 | assert_param(IS_EXTI_LINE(EXTI_Line)); 252 | 253 | EXTI->PR = EXTI_Line; 254 | } 255 | 256 | /** 257 | * @brief Checks whether the specified EXTI line is asserted or not. 258 | * @param EXTI_Line: specifies the EXTI line to check. 259 | * This parameter can be EXTI_Linex where x can be (0..27). 260 | * @retval The new state of EXTI_Line (SET or RESET). 261 | */ 262 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 263 | { 264 | ITStatus bitstatus = RESET; 265 | /* Check the parameters */ 266 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 267 | 268 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 269 | { 270 | bitstatus = SET; 271 | } 272 | else 273 | { 274 | bitstatus = RESET; 275 | } 276 | return bitstatus; 277 | 278 | } 279 | 280 | /** 281 | * @brief Clears the EXTI's line pending bits. 282 | * @param EXTI_Line: specifies the EXTI lines to clear. 283 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 284 | * @retval None 285 | */ 286 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 287 | { 288 | /* Check the parameters */ 289 | assert_param(IS_EXTI_LINE(EXTI_Line)); 290 | 291 | EXTI->PR = EXTI_Line; 292 | } 293 | 294 | /** 295 | * @} 296 | */ 297 | 298 | /** 299 | * @} 300 | */ 301 | 302 | /** 303 | * @} 304 | */ 305 | 306 | /** 307 | * @} 308 | */ 309 | 310 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 311 | -------------------------------------------------------------------------------- /stm32_lib/src/stm32f0xx_gpio.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_gpio.c 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 01-August-2013 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the GPIO peripheral: 9 | * + Initialization and Configuration functions 10 | * + GPIO Read and Write functions 11 | * + GPIO Alternate functions configuration functions 12 | * 13 | * @verbatim 14 | * 15 | * 16 | =========================================================================== 17 | ##### How to use this driver ##### 18 | =========================================================================== 19 | [..] 20 | (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd() 21 | (#) Configure the GPIO pin(s) using GPIO_Init() 22 | Four possible configuration are available for each pin: 23 | (++) Input: Floating, Pull-up, Pull-down. 24 | (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) 25 | Open Drain (Pull-up, Pull-down or no Pull). 26 | In output mode, the speed is configurable: Low, Medium, Fast or High. 27 | (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) 28 | Open Drain (Pull-up, Pull-down or no Pull). 29 | (++) Analog: required mode when a pin is to be used as ADC channel, 30 | DAC output or comparator input. 31 | (#) Peripherals alternate function: 32 | (++) For ADC, DAC and comparators, configure the desired pin in analog 33 | mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN 34 | (++) For other peripherals (TIM, USART...): 35 | (+++) Connect the pin to the desired peripherals' Alternate 36 | Function (AF) using GPIO_PinAFConfig() function. For PortC, 37 | PortD and PortF, no configuration is needed. 38 | (+++) Configure the desired pin in alternate function mode using 39 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF 40 | (+++) Select the type, pull-up/pull-down and output speed via 41 | GPIO_PuPd, GPIO_OType and GPIO_Speed members 42 | (+++) Call GPIO_Init() function 43 | (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() 44 | (#) To set/reset the level of a pin configured in output mode use 45 | GPIO_SetBits()/GPIO_ResetBits() 46 | (#) During and just after reset, the alternate functions are not active and 47 | the GPIO pins are configured in input floating mode (except JTAG pins). 48 | (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 49 | general-purpose (PC14 and PC15, respectively) when the LSE oscillator 50 | is off. The LSE has priority over the GPIO function. 51 | (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose 52 | PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has 53 | priority over the GPIO function. 54 | @endverbatim 55 | ****************************************************************************** 56 | * @attention 57 | * 58 | *

59 | * 60 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 61 | * You may not use this file except in compliance with the License. 62 | * You may obtain a copy of the License at: 63 | * 64 | * http://www.st.com/software_license_agreement_liberty_v2 65 | * 66 | * Unless required by applicable law or agreed to in writing, software 67 | * distributed under the License is distributed on an "AS IS" BASIS, 68 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 69 | * See the License for the specific language governing permissions and 70 | * limitations under the License. 71 | * 72 | ****************************************************************************** 73 | */ 74 | 75 | /* Includes ------------------------------------------------------------------*/ 76 | #include "stm32f0xx_gpio.h" 77 | #include "stm32f0xx_rcc.h" 78 | 79 | /** @addtogroup STM32F0xx_StdPeriph_Driver 80 | * @{ 81 | */ 82 | 83 | /** @defgroup GPIO 84 | * @brief GPIO driver modules 85 | * @{ 86 | */ 87 | 88 | /* Private typedef -----------------------------------------------------------*/ 89 | /* Private define ------------------------------------------------------------*/ 90 | /* Private macro -------------------------------------------------------------*/ 91 | /* Private variables ---------------------------------------------------------*/ 92 | /* Private function prototypes -----------------------------------------------*/ 93 | /* Private functions ---------------------------------------------------------*/ 94 | 95 | /** @defgroup GPIO_Private_Functions 96 | * @{ 97 | */ 98 | 99 | /** @defgroup GPIO_Group1 Initialization and Configuration 100 | * @brief Initialization and Configuration 101 | * 102 | @verbatim 103 | =============================================================================== 104 | ##### Initialization and Configuration ##### 105 | =============================================================================== 106 | 107 | @endverbatim 108 | * @{ 109 | */ 110 | 111 | /** 112 | * @brief Deinitializes the GPIOx peripheral registers to their default reset 113 | * values. 114 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 115 | * @retval None 116 | */ 117 | void GPIO_DeInit(GPIO_TypeDef* GPIOx) 118 | { 119 | /* Check the parameters */ 120 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 121 | 122 | if(GPIOx == GPIOA) 123 | { 124 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE); 125 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE); 126 | } 127 | else if(GPIOx == GPIOB) 128 | { 129 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE); 130 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE); 131 | } 132 | else if(GPIOx == GPIOC) 133 | { 134 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE); 135 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE); 136 | } 137 | else if(GPIOx == GPIOD) 138 | { 139 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE); 140 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE); 141 | } 142 | else 143 | { 144 | if(GPIOx == GPIOF) 145 | { 146 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE); 147 | RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE); 148 | } 149 | } 150 | } 151 | 152 | /** 153 | * @brief Initializes the GPIOx peripheral according to the specified 154 | * parameters in the GPIO_InitStruct. 155 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 156 | * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains 157 | * the configuration information for the specified GPIO peripheral. 158 | * @note The configured pins can be: GPIO_Pin_0 to GPIO_Pin_15 for GPIOA, GPIOB and GPIOC, 159 | * GPIO_Pin_0 to GPIO_Pin_2 for GPIOD, GPIO_Pin_0 to GPIO_Pin_3 for GPIOF. 160 | * @retval None 161 | */ 162 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) 163 | { 164 | uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; 165 | 166 | /* Check the parameters */ 167 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 168 | assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); 169 | assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); 170 | assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); 171 | 172 | /*-------------------------- Configure the port pins -----------------------*/ 173 | /*-- GPIO Mode Configuration --*/ 174 | for (pinpos = 0x00; pinpos < 0x10; pinpos++) 175 | { 176 | pos = ((uint32_t)0x01) << pinpos; 177 | 178 | /* Get the port pins position */ 179 | currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 180 | 181 | if (currentpin == pos) 182 | { 183 | if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) 184 | { 185 | /* Check Speed mode parameters */ 186 | assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); 187 | 188 | /* Speed mode configuration */ 189 | GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); 190 | GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); 191 | 192 | /* Check Output mode parameters */ 193 | assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); 194 | 195 | /* Output mode configuration */ 196 | GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)); 197 | GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); 198 | } 199 | 200 | GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); 201 | 202 | GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); 203 | 204 | /* Pull-up Pull down resistor configuration */ 205 | GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); 206 | GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); 207 | } 208 | } 209 | } 210 | 211 | /** 212 | * @brief Fills each GPIO_InitStruct member with its default value. 213 | * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will 214 | * be initialized. 215 | * @retval None 216 | */ 217 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) 218 | { 219 | /* Reset GPIO init structure parameters values */ 220 | GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; 221 | GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; 222 | GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2; 223 | GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; 224 | GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; 225 | } 226 | 227 | /** 228 | * @brief Locks GPIO Pins configuration registers. 229 | * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, 230 | * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. 231 | * @note The configuration of the locked GPIO pins can no longer be modified 232 | * until the next device reset. 233 | * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. 234 | * @param GPIO_Pin: specifies the port bit to be written. 235 | * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). 236 | * @retval None 237 | */ 238 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) 239 | { 240 | __IO uint32_t tmp = 0x00010000; 241 | 242 | /* Check the parameters */ 243 | assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); 244 | assert_param(IS_GPIO_PIN(GPIO_Pin)); 245 | 246 | tmp |= GPIO_Pin; 247 | /* Set LCKK bit */ 248 | GPIOx->LCKR = tmp; 249 | /* Reset LCKK bit */ 250 | GPIOx->LCKR = GPIO_Pin; 251 | /* Set LCKK bit */ 252 | GPIOx->LCKR = tmp; 253 | /* Read LCKK bit */ 254 | tmp = GPIOx->LCKR; 255 | /* Read LCKK bit */ 256 | tmp = GPIOx->LCKR; 257 | } 258 | 259 | /** 260 | * @} 261 | */ 262 | 263 | /** @defgroup GPIO_Group2 GPIO Read and Write 264 | * @brief GPIO Read and Write 265 | * 266 | @verbatim 267 | =============================================================================== 268 | ##### GPIO Read and Write ##### 269 | =============================================================================== 270 | 271 | @endverbatim 272 | * @{ 273 | */ 274 | 275 | /** 276 | * @brief Reads the specified input port pin. 277 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 278 | * @param GPIO_Pin: specifies the port bit to read. 279 | * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 280 | * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. 281 | * @retval The input port pin value. 282 | */ 283 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) 284 | { 285 | uint8_t bitstatus = 0x00; 286 | 287 | /* Check the parameters */ 288 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 289 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 290 | 291 | if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) 292 | { 293 | bitstatus = (uint8_t)Bit_SET; 294 | } 295 | else 296 | { 297 | bitstatus = (uint8_t)Bit_RESET; 298 | } 299 | return bitstatus; 300 | } 301 | 302 | /** 303 | * @brief Reads the specified input port pin. 304 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 305 | * @retval The input port pin value. 306 | */ 307 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) 308 | { 309 | /* Check the parameters */ 310 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 311 | 312 | return ((uint16_t)GPIOx->IDR); 313 | } 314 | 315 | /** 316 | * @brief Reads the specified output data port bit. 317 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 318 | * @param GPIO_Pin: Specifies the port bit to read. 319 | * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 320 | * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. 321 | * @retval The output port pin value. 322 | */ 323 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) 324 | { 325 | uint8_t bitstatus = 0x00; 326 | 327 | /* Check the parameters */ 328 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 329 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 330 | 331 | if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) 332 | { 333 | bitstatus = (uint8_t)Bit_SET; 334 | } 335 | else 336 | { 337 | bitstatus = (uint8_t)Bit_RESET; 338 | } 339 | return bitstatus; 340 | } 341 | 342 | /** 343 | * @brief Reads the specified GPIO output data port. 344 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 345 | * @retval GPIO output data port value. 346 | */ 347 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) 348 | { 349 | /* Check the parameters */ 350 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 351 | 352 | return ((uint16_t)GPIOx->ODR); 353 | } 354 | 355 | /** 356 | * @brief Sets the selected data port bits. 357 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 358 | * @param GPIO_Pin: specifies the port bits to be written. 359 | * @note This parameter can be GPIO_Pin_x where x can be:(0..15) for GPIOA, 360 | * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. 361 | * @retval None 362 | */ 363 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) 364 | { 365 | /* Check the parameters */ 366 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 367 | assert_param(IS_GPIO_PIN(GPIO_Pin)); 368 | 369 | GPIOx->BSRR = GPIO_Pin; 370 | } 371 | 372 | /** 373 | * @brief Clears the selected data port bits. 374 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 375 | * @param GPIO_Pin: specifies the port bits to be written. 376 | * @note This parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, 377 | * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. 378 | * @retval None 379 | */ 380 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) 381 | { 382 | /* Check the parameters */ 383 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 384 | assert_param(IS_GPIO_PIN(GPIO_Pin)); 385 | 386 | GPIOx->BRR = GPIO_Pin; 387 | } 388 | 389 | /** 390 | * @brief Sets or clears the selected data port bit. 391 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 392 | * @param GPIO_Pin: specifies the port bit to be written. 393 | * @param BitVal: specifies the value to be written to the selected bit. 394 | * This parameter can be one of the BitAction enumeration values: 395 | * @arg Bit_RESET: to clear the port pin 396 | * @arg Bit_SET: to set the port pin 397 | * @note The GPIO_Pin parameter can be GPIO_Pin_x where x can be: (0..15) for GPIOA, 398 | * GPIOB or GPIOC,(0..2) for GPIOD and(0..3) for GPIOF. 399 | * @retval None 400 | */ 401 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) 402 | { 403 | /* Check the parameters */ 404 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 405 | assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); 406 | assert_param(IS_GPIO_BIT_ACTION(BitVal)); 407 | 408 | if (BitVal != Bit_RESET) 409 | { 410 | GPIOx->BSRR = GPIO_Pin; 411 | } 412 | else 413 | { 414 | GPIOx->BRR = GPIO_Pin ; 415 | } 416 | } 417 | 418 | /** 419 | * @brief Writes data to the specified GPIO data port. 420 | * @param GPIOx: where x can be (A, B, C, D or F) to select the GPIO peripheral. 421 | * @param PortVal: specifies the value to be written to the port output data register. 422 | * @retval None 423 | */ 424 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) 425 | { 426 | /* Check the parameters */ 427 | assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); 428 | 429 | GPIOx->ODR = PortVal; 430 | } 431 | 432 | /** 433 | * @} 434 | */ 435 | 436 | /** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions 437 | * @brief GPIO Alternate functions configuration functions 438 | * 439 | @verbatim 440 | =============================================================================== 441 | ##### GPIO Alternate functions configuration functions ##### 442 | =============================================================================== 443 | 444 | @endverbatim 445 | * @{ 446 | */ 447 | 448 | /** 449 | * @brief Writes data to the specified GPIO data port. 450 | * @param GPIOx: where x can be (A or B) to select the GPIO peripheral. 451 | * @param GPIO_PinSource: specifies the pin for the Alternate function. 452 | * This parameter can be GPIO_PinSourcex where x can be (0..15). 453 | * @param GPIO_AF: selects the pin to used as Alternate function. 454 | * This parameter can be one of the following value: 455 | * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17,MCO, SWDAT, SWCLK, TIM14, 456 | * USART1, CEC, IR_OUT, SPI2 457 | * @arg GPIO_AF_1: USART2, CEC, Tim3, USART1, IR_OUT,EVENTOUT, I2C1, I2C2, TIM15 458 | * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17 459 | * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT 460 | * @arg GPIO_AF_4: TIM14, I2C1 (only for STM32F0XX_LD and STM32F030X6 devices) 461 | * @arg GPIO_AF_5: TIM16, TIM17 462 | * @arg GPIO_AF_6: EVENTOUT 463 | * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT 464 | * @note The pin should already been configured in Alternate Function mode(AF) 465 | * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF 466 | * @note Refer to the Alternate function mapping table in the device datasheet 467 | * for the detailed mapping of the system and peripherals'alternate 468 | * function I/O pins. 469 | * @retval None 470 | */ 471 | void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) 472 | { 473 | uint32_t temp = 0x00; 474 | uint32_t temp_2 = 0x00; 475 | 476 | /* Check the parameters */ 477 | assert_param(IS_GPIO_LIST_PERIPH(GPIOx)); 478 | assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); 479 | assert_param(IS_GPIO_AF(GPIO_AF)); 480 | 481 | temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); 482 | GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); 483 | temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; 484 | GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; 485 | } 486 | 487 | /** 488 | * @} 489 | */ 490 | 491 | /** 492 | * @} 493 | */ 494 | 495 | /** 496 | * @} 497 | */ 498 | 499 | /** 500 | * @} 501 | */ 502 | 503 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 504 | -------------------------------------------------------------------------------- /stm32_lib/src/stm32f0xx_misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_misc.c 4 | * @author MCD Application Team 5 | * @version V1.2.0 6 | * @date 01-August-2013 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

31 | * 32 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 33 | * You may not use this file except in compliance with the License. 34 | * You may obtain a copy of the License at: 35 | * 36 | * http://www.st.com/software_license_agreement_liberty_v2 37 | * 38 | * Unless required by applicable law or agreed to in writing, software 39 | * distributed under the License is distributed on an "AS IS" BASIS, 40 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 41 | * See the License for the specific language governing permissions and 42 | * limitations under the License. 43 | * 44 | ****************************************************************************** 45 | */ 46 | 47 | /* Includes ------------------------------------------------------------------*/ 48 | #include "stm32f0xx_syscfg.h" 49 | 50 | /** @addtogroup STM32F0xx_StdPeriph_Driver 51 | * @{ 52 | */ 53 | 54 | /** @defgroup SYSCFG 55 | * @brief SYSCFG driver modules 56 | * @{ 57 | */ 58 | 59 | /* Private typedef -----------------------------------------------------------*/ 60 | /* Private define ------------------------------------------------------------*/ 61 | /* Private macro -------------------------------------------------------------*/ 62 | /* Private variables ---------------------------------------------------------*/ 63 | /* Private function prototypes -----------------------------------------------*/ 64 | /* Private functions ---------------------------------------------------------*/ 65 | 66 | /** @defgroup SYSCFG_Private_Functions 67 | * @{ 68 | */ 69 | 70 | /** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions 71 | * @brief SYSCFG Initialization and Configuration functions 72 | * 73 | @verbatim 74 | =============================================================================== 75 | ##### SYSCFG Initialization and Configuration functions ##### 76 | =============================================================================== 77 | 78 | @endverbatim 79 | * @{ 80 | */ 81 | 82 | /** 83 | * @brief Deinitializes the SYSCFG registers to their default reset values. 84 | * @param None 85 | * @retval None 86 | * @note MEM_MODE bits are not affected by APB reset. 87 | * @note MEM_MODE bits took the value from the user option bytes. 88 | * @note CFGR2 register is not affected by APB reset. 89 | * @note CLABBB configuration bits are locked when set. 90 | * @note To unlock the configuration, perform a system reset. 91 | */ 92 | void SYSCFG_DeInit(void) 93 | { 94 | /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */ 95 | SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE; 96 | /* Set EXTICRx registers to reset value */ 97 | SYSCFG->EXTICR[0] = 0; 98 | SYSCFG->EXTICR[1] = 0; 99 | SYSCFG->EXTICR[2] = 0; 100 | SYSCFG->EXTICR[3] = 0; 101 | /* Set CFGR2 register to reset value: clear SRAM parity error flag */ 102 | SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE; 103 | } 104 | 105 | /** 106 | * @brief Configures the memory mapping at address 0x00000000. 107 | * @param SYSCFG_MemoryRemap: selects the memory remapping. 108 | * This parameter can be one of the following values: 109 | * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 110 | * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 111 | * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 112 | * @retval None 113 | */ 114 | void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) 115 | { 116 | uint32_t tmpctrl = 0; 117 | 118 | /* Check the parameter */ 119 | assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); 120 | 121 | /* Get CFGR1 register value */ 122 | tmpctrl = SYSCFG->CFGR1; 123 | 124 | /* Clear MEM_MODE bits */ 125 | tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE); 126 | 127 | /* Set the new MEM_MODE bits value */ 128 | tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; 129 | 130 | /* Set CFGR1 register with the new memory remap configuration */ 131 | SYSCFG->CFGR1 = tmpctrl; 132 | } 133 | 134 | /** 135 | * @brief Configure the DMA channels remapping. 136 | * @param SYSCFG_DMARemap: selects the DMA channels remap. 137 | * This parameter can be one of the following values: 138 | * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2 139 | * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4 140 | * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5 141 | * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4 142 | * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2 143 | * @param NewState: new state of the DMA channel remapping. 144 | * This parameter can be: ENABLE or DISABLE. 145 | * @note When enabled, DMA channel of the selected peripheral is remapped 146 | * @note When disabled, Default DMA channel is mapped to the selected peripheral 147 | * @note By default TIM17 DMA requests is mapped to channel 1, 148 | * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap 149 | * TIM17 DMA requests to channel 2 and use 150 | * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map 151 | * TIM17 DMA requests to channel 1 (default mapping) 152 | * @retval None 153 | */ 154 | void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState) 155 | { 156 | /* Check the parameters */ 157 | assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap)); 158 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 159 | 160 | if (NewState != DISABLE) 161 | { 162 | /* Remap the DMA channel */ 163 | SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap; 164 | } 165 | else 166 | { 167 | /* use the default DMA channel mapping */ 168 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap); 169 | } 170 | } 171 | 172 | /** 173 | * @brief Configure the I2C fast mode plus driving capability. 174 | * @param SYSCFG_I2CFastModePlus: selects the pin. 175 | * This parameter can be one of the following values: 176 | * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 177 | * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 178 | * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 179 | * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 180 | * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F0XX_LD and STM32F030X6 devices) 181 | * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F0XX_LD and STM32F030X6 devices) 182 | * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32F030X6 devices) 183 | * @param NewState: new state of the DMA channel remapping. 184 | * This parameter can be: ENABLE or DISABLE. 185 | * @note ENABLE: Enable fast mode plus driving capability for selected pin 186 | * @note DISABLE: Disable fast mode plus driving capability for selected pin 187 | * @retval None 188 | */ 189 | void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) 190 | { 191 | /* Check the parameters */ 192 | assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); 193 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 194 | 195 | if (NewState != DISABLE) 196 | { 197 | /* Enable fast mode plus driving capability for selected pin */ 198 | SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus; 199 | } 200 | else 201 | { 202 | /* Disable fast mode plus driving capability for selected pin */ 203 | SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus); 204 | } 205 | } 206 | 207 | /** 208 | * @brief Selects the GPIO pin used as EXTI Line. 209 | * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source 210 | * for EXTI lines where x can be (A, B, C, D or F). 211 | * @param EXTI_PinSourcex: specifies the EXTI line to be configured. 212 | * This parameter can be EXTI_PinSourcex where x can be (0..15) 213 | * @retval None 214 | */ 215 | void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) 216 | { 217 | uint32_t tmp = 0x00; 218 | 219 | /* Check the parameters */ 220 | assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); 221 | assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); 222 | 223 | tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); 224 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; 225 | SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); 226 | } 227 | 228 | /** 229 | * @brief Connect the selected parameter to the break input of TIM1. 230 | * @note The selected configuration is locked and can be unlocked by system reset 231 | * @param SYSCFG_Break: selects the configuration to be connected to break 232 | * input of TIM1 233 | * This parameter can be any combination of the following values: 234 | * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1. 235 | * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 . 236 | * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1. 237 | * @retval None 238 | */ 239 | void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) 240 | { 241 | /* Check the parameter */ 242 | assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); 243 | 244 | SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; 245 | } 246 | 247 | /** 248 | * @brief Checks whether the specified SYSCFG flag is set or not. 249 | * @param SYSCFG_Flag: specifies the SYSCFG flag to check. 250 | * This parameter can be one of the following values: 251 | * @arg SYSCFG_FLAG_PE: SRAM parity error flag. 252 | * @retval The new state of SYSCFG_Flag (SET or RESET). 253 | */ 254 | FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag) 255 | { 256 | FlagStatus bitstatus = RESET; 257 | 258 | /* Check the parameter */ 259 | assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); 260 | 261 | /* Check the status of the specified SPI flag */ 262 | if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET) 263 | { 264 | /* SYSCFG_Flag is set */ 265 | bitstatus = SET; 266 | } 267 | else 268 | { 269 | /* SYSCFG_Flag is reset */ 270 | bitstatus = RESET; 271 | } 272 | /* Return the SYSCFG_Flag status */ 273 | return bitstatus; 274 | } 275 | 276 | /** 277 | * @brief Clear the selected SYSCFG flag. 278 | * @param SYSCFG_Flag: selects the flag to be cleared. 279 | * This parameter can be any combination of the following values: 280 | * @arg SYSCFG_FLAG_PE: SRAM parity error flag. 281 | * @retval None 282 | */ 283 | void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag) 284 | { 285 | /* Check the parameter */ 286 | assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag)); 287 | 288 | SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag; 289 | } 290 | 291 | /** 292 | * @} 293 | */ 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 307 | -------------------------------------------------------------------------------- /stm32f0_ws2812b_dmx512.comarker: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /stm32f0_ws2812b_dmx512.coproj: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 21 | 22 | 50 | 51 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | -------------------------------------------------------------------------------- /ws2812b.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "stm32f0xx_dma.h" 4 | #include "stm32f0xx_gpio.h" 5 | #include "stm32f0xx_misc.h" 6 | #include "stm32f0xx_rcc.h" 7 | #include "stm32f0xx_tim.h" 8 | 9 | #include "ws2812b.h" 10 | 11 | static const uint8_t WS2812B_BUFFER_SIZE = 240; 12 | static const uint8_t WS2812B_DEAD_PERIOD = 1; 13 | 14 | __O uint8_t WS2812B_IO_High = 0xFF; 15 | __O uint8_t WS2812B_IO_Low = 0x00; 16 | 17 | __IO uint8_t WS2812B_IO_FrameData[240]; 18 | 19 | __IO uint8_t WS2812B_TC = 1; 20 | __IO uint8_t WS2812B_TIM_Overflows = 0; 21 | 22 | void WS2812B_Init_GPIO(void) 23 | { 24 | GPIO_InitTypeDef GPIO_InitStructure; 25 | 26 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); 27 | 28 | GPIO_InitStructure.GPIO_Pin = 0xFF; /* Pins 0-7 */ 29 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 30 | GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 31 | GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; 32 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 33 | 34 | GPIO_Init(GPIOA, &GPIO_InitStructure); 35 | } 36 | 37 | void WS2812B_Init_Timer(void) 38 | { 39 | TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; 40 | TIM_OCInitTypeDef TIM_OCInitStructure; 41 | NVIC_InitTypeDef NVIC_InitStructure; 42 | 43 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); 44 | 45 | TIM_TimeBaseStructure.TIM_ClockDivision = 0; 46 | TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; 47 | TIM_TimeBaseStructure.TIM_Prescaler = 0; 48 | TIM_TimeBaseStructure.TIM_Period = 10; 49 | TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; 50 | 51 | TIM_TimeBaseInit(TIM3, &TIM_TimeBaseStructure); 52 | TIM_ARRPreloadConfig(TIM3, DISABLE); 53 | 54 | TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_Timing; 55 | TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Disable; 56 | TIM_OCInitStructure.TIM_Pulse = 2; 57 | TIM_OC1Init(TIM3, &TIM_OCInitStructure); 58 | TIM_OC1PreloadConfig(TIM3, TIM_OCPreload_Disable); 59 | 60 | TIM_OCInitStructure.TIM_Pulse = 4; 61 | TIM_OC3Init(TIM3, &TIM_OCInitStructure); 62 | TIM_OC3PreloadConfig(TIM3, TIM_OCPreload_Disable); 63 | 64 | NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn; 65 | NVIC_InitStructure.NVIC_IRQChannelPriority = 1; 66 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 67 | NVIC_Init(&NVIC_InitStructure); 68 | } 69 | 70 | void WS2812B_Init_DMA(void) 71 | { 72 | DMA_InitTypeDef DMA_InitStructure; 73 | NVIC_InitTypeDef NVIC_InitStructure; 74 | 75 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); 76 | 77 | // TIM3 update event, DMA1 Channel 3 78 | DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&GPIOA->ODR; 79 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&WS2812B_IO_High; 80 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; 81 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; 82 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 83 | DMA_InitStructure.DMA_BufferSize = 0; // ??? 84 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 85 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; 86 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; 87 | DMA_InitStructure.DMA_Priority = DMA_Priority_High; 88 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 89 | DMA_Init(DMA1_Channel3, &DMA_InitStructure); 90 | 91 | // TIM3 CC1 event, DMA1 Channel 4 92 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)WS2812B_IO_FrameData; //WS2812B_IO_FrameData[0]; 93 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 94 | DMA_Init(DMA1_Channel4, &DMA_InitStructure); 95 | 96 | // TIM3 CC3 event, DMA1 Channel 2 97 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)&WS2812B_IO_Low; 98 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable; 99 | DMA_Init(DMA1_Channel2, &DMA_InitStructure); 100 | 101 | // DMA1 Channel 2 interrupt 102 | NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel2_3_IRQn; 103 | NVIC_InitStructure.NVIC_IRQChannelPriority = 0; 104 | NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 105 | NVIC_Init(&NVIC_InitStructure); 106 | 107 | DMA_ITConfig(DMA1_Channel2, DMA_IT_TC, ENABLE); 108 | } 109 | 110 | void WS2812B_Send_Buffer(void) 111 | { 112 | WS2812B_TC = 0; 113 | 114 | DMA_ClearFlag(DMA1_FLAG_TC2 | DMA1_FLAG_HT2 | DMA1_FLAG_GL2 | DMA1_FLAG_TE2); 115 | DMA_ClearFlag(DMA1_FLAG_TC3 | DMA1_FLAG_HT3 | DMA1_FLAG_GL3 | DMA1_FLAG_TE3); 116 | DMA_ClearFlag(DMA1_FLAG_TC4 | DMA1_FLAG_HT4 | DMA1_FLAG_GL4 | DMA1_FLAG_TE4); 117 | 118 | DMA_SetCurrDataCounter(DMA1_Channel2, WS2812B_BUFFER_SIZE); 119 | DMA_SetCurrDataCounter(DMA1_Channel3, WS2812B_BUFFER_SIZE); 120 | DMA_SetCurrDataCounter(DMA1_Channel4, WS2812B_BUFFER_SIZE); 121 | 122 | TIM3->SR = 0; 123 | 124 | DMA_Cmd(DMA1_Channel2, ENABLE); 125 | DMA_Cmd(DMA1_Channel3, ENABLE); 126 | DMA_Cmd(DMA1_Channel4, ENABLE); 127 | 128 | TIM_DMACmd(TIM3, TIM_DMA_CC1, ENABLE); 129 | TIM_DMACmd(TIM3, TIM_DMA_CC3, ENABLE); 130 | TIM_DMACmd(TIM3, TIM_DMA_Update, ENABLE); 131 | 132 | TIM_SetCounter(TIM3, 10); 133 | 134 | TIM_Cmd(TIM3, ENABLE); 135 | } 136 | 137 | uint8_t WS2812B_Get_TC(void) 138 | { 139 | return WS2812B_TC; 140 | } 141 | 142 | void WS2812B_Set_Pixel(uint8_t bank, uint8_t pixel, uint8_t red, uint8_t green, uint8_t blue) 143 | { 144 | uint8_t i; 145 | 146 | for (i = 0; i < 8; i++) { 147 | // Clear data 148 | WS2812B_IO_FrameData[pixel * 24 + i] &= ~(0x01 << bank); 149 | WS2812B_IO_FrameData[pixel * 24 + 8 + i] &= ~(0x01 << bank); 150 | WS2812B_IO_FrameData[pixel * 24 + 16 + i] &= ~(0x01 << bank); 151 | 152 | // Write new data 153 | WS2812B_IO_FrameData[pixel * 24 + i] |= ((((green<>7)<>7)<>7)< 5 | * Copyright (c) 2014 Elia Ritterbusch, http://eliaselectronics.com 6 | * 7 | * Permission is hereby granted, free of charge, to any person obtaining a copy 8 | * of this software and associated documentation files (the "Software"), to deal 9 | * in the Software without restriction, including without limitation the rights 10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | * copies of the Software, and to permit persons to whom the Software is 12 | * furnished to do so, subject to the following conditions: 13 | 14 | * The above copyright notice and this permission notice shall be included in 15 | * all copies or substantial portions of the Software. 16 | 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 | * THE SOFTWARE. 24 | */ 25 | 26 | #ifndef __WS2812B_H 27 | #define __WS2812B_H 28 | 29 | #include 30 | 31 | void WS2812B_Init_GPIO(void); 32 | void WS2812B_Init_Timer(void); 33 | void WS2812B_Init_DMA(void); 34 | 35 | void WS2812B_Send_Buffer(void); 36 | uint8_t WS2812B_Get_TC(void); 37 | void WS2812B_Set_Pixel(uint8_t bank, uint8_t pixel, uint8_t red, uint8_t green, uint8_t blue); 38 | 39 | 40 | void DMA1_Channel2_3_IRQHandler(void); 41 | void TIM3_IRQHandler(void); 42 | 43 | #endif /* __WS2812B_H */ 44 | --------------------------------------------------------------------------------