├── Hardware Description Language (HDL) Implementation ├── About ├── Before_Sig.mem ├── EE4218_MLP_Neural_Network_HDL.xpr ├── EE4218_MLP_Neural_Network_HDL_New.zip ├── EE4218_Project_MLP_HDL_New_10Apr.xsa ├── Sigmoid.v ├── X.mem ├── labels.mem ├── matrix_multiply.v ├── memory_RAM_new_file.v ├── myip_v1_0_new_file.v ├── tb_myip_v1_0_file.v ├── test_input.mem ├── test_input_new.mem ├── test_result_expected.mem ├── test_result_expected_new.mem ├── testbench_HDL.c ├── w_hid.mem └── w_out.mem ├── High Level Synthesis (HLS) Implementation ├── About ├── EE4218_MLP_Neural_Network.xpr ├── EE4218_MLP_Neural_Network_HLS_New.zip ├── EE4218_MLP_Project_HLS_Bitstream_10Apr.xsa ├── EE4218_MLP_Project_HLS_Optimized_10Apr.xsa ├── EE4218_MLP_Project_HLS_Version_Anurag_Johannes.xsa ├── mlp_hls.cpp ├── test_mlp_hls.cpp └── testbench.c ├── README.md ├── Software Implementation ├── About └── helloworld.c └── Test Inputs ├── About ├── X.txt ├── sigmoid.txt ├── w_hid.txt └── w_out.txt /Hardware Description Language (HDL) Implementation/About: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/Before_Sig.mem: -------------------------------------------------------------------------------- 1 | 2f 2 | 7d 3 | 70 4 | 64 5 | 50 6 | 4d 7 | 6f 8 | 74 9 | 73 10 | 59 11 | 4b 12 | 48 13 | 7e 14 | 70 15 | 72 16 | 53 17 | 82 18 | 51 19 | 6b 20 | 44 21 | 54 22 | 5b 23 | 73 24 | 46 25 | 69 26 | 61 27 | 72 28 | 6e 29 | 4b 30 | 44 31 | 46 32 | 51 33 | 48 34 | 45 35 | 69 36 | 67 37 | 51 38 | 7a 39 | 47 40 | 76 41 | 46 42 | 8b 43 | 42 44 | 47 45 | 52 46 | 7b 47 | 88 48 | 61 49 | 71 50 | 50 51 | 42 52 | 63 53 | 67 54 | 45 55 | 6c 56 | 45 57 | 3f 58 | 7b 59 | 51 60 | 4a 61 | 72 62 | 54 63 | 60 64 | 4b 65 | 14 66 | 51 67 | 54 68 | 43 69 | 38 70 | 40 71 | 54 72 | 5b 73 | 4c 74 | 3e 75 | 36 76 | 34 77 | 5e 78 | 55 79 | 54 80 | 3f 81 | 5f 82 | 39 83 | 52 84 | 36 85 | 3e 86 | 40 87 | 54 88 | 29 89 | 4f 90 | 4c 91 | 59 92 | 4c 93 | 35 94 | 28 95 | 35 96 | 37 97 | 3a 98 | 2e 99 | 4a 100 | 51 101 | 35 102 | 57 103 | 2e 104 | 5b 105 | 2d 106 | 6f 107 | 33 108 | 30 109 | 41 110 | 5a 111 | 66 112 | 4a 113 | 55 114 | 35 115 | 28 116 | 4e 117 | 4b 118 | 34 119 | 55 120 | 2d 121 | 27 122 | 5d 123 | 32 124 | 3a 125 | 58 126 | 31 127 | 44 128 | 3d 129 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/EE4218_MLP_Neural_Network_HDL.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 111 | 112 | 113 | 114 | 115 | 117 | 118 | 119 | 120 | 121 | 132 | 133 | 134 | 135 | 136 | 138 | 139 | 140 | 141 | 144 | 145 | 146 | 147 | 150 | 151 | 152 | 153 | 156 | 157 | 158 | 159 | 162 | 163 | 164 | 165 | 168 | 169 | 170 | 171 | 174 | 175 | 176 | 177 | 180 | 181 | 182 | 183 | 184 | 187 | 188 | 190 | 191 | 193 | 194 | 196 | 197 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | Vivado Synthesis Defaults 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | 334 | 335 | 336 | 337 | 338 | 339 | 340 | 341 | 342 | 343 | 344 | 345 | 346 | 347 | 348 | 349 | 350 | 351 | 352 | 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 362 | 363 | 364 | 365 | 366 | 367 | 368 | 369 | 370 | 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | Default settings for Implementation. 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | 451 | 452 | default_dashboard 453 | 454 | 455 | 456 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/EE4218_MLP_Neural_Network_HDL_New.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AnuragSChatterjee/Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA/05aaa9cf39f4ac76ec177f532ff0394c63cf62d9/Hardware Description Language (HDL) Implementation/EE4218_MLP_Neural_Network_HDL_New.zip -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/EE4218_Project_MLP_HDL_New_10Apr.xsa: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AnuragSChatterjee/Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA/05aaa9cf39f4ac76ec177f532ff0394c63cf62d9/Hardware Description Language (HDL) Implementation/EE4218_Project_MLP_HDL_New_10Apr.xsa -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/Sigmoid.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 03/21/2023 12:40:57 AM 7 | // Design Name: 8 | // Module Name: Sigmoid 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | //COMPARE WITH PURE CALCULATION LATER 23 | module Sigmoid #( 24 | parameter width = 8, // width is the number of bits per location 25 | parameter Interm1_depth_bits = 7, // depth is the number of locations (2^number of Location bits) 26 | parameter RES_depth_bits = 7 27 | ) 28 | ( 29 | input clk, 30 | input Start_Sigmoid, 31 | output reg End_Sigmoid, 32 | 33 | 34 | output wire Interm1_read_en, // matrix_multiply_0 -> A_RAM. Possibly reg. 35 | output reg [Interm1_depth_bits-1:0] Interm1_read_address, // matrix_multiply_0 -> A_RAM. Possibly reg. 36 | input [width-1:0] Interm1_read_data_out, // A_RAM -> matrix_multiply_0. 37 | 38 | output wire RES_write_en, // matrix_multiply_0 -> RES_RAM. Possibly reg. 39 | output reg [RES_depth_bits-1:0] RES_write_address, // matrix_multiply_0 -> RES_RAM. Possibly reg. 40 | output reg [width-1:0] RES_write_data_in // matrix_multiply_0 -> RES_RAM. Possibly reg. 41 | 42 | ); 43 | 44 | 45 | reg [Interm1_depth_bits:0] Location = 0; 46 | 47 | assign Interm1_read_en = Start_Sigmoid; //the function will allow reading for A_RAM and B_RAM 48 | assign RES_write_en = Start_Sigmoid; 49 | 50 | always @(posedge clk) 51 | begin 52 | if (Start_Sigmoid == 1) //once signal from the main state machine is given 53 | begin 54 | Interm1_read_address <= Location; 55 | RES_write_address <= Location-2; 56 | if (Interm1_read_data_out < 4) begin 57 | RES_write_data_in <= 12; 58 | end 59 | else if (Interm1_read_data_out < 7) begin 60 | RES_write_data_in <= 13; 61 | end 62 | else if (Interm1_read_data_out < 10) begin 63 | RES_write_data_in <= 14; 64 | end 65 | else if (Interm1_read_data_out < 13) begin 66 | RES_write_data_in <= 15; 67 | end 68 | else if (Interm1_read_data_out < 16) begin 69 | RES_write_data_in <= 16; 70 | end 71 | else if (Interm1_read_data_out < 18) begin 72 | RES_write_data_in <= 17; 73 | end 74 | else if (Interm1_read_data_out < 21) begin 75 | RES_write_data_in <= 18; 76 | end 77 | else if (Interm1_read_data_out < 23) begin 78 | RES_write_data_in <= 19; 79 | end 80 | else if (Interm1_read_data_out < 25) begin 81 | RES_write_data_in <= 20; 82 | end 83 | else if (Interm1_read_data_out < 28) begin 84 | RES_write_data_in <= 21; 85 | end 86 | else if (Interm1_read_data_out < 30) begin 87 | RES_write_data_in <= 22; 88 | end 89 | else if (Interm1_read_data_out < 32) begin 90 | RES_write_data_in <= 23; 91 | end 92 | else if (Interm1_read_data_out < 34) begin 93 | RES_write_data_in <= 24; 94 | end 95 | else if (Interm1_read_data_out < 35) begin 96 | RES_write_data_in <= 25; 97 | end 98 | else if (Interm1_read_data_out < 37) begin 99 | RES_write_data_in <= 26; 100 | end 101 | else if (Interm1_read_data_out < 39) begin 102 | RES_write_data_in <= 27; 103 | end 104 | else if (Interm1_read_data_out < 41) begin 105 | RES_write_data_in <= 28; 106 | end 107 | else if (Interm1_read_data_out < 42) begin 108 | RES_write_data_in <= 29; 109 | end 110 | else if (Interm1_read_data_out < 44) begin 111 | RES_write_data_in <= 30; 112 | end 113 | else if (Interm1_read_data_out < 45) begin 114 | RES_write_data_in <= 31; 115 | end 116 | else if (Interm1_read_data_out < 47) begin 117 | RES_write_data_in <= 32; 118 | end 119 | else if (Interm1_read_data_out < 48) begin 120 | RES_write_data_in <= 33; 121 | end 122 | else if (Interm1_read_data_out < 50) begin 123 | RES_write_data_in <= 34; 124 | end 125 | else if (Interm1_read_data_out < 51) begin 126 | RES_write_data_in <= 35; 127 | end 128 | else if (Interm1_read_data_out < 53) begin 129 | RES_write_data_in <= 36; 130 | end 131 | else if (Interm1_read_data_out < 54) begin 132 | RES_write_data_in <= 37; 133 | end 134 | else if (Interm1_read_data_out < 55) begin 135 | RES_write_data_in <= 38; 136 | end 137 | else if (Interm1_read_data_out < 57) begin 138 | RES_write_data_in <= 39; 139 | end 140 | else if (Interm1_read_data_out < 58) begin 141 | RES_write_data_in <= 40; 142 | end 143 | else if (Interm1_read_data_out < 59) begin 144 | RES_write_data_in <= 41; 145 | end 146 | else if (Interm1_read_data_out < 60) begin 147 | RES_write_data_in <= 42; 148 | end 149 | else if (Interm1_read_data_out < 61) begin 150 | RES_write_data_in <= 43; 151 | end 152 | else if (Interm1_read_data_out < 63) begin 153 | RES_write_data_in <= 44; 154 | end 155 | else if (Interm1_read_data_out < 64) begin 156 | RES_write_data_in <= 45; 157 | end 158 | else if (Interm1_read_data_out < 65) begin 159 | RES_write_data_in <= 46; 160 | end 161 | else if (Interm1_read_data_out < 66) begin 162 | RES_write_data_in <= 47; 163 | end 164 | else if (Interm1_read_data_out < 67) begin 165 | RES_write_data_in <= 48; 166 | end 167 | else if (Interm1_read_data_out < 68) begin 168 | RES_write_data_in <= 49; 169 | end 170 | else if (Interm1_read_data_out < 69) begin 171 | RES_write_data_in <= 50; 172 | end 173 | else if (Interm1_read_data_out < 70) begin 174 | RES_write_data_in <= 51; 175 | end 176 | else if (Interm1_read_data_out < 71) begin 177 | RES_write_data_in <= 52; 178 | end 179 | else if (Interm1_read_data_out < 72) begin 180 | RES_write_data_in <= 53; 181 | end 182 | else if (Interm1_read_data_out < 73) begin 183 | RES_write_data_in <= 54; 184 | end 185 | else if (Interm1_read_data_out < 74) begin 186 | RES_write_data_in <= 55; 187 | end 188 | else if (Interm1_read_data_out < 75) begin 189 | RES_write_data_in <= 56; 190 | end 191 | else if (Interm1_read_data_out < 76) begin 192 | RES_write_data_in <= 57; 193 | end 194 | else if (Interm1_read_data_out < 77) begin 195 | RES_write_data_in <= 58; 196 | end 197 | else if (Interm1_read_data_out < 78) begin 198 | RES_write_data_in <= 59; 199 | end 200 | else if (Interm1_read_data_out < 79) begin 201 | RES_write_data_in <= 60; 202 | end 203 | else if (Interm1_read_data_out < 80) begin 204 | RES_write_data_in <= 61; 205 | end 206 | else if (Interm1_read_data_out < 81) begin 207 | RES_write_data_in <= 62; 208 | end 209 | else if (Interm1_read_data_out < 82) begin 210 | RES_write_data_in <= 63; 211 | end 212 | else if (Interm1_read_data_out < 83) begin 213 | RES_write_data_in <= 64; 214 | end 215 | else if (Interm1_read_data_out < 84) begin 216 | RES_write_data_in <= 66; 217 | end 218 | else if (Interm1_read_data_out < 85) begin 219 | RES_write_data_in <= 67; 220 | end 221 | else if (Interm1_read_data_out < 86) begin 222 | RES_write_data_in <= 68; 223 | end 224 | else if (Interm1_read_data_out < 87) begin 225 | RES_write_data_in <= 69; 226 | end 227 | else if (Interm1_read_data_out < 88) begin 228 | RES_write_data_in <= 70; 229 | end 230 | else if (Interm1_read_data_out < 89) begin 231 | RES_write_data_in <= 72; 232 | end 233 | else if (Interm1_read_data_out < 90) begin 234 | RES_write_data_in <= 73; 235 | end 236 | else if (Interm1_read_data_out < 91) begin 237 | RES_write_data_in <= 74; 238 | end 239 | else if (Interm1_read_data_out < 92) begin 240 | RES_write_data_in <= 75; 241 | end 242 | else if (Interm1_read_data_out < 93) begin 243 | RES_write_data_in <= 76; 244 | end 245 | else if (Interm1_read_data_out < 94) begin 246 | RES_write_data_in <= 78; 247 | end 248 | else if (Interm1_read_data_out < 95) begin 249 | RES_write_data_in <= 79; 250 | end 251 | else if (Interm1_read_data_out < 96) begin 252 | RES_write_data_in <= 80; 253 | end 254 | else if (Interm1_read_data_out < 97) begin 255 | RES_write_data_in <= 82; 256 | end 257 | else if (Interm1_read_data_out < 98) begin 258 | RES_write_data_in <= 83; 259 | end 260 | else if (Interm1_read_data_out < 99) begin 261 | RES_write_data_in <= 84; 262 | end 263 | else if (Interm1_read_data_out < 100) begin 264 | RES_write_data_in <= 86; 265 | end 266 | else if (Interm1_read_data_out < 101) begin 267 | RES_write_data_in <= 87; 268 | end 269 | else if (Interm1_read_data_out < 102) begin 270 | RES_write_data_in <= 88; 271 | end 272 | else if (Interm1_read_data_out < 103) begin 273 | RES_write_data_in <= 90; 274 | end 275 | else if (Interm1_read_data_out < 104) begin 276 | RES_write_data_in <= 91; 277 | end 278 | else if (Interm1_read_data_out < 105) begin 279 | RES_write_data_in <= 92; 280 | end 281 | else if (Interm1_read_data_out < 106) begin 282 | RES_write_data_in <= 94; 283 | end 284 | else if (Interm1_read_data_out < 107) begin 285 | RES_write_data_in <= 95; 286 | end 287 | else if (Interm1_read_data_out < 108) begin 288 | RES_write_data_in <= 97; 289 | end 290 | else if (Interm1_read_data_out < 109) begin 291 | RES_write_data_in <= 98; 292 | end 293 | else if (Interm1_read_data_out < 110) begin 294 | RES_write_data_in <= 99; 295 | end 296 | else if (Interm1_read_data_out < 111) begin 297 | RES_write_data_in <= 101; 298 | end 299 | else if (Interm1_read_data_out < 112) begin 300 | RES_write_data_in <= 102; 301 | end 302 | else if (Interm1_read_data_out < 113) begin 303 | RES_write_data_in <= 104; 304 | end 305 | else if (Interm1_read_data_out < 114) begin 306 | RES_write_data_in <= 105; 307 | end 308 | else if (Interm1_read_data_out < 115) begin 309 | RES_write_data_in <= 107; 310 | end 311 | else if (Interm1_read_data_out < 116) begin 312 | RES_write_data_in <= 108; 313 | end 314 | else if (Interm1_read_data_out < 117) begin 315 | RES_write_data_in <= 110; 316 | end 317 | else if (Interm1_read_data_out < 118) begin 318 | RES_write_data_in <= 111; 319 | end 320 | else if (Interm1_read_data_out < 119) begin 321 | RES_write_data_in <= 113; 322 | end 323 | else if (Interm1_read_data_out < 120) begin 324 | RES_write_data_in <= 114; 325 | end 326 | else if (Interm1_read_data_out < 121) begin 327 | RES_write_data_in <= 116; 328 | end 329 | else if (Interm1_read_data_out < 122) begin 330 | RES_write_data_in <= 117; 331 | end 332 | else if (Interm1_read_data_out < 123) begin 333 | RES_write_data_in <= 119; 334 | end 335 | else if (Interm1_read_data_out < 124) begin 336 | RES_write_data_in <= 120; 337 | end 338 | else if (Interm1_read_data_out < 125) begin 339 | RES_write_data_in <= 122; 340 | end 341 | else if (Interm1_read_data_out < 126) begin 342 | RES_write_data_in <= 123; 343 | end 344 | else if (Interm1_read_data_out < 127) begin 345 | RES_write_data_in <= 125; 346 | end 347 | else if (Interm1_read_data_out < 128) begin 348 | RES_write_data_in <= 126; 349 | end 350 | else if (Interm1_read_data_out < 129) begin 351 | RES_write_data_in <= 128; 352 | end 353 | else if (Interm1_read_data_out < 130) begin 354 | RES_write_data_in <= 129; 355 | end 356 | else if (Interm1_read_data_out < 131) begin 357 | RES_write_data_in <= 130; 358 | end 359 | else if (Interm1_read_data_out < 132) begin 360 | RES_write_data_in <= 132; 361 | end 362 | else if (Interm1_read_data_out < 133) begin 363 | RES_write_data_in <= 133; 364 | end 365 | else if (Interm1_read_data_out < 134) begin 366 | RES_write_data_in <= 135; 367 | end 368 | else if (Interm1_read_data_out < 135) begin 369 | RES_write_data_in <= 136; 370 | end 371 | else if (Interm1_read_data_out < 136) begin 372 | RES_write_data_in <= 138; 373 | end 374 | else if (Interm1_read_data_out < 137) begin 375 | RES_write_data_in <= 139; 376 | end 377 | else if (Interm1_read_data_out < 138) begin 378 | RES_write_data_in <= 141; 379 | end 380 | else if (Interm1_read_data_out < 139) begin 381 | RES_write_data_in <= 142; 382 | end 383 | else if (Interm1_read_data_out < 140) begin 384 | RES_write_data_in <= 144; 385 | end 386 | else if (Interm1_read_data_out < 141) begin 387 | RES_write_data_in <= 145; 388 | end 389 | else if (Interm1_read_data_out < 142) begin 390 | RES_write_data_in <= 147; 391 | end 392 | else if (Interm1_read_data_out < 143) begin 393 | RES_write_data_in <= 148; 394 | end 395 | else if (Interm1_read_data_out < 144) begin 396 | RES_write_data_in <= 150; 397 | end 398 | else if (Interm1_read_data_out < 145) begin 399 | RES_write_data_in <= 151; 400 | end 401 | else if (Interm1_read_data_out < 146) begin 402 | RES_write_data_in <= 153; 403 | end 404 | else if (Interm1_read_data_out < 147) begin 405 | RES_write_data_in <= 154; 406 | end 407 | else if (Interm1_read_data_out < 148) begin 408 | RES_write_data_in <= 156; 409 | end 410 | else if (Interm1_read_data_out < 149) begin 411 | RES_write_data_in <= 157; 412 | end 413 | else if (Interm1_read_data_out < 150) begin 414 | RES_write_data_in <= 158; 415 | end 416 | else if (Interm1_read_data_out < 151) begin 417 | RES_write_data_in <= 160; 418 | end 419 | else if (Interm1_read_data_out < 152) begin 420 | RES_write_data_in <= 161; 421 | end 422 | else if (Interm1_read_data_out < 153) begin 423 | RES_write_data_in <= 163; 424 | end 425 | else if (Interm1_read_data_out < 154) begin 426 | RES_write_data_in <= 164; 427 | end 428 | else if (Interm1_read_data_out < 155) begin 429 | RES_write_data_in <= 165; 430 | end 431 | else if (Interm1_read_data_out < 156) begin 432 | RES_write_data_in <= 167; 433 | end 434 | else if (Interm1_read_data_out < 157) begin 435 | RES_write_data_in <= 168; 436 | end 437 | else if (Interm1_read_data_out < 158) begin 438 | RES_write_data_in <= 169; 439 | end 440 | else if (Interm1_read_data_out < 159) begin 441 | RES_write_data_in <= 171; 442 | end 443 | else if (Interm1_read_data_out < 160) begin 444 | RES_write_data_in <= 172; 445 | end 446 | else if (Interm1_read_data_out < 161) begin 447 | RES_write_data_in <= 173; 448 | end 449 | else if (Interm1_read_data_out < 162) begin 450 | RES_write_data_in <= 175; 451 | end 452 | else if (Interm1_read_data_out < 163) begin 453 | RES_write_data_in <= 176; 454 | end 455 | else if (Interm1_read_data_out < 164) begin 456 | RES_write_data_in <= 177; 457 | end 458 | else if (Interm1_read_data_out < 165) begin 459 | RES_write_data_in <= 179; 460 | end 461 | else if (Interm1_read_data_out < 166) begin 462 | RES_write_data_in <= 180; 463 | end 464 | else if (Interm1_read_data_out < 167) begin 465 | RES_write_data_in <= 181; 466 | end 467 | else if (Interm1_read_data_out < 168) begin 468 | RES_write_data_in <= 182; 469 | end 470 | else if (Interm1_read_data_out < 169) begin 471 | RES_write_data_in <= 183; 472 | end 473 | else if (Interm1_read_data_out < 170) begin 474 | RES_write_data_in <= 185; 475 | end 476 | else if (Interm1_read_data_out < 171) begin 477 | RES_write_data_in <= 186; 478 | end 479 | else if (Interm1_read_data_out < 172) begin 480 | RES_write_data_in <= 187; 481 | end 482 | else if (Interm1_read_data_out < 173) begin 483 | RES_write_data_in <= 188; 484 | end 485 | else if (Interm1_read_data_out < 174) begin 486 | RES_write_data_in <= 189; 487 | end 488 | else if (Interm1_read_data_out < 175) begin 489 | RES_write_data_in <= 191; 490 | end 491 | else if (Interm1_read_data_out < 176) begin 492 | RES_write_data_in <= 192; 493 | end 494 | else if (Interm1_read_data_out < 177) begin 495 | RES_write_data_in <= 193; 496 | end 497 | else if (Interm1_read_data_out < 178) begin 498 | RES_write_data_in <= 194; 499 | end 500 | else if (Interm1_read_data_out < 179) begin 501 | RES_write_data_in <= 195; 502 | end 503 | else if (Interm1_read_data_out < 180) begin 504 | RES_write_data_in <= 196; 505 | end 506 | else if (Interm1_read_data_out < 181) begin 507 | RES_write_data_in <= 197; 508 | end 509 | else if (Interm1_read_data_out < 182) begin 510 | RES_write_data_in <= 198; 511 | end 512 | else if (Interm1_read_data_out < 183) begin 513 | RES_write_data_in <= 199; 514 | end 515 | else if (Interm1_read_data_out < 184) begin 516 | RES_write_data_in <= 200; 517 | end 518 | else if (Interm1_read_data_out < 185) begin 519 | RES_write_data_in <= 201; 520 | end 521 | else if (Interm1_read_data_out < 186) begin 522 | RES_write_data_in <= 202; 523 | end 524 | else if (Interm1_read_data_out < 187) begin 525 | RES_write_data_in <= 203; 526 | end 527 | else if (Interm1_read_data_out < 188) begin 528 | RES_write_data_in <= 204; 529 | end 530 | else if (Interm1_read_data_out < 189) begin 531 | RES_write_data_in <= 205; 532 | end 533 | else if (Interm1_read_data_out < 190) begin 534 | RES_write_data_in <= 206; 535 | end 536 | else if (Interm1_read_data_out < 191) begin 537 | RES_write_data_in <= 207; 538 | end 539 | else if (Interm1_read_data_out < 192) begin 540 | RES_write_data_in <= 208; 541 | end 542 | else if (Interm1_read_data_out < 193) begin 543 | RES_write_data_in <= 209; 544 | end 545 | else if (Interm1_read_data_out < 194) begin 546 | RES_write_data_in <= 210; 547 | end 548 | else if (Interm1_read_data_out < 196) begin 549 | RES_write_data_in <= 211; 550 | end 551 | else if (Interm1_read_data_out < 197) begin 552 | RES_write_data_in <= 212; 553 | end 554 | else if (Interm1_read_data_out < 198) begin 555 | RES_write_data_in <= 213; 556 | end 557 | else if (Interm1_read_data_out < 199) begin 558 | RES_write_data_in <= 214; 559 | end 560 | else if (Interm1_read_data_out < 200) begin 561 | RES_write_data_in <= 215; 562 | end 563 | else if (Interm1_read_data_out < 202) begin 564 | RES_write_data_in <= 216; 565 | end 566 | else if (Interm1_read_data_out < 203) begin 567 | RES_write_data_in <= 217; 568 | end 569 | else if (Interm1_read_data_out < 204) begin 570 | RES_write_data_in <= 218; 571 | end 572 | else if (Interm1_read_data_out < 206) begin 573 | RES_write_data_in <= 219; 574 | end 575 | else if (Interm1_read_data_out < 207) begin 576 | RES_write_data_in <= 220; 577 | end 578 | else if (Interm1_read_data_out < 209) begin 579 | RES_write_data_in <= 221; 580 | end 581 | else if (Interm1_read_data_out < 210) begin 582 | RES_write_data_in <= 222; 583 | end 584 | else if (Interm1_read_data_out < 212) begin 585 | RES_write_data_in <= 223; 586 | end 587 | else if (Interm1_read_data_out < 213) begin 588 | RES_write_data_in <= 224; 589 | end 590 | else if (Interm1_read_data_out < 215) begin 591 | RES_write_data_in <= 225; 592 | end 593 | else if (Interm1_read_data_out < 216) begin 594 | RES_write_data_in <= 226; 595 | end 596 | else if (Interm1_read_data_out < 218) begin 597 | RES_write_data_in <= 227; 598 | end 599 | else if (Interm1_read_data_out < 220) begin 600 | RES_write_data_in <= 228; 601 | end 602 | else if (Interm1_read_data_out < 222) begin 603 | RES_write_data_in <= 229; 604 | end 605 | else if (Interm1_read_data_out < 223) begin 606 | RES_write_data_in <= 230; 607 | end 608 | else if (Interm1_read_data_out < 225) begin 609 | RES_write_data_in <= 231; 610 | end 611 | else if (Interm1_read_data_out < 227) begin 612 | RES_write_data_in <= 232; 613 | end 614 | else if (Interm1_read_data_out < 229) begin 615 | RES_write_data_in <= 233; 616 | end 617 | else if (Interm1_read_data_out < 232) begin 618 | RES_write_data_in <= 234; 619 | end 620 | else if (Interm1_read_data_out < 234) begin 621 | RES_write_data_in <= 235; 622 | end 623 | else if (Interm1_read_data_out < 236) begin 624 | RES_write_data_in <= 236; 625 | end 626 | else if (Interm1_read_data_out < 239) begin 627 | RES_write_data_in <= 237; 628 | end 629 | else if (Interm1_read_data_out < 241) begin 630 | RES_write_data_in <= 238; 631 | end 632 | else if (Interm1_read_data_out < 244) begin 633 | RES_write_data_in <= 239; 634 | end 635 | else if (Interm1_read_data_out < 247) begin 636 | RES_write_data_in <= 240; 637 | end 638 | else if (Interm1_read_data_out < 250) begin 639 | RES_write_data_in <= 241; 640 | end 641 | else if (Interm1_read_data_out < 253) begin 642 | RES_write_data_in <= 242; 643 | end 644 | else begin 645 | RES_write_data_in <= 243; 646 | end 647 | 648 | 649 | Location <= Location + 1; 650 | 651 | if (Location == 129) 652 | begin 653 | End_Sigmoid <= 1; 654 | end 655 | end 656 | 657 | else 658 | begin 659 | End_Sigmoid <= 0; 660 | Location <= 0; 661 | end 662 | 663 | end 664 | endmodule 665 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/X.mem: -------------------------------------------------------------------------------- 1 | 2c 2 | 5a 3 | 0 4 | 0 5 | 18 6 | 51 7 | 16 8 | 9f 9 | fa 10 | 8c 11 | b0 12 | 79 13 | b7 14 | 8a 15 | a7 16 | 9e 17 | ac 18 | 86 19 | ac 20 | a1 21 | 76 22 | 82 23 | b2 24 | 88 25 | 78 26 | 87 27 | 79 28 | 56 29 | 22 30 | 70 31 | 8e 32 | 70 33 | a3 34 | 9f 35 | 2b 36 | 3f 37 | 1c 38 | 91 39 | 7e 40 | be 41 | a5 42 | 42 43 | 58 44 | d6 45 | 9d 46 | 8c 47 | cd 48 | ae 49 | 80 50 | b9 51 | cb 52 | aa 53 | 6e 54 | d3 55 | 8a 56 | 7e 57 | 8c 58 | ff 59 | 6e 60 | 88 61 | 85 62 | 9c 63 | 83 64 | 49 65 | 5a 66 | a4 67 | 76 68 | 4b 69 | 79 70 | 6f 71 | 10 72 | 5d 73 | bb 74 | 58 75 | a2 76 | 65 77 | 1b 78 | 1f 79 | 6e 80 | 78 81 | 4d 82 | a6 83 | 65 84 | 2d 85 | b7 86 | b5 87 | 9b 88 | af 89 | 87 90 | d3 91 | b9 92 | 81 93 | c1 94 | 68 95 | 9f 96 | b8 97 | b7 98 | a1 99 | be 100 | b7 101 | 8f 102 | 7c 103 | 8b 104 | 8a 105 | 91 106 | 4f 107 | 71 108 | 73 109 | 6f 110 | a4 111 | 65 112 | 58 113 | d5 114 | d5 115 | 95 116 | 9f 117 | 85 118 | c7 119 | b7 120 | d 121 | 5e 122 | 7f 123 | 92 124 | 84 125 | 96 126 | 59 127 | 67 128 | af 129 | a4 130 | 8b 131 | bb 132 | 93 133 | 80 134 | 2a 135 | 52 136 | 68 137 | 53 138 | a7 139 | 32 140 | 47 141 | 1a 142 | 5a 143 | 6d 144 | 8f 145 | 87 146 | dc 147 | 6a 148 | 45 149 | 5a 150 | 65 151 | b4 152 | 7d 153 | de 154 | 6c 155 | 8f 156 | e1 157 | 7d 158 | 93 159 | c4 160 | c5 161 | 79 162 | 49 163 | 57 164 | 7d 165 | 1d 166 | 8 167 | 57 168 | 43 169 | 64 170 | 88 171 | fe 172 | 77 173 | aa 174 | 8c 175 | 4d 176 | 6e 177 | 88 178 | 65 179 | 89 180 | ba 181 | ae 182 | 7e 183 | a5 184 | 8f 185 | b3 186 | 97 187 | a7 188 | 9c 189 | 93 190 | b6 191 | cf 192 | 83 193 | 69 194 | 82 195 | 65 196 | 7c 197 | 22 198 | 33 199 | c2 200 | 5e 201 | 5a 202 | 5e 203 | 3a 204 | 6c 205 | 55 206 | 74 207 | 19 208 | 18 209 | 0 210 | 3b 211 | 12 212 | 46 213 | 6e 214 | 76 215 | b3 216 | 8a 217 | 32 218 | 23 219 | a5 220 | 78 221 | 48 222 | 7e 223 | 48 224 | 52 225 | 48 226 | 63 227 | 55 228 | 4c 229 | d2 230 | 65 231 | 38 232 | 1b 233 | 55 234 | 55 235 | 6d 236 | 7a 237 | 85 238 | 36 239 | 95 240 | a6 241 | b0 242 | 6f 243 | 87 244 | 73 245 | 62 246 | 8a 247 | b4 248 | 88 249 | 83 250 | ff 251 | 8b 252 | 54 253 | 78 254 | 61 255 | 73 256 | 60 257 | 6e 258 | 80 259 | 2c 260 | b7 261 | b5 262 | b7 263 | 98 264 | 77 265 | ae 266 | 94 267 | 26 268 | 71 269 | 7d 270 | 43 271 | 58 272 | 1a 273 | 44 274 | b4 275 | bc 276 | a9 277 | 89 278 | bc 279 | 7c 280 | 91 281 | 56 282 | 57 283 | 50 284 | 48 285 | 4c 286 | 49 287 | 47 288 | db 289 | e0 290 | 9b 291 | a5 292 | c5 293 | fc 294 | da 295 | 1f 296 | 41 297 | 91 298 | 26 299 | 70 300 | 20 301 | 4e 302 | 15 303 | 86 304 | 30 305 | 53 306 | 5e 307 | 4e 308 | 6f 309 | 6f 310 | 3e 311 | 80 312 | 59 313 | a3 314 | d1 315 | 41 316 | e0 317 | ce 318 | 80 319 | 9b 320 | a7 321 | aa 322 | 96 323 | e7 324 | e1 325 | 8b 326 | ae 327 | 95 328 | ca 329 | d0 330 | 8c 331 | 92 332 | 6a 333 | 7c 334 | c0 335 | 8e 336 | 68 337 | 74 338 | bf 339 | c4 340 | 88 341 | c0 342 | aa 343 | 6c 344 | 2b 345 | 88 346 | 83 347 | 3a 348 | 2c 349 | 32 350 | 76 351 | 27 352 | 4c 353 | 82 354 | 3f 355 | 47 356 | 3e 357 | 27 358 | 67 359 | a6 360 | aa 361 | 73 362 | ec 363 | 83 364 | 4b 365 | 53 366 | 94 367 | ce 368 | 78 369 | 8e 370 | 9c 371 | 66 372 | 49 373 | 29 374 | 96 375 | 3f 376 | 7b 377 | 4e 378 | 33 379 | 9f 380 | 88 381 | 5d 382 | 99 383 | 8c 384 | 95 385 | c6 386 | e 387 | 4d 388 | a0 389 | 43 390 | 44 391 | 48 392 | 38 393 | 25 394 | 46 395 | 83 396 | 35 397 | 48 398 | 2e 399 | 25 400 | e1 401 | ab 402 | 88 403 | 94 404 | 88 405 | a1 406 | bc 407 | 40 408 | b1 409 | 4c 410 | 45 411 | 5c 412 | 5c 413 | 54 414 | 2c 415 | 36 416 | a6 417 | 5d 418 | 9e 419 | 65 420 | 3b 421 | 99 422 | aa 423 | 96 424 | 7d 425 | 98 426 | ab 427 | a6 428 | 56 429 | 9b 430 | 88 431 | 29 432 | 24 433 | 83 434 | 3f 435 | 8a 436 | a0 437 | 68 438 | 77 439 | 95 440 | 7c 441 | 64 442 | 13 443 | 38 444 | 8c 445 | 8b 446 | d9 447 | a1 448 | 33 449 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/labels.mem: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 1 4 | 1 5 | 0 6 | 0 7 | 1 8 | 1 9 | 1 10 | 0 11 | 0 12 | 0 13 | 1 14 | 1 15 | 1 16 | 0 17 | 1 18 | 0 19 | 1 20 | 0 21 | 0 22 | 1 23 | 1 24 | 0 25 | 1 26 | 1 27 | 1 28 | 1 29 | 0 30 | 0 31 | 0 32 | 0 33 | 0 34 | 0 35 | 1 36 | 1 37 | 0 38 | 1 39 | 0 40 | 1 41 | 0 42 | 1 43 | 0 44 | 0 45 | 1 46 | 1 47 | 1 48 | 1 49 | 1 50 | 0 51 | 0 52 | 1 53 | 1 54 | 0 55 | 1 56 | 0 57 | 0 58 | 1 59 | 0 60 | 0 61 | 1 62 | 0 63 | 1 64 | 0 65 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/matrix_multiply.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | ---------------------------------------------------------------------------------- 5 | -- (c) Rajesh C Panicker, NUS 6 | -- Description : Template for the Matrix Multiply unit for the AXI Stream Coprocessor 7 | -- License terms : 8 | -- You are free to use this code as long as you 9 | -- (i) DO NOT post a modified version of this on any public repository; 10 | -- (ii) use it only for educational purposes; 11 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 12 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 13 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 14 | -- (vi) retain this notice in this file or any files derived from this. 15 | ---------------------------------------------------------------------------------- 16 | */ 17 | 18 | // those outputs which are assigned in an always block of matrix_multiply shoud be changes to reg (such as output reg Done). 19 | 20 | module matrix_multiply 21 | #( parameter width = 8, // width is the number of bits per location 22 | parameter A_depth_bits = 9, // for 64 x 7 matrix 23 | parameter B_depth_bits = 4, // for 8 x 2 matrix 24 | //parameter D_depth_bits = 2, 25 | parameter Interm1_depth_bits = 7 //for 64 x 2 matrix for A * B 26 | ) 27 | ( 28 | input clk, 29 | input Start, // myip_v1_0 -> matrix_multiply_0. 30 | output reg Done, // matrix_multiply_0 -> myip_v1_0. Possibly reg. 31 | 32 | output A_read_en, // matrix_multiply_0 -> A_RAM. Possibly reg. 33 | output [A_depth_bits-1:0] A_read_address, // matrix_multiply_0 -> A_RAM. Possibly reg. 34 | input [width-1:0] A_read_data_out, // A_RAM -> matrix_multiply_0. 35 | 36 | output B_read_en, // matrix_multiply_0 -> B_RAM. Possibly reg. 37 | output [B_depth_bits-1:0] B_read_address, // matrix_multiply_0 -> B_RAM. Possibly reg. 38 | input [width-1:0] B_read_data_out, // B_RAM -> matrix_multiply_0. 39 | 40 | output reg Interm1_write_en, // matrix_multiply_0 -> RES_RAM. Possibly reg. 41 | output reg [Interm1_depth_bits-1:0] Interm1_write_address, // matrix_multiply_0 -> RES_RAM. Possibly reg. 42 | output reg [width-1:0] Interm1_write_data_in, // matrix_multiply_0 -> RES_RAM. Possibly reg. 43 | 44 | input [7:0] bias_A, 45 | input [7:0] bias_B 46 | ); 47 | 48 | // implement the logic to read A_RAM, read B_RAM, do the multiplication and write the results to RES_RAM 49 | // Note: A_RAM and B_RAM are to be read synchronously. Read the wiki for more details. 50 | 51 | reg [15:0] sum = 0; 52 | reg [$clog2(2**A_depth_bits):0] read_A_counter = 0; //read X matrix i.e. 64 x 7 matrix 53 | reg [$clog2(8):0] read_B_counter = 0; //read w_hid matrix rows i.e 8 54 | reg [$clog2(2**A_depth_bits - 64):0] write_counter = 0; //write result which is A*B i.e a 64 x 7 matrix 55 | 56 | wire [15:0] AB_PRODUCT; 57 | 58 | reg sum_delay = 0; 59 | assign AB_PRODUCT = A_read_data_out * B_read_data_out; 60 | assign A_read_address = read_A_counter; 61 | assign B_read_address = read_B_counter; 62 | assign A_read_en = Start; 63 | assign B_read_en = Start; 64 | 65 | 66 | always @(posedge clk) 67 | begin 68 | if (Start) //once signal from the main state machine is given 69 | begin 70 | if (read_A_counter == 0 && write_counter == 0) 71 | begin 72 | sum <= bias_A << 8; 73 | read_A_counter <= read_A_counter + 1; 74 | read_B_counter <= read_B_counter + 1; 75 | end 76 | else if (write_counter == 2**Interm1_depth_bits) 77 | begin 78 | Interm1_write_en <= 0; 79 | sum <= 0; 80 | Done <= 1; 81 | end 82 | else if ( read_A_counter == 7 && write_counter < 63) 83 | begin 84 | read_B_counter <= 0; 85 | sum <= sum + AB_PRODUCT; 86 | end 87 | else if ( read_B_counter == 6 && write_counter < 63) 88 | begin 89 | read_B_counter <= 7; 90 | read_A_counter <= 0; 91 | sum <= sum + AB_PRODUCT; 92 | sum_delay = 1; 93 | end 94 | else if(sum_delay == 1) 95 | begin 96 | sum <= sum + AB_PRODUCT; 97 | sum_delay <= 0; 98 | end 99 | else if ( read_B_counter == 14) 100 | begin 101 | read_B_counter <= 7; 102 | sum <= sum + AB_PRODUCT; 103 | end 104 | else if ( (read_B_counter == 0 && write_counter < 63) | read_B_counter== 7) 105 | begin 106 | Interm1_write_en <= 1; 107 | Interm1_write_address <= write_counter; 108 | Interm1_write_data_in <= sum[15:8]; 109 | write_counter <= write_counter + 1; 110 | read_B_counter <= (write_counter < 63) ? 1:8; 111 | sum <= (write_counter < 63) ? bias_A << 8 : bias_B << 8; 112 | read_A_counter <= read_B_counter + 1; 113 | end 114 | 115 | else begin 116 | sum <= sum + AB_PRODUCT; 117 | read_A_counter <= read_A_counter + 1; 118 | read_B_counter <= read_B_counter + 1; 119 | end 120 | end 121 | 122 | else begin 123 | Done <= 0; 124 | read_A_counter <= 0; 125 | read_B_counter <= 0; 126 | write_counter <= 0; 127 | end 128 | end 129 | endmodule 130 | 131 | 132 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/memory_RAM_new_file.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | ---------------------------------------------------------------------------------- 5 | -- (c) Rajesh C Panicker, NUS 6 | -- Description : Module implementing a single port fully synchronous RAM to act as local memory for the AXI Stream Coprocessor 7 | -- License terms : 8 | -- You are free to use this code as long as you 9 | -- (i) DO NOT post a modified version of this on any public repository; 10 | -- (ii) use it only for educational purposes; 11 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 12 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 13 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 14 | -- (vi) retain this notice in this file or any files derived from this. 15 | ---------------------------------------------------------------------------------- 16 | */ 17 | 18 | // width is the number of bits per location; depth_bits is the number of address bits. 2^depth_bits is the number of locations 19 | 20 | module memory_RAM 21 | #( 22 | parameter width = 8, // width is the number of bits per location 23 | parameter depth_bits = 2 // depth is the number of locations (2^number of address bits) 24 | ) 25 | ( 26 | input clk, 27 | input write_en, 28 | input [depth_bits-1:0] write_address, 29 | input [width-1:0] write_data_in, 30 | input read_en, 31 | input [depth_bits-1:0] read_address, 32 | output reg [width-1:0] read_data_out 33 | ); 34 | 35 | reg [width-1:0] RAM [0:2**depth_bits-1]; 36 | wire [depth_bits-1:0] address; 37 | wire enable; 38 | 39 | // to convert external signals to a form followed in the template given in Vivado synthesis manual. 40 | // Not really necessary, but to follow the spirit of using templates 41 | assign enable = read_en | write_en; 42 | assign address = write_en? write_address:read_address; 43 | 44 | // the following is from a template given in Vivado synthesis manual. 45 | // Read up more about write first, read first, no change modes. 46 | 47 | always @(posedge clk) 48 | begin 49 | if (enable) 50 | begin 51 | if (write_en) 52 | RAM[address] <= write_data_in; 53 | else 54 | read_data_out <= RAM[address]; 55 | end 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/myip_v1_0_new_file.v: -------------------------------------------------------------------------------- 1 | /* 2 | ---------------------------------------------------------------------------------- 3 | -- (c) Rajesh C Panicker, NUS 4 | -- Description : Matrix Multiplication AXI Stream Coprocessor. Based on the orginal AXIS Coprocessor template (c) Xilinx Inc 5 | -- Based on the orginal AXIS coprocessor template (c) Xilinx Inc 6 | -- License terms : 7 | -- You are free to use this code as long as you 8 | -- (i) DO NOT post a modified version of this on any public repository; 9 | -- (ii) use it only for educational purposes; 10 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 11 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 12 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 13 | -- (vi) retain this notice in this file or any files derived from this. 14 | ---------------------------------------------------------------------------------- 15 | */ 16 | /* 17 | ------------------------------------------------------------------------------- 18 | -- 19 | -- Definition of Ports 20 | -- ACLK : Synchronous clock 21 | -- ARESETN : System reset, active low 22 | -- S_AXIS_TREADY : Ready to accept data in 23 | -- S_AXIS_TDATA : Data in 24 | -- S_AXIS_TLAST : Optional data in qualifier 25 | -- S_AXIS_TVALID : Data in is valid 26 | -- M_AXIS_TVALID : Data out is valid 27 | -- M_AXIS_TDATA : Data Out 28 | -- M_AXIS_TLAST : Optional data out qualifier 29 | -- M_AXIS_TREADY : Connected slave device is ready to accept data out 30 | -- 31 | ------------------------------------------------------------------------------- 32 | */ 33 | 34 | module myip_v1_0 35 | ( 36 | // DO NOT EDIT BELOW THIS LINE //////////////////// 37 | ACLK, 38 | ARESETN, 39 | S_AXIS_TREADY, 40 | S_AXIS_TDATA, 41 | S_AXIS_TLAST, 42 | S_AXIS_TVALID, 43 | M_AXIS_TVALID, 44 | M_AXIS_TDATA, 45 | M_AXIS_TLAST, 46 | M_AXIS_TREADY 47 | // DO NOT EDIT ABOVE THIS LINE //////////////////// 48 | ); 49 | 50 | input ACLK; // Synchronous clock 51 | input ARESETN; // System reset, active low 52 | // slave in interface 53 | output reg S_AXIS_TREADY; // Ready to accept data in 54 | input [31 : 0] S_AXIS_TDATA; // Data in 55 | input S_AXIS_TLAST; // Optional data in qualifier 56 | input S_AXIS_TVALID; // Data in is valid 57 | // master out interface 58 | output reg M_AXIS_TVALID; // Data out is valid 59 | output wire [31 : 0] M_AXIS_TDATA; // Data Out 60 | output M_AXIS_TLAST; // Optional data out qualifier 61 | input M_AXIS_TREADY; // Connected slave device is ready to accept data out 62 | 63 | //---------------------------------------- 64 | // Implementation Section 65 | //---------------------------------------- 66 | // In this section, we povide an example implementation of MODULE myip_v1_0 67 | // that does the following: 68 | // 69 | // 1. Read all inputs 70 | // 2. Add each input to the contents of register 'sum' which acts as an accumulator 71 | // 3. After all the inputs have been read, write out the content of 'sum', 'sum+1', 'sum+2', 'sum+3' 72 | // 73 | // You will need to modify this example for 74 | // MODULE myip_v1_0 to implement your coprocessor 75 | 76 | 77 | // RAM parameters for assignment 1 78 | localparam A_depth_bits = 9; // X matrix (A is a 64x7 matrix so just keeping it at 2**9 which is 512 79 | localparam B_depth_bits = 4; // w_hid (B is a 8x2 matrix) 80 | localparam C_depth_bits = 2; // w_out matrix (C is a 3x1 matrix so keeping it as 2**2 which is 4) 81 | localparam RES_depth_bits = 7; // to store A * B first which is a 64 x 2 matrix 82 | 83 | localparam Interm1_depth_bits = 7; // 2 elements (RES is a 2x1 matrix), 128 elements (RES = 64 x 2 matrix) 84 | localparam Interm2_depth_bits = 7; // 2 elements (RES is a 2x1 matrix), 128 elements (RES = 64 x 2 matrix) which feeds in from Interm1 85 | localparam width = 8; // all 8-bit data 86 | 87 | // wires (or regs) to connect to RAMs and matrix_multiply_0 for assignment 1 88 | // those which are assigned in an always block of myip_v1_0 shoud be changes to reg. 89 | reg A_write_en; // myip_v1_0 -> A_RAM. To be assigned within myip_v1_0. Possibly reg. 90 | reg [A_depth_bits-1:0] A_write_address; // myip_v1_0 -> A_RAM. To be assigned within myip_v1_0. Possibly reg. 91 | reg [width-1:0] A_write_data_in; // myip_v1_0 -> A_RAM. To be assigned within myip_v1_0. Possibly reg. 92 | wire A_read_en; // matrix_multiply_0 -> A_RAM. 93 | wire [A_depth_bits-1:0] A_read_address; // matrix_multiply_0 -> A_RAM. 94 | wire [width-1:0] A_read_data_out; // A_RAM -> matrix_multiply_0. 95 | 96 | reg B_write_en; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 97 | reg [B_depth_bits-1:0] B_write_address; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 98 | reg [width-1:0] B_write_data_in; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 99 | wire B_read_en; // matrix_multiply_0 -> B_RAM. 100 | wire [B_depth_bits-1:0] B_read_address; // matrix_multiply_0 -> B_RAM. 101 | wire [width-1:0] B_read_data_out; // B_RAM -> matrix_multiply_0. 102 | 103 | reg C_write_en; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 104 | reg [C_depth_bits-1:0] C_write_address; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 105 | reg [width-1:0] C_write_data_in; // myip_v1_0 -> B_RAM. To be assigned within myip_v1_0. Possibly reg. 106 | wire C_read_en; // matrix_multiply_0 -> B_RAM. 107 | wire [C_depth_bits-1:0] C_read_address; // matrix_multiply_0 -> B_RAM. 108 | wire [width-1:0] C_read_data_out; // B_RAM -> matrix_multiply_0. 109 | 110 | wire RES_write_en; // matrix_multiply_0 -> RES_RAM. 111 | wire [RES_depth_bits-1:0] RES_write_address; // matrix_multiply_0 -> RES_RAM. 112 | wire [width-1:0] RES_write_data_in; // matrix_multiply_0 -> RES_RAM. 113 | reg RES_read_en = 0; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 114 | wire [RES_depth_bits-1:0] RES_read_address; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 115 | wire [width-1:0] RES_read_data_out; // RES_RAM -> myip_v1_0 116 | 117 | wire Interm1_write_en; // matrix_multiply_0 -> RES_RAM. 118 | wire [Interm1_depth_bits-1:0] Interm1_write_address; // matrix_multiply_0 -> RES_RAM. 119 | wire [width-1:0] Interm1_write_data_in; // matrix_multiply_0 -> RES_RAM. 120 | wire Interm1_read_en; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 121 | wire [Interm1_depth_bits-1:0] Interm1_read_address; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 122 | wire [width-1:0] Interm1_read_data_out; // RES_RAM -> myip_v1_0 123 | 124 | wire Interm2_write_en; // matrix_multiply_0 -> RES_RAM. 125 | wire [Interm2_depth_bits-1:0] Interm2_write_address; // matrix_multiply_0 -> RES_RAM. 126 | wire [width-1:0] Interm2_write_data_in; // matrix_multiply_0 -> RES_RAM. 127 | reg Interm2_read_en = 0; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 128 | wire [Interm2_depth_bits-1:0] Interm2_read_address; // myip_v1_0 -> RES_RAM. To be assigned within myip_v1_0. Possibly reg. 129 | wire [width-1:0] Interm2_read_data_out; // RES_RAM -> myip_v1_0 130 | 131 | // wires (or regs) to connect to matrix_multiply for assignment 1 132 | reg Start; // myip_v1_0 -> matrix_multiply_0. To be assigned within myip_v1_0. Possibly reg. 133 | wire Done; // matrix_multiply_0 -> myip_v1_0. 134 | 135 | reg Start_Sigmoid; //Starts sigmoid function call 136 | wire End_Sigmoid; //Ends sigmoid function call 137 | 138 | // Total number of input data. 139 | localparam NUMBER_OF_A_WORDS = (2**A_depth_bits - 64); //448 data points for 64 x 7 matrix 140 | localparam NUMBER_OF_B_WORDS = 2**B_depth_bits; //4 data points for 8 x 2 matrix 141 | localparam NUMBER_OF_C_WORDS = (2**C_depth_bits - 1); //3 data points for 3 x 1 matrix 142 | //localparam NUMBER_OF_SIG_WORDS = 2**Sig_depth_bits; 143 | 144 | localparam NUMBER_OF_INPUT_WORDS = NUMBER_OF_A_WORDS + NUMBER_OF_B_WORDS + NUMBER_OF_C_WORDS; //467 in total 145 | // Total number of output data 146 | localparam NUMBER_OF_OUTPUT_WORDS = 2**RES_depth_bits; 147 | 148 | // Total number of output data 149 | //localparam NUMBER_OF_OUTPUT_WORDS = 128; // 2**RES_depth_bits = 2 for assignment 1 150 | 151 | // Define the states of state machine (one hot encoding) 152 | localparam Idle = 5'b10000; 153 | localparam Read_Inputs = 5'b01000; 154 | localparam Compute = 5'b00100; 155 | localparam Compute_Last_Layer = 5'b0010; 156 | localparam Write_Outputs = 5'b0001; 157 | 158 | reg [4:0] state; 159 | 160 | // Accumulator to hold sum of inputs read at any point in time 161 | // reg [31:0] sum; 162 | 163 | // Counters to store the number inputs read & outputs written. 164 | // Could be done using the same counter if reads and writes are not overlapped (i.e., no dataflow optimization) 165 | // Left as separate for ease of debugging 166 | reg [$clog2(NUMBER_OF_INPUT_WORDS) - 1:0] read_input_counter; //counter to read all matrix values 167 | reg [RES_depth_bits:0] write_RES_counter; //counter to compute the final result value 168 | 169 | reg disabled = 0; 170 | 171 | reg [$clog2(7) :0] bias_A; //first bias of w_hid 172 | reg [$clog2(7) :0] bias_B; //second bias of w_hid 173 | reg [$clog2(7) :0] bias_C; //first bias of w_out 174 | 175 | reg [15:0] Last_Layer_Value; 176 | 177 | /*************************** 178 | THIS SECTION IS ADDED 179 | */ 180 | assign RES_read_address = write_RES_counter; 181 | assign M_AXIS_TDATA = RES_read_data_out; 182 | assign M_AXIS_TLAST = (state == Write_Outputs) & (write_RES_counter == NUMBER_OF_OUTPUT_WORDS); //if goes into last state and wrote result already 183 | /* 184 | *///////////////////////////// 185 | 186 | 187 | always @(posedge ACLK) 188 | begin 189 | // implemented as a single-always Moore machine 190 | // a Mealy machine that asserts S_AXIS_TREADY and captures S_AXIS_TDATA etc can save a clock cycle 191 | 192 | /****** Synchronous reset (active low) ******/ 193 | if (!ARESETN) 194 | begin 195 | // CAUTION: make sure your reset polarity is consistent with the system reset polarity 196 | state <= Idle; 197 | end 198 | else 199 | begin 200 | case (state) 201 | 202 | Idle: 203 | begin 204 | read_input_counter <= 0; 205 | write_RES_counter <= 0; 206 | S_AXIS_TREADY <= 0; 207 | M_AXIS_TVALID <= 0; 208 | if (S_AXIS_TVALID == 1) 209 | begin 210 | state <= Read_Inputs; 211 | S_AXIS_TREADY <= 1; 212 | // start receiving data once you go into Read_Inputs 213 | end 214 | end 215 | 216 | Read_Inputs: 217 | begin 218 | S_AXIS_TREADY <= 1; 219 | if (S_AXIS_TVALID == 1) 220 | begin 221 | // Coprocessor function (adding the numbers together) happens here (partly) 222 | if (read_input_counter < NUMBER_OF_A_WORDS) //read X csv matrix 223 | begin 224 | A_write_en <= 1; 225 | A_write_address <= read_input_counter; 226 | A_write_data_in <= S_AXIS_TDATA; 227 | end 228 | else if (read_input_counter < NUMBER_OF_A_WORDS + 14) //starts reading w_hid matrix 229 | begin //last data will be sent to B_RAM 230 | A_write_en <= 0; 231 | B_write_en <= 1; 232 | B_write_address <= read_input_counter - NUMBER_OF_A_WORDS; 233 | B_write_data_in <= S_AXIS_TDATA; 234 | end 235 | else if (read_input_counter < NUMBER_OF_A_WORDS + 15) 236 | begin //last data will be sent to B_RAM 237 | Last_Layer_Value[7:0] <= S_AXIS_TDATA; //reads first 8 bit data for last layer for w_hid 238 | end 239 | else if (read_input_counter < NUMBER_OF_A_WORDS + 16) 240 | begin //last data will be sent to B_RAM 241 | Last_Layer_Value[15:8] <= S_AXIS_TDATA; //reads last 8 bit data for last layer for w_hid 242 | end 243 | else if (read_input_counter < NUMBER_OF_A_WORDS + 17) 244 | begin //last data will be sent to B_RAM 245 | bias_A <= S_AXIS_TDATA; //read first bias of w_hid at the end of the matrix 246 | end 247 | else if (read_input_counter < NUMBER_OF_A_WORDS + 18) 248 | begin //last data will be sent to B_RAM 249 | bias_B <= S_AXIS_TDATA; //read second bias of w_hid at the end of the matrix 250 | end 251 | else if (read_input_counter < NUMBER_OF_A_WORDS + 19) 252 | begin //last data will be sent to B_RAM 253 | bias_C <= S_AXIS_TDATA; //read first bias of w_out 254 | end 255 | // If we are expecting a variable number of words, we should make use of S_AXIS_TLAST. 256 | // Since the number of words we are expecting is fixed, we simply count and receive 257 | // the expected number (NUMBER_OF_INPUT_WORDS) instead. 258 | if (read_input_counter == NUMBER_OF_INPUT_WORDS -1) 259 | begin 260 | state <= Compute; 261 | read_input_counter <= 0; 262 | Start <= 1; //added this new 263 | S_AXIS_TREADY <= 0; 264 | end 265 | else 266 | begin 267 | read_input_counter <= read_input_counter + 1; 268 | 269 | end 270 | end 271 | end 272 | 273 | Compute: 274 | begin 275 | B_write_en <= 0; 276 | Start <= 1; //to activate matrax_multiply 277 | // Coprocessor function to be implemented (matrix multiply) should be here. Right now, nothing happens here. 278 | // Possible to save a cycle by asserting M_AXIS_TVALID and presenting M_AXIS_TDATA just before going into 279 | // Write_Outputs state. However, need to adjust write_counter limits accordingly 280 | // Alternatively, M_AXIS_TVALID and M_AXIS_TDATA can be asserted combinationally to save a cycle. 281 | if (Done == 1) 282 | begin //once done =1, change state in next clock cycle 283 | state <= Last_Layer_Value; 284 | Start <= 0; 285 | //RES_read_en <= 1; 286 | end 287 | end 288 | 289 | Compute_Last_Layer: 290 | begin 291 | Start_Sigmoid <= 1; //to activate matrax_multiply 292 | // Coprocessor function to be implemented (matrix multiply) should be here. Right now, nothing happens here. 293 | // Possible to save a cycle by asserting M_AXIS_TVALID and presenting M_AXIS_TDATA just before going into 294 | // Write_Outputs state. However, need to adjust write_counter limits accordingly 295 | // Alternatively, M_AXIS_TVALID and M_AXIS_TDATA can be asserted combinationally to save a cycle. 296 | if (End_Sigmoid == 1) 297 | begin //once done =1, change state in next clock cycle 298 | state <= Write_Outputs; 299 | Start_Sigmoid <= 0; 300 | RES_read_en <= 1; 301 | end 302 | end 303 | 304 | Write_Outputs: 305 | begin 306 | M_AXIS_TVALID <= 1; 307 | 308 | // Coprocessor function (adding 1 to sum in each iteration = adding iteration count to sum) happens here (partly) 309 | if (M_AXIS_TREADY == 1) 310 | begin 311 | if (disabled == 1) 312 | begin 313 | write_RES_counter <= write_RES_counter +1; 314 | M_AXIS_TVALID <= 0; 315 | disabled = 0; 316 | end 317 | 318 | 319 | if (write_RES_counter == NUMBER_OF_OUTPUT_WORDS - 1) 320 | begin 321 | state <= Idle; 322 | RES_read_en <= 0; 323 | write_RES_counter <= 0; 324 | M_AXIS_TVALID <= 0; 325 | // M_AXIS_TLAST, though optional in AXIS, is necessary in practice as AXI Stream FIFO and AXI DMA expects it. 326 | end 327 | 328 | else 329 | begin 330 | write_RES_counter <= write_RES_counter + 1; 331 | end 332 | 333 | end 334 | 335 | else if (disabled == 0) 336 | begin 337 | write_RES_counter <= write_RES_counter -1; 338 | disabled <= 1; 339 | end 340 | end 341 | 342 | endcase 343 | end 344 | end 345 | 346 | // Connection to sub-modules / components for assignment 1 347 | 348 | memory_RAM 349 | #( 350 | .width(width), 351 | .depth_bits(A_depth_bits) 352 | ) A_RAM 353 | ( 354 | .clk(ACLK), 355 | .write_en(A_write_en), 356 | .write_address(A_write_address), 357 | .write_data_in(A_write_data_in), 358 | .read_en(A_read_en), 359 | .read_address(A_read_address), 360 | .read_data_out(A_read_data_out) 361 | ); 362 | 363 | 364 | memory_RAM 365 | #( 366 | .width(width), 367 | .depth_bits(B_depth_bits) 368 | ) B_RAM 369 | ( 370 | .clk(ACLK), 371 | .write_en(B_write_en), 372 | .write_address(B_write_address), 373 | .write_data_in(B_write_data_in), 374 | .read_en(B_read_en), 375 | .read_address(B_read_address), 376 | .read_data_out(B_read_data_out) 377 | ); 378 | 379 | // memory_RAM 380 | // #( 381 | // .width(width), 382 | // .depth_bits(C_depth_bits) 383 | // ) C_RAM 384 | // ( 385 | // .clk(ACLK), 386 | // .write_en(C_write_en), 387 | // .write_address(C_write_address), 388 | // .write_data_in(C_write_data_in), 389 | // .read_en(C_read_en), 390 | // .read_address(C_read_address), 391 | // .read_data_out(C_read_data_out) 392 | // ); 393 | 394 | memory_RAM 395 | #( 396 | .width(width), 397 | .depth_bits(RES_depth_bits) 398 | ) RES_RAM 399 | ( 400 | .clk(ACLK), 401 | .write_en(RES_write_en), 402 | .write_address(RES_write_address), 403 | .write_data_in(RES_write_data_in), 404 | .read_en(RES_read_en), 405 | .read_address(RES_read_address), 406 | .read_data_out(RES_read_data_out) 407 | ); 408 | 409 | memory_RAM 410 | #( 411 | .width(width), 412 | .depth_bits(Interm1_depth_bits) 413 | ) Interm1_RAM 414 | ( 415 | .clk(ACLK), 416 | .write_en(Interm1_write_en), 417 | .write_address(Interm1_write_address), 418 | .write_data_in(Interm1_write_data_in), 419 | .read_en(Interm1_read_en), 420 | .read_address(Interm1_read_address), 421 | .read_data_out(Interm1_read_data_out) 422 | ); 423 | 424 | memory_RAM 425 | #( 426 | .width(width), 427 | .depth_bits(Interm2_depth_bits) 428 | ) Interm2_RAM 429 | ( 430 | .clk(ACLK), 431 | .write_en(Interm2_write_en), 432 | .write_address(Interm2_write_address), 433 | .write_data_in(Interm2_write_data_in), 434 | .read_en(Interm2_read_en), 435 | .read_address(Interm2_read_address), 436 | .read_data_out(Interm2_read_data_out) 437 | ); 438 | 439 | 440 | matrix_multiply 441 | #( 442 | .width(width), 443 | .A_depth_bits(A_depth_bits), 444 | .B_depth_bits(B_depth_bits), 445 | .Interm1_depth_bits(Interm1_depth_bits) 446 | ) matrix_multiply_0 447 | ( 448 | .clk(ACLK), 449 | .Start(Start), 450 | .Done(Done), 451 | 452 | .A_read_en(A_read_en), 453 | .A_read_address(A_read_address), 454 | .A_read_data_out(A_read_data_out), 455 | 456 | .B_read_en(B_read_en), 457 | .B_read_address(B_read_address), 458 | .B_read_data_out(B_read_data_out), 459 | 460 | .Interm1_write_en(Interm1_write_en), 461 | .Interm1_write_address(Interm1_write_address), 462 | .Interm1_write_data_in(Interm1_write_data_in), 463 | 464 | .bias_A(bias_A), 465 | .bias_B(bias_B) 466 | ); 467 | 468 | Sigmoid 469 | #( 470 | .width(width), // width is the number of bits per location 471 | .Interm1_depth_bits(Interm1_depth_bits) , // depth is the number of locations (2^number of address bits) 472 | .RES_depth_bits(RES_depth_bits) 473 | ) Sigmoid_0 474 | ( 475 | .clk(ACLK), 476 | .Start_Sigmoid(Start_Sigmoid), 477 | .End_Sigmoid(End_Sigmoid), 478 | 479 | 480 | .Interm1_read_en(Interm1_read_en), // matrix_multiply_0 -> A_RAM. Possibly reg. 481 | .Interm1_read_address(Interm1_read_address), // matrix_multiply_0 -> A_RAM. Possibly reg. 482 | .Interm1_read_data_out(Interm1_read_data_out), // A_RAM -> matrix_multiply_0. 483 | 484 | .RES_write_en(RES_write_en), // matrix_multiply_0 -> RES_RAM. Possibly reg. 485 | .RES_write_address(RES_write_address), // matrix_multiply_0 -> RES_RAM. Possibly reg. 486 | .RES_write_data_in(RES_write_data_in) // matrix_multiply_0 -> RES_RAM. Possibly reg. 487 | 488 | ); 489 | 490 | endmodule 491 | 492 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/tb_myip_v1_0_file.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* 4 | ---------------------------------------------------------------------------------- 5 | -- (c) Rajesh C Panicker, NUS 6 | -- Description : Self-checking testbench for Matrix Multiplication AXI Stream Coprocessor. 7 | -- License terms : 8 | -- You are free to use this code as long as you 9 | -- (i) DO NOT post a modified version of this on any public repository; 10 | -- (ii) use it only for educational purposes; 11 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 12 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 13 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 14 | -- (vi) retain this notice in this file or any files derived from this. 15 | ---------------------------------------------------------------------------------- 16 | */ 17 | 18 | 19 | module tb_myip_v1_0( 20 | 21 | ); 22 | 23 | reg ACLK = 0; // Synchronous clock 24 | reg ARESETN; // System reset, active low 25 | // slave in interface 26 | wire S_AXIS_TREADY; // Ready to accept data in 27 | reg [31 : 0] S_AXIS_TDATA; // Data in 28 | reg S_AXIS_TLAST; // Optional data in qualifier 29 | reg S_AXIS_TVALID; // Data in is valid 30 | // master out interface 31 | wire M_AXIS_TVALID; // Data out is valid 32 | wire [31 : 0] M_AXIS_TDATA; // Data out 33 | wire M_AXIS_TLAST; // Optional data out qualifier 34 | reg M_AXIS_TREADY; // Connected slave device is ready to accept data out 35 | 36 | myip_v1_0 U1 ( 37 | .ACLK(ACLK), 38 | .ARESETN(ARESETN), 39 | .S_AXIS_TREADY(S_AXIS_TREADY), 40 | .S_AXIS_TDATA(S_AXIS_TDATA), 41 | .S_AXIS_TLAST(S_AXIS_TLAST), 42 | .S_AXIS_TVALID(S_AXIS_TVALID), 43 | .M_AXIS_TVALID(M_AXIS_TVALID), 44 | .M_AXIS_TDATA(M_AXIS_TDATA), 45 | .M_AXIS_TLAST(M_AXIS_TLAST), 46 | .M_AXIS_TREADY(M_AXIS_TREADY) 47 | ); 48 | 49 | localparam NUMBER_OF_INPUT_WORDS = 467; // length of an input vector 50 | localparam NUMBER_OF_OUTPUT_WORDS = 128; // length of an input vector 51 | localparam NUMBER_OF_TEST_VECTORS = 1; // number of such test vectors (cases) 52 | localparam width = 8; // width of an input vector 53 | 54 | reg [width-1:0] test_input_memory [0:NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS-1]; // 4 inputs * 2 55 | reg [width-1:0] test_result_expected_memory [0:NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS-1]; // 4 outputs *2 56 | reg [width-1:0] result_memory [0:NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS-1]; // same size as test_result_expected_memory 57 | 58 | integer word_cnt, test_case_cnt; 59 | reg success = 1'b1; 60 | reg M_AXIS_TLAST_prev = 1'b0; 61 | reg DO_ONCE = 0; 62 | 63 | always@(posedge ACLK) 64 | M_AXIS_TLAST_prev <= M_AXIS_TLAST; 65 | 66 | always 67 | #50 ACLK = ~ACLK; 68 | 69 | initial 70 | begin 71 | $display("Loading Memory."); 72 | $readmemh("test_input.mem", test_input_memory); // add the .mem file to the project or specify the complete path 73 | $readmemh("test_result_expected.mem", test_result_expected_memory); // add the .mem file to the project or specify the complete path 74 | #25 // to make inputs and capture from testbench not aligned with clock edges 75 | ARESETN = 1'b0; // apply reset (active low) 76 | S_AXIS_TVALID = 1'b0; // no valid data placed on the S_AXIS_TDATA yet 77 | S_AXIS_TLAST = 1'b0; // not required unless we are dealing with an unknown number of inputs. Ignored by the coprocessor. We will be asserting it correctly anyway 78 | M_AXIS_TREADY = 1'b0; // not ready to receive data from the co-processor yet. 79 | 80 | #100 // hold reset for 100 ns. 81 | ARESETN = 1'b1; // release reset 82 | 83 | 84 | for(test_case_cnt=0; test_case_cnt < NUMBER_OF_TEST_VECTORS; test_case_cnt=test_case_cnt+1) 85 | begin 86 | 87 | //// Input 88 | word_cnt=0; 89 | S_AXIS_TVALID = 1'b1; // data is ready at the input of the coprocessor. 90 | while(word_cnt < NUMBER_OF_INPUT_WORDS) 91 | begin 92 | if(S_AXIS_TREADY) // S_AXIS_TREADY is asserted by the coprocessor in response to S_AXIS_TVALID 93 | begin 94 | S_AXIS_TDATA = test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]; // set the next data ready 95 | if(word_cnt == NUMBER_OF_INPUT_WORDS-1) 96 | S_AXIS_TLAST = 1'b1; 97 | else 98 | S_AXIS_TLAST = 1'b0; 99 | word_cnt=word_cnt+1; 100 | end 101 | #100; // wait for one clock cycle before for co-processor to capture data (if S_AXIS_TREADY was set) 102 | // or before checking S_AXIS_TREADY again (if S_AXIS_TREADY was not set) 103 | end 104 | S_AXIS_TVALID = 1'b0; // we no longer give any data to the co-processor 105 | S_AXIS_TLAST = 1'b0; 106 | 107 | /// Output 108 | // Note: result_memory is not written at a clock edge, which is fine as it is just a testbench construct and not actual hardware 109 | word_cnt = 0; 110 | M_AXIS_TREADY = 1'b1; // we are now ready to receive data 111 | while(M_AXIS_TLAST | ~M_AXIS_TLAST_prev) // receive data until the falling edge of M_AXIS_TLAST 112 | begin 113 | if(word_cnt == 4 && DO_ONCE ==0) 114 | begin 115 | M_AXIS_TREADY = 1'b0; 116 | #300; 117 | M_AXIS_TREADY = 1'b1; 118 | DO_ONCE = 1; 119 | end 120 | if(M_AXIS_TVALID) 121 | begin 122 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = M_AXIS_TDATA; 123 | word_cnt = word_cnt+1; 124 | end 125 | #100; 126 | end // receive loop 127 | M_AXIS_TREADY = 1'b0; // not ready to receive data from the co-processor anymore. 128 | end // next test vector 129 | 130 | // checking correctness of results 131 | for(word_cnt=0; word_cnt < NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS; word_cnt=word_cnt+1) 132 | success = success & (result_memory[word_cnt] == test_result_expected_memory[word_cnt]); 133 | if(success) 134 | $display("Test Passed."); 135 | else 136 | $display("Test Failed."); 137 | 138 | $finish; 139 | end 140 | 141 | endmodule 142 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/test_input.mem: -------------------------------------------------------------------------------- 1 | 2c 2 | 5a 3 | 0 4 | 0 5 | 18 6 | 51 7 | 16 8 | 9f 9 | fa 10 | 8c 11 | b0 12 | 79 13 | b7 14 | 8a 15 | a7 16 | 9e 17 | ac 18 | 86 19 | ac 20 | a1 21 | 76 22 | 82 23 | b2 24 | 88 25 | 78 26 | 87 27 | 79 28 | 56 29 | 22 30 | 70 31 | 8e 32 | 70 33 | a3 34 | 9f 35 | 2b 36 | 3f 37 | 1c 38 | 91 39 | 7e 40 | be 41 | a5 42 | 42 43 | 58 44 | d6 45 | 9d 46 | 8c 47 | cd 48 | ae 49 | 80 50 | b9 51 | cb 52 | aa 53 | 6e 54 | d3 55 | 8a 56 | 7e 57 | 8c 58 | ff 59 | 6e 60 | 88 61 | 85 62 | 9c 63 | 83 64 | 49 65 | 5a 66 | a4 67 | 76 68 | 4b 69 | 79 70 | 6f 71 | 10 72 | 5d 73 | bb 74 | 58 75 | a2 76 | 65 77 | 1b 78 | 1f 79 | 6e 80 | 78 81 | 4d 82 | a6 83 | 65 84 | 2d 85 | b7 86 | b5 87 | 9b 88 | af 89 | 87 90 | d3 91 | b9 92 | 81 93 | c1 94 | 68 95 | 9f 96 | b8 97 | b7 98 | a1 99 | be 100 | b7 101 | 8f 102 | 7c 103 | 8b 104 | 8a 105 | 91 106 | 4f 107 | 71 108 | 73 109 | 6f 110 | a4 111 | 65 112 | 58 113 | d5 114 | d5 115 | 95 116 | 9f 117 | 85 118 | c7 119 | b7 120 | d 121 | 5e 122 | 7f 123 | 92 124 | 84 125 | 96 126 | 59 127 | 67 128 | af 129 | a4 130 | 8b 131 | bb 132 | 93 133 | 80 134 | 2a 135 | 52 136 | 68 137 | 53 138 | a7 139 | 32 140 | 47 141 | 1a 142 | 5a 143 | 6d 144 | 8f 145 | 87 146 | dc 147 | 6a 148 | 45 149 | 5a 150 | 65 151 | b4 152 | 7d 153 | de 154 | 6c 155 | 8f 156 | e1 157 | 7d 158 | 93 159 | c4 160 | c5 161 | 79 162 | 49 163 | 57 164 | 7d 165 | 1d 166 | 8 167 | 57 168 | 43 169 | 64 170 | 88 171 | fe 172 | 77 173 | aa 174 | 8c 175 | 4d 176 | 6e 177 | 88 178 | 65 179 | 89 180 | ba 181 | ae 182 | 7e 183 | a5 184 | 8f 185 | b3 186 | 97 187 | a7 188 | 9c 189 | 93 190 | b6 191 | cf 192 | 83 193 | 69 194 | 82 195 | 65 196 | 7c 197 | 22 198 | 33 199 | c2 200 | 5e 201 | 5a 202 | 5e 203 | 3a 204 | 6c 205 | 55 206 | 74 207 | 19 208 | 18 209 | 0 210 | 3b 211 | 12 212 | 46 213 | 6e 214 | 76 215 | b3 216 | 8a 217 | 32 218 | 23 219 | a5 220 | 78 221 | 48 222 | 7e 223 | 48 224 | 52 225 | 48 226 | 63 227 | 55 228 | 4c 229 | d2 230 | 65 231 | 38 232 | 1b 233 | 55 234 | 55 235 | 6d 236 | 7a 237 | 85 238 | 36 239 | 95 240 | a6 241 | b0 242 | 6f 243 | 87 244 | 73 245 | 62 246 | 8a 247 | b4 248 | 88 249 | 83 250 | ff 251 | 8b 252 | 54 253 | 78 254 | 61 255 | 73 256 | 60 257 | 6e 258 | 80 259 | 2c 260 | b7 261 | b5 262 | b7 263 | 98 264 | 77 265 | ae 266 | 94 267 | 26 268 | 71 269 | 7d 270 | 43 271 | 58 272 | 1a 273 | 44 274 | b4 275 | bc 276 | a9 277 | 89 278 | bc 279 | 7c 280 | 91 281 | 56 282 | 57 283 | 50 284 | 48 285 | 4c 286 | 49 287 | 47 288 | db 289 | e0 290 | 9b 291 | a5 292 | c5 293 | fc 294 | da 295 | 1f 296 | 41 297 | 91 298 | 26 299 | 70 300 | 20 301 | 4e 302 | 15 303 | 86 304 | 30 305 | 53 306 | 5e 307 | 4e 308 | 6f 309 | 6f 310 | 3e 311 | 80 312 | 59 313 | a3 314 | d1 315 | 41 316 | e0 317 | ce 318 | 80 319 | 9b 320 | a7 321 | aa 322 | 96 323 | e7 324 | e1 325 | 8b 326 | ae 327 | 95 328 | ca 329 | d0 330 | 8c 331 | 92 332 | 6a 333 | 7c 334 | c0 335 | 8e 336 | 68 337 | 74 338 | bf 339 | c4 340 | 88 341 | c0 342 | aa 343 | 6c 344 | 2b 345 | 88 346 | 83 347 | 3a 348 | 2c 349 | 32 350 | 76 351 | 27 352 | 4c 353 | 82 354 | 3f 355 | 47 356 | 3e 357 | 27 358 | 67 359 | a6 360 | aa 361 | 73 362 | ec 363 | 83 364 | 4b 365 | 53 366 | 94 367 | ce 368 | 78 369 | 8e 370 | 9c 371 | 66 372 | 49 373 | 29 374 | 96 375 | 3f 376 | 7b 377 | 4e 378 | 33 379 | 9f 380 | 88 381 | 5d 382 | 99 383 | 8c 384 | 95 385 | c6 386 | e 387 | 4d 388 | a0 389 | 43 390 | 44 391 | 48 392 | 38 393 | 25 394 | 46 395 | 83 396 | 35 397 | 48 398 | 2e 399 | 25 400 | e1 401 | ab 402 | 88 403 | 94 404 | 88 405 | a1 406 | bc 407 | 40 408 | b1 409 | 4c 410 | 45 411 | 5c 412 | 5c 413 | 54 414 | 2c 415 | 36 416 | a6 417 | 5d 418 | 9e 419 | 65 420 | 3b 421 | 99 422 | aa 423 | 96 424 | 7d 425 | 98 426 | ab 427 | a6 428 | 56 429 | 9b 430 | 88 431 | 29 432 | 24 433 | 83 434 | 3f 435 | 8a 436 | a0 437 | 68 438 | 77 439 | 95 440 | 7c 441 | 64 442 | 13 443 | 38 444 | 8c 445 | 8b 446 | d9 447 | a1 448 | 33 449 | 19 450 | 1f 451 | 1d 452 | 16 453 | 1 454 | b 455 | 1a 456 | 12 457 | 6 458 | 1a 459 | 1 460 | 1c 461 | 9 462 | 2d 463 | 32 464 | c8 465 | 1a 466 | 6 467 | 50 468 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/test_input_new.mem: -------------------------------------------------------------------------------- 1 | //first input vector 2 | 80 3 | 80 4 | 40 5 | 40 6 | 80 7 | 80 8 | 40 9 | 40 10 | 80 11 | 80 12 | 80 13 | 80 14 | 80 15 | 80 16 | 40 17 | 40 18 | 80 19 | 80 20 | 40 21 | 40 22 | 80 23 | 80 24 | 80 25 | 80 26 | 80 27 | 80 28 | 40 29 | 40 30 | 80 31 | 80 32 | 40 33 | 40 34 | 80 35 | 80 36 | 80 37 | 80 38 | 80 39 | 80 40 | 40 41 | 40 42 | 80 43 | 80 44 | 40 45 | 40 46 | 80 47 | 80 48 | 80 49 | 80 50 | 80 51 | 80 52 | 40 53 | 40 54 | 80 55 | 80 56 | 40 57 | 40 58 | 80 59 | 80 60 | 80 61 | 80 62 | 80 63 | 80 64 | 40 65 | 40 66 | 80 67 | 80 68 | 40 69 | 40 70 | 80 71 | 80 72 | 80 73 | 80 74 | 80 75 | 80 76 | 40 77 | 40 78 | 80 79 | 80 80 | 40 81 | 40 82 | 80 83 | 80 84 | 80 85 | 80 86 | 80 87 | 80 88 | 40 89 | 40 90 | 80 91 | 80 92 | 40 93 | 40 94 | 80 95 | 80 96 | 80 97 | 80 98 | 80 99 | 80 100 | 40 101 | 40 102 | 80 103 | 80 104 | 40 105 | 40 106 | 80 107 | 80 108 | 80 109 | 80 110 | 80 111 | 80 112 | 40 113 | 40 114 | 80 115 | 80 116 | 40 117 | 40 118 | 80 119 | 80 120 | 80 121 | 80 122 | 80 123 | 80 124 | 40 125 | 40 126 | 80 127 | 80 128 | 40 129 | 40 130 | 80 131 | 80 132 | 80 133 | 80 134 | 80 135 | 80 136 | 40 137 | 40 138 | 80 139 | 80 140 | 40 141 | 40 142 | 80 143 | 80 144 | 80 145 | 80 146 | 80 147 | 80 148 | 40 149 | 40 150 | 80 151 | 80 152 | 40 153 | 40 154 | 80 155 | 80 156 | 80 157 | 80 158 | 80 159 | 80 160 | 40 161 | 40 162 | 80 163 | 80 164 | 40 165 | 40 166 | 80 167 | 80 168 | 80 169 | 80 170 | 80 171 | 80 172 | 40 173 | 40 174 | 80 175 | 80 176 | 40 177 | 40 178 | 80 179 | 80 180 | 80 181 | 80 182 | 80 183 | 80 184 | 40 185 | 40 186 | 80 187 | 80 188 | 40 189 | 40 190 | 80 191 | 80 192 | 80 193 | 80 194 | 80 195 | 80 196 | 40 197 | 40 198 | 80 199 | 80 200 | 40 201 | 40 202 | 80 203 | 80 204 | 80 205 | 80 206 | 80 207 | 80 208 | 40 209 | 40 210 | 80 211 | 80 212 | 40 213 | 40 214 | 80 215 | 80 216 | 80 217 | 80 218 | 80 219 | 80 220 | 40 221 | 40 222 | 80 223 | 80 224 | 40 225 | 40 226 | 80 227 | 80 228 | 80 229 | 80 230 | 80 231 | 80 232 | 40 233 | 40 234 | 80 235 | 80 236 | 40 237 | 40 238 | 80 239 | 80 240 | 80 241 | 80 242 | 80 243 | 80 244 | 40 245 | 40 246 | 80 247 | 80 248 | 40 249 | 40 250 | 80 251 | 80 252 | 80 253 | 80 254 | 80 255 | 80 256 | 40 257 | 40 258 | 80 259 | 80 260 | 40 261 | 40 262 | 80 263 | 80 264 | 80 265 | 80 266 | 80 267 | 80 268 | 40 269 | 40 270 | 80 271 | 80 272 | 40 273 | 40 274 | 80 275 | 80 276 | 80 277 | 80 278 | 80 279 | 80 280 | 40 281 | 40 282 | 80 283 | 80 284 | 40 285 | 40 286 | 80 287 | 80 288 | 80 289 | 80 290 | 80 291 | 80 292 | 40 293 | 40 294 | 80 295 | 80 296 | 40 297 | 40 298 | 80 299 | 80 300 | 80 301 | 80 302 | 80 303 | 80 304 | 40 305 | 40 306 | 80 307 | 80 308 | 40 309 | 40 310 | 80 311 | 80 312 | 80 313 | 80 314 | 80 315 | 80 316 | 40 317 | 40 318 | 80 319 | 80 320 | 40 321 | 40 322 | 80 323 | 80 324 | 80 325 | 80 326 | 80 327 | 80 328 | 40 329 | 40 330 | 80 331 | 80 332 | 40 333 | 40 334 | 80 335 | 80 336 | 80 337 | 80 338 | 80 339 | 80 340 | 40 341 | 40 342 | 80 343 | 80 344 | 40 345 | 40 346 | 80 347 | 80 348 | 80 349 | 80 350 | 80 351 | 80 352 | 40 353 | 40 354 | 80 355 | 80 356 | 40 357 | 40 358 | 80 359 | 80 360 | 80 361 | 80 362 | 80 363 | 80 364 | 40 365 | 40 366 | 80 367 | 80 368 | 40 369 | 40 370 | 80 371 | 80 372 | 80 373 | 80 374 | 80 375 | 80 376 | 40 377 | 40 378 | 80 379 | 80 380 | 40 381 | 40 382 | 80 383 | 80 384 | 80 385 | 80 386 | 80 387 | 80 388 | 40 389 | 40 390 | 80 391 | 80 392 | 40 393 | 40 394 | 80 395 | 80 396 | 80 397 | 80 398 | 80 399 | 80 400 | 80 401 | 40 402 | 40 403 | 80 404 | 80 405 | 40 406 | 40 407 | 80 408 | 80 409 | 80 410 | 80 411 | 80 412 | 80 413 | 80 414 | 40 415 | 40 416 | 80 417 | 80 418 | 40 419 | 40 420 | 80 421 | 80 422 | 80 423 | 80 424 | 80 425 | 80 426 | 80 427 | 40 428 | 40 429 | 80 430 | 80 431 | 40 432 | 40 433 | 80 434 | 80 435 | 80 436 | 80 437 | 80 438 | 80 439 | 80 440 | 40 441 | 40 442 | 80 443 | 80 444 | 40 445 | 40 446 | 80 447 | 80 448 | 80 449 | 80 450 | 80 451 | 80 452 | 80 453 | 40 454 | 40 455 | 80 456 | 80 457 | 40 458 | 40 459 | 80 460 | 80 461 | 80 462 | 80 463 | 80 464 | 80 465 | 80 466 | 40 467 | 40 468 | 80 469 | 80 470 | 40 471 | 40 472 | 80 473 | 80 474 | 80 475 | 80 476 | 80 477 | 80 478 | 80 479 | 40 480 | 40 481 | 80 482 | 80 483 | 40 484 | 40 485 | 80 486 | 80 487 | 80 488 | 80 489 | 80 490 | 80 491 | 80 492 | 40 493 | 40 494 | 80 495 | 80 496 | 40 497 | 40 498 | 80 499 | 80 500 | 80 501 | 80 502 | 80 503 | 80 504 | 80 505 | 40 506 | 40 507 | 80 508 | 80 509 | 40 510 | 40 511 | 80 512 | 80 513 | 80 514 | 80 515 | 80 516 | 40 517 | 40 518 | 80 519 | 80 520 | 40 521 | 40 522 | //second input vector 523 | 80 524 | 80 525 | 40 526 | 40 527 | 80 528 | 80 529 | 40 530 | 40 531 | 80 532 | 80 533 | 80 534 | 80 535 | 80 536 | 80 537 | 40 538 | 40 539 | 80 540 | 80 541 | 40 542 | 40 543 | 80 544 | 80 545 | 80 546 | 80 547 | 80 548 | 80 549 | 40 550 | 40 551 | 80 552 | 80 553 | 40 554 | 40 555 | 80 556 | 80 557 | 80 558 | 80 559 | 80 560 | 80 561 | 40 562 | 40 563 | 80 564 | 80 565 | 40 566 | 40 567 | 80 568 | 80 569 | 80 570 | 80 571 | 80 572 | 80 573 | 40 574 | 40 575 | 80 576 | 80 577 | 40 578 | 40 579 | 80 580 | 80 581 | 80 582 | 80 583 | 80 584 | 80 585 | 40 586 | 40 587 | 80 588 | 80 589 | 40 590 | 40 591 | 80 592 | 80 593 | 80 594 | 80 595 | 80 596 | 80 597 | 40 598 | 40 599 | 80 600 | 80 601 | 40 602 | 40 603 | 80 604 | 80 605 | 80 606 | 80 607 | 80 608 | 80 609 | 40 610 | 40 611 | 80 612 | 80 613 | 40 614 | 40 615 | 80 616 | 80 617 | 80 618 | 80 619 | 80 620 | 80 621 | 40 622 | 40 623 | 80 624 | 80 625 | 40 626 | 40 627 | 80 628 | 80 629 | 80 630 | 80 631 | 80 632 | 80 633 | 40 634 | 40 635 | 80 636 | 80 637 | 40 638 | 40 639 | 80 640 | 80 641 | 80 642 | 80 643 | 80 644 | 80 645 | 40 646 | 40 647 | 80 648 | 80 649 | 40 650 | 40 651 | 80 652 | 80 653 | 80 654 | 80 655 | 80 656 | 80 657 | 40 658 | 40 659 | 80 660 | 80 661 | 40 662 | 40 663 | 80 664 | 80 665 | 80 666 | 80 667 | 80 668 | 80 669 | 40 670 | 40 671 | 80 672 | 80 673 | 40 674 | 40 675 | 80 676 | 80 677 | 80 678 | 80 679 | 80 680 | 80 681 | 40 682 | 40 683 | 80 684 | 80 685 | 40 686 | 40 687 | 80 688 | 80 689 | 80 690 | 80 691 | 80 692 | 80 693 | 40 694 | 40 695 | 80 696 | 80 697 | 40 698 | 40 699 | 80 700 | 80 701 | 80 702 | 80 703 | 80 704 | 80 705 | 40 706 | 40 707 | 80 708 | 80 709 | 40 710 | 40 711 | 80 712 | 80 713 | 80 714 | 80 715 | 80 716 | 80 717 | 40 718 | 40 719 | 80 720 | 80 721 | 40 722 | 40 723 | 80 724 | 80 725 | 80 726 | 80 727 | 80 728 | 80 729 | 40 730 | 40 731 | 80 732 | 80 733 | 40 734 | 40 735 | 80 736 | 80 737 | 80 738 | 80 739 | 80 740 | 80 741 | 40 742 | 40 743 | 80 744 | 80 745 | 40 746 | 40 747 | 80 748 | 80 749 | 80 750 | 80 751 | 80 752 | 80 753 | 40 754 | 40 755 | 80 756 | 80 757 | 40 758 | 40 759 | 80 760 | 80 761 | 80 762 | 80 763 | 80 764 | 80 765 | 40 766 | 40 767 | 80 768 | 80 769 | 40 770 | 40 771 | 80 772 | 80 773 | 80 774 | 80 775 | 80 776 | 80 777 | 40 778 | 40 779 | 80 780 | 80 781 | 40 782 | 40 783 | 80 784 | 80 785 | 80 786 | 80 787 | 80 788 | 80 789 | 40 790 | 40 791 | 80 792 | 80 793 | 40 794 | 40 795 | 80 796 | 80 797 | 80 798 | 80 799 | 80 800 | 80 801 | 40 802 | 40 803 | 80 804 | 80 805 | 40 806 | 40 807 | 80 808 | 80 809 | 80 810 | 80 811 | 80 812 | 80 813 | 40 814 | 40 815 | 80 816 | 80 817 | 40 818 | 40 819 | 80 820 | 80 821 | 80 822 | 80 823 | 80 824 | 80 825 | 40 826 | 40 827 | 80 828 | 80 829 | 40 830 | 40 831 | 80 832 | 80 833 | 80 834 | 80 835 | 80 836 | 80 837 | 40 838 | 40 839 | 80 840 | 80 841 | 40 842 | 40 843 | 80 844 | 80 845 | 80 846 | 80 847 | 80 848 | 80 849 | 40 850 | 40 851 | 80 852 | 80 853 | 40 854 | 40 855 | 80 856 | 80 857 | 80 858 | 80 859 | 80 860 | 80 861 | 40 862 | 40 863 | 80 864 | 80 865 | 40 866 | 40 867 | 80 868 | 80 869 | 80 870 | 80 871 | 80 872 | 80 873 | 40 874 | 40 875 | 80 876 | 80 877 | 40 878 | 40 879 | 80 880 | 80 881 | 80 882 | 80 883 | 80 884 | 80 885 | 40 886 | 40 887 | 80 888 | 80 889 | 40 890 | 40 891 | 80 892 | 80 893 | 80 894 | 80 895 | 80 896 | 80 897 | 40 898 | 40 899 | 80 900 | 80 901 | 40 902 | 40 903 | 80 904 | 80 905 | 80 906 | 80 907 | 80 908 | 80 909 | 40 910 | 40 911 | 80 912 | 80 913 | 40 914 | 40 915 | 80 916 | 80 917 | 80 918 | 80 919 | 80 920 | 80 921 | 80 922 | 40 923 | 40 924 | 80 925 | 80 926 | 40 927 | 40 928 | 80 929 | 80 930 | 80 931 | 80 932 | 80 933 | 80 934 | 80 935 | 40 936 | 40 937 | 80 938 | 80 939 | 40 940 | 40 941 | 80 942 | 80 943 | 80 944 | 80 945 | 80 946 | 80 947 | 80 948 | 40 949 | 40 950 | 80 951 | 80 952 | 40 953 | 40 954 | 80 955 | 80 956 | 80 957 | 80 958 | 80 959 | 80 960 | 80 961 | 40 962 | 40 963 | 80 964 | 80 965 | 40 966 | 40 967 | 80 968 | 80 969 | 80 970 | 80 971 | 80 972 | 80 973 | 80 974 | 40 975 | 40 976 | 80 977 | 80 978 | 40 979 | 40 980 | 80 981 | 80 982 | 80 983 | 80 984 | 80 985 | 80 986 | 80 987 | 40 988 | 40 989 | 80 990 | 80 991 | 40 992 | 40 993 | 80 994 | 80 995 | 80 996 | 80 997 | 80 998 | 80 999 | 80 1000 | 40 1001 | 40 1002 | 80 1003 | 80 1004 | 40 1005 | 40 1006 | 80 1007 | 80 1008 | 80 1009 | 80 1010 | 80 1011 | 80 1012 | 80 1013 | 40 1014 | 40 1015 | 80 1016 | 80 1017 | 40 1018 | 40 1019 | 80 1020 | 80 1021 | 80 1022 | 80 1023 | 80 1024 | 80 1025 | 80 1026 | 40 1027 | 40 1028 | 80 1029 | 80 1030 | 40 1031 | 40 1032 | 80 1033 | 80 1034 | 80 1035 | 30 1036 | 70 1037 | 50 1038 | 90 1039 | 10 1040 | 20 1041 | 50 1042 | 40 1043 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/test_result_expected.mem: -------------------------------------------------------------------------------- 1 | 21 2 | 7b 3 | 68 4 | 57 5 | 3e 6 | 3b 7 | 66 8 | 6e 9 | 6c 10 | 49 11 | 39 12 | 36 13 | 7d 14 | 68 15 | 6b 16 | 42 17 | 82 18 | 3f 19 | 61 20 | 32 21 | 43 22 | 4b 23 | 6c 24 | 34 25 | 5e 26 | 53 27 | 6b 28 | 65 29 | 39 30 | 32 31 | 34 32 | 3f 33 | 36 34 | 33 35 | 5e 36 | 5b 37 | 3f 38 | 77 39 | 35 40 | 71 41 | 34 42 | 90 43 | 30 44 | 35 45 | 40 46 | 78 47 | 8b 48 | 53 49 | 69 50 | 3e 51 | 30 52 | 56 53 | 5b 54 | 33 55 | 62 56 | 33 57 | 2d 58 | 78 59 | 3f 60 | 38 61 | 6b 62 | 43 63 | 52 64 | 39 65 | 12 66 | 3f 67 | 43 68 | 31 69 | 27 70 | 2e 71 | 43 72 | 4b 73 | 3a 74 | 2c 75 | 26 76 | 24 77 | 4f 78 | 44 79 | 43 80 | 2d 81 | 50 82 | 28 83 | 40 84 | 26 85 | 2c 86 | 2e 87 | 43 88 | 1d 89 | 3d 90 | 3a 91 | 49 92 | 3a 93 | 25 94 | 1c 95 | 25 96 | 27 97 | 29 98 | 20 99 | 38 100 | 3f 101 | 25 102 | 46 103 | 20 104 | 4b 105 | 20 106 | 66 107 | 24 108 | 22 109 | 2f 110 | 4a 111 | 5a 112 | 38 113 | 44 114 | 25 115 | 1c 116 | 3c 117 | 39 118 | 24 119 | 44 120 | 20 121 | 1c 122 | 4e 123 | 23 124 | 29 125 | 48 126 | 22 127 | 32 128 | 2c 129 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/test_result_expected_new.mem: -------------------------------------------------------------------------------- 1 | //first output vector 2 | 40 3 | 00 4 | a0 5 | 40 6 | 00 7 | a0 8 | 40 9 | 00 10 | a0 11 | 40 12 | 00 13 | a0 14 | 40 15 | 00 16 | a0 17 | 40 18 | 00 19 | a0 20 | 40 21 | 00 22 | a0 23 | 40 24 | 00 25 | a0 26 | 40 27 | e0 28 | 60 29 | e0 30 | 80 31 | e0 32 | 80 33 | 30 34 | a0 35 | 60 36 | 00 37 | a0 38 | 60 39 | 00 40 | a0 41 | 60 42 | 00 43 | a0 44 | 60 45 | 00 46 | a0 47 | 60 48 | 00 49 | a0 50 | 60 51 | 00 52 | a0 53 | 60 54 | 00 55 | a0 56 | 60 57 | 00 58 | a0 59 | 40 60 | c0 61 | 40 62 | e0 63 | 40 64 | e0 65 | 90 66 | //second output vector 67 | cc 68 | c0 69 | 90 70 | 4c 71 | 40 72 | 10 73 | cc 74 | c0 75 | 90 76 | 4c 77 | 40 78 | 10 79 | cc 80 | c0 81 | 90 82 | 4c 83 | 40 84 | 10 85 | cc 86 | c0 87 | 90 88 | 4c 89 | 40 90 | 10 91 | cc 92 | d4 93 | ec 94 | cc 95 | 9c 96 | b4 97 | b8 98 | 8c 99 | 44 100 | 38 101 | 08 102 | c4 103 | b8 104 | 88 105 | 44 106 | 38 107 | 08 108 | c4 109 | b8 110 | 88 111 | 44 112 | 38 113 | 08 114 | c4 115 | b8 116 | 88 117 | 44 118 | 38 119 | 08 120 | c4 121 | b8 122 | 88 123 | 44 124 | 4c 125 | 64 126 | 44 127 | 14 128 | 2c 129 | 30 130 | 04 -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/testbench_HDL.c: -------------------------------------------------------------------------------- 1 | /* 2 | ---------------------------------------------------------------------------------- 3 | -- (c) Rajesh C Panicker, NUS, 4 | -- Modified from XLlFifo_polling_example.c, (c) Xilinx Inc 5 | -- Description : Self-checking sample program for AXI Stream Coprocessor interfaced using AXI Stream FIFO. 6 | -- License terms : 7 | -- You are free to use this code as long as you 8 | -- (i) DO NOT post a modified version of this on any public repository; 9 | -- (ii) use it only for educational purposes; 10 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 11 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 12 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 13 | -- (vi) retain this notice in this file or any files derived from this. 14 | ---------------------------------------------------------------------------------- 15 | */ 16 | 17 | /***************************** Include Files *********************************/ 18 | #include "xparameters.h" 19 | #include "xil_exception.h" 20 | #include "xstreamer.h" 21 | #include "xil_cache.h" 22 | #include "xllfifo.h" 23 | #include "xstatus.h" 24 | #include 25 | #include "xil_printf.h" 26 | #include "xtmrctr.h" 27 | /************************** Constant Definitions *****************************/ 28 | 29 | /* 30 | * The following constants map to the XPAR parameters created in the 31 | * xparameters.h file. They are only defined here such that a user can easily 32 | * change all the needed parameters in one place. 33 | */ 34 | #define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID 35 | 36 | 37 | /* 38 | * This example only uses the 1st of the 2 timer counters contained in a 39 | * single timer counter hardware device 40 | */ 41 | #define TIMER_COUNTER_0 0 42 | 43 | /************************** Variable Definitions *****************************/ 44 | 45 | XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */ 46 | 47 | /***************** Macros *********************/ 48 | #define NUMBER_OF_INPUT_WORDS 467 // length of an input vector 49 | #define NUMBER_OF_OUTPUT_WORDS 64 // length of an input vector 50 | #define NUMBER_OF_TEST_VECTORS 1 // number of such test vectors (cases) 51 | 52 | #define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID 53 | 54 | #define TIMEOUT_VALUE 1<<20; // timeout for reception 55 | 56 | /************************** Variable Definitions *****************************/ 57 | u16 DeviceId = FIFO_DEV_ID; 58 | XLlFifo FifoInstance; // Device instance 59 | XLlFifo *InstancePtr = &FifoInstance; // Device pointer 60 | 61 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS]; 62 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = {0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05}; 63 | int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = { 64 | 44, 65 | 159, 66 | 167, 67 | 130, 68 | 34, 69 | 63, 70 | 88, 71 | 185, 72 | 140, 73 | 73, 74 | 16, 75 | 31, 76 | 183, 77 | 129, 78 | 190, 79 | 79, 80 | 213, 81 | 13, 82 | 103, 83 | 42, 84 | 26, 85 | 69, 86 | 143, 87 | 73, 88 | 100, 89 | 110, 90 | 165, 91 | 182, 92 | 34, 93 | 108, 94 | 18, 95 | 35, 96 | 72, 97 | 27, 98 | 149, 99 | 138, 100 | 120, 101 | 183, 102 | 38, 103 | 180, 104 | 86, 105 | 219, 106 | 31, 107 | 21, 108 | 111, 109 | 224, 110 | 231, 111 | 140, 112 | 116, 113 | 43, 114 | 39, 115 | 103, 116 | 83, 117 | 73, 118 | 159, 119 | 14, 120 | 37, 121 | 225, 122 | 64, 123 | 44, 124 | 153, 125 | 86, 126 | 138, 127 | 19, 128 | 90, 129 | 250, 130 | 158, 131 | 178, 132 | 112, 133 | 28, 134 | 214, 135 | 203, 136 | 255, 137 | 90, 138 | 93, 139 | 110, 140 | 181, 141 | 193, 142 | 183, 143 | 113, 144 | 213, 145 | 94, 146 | 175, 147 | 82, 148 | 90, 149 | 90, 150 | 225, 151 | 87, 152 | 136, 153 | 136, 154 | 143, 155 | 207, 156 | 51, 157 | 85, 158 | 70, 159 | 165, 160 | 99, 161 | 85, 162 | 166, 163 | 180, 164 | 97, 165 | 181, 166 | 113, 167 | 188, 168 | 87, 169 | 224, 170 | 65, 171 | 134, 172 | 62, 173 | 206, 174 | 225, 175 | 146, 176 | 191, 177 | 136, 178 | 76, 179 | 166, 180 | 148, 181 | 41, 182 | 136, 183 | 77, 184 | 70, 185 | 171, 186 | 177, 187 | 54, 188 | 170, 189 | 155, 190 | 160, 191 | 0, 192 | 0, 193 | 140, 194 | 172, 195 | 136, 196 | 142, 197 | 145, 198 | 157, 199 | 170, 200 | 110, 201 | 164, 202 | 187, 203 | 120, 204 | 155, 205 | 104, 206 | 143, 207 | 115, 208 | 149, 209 | 127, 210 | 164, 211 | 104, 212 | 109, 213 | 101, 214 | 125, 215 | 125, 216 | 254, 217 | 101, 218 | 179, 219 | 131, 220 | 194, 221 | 116, 222 | 110, 223 | 120, 224 | 85, 225 | 85, 226 | 176, 227 | 136, 228 | 115, 229 | 183, 230 | 125, 231 | 169, 232 | 80, 233 | 155, 234 | 145, 235 | 48, 236 | 128, 237 | 128, 238 | 139, 239 | 106, 240 | 196, 241 | 131, 242 | 130, 243 | 170, 244 | 206, 245 | 150, 246 | 93, 247 | 160, 248 | 131, 249 | 136, 250 | 76, 251 | 166, 252 | 150, 253 | 136, 254 | 104, 255 | 140, 256 | 0, 257 | 176, 258 | 134, 259 | 120, 260 | 112, 261 | 126, 262 | 140, 263 | 110, 264 | 136, 265 | 118, 266 | 88, 267 | 77, 268 | 175, 269 | 159, 270 | 124, 271 | 111, 272 | 159, 273 | 146, 274 | 139, 275 | 83, 276 | 143, 277 | 180, 278 | 147, 279 | 29, 280 | 119, 281 | 137, 282 | 151, 283 | 105, 284 | 94, 285 | 25, 286 | 118, 287 | 72, 288 | 76, 289 | 109, 290 | 111, 291 | 131, 292 | 96, 293 | 152, 294 | 67, 295 | 137, 296 | 72, 297 | 165, 298 | 38, 299 | 83, 300 | 89, 301 | 155, 302 | 174, 303 | 124, 304 | 136, 305 | 58, 306 | 63, 307 | 115, 308 | 120, 309 | 63, 310 | 153, 311 | 67, 312 | 53, 313 | 148, 314 | 69, 315 | 93, 316 | 125, 317 | 41, 318 | 119, 319 | 139, 320 | 24, 321 | 121, 322 | 172, 323 | 135, 324 | 163, 325 | 190, 326 | 205, 327 | 211, 328 | 133, 329 | 75, 330 | 162, 331 | 166, 332 | 135, 333 | 184, 334 | 139, 335 | 164, 336 | 133, 337 | 132, 338 | 187, 339 | 167, 340 | 135, 341 | 125, 342 | 196, 343 | 8, 344 | 170, 345 | 186, 346 | 167, 347 | 130, 348 | 90, 349 | 24, 350 | 179, 351 | 126, 352 | 210, 353 | 122, 354 | 135, 355 | 255, 356 | 110, 357 | 119, 358 | 88, 359 | 188, 360 | 76, 361 | 197, 362 | 112, 363 | 94, 364 | 163, 365 | 167, 366 | 149, 367 | 192, 368 | 192, 369 | 44, 370 | 71, 371 | 236, 372 | 142, 373 | 123, 374 | 140, 375 | 68, 376 | 72, 377 | 136, 378 | 92, 379 | 158, 380 | 152, 381 | 36, 382 | 149, 383 | 217, 384 | 81, 385 | 183, 386 | 161, 387 | 121, 388 | 159, 389 | 165, 390 | 174, 391 | 138, 392 | 156, 393 | 121, 394 | 101, 395 | 101, 396 | 211, 397 | 183, 398 | 138, 399 | 101, 400 | 199, 401 | 150, 402 | 147, 403 | 50, 404 | 220, 405 | 222, 406 | 197, 407 | 87, 408 | 140, 409 | 174, 410 | 156, 411 | 101, 412 | 94, 413 | 0, 414 | 138, 415 | 72, 416 | 101, 417 | 133, 418 | 115, 419 | 139, 420 | 128, 421 | 174, 422 | 26, 423 | 124, 424 | 73, 425 | 252, 426 | 32, 427 | 78, 428 | 209, 429 | 170, 430 | 202, 431 | 142, 432 | 170, 433 | 50, 434 | 62, 435 | 131, 436 | 156, 437 | 78, 438 | 149, 439 | 72, 440 | 46, 441 | 161, 442 | 92, 443 | 101, 444 | 171, 445 | 131, 446 | 124, 447 | 161, 448 | 22, 449 | 138, 450 | 118, 451 | 86, 452 | 43, 453 | 66, 454 | 128, 455 | 126, 456 | 131, 457 | 111, 458 | 27, 459 | 45, 460 | 185, 461 | 161, 462 | 145, 463 | 88, 464 | 183, 465 | 89, 466 | 128, 467 | 71, 468 | 106, 469 | 108, 470 | 121, 471 | 67, 472 | 77, 473 | 126, 474 | 147, 475 | 124, 476 | 58, 477 | 59, 478 | 50, 479 | 82, 480 | 56, 481 | 54, 482 | 98, 483 | 84, 484 | 44, 485 | 148, 486 | 68, 487 | 145, 488 | 71, 489 | 218, 490 | 78, 491 | 111, 492 | 65, 493 | 150, 494 | 208, 495 | 104, 496 | 108, 497 | 118, 498 | 39, 499 | 75, 500 | 102, 501 | 51, 502 | 198, 503 | 56, 504 | 37, 505 | 188, 506 | 84, 507 | 59, 508 | 166, 509 | 63, 510 | 100, 511 | 51, 512 | 25, 513 | 31, 514 | 29, 515 | 22, 516 | 1, 517 | 11, 518 | 26, 519 | 18, 520 | 6, 521 | 26, 522 | 1, 523 | 28, 524 | 9, 525 | 45, 526 | 50, 527 | 200, 528 | 26, 529 | 6, 530 | 80}; 531 | 532 | int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS] = {0, 533 | 1, 534 | 1, 535 | 1, 536 | 0, 537 | 0, 538 | 1, 539 | 1, 540 | 1, 541 | 0, 542 | 0, 543 | 0, 544 | 1, 545 | 1, 546 | 1, 547 | 0, 548 | 1, 549 | 0, 550 | 1, 551 | 0, 552 | 0, 553 | 1, 554 | 1, 555 | 0, 556 | 1, 557 | 1, 558 | 1, 559 | 1, 560 | 0, 561 | 0, 562 | 0, 563 | 0, 564 | 0, 565 | 0, 566 | 1, 567 | 1, 568 | 0, 569 | 1, 570 | 0, 571 | 1, 572 | 0, 573 | 1, 574 | 0, 575 | 0, 576 | 1, 577 | 1, 578 | 1, 579 | 1, 580 | 1, 581 | 0, 582 | 0, 583 | 1, 584 | 1, 585 | 0, 586 | 1, 587 | 0, 588 | 0, 589 | 1, 590 | 0, 591 | 0, 592 | 1, 593 | 0, 594 | 1, 595 | 0}; 596 | 597 | //int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS];// 4 outputs *2 598 | int result_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS]; // same size as test_result_expected_memory 599 | 600 | /***************************************************************************** 601 | * Main function 602 | ******************************************************************************/ 603 | int main() 604 | { 605 | int Status = XST_SUCCESS; 606 | int word_cnt, test_case_cnt = 0; 607 | int success; 608 | // Timer initialization 609 | u8 TmrCtrNumber = TIMER_COUNTER_0; 610 | u16 DeviceId = TMRCTR_DEVICE_ID; 611 | int Status_Timer; 612 | u32 Timer1; 613 | u32 Timer2; 614 | XTmrCtr TimerCounter; 615 | XTmrCtr *TmrCtrInstancePtr = &TimerCounter; 616 | 617 | /* 618 | * Initialize the timer counter so that it's ready to use, 619 | * specify the device ID that is generated in xparameters.h 620 | */ 621 | Status_Timer = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId); 622 | if (Status_Timer != XST_SUCCESS) { 623 | return XST_FAILURE; 624 | } 625 | 626 | 627 | /************************** Initializations *****************************/ 628 | XLlFifo_Config *Config; 629 | 630 | /* Initialize the Device Configuration Interface driver */ 631 | Config = XLlFfio_LookupConfig(DeviceId); 632 | if (!Config) { 633 | xil_printf("No config found for %d\r\n", DeviceId); 634 | return XST_FAILURE; 635 | } 636 | 637 | Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress); 638 | if (Status != XST_SUCCESS) { 639 | xil_printf("Initialization failed\r\n"); 640 | return XST_FAILURE; 641 | } 642 | 643 | /* Check for the Reset value */ 644 | Status = XLlFifo_Status(InstancePtr); 645 | XLlFifo_IntClear(InstancePtr,0xffffffff); 646 | Status = XLlFifo_Status(InstancePtr); 647 | if(Status != 0x0) { 648 | xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t. Expected : 0x0\r\n", 649 | XLlFifo_Status(InstancePtr)); 650 | return XST_FAILURE; 651 | } 652 | 653 | // for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 654 | // 655 | // for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 656 | // scanf("%d", &test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]); 657 | // } 658 | // 659 | // } 660 | 661 | /************** Run a software version of the hardware function to validate results ************/ 662 | // instead of hard-coding the results in test_result_expected_memory 663 | 664 | // int sum; 665 | // for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 666 | // sum = 0; 667 | // for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 668 | // sum +=test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]; 669 | // } 670 | // for (word_cnt=0; word_cnt < NUMBER_OF_OUTPUT_WORDS; word_cnt++) { 671 | // test_result_expected_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = sum + word_cnt; 672 | // } 673 | // } 674 | // 675 | // 676 | /* 677 | * Perform a self-test to ensure that the hardware was built 678 | * correctly, use the 1st timer in the device (0) 679 | */ 680 | Status_Timer = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber); 681 | if (Status_Timer != XST_SUCCESS) { 682 | return XST_FAILURE; 683 | } 684 | 685 | 686 | /* 687 | * Enable the Autoreload mode of the timer counters. 688 | */ 689 | XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, 690 | XTC_AUTO_RELOAD_OPTION); 691 | 692 | /* 693 | * Get a snapshot of the timer counter value before it's started 694 | * to compare against later 695 | */ 696 | Timer1 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber); 697 | /* 698 | * Start the timer counter such that it's incrementing by default 699 | */ 700 | XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber); 701 | 702 | for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 703 | 704 | /******************** Input to Coprocessor : Transmit the Data Stream ***********************/ 705 | xil_printf(" Transmitting Data for test case %d ... \r\n", test_case_cnt); 706 | 707 | /* Writing into the FIFO Transmit Port Buffer */ 708 | for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 709 | if( XLlFifo_iTxVacancy(InstancePtr) ){ 710 | XLlFifo_TxPutWord(InstancePtr, test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]); 711 | } 712 | } 713 | 714 | /* Start Transmission by writing transmission length (number of bytes = 4* number of words) into the TLR */ 715 | XLlFifo_iTxSetLen(InstancePtr, NUMBER_OF_INPUT_WORDS * 4); 716 | 717 | /* Check for Transmission completion */ 718 | while( !(XLlFifo_IsTxDone(InstancePtr)) ){ 719 | 720 | } 721 | 722 | /* Transmission Complete */ 723 | 724 | /******************** Output from Coprocessor : Receive the Data Stream ***********************/ 725 | 726 | xil_printf(" Receiving data for test case %d ... \r\n", test_case_cnt); 727 | 728 | int timeout_count = TIMEOUT_VALUE; 729 | // wait for coprocessor to send data, subject to a timeout 730 | while(!XLlFifo_iRxOccupancy(InstancePtr)) { 731 | timeout_count--; 732 | if (timeout_count == 0) 733 | { 734 | xil_printf("Timeout while waiting for data ... \r\n"); 735 | return XST_FAILURE; 736 | } 737 | } 738 | 739 | // we are expecting only one packet of data per test case. one packet = sequence of data until TLAST 740 | // if more packets are expected from the coprocessor, the part below should be done in a loop. 741 | u32 ReceiveLength = XLlFifo_iRxGetLen(InstancePtr)/4; 742 | for (word_cnt=0; word_cnt < ReceiveLength; word_cnt++) { 743 | // read one word at a time 744 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = XLlFifo_RxGetWord(InstancePtr); 745 | xil_printf("%d ", result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS]); 746 | } 747 | 748 | Status = XLlFifo_IsRxDone(InstancePtr); 749 | if(Status != TRUE){ 750 | xil_printf("Failing in receive complete ... \r\n"); 751 | return XST_FAILURE; 752 | } 753 | /* Reception Complete */ 754 | } 755 | Timer2 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber); 756 | 757 | /* 758 | * Disable the Autoreload mode of the timer counters. 759 | */ 760 | XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, 0); 761 | 762 | /************************** Checking correctness of results *****************************/ 763 | 764 | success = 1; 765 | 766 | /* Compare the data send with the data received */ 767 | xil_printf(" Comparing data ...\r\n"); 768 | for(word_cnt=0; word_cnt < NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS; word_cnt++){ 769 | xil_printf("%d %d\n", result_memory[word_cnt], test_result_expected_memory[word_cnt]); 770 | success = success & (result_memory[word_cnt] == test_result_expected_memory[word_cnt]); 771 | } 772 | 773 | // if (success != 1){ 774 | // xil_printf("Test Failed\r\n"); 775 | // return XST_FAILURE; 776 | // } 777 | // 778 | // xil_printf("Test Success\r\n"); 779 | printf("Time taken for Transmission and Receiving: %lu, %lu \n", Timer1, Timer2); 780 | 781 | return XST_SUCCESS; 782 | } 783 | 784 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/w_hid.mem: -------------------------------------------------------------------------------- 1 | 1a 2 | 19 3 | 1f 4 | 1d 5 | 16 6 | 1 7 | b 8 | 1a 9 | 6 10 | 12 11 | 6 12 | 1a 13 | 1 14 | 1c 15 | 9 16 | 2d 17 | -------------------------------------------------------------------------------- /Hardware Description Language (HDL) Implementation/w_out.mem: -------------------------------------------------------------------------------- 1 | 50 2 | 32 3 | c8 4 | -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/About: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/EE4218_MLP_Neural_Network.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 104 | 105 | 106 | 107 | 108 | 110 | 111 | 112 | 113 | 114 | 125 | 126 | 127 | 128 | 129 | 131 | 132 | 133 | 134 | 137 | 138 | 139 | 140 | 143 | 144 | 145 | 146 | 149 | 150 | 151 | 152 | 155 | 156 | 157 | 158 | 161 | 162 | 163 | 164 | 167 | 168 | 169 | 170 | 171 | 174 | 175 | 177 | 178 | 180 | 181 | 183 | 184 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 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| 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | 382 | 383 | 384 | 385 | 386 | 387 | 388 | 389 | 390 | 391 | 392 | 393 | 394 | 395 | 396 | 397 | 398 | 399 | 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | default_dashboard 409 | 410 | 411 | 412 | -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/EE4218_MLP_Neural_Network_HLS_New.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AnuragSChatterjee/Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA/05aaa9cf39f4ac76ec177f532ff0394c63cf62d9/High Level Synthesis (HLS) Implementation/EE4218_MLP_Neural_Network_HLS_New.zip -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/EE4218_MLP_Project_HLS_Bitstream_10Apr.xsa: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/AnuragSChatterjee/Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA/05aaa9cf39f4ac76ec177f532ff0394c63cf62d9/High Level Synthesis (HLS) Implementation/EE4218_MLP_Project_HLS_Version_Anurag_Johannes.xsa -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/mlp_hls.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | ---------------------------------------------------------------------------------- 3 | -- (c) Rajesh C Panicker, NUS, 4 | -- Description : AXI Stream Coprocessor (HLS), implementing the sum of 4 numbers 5 | -- License terms : 6 | -- You are free to use this code as long as you 7 | -- (i) DO NOT post a modified version of this on any public repository; 8 | -- (ii) use it only for educational purposes; 9 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 10 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 11 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 12 | -- (vi) retain this notice in this file or any files derived from this. 13 | ---------------------------------------------------------------------------------- 14 | */ 15 | 16 | #include "hls_stream.h" 17 | #include "ap_int.h" 18 | #include "ap_axi_sdata.h" 19 | #include 20 | #include 21 | 22 | #define NUMBER_OF_INPUT_WORDS 467 // length of an input vector => 64x7 +8x2 +3x1 23 | #define NUMBER_OF_OUTPUT_WORDS 64 // length of an input vector 24 | 25 | // Creating a custom structure which includes the data word and TLAST signal. 26 | // ACLK, ARESETN, TREADY, TDATA, TVALID are essential signals for AXIS. 27 | // TLAST is a sideband signal which is optional in AXIS. 28 | // However, it is necessary for us since we connecting M_AXIS to AXI Stream FIFO / AXI DMA. 29 | // So, we create a struct with data (TDATA) and last (TLAST). The rest of the essential AXIS signals are automatically dealt with by the HLS tool. 30 | 31 | 32 | /* // doesn't work with HLS version 2022.2 33 | struct AXIS_wLAST{ 34 | int data; 35 | //ap_uint<32> data; 36 | bool last; 37 | }; 38 | */ 39 | int sig_arr[256] = { 40 | 12, 41 | 12, 42 | 12, 43 | 12, 44 | 13, 45 | 13, 46 | 13, 47 | 14, 48 | 14, 49 | 14, 50 | 15, 51 | 15, 52 | 15, 53 | 16, 54 | 16, 55 | 16, 56 | 17, 57 | 17, 58 | 18, 59 | 18, 60 | 18, 61 | 19, 62 | 19, 63 | 20, 64 | 20, 65 | 21, 66 | 21, 67 | 21, 68 | 22, 69 | 22, 70 | 23, 71 | 23, 72 | 24, 73 | 24, 74 | 25, 75 | 26, 76 | 26, 77 | 27, 78 | 27, 79 | 28, 80 | 28, 81 | 29, 82 | 30, 83 | 30, 84 | 31, 85 | 32, 86 | 32, 87 | 33, 88 | 34, 89 | 34, 90 | 35, 91 | 36, 92 | 36, 93 | 37, 94 | 38, 95 | 39, 96 | 39, 97 | 40, 98 | 41, 99 | 42, 100 | 43, 101 | 44, 102 | 44, 103 | 45, 104 | 46, 105 | 47, 106 | 48, 107 | 49, 108 | 50, 109 | 51, 110 | 52, 111 | 53, 112 | 54, 113 | 55, 114 | 56, 115 | 57, 116 | 58, 117 | 59, 118 | 60, 119 | 61, 120 | 62, 121 | 63, 122 | 64, 123 | 66, 124 | 67, 125 | 68, 126 | 69, 127 | 70, 128 | 72, 129 | 73, 130 | 74, 131 | 75, 132 | 76, 133 | 78, 134 | 79, 135 | 80, 136 | 82, 137 | 83, 138 | 84, 139 | 86, 140 | 87, 141 | 88, 142 | 90, 143 | 91, 144 | 92, 145 | 94, 146 | 95, 147 | 97, 148 | 98, 149 | 99, 150 | 101, 151 | 102, 152 | 104, 153 | 105, 154 | 107, 155 | 108, 156 | 110, 157 | 111, 158 | 113, 159 | 114, 160 | 116, 161 | 117, 162 | 119, 163 | 120, 164 | 122, 165 | 123, 166 | 125, 167 | 126, 168 | 128, 169 | 129, 170 | 130, 171 | 132, 172 | 133, 173 | 135, 174 | 136, 175 | 138, 176 | 139, 177 | 141, 178 | 142, 179 | 144, 180 | 145, 181 | 147, 182 | 148, 183 | 150, 184 | 151, 185 | 153, 186 | 154, 187 | 156, 188 | 157, 189 | 158, 190 | 160, 191 | 161, 192 | 163, 193 | 164, 194 | 165, 195 | 167, 196 | 168, 197 | 169, 198 | 171, 199 | 172, 200 | 173, 201 | 175, 202 | 176, 203 | 177, 204 | 179, 205 | 180, 206 | 181, 207 | 182, 208 | 183, 209 | 185, 210 | 186, 211 | 187, 212 | 188, 213 | 189, 214 | 191, 215 | 192, 216 | 193, 217 | 194, 218 | 195, 219 | 196, 220 | 197, 221 | 198, 222 | 199, 223 | 200, 224 | 201, 225 | 202, 226 | 203, 227 | 204, 228 | 205, 229 | 206, 230 | 207, 231 | 208, 232 | 209, 233 | 210, 234 | 211, 235 | 211, 236 | 212, 237 | 213, 238 | 214, 239 | 215, 240 | 216, 241 | 216, 242 | 217, 243 | 218, 244 | 219, 245 | 219, 246 | 220, 247 | 221, 248 | 221, 249 | 222, 250 | 223, 251 | 223, 252 | 224, 253 | 225, 254 | 225, 255 | 226, 256 | 227, 257 | 227, 258 | 228, 259 | 228, 260 | 229, 261 | 229, 262 | 230, 263 | 231, 264 | 231, 265 | 232, 266 | 232, 267 | 233, 268 | 233, 269 | 234, 270 | 234, 271 | 234, 272 | 235, 273 | 235, 274 | 236, 275 | 236, 276 | 237, 277 | 237, 278 | 237, 279 | 238, 280 | 238, 281 | 239, 282 | 239, 283 | 239, 284 | 240, 285 | 240, 286 | 240, 287 | 241, 288 | 241, 289 | 241, 290 | 242, 291 | 242, 292 | 242, 293 | 243, 294 | 243, 295 | 243 296 | }; 297 | typedef ap_axis<32,0,0,0> AXIS_wLAST; 298 | 299 | int sigmoid(int sum, int sig_arr[256]){ 300 | for (int i=0; i<256; i++) { 301 | if (i==sum) { 302 | return sig_arr[i]; 303 | } 304 | } 305 | } 306 | 307 | void matrix_multiply(int input_arr[], int sig_arr[256], int x_rows, int x_cols, int whid_rows, int whid_cols, int wout_rows, int wout_cols, int result[]) { 308 | // Separate the input array into the three matrices 309 | int X[x_rows][x_cols]; 310 | int W_hid[whid_rows][whid_cols]; 311 | int W_out[wout_rows][wout_cols]; 312 | int res_hidden[x_rows][whid_cols]; //computes hidden layer x input layer 313 | 314 | //printf("input layer\n"); 315 | for (int i = 0; i < x_rows; i++) { 316 | for (int j = 0; j < x_cols; j++) { 317 | X[i][j] = input_arr[i*x_cols + j]; 318 | //printf("%d\n", X[i][j]); 319 | } 320 | } 321 | //printf("Hidden layer\n"); 322 | for (int i = 0; i < whid_rows; i++) { 323 | for (int j = 0; j < whid_cols; j++) { 324 | W_hid[i][j] = input_arr[x_rows*x_cols + i*whid_cols + j ]; 325 | //printf("%d\n", W_hid[i][j]); 326 | } 327 | } 328 | //printf("out layer\n"); 329 | for (int i = 0; i < wout_rows; i++) { 330 | for (int j = 0; j < wout_cols; j++) { 331 | W_out[i][j] = input_arr[x_rows*x_cols + whid_rows*whid_cols + i*wout_cols + j ]; 332 | //printf("%d\n", W_out[i][j]); 333 | } 334 | } 335 | 336 | //printf("Multiplication layer 1 \n"); 337 | 338 | // Perform matrix multiplication on the three matrices 339 | // Multiply X and W_hid and store the result in result 340 | for (int i = 0; i < x_rows; i++) { 341 | for (int j = 0; j < whid_cols; j++) { 342 | int sum = 0; 343 | for (int k = 0; k < x_cols; k++) { 344 | sum += X[i][k] * W_hid[k+1][j]; 345 | } 346 | sum /= 256; 347 | //printf("%d\n", sum); 348 | if(j == 0){ 349 | sum += W_hid[0][0]; //add bias 350 | } 351 | else{ 352 | sum += W_hid[0][1]; 353 | } 354 | //printf("%d\n", sum); 355 | res_hidden[i][j] = sigmoid(sum, sig_arr); //activation function 356 | //printf("%d\n", res_hidden[i][j]); 357 | } 358 | } 359 | 360 | printf("Multiplication layer 2\n"); 361 | // Multiply only the 2nd and 3rd rows of the result with the W_out matrix 362 | for (int i = 1; i < x_rows; i++) { 363 | for (int j = 0; j < wout_cols; j++) { 364 | int sum = 0; 365 | for (int k = 0; k < whid_cols; k++) { 366 | sum += res_hidden[i][k] * W_out[k+1][j]; 367 | } 368 | sum /= 256; 369 | sum += W_out[0][0]; 370 | //printf("%d\n", sum); 371 | 372 | result[i] = sigmoid(sum, sig_arr); 373 | printf("%d\n", result[i]); 374 | 375 | if (result[i] >= 198 && result[i] <= 240) { 376 | printf("Class 1\n"); 377 | } 378 | else if (result[i] >= 150 && result[i] < 198) { 379 | printf("Class 0\n"); 380 | } 381 | else { 382 | printf("Class 0\n"); 383 | } 384 | } 385 | } 386 | } 387 | void myip_v1_0_HLS(hls::stream& S_AXIS, hls::stream& M_AXIS){ 388 | #pragma HLS INTERFACE ap_ctrl_none port=return 389 | #pragma HLS INTERFACE axis port=S_AXIS 390 | #pragma HLS INTERFACE axis port=M_AXIS 391 | 392 | int word_cnt; 393 | ap_uint<8> sum = 0; // using arbitrary precision 394 | //int sum = 0; // using 32 bit precision 395 | AXIS_wLAST read_input, write_output; 396 | int arr[NUMBER_OF_INPUT_WORDS]; 397 | //int sig_arr[256]; 398 | 399 | myip_v1_0_HLS_for1:for(word_cnt = 0; word_cnt < NUMBER_OF_INPUT_WORDS; word_cnt++){ 400 | #pragma HLS pipeline II=4 401 | 402 | read_input = S_AXIS.read(); 403 | // read_input is the element (data + other signals) received by our ip through S_AXIS in one clock cycle (which contains one word). 404 | // read() extracts it from the stream. Overloaded operator >> can also be used. 405 | //extracting that word 406 | 407 | arr[word_cnt] = read_input.data; 408 | //printf("%d\n", arr[word_cnt]); 409 | 410 | //printf("%d\n", sig_arr[word_cnt]); 411 | 412 | //printf("%d\n", arr[word_cnt]); 413 | 414 | // We are not making using of S_AXIS_TLAST in this example. 415 | // S_AXIS_TLAST is required only when we are receiving an unknown number of words. 416 | } 417 | 418 | // Initialize the result matrix as a 1D array of size 64 419 | int result[NUMBER_OF_OUTPUT_WORDS]; 420 | int x_rows = 64; 421 | int x_cols = 7; 422 | int whid_rows = 8; 423 | int whid_cols = 2; 424 | int wout_rows = 3; 425 | int wout_cols = 1; 426 | 427 | 428 | // Compute the matrix multiplication using the function 429 | matrix_multiply(arr, sig_arr, x_rows, x_cols, whid_rows, whid_cols, wout_rows, wout_cols, result); 430 | 431 | myip_v1_0_HLS_for2:for(word_cnt = 0; word_cnt < NUMBER_OF_OUTPUT_WORDS; word_cnt++){ 432 | 433 | //rite_output.data = sum.to_int() + word_cnt; // using arbitrary precision internally but int for interfacing 434 | //write_output.data = sum + word_cnt; // using 32 bit precision or arbitrary precision all the way 435 | // write_output is the element sent by our ip through M_AXIS in one clock cycle. 436 | write_output.data = result[word_cnt]; 437 | write_output.last = 0; 438 | if(word_cnt==NUMBER_OF_OUTPUT_WORDS-1) 439 | { 440 | write_output.last = 1; 441 | // M_AXIS_TLAST is required to be asserted for the last word. 442 | // Else, the AXI Stream FIFO / AXI DMA will not know if all the words have been received from the co-processor. 443 | } 444 | M_AXIS.write(write_output); 445 | // write() inserts it into the stream. Overloaded operator << can also be used. 446 | } 447 | } 448 | 449 | -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/test_mlp_hls.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | ---------------------------------------------------------------------------------- 3 | -- (c) Rajesh C Panicker, NUS, 4 | -- Description : Self-checking testbench for AXI Stream Coprocessor (HLS) implementing the sum of 4 numbers 5 | -- License terms : 6 | -- You are free to use this code as long as you 7 | -- (i) DO NOT post a modified version of this on any public repository; 8 | -- (ii) use it only for educational purposes; 9 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 10 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 11 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 12 | -- (vi) retain this notice in this file or any files derived from this. 13 | ---------------------------------------------------------------------------------- 14 | */ 15 | 16 | #include 17 | #include "hls_stream.h" 18 | #include "ap_axi_sdata.h" 19 | 20 | /***************** AXIS with TLAST structure declaration *********************/ 21 | /* 22 | struct AXIS_wLAST{ 23 | int data; 24 | bool last; 25 | }; 26 | */ 27 | typedef ap_axis<32,0,0,0> AXIS_wLAST; 28 | 29 | /***************** Coprocessor function declaration *********************/ 30 | 31 | void myip_v1_0_HLS(hls::stream& S_AXIS, hls::stream& M_AXIS); 32 | 33 | 34 | /***************** Macros *********************/ 35 | #define NUMBER_OF_INPUT_WORDS 467 // length of an input vector 36 | #define NUMBER_OF_OUTPUT_WORDS 64 // length of an input vector 37 | #define NUMBER_OF_TEST_VECTORS 1 // number of such test vectors (cases) 38 | 39 | 40 | /************************** Variable Definitions *****************************/ 41 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = {0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05}; // 4 inputs * 2 42 | 43 | int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = { 44 | 44, 45 | 159, 46 | 167, 47 | 130, 48 | 34, 49 | 63, 50 | 88, 51 | 185, 52 | 140, 53 | 73, 54 | 16, 55 | 31, 56 | 183, 57 | 129, 58 | 190, 59 | 79, 60 | 213, 61 | 13, 62 | 103, 63 | 42, 64 | 26, 65 | 69, 66 | 143, 67 | 73, 68 | 100, 69 | 110, 70 | 165, 71 | 182, 72 | 34, 73 | 108, 74 | 18, 75 | 35, 76 | 72, 77 | 27, 78 | 149, 79 | 138, 80 | 120, 81 | 183, 82 | 38, 83 | 180, 84 | 86, 85 | 219, 86 | 31, 87 | 21, 88 | 111, 89 | 224, 90 | 231, 91 | 140, 92 | 116, 93 | 43, 94 | 39, 95 | 103, 96 | 83, 97 | 73, 98 | 159, 99 | 14, 100 | 37, 101 | 225, 102 | 64, 103 | 44, 104 | 153, 105 | 86, 106 | 138, 107 | 19, 108 | 90, 109 | 250, 110 | 158, 111 | 178, 112 | 112, 113 | 28, 114 | 214, 115 | 203, 116 | 255, 117 | 90, 118 | 93, 119 | 110, 120 | 181, 121 | 193, 122 | 183, 123 | 113, 124 | 213, 125 | 94, 126 | 175, 127 | 82, 128 | 90, 129 | 90, 130 | 225, 131 | 87, 132 | 136, 133 | 136, 134 | 143, 135 | 207, 136 | 51, 137 | 85, 138 | 70, 139 | 165, 140 | 99, 141 | 85, 142 | 166, 143 | 180, 144 | 97, 145 | 181, 146 | 113, 147 | 188, 148 | 87, 149 | 224, 150 | 65, 151 | 134, 152 | 62, 153 | 206, 154 | 225, 155 | 146, 156 | 191, 157 | 136, 158 | 76, 159 | 166, 160 | 148, 161 | 41, 162 | 136, 163 | 77, 164 | 70, 165 | 171, 166 | 177, 167 | 54, 168 | 170, 169 | 155, 170 | 160, 171 | 0, 172 | 0, 173 | 140, 174 | 172, 175 | 136, 176 | 142, 177 | 145, 178 | 157, 179 | 170, 180 | 110, 181 | 164, 182 | 187, 183 | 120, 184 | 155, 185 | 104, 186 | 143, 187 | 115, 188 | 149, 189 | 127, 190 | 164, 191 | 104, 192 | 109, 193 | 101, 194 | 125, 195 | 125, 196 | 254, 197 | 101, 198 | 179, 199 | 131, 200 | 194, 201 | 116, 202 | 110, 203 | 120, 204 | 85, 205 | 85, 206 | 176, 207 | 136, 208 | 115, 209 | 183, 210 | 125, 211 | 169, 212 | 80, 213 | 155, 214 | 145, 215 | 48, 216 | 128, 217 | 128, 218 | 139, 219 | 106, 220 | 196, 221 | 131, 222 | 130, 223 | 170, 224 | 206, 225 | 150, 226 | 93, 227 | 160, 228 | 131, 229 | 136, 230 | 76, 231 | 166, 232 | 150, 233 | 136, 234 | 104, 235 | 140, 236 | 0, 237 | 176, 238 | 134, 239 | 120, 240 | 112, 241 | 126, 242 | 140, 243 | 110, 244 | 136, 245 | 118, 246 | 88, 247 | 77, 248 | 175, 249 | 159, 250 | 124, 251 | 111, 252 | 159, 253 | 146, 254 | 139, 255 | 83, 256 | 143, 257 | 180, 258 | 147, 259 | 29, 260 | 119, 261 | 137, 262 | 151, 263 | 105, 264 | 94, 265 | 25, 266 | 118, 267 | 72, 268 | 76, 269 | 109, 270 | 111, 271 | 131, 272 | 96, 273 | 152, 274 | 67, 275 | 137, 276 | 72, 277 | 165, 278 | 38, 279 | 83, 280 | 89, 281 | 155, 282 | 174, 283 | 124, 284 | 136, 285 | 58, 286 | 63, 287 | 115, 288 | 120, 289 | 63, 290 | 153, 291 | 67, 292 | 53, 293 | 148, 294 | 69, 295 | 93, 296 | 125, 297 | 41, 298 | 119, 299 | 139, 300 | 24, 301 | 121, 302 | 172, 303 | 135, 304 | 163, 305 | 190, 306 | 205, 307 | 211, 308 | 133, 309 | 75, 310 | 162, 311 | 166, 312 | 135, 313 | 184, 314 | 139, 315 | 164, 316 | 133, 317 | 132, 318 | 187, 319 | 167, 320 | 135, 321 | 125, 322 | 196, 323 | 8, 324 | 170, 325 | 186, 326 | 167, 327 | 130, 328 | 90, 329 | 24, 330 | 179, 331 | 126, 332 | 210, 333 | 122, 334 | 135, 335 | 255, 336 | 110, 337 | 119, 338 | 88, 339 | 188, 340 | 76, 341 | 197, 342 | 112, 343 | 94, 344 | 163, 345 | 167, 346 | 149, 347 | 192, 348 | 192, 349 | 44, 350 | 71, 351 | 236, 352 | 142, 353 | 123, 354 | 140, 355 | 68, 356 | 72, 357 | 136, 358 | 92, 359 | 158, 360 | 152, 361 | 36, 362 | 149, 363 | 217, 364 | 81, 365 | 183, 366 | 161, 367 | 121, 368 | 159, 369 | 165, 370 | 174, 371 | 138, 372 | 156, 373 | 121, 374 | 101, 375 | 101, 376 | 211, 377 | 183, 378 | 138, 379 | 101, 380 | 199, 381 | 150, 382 | 147, 383 | 50, 384 | 220, 385 | 222, 386 | 197, 387 | 87, 388 | 140, 389 | 174, 390 | 156, 391 | 101, 392 | 94, 393 | 0, 394 | 138, 395 | 72, 396 | 101, 397 | 133, 398 | 115, 399 | 139, 400 | 128, 401 | 174, 402 | 26, 403 | 124, 404 | 73, 405 | 252, 406 | 32, 407 | 78, 408 | 209, 409 | 170, 410 | 202, 411 | 142, 412 | 170, 413 | 50, 414 | 62, 415 | 131, 416 | 156, 417 | 78, 418 | 149, 419 | 72, 420 | 46, 421 | 161, 422 | 92, 423 | 101, 424 | 171, 425 | 131, 426 | 124, 427 | 161, 428 | 22, 429 | 138, 430 | 118, 431 | 86, 432 | 43, 433 | 66, 434 | 128, 435 | 126, 436 | 131, 437 | 111, 438 | 27, 439 | 45, 440 | 185, 441 | 161, 442 | 145, 443 | 88, 444 | 183, 445 | 89, 446 | 128, 447 | 71, 448 | 106, 449 | 108, 450 | 121, 451 | 67, 452 | 77, 453 | 126, 454 | 147, 455 | 124, 456 | 58, 457 | 59, 458 | 50, 459 | 82, 460 | 56, 461 | 54, 462 | 98, 463 | 84, 464 | 44, 465 | 148, 466 | 68, 467 | 145, 468 | 71, 469 | 218, 470 | 78, 471 | 111, 472 | 65, 473 | 150, 474 | 208, 475 | 104, 476 | 108, 477 | 118, 478 | 39, 479 | 75, 480 | 102, 481 | 51, 482 | 198, 483 | 56, 484 | 37, 485 | 188, 486 | 84, 487 | 59, 488 | 166, 489 | 63, 490 | 100, 491 | 51, 492 | 26, 493 | 25, 494 | 31, 495 | 29, 496 | 22, 497 | 1, 498 | 11, 499 | 26, 500 | 6, 501 | 18, 502 | 6, 503 | 26, 504 | 1, 505 | 28, 506 | 9, 507 | 45, 508 | 80, 509 | 50, 510 | 200}; 511 | 512 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS];//= {0x01, 0x02, 0x03, 0x04, 0x01, 0x02, 0x03, 0x04}; 513 | 514 | int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS] = {0, 515 | 1, 516 | 1, 517 | 1, 518 | 0, 519 | 0, 520 | 1, 521 | 1, 522 | 1, 523 | 0, 524 | 0, 525 | 0, 526 | 1, 527 | 1, 528 | 1, 529 | 0, 530 | 1, 531 | 0, 532 | 1, 533 | 0, 534 | 0, 535 | 1, 536 | 1, 537 | 0, 538 | 1, 539 | 1, 540 | 1, 541 | 1, 542 | 0, 543 | 0, 544 | 0, 545 | 0, 546 | 0, 547 | 0, 548 | 1, 549 | 1, 550 | 0, 551 | 1, 552 | 0, 553 | 1, 554 | 0, 555 | 1, 556 | 0, 557 | 0, 558 | 1, 559 | 1, 560 | 1, 561 | 1, 562 | 1, 563 | 0, 564 | 0, 565 | 1, 566 | 1, 567 | 0, 568 | 1, 569 | 0, 570 | 0, 571 | 1, 572 | 0, 573 | 0, 574 | 1, 575 | 0, 576 | 1, 577 | 0}; 578 | 579 | //int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS];// 4 outputs *2 580 | int result_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS]; // same size as test_result_expected_memory 581 | 582 | /***************************************************************************** 583 | * Main function 584 | ******************************************************************************/ 585 | int main() 586 | { 587 | int word_cnt, test_case_cnt = 0; 588 | int success; 589 | AXIS_wLAST read_output, write_input; 590 | hls::stream S_AXIS; 591 | hls::stream M_AXIS; 592 | 593 | /************** Run a software version of the hardware function to validate results ************/ 594 | // instead of hard-coding the results in test_result_expected_memory 595 | 596 | // int sum; 597 | // for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 598 | // sum = 0; 599 | // for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 600 | // sum +=test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]; 601 | // } 602 | // for (word_cnt=0; word_cnt < NUMBER_OF_OUTPUT_WORDS; word_cnt++) { 603 | // test_result_expected_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = sum + word_cnt; 604 | // } 605 | // } 606 | 607 | 608 | for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 609 | 610 | 611 | /******************** Input to Coprocessor : Transmit the Data Stream ***********************/ 612 | 613 | printf(" Transmitting Data for test case %d ... \r\n", test_case_cnt); 614 | 615 | for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS; word_cnt++){ 616 | 617 | write_input.data = test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]; 618 | write_input.last = 0; 619 | if(word_cnt==NUMBER_OF_INPUT_WORDS-1) 620 | { 621 | write_input.last = 1; 622 | // S_AXIS_TLAST is asserted for the last word. 623 | // Actually, doesn't matter since we are not making using of S_AXIS_TLAST. 624 | } 625 | S_AXIS.write(write_input); // insert one word into the stream 626 | } 627 | 628 | /* Transmission Complete */ 629 | 630 | /********************* Call the hardware function (invoke the co-processor / ip) ***************/ 631 | 632 | myip_v1_0_HLS(S_AXIS, M_AXIS); 633 | 634 | 635 | /******************** Output from Coprocessor : Receive the Data Stream ***********************/ 636 | 637 | printf(" Receiving data for test case %d ... \r\n", test_case_cnt); 638 | 639 | for (word_cnt=0 ; word_cnt < NUMBER_OF_OUTPUT_WORDS ; word_cnt++){ 640 | read_output = M_AXIS.read(); // extract one word from the stream 641 | read_output.data = test_result_expected_memory[word_cnt]; 642 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = read_output.data; 643 | } 644 | 645 | /* Reception Complete */ 646 | } 647 | 648 | /************************** Checking correctness of results *****************************/ 649 | 650 | success = 1; 651 | 652 | /* Compare the data send with the data received */ 653 | printf(" Comparing data ...\r\n"); 654 | for(word_cnt=0; word_cnt < NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS; word_cnt++){ 655 | printf("%d %d\n", result_memory[word_cnt], test_result_expected_memory[word_cnt]); 656 | success = success & (result_memory[word_cnt] == test_result_expected_memory[word_cnt]); 657 | } 658 | 659 | if (success != 1){ 660 | printf("Test Failed\r\n"); 661 | return 1; 662 | } 663 | 664 | printf("Test Success\r\n"); 665 | 666 | return 0; 667 | } 668 | -------------------------------------------------------------------------------- /High Level Synthesis (HLS) Implementation/testbench.c: -------------------------------------------------------------------------------- 1 | /* 2 | ---------------------------------------------------------------------------------- 3 | -- (c) Rajesh C Panicker, NUS, 4 | -- Modified from XLlFifo_polling_example.c, (c) Xilinx Inc 5 | -- Description : Self-checking sample program for AXI Stream Coprocessor interfaced using AXI Stream FIFO. 6 | -- License terms : 7 | -- You are free to use this code as long as you 8 | -- (i) DO NOT post a modified version of this on any public repository; 9 | -- (ii) use it only for educational purposes; 10 | -- (iii) accept the responsibility to ensure that your implementation does not violate any intellectual property of any entity. 11 | -- (iv) accept that the program is provided "as is" without warranty of any kind or assurance regarding its suitability for any particular purpose; 12 | -- (v) send an email to rajesh.panicker@ieee.org briefly mentioning its use (except when used for the course EE4218 at the National University of Singapore); 13 | -- (vi) retain this notice in this file or any files derived from this. 14 | ---------------------------------------------------------------------------------- 15 | */ 16 | 17 | /***************************** Include Files *********************************/ 18 | #include "xparameters.h" 19 | #include "xil_exception.h" 20 | #include "xstreamer.h" 21 | #include "xil_cache.h" 22 | #include "xllfifo.h" 23 | #include "xstatus.h" 24 | #include 25 | #include "xil_printf.h" 26 | #include "xtmrctr.h" 27 | /************************** Constant Definitions *****************************/ 28 | 29 | /* 30 | * The following constants map to the XPAR parameters created in the 31 | * xparameters.h file. They are only defined here such that a user can easily 32 | * change all the needed parameters in one place. 33 | */ 34 | #define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID 35 | 36 | 37 | /* 38 | * This example only uses the 1st of the 2 timer counters contained in a 39 | * single timer counter hardware device 40 | */ 41 | #define TIMER_COUNTER_0 0 42 | 43 | /************************** Variable Definitions *****************************/ 44 | 45 | XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */ 46 | 47 | /***************** Macros *********************/ 48 | #define NUMBER_OF_INPUT_WORDS 467 // length of an input vector 49 | #define NUMBER_OF_OUTPUT_WORDS 64 // length of an input vector 50 | #define NUMBER_OF_TEST_VECTORS 1 // number of such test vectors (cases) 51 | 52 | #define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID 53 | 54 | #define TIMEOUT_VALUE 1<<20; // timeout for reception 55 | 56 | /************************** Variable Definitions *****************************/ 57 | u16 DeviceId = FIFO_DEV_ID; 58 | XLlFifo FifoInstance; // Device instance 59 | XLlFifo *InstancePtr = &FifoInstance; // Device pointer 60 | 61 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS]; 62 | //int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = {0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05,0x01, 0x02, 0x03, 0x04, 0x02, 0x03, 0x04, 0x05}; 63 | int test_input_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_INPUT_WORDS] = { 64 | 44, 65 | 159, 66 | 167, 67 | 130, 68 | 34, 69 | 63, 70 | 88, 71 | 185, 72 | 140, 73 | 73, 74 | 16, 75 | 31, 76 | 183, 77 | 129, 78 | 190, 79 | 79, 80 | 213, 81 | 13, 82 | 103, 83 | 42, 84 | 26, 85 | 69, 86 | 143, 87 | 73, 88 | 100, 89 | 110, 90 | 165, 91 | 182, 92 | 34, 93 | 108, 94 | 18, 95 | 35, 96 | 72, 97 | 27, 98 | 149, 99 | 138, 100 | 120, 101 | 183, 102 | 38, 103 | 180, 104 | 86, 105 | 219, 106 | 31, 107 | 21, 108 | 111, 109 | 224, 110 | 231, 111 | 140, 112 | 116, 113 | 43, 114 | 39, 115 | 103, 116 | 83, 117 | 73, 118 | 159, 119 | 14, 120 | 37, 121 | 225, 122 | 64, 123 | 44, 124 | 153, 125 | 86, 126 | 138, 127 | 19, 128 | 90, 129 | 250, 130 | 158, 131 | 178, 132 | 112, 133 | 28, 134 | 214, 135 | 203, 136 | 255, 137 | 90, 138 | 93, 139 | 110, 140 | 181, 141 | 193, 142 | 183, 143 | 113, 144 | 213, 145 | 94, 146 | 175, 147 | 82, 148 | 90, 149 | 90, 150 | 225, 151 | 87, 152 | 136, 153 | 136, 154 | 143, 155 | 207, 156 | 51, 157 | 85, 158 | 70, 159 | 165, 160 | 99, 161 | 85, 162 | 166, 163 | 180, 164 | 97, 165 | 181, 166 | 113, 167 | 188, 168 | 87, 169 | 224, 170 | 65, 171 | 134, 172 | 62, 173 | 206, 174 | 225, 175 | 146, 176 | 191, 177 | 136, 178 | 76, 179 | 166, 180 | 148, 181 | 41, 182 | 136, 183 | 77, 184 | 70, 185 | 171, 186 | 177, 187 | 54, 188 | 170, 189 | 155, 190 | 160, 191 | 0, 192 | 0, 193 | 140, 194 | 172, 195 | 136, 196 | 142, 197 | 145, 198 | 157, 199 | 170, 200 | 110, 201 | 164, 202 | 187, 203 | 120, 204 | 155, 205 | 104, 206 | 143, 207 | 115, 208 | 149, 209 | 127, 210 | 164, 211 | 104, 212 | 109, 213 | 101, 214 | 125, 215 | 125, 216 | 254, 217 | 101, 218 | 179, 219 | 131, 220 | 194, 221 | 116, 222 | 110, 223 | 120, 224 | 85, 225 | 85, 226 | 176, 227 | 136, 228 | 115, 229 | 183, 230 | 125, 231 | 169, 232 | 80, 233 | 155, 234 | 145, 235 | 48, 236 | 128, 237 | 128, 238 | 139, 239 | 106, 240 | 196, 241 | 131, 242 | 130, 243 | 170, 244 | 206, 245 | 150, 246 | 93, 247 | 160, 248 | 131, 249 | 136, 250 | 76, 251 | 166, 252 | 150, 253 | 136, 254 | 104, 255 | 140, 256 | 0, 257 | 176, 258 | 134, 259 | 120, 260 | 112, 261 | 126, 262 | 140, 263 | 110, 264 | 136, 265 | 118, 266 | 88, 267 | 77, 268 | 175, 269 | 159, 270 | 124, 271 | 111, 272 | 159, 273 | 146, 274 | 139, 275 | 83, 276 | 143, 277 | 180, 278 | 147, 279 | 29, 280 | 119, 281 | 137, 282 | 151, 283 | 105, 284 | 94, 285 | 25, 286 | 118, 287 | 72, 288 | 76, 289 | 109, 290 | 111, 291 | 131, 292 | 96, 293 | 152, 294 | 67, 295 | 137, 296 | 72, 297 | 165, 298 | 38, 299 | 83, 300 | 89, 301 | 155, 302 | 174, 303 | 124, 304 | 136, 305 | 58, 306 | 63, 307 | 115, 308 | 120, 309 | 63, 310 | 153, 311 | 67, 312 | 53, 313 | 148, 314 | 69, 315 | 93, 316 | 125, 317 | 41, 318 | 119, 319 | 139, 320 | 24, 321 | 121, 322 | 172, 323 | 135, 324 | 163, 325 | 190, 326 | 205, 327 | 211, 328 | 133, 329 | 75, 330 | 162, 331 | 166, 332 | 135, 333 | 184, 334 | 139, 335 | 164, 336 | 133, 337 | 132, 338 | 187, 339 | 167, 340 | 135, 341 | 125, 342 | 196, 343 | 8, 344 | 170, 345 | 186, 346 | 167, 347 | 130, 348 | 90, 349 | 24, 350 | 179, 351 | 126, 352 | 210, 353 | 122, 354 | 135, 355 | 255, 356 | 110, 357 | 119, 358 | 88, 359 | 188, 360 | 76, 361 | 197, 362 | 112, 363 | 94, 364 | 163, 365 | 167, 366 | 149, 367 | 192, 368 | 192, 369 | 44, 370 | 71, 371 | 236, 372 | 142, 373 | 123, 374 | 140, 375 | 68, 376 | 72, 377 | 136, 378 | 92, 379 | 158, 380 | 152, 381 | 36, 382 | 149, 383 | 217, 384 | 81, 385 | 183, 386 | 161, 387 | 121, 388 | 159, 389 | 165, 390 | 174, 391 | 138, 392 | 156, 393 | 121, 394 | 101, 395 | 101, 396 | 211, 397 | 183, 398 | 138, 399 | 101, 400 | 199, 401 | 150, 402 | 147, 403 | 50, 404 | 220, 405 | 222, 406 | 197, 407 | 87, 408 | 140, 409 | 174, 410 | 156, 411 | 101, 412 | 94, 413 | 0, 414 | 138, 415 | 72, 416 | 101, 417 | 133, 418 | 115, 419 | 139, 420 | 128, 421 | 174, 422 | 26, 423 | 124, 424 | 73, 425 | 252, 426 | 32, 427 | 78, 428 | 209, 429 | 170, 430 | 202, 431 | 142, 432 | 170, 433 | 50, 434 | 62, 435 | 131, 436 | 156, 437 | 78, 438 | 149, 439 | 72, 440 | 46, 441 | 161, 442 | 92, 443 | 101, 444 | 171, 445 | 131, 446 | 124, 447 | 161, 448 | 22, 449 | 138, 450 | 118, 451 | 86, 452 | 43, 453 | 66, 454 | 128, 455 | 126, 456 | 131, 457 | 111, 458 | 27, 459 | 45, 460 | 185, 461 | 161, 462 | 145, 463 | 88, 464 | 183, 465 | 89, 466 | 128, 467 | 71, 468 | 106, 469 | 108, 470 | 121, 471 | 67, 472 | 77, 473 | 126, 474 | 147, 475 | 124, 476 | 58, 477 | 59, 478 | 50, 479 | 82, 480 | 56, 481 | 54, 482 | 98, 483 | 84, 484 | 44, 485 | 148, 486 | 68, 487 | 145, 488 | 71, 489 | 218, 490 | 78, 491 | 111, 492 | 65, 493 | 150, 494 | 208, 495 | 104, 496 | 108, 497 | 118, 498 | 39, 499 | 75, 500 | 102, 501 | 51, 502 | 198, 503 | 56, 504 | 37, 505 | 188, 506 | 84, 507 | 59, 508 | 166, 509 | 63, 510 | 100, 511 | 51, 512 | 26, 513 | 25, 514 | 31, 515 | 29, 516 | 22, 517 | 1, 518 | 11, 519 | 26, 520 | 6, 521 | 18, 522 | 6, 523 | 26, 524 | 1, 525 | 28, 526 | 9, 527 | 45, 528 | 80, 529 | 50, 530 | 200}; 531 | 532 | int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS] = {0, 533 | 1, 534 | 1, 535 | 1, 536 | 0, 537 | 0, 538 | 1, 539 | 1, 540 | 1, 541 | 0, 542 | 0, 543 | 0, 544 | 1, 545 | 1, 546 | 1, 547 | 0, 548 | 1, 549 | 0, 550 | 1, 551 | 0, 552 | 0, 553 | 1, 554 | 1, 555 | 0, 556 | 1, 557 | 1, 558 | 1, 559 | 1, 560 | 0, 561 | 0, 562 | 0, 563 | 0, 564 | 0, 565 | 0, 566 | 1, 567 | 1, 568 | 0, 569 | 1, 570 | 0, 571 | 1, 572 | 0, 573 | 1, 574 | 0, 575 | 0, 576 | 1, 577 | 1, 578 | 1, 579 | 1, 580 | 1, 581 | 0, 582 | 0, 583 | 1, 584 | 1, 585 | 0, 586 | 1, 587 | 0, 588 | 0, 589 | 1, 590 | 0, 591 | 0, 592 | 1, 593 | 0, 594 | 1, 595 | 0}; 596 | 597 | //int test_result_expected_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS];// 4 outputs *2 598 | int result_memory [NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS]; // same size as test_result_expected_memory 599 | 600 | /***************************************************************************** 601 | * Main function 602 | ******************************************************************************/ 603 | int main() 604 | { 605 | int Status = XST_SUCCESS; 606 | int word_cnt, test_case_cnt = 0; 607 | int success; 608 | // Timer initialization 609 | u8 TmrCtrNumber = TIMER_COUNTER_0; 610 | u16 DeviceId = TMRCTR_DEVICE_ID; 611 | int Status_Timer; 612 | u32 Timer1; 613 | u32 Timer2; 614 | XTmrCtr TimerCounter; 615 | XTmrCtr *TmrCtrInstancePtr = &TimerCounter; 616 | 617 | /* 618 | * Initialize the timer counter so that it's ready to use, 619 | * specify the device ID that is generated in xparameters.h 620 | */ 621 | Status_Timer = XTmrCtr_Initialize(TmrCtrInstancePtr, DeviceId); 622 | if (Status_Timer != XST_SUCCESS) { 623 | return XST_FAILURE; 624 | } 625 | 626 | 627 | /************************** Initializations *****************************/ 628 | XLlFifo_Config *Config; 629 | 630 | /* Initialize the Device Configuration Interface driver */ 631 | Config = XLlFfio_LookupConfig(DeviceId); 632 | if (!Config) { 633 | xil_printf("No config found for %d\r\n", DeviceId); 634 | return XST_FAILURE; 635 | } 636 | 637 | Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress); 638 | if (Status != XST_SUCCESS) { 639 | xil_printf("Initialization failed\r\n"); 640 | return XST_FAILURE; 641 | } 642 | 643 | /* Check for the Reset value */ 644 | Status = XLlFifo_Status(InstancePtr); 645 | XLlFifo_IntClear(InstancePtr,0xffffffff); 646 | Status = XLlFifo_Status(InstancePtr); 647 | if(Status != 0x0) { 648 | xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t. Expected : 0x0\r\n", 649 | XLlFifo_Status(InstancePtr)); 650 | return XST_FAILURE; 651 | } 652 | 653 | // for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 654 | // 655 | // for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 656 | // scanf("%d", &test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]); 657 | // } 658 | // 659 | // } 660 | 661 | /************** Run a software version of the hardware function to validate results ************/ 662 | // instead of hard-coding the results in test_result_expected_memory 663 | 664 | // int sum; 665 | // for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 666 | // sum = 0; 667 | // for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 668 | // sum +=test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]; 669 | // } 670 | // for (word_cnt=0; word_cnt < NUMBER_OF_OUTPUT_WORDS; word_cnt++) { 671 | // test_result_expected_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = sum + word_cnt; 672 | // } 673 | // } 674 | // 675 | // 676 | /* 677 | * Perform a self-test to ensure that the hardware was built 678 | * correctly, use the 1st timer in the device (0) 679 | */ 680 | Status_Timer = XTmrCtr_SelfTest(TmrCtrInstancePtr, TmrCtrNumber); 681 | if (Status_Timer != XST_SUCCESS) { 682 | return XST_FAILURE; 683 | } 684 | 685 | 686 | /* 687 | * Enable the Autoreload mode of the timer counters. 688 | */ 689 | XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, 690 | XTC_AUTO_RELOAD_OPTION); 691 | 692 | /* 693 | * Get a snapshot of the timer counter value before it's started 694 | * to compare against later 695 | */ 696 | Timer1 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber); 697 | /* 698 | * Start the timer counter such that it's incrementing by default 699 | */ 700 | XTmrCtr_Start(TmrCtrInstancePtr, TmrCtrNumber); 701 | 702 | for (test_case_cnt=0 ; test_case_cnt < NUMBER_OF_TEST_VECTORS ; test_case_cnt++){ 703 | 704 | /******************** Input to Coprocessor : Transmit the Data Stream ***********************/ 705 | xil_printf(" Transmitting Data for test case %d ... \r\n", test_case_cnt); 706 | 707 | /* Writing into the FIFO Transmit Port Buffer */ 708 | for (word_cnt=0 ; word_cnt < NUMBER_OF_INPUT_WORDS ; word_cnt++){ 709 | if( XLlFifo_iTxVacancy(InstancePtr) ){ 710 | XLlFifo_TxPutWord(InstancePtr, test_input_memory[word_cnt+test_case_cnt*NUMBER_OF_INPUT_WORDS]); 711 | } 712 | } 713 | 714 | /* Start Transmission by writing transmission length (number of bytes = 4* number of words) into the TLR */ 715 | XLlFifo_iTxSetLen(InstancePtr, NUMBER_OF_INPUT_WORDS * 4); 716 | 717 | /* Check for Transmission completion */ 718 | while( !(XLlFifo_IsTxDone(InstancePtr)) ){ 719 | 720 | } 721 | 722 | /* Transmission Complete */ 723 | 724 | /******************** Output from Coprocessor : Receive the Data Stream ***********************/ 725 | 726 | xil_printf(" Receiving data for test case %d ... \r\n", test_case_cnt); 727 | 728 | int timeout_count = TIMEOUT_VALUE; 729 | // wait for coprocessor to send data, subject to a timeout 730 | while(!XLlFifo_iRxOccupancy(InstancePtr)) { 731 | timeout_count--; 732 | if (timeout_count == 0) 733 | { 734 | xil_printf("Timeout while waiting for data ... \r\n"); 735 | return XST_FAILURE; 736 | } 737 | } 738 | 739 | // we are expecting only one packet of data per test case. one packet = sequence of data until TLAST 740 | // if more packets are expected from the coprocessor, the part below should be done in a loop. 741 | u32 ReceiveLength = XLlFifo_iRxGetLen(InstancePtr)/4; 742 | for (word_cnt=0; word_cnt < ReceiveLength; word_cnt++) { 743 | // read one word at a time 744 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = XLlFifo_RxGetWord(InstancePtr); 745 | if (result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] >= 198 && result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] <= 240) { 746 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = 1; 747 | } 748 | else if (result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] >= 150 && result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] <= 198) { 749 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = 0; 750 | } 751 | else { 752 | result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS] = 0; 753 | } 754 | xil_printf("%d ", result_memory[word_cnt+test_case_cnt*NUMBER_OF_OUTPUT_WORDS]); 755 | } 756 | 757 | Status = XLlFifo_IsRxDone(InstancePtr); 758 | if(Status != TRUE){ 759 | xil_printf("Failing in receive complete ... \r\n"); 760 | return XST_FAILURE; 761 | } 762 | /* Reception Complete */ 763 | } 764 | Timer2 = XTmrCtr_GetValue(TmrCtrInstancePtr, TmrCtrNumber); 765 | 766 | /* 767 | * Disable the Autoreload mode of the timer counters. 768 | */ 769 | XTmrCtr_SetOptions(TmrCtrInstancePtr, TmrCtrNumber, 0); 770 | 771 | /************************** Checking correctness of results *****************************/ 772 | 773 | success = 1; 774 | 775 | /* Compare the data send with the data received */ 776 | xil_printf(" Comparing data ...\r\n"); 777 | for(word_cnt=0; word_cnt < NUMBER_OF_TEST_VECTORS*NUMBER_OF_OUTPUT_WORDS; word_cnt++){ 778 | xil_printf("%d %d\n", result_memory[word_cnt], test_result_expected_memory[word_cnt]); 779 | success = success & (result_memory[word_cnt] == test_result_expected_memory[word_cnt]); 780 | } 781 | 782 | // if (success != 1){ 783 | // xil_printf("Test Failed\r\n"); 784 | // return XST_FAILURE; 785 | // } 786 | // 787 | // xil_printf("Test Success\r\n"); 788 | printf("Time taken for Transmission and Receiving: %lu \n", Timer2); 789 | 790 | return XST_SUCCESS; 791 | } 792 | 793 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA 2 | A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform Machine Learning models i.e. MLP Neural Networks on an FPGA using C, C++, Hardware Description Languages (HDL), High Level Synthesis (HLS) and Verilog. 3 | 4 | Project Link: https://wiki.nus.edu.sg/pages/viewpage.action?pageId=167809322 5 | -------------------------------------------------------------------------------- /Software Implementation/About: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Software Implementation/helloworld.c: -------------------------------------------------------------------------------- 1 | ///****************************************************************************** 2 | //* 3 | //* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. 4 | //* 5 | //* Permission is hereby granted, free of charge, to any person obtaining a copy 6 | //* of this software and associated documentation files (the "Software"), to deal 7 | //* in the Software without restriction, including without limitation the rights 8 | //* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | //* copies of the Software, and to permit persons to whom the Software is 10 | //* furnished to do so, subject to the following conditions: 11 | //* 12 | //* The above copyright notice and this permission notice shall be included in 13 | //* all copies or substantial portions of the Software. 14 | //* 15 | //* Use of the Software is limited solely to applications: 16 | //* (a) running on a Xilinx device, or 17 | //* (b) that interact with a Xilinx device through a bus or interconnect. 18 | //* 19 | //* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 | //* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 | //* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 | //* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23 | //* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 24 | //* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25 | //* SOFTWARE. 26 | //* 27 | //* Except as contained in this notice, the name of the Xilinx shall not be used 28 | //* in advertising or otherwise to promote the sale, use or other dealings in 29 | //* this Software without prior written authorization from Xilinx. 30 | //* 31 | //******************************************************************************/ 32 | // 33 | ///* 34 | // * helloworld.c: simple test application 35 | // * 36 | // * This application configures UART 16550 to baud rate 9600. 37 | // * PS7 UART (Zynq) is not initialized by this application, since 38 | // * bootrom/bsp configures it to baud rate 115200 39 | // * 40 | // * ------------------------------------------------ 41 | // * | UART TYPE BAUD RATE | 42 | // * ------------------------------------------------ 43 | // * uartns550 9600 44 | // * uartlite Configurable only in HW design 45 | // * ps7_uart 115200 (configured by bootrom/bsp) 46 | // */ 47 | // 48 | //#include 49 | //#include "platform.h" 50 | //#include "xil_printf.h" 51 | //#include 52 | // 53 | //#define NUMBER_OF_INPUT_WORDS 467 // length of an input vector => 64x7 +8x2 +3x1 54 | //#define NUMBER_OF_OUTPUT_WORDS 64 // length of an input vector 55 | // 56 | //int sigmoid(int sum, int sig_arr[]){ 57 | // for(i = 0; i < 256; i++){ 58 | // if(i == sum){ 59 | // return sig_arr[i]; 60 | // } 61 | // } 62 | //} 63 | // 64 | //void matrix_multiply(int input_arr[], int sig_arr[], int x_rows, int x_cols, int whid_rows, int whid_cols, int wout_rows, int wout_cols, int result[]) { 65 | // // Separate the input array into the three matrices 66 | // int X[x_rows][x_cols]; 67 | // int W_hid[whid_rows][whid_cols]; 68 | // int W_out[wout_rows][wout_cols]; 69 | // int res_hidden[x_rows][whid_cols]; //computes hidden layer x input layer 70 | // 71 | // //printf("input layer\n"); 72 | // for (int i = 0; i < x_rows; i++) { 73 | // for (int j = 0; j < x_cols; j++) { 74 | // X[i][j] = input_arr[i*x_cols + j]; 75 | // //printf("%d\n", X[i][j]); 76 | // } 77 | // } 78 | // //printf("Hidden layer\n"); 79 | // for (int i = 0; i < whid_rows; i++) { 80 | // for (int j = 0; j < whid_cols; j++) { 81 | // W_hid[i][j] = input_arr[x_rows*x_cols + i*whid_cols + j ]; 82 | // //printf("%d\n", W_hid[i][j]); 83 | // } 84 | // } 85 | // //printf("out layer\n"); 86 | // for (int i = 0; i < wout_rows; i++) { 87 | // for (int j = 0; j < wout_cols; j++) { 88 | // W_out[i][j] = input_arr[x_rows*x_cols + whid_rows*whid_cols + i*wout_cols + j ]; 89 | // //printf("%d\n", W_out[i][j]); 90 | // } 91 | // } 92 | // 93 | // //printf("Multiplication layer 1 \n"); 94 | // 95 | // // Perform matrix multiplication on the three matrices 96 | // // Multiply X and W_hid and store the result in result 97 | // for (int i = 0; i < x_rows; i++) { 98 | // for (int j = 0; j < whid_cols; j++) { 99 | // int sum = 0; 100 | // for (int k = 0; k < x_cols; k++) { 101 | // sum += X[i][k] * W_hid[k+1][j]; 102 | // } 103 | // sum /= 256; 104 | // if(j == 0){ 105 | // sum += W_hid[0][0]; //add bias 106 | // } 107 | // else{ 108 | // sum += W_hid[0][1]; 109 | // } 110 | // 111 | // 112 | // res_hidden[i][j] = sigmoid(sum, sig_arr); //activation function 113 | // 114 | // //printf("%0.1f\n", res_hidden[i][j]); 115 | // } 116 | // } 117 | // //printf("Multiplication layer 2\n"); 118 | // // Multiply only the 2nd and 3rd rows of the result with the W_out matrix 119 | // for (int i = 1; i < x_rows; i++) { 120 | // for (int j = 0; j < wout_cols; j++) { 121 | // int sum = 0; 122 | // for (int k = 0; k < whid_cols; k++) { 123 | // sum += res_hidden[i][k] * W_out[k+1][j]; 124 | // } 125 | // sum /= 256; 126 | // sum += W_out[0][0]; 127 | // 128 | // result[i] = sigmoid(sum, sig_arr); 129 | // //if(result[i] >) 130 | // printf("%d\n", result[i]); 131 | // } 132 | // } 133 | //} 134 | // 135 | // 136 | //int main() 137 | //{ 138 | // init_platform(); 139 | // 140 | // int arr[NUMBER_OF_INPUT_WORDS]; 141 | // int result[NUMBER_OF_OUTPUT_WORDS]; 142 | // 143 | // int x_rows = 64; 144 | // int x_cols = 7; 145 | // int whid_rows = 8; 146 | // int whid_cols = 2; 147 | // int wout_rows = 3; 148 | // int wout_cols = 1; 149 | // int sig_arr[256]; 150 | // 151 | // // Scan in Matrix X + W_hid + W_out 152 | // for(int i=0; i < NUMBER_OF_INPUT_WORDS; i++) { 153 | // scanf("%d", &arr[i]); 154 | // //printf("%d\n", arr[i]); 155 | // } 156 | // for(int i = 0; i < 256; i ++){ 157 | // scanf("%d", &sig_arr[i]) 158 | // } 159 | // 160 | // matrix_multiply(arr, sig_arr, x_rows, x_cols, whid_rows, whid_cols, wout_rows, wout_cols, result); 161 | // 162 | // cleanup_platform(); 163 | // return 0; 164 | //} 165 | -------------------------------------------------------------------------------- /Test Inputs/About: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Test Inputs/X.txt: -------------------------------------------------------------------------------- 1 | 44 2 | 159 3 | 167 4 | 130 5 | 34 6 | 63 7 | 88 8 | 185 9 | 140 10 | 73 11 | 16 12 | 31 13 | 183 14 | 129 15 | 190 16 | 79 17 | 213 18 | 13 19 | 103 20 | 42 21 | 26 22 | 69 23 | 143 24 | 73 25 | 100 26 | 110 27 | 165 28 | 182 29 | 34 30 | 108 31 | 18 32 | 35 33 | 72 34 | 27 35 | 149 36 | 138 37 | 120 38 | 183 39 | 38 40 | 180 41 | 86 42 | 219 43 | 31 44 | 21 45 | 111 46 | 224 47 | 231 48 | 140 49 | 116 50 | 43 51 | 39 52 | 103 53 | 83 54 | 73 55 | 159 56 | 14 57 | 37 58 | 225 59 | 64 60 | 44 61 | 153 62 | 86 63 | 138 64 | 19 65 | 90 66 | 250 67 | 158 68 | 178 69 | 112 70 | 28 71 | 214 72 | 203 73 | 255 74 | 90 75 | 93 76 | 110 77 | 181 78 | 193 79 | 183 80 | 113 81 | 213 82 | 94 83 | 175 84 | 82 85 | 90 86 | 90 87 | 225 88 | 87 89 | 136 90 | 136 91 | 143 92 | 207 93 | 51 94 | 85 95 | 70 96 | 165 97 | 99 98 | 85 99 | 166 100 | 180 101 | 97 102 | 181 103 | 113 104 | 188 105 | 87 106 | 224 107 | 65 108 | 134 109 | 62 110 | 206 111 | 225 112 | 146 113 | 191 114 | 136 115 | 76 116 | 166 117 | 148 118 | 41 119 | 136 120 | 77 121 | 70 122 | 171 123 | 177 124 | 54 125 | 170 126 | 155 127 | 160 128 | 0 129 | 0 130 | 140 131 | 172 132 | 136 133 | 142 134 | 145 135 | 157 136 | 170 137 | 110 138 | 164 139 | 187 140 | 120 141 | 155 142 | 104 143 | 143 144 | 115 145 | 149 146 | 127 147 | 164 148 | 104 149 | 109 150 | 101 151 | 125 152 | 125 153 | 254 154 | 101 155 | 179 156 | 131 157 | 194 158 | 116 159 | 110 160 | 120 161 | 85 162 | 85 163 | 176 164 | 136 165 | 115 166 | 183 167 | 125 168 | 169 169 | 80 170 | 155 171 | 145 172 | 48 173 | 128 174 | 128 175 | 139 176 | 106 177 | 196 178 | 131 179 | 130 180 | 170 181 | 206 182 | 150 183 | 93 184 | 160 185 | 131 186 | 136 187 | 76 188 | 166 189 | 150 190 | 136 191 | 104 192 | 140 193 | 0 194 | 176 195 | 134 196 | 120 197 | 112 198 | 126 199 | 140 200 | 110 201 | 136 202 | 118 203 | 88 204 | 77 205 | 175 206 | 159 207 | 124 208 | 111 209 | 159 210 | 146 211 | 139 212 | 83 213 | 143 214 | 180 215 | 147 216 | 29 217 | 119 218 | 137 219 | 151 220 | 105 221 | 94 222 | 25 223 | 118 224 | 72 225 | 76 226 | 109 227 | 111 228 | 131 229 | 96 230 | 152 231 | 67 232 | 137 233 | 72 234 | 165 235 | 38 236 | 83 237 | 89 238 | 155 239 | 174 240 | 124 241 | 136 242 | 58 243 | 63 244 | 115 245 | 120 246 | 63 247 | 153 248 | 67 249 | 53 250 | 148 251 | 69 252 | 93 253 | 125 254 | 41 255 | 119 256 | 139 257 | 24 258 | 121 259 | 172 260 | 135 261 | 163 262 | 190 263 | 205 264 | 211 265 | 133 266 | 75 267 | 162 268 | 166 269 | 135 270 | 184 271 | 139 272 | 164 273 | 133 274 | 132 275 | 187 276 | 167 277 | 135 278 | 125 279 | 196 280 | 8 281 | 170 282 | 186 283 | 167 284 | 130 285 | 90 286 | 24 287 | 179 288 | 126 289 | 210 290 | 122 291 | 135 292 | 255 293 | 110 294 | 119 295 | 88 296 | 188 297 | 76 298 | 197 299 | 112 300 | 94 301 | 163 302 | 167 303 | 149 304 | 192 305 | 192 306 | 44 307 | 71 308 | 236 309 | 142 310 | 123 311 | 140 312 | 68 313 | 72 314 | 136 315 | 92 316 | 158 317 | 152 318 | 36 319 | 149 320 | 217 321 | 81 322 | 183 323 | 161 324 | 121 325 | 159 326 | 165 327 | 174 328 | 138 329 | 156 330 | 121 331 | 101 332 | 101 333 | 211 334 | 183 335 | 138 336 | 101 337 | 199 338 | 150 339 | 147 340 | 50 341 | 220 342 | 222 343 | 197 344 | 87 345 | 140 346 | 174 347 | 156 348 | 101 349 | 94 350 | 0 351 | 138 352 | 72 353 | 101 354 | 133 355 | 115 356 | 139 357 | 128 358 | 174 359 | 26 360 | 124 361 | 73 362 | 252 363 | 32 364 | 78 365 | 209 366 | 170 367 | 202 368 | 142 369 | 170 370 | 50 371 | 62 372 | 131 373 | 156 374 | 78 375 | 149 376 | 72 377 | 46 378 | 161 379 | 92 380 | 101 381 | 171 382 | 131 383 | 124 384 | 161 385 | 22 386 | 138 387 | 118 388 | 86 389 | 43 390 | 66 391 | 128 392 | 126 393 | 131 394 | 111 395 | 27 396 | 45 397 | 185 398 | 161 399 | 145 400 | 88 401 | 183 402 | 89 403 | 128 404 | 71 405 | 106 406 | 108 407 | 121 408 | 67 409 | 77 410 | 126 411 | 147 412 | 124 413 | 58 414 | 59 415 | 50 416 | 82 417 | 56 418 | 54 419 | 98 420 | 84 421 | 44 422 | 148 423 | 68 424 | 145 425 | 71 426 | 218 427 | 78 428 | 111 429 | 65 430 | 150 431 | 208 432 | 104 433 | 108 434 | 118 435 | 39 436 | 75 437 | 102 438 | 51 439 | 198 440 | 56 441 | 37 442 | 188 443 | 84 444 | 59 445 | 166 446 | 63 447 | 100 448 | 51 449 | -------------------------------------------------------------------------------- /Test Inputs/sigmoid.txt: -------------------------------------------------------------------------------- 1 | 12 2 | 12 3 | 12 4 | 12 5 | 13 6 | 13 7 | 13 8 | 14 9 | 14 10 | 14 11 | 15 12 | 15 13 | 15 14 | 16 15 | 16 16 | 16 17 | 17 18 | 17 19 | 18 20 | 18 21 | 18 22 | 19 23 | 19 24 | 20 25 | 20 26 | 21 27 | 21 28 | 21 29 | 22 30 | 22 31 | 23 32 | 23 33 | 24 34 | 24 35 | 25 36 | 26 37 | 26 38 | 27 39 | 27 40 | 28 41 | 28 42 | 29 43 | 30 44 | 30 45 | 31 46 | 32 47 | 32 48 | 33 49 | 34 50 | 34 51 | 35 52 | 36 53 | 36 54 | 37 55 | 38 56 | 39 57 | 39 58 | 40 59 | 41 60 | 42 61 | 43 62 | 44 63 | 44 64 | 45 65 | 46 66 | 47 67 | 48 68 | 49 69 | 50 70 | 51 71 | 52 72 | 53 73 | 54 74 | 55 75 | 56 76 | 57 77 | 58 78 | 59 79 | 60 80 | 61 81 | 62 82 | 63 83 | 64 84 | 66 85 | 67 86 | 68 87 | 69 88 | 70 89 | 72 90 | 73 91 | 74 92 | 75 93 | 76 94 | 78 95 | 79 96 | 80 97 | 82 98 | 83 99 | 84 100 | 86 101 | 87 102 | 88 103 | 90 104 | 91 105 | 92 106 | 94 107 | 95 108 | 97 109 | 98 110 | 99 111 | 101 112 | 102 113 | 104 114 | 105 115 | 107 116 | 108 117 | 110 118 | 111 119 | 113 120 | 114 121 | 116 122 | 117 123 | 119 124 | 120 125 | 122 126 | 123 127 | 125 128 | 126 129 | 128 130 | 129 131 | 130 132 | 132 133 | 133 134 | 135 135 | 136 136 | 138 137 | 139 138 | 141 139 | 142 140 | 144 141 | 145 142 | 147 143 | 148 144 | 150 145 | 151 146 | 153 147 | 154 148 | 156 149 | 157 150 | 158 151 | 160 152 | 161 153 | 163 154 | 164 155 | 165 156 | 167 157 | 168 158 | 169 159 | 171 160 | 172 161 | 173 162 | 175 163 | 176 164 | 177 165 | 179 166 | 180 167 | 181 168 | 182 169 | 183 170 | 185 171 | 186 172 | 187 173 | 188 174 | 189 175 | 191 176 | 192 177 | 193 178 | 194 179 | 195 180 | 196 181 | 197 182 | 198 183 | 199 184 | 200 185 | 201 186 | 202 187 | 203 188 | 204 189 | 205 190 | 206 191 | 207 192 | 208 193 | 209 194 | 210 195 | 211 196 | 211 197 | 212 198 | 213 199 | 214 200 | 215 201 | 216 202 | 216 203 | 217 204 | 218 205 | 219 206 | 219 207 | 220 208 | 221 209 | 221 210 | 222 211 | 223 212 | 223 213 | 224 214 | 225 215 | 225 216 | 226 217 | 227 218 | 227 219 | 228 220 | 228 221 | 229 222 | 229 223 | 230 224 | 231 225 | 231 226 | 232 227 | 232 228 | 233 229 | 233 230 | 234 231 | 234 232 | 234 233 | 235 234 | 235 235 | 236 236 | 236 237 | 237 238 | 237 239 | 237 240 | 238 241 | 238 242 | 239 243 | 239 244 | 239 245 | 240 246 | 240 247 | 240 248 | 241 249 | 241 250 | 241 251 | 242 252 | 242 253 | 242 254 | 243 255 | 243 256 | 243 257 | -------------------------------------------------------------------------------- /Test Inputs/w_hid.txt: -------------------------------------------------------------------------------- 1 | 26 2 | 25 3 | 31 4 | 29 5 | 22 6 | 1 7 | 11 8 | 26 9 | 6 10 | 18 11 | 6 12 | 26 13 | 1 14 | 28 15 | 9 16 | 45 17 | -------------------------------------------------------------------------------- /Test Inputs/w_out.txt: -------------------------------------------------------------------------------- 1 | 80 2 | 50 3 | 200 4 | --------------------------------------------------------------------------------