├── .gitignore ├── DepthMap.bit ├── DepthMap_Exp_SSD_fixed.bit ├── IMG ├── Bat.gif ├── Bat.png ├── Bat2.png ├── Bat2_av_crop.png ├── Bat2_crop.png ├── Bat_av_crop.png ├── Bat_crop.png ├── Bottle.gif ├── Demo_rectified_Colorbal_issue.gif ├── LUT_problem.png ├── assembled.jpg ├── basys3.png ├── cad.png ├── hand.gif ├── ov7670.jpg ├── ov7670.png ├── routing_problm.png ├── studio.gif └── utilization.png ├── LICENSE ├── README.md ├── depthMap.runs ├── impl_1 │ └── DepthMap.bit └── synth_1 │ ├── .Xil │ └── DepthMap_propImpl.xdc │ └── dont_touch.xdc └── depthMap.srcs ├── constrs_1 └── imports │ └── new │ └── basys3_xdc.xdc └── sources_1 ├── imports ├── RGB.vhd ├── address_Generator.vhd ├── clocking.vhd ├── debounce.vhd ├── depthmap.vhd ├── disparity_generator.v ├── disparity_generator.vhd ├── i2c_sender.vhd ├── i3c2.vhd ├── ov7670_capture.vhd ├── ov7670_controller_left.vhd ├── ov7670_controller_right.vhd ├── ov7670_registers_left.vhd ├── ov7670_registers_right.vhd ├── transmitter.v └── vga.vhd └── new └── Image_Rectification.vhd /.gitignore: -------------------------------------------------------------------------------- 1 | ######################################################################################################### 2 | ## This is an example .gitignore file for Vivado, please treat it as an example as 3 | ## it might not be complete. In addition, XAPP 1165 should be followed. 4 | ######################################################################################################### 5 | ######### 6 | #Exclude all 7 | ######### 8 | basys3_ov7670_v1.cache/ 9 | 10 | * 11 | !*/ 12 | !.gitignore 13 | ########################################################################### 14 | ## VIVADO 15 | ########################################################################### 16 | ######### 17 | #Source files: 18 | ######### 19 | #Do NOT ignore VHDL, Verilog, block diagrams or EDIF files. 20 | !*.vhd 21 | !*.v 22 | !*.bd 23 | *.edif 24 | !*.bit 25 | !*.bit 26 | !*.gif 27 | !*.jpg 28 | !*.png 29 | ######### 30 | #IP files 31 | ######### 32 | #.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products 33 | #.xci + .dcp: implementation possible but not re-synthesis 34 | #*.xci(www.spiritconsortium.org) 35 | *.xci 36 | #*.dcp(checkpoint files) 37 | *.dcp 38 | *.vds 39 | *.pb 40 | #All bd comments and layout coordinates are stored within .ui 41 | *.ui 42 | *.ooc 43 | ######### 44 | #System Generator 45 | ######### 46 | *.mdl 47 | *.slx 48 | *.bxml 49 | ######### 50 | #Simulation logic analyzer 51 | ######### 52 | *.wcfg 53 | *.coe 54 | ######### 55 | #MIG 56 | ######### 57 | *.prj 58 | *.mem 59 | ######### 60 | #Project files 61 | ######### 62 | #XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version) 63 | #Do NOT ignore *.xpr files 64 | *.xpr 65 | #Include *.xml files for 2013.4 or earlier version 66 | *.xml 67 | ######### 68 | #Constraint files 69 | ######### 70 | #Do NOT ignore *.xdc files 71 | !*.xdc 72 | ######### 73 | #TCL - files 74 | ######### 75 | *.tcl 76 | ######### 77 | #Journal - files 78 | ######### 79 | *.jou 80 | ######### 81 | #Reports 82 | ######### 83 | *.rpt 84 | *.txt 85 | *.vdi 86 | ######### 87 | #C-files 88 | ######### 89 | *.c 90 | *.h 91 | *.elf 92 | *.bmm 93 | *.xmp -------------------------------------------------------------------------------- /DepthMap.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/DepthMap.bit -------------------------------------------------------------------------------- /DepthMap_Exp_SSD_fixed.bit: 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-------------------------------------------------------------------------------- /IMG/ov7670.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/IMG/ov7670.png -------------------------------------------------------------------------------- /IMG/routing_problm.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/IMG/routing_problm.png -------------------------------------------------------------------------------- /IMG/studio.gif: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/IMG/studio.gif -------------------------------------------------------------------------------- /IMG/utilization.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/IMG/utilization.png -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2020 Aruna Jayasena 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | # DepthMap generation on FPGA 3 | [![DOI](https://zenodo.org/badge/202063958.svg)](https://zenodo.org/badge/latestdoi/202063958) 4 | 5 | ## Cite this work 6 | 7 | Jayasena, A., 2021. Register Transfer Level Disparity generator with Stereo Vision. Journal of Open Research Software, 9(1), p.18. DOI: http://doi.org/10.5334/jors.339 8 | 9 | ``` 10 | Citation (bibtex) [Switch view]@article{Jayasena_2021, 11 | doi = {10.5334/jors.339}, 12 | url = {https://doi.org/10.5334%2Fjors.339}, 13 | year = 2021, 14 | publisher = {Ubiquity Press, Ltd.}, 15 | volume = {9}, 16 | author = {Aruna Jayasena}, 17 | title = {Register Transfer Level Disparity generator with Stereo Vision}, 18 | journal = {Journal of Open Research Software} 19 | } 20 | ``` 21 | 22 | ## About 23 | 24 | Most of the image processing projects in academia has been done on higher-end FPGA's with a considerable amount of resources. The main objective of this project is to implement a reliable embedded system on a lower end FPGA with limited resources. This project is based on Disparity calculation based on SAD (Sum of Absolute Difference) algorithm and creating a depth map. 25 | 26 | 27 | 28 | 29 | Hardware used for this project 30 | 31 | - Basys 3 FPGA board 32 | - 2x OV7670 image sensor modules 33 |
34 |
35 |
36 |
37 | 38 | This project has 3 major sections 39 | 40 | 1. [Functional verification of disparity generator based on Verilog](https://github.com/Archfx/FPGA_depthMap) 41 | 2. [Stereo camera implementation using OV7670 sensors based on VHDL](https://github.com/Archfx/FPGA-stereo-Camera-Basys3) 42 | 3. [Real time disparity generation on Basys3 FPGA](https://github.com/Archfx/FPGA-DepthMap-Basys3) 43 | 44 | 45 | ## Functional verification 46 | 47 | Hardware description languages(HDL) are not meant to be for rapid prototyping. Therefore, in this case, I have used python as the prototyping tool. The SAD algorithm was implemented on python from scratch without using any external library. I refrained from using 2D image arrays to store data because then the HDL implementation is straight forward. 48 | 49 | **SAD/SSD theory** 50 | 51 | Sum of Absolute difference and Sum of Squared Difference Disparity calculation theory is based on a simple geometric concept. Where they use the stereo vision to calculate the distance to the objects. For the implementation, two cameras should be on the same plane and they should not have any vertical offsets in their alignments. 52 | 53 | 54 | 55 | 56 | 57 | **Python implementation** 58 | 59 | The python implementation can be found [here](https://github.com/Archfx/FPGA_depthMap/blob/master/Python_test_implementation/Disparity_Python_implementation_scratch.ipynb) 60 | 61 | Test images used 62 | For the functional verification, I have used the most famous stereo image pair "Tsukuba" stereo pair 63 | 64 | 65 | 66 | 67 |

68 | Left image and Right Tsukuba images 69 |

70 | 71 |
72 |
73 |
74 |
75 |
76 |
77 |
78 |
79 |
80 | 81 |

82 | 83 |

84 | Python results 85 |

86 |

87 | 88 | For this generation, it took more than 4 seconds using an average laptop computer without any accelerating techniques. 89 | Based on the Python implementation Abstract flow chart is generated as follows. 90 | 91 |

92 | 93 |

94 | Disparity generation Flow chart 95 |

96 |

97 | 98 | Then this algorithm is directly ported to Verilog. The implementation was done using ISE design suite by Xilinx. The image files were converted to hex and imported to the simulation and the output is directly saved as a Bitmap image. 99 | 100 | 101 |

102 | 103 |

104 | Timing diagrams at 50MHz 105 |

106 |

107 | 108 |

109 | 110 |

111 | Simulation Output 112 |

113 |

114 | 115 | *** these modules are only for simulation purposes, Do not synthesize the code. 116 | 117 | 118 | ## Stereo Camera implementation 119 | 120 | The cameras that were used for this project is very inexpensive OV7670 modules. They are commonly available and the output can be configured to 8bit parallel. 121 | These cameras are using I2C interface to communicate with the master. We can configure the camera output by changing the internal registers of the cameras. 122 |

123 | 124 |

125 | Pmod connections with Cameras 126 |

127 |

128 |

129 | 130 |

131 | Pmod connector pinouts 132 |

133 |

134 |

135 | 136 |

137 | Basys3 Pmod pinout diagram 138 |

139 |

140 | This repo contains VHDL implementation for image read from two cameras and displaying the average of two images from the VGA output. 141 | 142 | OV7670 dual camera mount was designed using a cad tool and 3D printed to mount the cameras. STL files for camera mount can be found from [here](https://github.com/Archfx/FPGA-stereo-Camera-Basys3/tree/master/CamMountCAD). 143 |

144 | 145 |

146 | CAD Stereo camera mount 147 |

148 |

149 |

150 | 151 |

152 | Hardware connected together 153 |

154 |

155 | 156 | **Camera configuration** 157 | 158 | OV7670 camera module comes with I2C interface to configure it's internal registers. The problem here is we are using two cameras with the same type. By taking the advantage of paralel hardware implementation on FPGA two seperate I2C buses were used for the dual camera intergration. Fortunatly prioir work related to OV7670 Camera intergration to Zedboard FPGA has been done by the Engineer [Mike Field](https://github.com/hamsternz) at [here](http://hamsterworks.co.nz/mediawiki/index.php/OV7670_camera). 159 | This I2C driver was direcly ported to the Basys3 FPGA. Camera register configuration was done inorder to get required output from the Camera. 160 | 161 | ## Real-time depth map generation on FPGA 162 | 163 | When converting the functional verification module into synthesizable code due to limited functionalities in Verilog, VHDL was selected as the developing language. 164 | 165 | **Resource Utilization** 166 | 167 | Basys 3 is a entry level FPGA board. Hence it is not designed for image processing tasks. The Challange here was to run complex image processing algorithm on limited resources. Basys 3 Trainer FPGA board consists of following resources. 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 |
ResourceAvailable
LUT
20800
LUTRAM9600
FF41600
BRAM50
DSP90
IO106
BUFG32
MMCM5
207 | 208 | The main bottle necks were the Block memory and the LUTRAM. Basys 3 has 1,800Kbits of memory in 50 cells as 36,000bits in each cell. We are getting the camera output in YCbCr format. Here Y is the gray scale image of individual pixel size 4bits. 209 | 210 | Memory requirement calculation 211 | For left image : 320x240x4 bits 212 | For right image : 320x240x4 bits 213 | For Average image : 320x240x4 bits 214 | For Disparity image : 320x240x8 bits 215 | Total memory required : 1,536,000 bits/1,800 000 bits 216 | 217 | We cant process them images while it is in the BRAM because BRAM is FIFO (First In First Out) memory device. Therefor the Image sholud be loaded in a cache so that data can be accessed parallely. The cache can be created using the LUTRAM. The problem we have is the LUTRAM is insufficient to store two 320x240 images. Even the 160x120 size images cannot be stored to support SAD algorithm to compare. 218 | 219 |

220 | 221 |

222 | LUT bottleneck for 160x120 resolution 223 |

224 |

225 | 226 | Therefore a blockwise disparity calculation was used in order to utilize the full 320x240 resolution with available resources. The caching is done in block wise and then the caculated dispairty values are saved to the disparity_buffer circuit. 227 | 228 | ```diff 229 | - Although there are 9600 LUTRAMS are available we cannot ulilize 100% of that due to routing issues. 230 | 231 | ``` 232 |

233 | 234 |

235 | Routing failure 236 |

237 |

238 |

239 | 240 |

241 | Blockwise disparity calculation Utilization at 320x240 resolution 242 |

243 |

244 | 245 | **VGA Output** 246 | 247 | The system outputs the generated disparity map using the VGA output of the FPGA. 248 | Following are recorded output from the monitor using a camera. 249 | 250 |

251 | 252 |

253 | Demo -1 254 |

255 |

256 | 257 |

258 | 259 |

260 | Demo -2 261 |

262 |

263 | 264 | In both the demonstrations you may observe that camera exposure changes with the environement changes. Improvements are needed to fix this. It will reduce the noise in the output. 265 | Auto Exposure Correction (AEC) has been disabled from the cameras by editing the internal register modules. After disableing AEC, the result was much more clear and the noise was removed from the background. 266 | 267 | **Image Rectification and Camera Caliberation** 268 | 269 | The offsets of the two cameras are fixed using a image rectification module. Although the Automatic Exposure Caliberation is turned of one of the Cameras output is very darker while the other one is too bright. This should be corrected for the Disparity aldorithm to work correctly. 270 | 271 |

272 | 273 |

274 | Demo -3 ( Left : Disparity output | Right : average image of two cameras ) 275 |

276 |

277 | If we observe closely left camera brightness is too lower than the right hand side camera. 278 | 279 | After caliberation of exposure in cameras individually and improving the Image rectification module final output was in a good condition. There are noice and miss calculated points due to the inability of the cameras to identify the features correctly. But the output is smooth and clear. 280 | 281 |

282 | 283 |

284 | Demo -4 ( Left : Disparity output | Right : average image of two cameras ) 285 |

286 |

287 | 288 |

289 | 290 |

291 | Optimized system demo ( Left : Disparity output | Right : average image of two cameras ) 292 |

293 |

294 | 295 | ## Image rectification 296 | 297 | Due to the physical imperfections of camera mounts and the camera itself, there can be horizontal (X) and Vertical (Y) alignment issues. Initially try to rectify them physically as much as possible and then rectify them by moving the image frames using push buttons on the FPGA. 298 | (BTNL & BTNR -> X | BTNU & BTND -> Y) 299 | -------------------------------------------------------------------------------- /depthMap.runs/impl_1/DepthMap.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/depthMap.runs/impl_1/DepthMap.bit -------------------------------------------------------------------------------- /depthMap.runs/synth_1/.Xil/DepthMap_propImpl.xdc: -------------------------------------------------------------------------------- 1 | set_property SRC_FILE_INFO {cfile:c:/Users/Aruna/Documents/Vivado/DepthMap_implementaion_basys3_320x240_With_UART/depthMap.srcs/sources_1/ip/Clocks/Clocks.xdc rfile:../../../depthMap.srcs/sources_1/ip/Clocks/Clocks.xdc id:1 order:EARLY scoped_inst:Inst_ClockDev/inst} [current_design] 2 | set_property SRC_FILE_INFO {cfile:C:/Users/Aruna/Documents/Vivado/DepthMap_implementaion_basys3_320x240_With_UART/depthMap.srcs/constrs_1/imports/new/basys3_xdc.xdc rfile:../../../depthMap.srcs/constrs_1/imports/new/basys3_xdc.xdc id:2} [current_design] 3 | current_instance Inst_ClockDev/inst 4 | set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] 5 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.1 6 | current_instance 7 | set_property src_info {type:XDC file:2 line:5 export:INPUT save:INPUT read:READ} [current_design] 8 | set_property PACKAGE_PIN W5 [get_ports clk100] 9 | set_property src_info {type:XDC file:2 line:13 export:INPUT save:INPUT read:READ} [current_design] 10 | set_property PACKAGE_PIN G19 [get_ports {vga_r[0]}] 11 | set_property src_info {type:XDC file:2 line:15 export:INPUT save:INPUT read:READ} [current_design] 12 | set_property PACKAGE_PIN H19 [get_ports {vga_r[1]}] 13 | set_property src_info {type:XDC file:2 line:17 export:INPUT save:INPUT read:READ} [current_design] 14 | set_property PACKAGE_PIN J19 [get_ports {vga_r[2]}] 15 | set_property src_info {type:XDC file:2 line:19 export:INPUT save:INPUT read:READ} [current_design] 16 | set_property PACKAGE_PIN N19 [get_ports {vga_r[3]}] 17 | set_property src_info {type:XDC file:2 line:21 export:INPUT save:INPUT read:READ} [current_design] 18 | set_property PACKAGE_PIN N18 [get_ports {vga_b[0]}] 19 | set_property src_info {type:XDC file:2 line:23 export:INPUT save:INPUT read:READ} [current_design] 20 | set_property PACKAGE_PIN L18 [get_ports {vga_b[1]}] 21 | set_property src_info {type:XDC file:2 line:25 export:INPUT save:INPUT read:READ} [current_design] 22 | set_property PACKAGE_PIN K18 [get_ports {vga_b[2]}] 23 | set_property src_info {type:XDC file:2 line:27 export:INPUT save:INPUT read:READ} [current_design] 24 | set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}] 25 | set_property src_info {type:XDC file:2 line:29 export:INPUT save:INPUT read:READ} [current_design] 26 | set_property PACKAGE_PIN J17 [get_ports {vga_g[0]}] 27 | set_property src_info {type:XDC file:2 line:31 export:INPUT save:INPUT read:READ} [current_design] 28 | set_property PACKAGE_PIN H17 [get_ports {vga_g[1]}] 29 | set_property src_info {type:XDC file:2 line:33 export:INPUT save:INPUT read:READ} [current_design] 30 | set_property PACKAGE_PIN G17 [get_ports {vga_g[2]}] 31 | set_property src_info {type:XDC file:2 line:35 export:INPUT save:INPUT read:READ} [current_design] 32 | set_property PACKAGE_PIN D17 [get_ports {vga_g[3]}] 33 | set_property src_info {type:XDC file:2 line:37 export:INPUT save:INPUT read:READ} [current_design] 34 | set_property PACKAGE_PIN P19 [get_ports vga_hsync] 35 | set_property src_info {type:XDC file:2 line:39 export:INPUT save:INPUT read:READ} [current_design] 36 | set_property PACKAGE_PIN R19 [get_ports vga_vsync] 37 | set_property src_info {type:XDC file:2 line:43 export:INPUT save:INPUT read:READ} [current_design] 38 | set_property PACKAGE_PIN U16 [get_ports {config_finished_l}] 39 | set_property src_info {type:XDC file:2 line:46 export:INPUT save:INPUT read:READ} [current_design] 40 | set_property PACKAGE_PIN L1 [get_ports {config_finished_r}] 41 | set_property src_info {type:XDC file:2 line:52 export:INPUT save:INPUT read:READ} [current_design] 42 | set_property PACKAGE_PIN W19 [get_ports btnl] 43 | set_property src_info {type:XDC file:2 line:54 export:INPUT save:INPUT read:READ} [current_design] 44 | set_property PACKAGE_PIN T17 [get_ports btnr] 45 | set_property src_info {type:XDC file:2 line:56 export:INPUT save:INPUT read:READ} [current_design] 46 | set_property PACKAGE_PIN T18 [get_ports btnp] 47 | set_property src_info {type:XDC file:2 line:58 export:INPUT save:INPUT read:READ} [current_design] 48 | set_property PACKAGE_PIN U17 [get_ports btnm] 49 | set_property src_info {type:XDC file:2 line:61 export:INPUT save:INPUT read:READ} [current_design] 50 | set_property PACKAGE_PIN V17 [get_ports {btnc}] 51 | set_property src_info {type:XDC file:2 line:74 export:INPUT save:INPUT read:READ} [current_design] 52 | set_property PACKAGE_PIN A14 [get_ports {ov7670_pwdn_l}] 53 | set_property src_info {type:XDC file:2 line:77 export:INPUT save:INPUT read:READ} [current_design] 54 | set_property PACKAGE_PIN A16 [get_ports {ov7670_data_l[0]}] 55 | set_property src_info {type:XDC file:2 line:80 export:INPUT save:INPUT read:READ} [current_design] 56 | set_property PACKAGE_PIN B15 [get_ports {ov7670_data_l[2]}] 57 | set_property src_info {type:XDC file:2 line:83 export:INPUT save:INPUT read:READ} [current_design] 58 | set_property PACKAGE_PIN B16 [get_ports {ov7670_data_l[4]}] 59 | set_property src_info {type:XDC file:2 line:86 export:INPUT save:INPUT read:READ} [current_design] 60 | set_property PACKAGE_PIN A15 [get_ports {ov7670_reset_l}] 61 | set_property src_info {type:XDC file:2 line:89 export:INPUT save:INPUT read:READ} [current_design] 62 | set_property PACKAGE_PIN A17 [get_ports {ov7670_data_l[1]}] 63 | set_property src_info {type:XDC file:2 line:92 export:INPUT save:INPUT read:READ} [current_design] 64 | set_property PACKAGE_PIN C15 [get_ports {ov7670_data_l[3]}] 65 | set_property src_info {type:XDC file:2 line:95 export:INPUT save:INPUT read:READ} [current_design] 66 | set_property PACKAGE_PIN C16 [get_ports {ov7670_data_l[5]}] 67 | set_property src_info {type:XDC file:2 line:101 export:INPUT save:INPUT read:READ} [current_design] 68 | set_property PACKAGE_PIN K17 [get_ports {ov7670_data_l[6]}] 69 | set_property src_info {type:XDC file:2 line:104 export:INPUT save:INPUT read:READ} [current_design] 70 | set_property PACKAGE_PIN M18 [get_ports ov7670_xclk_l] 71 | set_property src_info {type:XDC file:2 line:107 export:INPUT save:INPUT read:READ} [current_design] 72 | set_property PACKAGE_PIN N17 [get_ports ov7670_href_l] 73 | set_property src_info {type:XDC file:2 line:110 export:INPUT save:INPUT read:READ} [current_design] 74 | set_property PACKAGE_PIN P18 [get_ports ov7670_siod_l] 75 | set_property src_info {type:XDC file:2 line:114 export:INPUT save:INPUT read:READ} [current_design] 76 | set_property PACKAGE_PIN L17 [get_ports {ov7670_data_l[7]}] 77 | set_property src_info {type:XDC file:2 line:117 export:INPUT save:INPUT read:READ} [current_design] 78 | set_property PACKAGE_PIN M19 [get_ports ov7670_pclk_l] 79 | set_property src_info {type:XDC file:2 line:119 export:INPUT save:INPUT read:READ} [current_design] 80 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ov7670_pclk_l_IBUF}] 81 | set_property src_info {type:XDC file:2 line:121 export:INPUT save:INPUT read:READ} [current_design] 82 | set_property PACKAGE_PIN P17 [get_ports ov7670_vsync_l] 83 | set_property src_info {type:XDC file:2 line:124 export:INPUT save:INPUT read:READ} [current_design] 84 | set_property PACKAGE_PIN R18 [get_ports ov7670_sioc_l] 85 | set_property src_info {type:XDC file:2 line:130 export:INPUT save:INPUT read:READ} [current_design] 86 | set_property PACKAGE_PIN J1 [get_ports {ov7670_pwdn_r}] 87 | set_property src_info {type:XDC file:2 line:133 export:INPUT save:INPUT read:READ} [current_design] 88 | set_property PACKAGE_PIN L2 [get_ports {ov7670_data_r[0]}] 89 | set_property src_info {type:XDC file:2 line:136 export:INPUT save:INPUT read:READ} [current_design] 90 | set_property PACKAGE_PIN J2 [get_ports {ov7670_data_r[2]}] 91 | set_property src_info {type:XDC file:2 line:139 export:INPUT save:INPUT read:READ} [current_design] 92 | set_property PACKAGE_PIN G2 [get_ports {ov7670_data_r[4]}] 93 | set_property src_info {type:XDC file:2 line:142 export:INPUT save:INPUT read:READ} [current_design] 94 | set_property PACKAGE_PIN H1 [get_ports {ov7670_reset_r}] 95 | set_property src_info {type:XDC file:2 line:145 export:INPUT save:INPUT read:READ} [current_design] 96 | set_property PACKAGE_PIN K2 [get_ports {ov7670_data_r[1]}] 97 | set_property src_info {type:XDC file:2 line:148 export:INPUT save:INPUT read:READ} [current_design] 98 | set_property PACKAGE_PIN H2 [get_ports {ov7670_data_r[3]}] 99 | set_property src_info {type:XDC file:2 line:151 export:INPUT save:INPUT read:READ} [current_design] 100 | set_property PACKAGE_PIN G3 [get_ports {ov7670_data_r[5]}] 101 | set_property src_info {type:XDC file:2 line:157 export:INPUT save:INPUT read:READ} [current_design] 102 | set_property PACKAGE_PIN J3 [get_ports {ov7670_data_r[6]}] 103 | set_property src_info {type:XDC file:2 line:160 export:INPUT save:INPUT read:READ} [current_design] 104 | set_property PACKAGE_PIN L3 [get_ports ov7670_xclk_r] 105 | set_property src_info {type:XDC file:2 line:163 export:INPUT save:INPUT read:READ} [current_design] 106 | set_property PACKAGE_PIN M2 [get_ports ov7670_href_r] 107 | set_property src_info {type:XDC file:2 line:166 export:INPUT save:INPUT read:READ} [current_design] 108 | set_property PACKAGE_PIN N2 [get_ports ov7670_siod_r] 109 | set_property src_info {type:XDC file:2 line:170 export:INPUT save:INPUT read:READ} [current_design] 110 | set_property PACKAGE_PIN K3 [get_ports {ov7670_data_r[7]}] 111 | set_property src_info {type:XDC file:2 line:173 export:INPUT save:INPUT read:READ} [current_design] 112 | set_property PACKAGE_PIN M3 [get_ports ov7670_pclk_r] 113 | set_property src_info {type:XDC file:2 line:175 export:INPUT save:INPUT read:READ} [current_design] 114 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ov7670_pclk_r_IBUF}] 115 | set_property src_info {type:XDC file:2 line:177 export:INPUT save:INPUT read:READ} [current_design] 116 | set_property PACKAGE_PIN M1 [get_ports ov7670_vsync_r] 117 | set_property src_info {type:XDC file:2 line:180 export:INPUT save:INPUT read:READ} [current_design] 118 | set_property PACKAGE_PIN N1 [get_ports ov7670_sioc_r] 119 | set_property src_info {type:XDC file:2 line:187 export:INPUT save:INPUT read:READ} [current_design] 120 | set_property PACKAGE_PIN A18 [get_ports TxD] 121 | -------------------------------------------------------------------------------- /depthMap.runs/synth_1/dont_touch.xdc: -------------------------------------------------------------------------------- 1 | # This file is automatically generated. 2 | # It contains project source information necessary for synthesis and implementation. 3 | 4 | # XDC: imports/new/basys3_xdc.xdc 5 | 6 | # IP: ip/disparity_ram/disparity_ram.xci 7 | set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==disparity_ram || ORIG_REF_NAME==disparity_ram} -quiet] -quiet 8 | 9 | # IP: ip/frame_buffer/frame_buffer.xci 10 | set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==frame_buffer || ORIG_REF_NAME==frame_buffer} -quiet] -quiet 11 | 12 | # IP: ip/Clocks/Clocks.xci 13 | set_property DONT_TOUCH TRUE [get_cells -hier -filter {REF_NAME==Clocks || ORIG_REF_NAME==Clocks} -quiet] -quiet 14 | 15 | # XDC: ip/disparity_ram/disparity_ram_ooc.xdc 16 | 17 | # XDC: ip/frame_buffer/frame_buffer_ooc.xdc 18 | 19 | # XDC: ip/Clocks/Clocks_board.xdc 20 | set_property DONT_TOUCH TRUE [get_cells [split [join [get_cells -hier -filter {REF_NAME==Clocks || ORIG_REF_NAME==Clocks} -quiet] {/inst } ]/inst ] -quiet] -quiet 21 | 22 | # XDC: ip/Clocks/Clocks.xdc 23 | #dup# set_property DONT_TOUCH TRUE [get_cells [split [join [get_cells -hier -filter {REF_NAME==Clocks || ORIG_REF_NAME==Clocks} -quiet] {/inst } ]/inst ] -quiet] -quiet 24 | 25 | # XDC: ip/Clocks/Clocks_ooc.xdc 26 | -------------------------------------------------------------------------------- /depthMap.srcs/constrs_1/imports/new/basys3_xdc.xdc: -------------------------------------------------------------------------------- 1 | ## Interfacing Basys 3 FPGA with two OV7670 Cameras 2 | ## Pin assignment 3 | 4 | ## Clock signal 5 | set_property PACKAGE_PIN W5 [get_ports clk100] 6 | set_property IOSTANDARD LVCMOS33 [get_ports clk100] 7 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100] 8 | # create_clock -period 10 [get_ports clk100] 9 | #create_clock -name sysclk -waveform {0 5} [get_ports clk100] 10 | # create_clock -name CLK50MHZ -source [get_ports clk100] -divide_by 2 \ [get_pins CLK50MHZ_clk_wiz_0] 11 | #_generated 12 | ##VGA Connector 13 | set_property PACKAGE_PIN G19 [get_ports {vga_r[0]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[0]}] 15 | set_property PACKAGE_PIN H19 [get_ports {vga_r[1]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[1]}] 17 | set_property PACKAGE_PIN J19 [get_ports {vga_r[2]}] 18 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[2]}] 19 | set_property PACKAGE_PIN N19 [get_ports {vga_r[3]}] 20 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_r[3]}] 21 | set_property PACKAGE_PIN N18 [get_ports {vga_b[0]}] 22 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[0]}] 23 | set_property PACKAGE_PIN L18 [get_ports {vga_b[1]}] 24 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[1]}] 25 | set_property PACKAGE_PIN K18 [get_ports {vga_b[2]}] 26 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[2]}] 27 | set_property PACKAGE_PIN J18 [get_ports {vga_b[3]}] 28 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_b[3]}] 29 | set_property PACKAGE_PIN J17 [get_ports {vga_g[0]}] 30 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[0]}] 31 | set_property PACKAGE_PIN H17 [get_ports {vga_g[1]}] 32 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[1]}] 33 | set_property PACKAGE_PIN G17 [get_ports {vga_g[2]}] 34 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[2]}] 35 | set_property PACKAGE_PIN D17 [get_ports {vga_g[3]}] 36 | set_property IOSTANDARD LVCMOS33 [get_ports {vga_g[3]}] 37 | set_property PACKAGE_PIN P19 [get_ports vga_hsync] 38 | set_property IOSTANDARD LVCMOS33 [get_ports vga_hsync] 39 | set_property PACKAGE_PIN R19 [get_ports vga_vsync] 40 | set_property IOSTANDARD LVCMOS33 [get_ports vga_vsync] 41 | 42 | ## LEDs 43 | set_property PACKAGE_PIN U16 [get_ports {config_finished_l}] 44 | set_property IOSTANDARD LVCMOS33 [get_ports {config_finished_l}] 45 | 46 | set_property PACKAGE_PIN L1 [get_ports {config_finished_r}] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {config_finished_r}] 48 | 49 | ##Buttons 50 | #set_property PACKAGE_PIN U18 [get_ports btnc] 51 | # set_property IOSTANDARD LVCMOS33 [get_ports btnc] 52 | set_property PACKAGE_PIN W19 [get_ports btnl] 53 | set_property IOSTANDARD LVCMOS33 [get_ports btnl] 54 | set_property PACKAGE_PIN T17 [get_ports btnr] 55 | set_property IOSTANDARD LVCMOS33 [get_ports btnr] 56 | set_property PACKAGE_PIN T18 [get_ports btnp] 57 | set_property IOSTANDARD LVCMOS33 [get_ports btnp] 58 | set_property PACKAGE_PIN U17 [get_ports btnm] 59 | set_property IOSTANDARD LVCMOS33 [get_ports btnm] 60 | 61 | set_property PACKAGE_PIN V17 [get_ports {btnc}] 62 | set_property IOSTANDARD LVCMOS33 [get_ports {btnc}] 63 | #set_property PACKAGE_PIN V16 [get_ports {btnl}] 64 | # set_property IOSTANDARD LVCMOS33 [get_ports {btnl}] 65 | #set_property PACKAGE_PIN W16 [get_ports {btnr}] 66 | # set_property IOSTANDARD LVCMOS33 [get_ports {btnr}] 67 | 68 | ## OV7670 Camera header pins 69 | 70 | # Switches 71 | 72 | ##Pmod Header JB 73 | ##Sch name = JB1 74 | set_property PACKAGE_PIN A14 [get_ports {ov7670_pwdn_l}] 75 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_pwdn_l}] 76 | ##Sch name = JB2 77 | set_property PACKAGE_PIN A16 [get_ports {ov7670_data_l[0]}] 78 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[0]}] 79 | ##Sch name = JB3 80 | set_property PACKAGE_PIN B15 [get_ports {ov7670_data_l[2]}] 81 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[2]}] 82 | ##Sch name = JB4 83 | set_property PACKAGE_PIN B16 [get_ports {ov7670_data_l[4]}] 84 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[4]}] 85 | ##Sch name = JB7 86 | set_property PACKAGE_PIN A15 [get_ports {ov7670_reset_l}] 87 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_reset_l}] 88 | ##Sch name = JB8 89 | set_property PACKAGE_PIN A17 [get_ports {ov7670_data_l[1]}] 90 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[1]}] 91 | ##Sch name = JB9 92 | set_property PACKAGE_PIN C15 [get_ports {ov7670_data_l[3]}] 93 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[3]}] 94 | ##Sch name = JB10 95 | set_property PACKAGE_PIN C16 [get_ports {ov7670_data_l[5]}] 96 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[5]}] 97 | 98 | 99 | ##Pmod Header JC 100 | ##Sch name = JC1 101 | set_property PACKAGE_PIN K17 [get_ports {ov7670_data_l[6]}] 102 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[6]}] 103 | ##Sch name = JC2 104 | set_property PACKAGE_PIN M18 [get_ports ov7670_xclk_l] 105 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_xclk_l] 106 | ##Sch name = JC3 107 | set_property PACKAGE_PIN N17 [get_ports ov7670_href_l] 108 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_href_l] 109 | ##Sch name = JC4 110 | set_property PACKAGE_PIN P18 [get_ports ov7670_siod_l] 111 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_siod_l] 112 | set_property PULLUP TRUE [get_ports ov7670_siod_l] 113 | ##Sch name = JC7 114 | set_property PACKAGE_PIN L17 [get_ports {ov7670_data_l[7]}] 115 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_l[7]}] 116 | ##Sch name = JC8 117 | set_property PACKAGE_PIN M19 [get_ports ov7670_pclk_l] 118 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_pclk_l] 119 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ov7670_pclk_l_IBUF}] 120 | ##Sch name = JC9 121 | set_property PACKAGE_PIN P17 [get_ports ov7670_vsync_l] 122 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_vsync_l] 123 | ##Sch name = JC10 124 | set_property PACKAGE_PIN R18 [get_ports ov7670_sioc_l] 125 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_sioc_l] 126 | 127 | 128 | ##Pmod Header JA 129 | ##Sch name = JA1 130 | set_property PACKAGE_PIN J1 [get_ports {ov7670_pwdn_r}] 131 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_pwdn_r}] 132 | #Sch name = JA2 133 | set_property PACKAGE_PIN L2 [get_ports {ov7670_data_r[0]}] 134 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[0]}] 135 | #Sch name = JA3 136 | set_property PACKAGE_PIN J2 [get_ports {ov7670_data_r[2]}] 137 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[2]}] 138 | #Sch name = JA4 139 | set_property PACKAGE_PIN G2 [get_ports {ov7670_data_r[4]}] 140 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[4]}] 141 | #Sch name = JA7 142 | set_property PACKAGE_PIN H1 [get_ports {ov7670_reset_r}] 143 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_reset_r}] 144 | #Sch name = JA8 145 | set_property PACKAGE_PIN K2 [get_ports {ov7670_data_r[1]}] 146 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[1]}] 147 | #Sch name = JA9 148 | set_property PACKAGE_PIN H2 [get_ports {ov7670_data_r[3]}] 149 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[3]}] 150 | #Sch name = JA10 151 | set_property PACKAGE_PIN G3 [get_ports {ov7670_data_r[5]}] 152 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[5]}] 153 | 154 | 155 | #Pmod Header JXADC 156 | #Sch name = XA1_P 157 | set_property PACKAGE_PIN J3 [get_ports {ov7670_data_r[6]}] 158 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[6]}] 159 | #Sch name = XA2_P 160 | set_property PACKAGE_PIN L3 [get_ports ov7670_xclk_r] 161 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_xclk_r] 162 | #Sch name = XA3_P 163 | set_property PACKAGE_PIN M2 [get_ports ov7670_href_r] 164 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_href_r] 165 | #Sch name = XA4_P 166 | set_property PACKAGE_PIN N2 [get_ports ov7670_siod_r] 167 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_siod_r] 168 | set_property PULLUP TRUE [get_ports ov7670_siod_r] 169 | #Sch name = XA1_N 170 | set_property PACKAGE_PIN K3 [get_ports {ov7670_data_r[7]}] 171 | set_property IOSTANDARD LVCMOS33 [get_ports {ov7670_data_r[7]}] 172 | #Sch name = XA2_N 173 | set_property PACKAGE_PIN M3 [get_ports ov7670_pclk_r] 174 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_pclk_r] 175 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ov7670_pclk_r_IBUF}] 176 | #Sch name = XA3_N 177 | set_property PACKAGE_PIN M1 [get_ports ov7670_vsync_r] 178 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_vsync_r] 179 | #Sch name = XA4_N 180 | set_property PACKAGE_PIN N1 [get_ports ov7670_sioc_r] 181 | set_property IOSTANDARD LVCMOS33 [get_ports ov7670_sioc_r] 182 | 183 | 184 | ##USB-RS232 Interface 185 | #set_property PACKAGE_PIN B18 [get_ports RxD] 186 | #set_property IOSTANDARD LVCMOS33 [get_ports RxD] 187 | set_property PACKAGE_PIN A18 [get_ports TxD] 188 | set_property IOSTANDARD LVCMOS33 [get_ports TxD] 189 | 190 | set_property BITSTREAM.STARTUP.STARTUPCLK JTAGCLK [current_design] 191 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/RGB.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.ALL; 3 | --use IEEE.STD_LOGIC_ARITH.ALL; 4 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 5 | use IEEE.numeric_std.all; 6 | 7 | 8 | 9 | entity RGB is 10 | Port ( Din : in STD_LOGIC_VECTOR (7 downto 0); 11 | Din_avg : in STD_LOGIC_VECTOR (3 downto 0); 12 | Nblank : in STD_LOGIC; 13 | R,G,B : out STD_LOGIC_VECTOR (7 downto 0); 14 | avg_en : in STD_LOGIC ); 15 | end RGB; 16 | 17 | architecture Behavioral of RGB is 18 | signal vga_out : STD_LOGIC_VECTOR(7 downto 0); 19 | 20 | begin 21 | with avg_en select 22 | vga_out <= Din when '0', 23 | Din_avg & Din_avg when '1'; 24 | 25 | -- R <= (Din) when Nblank='1' and 200<(unsigned(Din)) and avg_en='0' else "00000000"; 26 | -- G <= (Din) when Nblank='1' and 150<(unsigned(Din)) and 220>(unsigned(Din)) and avg_en='0' else "00000000"; 27 | -- B <= (Din) when Nblank='1' and 160>(unsigned(Din)) and avg_en='0' else "00000000"; 28 | 29 | R <= (vga_out) when Nblank='1' else "00000000"; 30 | G <= (vga_out) when Nblank='1' else "00000000"; 31 | B <= (vga_out) when Nblank='1' else "00000000"; 32 | 33 | end Behavioral; 34 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/address_Generator.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/depthMap.srcs/sources_1/imports/address_Generator.vhd -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/clocking.vhd: -------------------------------------------------------------------------------- 1 | -- file: clocking.vhd 2 | -- 3 | -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. 4 | -- 5 | -- This file contains confidential and proprietary information 6 | -- of Xilinx, Inc. and is protected under U.S. and 7 | -- international copyright and other intellectual property 8 | -- laws. 9 | -- 10 | -- DISCLAIMER 11 | -- This disclaimer is not a license and does not grant any 12 | -- rights to the materials distributed herewith. Except as 13 | -- otherwise provided in a valid license issued to you by 14 | -- Xilinx, and to the maximum extent permitted by applicable 15 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | -- (2) Xilinx shall not be liable (whether in contract or tort, 21 | -- including negligence, or under any other theory of 22 | -- liability) for any loss or damage of any kind or nature 23 | -- related to, arising under or in connection with these 24 | -- materials, including for any direct, or any indirect, 25 | -- special, incidental, or consequential loss or damage 26 | -- (including loss of data, profits, goodwill, or any type of 27 | -- loss or damage suffered as a result of any action brought 28 | -- by a third party) even if such damage or loss was 29 | -- reasonably foreseeable or Xilinx had been advised of the 30 | -- possibility of the same. 31 | -- 32 | -- CRITICAL APPLICATIONS 33 | -- Xilinx products are not designed or intended to be fail- 34 | -- safe, or for use in any application requiring fail-safe 35 | -- performance, such as life-support or safety devices or 36 | -- systems, Class III medical devices, nuclear facilities, 37 | -- applications related to the deployment of airbags, or any 38 | -- other applications that could lead to death, personal 39 | -- injury, or severe property or environmental damage 40 | -- (individually and collectively, "Critical 41 | -- Applications"). Customer assumes the sole risk and 42 | -- liability of any use of Xilinx products in Critical 43 | -- Applications, subject only to applicable laws and 44 | -- regulations governing limitations on product liability. 45 | -- 46 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | -- PART OF THIS FILE AT ALL TIMES. 48 | -- 49 | ------------------------------------------------------------------------------ 50 | -- User entered comments 51 | ------------------------------------------------------------------------------ 52 | -- None 53 | -- 54 | ------------------------------------------------------------------------------ 55 | -- "Output Output Phase Duty Pk-to-Pk Phase" 56 | -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" 57 | ------------------------------------------------------------------------------ 58 | -- CLK_OUT1____50.000______0.000______50.0______151.636_____98.575 59 | -- CLK_OUT2____25.000______0.000______50.0______175.402_____98.575 60 | -- 61 | ------------------------------------------------------------------------------ 62 | -- "Input Clock Freq (MHz) Input Jitter (UI)" 63 | ------------------------------------------------------------------------------ 64 | -- __primary_________100.000____________0.010 65 | 66 | library ieee; 67 | use ieee.std_logic_1164.all; 68 | use ieee.std_logic_unsigned.all; 69 | use ieee.std_logic_arith.all; 70 | use ieee.numeric_std.all; 71 | 72 | library unisim; 73 | use unisim.vcomponents.all; 74 | 75 | entity clocking is 76 | port 77 | (-- Clock in ports 78 | CLK_100 : in std_logic; 79 | -- Clock out ports 80 | CLK_50 : out std_logic; 81 | CLK_25 : out std_logic 82 | ); 83 | end clocking; 84 | 85 | architecture xilinx of clocking is 86 | attribute CORE_GENERATION_INFO : string; 87 | attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}"; 88 | -- Input clock buffering / unused connectors 89 | signal clkin1 : std_logic; 90 | -- Output clock buffering / unused connectors 91 | signal clkfbout : std_logic; 92 | signal clkfbout_buf : std_logic; 93 | signal clkfboutb_unused : std_logic; 94 | signal clkout0 : std_logic; 95 | signal clkout0b_unused : std_logic; 96 | signal clkout1 : std_logic; 97 | signal clkout1b_unused : std_logic; 98 | signal clkout2_unused : std_logic; 99 | signal clkout2b_unused : std_logic; 100 | signal clkout3_unused : std_logic; 101 | signal clkout3b_unused : std_logic; 102 | signal clkout4_unused : std_logic; 103 | signal clkout5_unused : std_logic; 104 | signal clkout6_unused : std_logic; 105 | -- Dynamic programming unused signals 106 | signal do_unused : std_logic_vector(15 downto 0); 107 | signal drdy_unused : std_logic; 108 | -- Dynamic phase shift unused signals 109 | signal psdone_unused : std_logic; 110 | -- Unused status signals 111 | signal locked_unused : std_logic; 112 | signal clkfbstopped_unused : std_logic; 113 | signal clkinstopped_unused : std_logic; 114 | begin 115 | 116 | 117 | -- Input buffering 118 | -------------------------------------- 119 | clkin1_buf : IBUFG 120 | port map 121 | (O => clkin1, 122 | I => CLK_100); 123 | 124 | 125 | -- Clocking primitive 126 | -------------------------------------- 127 | -- Instantiation of the MMCM primitive 128 | -- * Unused inputs are tied off 129 | -- * Unused outputs are labeled unused 130 | mmcm_adv_inst : MMCME2_ADV 131 | generic map 132 | (BANDWIDTH => "OPTIMIZED", 133 | CLKOUT4_CASCADE => FALSE, 134 | COMPENSATION => "ZHOLD", 135 | STARTUP_WAIT => FALSE, 136 | DIVCLK_DIVIDE => 1, 137 | CLKFBOUT_MULT_F => 10.000, 138 | CLKFBOUT_PHASE => 0.000, 139 | CLKFBOUT_USE_FINE_PS => FALSE, 140 | CLKOUT0_DIVIDE_F => 20.000, 141 | CLKOUT0_PHASE => 0.000, 142 | CLKOUT0_DUTY_CYCLE => 0.500, 143 | CLKOUT0_USE_FINE_PS => FALSE, 144 | CLKOUT1_DIVIDE => 40, 145 | CLKOUT1_PHASE => 0.000, 146 | CLKOUT1_DUTY_CYCLE => 0.500, 147 | CLKOUT1_USE_FINE_PS => FALSE, 148 | CLKIN1_PERIOD => 10.000, 149 | REF_JITTER1 => 0.010) 150 | port map 151 | -- Output clocks 152 | (CLKFBOUT => clkfbout, 153 | CLKFBOUTB => clkfboutb_unused, 154 | CLKOUT0 => clkout0, 155 | CLKOUT0B => clkout0b_unused, 156 | CLKOUT1 => clkout1, 157 | CLKOUT1B => clkout1b_unused, 158 | CLKOUT2 => clkout2_unused, 159 | CLKOUT2B => clkout2b_unused, 160 | CLKOUT3 => clkout3_unused, 161 | CLKOUT3B => clkout3b_unused, 162 | CLKOUT4 => clkout4_unused, 163 | CLKOUT5 => clkout5_unused, 164 | CLKOUT6 => clkout6_unused, 165 | -- Input clock control 166 | CLKFBIN => clkfbout_buf, 167 | CLKIN1 => clkin1, 168 | CLKIN2 => '0', 169 | -- Tied to always select the primary input clock 170 | CLKINSEL => '1', 171 | -- Ports for dynamic reconfiguration 172 | DADDR => (others => '0'), 173 | DCLK => '0', 174 | DEN => '0', 175 | DI => (others => '0'), 176 | DO => do_unused, 177 | DRDY => drdy_unused, 178 | DWE => '0', 179 | -- Ports for dynamic phase shift 180 | PSCLK => '0', 181 | PSEN => '0', 182 | PSINCDEC => '0', 183 | PSDONE => psdone_unused, 184 | -- Other control and status signals 185 | LOCKED => locked_unused, 186 | CLKINSTOPPED => clkinstopped_unused, 187 | CLKFBSTOPPED => clkfbstopped_unused, 188 | PWRDWN => '0', 189 | RST => '0'); 190 | 191 | -- Output buffering 192 | ------------------------------------- 193 | clkf_buf : BUFG 194 | port map 195 | (O => clkfbout_buf, 196 | I => clkfbout); 197 | 198 | 199 | clkout1_buf : BUFG 200 | port map 201 | (O => CLK_50, 202 | I => clkout0); 203 | 204 | 205 | 206 | clkout2_buf : BUFG 207 | port map 208 | (O => CLK_25, 209 | I => clkout1); 210 | 211 | end xilinx; 212 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/debounce.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Mike Field 3 | -- 4 | -- Description: Convert the push button to a 1PPS that can be used to restart 5 | -- camera initialisation 6 | ---------------------------------------------------------------------------------- 7 | library IEEE; 8 | use IEEE.STD_LOGIC_1164.ALL; 9 | use IEEE.NUMERIC_STD.ALL; 10 | 11 | entity debounce is 12 | Port ( clk : in STD_LOGIC; 13 | i : in STD_LOGIC; 14 | o : out STD_LOGIC); 15 | end debounce; 16 | 17 | architecture Behavioral of debounce is 18 | signal c : unsigned(23 downto 0); 19 | begin 20 | process(clk) 21 | begin 22 | if rising_edge(clk) then 23 | if i = '1' then 24 | if c = x"FFFFFF" then 25 | o <= '1'; 26 | else 27 | o <= '0'; 28 | end if; 29 | c <= c+1; 30 | else 31 | c <= (others => '0'); 32 | o <= '0'; 33 | end if; 34 | end if; 35 | end process; 36 | 37 | end Behavioral; 38 | 39 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/depthmap.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Aruna Jayasena 3 | -- 4 | -- Module Name: DepthMap - Behavioral 5 | -- Description: Top level module For the disparity implementation using dual OV7670 camara modules on Basys 3 6 | -- 7 | ---------------------------------------------------------------------------------- 8 | library IEEE; 9 | use IEEE.STD_LOGIC_1164.ALL; 10 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 11 | use IEEE.numeric_std.all; 12 | 13 | 14 | entity DepthMap is 15 | Port ( clk100 : in STD_LOGIC; 16 | btnl : in STD_LOGIC; 17 | btnc : in STD_LOGIC; 18 | btnr : in STD_LOGIC; 19 | btnp : in STD_LOGIC; 20 | btnm : in STD_LOGIC; 21 | config_finished_l : out STD_LOGIC; 22 | config_finished_r : out STD_LOGIC; 23 | 24 | vga_hsync : out STD_LOGIC; 25 | vga_vsync : out STD_LOGIC; 26 | vga_r : out STD_LOGIC_vector(3 downto 0); 27 | vga_g : out STD_LOGIC_vector(3 downto 0); 28 | vga_b : out STD_LOGIC_vector(3 downto 0); 29 | 30 | ov7670_pclk_l : in STD_LOGIC; 31 | ov7670_xclk_l : out STD_LOGIC; 32 | ov7670_vsync_l : in STD_LOGIC; 33 | ov7670_href_l : in STD_LOGIC; 34 | ov7670_data_l : in STD_LOGIC_vector(7 downto 0); 35 | ov7670_sioc_l : out STD_LOGIC; 36 | ov7670_siod_l : inout STD_LOGIC; 37 | ov7670_pwdn_l : out STD_LOGIC; 38 | ov7670_reset_l : out STD_LOGIC; 39 | 40 | ov7670_pclk_r : in STD_LOGIC; 41 | ov7670_xclk_r : out STD_LOGIC; 42 | ov7670_vsync_r : in STD_LOGIC; 43 | ov7670_href_r : in STD_LOGIC; 44 | ov7670_data_r : in STD_LOGIC_vector(7 downto 0); 45 | ov7670_sioc_r : out STD_LOGIC; 46 | ov7670_siod_r : inout STD_LOGIC; 47 | ov7670_pwdn_r : out STD_LOGIC; 48 | ov7670_reset_r : out STD_LOGIC; 49 | 50 | TxD : out STD_LOGIC 51 | ); 52 | end DepthMap; 53 | 54 | architecture Behavioral of DepthMap is 55 | 56 | COMPONENT VGA 57 | PORT( 58 | CLK25 : IN std_logic; 59 | rez_160x120 : IN std_logic; 60 | rez_320x240 : IN std_logic; 61 | Hsync : OUT std_logic; 62 | Vsync : OUT std_logic; 63 | Nblank : OUT std_logic; 64 | clkout : OUT std_logic; 65 | activeArea : OUT std_logic; 66 | Nsync : OUT std_logic; 67 | avg_en : out STD_LOGIC 68 | ); 69 | END COMPONENT; 70 | 71 | COMPONENT ov7670_controller_left 72 | PORT( 73 | clk : IN std_logic; 74 | resend : IN std_logic; 75 | siod : INOUT std_logic; 76 | config_finished : OUT std_logic; 77 | sioc : OUT std_logic; 78 | reset : OUT std_logic; 79 | pwdn : OUT std_logic; 80 | xclk : OUT std_logic 81 | ); 82 | END COMPONENT; 83 | 84 | COMPONENT ov7670_controller_right 85 | PORT( 86 | clk : IN std_logic; 87 | resend : IN std_logic; 88 | exposure : in STD_LOGIC_VECTOR (15 downto 0); 89 | siod : INOUT std_logic; 90 | config_finished : OUT std_logic; 91 | sioc : OUT std_logic; 92 | reset : OUT std_logic; 93 | pwdn : OUT std_logic; 94 | xclk : OUT std_logic 95 | ); 96 | END COMPONENT; 97 | 98 | 99 | COMPONENT debounce 100 | PORT( 101 | clk : IN std_logic; 102 | i : IN std_logic; 103 | o : OUT std_logic 104 | ); 105 | END COMPONENT; 106 | 107 | COMPONENT frame_buffer 108 | PORT ( 109 | clka : IN STD_LOGIC; 110 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 111 | addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); 112 | dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 113 | clkb : IN STD_LOGIC; 114 | enb : IN STD_LOGIC; 115 | addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0); 116 | doutb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) 117 | ); 118 | END COMPONENT; 119 | 120 | COMPONENT disparity_ram 121 | PORT ( 122 | clka : IN STD_LOGIC; 123 | wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); 124 | addra : IN STD_LOGIC_VECTOR(16 DOWNTO 0); 125 | dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); 126 | clkb : IN STD_LOGIC; 127 | addrb : IN STD_LOGIC_VECTOR(16 DOWNTO 0); 128 | doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) 129 | ); 130 | END COMPONENT; 131 | 132 | COMPONENT ov7670_capture 133 | PORT( 134 | rez_160x120 : IN std_logic; 135 | rez_320x240 : IN std_logic; 136 | pclk : IN std_logic; 137 | vsync : IN std_logic; 138 | href : IN std_logic; 139 | d : IN std_logic_vector(7 downto 0); 140 | addr : OUT std_logic_vector(16 downto 0); 141 | dout : OUT std_logic_vector(11 downto 0); 142 | we : OUT std_logic 143 | ); 144 | END COMPONENT; 145 | 146 | COMPONENT RGB 147 | PORT( 148 | Din : IN std_logic_vector(7 downto 0); 149 | Din_avg : IN std_logic_vector(3 downto 0); 150 | Nblank : IN std_logic; 151 | R : OUT std_logic_vector(7 downto 0); 152 | G : OUT std_logic_vector(7 downto 0); 153 | B : OUT std_logic_vector(7 downto 0); 154 | avg_en : in STD_LOGIC 155 | ); 156 | END COMPONENT; 157 | 158 | component Clocks 159 | port ( 160 | clk_in1 : in std_logic; 161 | -- Clock out ports 162 | CLK50MHZ : out std_logic; 163 | CLK25MHZ : out std_logic; 164 | CLK_MAIN : out std_logic); 165 | end component; 166 | 167 | COMPONENT vga_pll 168 | PORT( 169 | inclk0 : IN std_logic; 170 | c0 : OUT std_logic; 171 | c1 : OUT std_logic 172 | ); 173 | END COMPONENT; 174 | 175 | COMPONENT Transmitter 176 | PORT( 177 | clk : IN std_logic; 178 | reset : IN std_logic; 179 | transmit : IN std_logic; 180 | data : IN STD_LOGIC_VECTOR (7 downto 0); 181 | TxD : OUT std_logic 182 | ); 183 | END COMPONENT; 184 | 185 | COMPONENT Address_Generator 186 | PORT( 187 | CLK : IN std_logic; 188 | rez_160x120 : IN std_logic; 189 | rez_320x240 : IN std_logic; 190 | enable : IN std_logic; 191 | vsync : in STD_LOGIC; 192 | avg_en : in STD_LOGIC; 193 | address : OUT std_logic_vector(16 downto 0) 194 | ); 195 | END COMPONENT; 196 | 197 | COMPONENT Image_Rectification 198 | PORT( 199 | address_in : in STD_LOGIC_VECTOR (16 downto 0); 200 | plus : in STD_LOGIC; 201 | minus : in STD_LOGIC; 202 | plus_col : in STD_LOGIC; 203 | minus_col : in STD_LOGIC; 204 | CLK : in STD_LOGIC; 205 | exposure : out STD_LOGIC_VECTOR (15 downto 0); 206 | address_left : out STD_LOGIC_VECTOR (16 downto 0); 207 | address_right : out STD_LOGIC_VECTOR (16 downto 0)); 208 | END COMPONENT; 209 | 210 | COMPONENT disparity_generator 211 | PORT( 212 | CLK_MAIN : in STD_LOGIC; 213 | HCLK : IN std_logic; 214 | -- HRESETn : IN std_logic; 215 | left_in : IN std_logic_vector(3 downto 0); 216 | right_in : IN std_logic_vector(3 downto 0); 217 | avg_out : OUT STD_LOGIC_vector(3 downto 0); 218 | dOUT : OUT std_logic_vector(7 downto 0); 219 | left_right_addr : OUT std_logic_vector(16 downto 0); 220 | -- right_addr : OUT std_logic_vector(16 downto 0); 221 | dOUT_addr : OUT std_logic_vector(16 downto 0); 222 | avg_reg_en : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); 223 | wr_en : OUT std_logic_vector(0 downto 0) 224 | 225 | 226 | 227 | 228 | ); 229 | END COMPONENT; 230 | 231 | 232 | signal CLK_MAIN : std_logic; 233 | signal clk_camera : std_logic; 234 | signal clk_vga : std_logic; 235 | signal wren_l,wren_r,avg_reg_en : std_logic_vector(0 downto 0); 236 | signal resend : std_logic; 237 | signal nBlank : std_logic; 238 | signal vSync : std_logic; 239 | signal nSync : std_logic; 240 | 241 | signal wraddress_l : std_logic_vector(16 downto 0); 242 | signal wrdata_l : std_logic_vector(11 downto 0); 243 | signal wraddress_r : std_logic_vector(16 downto 0); 244 | signal wrdata_r : std_logic_vector(11 downto 0); 245 | 246 | signal rdaddress_l : std_logic_vector(16 downto 0); 247 | signal rddata_l : std_logic_vector(3 downto 0); 248 | signal rdaddress_r : std_logic_vector(16 downto 0); 249 | signal rddata_r : std_logic_vector(3 downto 0); 250 | signal avg_out : std_logic_vector(3 downto 0); 251 | signal din_avg : std_logic_vector(3 downto 0); 252 | signal avg_en : std_logic; 253 | 254 | signal exposure : std_logic_vector(15 downto 0); 255 | signal plus_deb,plus_col_deb : std_logic; 256 | signal minus_deb,minus_col_deb : std_logic; 257 | 258 | signal disparity_out : std_logic_vector(7 downto 0); 259 | signal rdaddress_disp : std_logic_vector(16 downto 0); 260 | signal rddisp : std_logic_vector(7 downto 0); 261 | signal wr_address_disp : std_logic_vector(16 downto 0); 262 | signal wr_en : std_logic_vector(0 downto 0); 263 | signal left_right_addr,address_left,address_right : std_logic_vector(16 downto 0); 264 | signal red,green,blue : std_logic_vector(7 downto 0); 265 | signal activeArea : std_logic; 266 | 267 | signal rez_160x120 : std_logic; 268 | signal rez_320x240 : std_logic; 269 | signal size_select: std_logic_vector(1 downto 0); 270 | signal rd_addr_l,wr_addr_l,rd_addr_r,wr_addr_r : std_logic_vector(16 downto 0); 271 | begin 272 | vga_r <= red(7 downto 4); 273 | vga_g <= green(7 downto 4); 274 | vga_b <= blue(7 downto 4); 275 | 276 | rez_160x120 <= '0'; 277 | rez_320x240 <= '1'; 278 | 279 | Inst_ClockDev : Clocks 280 | port map 281 | (-- Clock in ports 282 | clk_in1 => CLK100, 283 | -- Clock out ports 284 | CLK_MAIN =>CLK_MAIN, 285 | CLK50MHZ => CLK_camera, 286 | CLK25MHZ => CLK_vga); 287 | 288 | 289 | vga_vsync <= vsync; 290 | 291 | Inst_VGA: VGA PORT MAP( 292 | CLK25 => clk_vga, 293 | rez_160x120 => rez_160x120, 294 | rez_320x240 => rez_320x240, 295 | clkout => open, 296 | Hsync => vga_hsync, 297 | Vsync => vsync, 298 | Nblank => nBlank, 299 | Nsync => nsync, 300 | activeArea => activeArea, 301 | avg_en => avg_en 302 | ); 303 | 304 | Inst_debounce: debounce PORT MAP( 305 | clk => CLK_MAIN, 306 | i => btnc, 307 | o => resend 308 | ); 309 | 310 | -- Inst_debounce_plus: debounce PORT MAP( 311 | -- clk => CLK_MAIN, 312 | -- i => btnr, 313 | -- o => plus_deb 314 | -- ); 315 | 316 | -- Inst_debounce_minus: debounce PORT MAP( 317 | -- clk => CLK_MAIN, 318 | -- i => btnl, 319 | -- o => minus_deb 320 | -- ); 321 | 322 | -- Inst_debounce_plus_col: debounce PORT MAP( 323 | -- clk => CLK_MAIN, 324 | -- i => btnp, 325 | -- o => plus_col_deb 326 | -- ); 327 | 328 | -- Inst_debounce_minus_col: debounce PORT MAP( 329 | -- clk => CLK_MAIN, 330 | -- i => btnm, 331 | -- o => minus_col_deb 332 | -- ); 333 | 334 | Inst_ov7670_controller_left: ov7670_controller_left PORT MAP( 335 | clk => clk_camera, 336 | resend => resend, 337 | config_finished => config_finished_l, 338 | sioc => ov7670_sioc_l, 339 | siod => ov7670_siod_l, 340 | reset => ov7670_reset_l, 341 | pwdn => ov7670_pwdn_l, 342 | xclk => ov7670_xclk_l 343 | ); 344 | 345 | Inst_ov7670_controller_right: ov7670_controller_right PORT MAP( 346 | clk => clk_camera, 347 | resend => resend, 348 | exposure => exposure, 349 | config_finished => config_finished_r, 350 | sioc => ov7670_sioc_r, 351 | siod => ov7670_siod_r, 352 | reset => ov7670_reset_r, 353 | pwdn => ov7670_pwdn_r, 354 | xclk => ov7670_xclk_r 355 | ); 356 | 357 | -- size_select <= rez_160x120&rez_320x240; 358 | 359 | --with size_select select 360 | rd_addr_l <= --rdaddress_l(18 downto 2) when "00", 361 | rdaddress_l(16 downto 0);-- when "01", 362 | -- rdaddress_l(16 downto 0) when "10", 363 | -- rdaddress_l(16 downto 0) when "11"; 364 | -- with size_select select 365 | rd_addr_r <= --rdaddress_r(18 downto 2) when "00", 366 | rdaddress_r(16 downto 0);-- when "01", 367 | -- rdaddress_r(16 downto 0) when "10", 368 | -- rdaddress_r(16 downto 0) when "11"; 369 | -- with size_select select 370 | wr_addr_r <= --wraddress_r(18 downto 2) when "00", 371 | wraddress_r(16 downto 0);-- when "01", 372 | -- wraddress_r(16 downto 0) when "10", 373 | -- wraddress_r(16 downto 0) when "11"; 374 | --with size_select select 375 | wr_addr_l <= --wraddress_l(18 downto 2) when "00", 376 | wraddress_l(16 downto 0);-- when "01", 377 | -- wraddress_l(16 downto 0) when "10", 378 | -- wraddress_l(16 downto 0) when "11"; 379 | 380 | Inst_frame_buffer_l: frame_buffer PORT MAP( 381 | addrb => address_left, 382 | clkb => clk_camera,--CLK100, 383 | doutb => rddata_l, 384 | enb =>'1', 385 | clka => ov7670_pclk_l, 386 | addra => wr_addr_l, 387 | dina => wrdata_l(7 downto 4), 388 | wea => wren_l 389 | ); 390 | 391 | Inst_frame_buffer_r: frame_buffer PORT MAP( 392 | addrb => address_right, 393 | clkb => clk_camera, --CLK100, 394 | doutb => rddata_r, 395 | enb =>'1', 396 | clka => ov7670_pclk_r, 397 | addra => wr_addr_r, 398 | dina => wrdata_r(7 downto 4), 399 | wea => wren_r 400 | ); 401 | 402 | Inst_frame_buffer_avg: frame_buffer PORT MAP( 403 | addrb => rdaddress_disp, 404 | clkb => clk_vga, --CLK100, 405 | doutb => din_avg, 406 | enb =>'1', 407 | clka => CLK_MAIN, 408 | addra => left_right_addr, 409 | dina => avg_out, 410 | wea => avg_reg_en 411 | ); 412 | 413 | Inst_disparity_buffer: disparity_ram PORT MAP( 414 | addrb => rdaddress_disp, 415 | clkb => clk_vga, 416 | doutb => rddisp, 417 | clka => CLK_MAIN,--CLK_camera, --CLK100, 418 | addra => wr_address_disp, 419 | dina => disparity_out, 420 | wea => wr_en 421 | ); 422 | 423 | Inst_Transmitter: Transmitter PORT MAP( 424 | clk => CLK_MAIN, 425 | reset => '0', 426 | transmit => '1', 427 | data => "10101011", 428 | TxD => TxD 429 | 430 | ); 431 | 432 | Inst_ov7670_capture_l: ov7670_capture PORT MAP( 433 | pclk => ov7670_pclk_l, 434 | rez_160x120 => rez_160x120, 435 | rez_320x240 => rez_320x240, 436 | vsync => ov7670_vsync_l, 437 | href => ov7670_href_l, 438 | d => ov7670_data_l, 439 | addr => wraddress_l, 440 | dout => wrdata_l, 441 | we => wren_l(0) 442 | ); 443 | 444 | Inst_ov7670_capture_r: ov7670_capture PORT MAP( 445 | pclk => ov7670_pclk_r, 446 | rez_160x120 => rez_160x120, 447 | rez_320x240 => rez_320x240, 448 | vsync => ov7670_vsync_r, 449 | href => ov7670_href_r, 450 | d => ov7670_data_r, 451 | addr => wraddress_r, 452 | dout => wrdata_r, 453 | we => wren_r(0) 454 | ); 455 | 456 | Inst_RGB: RGB PORT MAP( 457 | Din => rddisp, 458 | Din_avg =>din_avg, 459 | Nblank => activeArea, 460 | R => red, 461 | G => green, 462 | B => blue, 463 | avg_en => avg_en 464 | ); 465 | 466 | Inst_Address_Generator: Address_Generator PORT MAP( 467 | CLK => clk_vga, 468 | rez_160x120 => rez_160x120, 469 | rez_320x240 => rez_320x240, 470 | enable => activeArea, 471 | vsync => vsync, 472 | avg_en => avg_en, 473 | address => rdaddress_disp 474 | ); 475 | 476 | Inst_rectification: Image_Rectification PORT MAP( 477 | address_in => left_right_addr, 478 | plus =>btnr,--plus_deb, 479 | minus => btnl,--minus_deb, 480 | plus_col=>btnp, 481 | minus_col =>btnm, 482 | CLK => clk_camera, 483 | exposure => exposure, 484 | address_left => address_left, 485 | address_right => address_right 486 | ); 487 | 488 | 489 | Inst_disparity_generator: disparity_generator PORT MAP( 490 | HCLK=> clk_camera,--CLK100, 491 | CLK_MAIN=>CLK_MAIN, 492 | left_in => rddata_l, 493 | right_in => rddata_r, 494 | avg_out => avg_out, 495 | dOUT => disparity_out, 496 | dOUT_addr => wr_address_disp, 497 | wr_en => wr_en, 498 | avg_reg_en => avg_reg_en, 499 | left_right_addr =>left_right_addr 500 | ); 501 | end Behavioral; 502 | 503 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/disparity_generator.v: -------------------------------------------------------------------------------- 1 | 2 | /******************************************************************************/ 3 | /****************** Module for processing image **************/ 4 | /******************************************************************************/ 5 | //`include "parameter.v" // Include definition file 6 | module disparity_generator 7 | #( 8 | parameter WIDTH = 320, // Image width 9 | HEIGHT = 240, // Image height 10 | // INFILE_L = "Tsukuba_L.hex", // image file 11 | // INFILE_R = "Tsukuba_R.hex", // image file 12 | START_UP_DELAY = 100, // Delay during start up time 13 | HSYNC_DELAY = 160, // Delay between HSYNC pulses 14 | VALUE= 100 // value for Brightness operation 15 | // THRESHOLD= 90, // Threshold value for Threshold operation 16 | // SIGN=0 // Sign value using for brightness operation 17 | // SIGN = 0: Brightness subtraction 18 | // SIGN = 1: Brightness addition 19 | ) 20 | ( 21 | input HCLK, // clock 22 | input [3:0] left_in, 23 | input [3:0] right_in, 24 | output [3:0] dOUT, // Disparity out (even) 25 | output [16:0] dOUT_addr, // Disparity out (even) 26 | output [16:0] left_right_addr, 27 | // output [16:0] right_addr, 28 | output reg ctrl_done, 29 | output reg offsetfound // Done flag 30 | 31 | 32 | ); 33 | 34 | reg ctrl_data_run; // control signal for data processing 35 | 36 | 37 | reg [0 : (WIDTH*HEIGHT - 1)*4] org_L; // temporary storage for Left image 38 | reg [0 : (WIDTH*HEIGHT - 1)*4] org_R ; // temporary storage for Right image 39 | 40 | reg [8:0] row; // row index of the image 41 | reg [8:0] col; // column index of the Left image 42 | parameter window = 5; 43 | integer x,y; // column index of the Right image 44 | reg [3:0] offset, best_offset;//, best_offset_1; 45 | localparam [4:0] maxoffset = 10; // Maximum extent where to look for the same pixel 46 | reg offsetfound; 47 | reg offsetping; 48 | reg compare; 49 | reg [20:0] ssd;//, ssd_1; // sum of squared difference 50 | reg [20:0] prev_ssd;//, prev_ssd_1; 51 | reg [16:0] data_count; // data counting for entire pixels of the image 52 | reg [16:0] readreg; 53 | reg doneFetch; 54 | 55 | assign dOUT_addr= data_count; 56 | assign left_right_addr=readreg; 57 | assign dOUT=best_offset; 58 | 59 | always@(posedge HCLK) begin 60 | if (~doneFetch) begin 61 | if (readreg<76800) begin 62 | org_L[readreg*4+:4]<= left_in; 63 | org_R[readreg*4+:4]<= right_in; 64 | readreg=readreg+1; 65 | end 66 | else begin 67 | readreg <= 0; 68 | doneFetch <=1; 69 | end 70 | end 71 | 72 | //2 73 | if(ctrl_done) begin 74 | data_count <= 0; 75 | end 76 | else begin 77 | if(ctrl_data_run) 78 | data_count <= data_count + 1; 79 | end 80 | 81 | ctrl_done <= (data_count == 308487)? 1'b1: 1'b0; // done flag308472 82 | if (ctrl_done) doneFetch=0; 83 | 84 | //2 85 | 86 | //3 87 | 88 | if (offsetfound) begin 89 | offset <= 4'd4; 90 | end 91 | //3 92 | 93 | //4 94 | if (offsetping) begin 95 | for(x=-(window-1)/2; x<((window-1)/2)+1; x=x+1) begin 96 | for(y=-(window-1)/2; y<((window-1)/2)+1; y=y+1) begin 97 | ssd=ssd+(org_L[((row + x ) * WIDTH + col + y)*4 +:4 ]-org_R[((row + x ) * WIDTH + col + y -offset)*4 +:4 ])*(org_L[((row + x ) * WIDTH + col + y )*4 +:4 ]-org_R[((row + x ) * WIDTH + col + y - offset)*4 +:4 ]); 98 | // ssd_1=ssd_1+(org_L[(row + x ) * WIDTH + col + y + 1 ]-org_R[(row + x ) * WIDTH + col + y -offset + 1 ])*(org_L[(row + x ) * WIDTH + col + y + 1 ]-org_R[(row + x ) * WIDTH + col + y - offset + 1 ]); 99 | end 100 | end 101 | 102 | compare<=1; 103 | end 104 | 105 | //4 106 | 107 | //5 108 | if (compare) begin 109 | if (ssd < prev_ssd ) begin 110 | prev_ssd<=ssd; 111 | best_offset<=offset; 112 | 113 | end 114 | 115 | 116 | 117 | 118 | offsetping<=0; 119 | compare<=0; 120 | end 121 | //5 122 | 123 | //6 124 | if (doneFetch) begin 125 | if(ctrl_done) begin 126 | row <= 0; 127 | col<= 0; 128 | offset<=4'd4; 129 | offsetping<=0; 130 | compare<=0; 131 | ctrl_done <= 0; 132 | 133 | end 134 | else begin 135 | 136 | if(ctrl_data_run & offsetping==0 & compare==0) begin 137 | if (offsetfound) begin 138 | if(col == WIDTH - 1) begin 139 | row <= row + 1; 140 | 141 | end 142 | if(col == WIDTH - 1) begin 143 | col <= 0; 144 | end 145 | else begin 146 | col <= col + 1; // reading 2 pixels in parallel 147 | end 148 | offsetfound <= 0; 149 | best_offset <= 0; 150 | prev_ssd <= 21'd65535; 151 | // best_offset_1 <= 0; 152 | // prev_ssd_1 <= 65535; 153 | end 154 | else begin 155 | if(offset==maxoffset) begin 156 | offsetfound <= 1; 157 | end 158 | else begin 159 | offset<=offset+1; 160 | //$display("row %d col %d offset %d",row,col,offset); 161 | end 162 | ssd<=0; 163 | // ssd_1<=0; 164 | offsetping<=1; 165 | end 166 | 167 | 168 | end 169 | end 170 | end 171 | //6 172 | 173 | end 174 | 175 | 176 | //always@(posedge HCLK,posedge doneFetch) 177 | //begin 178 | //if (doneFetch) begin 179 | // if(ctrl_done) begin 180 | // row <= 0; 181 | // col<= 0; 182 | // offset<=4'd4; 183 | // offsetping<=0; 184 | // compare<=0; 185 | // ctrl_done <= 0; 186 | 187 | // end 188 | // else begin 189 | 190 | // if(ctrl_data_run & offsetping==0 & compare==0) begin 191 | // if (offsetfound) begin 192 | // if(col == WIDTH - 1) begin 193 | // row <= row + 1; 194 | 195 | // end 196 | // if(col == WIDTH - 1) begin 197 | // col <= 0; 198 | // end 199 | // else begin 200 | // col <= col + 1; // reading 2 pixels in parallel 201 | // end 202 | // offsetfound <= 0; 203 | // best_offset <= 0; 204 | // prev_ssd <= 21'd65535; 205 | //// best_offset_1 <= 0; 206 | //// prev_ssd_1 <= 65535; 207 | // end 208 | // else begin 209 | // if(offset==maxoffset) begin 210 | // offsetfound <= 1; 211 | // end 212 | // else begin 213 | // offset<=offset+1; 214 | // //$display("row %d col %d offset %d",row,col,offset); 215 | // end 216 | // ssd<=0; 217 | //// ssd_1<=0; 218 | // offsetping<=1; 219 | // end 220 | 221 | 222 | // end 223 | //end 224 | //end 225 | //end 226 | //always@(posedge offsetping) begin 227 | // for(x=-(window-1)/2; x<((window-1)/2)+1; x=x+1) begin 228 | // for(y=-(window-1)/2; y<((window-1)/2)+1; y=y+1) begin 229 | // ssd=ssd+(org_L[((row + x ) * WIDTH + col + y)*4 +:4 ]-org_R[((row + x ) * WIDTH + col + y -offset)*4 +:4 ])*(org_L[((row + x ) * WIDTH + col + y )*4 +:4 ]-org_R[((row + x ) * WIDTH + col + y - offset)*4 +:4 ]); 230 | //// ssd_1=ssd_1+(org_L[(row + x ) * WIDTH + col + y + 1 ]-org_R[(row + x ) * WIDTH + col + y -offset + 1 ])*(org_L[(row + x ) * WIDTH + col + y + 1 ]-org_R[(row + x ) * WIDTH + col + y - offset + 1 ]); 231 | // end 232 | // end 233 | 234 | // compare<=1; 235 | //end 236 | 237 | //always @(posedge compare) begin 238 | 239 | // if (ssd < prev_ssd ) begin 240 | // prev_ssd<=ssd; 241 | // best_offset<=offset; 242 | 243 | // end 244 | 245 | 246 | 247 | 248 | // offsetping<=0; 249 | // compare<=0; 250 | 251 | //end 252 | 253 | //always@(posedge offsetfound) begin 254 | //// dOUT<=best_offset; 255 | ////// DATA_1_L =best_offset_1*(255/maxoffset); 256 | //// //DATA_0_L=(org_L[WIDTH * row + col ]+org_R[WIDTH * row + col ])/2 ; 257 | //// //DATA_1_L =(org_L[WIDTH * row + col+1 ]+org_R[WIDTH * row + col+1 ])/2; 258 | // offset <= 4'd4; 259 | //end 260 | 261 | 262 | //////-------------------------------------------------// 263 | //////----------------Data counting---------- ---------// 264 | //////-------------------------------------------------// 265 | //always@(posedge HCLK) 266 | //begin 267 | // if(ctrl_done) begin 268 | // data_count <= 0; 269 | // end 270 | // else begin 271 | // if(ctrl_data_run) 272 | // data_count <= data_count + 1; 273 | // end 274 | 275 | // ctrl_done <= (data_count == 308487)? 1'b1: 1'b0; // done flag308472 276 | // if (ctrl_done) doneFetch=0; 277 | //end 278 | ////assign VSYNC = ctrl_vsync_run; 279 | 280 | ////-------------------------------------------------// 281 | ////------------- Image processing ---------------// 282 | ////-------------------------------------------------// 283 | ////always @(*) begin 284 | 285 | //// HSYNC = 1'b0; 286 | ////// DATA_0_L = 0; 287 | //// dOUT = 0; 288 | ////// DATA_0_R = 0; 289 | ////// DATA_1_R = 0; 290 | 291 | //// if(ctrl_data_run) begin 292 | //// if (offsetfound) HSYNC = 1'b1; 293 | //// else HSYNC = 1'b0; 294 | 295 | //// end 296 | ////end 297 | 298 | endmodule 299 | 300 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/disparity_generator.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------------- 2 | -- Company: Computer science and Engineering Department 3 | -- Engineer: Aruna Jayasena (aruna.15@cse.mrt.ac.lk) 4 | -- 5 | -- Create Date: 08/12/2019 04:50:30 PM 6 | -- Design Name: DepthMap 7 | -- Module Name: disparity_generator - Behavioral 8 | -- Project Name: Obstacle aviodance using stereo vision 9 | -- Target Devices: Basys 3 10 | -- Tool Versions: Vivado 2019.1 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | use IEEE.numeric_std.all; 26 | 27 | -- Uncomment the following library declaration if using 28 | -- arithmetic functions with Signed or Unsigned values 29 | --use IEEE.NUMERIC_STD.ALL; 30 | 31 | -- Uncomment the following library declaration if instantiating 32 | -- any Xilinx leaf cells in this code. 33 | --library UNISIM; 34 | --use UNISIM.VComponents.all; 35 | 36 | entity disparity_generator is 37 | generic (window:positive:=5; 38 | WIDTH:positive:=320; 39 | HEIGHT:positive:=240; 40 | maxoffset:positive:=60; --Maximum extent where to look for the same pixel 41 | minoffset:positive:=1; ----minimum extent where to look for the same pixel 42 | fetchBlock:positive:=15); 43 | Port ( 44 | HCLK : in STD_LOGIC; 45 | CLK_MAIN : in STD_LOGIC; 46 | left_in : in STD_LOGIC_vector(3 downto 0); 47 | right_in : in STD_LOGIC_vector(3 downto 0); 48 | avg_out : out STD_LOGIC_vector(3 downto 0); 49 | dOUT : out STD_LOGIC_vector(7 downto 0); 50 | dOUT_addr : out STD_LOGIC_vector(16 downto 0); 51 | left_right_addr: out STD_LOGIC_vector(16 downto 0); 52 | avg_reg_en : out STD_LOGIC; 53 | wr_en : out STD_LOGIC 54 | ); 55 | end disparity_generator; 56 | 57 | architecture Behavioral of disparity_generator is 58 | 59 | type CacheArray is array(0 to WIDTH*fetchBlock+1) of std_logic_vector(3 downto 0); 60 | signal org_L : CacheArray; --temporary storage for Left image 61 | signal org_R : CacheArray; --temporary storage for Right image 62 | 63 | signal row,row_fetch :std_logic_vector(8 downto 0); --row index of the image 64 | signal col,col_fetch :std_logic_vector(8 downto 0); --column index of the Left image 65 | 66 | signal offset,best_offset :std_logic_vector(7 downto 0); 67 | signal offsetping,offsetfound : std_logic ; 68 | 69 | signal ssd,prev_ssd :std_logic_vector(20 downto 0); --sum of squared difference 70 | 71 | signal data_count,readreg :std_logic_vector(16 downto 0); --data counting for entire pixels of the image 72 | signal doneFetch: std_logic; 73 | 74 | --signal cacheManager :std_logic_vector(2 downto 0); 75 | signal cacheManager :std_logic_vector(3 downto 0); 76 | signal SSD_calc : std_logic; 77 | 78 | begin 79 | 80 | 81 | with cacheManager select 82 | left_right_addr <= readreg when "0000", 83 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock-WIDTH, readreg'length)) when "0001", 84 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2-WIDTH, readreg'length)) when "0010", 85 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3-WIDTH, readreg'length)) when "0011", 86 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4-WIDTH, readreg'length)) when "0100", 87 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5-WIDTH, readreg'length)) when "0101", 88 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6-WIDTH, readreg'length)) when "0110", 89 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7-WIDTH, readreg'length)) when "0111", 90 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8-WIDTH, readreg'length)) when "1000", 91 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9-WIDTH, readreg'length)) when "1001", 92 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10-WIDTH, readreg'length)) when "1010", 93 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11-WIDTH, readreg'length)) when "1011", 94 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12-WIDTH, readreg'length)) when "1100", 95 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13-WIDTH, readreg'length)) when "1101", 96 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14-WIDTH, readreg'length)) when "1110", 97 | readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15-WIDTH, readreg'length)) when "1111"; 98 | 99 | with cacheManager select 100 | dOUT_addr <=std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) when "000", ---to_integer(unsigned(best_offset)) 101 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock, dOUT_addr'length)) when "0001", 102 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, dOUT_addr'length)) when "0010", 103 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, dOUT_addr'length)) when "0011", 104 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*4, dOUT_addr'length)) when "0100", 105 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*5, dOUT_addr'length)) when "0101", 106 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*6, dOUT_addr'length)) when "0110", 107 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*7, dOUT_addr'length)) when "0111", 108 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*8, dOUT_addr'length)) when "1000", 109 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*9, dOUT_addr'length)) when "1001", 110 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*10, dOUT_addr'length)) when "1010", 111 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*11, dOUT_addr'length)) when "1011", 112 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*12, dOUT_addr'length)) when "1100", 113 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*13, dOUT_addr'length)) when "1101", 114 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*14, dOUT_addr'length)) when "1110", 115 | std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))-to_integer(unsigned(best_offset)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*15, dOUT_addr'length)) when "1111"; 116 | 117 | --with cacheManager select 118 | -- left_right_addr <= readreg when "00", 119 | -- readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock, readreg'length)) when "01", 120 | -- readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, readreg'length)) when "10", 121 | -- readreg + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, readreg'length)) when "11"; 122 | 123 | 124 | --with cacheManager select 125 | -- dOUT_addr <= std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) when "00", 126 | -- std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock, dOUT_addr'length)) when "01", 127 | -- std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*2, dOUT_addr'length)) when "10", 128 | -- std_logic_vector(to_unsigned((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col)), dOUT_addr'length)) + std_logic_vector(to_unsigned(WIDTH*fetchBlock*3, dOUT_addr'length)) when "11"; 129 | 130 | avg_reg_en <= not doneFetch; 131 | 132 | 133 | 134 | 135 | caching_process: process (HCLK) begin 136 | if rising_edge(HCLK) then 137 | if doneFetch='0' then 138 | if unsigned(readreg) '0'); 145 | end if; 146 | end if; 147 | end if; 148 | end process; 149 | 150 | 151 | Image_process: process (CLK_MAIN) begin 152 | if rising_edge(CLK_MAIN) then 153 | if unsigned(readreg)=WIDTH*fetchBlock then -- replace fetchBlock with height if fetchBlock concept is removed 154 | doneFetch <='1'; 155 | end if; 156 | if doneFetch='1' then 157 | if unsigned(data_count) '0'); 161 | row <= row + 1; 162 | else 163 | col <= col + 1; 164 | end if; 165 | data_count<=data_count+"1"; 166 | offsetfound <= '0'; 167 | best_offset <= (others => '0'); 168 | prev_ssd <= (others => '1'); 169 | offset <= std_logic_vector(to_unsigned(minoffset,offset'length)); 170 | else 171 | if(offset=maxoffset) then 172 | offsetfound <= '1'; 173 | else 174 | offset<=offset+1; 175 | end if; 176 | offsetping<='1'; 177 | end if; 178 | 179 | if (ssd < prev_ssd and SSD_calc='1') then 180 | prev_ssd <= ssd; 181 | best_offset <= offset; 182 | end if; 183 | if SSD_calc='1' then 184 | offsetping<='0'; 185 | end if; 186 | -- end if; 187 | else 188 | cacheManager<=cacheManager+"1"; --Comment this if remove fetchBlock concept 189 | data_count <= std_logic_vector(to_unsigned(WIDTH,data_count'length)); 190 | doneFetch <='0'; 191 | row<=std_logic_vector(to_unsigned(1,row'length)); 192 | end if; 193 | 194 | end if; 195 | 196 | end if; 197 | end process; 198 | 199 | SSD_calc_process: process (CLK_MAIN) begin 200 | if rising_edge(CLK_MAIN) then 201 | SSD_calc<='0'; 202 | if (offsetping='1') then 203 | ssd <= std_logic_vector(to_unsigned( 204 | (to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset)))))) 205 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset)))))) 206 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset)))))) 207 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset)))))) 208 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset)))))) 209 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 0 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset)))))) 210 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) -1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) -1 - to_integer(unsigned(offset)))))) 211 | +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 0 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 0 - to_integer(unsigned(offset)))))) 212 | -- +(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset))))))*(to_integer(unsigned(org_L((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 1 )))-to_integer(unsigned(org_R((to_integer(unsigned(row)) + 1 ) * WIDTH + to_integer(unsigned(col)) + 1 - to_integer(unsigned(offset)))))) 213 | ,ssd'length)); 214 | SSD_calc<='1'; 215 | 216 | else 217 | ssd<=(others => '0'); 218 | end if; 219 | end if; 220 | end process; 221 | 222 | Image_write_process: process (offsetfound,HCLK) begin 223 | if rising_edge(offsetfound) or rising_edge(HCLK) then 224 | if (offsetfound='1') then 225 | wr_en<='1'; 226 | -- dOUT<=std_logic_vector(to_unsigned(to_integer((unsigned(best_offset)-minoffset)*4),dOUT'length)); 227 | -- dOUT<=std_logic_vector(to_unsigned(to_integer(unsigned(best_offset)),dOUT'length)); 228 | -- if to_integer(unsigned(best_offset)) > 10 then 229 | dOUT<=(std_logic_vector(to_unsigned(to_integer((unsigned(best_offset))-minoffset)*(4),dOUT'length))); 230 | -- else 231 | -- dOUT<= "00000000"; 232 | -- end if; 233 | -- dOUT<=std_logic_vector(unsigned(org_L((to_integer(unsigned(row))) * WIDTH + to_integer(unsigned(col))))+unsigned(org_R((to_integer(unsigned(row)) -1 ) * WIDTH + to_integer(unsigned(col))))/2); 234 | else 235 | wr_en<='0'; 236 | end if; 237 | end if; 238 | end process; 239 | 240 | end Behavioral; -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/i2c_sender.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: '0'); 28 | signal data_sr : std_logic_vector(31 downto 0) := (others => '1'); 29 | begin 30 | process(busy_sr, data_sr(31)) 31 | begin 32 | if busy_sr(11 downto 10) = "10" or 33 | busy_sr(20 downto 19) = "10" or 34 | busy_sr(29 downto 28) = "10" then 35 | siod <= 'Z'; 36 | else 37 | siod <= data_sr(31); 38 | end if; 39 | end process; 40 | 41 | process(clk) 42 | begin 43 | if rising_edge(clk) then 44 | taken <= '0'; 45 | if busy_sr(31) = '0' then 46 | SIOC <= '1'; 47 | if send = '1' then 48 | if divider = "00000000" then 49 | data_sr <= "100" & id & '0' & reg & '0' & value & '0' & "01"; 50 | busy_sr <= "111" & "111111111" & "111111111" & "111111111" & "11"; 51 | taken <= '1'; 52 | else 53 | divider <= divider+1; -- this only happens on powerup 54 | end if; 55 | end if; 56 | else 57 | 58 | case busy_sr(32-1 downto 32-3) & busy_sr(2 downto 0) is 59 | when "111"&"111" => -- start seq #1 60 | case divider(7 downto 6) is 61 | when "00" => SIOC <= '1'; 62 | when "01" => SIOC <= '1'; 63 | when "10" => SIOC <= '1'; 64 | when others => SIOC <= '1'; 65 | end case; 66 | when "111"&"110" => -- start seq #2 67 | case divider(7 downto 6) is 68 | when "00" => SIOC <= '1'; 69 | when "01" => SIOC <= '1'; 70 | when "10" => SIOC <= '1'; 71 | when others => SIOC <= '1'; 72 | end case; 73 | when "111"&"100" => -- start seq #3 74 | case divider(7 downto 6) is 75 | when "00" => SIOC <= '0'; 76 | when "01" => SIOC <= '0'; 77 | when "10" => SIOC <= '0'; 78 | when others => SIOC <= '0'; 79 | end case; 80 | when "110"&"000" => -- end seq #1 81 | case divider(7 downto 6) is 82 | when "00" => SIOC <= '0'; 83 | when "01" => SIOC <= '1'; 84 | when "10" => SIOC <= '1'; 85 | when others => SIOC <= '1'; 86 | end case; 87 | when "100"&"000" => -- end seq #2 88 | case divider(7 downto 6) is 89 | when "00" => SIOC <= '1'; 90 | when "01" => SIOC <= '1'; 91 | when "10" => SIOC <= '1'; 92 | when others => SIOC <= '1'; 93 | end case; 94 | when "000"&"000" => -- Idle 95 | case divider(7 downto 6) is 96 | when "00" => SIOC <= '1'; 97 | when "01" => SIOC <= '1'; 98 | when "10" => SIOC <= '1'; 99 | when others => SIOC <= '1'; 100 | end case; 101 | when others => 102 | case divider(7 downto 6) is 103 | when "00" => SIOC <= '0'; 104 | when "01" => SIOC <= '1'; 105 | when "10" => SIOC <= '1'; 106 | when others => SIOC <= '0'; 107 | end case; 108 | end case; 109 | 110 | if divider = "11111111" then 111 | busy_sr <= busy_sr(32-2 downto 0) & '0'; 112 | data_sr <= data_sr(32-2 downto 0) & '1'; 113 | divider <= (others => '0'); 114 | else 115 | divider <= divider+1; 116 | end if; 117 | end if; 118 | end if; 119 | end process; 120 | end Behavioral; 121 | 122 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/i3c2.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Mike Field 3 | -- 4 | -- Create Date: 21:30:20 05/25/2013 5 | -- Design Name: i3c2 - Intelligent I2C Controller 6 | -- Module Name: i3c2 - Behavioral 7 | -- Description: The main CPU/logic 8 | -- 9 | -- Revision: 10 | -- Revision 0.01 - File Created 11 | -- Additional Comments: 12 | -- 13 | 14 | -- This file is borrowed from https://github.com/laurivosandi/hdl 15 | -- MIT LICENSE can be found here for this file https://github.com/laurivosandi/hdl/blob/master/LICENSE 16 | ---------------------------------------------------------------------------------- 17 | library IEEE; 18 | use IEEE.STD_LOGIC_1164.ALL; 19 | use IEEE.NUMERIC_STD.ALL; 20 | 21 | entity i3c2 is 22 | Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0)); 23 | 24 | Port ( clk : in STD_LOGIC; 25 | inst_address : out STD_LOGIC_VECTOR (9 downto 0); 26 | inst_data : in STD_LOGIC_VECTOR (8 downto 0); 27 | i2c_scl : out STD_LOGIC; 28 | i2c_sda : inout STD_LOGIC; 29 | inputs : in STD_LOGIC_VECTOR (15 downto 0); 30 | outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0'); 31 | reg_addr : out STD_LOGIC_VECTOR (4 downto 0); 32 | reg_data : out STD_LOGIC_VECTOR (7 downto 0); 33 | reg_write : out STD_LOGIC; 34 | error : out STD_LOGIC); 35 | end i3c2; 36 | 37 | architecture Behavioral of i3c2 is 38 | 39 | constant STATE_RUN : std_logic_vector(3 downto 0) := "0000"; 40 | constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001"; 41 | constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010"; 42 | constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011"; 43 | constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100"; 44 | signal state : std_logic_vector(3 downto 0) := STATE_RUN; 45 | 46 | constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000"; 47 | constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001"; 48 | constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010"; 49 | constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011"; 50 | constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100"; 51 | constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101"; 52 | constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110"; 53 | constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111"; 54 | constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000"; 55 | constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001"; 56 | constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010"; 57 | constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011"; 58 | constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100"; 59 | constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101"; 60 | constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110"; 61 | signal opcode : std_logic_vector( 3 downto 0); 62 | 63 | 64 | signal ack_flag : std_logic := '0'; 65 | signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION 66 | 67 | -- I2C status 68 | signal i2c_doing_read : std_logic := '0'; 69 | signal i2c_started : std_logic := '0'; 70 | signal i2c_bits_left : unsigned(3 downto 0); 71 | 72 | -- counters 73 | signal pcnext : unsigned(9 downto 0) := (others => '0'); 74 | signal delay : unsigned(15 downto 0); 75 | signal bitcount : unsigned( 7 downto 0); 76 | 77 | -- Input/output data 78 | signal i2c_data : std_logic_vector( 8 downto 0); 79 | 80 | begin 81 | 82 | -- |Opcode | Instruction | Action 83 | -- +---------+-------------+---------------------------------------- 84 | -- |00nnnnnnn| JUMP m | Set PC to m (n = m/8) 85 | -- |01000nnnn| SKIPCLEAR n | Skip if input n clear 86 | -- |01001nnnn| SKIPSET n | skip if input n set 87 | -- |01010nnnn| CLEAR n | Clear output n 88 | -- |01011nnnn| SET n | Set output n 89 | -- |0110nnnnn| READ n | Read to register n 90 | -- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m)) 91 | -- |011110000| SKIPNACK | Skip if NACK is set 92 | -- |011110001| SKIPACK | Skip if ACK is set 93 | -- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus 94 | -- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus 95 | -- |011110100| USER0 | User defined 96 | -- |.........| | 97 | -- |011111110| USER9 | User defined 98 | -- |011111111| STOP | Send Stop on i2C bus 99 | -- |1nnnnnnnn| WRITE n | Output n on I2C bus 100 | 101 | opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else 102 | OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else 103 | OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else 104 | OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else 105 | OPCODE_SET when inst_data(8 downto 4) = "01011" else 106 | OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else 107 | OPCODE_DELAY when inst_data(8 downto 4) = "01110" else 108 | OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else 109 | OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else 110 | OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else 111 | OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else 112 | -- user codes can go here 113 | OPCODE_NOP when inst_data(8 downto 0) = "011111110" else 114 | OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else 115 | OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN; 116 | 117 | inst_address <= std_logic_vector(pcnext); 118 | 119 | cpu: process(clk) 120 | begin 121 | if rising_edge(clk) then 122 | case state is 123 | when STATE_I2C_START => 124 | i2c_started <= '1'; 125 | i2c_scl <= '1'; 126 | 127 | if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then 128 | i2c_sda <= '0'; 129 | end if; 130 | 131 | if bitcount = 0 then 132 | state <= STATE_I2C_BITS; 133 | i2c_scl <= '0'; 134 | bitcount <= unsigned(clk_divide); 135 | else 136 | bitcount <= bitcount-1; 137 | end if; 138 | 139 | 140 | when STATE_I2C_BITS => -- scl has always just lowered '0' on entry 141 | -- set the data half way through clock low half of the cycle 142 | if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then 143 | if i2c_data(8) = '0' then 144 | i2c_sda <= '0'; 145 | else 146 | i2c_sda <= 'Z'; 147 | end if; 148 | end if; 149 | 150 | -- raise the clock half way thorugh 151 | if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then 152 | i2c_scl <= '1'; 153 | end if; 154 | 155 | -- Input bits three quarters through the cycle 156 | if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then 157 | i2c_data <= i2c_data(7 downto 0) & i2c_sda; 158 | end if; 159 | 160 | -- lower the clock at the end of the cycle 161 | if bitcount = 0 then 162 | i2c_scl <= '0'; 163 | if i2c_bits_left = "000" then 164 | i2c_scl <= '0'; 165 | if i2c_doing_read = '1' then 166 | reg_data <= i2c_data(8 downto 1); 167 | reg_write <= '1'; 168 | end if; 169 | ack_flag <= NOT i2c_data(0); 170 | state <= STATE_RUN; 171 | pcnext <= pcnext+1; 172 | else 173 | i2c_bits_left <= i2c_bits_left -1; 174 | end if; 175 | bitcount <= unsigned(clk_divide); 176 | else 177 | bitcount <= bitcount-1; 178 | end if; 179 | 180 | 181 | when STATE_I2C_STOP => 182 | -- clock stays high, and data goes high half way through a bit 183 | i2c_started <= '0'; 184 | if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then 185 | i2c_sda <= '0'; 186 | end if; 187 | 188 | if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then 189 | i2c_scl <= '1'; 190 | end if; 191 | 192 | if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then 193 | i2c_sda <= 'Z'; 194 | end if; 195 | if bitcount = 0 then 196 | state <= STATE_RUN; 197 | pcnext <= pcnext+1; 198 | else 199 | bitcount <= bitcount-1; 200 | end if; 201 | 202 | when STATE_DELAY => 203 | if bitcount /= 0 then 204 | bitcount <= bitcount -1; 205 | else 206 | if delay = 0 then 207 | pcnext <= pcnext+1; 208 | state <= STATE_RUN; 209 | else 210 | delay <= delay-1; 211 | bitcount <= unsigned(clk_divide) - 1; 212 | end if; 213 | end if; 214 | 215 | when STATE_RUN => 216 | reg_data <= "XXXXXXXX"; 217 | 218 | if skip = '1'then 219 | -- Do nothing for a cycle other than unset 'skip'; 220 | skip <= '0'; 221 | pcnext <= pcnext+1; 222 | else 223 | case opcode is 224 | when OPCODE_JUMP => 225 | -- Ignore the next instruciton while fetching the jump destination 226 | skip <= '1'; 227 | pcnext <= unsigned(inst_data(6 downto 0)) & "000"; 228 | 229 | when OPCODE_I2C_WRITE => 230 | i2c_data <= inst_data(7 downto 0) & "1"; 231 | bitcount <= unsigned(clk_divide); 232 | i2c_doing_read <= '0'; 233 | i2c_bits_left <= "1000"; 234 | if i2c_started = '0' then 235 | state <= STATE_I2C_START; 236 | else 237 | state <= STATE_I2C_BITS; 238 | end if; 239 | 240 | when OPCODE_I2C_READ => 241 | reg_addr <= inst_data(4 downto 0); 242 | i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK 243 | bitcount <= unsigned(clk_divide); 244 | i2c_bits_left <= "1000"; 245 | i2c_doing_read <= '1'; 246 | if i2c_started = '0' then 247 | state <= STATE_I2C_START; 248 | else 249 | state <= STATE_I2C_BITS; 250 | end if; 251 | 252 | when OPCODE_SKIPCLEAR => 253 | skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4); 254 | pcnext <= pcnext+1; 255 | 256 | when OPCODE_SKIPSET => 257 | skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4); 258 | pcnext <= pcnext+1; 259 | 260 | when OPCODE_CLEAR => 261 | outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4); 262 | pcnext <= pcnext+1; 263 | 264 | when OPCODE_SET => 265 | outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4); 266 | pcnext <= pcnext+1; 267 | 268 | when OPCODE_SKIPACK => 269 | skip <= ack_flag; 270 | pcnext <= pcnext+1; 271 | 272 | when OPCODE_SKIPNACK => 273 | skip <= not ack_flag; 274 | pcnext <= pcnext+1; 275 | 276 | when OPCODE_DELAY => 277 | state <= STATE_DELAY; 278 | bitcount <= unsigned(clk_divide); 279 | case inst_data(3 downto 0) is 280 | when "0000" => delay <= x"0001"; 281 | when "0001" => delay <= x"0002"; 282 | when "0010" => delay <= x"0004"; 283 | when "0011" => delay <= x"0008"; 284 | when "0100" => delay <= x"0010"; 285 | when "0101" => delay <= x"0020"; 286 | when "0110" => delay <= x"0040"; 287 | when "0111" => delay <= x"0080"; 288 | when "1000" => delay <= x"0100"; 289 | when "1001" => delay <= x"0200"; 290 | when "1010" => delay <= x"0400"; 291 | when "1011" => delay <= x"0800"; 292 | when "1100" => delay <= x"1000"; 293 | when "1101" => delay <= x"2000"; 294 | when "1110" => delay <= x"4000"; 295 | when others => delay <= x"8000"; 296 | end case; 297 | 298 | when OPCODE_I2C_STOP => 299 | bitcount <= unsigned(clk_divide); 300 | state <= STATE_I2C_STOP; 301 | 302 | when OPCODE_NOP => 303 | pcnext <= pcnext+1; 304 | when others => 305 | error <= '1'; 306 | end case; 307 | end if; 308 | 309 | when others => 310 | state <= STATE_RUN; 311 | pcnext <= (others => '0'); 312 | skip <= '1'; 313 | 314 | end case; 315 | end if; 316 | end process; 317 | end Behavioral; 318 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/ov7670_capture.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Aruna Jayasena 3 | -- 4 | -- Description: Captures the pixels coming from the two OV7670 cameras and 5 | -- Stores them in seperate block RAMs 6 | -- 7 | -- The length of href last controls how often pixels are captive - (2 downto 0) stores 8 | -- one pixel every 4 cycles. 9 | -- 10 | -- "line" is used to control how often data is captured. In this case every forth 11 | -- line 12 | ---------------------------------------------------------------------------------- 13 | library IEEE; 14 | use IEEE.STD_LOGIC_1164.ALL; 15 | use IEEE.NUMERIC_STD.ALL; 16 | 17 | entity ov7670_capture is 18 | Port ( pclk : in STD_LOGIC; 19 | rez_160x120 : IN std_logic; 20 | rez_320x240 : IN std_logic; 21 | vsync : in STD_LOGIC; 22 | href : in STD_LOGIC; 23 | d : in STD_LOGIC_VECTOR (7 downto 0); 24 | addr : out STD_LOGIC_VECTOR (16 downto 0); 25 | dout : out STD_LOGIC_VECTOR (11 downto 0); 26 | we : out STD_LOGIC); 27 | end ov7670_capture; 28 | 29 | architecture Behavioral of ov7670_capture is 30 | signal d_latch : std_logic_vector(15 downto 0) := (others => '0'); 31 | signal address : STD_LOGIC_VECTOR(16 downto 0) := (others => '0'); 32 | signal line : std_logic_vector(1 downto 0) := (others => '0'); 33 | signal href_last : std_logic_vector(6 downto 0) := (others => '0'); 34 | signal we_reg : std_logic := '0'; 35 | signal href_hold : std_logic := '0'; 36 | signal latched_vsync : STD_LOGIC := '0'; 37 | signal latched_href : STD_LOGIC := '0'; 38 | signal latched_d : STD_LOGIC_VECTOR (7 downto 0) := (others => '0'); 39 | begin 40 | addr <= address; 41 | we <= we_reg; 42 | dout <= d_latch(15 downto 12) & d_latch(10 downto 7) & d_latch(4 downto 1); 43 | 44 | capture_process: process(pclk) 45 | begin 46 | if rising_edge(pclk) then 47 | if we_reg = '1' then 48 | address <= std_logic_vector(unsigned(address)+1); 49 | end if; 50 | 51 | -- This is a bit tricky href starts a pixel transfer that takes 3 cycles 52 | -- Input | state after clock tick 53 | -- href | wr_hold d_latch dout we address address_next 54 | -- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxx x xxxx xxxx 55 | -- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxx x xxxx addr 56 | -- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxxxxx x addr addr 57 | -- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRGGGGBBBB 1 addr addr+1 58 | 59 | -- detect the rising edge on href - the start of the scan line 60 | if href_hold = '0' and latched_href = '1' then 61 | case line is 62 | when "00" => line <= "01"; 63 | when "01" => line <= "10"; 64 | when "10" => line <= "11"; 65 | when others => line <= "00"; 66 | end case; 67 | end if; 68 | href_hold <= latched_href; 69 | 70 | -- capturing the data from the camera, 12-bit RGB 71 | if latched_href = '1' then 72 | d_latch <= d_latch( 7 downto 0) & latched_d; 73 | end if; 74 | we_reg <= '0'; 75 | 76 | -- Is a new screen about to start (i.e. we have to restart capturing 77 | if latched_vsync = '1' then 78 | address <= (others => '0'); 79 | href_last <= (others => '0'); 80 | line <= (others => '0'); 81 | else 82 | -- If not, set the write enable whenever we need to capture a pixel 83 | if (rez_160x120 = '1' and href_last(6) = '1') or 84 | (rez_320x240 = '1' and href_last(2) = '1') or 85 | (rez_160x120 = '0' and rez_320x240 = '0' and href_last(0) = '1') then 86 | 87 | if rez_160x120 = '1' then 88 | if line = "10" then 89 | we_reg <= '1'; 90 | end if; 91 | elsif rez_320x240 = '1' then 92 | if line(1) = '1' then 93 | we_reg <= '1'; 94 | end if; 95 | else 96 | we_reg <= '1'; 97 | end if; 98 | href_last <= (others => '0'); 99 | else 100 | href_last <= href_last(href_last'high-1 downto 0) & latched_href; 101 | end if; 102 | end if; 103 | end if; 104 | if falling_edge(pclk) then 105 | latched_d <= d; 106 | latched_href <= href; 107 | latched_vsync <= vsync; 108 | end if; 109 | end process; 110 | end Behavioral; 111 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/ov7670_controller_left.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Mike Field 3 | -- 4 | -- Description: Controller for the OV760 camera - transferes registers to the 5 | -- camera over an I2C like bus 6 | 7 | -- This file is borrowed from https://github.com/laurivosandi/hdl 8 | -- MIT LICENSE can be found here for this file https://github.com/laurivosandi/hdl/blob/master/LICENSE 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | entity ov7670_controller_left is 15 | Port ( clk : in STD_LOGIC; 16 | resend :in STD_LOGIC; 17 | config_finished : out std_logic; 18 | sioc : out STD_LOGIC; 19 | siod : inout STD_LOGIC; 20 | reset : out STD_LOGIC; 21 | pwdn : out STD_LOGIC; 22 | xclk : out STD_LOGIC 23 | ); 24 | end ov7670_controller_left; 25 | 26 | architecture Behavioral of ov7670_controller_left is 27 | COMPONENT ov7670_registers_left 28 | PORT( 29 | clk : IN std_logic; 30 | advance : IN std_logic; 31 | resend : in STD_LOGIC; 32 | command : OUT std_logic_vector(15 downto 0); 33 | finished : OUT std_logic 34 | ); 35 | END COMPONENT; 36 | 37 | COMPONENT i2c_sender 38 | PORT( 39 | clk : IN std_logic; 40 | send : IN std_logic; 41 | taken : out std_logic; 42 | id : IN std_logic_vector(7 downto 0); 43 | reg : IN std_logic_vector(7 downto 0); 44 | value : IN std_logic_vector(7 downto 0); 45 | siod : INOUT std_logic; 46 | sioc : OUT std_logic 47 | ); 48 | END COMPONENT; 49 | 50 | signal sys_clk : std_logic := '0'; 51 | signal command : std_logic_vector(15 downto 0); 52 | signal finished : std_logic := '0'; 53 | signal taken : std_logic := '0'; 54 | signal send : std_logic; 55 | 56 | constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet 57 | begin 58 | config_finished <= finished; 59 | 60 | send <= not finished; 61 | Inst_i2c_sender: i2c_sender PORT MAP( 62 | clk => clk, 63 | taken => taken, 64 | siod => siod, 65 | sioc => sioc, 66 | send => send, 67 | id => camera_address, 68 | reg => command(15 downto 8), 69 | value => command(7 downto 0) 70 | ); 71 | 72 | reset <= '1'; -- Normal mode 73 | pwdn <= '0'; -- Power device up 74 | xclk <= sys_clk; 75 | 76 | Inst_ov7670_registers_left: ov7670_registers_left PORT MAP( 77 | clk => clk, 78 | advance => taken, 79 | command => command, 80 | finished => finished, 81 | resend => resend 82 | ); 83 | 84 | process(clk) 85 | begin 86 | if rising_edge(clk) then 87 | sys_clk <= not sys_clk; 88 | end if; 89 | end process; 90 | end Behavioral; 91 | 92 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/ov7670_controller_right.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Engineer: Mike Field 3 | -- 4 | -- Description: Controller for the OV760 camera - transferes registers to the 5 | -- camera over an I2C like bus 6 | 7 | -- This file is borrowed from https://github.com/laurivosandi/hdl 8 | -- MIT LICENSE can be found here for this file https://github.com/laurivosandi/hdl/blob/master/LICENSE 9 | ---------------------------------------------------------------------------------- 10 | library IEEE; 11 | use IEEE.STD_LOGIC_1164.ALL; 12 | use IEEE.NUMERIC_STD.ALL; 13 | 14 | entity ov7670_controller_right is 15 | Port ( clk : in STD_LOGIC; 16 | resend :in STD_LOGIC; 17 | exposure : in STD_LOGIC_VECTOR (15 downto 0); 18 | config_finished : out std_logic; 19 | sioc : out STD_LOGIC; 20 | siod : inout STD_LOGIC; 21 | reset : out STD_LOGIC; 22 | pwdn : out STD_LOGIC; 23 | xclk : out STD_LOGIC 24 | ); 25 | end ov7670_controller_right; 26 | 27 | architecture Behavioral of ov7670_controller_right is 28 | COMPONENT ov7670_registers_right 29 | PORT( 30 | clk : IN std_logic; 31 | advance : IN std_logic; 32 | resend : in STD_LOGIC; 33 | exposure : in STD_LOGIC_VECTOR (15 downto 0); 34 | command : OUT std_logic_vector(15 downto 0); 35 | finished : OUT std_logic 36 | ); 37 | END COMPONENT; 38 | 39 | COMPONENT i2c_sender 40 | PORT( 41 | clk : IN std_logic; 42 | send : IN std_logic; 43 | taken : out std_logic; 44 | id : IN std_logic_vector(7 downto 0); 45 | reg : IN std_logic_vector(7 downto 0); 46 | value : IN std_logic_vector(7 downto 0); 47 | siod : INOUT std_logic; 48 | sioc : OUT std_logic 49 | ); 50 | END COMPONENT; 51 | 52 | signal sys_clk : std_logic := '0'; 53 | signal command : std_logic_vector(15 downto 0); 54 | signal finished : std_logic := '0'; 55 | signal taken : std_logic := '0'; 56 | signal send : std_logic; 57 | 58 | constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet 59 | begin 60 | config_finished <= finished; 61 | 62 | send <= not finished; 63 | Inst_i2c_sender: i2c_sender PORT MAP( 64 | clk => clk, 65 | taken => taken, 66 | siod => siod, 67 | sioc => sioc, 68 | send => send, 69 | id => camera_address, 70 | reg => command(15 downto 8), 71 | value => command(7 downto 0) 72 | ); 73 | 74 | reset <= '1'; -- Normal mode 75 | pwdn <= '0'; -- Power device up 76 | xclk <= sys_clk; 77 | 78 | Inst_ov7670_registers_right: ov7670_registers_right PORT MAP( 79 | clk => clk, 80 | advance => taken, 81 | exposure => exposure, 82 | command => command, 83 | finished => finished, 84 | resend => resend 85 | ); 86 | 87 | process(clk) 88 | begin 89 | if rising_edge(clk) then 90 | sys_clk <= not sys_clk; 91 | end if; 92 | end process; 93 | end Behavioral; 94 | 95 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/ov7670_registers_left.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: Mike Field 4 | -- 5 | -- Description: Register settings for the OV7670 Caamera (partially from OV7670.c 6 | -- in the Linux Kernel 7 | 8 | -- This file is borrowed from https://github.com/laurivosandi/hdl 9 | -- MIT LICENSE can be found here for this file https://github.com/laurivosandi/hdl/blob/master/LICENSE 10 | ------------------------------------------------------------------------------------ 11 | library IEEE; 12 | use IEEE.STD_LOGIC_1164.ALL; 13 | use IEEE.NUMERIC_STD.ALL; 14 | 15 | entity ov7670_registers_left is 16 | Port ( clk : in STD_LOGIC; 17 | resend : in STD_LOGIC; 18 | advance : in STD_LOGIC; 19 | command : out std_logic_vector(15 downto 0); 20 | finished : out STD_LOGIC); 21 | end ov7670_registers_left; 22 | 23 | architecture Behavioral of ov7670_registers_left is 24 | signal sreg : std_logic_vector(15 downto 0); 25 | signal address : std_logic_vector(7 downto 0) := (others => '0'); 26 | signal AECH : std_logic_vector(7 downto 0); 27 | signal AECHH : std_logic_vector(5 downto 0); 28 | signal COM1 : std_logic_vector(1 downto 0); 29 | 30 | begin 31 | command <= sreg; 32 | with sreg select finished <= '1' when x"FFFF", '0' when others; 33 | AECHH <= "000000";--exposure(15 downto 10); 34 | AECH <= "11000000";--exposure(9 downto 2); --8 was higher 1111 was too much 11100000 too high 35 | COM1 <= (others => '0');--exposure(1 downto 0); 36 | 37 | process(clk) 38 | begin 39 | if rising_edge(clk) then 40 | if resend = '1' then 41 | address <= (others => '0'); 42 | elsif advance = '1' then 43 | address <= std_logic_vector(unsigned(address)+1); 44 | end if; 45 | 46 | case address is 47 | when x"00" => sreg <= x"1280"; -- COM7 Reset 48 | when x"01" => sreg <= x"1280"; -- COM7 Reset 49 | when x"02" => sreg <= x"1200";--x"1204"; -- COM7 Size & RGB output 50 | when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1) 51 | when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off 52 | when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off 53 | 54 | when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format 55 | when x"07" => sreg <= "01000000000000" & COM1 ; -- COM1 no CCIR601 56 | when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565 57 | when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window 58 | when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling 59 | when x"0B" => sreg <= x"4fb3"; -- MTX1 - colour conversion matrix 60 | when x"0C" => sreg <= x"50b3"; -- MTX2 - colour conversion matrix 61 | when x"0D" => sreg <= x"5100"; -- MTX3 - colour conversion matrix 62 | when x"0E" => sreg <= x"523d"; -- MTX4 - colour conversion matrix 63 | when x"0F" => sreg <= x"53a7"; -- MTX5 - colour conversion matrix 64 | when x"10" => sreg <= x"54e4"; -- MTX6 - colour conversion matrix 65 | when x"11" => sreg <= x"589e"; -- MTXS - Matrix sign and auto contrast 66 | when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust 67 | when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1) 68 | 69 | when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits) 70 | when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits) 71 | when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP 72 | 73 | when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits) 74 | when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits) 75 | when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits 76 | 77 | when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61 78 | when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B 79 | 80 | when x"1C" => sreg <= x"1602"; -- 81 | when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x 82 | 83 | when x"1E" => sreg <= x"2102"; 84 | when x"1F" => sreg <= x"2291"; 85 | 86 | when x"20" => sreg <= x"2907"; 87 | when x"21" => sreg <= x"330b"; 88 | 89 | when x"22" => sreg <= x"350b"; 90 | when x"23" => sreg <= x"371d"; 91 | 92 | when x"24" => sreg <= x"3871"; 93 | when x"25" => sreg <= x"392a"; 94 | 95 | when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78 96 | when x"27" => sreg <= x"4d40"; 97 | 98 | when x"28" => sreg <= x"4e20"; 99 | when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00 100 | 101 | when x"2A" => sreg <= x"6b4a"; 102 | when x"2B" => sreg <= x"7410"; 103 | 104 | when x"2C" => sreg <= x"8d4f"; 105 | when x"2D" => sreg <= x"8e00"; 106 | 107 | when x"2E" => sreg <= x"8f00"; 108 | when x"2F" => sreg <= x"9000"; 109 | 110 | when x"30" => sreg <= x"9100"; 111 | when x"31" => sreg <= x"9600"; 112 | 113 | when x"32" => sreg <= x"9a00"; 114 | when x"33" => sreg <= x"b084"; 115 | 116 | when x"34" => sreg <= x"b10c"; 117 | when x"35" => sreg <= x"b20e"; 118 | 119 | when x"36" => sreg <= x"b382"; 120 | when x"37" => sreg <= x"b80a"; 121 | when x"38" => sreg <= x"138e";--x"138e"; -- COM8 - AGC switched off 138f for default, White balance 122 | when x"39" => sreg <= x"4200"; -- COM17 - Color bar removed 123 | -- when x"3A" => sreg <= x"10" & AECH; 124 | -- when x"3B" => sreg <= "0111000000" & AECHH; 125 | -- when x"10" => sreg <= x"703a"; -- SCALING_XSC 126 | -- when x"11" => sreg <= x"7135"; -- SCALING_YSC 127 | -- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11 128 | -- when x"13" => sreg <= x"7300"; -- SCALING_PCLK_DIV 129 | -- when x"14" => sreg <= x"a200"; -- SCALING_PCLK_DELAY must match COM14 130 | -- when x"15" => sreg <= x"1500"; -- COM10 Use HREF not hSYNC 131 | -- 132 | -- when x"1D" => sreg <= x"B104"; -- ABLC1 - Turn on auto black level 133 | -- when x"1F" => sreg <= x"138F"; -- COM8 - AGC, White balance 134 | -- when x"21" => sreg <= x"FFFF"; -- spare 135 | -- when x"22" => sreg <= x"FFFF"; -- spare 136 | -- when x"23" => sreg <= x"0000"; -- spare 137 | -- when x"24" => sreg <= x"0000"; -- spare 138 | -- when x"25" => sreg <= x"138F"; -- COM8 - AGC, White balance 139 | -- when x"26" => sreg <= x"0000"; -- spare 140 | -- when x"27" => sreg <= x"1000"; -- AECH Exposure 141 | -- when x"28" => sreg <= x"0D40"; -- COMM4 - Window Size 142 | -- when x"29" => sreg <= x"0000"; -- spare 143 | -- when x"2a" => sreg <= x"a505"; -- AECGMAX banding filter step 144 | -- when x"2b" => sreg <= x"2495"; -- AEW AGC Stable upper limite 145 | -- when x"2c" => sreg <= x"2533"; -- AEB AGC Stable lower limi 146 | -- when x"2d" => sreg <= x"26e3"; -- VPT AGC fast mode limits 147 | -- when x"2e" => sreg <= x"9f78"; -- HRL High reference level 148 | -- when x"2f" => sreg <= x"A068"; -- LRL low reference level 149 | -- when x"30" => sreg <= x"a103"; -- DSPC3 DSP control 150 | -- when x"31" => sreg <= x"A6d8"; -- LPH Lower Prob High 151 | -- when x"32" => sreg <= x"A7d8"; -- UPL Upper Prob Low 152 | -- when x"33" => sreg <= x"A8f0"; -- TPL Total Prob Low 153 | -- when x"34" => sreg <= x"A990"; -- TPH Total Prob High 154 | -- when x"35" => sreg <= x"AA94"; -- NALG AEC Algo select 155 | -- when x"36" => sreg <= x"13E5"; -- COM8 AGC Settings 156 | when others => sreg <= x"ffff"; 157 | end case; 158 | end if; 159 | end process; 160 | end Behavioral; 161 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/ov7670_registers_right.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: Mike Field 4 | -- 5 | -- Description: Register settings for the OV7670 Caamera (partially from OV7670.c 6 | -- in the Linux Kernel 7 | 8 | -- This file is borrowed from https://github.com/laurivosandi/hdl 9 | -- MIT LICENSE can be found here for this file https://github.com/laurivosandi/hdl/blob/master/LICENSE 10 | 11 | ------------------------------------------------------------------------------------ 12 | library IEEE; 13 | use IEEE.STD_LOGIC_1164.ALL; 14 | use IEEE.NUMERIC_STD.ALL; 15 | 16 | entity ov7670_registers_right is 17 | Port ( clk : in STD_LOGIC; 18 | resend : in STD_LOGIC; 19 | advance : in STD_LOGIC; 20 | exposure : in STD_LOGIC_VECTOR (15 downto 0); 21 | command : out std_logic_vector(15 downto 0); 22 | finished : out STD_LOGIC); 23 | end ov7670_registers_right; 24 | 25 | architecture Behavioral of ov7670_registers_right is 26 | signal sreg : std_logic_vector(15 downto 0); 27 | signal address : std_logic_vector(7 downto 0) := (others => '0'); 28 | signal AECH : std_logic_vector(7 downto 0); 29 | signal AECHH : std_logic_vector(5 downto 0); 30 | signal COM1 : std_logic_vector(1 downto 0); 31 | 32 | begin 33 | command <= sreg; 34 | with sreg select finished <= '1' when x"FFFF", '0' when others; 35 | AECHH <= (others => '1');--exposure(15 downto 10); 36 | AECH <= (others => '1');--exposure(9 downto 2); 37 | COM1 <= (others => '1');--exposure(1 downto 0); 38 | 39 | process(clk) 40 | begin 41 | if rising_edge(clk) then 42 | if resend = '1' then 43 | address <= (others => '0'); 44 | elsif advance = '1' then 45 | address <= std_logic_vector(unsigned(address)+1); 46 | end if; 47 | 48 | case address is 49 | when x"00" => sreg <= x"1280"; -- COM7 Reset 50 | when x"01" => sreg <= x"1280"; -- COM7 Reset 51 | when x"02" => sreg <= x"1200";--x"1204"; -- COM7 Size & RGB output 52 | when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1) 53 | when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off 54 | when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off 55 | 56 | when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format 57 | when x"07" => sreg <= "01000000000000" & COM1 ; -- COM1 no CCIR601 58 | when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565 59 | when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window 60 | when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling 61 | when x"0B" => sreg <= x"4fb3"; -- MTX1 - colour conversion matrix 62 | when x"0C" => sreg <= x"50b3"; -- MTX2 - colour conversion matrix 63 | when x"0D" => sreg <= x"5100"; -- MTX3 - colour conversion matrix 64 | when x"0E" => sreg <= x"523d"; -- MTX4 - colour conversion matrix 65 | when x"0F" => sreg <= x"53a7"; -- MTX5 - colour conversion matrix 66 | when x"10" => sreg <= x"54e4"; -- MTX6 - colour conversion matrix 67 | when x"11" => sreg <= x"589e"; -- MTXS - Matrix sign and auto contrast 68 | when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust 69 | when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1) 70 | 71 | when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits) 72 | when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits) 73 | when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP 74 | 75 | when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits) 76 | when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits) 77 | when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits 78 | 79 | when x"1A" => sreg <= x"0e61"; -- COM5(0x0E) 0x61 80 | when x"1B" => sreg <= x"0f4b"; -- COM6(0x0F) 0x4B 81 | 82 | when x"1C" => sreg <= x"1602"; -- 83 | when x"1D" => sreg <= x"1e37"; -- MVFP (0x1E) 0x07 -- FLIP AND MIRROR IMAGE 0x3x 84 | 85 | when x"1E" => sreg <= x"2102"; 86 | when x"1F" => sreg <= x"2291"; 87 | 88 | when x"20" => sreg <= x"2907"; 89 | when x"21" => sreg <= x"330b"; 90 | 91 | when x"22" => sreg <= x"350b"; 92 | when x"23" => sreg <= x"371d"; 93 | 94 | when x"24" => sreg <= x"3871"; 95 | when x"25" => sreg <= x"392a"; 96 | 97 | when x"26" => sreg <= x"3c78"; -- COM12 (0x3C) 0x78 98 | when x"27" => sreg <= x"4d40"; 99 | 100 | when x"28" => sreg <= x"4e20"; 101 | when x"29" => sreg <= x"6900"; -- GFIX (0x69) 0x00 102 | 103 | when x"2A" => sreg <= x"6b4a"; 104 | when x"2B" => sreg <= x"7410"; 105 | 106 | when x"2C" => sreg <= x"8d4f"; 107 | when x"2D" => sreg <= x"8e00"; 108 | 109 | when x"2E" => sreg <= x"8f00"; 110 | when x"2F" => sreg <= x"9000"; 111 | 112 | when x"30" => sreg <= x"9100"; 113 | when x"31" => sreg <= x"9600"; 114 | 115 | when x"32" => sreg <= x"9a00"; 116 | when x"33" => sreg <= x"b084"; 117 | 118 | when x"34" => sreg <= x"b10c"; 119 | when x"35" => sreg <= x"b20e"; 120 | 121 | when x"36" => sreg <= x"b382"; 122 | when x"37" => sreg <= x"b80a"; 123 | when x"38" => sreg <= x"138e";--x"138e"; -- COM8 - AGC switched off 138f for default, White balance 124 | when x"39" => sreg <= x"4200"; -- COM17 - Color bar removed 125 | -- when x"3A" => sreg <= x"10" & AECH; 126 | -- when x"3B" => sreg <= "0111000000" & AECHH; 127 | 128 | -- when x"10" => sreg <= x"703a"; -- SCALING_XSC 129 | -- when x"11" => sreg <= x"7135"; -- SCALING_YSC 130 | -- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11 131 | -- when x"13" => sreg <= x"7300"; -- SCALING_PCLK_DIV 132 | -- when x"14" => sreg <= x"a200"; -- SCALING_PCLK_DELAY must match COM14 133 | -- when x"15" => sreg <= x"1500"; -- COM10 Use HREF not hSYNC 134 | -- 135 | -- when x"1D" => sreg <= x"B104"; -- ABLC1 - Turn on auto black level 136 | -- when x"1F" => sreg <= x"138F"; -- COM8 - AGC, White balance 137 | -- when x"21" => sreg <= x"FFFF"; -- spare 138 | -- when x"22" => sreg <= x"FFFF"; -- spare 139 | -- when x"23" => sreg <= x"0000"; -- spare 140 | -- when x"24" => sreg <= x"0000"; -- spare 141 | -- when x"25" => sreg <= x"138F"; -- COM8 - AGC, White balance 142 | -- when x"26" => sreg <= x"0000"; -- spare 143 | -- when x"27" => sreg <= x"1000"; -- AECH Exposure 144 | -- when x"28" => sreg <= x"0D40"; -- COMM4 - Window Size 145 | -- when x"29" => sreg <= x"0000"; -- spare 146 | -- when x"2a" => sreg <= x"a505"; -- AECGMAX banding filter step 147 | -- when x"2b" => sreg <= x"2495"; -- AEW AGC Stable upper limite 148 | -- when x"2c" => sreg <= x"2533"; -- AEB AGC Stable lower limi 149 | -- when x"2d" => sreg <= x"26e3"; -- VPT AGC fast mode limits 150 | -- when x"2e" => sreg <= x"9f78"; -- HRL High reference level 151 | -- when x"2f" => sreg <= x"A068"; -- LRL low reference level 152 | -- when x"30" => sreg <= x"a103"; -- DSPC3 DSP control 153 | -- when x"31" => sreg <= x"A6d8"; -- LPH Lower Prob High 154 | -- when x"32" => sreg <= x"A7d8"; -- UPL Upper Prob Low 155 | -- when x"33" => sreg <= x"A8f0"; -- TPL Total Prob Low 156 | -- when x"34" => sreg <= x"A990"; -- TPH Total Prob High 157 | -- when x"35" => sreg <= x"AA94"; -- NALG AEC Algo select 158 | -- when x"36" => sreg <= x"13E5"; -- COM8 AGC Settings 159 | when others => sreg <= x"ffff"; 160 | end case; 161 | end if; 162 | end process; 163 | end Behavioral; 164 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/transmitter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Archfx/FPGA-DepthMap-Basys3/05cb76c8dbc11ef6f212b03a2d79099b1b0160ab/depthMap.srcs/sources_1/imports/transmitter.v -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/imports/vga.vhd: -------------------------------------------------------------------------------- 1 | 2 | ---------------------------------------------------------------------------------- 3 | library IEEE; 4 | use IEEE.STD_LOGIC_1164.ALL; 5 | use IEEE.STD_LOGIC_ARITH.ALL; 6 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 7 | 8 | 9 | 10 | entity VGA is 11 | Port ( CLK25 : in STD_LOGIC; -- 25 MHz 12 | clkout : out STD_LOGIC; 13 | rez_160x120 : IN std_logic; 14 | rez_320x240 : IN std_logic; 15 | Hsync,Vsync : out STD_LOGIC; 16 | Nblank : out STD_LOGIC; 17 | activeArea : out STD_LOGIC; 18 | Nsync : out STD_LOGIC; 19 | avg_en : out STD_LOGIC ); 20 | end VGA; 21 | 22 | architecture Behavioral of VGA is 23 | signal Hcnt:STD_LOGIC_VECTOR(9 downto 0):="0000000000"; 24 | signal Vcnt:STD_LOGIC_VECTOR(9 downto 0):="1000001000"; 25 | signal video:STD_LOGIC; 26 | 27 | constant HM: integer :=799; 28 | constant HD: integer :=640; 29 | constant HF: integer :=16; 30 | constant HB: integer :=48; 31 | constant HR: integer :=96; 32 | constant VM: integer :=524; 33 | constant VD: integer :=480; 34 | constant VF: integer :=10; 35 | constant VB: integer :=33; 36 | constant VR: integer :=2; 37 | 38 | begin 39 | 40 | 41 | process(CLK25) 42 | begin 43 | if (CLK25'event and CLK25='1') then 44 | if (Hcnt = HM) then 45 | Hcnt <= "0000000000"; 46 | if (Vcnt= VM) then 47 | Vcnt <= "0000000000"; 48 | activeArea <= '1'; 49 | else 50 | if rez_160x120 = '1' then 51 | if vCnt < 120-1 then 52 | activeArea <= '1'; 53 | end if; 54 | elsif rez_320x240 = '1' then 55 | if vCnt < 240-1 then 56 | activeArea <= '1'; 57 | end if; 58 | else 59 | if vCnt < 480-1 then 60 | activeArea <= '1'; 61 | end if; 62 | end if; 63 | Vcnt <= Vcnt+1; 64 | end if; 65 | else 66 | if rez_160x120 = '1' then 67 | if hcnt = 160-1 then 68 | activeArea <= '0'; 69 | end if; 70 | elsif rez_320x240 = '1' then 71 | if hcnt < 320 then 72 | avg_en <= '0'; 73 | else 74 | avg_en <= '1'; 75 | end if; 76 | if hcnt = 640-1 then 77 | activeArea <= '0'; 78 | end if; 79 | else 80 | if hcnt = 640-1 then 81 | activeArea <= '0'; 82 | end if; 83 | end if; 84 | Hcnt <= Hcnt + 1; 85 | end if; 86 | end if; 87 | end process; 88 | ---------------------------------------------------------------- 89 | 90 | -- Hsync: 91 | process(CLK25) 92 | begin 93 | if (CLK25'event and CLK25='1') then 94 | if (Hcnt >= (HD+HF) and Hcnt <= (HD+HF+HR-1)) then 95 | Hsync <= '0'; 96 | else 97 | Hsync <= '1'; 98 | end if; 99 | end if; 100 | end process; 101 | ---------------------------------------------------------------- 102 | 103 | -- Vsync: 104 | process(CLK25) 105 | begin 106 | if (CLK25'event and CLK25='1') then 107 | if (Vcnt >= (VD+VF) and Vcnt <= (VD+VF+VR-1)) then ---Vcnt >= 490 and vcnt<= 491 108 | Vsync <= '0'; 109 | else 110 | Vsync <= '1'; 111 | end if; 112 | end if; 113 | end process; 114 | ---------------------------------------------------------------- 115 | 116 | 117 | Nsync <= '1'; 118 | video <= '1' when (Hcnt < HD) and (Vcnt < VD) 119 | else '0'; 120 | Nblank <= video; 121 | clkout <= CLK25; 122 | 123 | 124 | end Behavioral; 125 | 126 | 127 | -------------------------------------------------------------------------------- /depthMap.srcs/sources_1/new/Image_Rectification.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------- 2 | -- Company: 3 | -- Engineer: 4 | -- 5 | -- Create Date: 09/07/2019 10:25:48 AM 6 | -- Design Name: 7 | -- Module Name: Image_Rectification - Behavioral 8 | -- Project Name: 9 | -- Target Devices: 10 | -- Tool Versions: 11 | -- Description: 12 | -- 13 | -- Dependencies: 14 | -- 15 | -- Revision: 16 | -- Revision 0.01 - File Created 17 | -- Additional Comments: 18 | -- 19 | ---------------------------------------------------------------------------------- 20 | 21 | 22 | library IEEE; 23 | use IEEE.STD_LOGIC_1164.ALL; 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; 25 | use IEEE.numeric_std.all; 26 | 27 | -- Uncomment the following library declaration if using 28 | -- arithmetic functions with Signed or Unsigned values 29 | --use IEEE.NUMERIC_STD.ALL; 30 | 31 | -- Uncomment the following library declaration if instantiating 32 | -- any Xilinx leaf cells in this code. 33 | --library UNISIM; 34 | --use UNISIM.VComponents.all; 35 | 36 | entity Image_Rectification is 37 | Port (address_in : in STD_LOGIC_VECTOR (16 downto 0); 38 | plus : in STD_LOGIC; 39 | minus : in STD_LOGIC; 40 | plus_col : in STD_LOGIC; 41 | minus_col : in STD_LOGIC; 42 | CLK : in STD_LOGIC; 43 | exposure : out STD_LOGIC_VECTOR (15 downto 0); 44 | address_left : out STD_LOGIC_VECTOR (16 downto 0); 45 | address_right : out STD_LOGIC_VECTOR (16 downto 0)); 46 | end Image_Rectification; 47 | 48 | architecture Behavioral of Image_Rectification is 49 | 50 | signal adjust: STD_LOGIC_VECTOR (3 downto 0) := "1000"; 51 | signal adjust_vert: STD_LOGIC_VECTOR (7 downto 0) := "00010100"; 52 | 53 | signal counter: STD_LOGIC_VECTOR (15 downto 0); 54 | 55 | begin 56 | address_left <= address_in; 57 | address_right <= std_logic_vector(unsigned(address_in) + (to_integer(unsigned(adjust))*320) + to_integer(unsigned(adjust_vert))); 58 | 59 | --exposure<=adjust_exposure; 60 | 61 | caliberate_alignment_process: process (CLK) begin 62 | if rising_edge(CLK) then 63 | counter <= counter + '1'; 64 | if plus = '1' and counter = x"ffff" then 65 | adjust <= adjust + '1'; 66 | end if; 67 | if minus = '1' and counter = x"ffff" then 68 | adjust <= adjust - '1'; 69 | end if; 70 | end if; 71 | end process; 72 | caliberate_exposure_process: process (CLK) begin 73 | if rising_edge(CLK) then 74 | if plus_col = '1' and counter = x"ffff" then 75 | adjust_vert <= adjust_vert + '1'; 76 | end if; 77 | if minus_col = '1' and counter = x"ffff" then 78 | adjust_vert <= adjust_vert - '1'; 79 | end if; 80 | end if; 81 | end process; 82 | 83 | 84 | end Behavioral; 85 | --------------------------------------------------------------------------------