├── .codecov.yml ├── .gitattributes ├── .github └── workflows │ └── build.yml ├── .gitignore ├── .sbtopts ├── .scalafmt.conf ├── LICENSE ├── README.md ├── bootstrap └── alogic ├── build.sbt ├── doc ├── README.md ├── assert.md ├── bslice.svg ├── bslice.xml ├── bubble.svg ├── bubble.xml ├── builtins.md ├── compilation.md ├── compilation.svg ├── concepts.md ├── control-unit.svg ├── control.md ├── entities.md ├── expr.md ├── ffi.md ├── fslice.svg ├── fslice.xml ├── fsms.md ├── gen.md ├── import.md ├── index.md ├── install.md ├── interop.md ├── intro.svg ├── literals.md ├── memories.md ├── networks.md ├── output-slice-signal-dependencies.svg ├── output-slice-signal-dependencies.xml ├── output-storage.svg ├── params.md ├── pipelines.md ├── ports-sync-ready.svg ├── ports-sync.svg ├── ports-wave-none-reg.svg ├── ports-wave-none-wire.svg ├── ports-wave-sync-reg-wire.svg ├── ports.md ├── srams.md ├── statements.md ├── types.md ├── using.md ├── vectors.svg ├── verilog-diffs.md └── widths.md ├── project ├── build.properties ├── build.sbt └── plugins.sbt ├── setup-symbiyosys ├── setup-verilator └── src ├── main ├── antlr4 │ ├── AlogicLexer.g4 │ └── AlogicParser.g4 └── scala │ └── com │ └── argondesign │ └── alogic │ ├── CommandLineInterface.scala │ ├── Compiler.scala │ ├── OptionParser.scala │ ├── analysis │ ├── BitwiseLiveVariableAnalysis.scala │ ├── DataFlowAnalysis.scala │ ├── Liveness.scala │ ├── ReadSymbolBits.scala │ ├── ReadSymbols.scala │ ├── StaticEvaluation.scala │ ├── SymbolBitSet.scala │ ├── WrittenSymbolBits.scala │ ├── WrittenSymbols.scala │ └── WrittenSyms.scala │ ├── antlr │ ├── AlogicBaseVisitor.scala │ ├── AlogicParseErrorListener.scala │ ├── AlogicParserRuleContext.scala │ ├── AlogicScalarVisitor.scala │ ├── AlogicToken.scala │ ├── AlogicTokenFactory.scala │ ├── AntlrConverters.scala │ ├── ArgBuilder.scala │ ├── AssertionBuilder.scala │ ├── AttrBuilder.scala │ ├── BaseBuilder.scala │ ├── CaseBuilder.scala │ ├── DescBuilder.scala │ ├── EntBuilder.scala │ ├── ExprBuilder.scala │ ├── FromBuilder.scala │ ├── IdentBuilder.scala │ ├── ImportBuilder.scala │ ├── PackageBuilder.scala │ ├── PkgBuilder.scala │ ├── RecBuilder.scala │ ├── SlicesBuilder.scala │ ├── StmtBuilder.scala │ └── UsingBuilder.scala │ ├── ast │ ├── AttrOps.scala │ ├── CaseOps.scala │ ├── DeclEntityOps.scala │ ├── DeclOps.scala │ ├── DeclSingletonOps.scala │ ├── DefnEntityOps.scala │ ├── DefnOps.scala │ ├── DefnRecordOps.scala │ ├── DescOps.scala │ ├── ExprOps.scala │ ├── SpliceOps.scala │ ├── StatefulTreeTransformer.scala │ ├── StatelessTreeTransformer.scala │ ├── StmtCaseOps.scala │ ├── StmtOps.scala │ ├── TreeCopier.scala │ ├── TreeOps.scala │ ├── TreePrintOps.scala │ ├── TreeTransformer.scala │ ├── Trees.scala │ └── UsingOps.scala │ ├── backend │ ├── CodeGeneration.scala │ ├── CodeWriter.scala │ ├── EntityDetails.scala │ └── MakeVerilog.scala │ ├── builtins │ ├── AtBits.scala │ ├── AtDisplay.scala │ ├── AtEx.scala │ ├── AtFinish.scala │ ├── AtMax.scala │ ├── AtMin.scala │ ├── AtMsb.scala │ ├── AtSx.scala │ ├── AtUnknownI.scala │ ├── AtUnknownU.scala │ ├── AtZx.scala │ ├── Builtin.scala │ ├── Builtins.scala │ ├── DollarClog2.scala │ ├── DollarSigned.scala │ ├── DollarUnsigned.scala │ └── package.scala │ ├── core │ ├── Attribute.scala │ ├── Bindings.scala │ ├── CompilerContext.scala │ ├── FlowControlTypes.scala │ ├── FuncVariant.scala │ ├── Input.scala │ ├── Loc.scala │ ├── Locatable.scala │ ├── Locationed.scala │ ├── MessageBuffer.scala │ ├── Messages.scala │ ├── Messaging.scala │ ├── Output.scala │ ├── ParOrSeqIterable.scala │ ├── ParOrSeqMap.scala │ ├── Profiling.scala │ ├── Settings.scala │ ├── Source.scala │ ├── SourceContext.scala │ ├── SramFactory.scala │ ├── StackFactory.scala │ ├── StatelessTransforms.scala │ ├── Statistics.scala │ ├── StorageTypes.scala │ ├── Symbol.scala │ ├── SymbolAttributes.scala │ ├── SyncRegFactory.scala │ ├── SyncSliceFactory.scala │ ├── TypeAssigner.scala │ ├── TypeOps.scala │ ├── TypePrintOps.scala │ ├── Types.scala │ └── enums │ │ ├── EntityVariant.scala │ │ ├── ResetStyle.scala │ │ └── UninitializedLocals.scala │ ├── frontend │ ├── Clarify.scala │ ├── ConnectChecks.scala │ ├── Elaborate.scala │ ├── Evaluate.scala │ ├── Finalize.scala │ ├── Frontend.scala │ ├── Parser.scala │ ├── Result.scala │ ├── Specialize.scala │ ├── SymbolTable.scala │ ├── SyntaxCheck.scala │ ├── SyntaxNormalize.scala │ ├── TypeChecker.scala │ ├── TypeOf.scala │ └── UnusedCheck.scala │ ├── gcp │ └── FunctionCompile.scala │ ├── lib │ ├── Json.scala │ ├── Math.scala │ └── Matrix.scala │ ├── passes │ ├── AddClockAndReset.scala │ ├── AddSyntheticEntities.scala │ ├── AnalyseCallGraph.scala │ ├── CombineStatements.scala │ ├── ConvertControl.scala │ ├── ConvertCtrlFuncArgret.scala │ ├── ConvertCtrlFuncLocals.scala │ ├── CreateStateSystem.scala │ ├── CreateTemporaries.scala │ ├── DefaultAssignments.scala │ ├── DefaultStorage.scala │ ├── DescToDeclDefn.scala │ ├── Desugar.scala │ ├── DropPackageAndParametrizedDescs.scala │ ├── ExtractTypes.scala │ ├── Fold.scala │ ├── FrontendPass.scala │ ├── InferImplications.scala │ ├── InlineKnownVars.scala │ ├── InlineMethods.scala │ ├── InterconnectCheck.scala │ ├── LiftSrams.scala │ ├── LowerArrays.scala │ ├── LowerDeferredStatements.scala │ ├── LowerFlowControl.scala │ ├── LowerForeignFunctions.scala │ ├── LowerInterconnect.scala │ ├── LowerLoops.scala │ ├── LowerPipeline.scala │ ├── LowerRegPorts.scala │ ├── LowerSrams.scala │ ├── LowerStacks.scala │ ├── LowerVariables.scala │ ├── LowerVectors.scala │ ├── LowerWait.scala │ ├── MarkTopLevels.scala │ ├── NormalizeControl.scala │ ├── NormalizeFunctions.scala │ ├── NormalizeReferences.scala │ ├── OptimizeClearOnStall.scala │ ├── Pass.scala │ ├── Passes.scala │ ├── PortCheck.scala │ ├── PropagateImplications.scala │ ├── RemoveAssume.scala │ ├── RemoveRedundantAssignments.scala │ ├── RemoveStructuralSharing.scala │ ├── RemoveUnused.scala │ ├── RenameSymbols.scala │ ├── Replace1Stacks.scala │ ├── SignOffUnused.scala │ ├── SimplifyCat.scala │ ├── SimplifyStates.scala │ ├── SplitStructs.scala │ ├── TieOffInputs.scala │ ├── WriteAux.scala │ ├── WriteSchematic.scala │ └── package.scala │ ├── transform │ ├── Regularize.scala │ ├── ReplaceTermRefs.scala │ ├── SimplifyExpr.scala │ └── StatementFilter.scala │ └── util │ ├── BigIntOps.scala │ ├── BooleanOps.scala │ ├── IteratorOps.scala │ ├── Ordinal.scala │ ├── PartialMatch.scala │ ├── UnreachableException.scala │ └── package.scala └── test ├── resources └── compile │ ├── multi │ ├── args_dump_trees │ │ ├── not.alogic │ │ └── top.alogic │ ├── args_y_00 │ │ ├── something_that_hopefully_does_not_exist_in_tmp.alogic │ │ └── top.alogic │ ├── args_y_01 │ │ ├── something_that_hopefully_does_not_exist_in_tmp_nor_home.alogic │ │ └── top.alogic │ ├── args_y_02 │ │ ├── this_is_the_correct_package.alogic │ │ └── top.alogic │ ├── args_y_03 │ │ ├── top.alogic │ │ └── ydir │ │ │ └── this_is_the_correct_package.alogic │ ├── elab_hang_00 │ │ ├── a.alogic │ │ └── top.alogic │ ├── elab_hang_01 │ │ ├── top.alogic │ │ └── types.alogic │ ├── elab_hang_02 │ │ ├── top.alogic │ │ └── types.alogic │ ├── entity_name_collision │ │ ├── foo.alogic │ │ └── top.alogic │ ├── from │ │ ├── nest_00 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── nest_01 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── nest_02 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── nest_03 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── simple_00 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_01 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_02 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_03 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_04 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_05 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_06 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_07 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_08 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_09 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_10 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_11 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_12 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_13 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_14 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_15 │ │ │ └── top.alogic │ │ ├── specialized_00 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── specialized_01 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── specialized_02 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_00 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_01 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_02 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_03 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_04 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_05 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_06 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_07 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_08 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ └── transitive_09 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ ├── import │ │ ├── circular_00 │ │ │ └── top.alogic │ │ ├── circular_01 │ │ │ ├── other.alogic │ │ │ └── top.alogic │ │ ├── diamond_00 │ │ │ ├── leaf.alogic │ │ │ ├── mid_a.alogic │ │ │ ├── mid_b.alogic │ │ │ └── top.alogic │ │ ├── diamond_01 │ │ │ ├── leaf.alogic │ │ │ ├── mid_a.alogic │ │ │ ├── mid_b.alogic │ │ │ └── top.alogic │ │ ├── line_directive │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── nest_00 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── nest_01 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── nest_02 │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── parametrized_00 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_01 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_02 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_03 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_04 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_05 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_06 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── parametrized_07 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── relative_00 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── relative_01 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── relative_02 │ │ │ ├── a.alogic │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── relative_03 │ │ │ ├── a.alogic │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── relative_04 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── relative_05 │ │ │ ├── a.alogic │ │ │ ├── a │ │ │ │ └── b.alogic │ │ │ └── top.alogic │ │ ├── relative_06 │ │ │ ├── a │ │ │ │ └── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── relative_07 │ │ │ ├── a │ │ │ │ ├── b │ │ │ │ │ └── c.alogic │ │ │ │ └── d │ │ │ │ │ └── e.alogic │ │ │ └── top.alogic │ │ ├── relative_08 │ │ │ ├── a │ │ │ │ ├── b │ │ │ │ │ └── c.alogic │ │ │ │ └── d │ │ │ │ │ └── e.alogic │ │ │ └── top.alogic │ │ ├── relative_09 │ │ │ ├── a │ │ │ │ ├── b │ │ │ │ │ └── c.alogic │ │ │ │ └── d │ │ │ │ │ └── e.alogic │ │ │ └── top.alogic │ │ ├── simple_00 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_01 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_02 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_03 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_04 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_05 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_06 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_07 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_08 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_09 │ │ │ ├── a.alogic │ │ │ └── top.alogic │ │ ├── simple_10 │ │ │ └── top.alogic │ │ ├── transitive_00 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_01 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_02 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_03 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── transitive_04 │ │ │ ├── a.alogic │ │ │ ├── b.alogic │ │ │ └── top.alogic │ │ ├── unknown_file_type_00 │ │ │ ├── a.notalogic │ │ │ └── top.alogic │ │ └── unknown_file_type_01 │ │ │ ├── a │ │ │ └── top.alogic │ ├── propagate_param_value │ │ ├── inner.alogic │ │ ├── inner_2.alogic │ │ └── top.alogic │ ├── recursive_connect │ │ ├── recursive_connect.alogic │ │ └── top.alogic │ ├── reference_to_global_in_gen │ │ ├── test_add.alogic │ │ └── top.alogic │ ├── replace_with_specializations │ │ ├── sub.alogic │ │ └── top.alogic │ ├── select_yielding_alias_to_package_member │ │ ├── a.alogic │ │ └── top.alogic │ ├── select_yielding_package │ │ ├── a.alogic │ │ └── top.alogic │ ├── target_language_keyword_00 │ │ ├── always.alogic │ │ └── top.alogic │ ├── type_of_00 │ │ ├── a.alogic │ │ └── top.alogic │ └── unused_in_package │ │ ├── pkg.alogic │ │ └── top.alogic │ └── single │ ├── access_outer_instance.alogic │ ├── access_outer_param.alogic │ ├── access_outer_type.alogic │ ├── arbitrary_connects_builtins.alogic │ ├── arbitrary_connects_concats_reps.alogic │ ├── arbitrary_connects_const_param_indices.alogic │ ├── arbitrary_connects_consts_params.alogic │ ├── arbitrary_connects_dict_idents.alogic │ ├── arbitrary_connects_indices_slices.alogic │ ├── arbitrary_connects_structs.alogic │ ├── arbitrary_connects_structs_in_submodules.alogic │ ├── arbitrary_connects_submodules.alogic │ ├── args_dump_trees.alogic │ ├── args_input_file_does_not_exist.alogic │ ├── args_input_file_is_not_a_regular_file.alogic │ ├── args_profile.alogic │ ├── args_uninitialized_bad.alogic │ ├── args_uninitialized_none.alogic │ ├── args_uninitialized_ones.alogic │ ├── args_uninitialized_random.alogic │ ├── args_uninitialized_zeros.alogic │ ├── assert_false_0.alogic │ ├── assert_false_1.alogic │ ├── assert_false_2.alogic │ ├── assert_false_3.alogic │ ├── assert_false_4.alogic │ ├── assertions │ ├── stmt_unreachable_00.alogic │ ├── stmt_unreachable_01.alogic │ ├── stmt_unreachable_02.alogic │ ├── stmt_unreachable_03.alogic │ ├── stmt_unreachable_04.alogic │ ├── stmt_unreachable_05.alogic │ ├── stmt_unreachable_06.alogic │ ├── stmt_unreachable_07.alogic │ ├── stmt_unreachable_08.alogic │ ├── stmt_unreachable_09.alogic │ ├── stmt_unreachable_10.alogic │ ├── stmt_unreachable_11.alogic │ ├── stmt_unreachable_12.alogic │ ├── stmt_unreachable_13.alogic │ ├── stmt_unreachable_14.alogic │ ├── stmt_unreachable_15.alogic │ ├── stmt_unreachable_16.alogic │ ├── stmt_unreachable_17.alogic │ ├── stmt_unreachable_18.alogic │ ├── stmt_unreachable_19.alogic │ ├── stmt_unreachable_20.alogic │ ├── stmt_unreachable_21.alogic │ └── stmt_unreachable_22.alogic │ ├── assume_00.alogic │ ├── assume_01.alogic │ ├── assume_02.alogic │ ├── assume_03.alogic │ ├── assume_04.alogic │ ├── assume_05.alogic │ ├── assume_06.alogic │ ├── assume_07.alogic │ ├── assume_08.alogic │ ├── assume_09.alogic │ ├── assume_10.alogic │ ├── assume_11.alogic │ ├── assume_12.alogic │ ├── assume_13.alogic │ ├── assume_14.alogic │ ├── atbits.alogic │ ├── attributes │ ├── bad_liftsrams.alogic │ ├── bad_reclimit.alogic │ ├── bad_stacklimit.alogic │ └── bad_unknown.alogic │ ├── bad_gen_00.alogic │ ├── bad_gen_01.alogic │ ├── bad_gen_02.alogic │ ├── bad_gen_03.alogic │ ├── bad_gen_04.alogic │ ├── bad_gen_05.alogic │ ├── bad_gen_06.alogic │ ├── bad_gen_07.alogic │ ├── bad_gen_08.alogic │ ├── bad_gen_09.alogic │ ├── bad_gen_10.alogic │ ├── bad_gen_11.alogic │ ├── bad_static_function_definition_00.alogic │ ├── bad_static_function_definition_01.alogic │ ├── bad_static_function_definition_02.alogic │ ├── bad_static_function_definition_03.alogic │ ├── bad_static_function_definition_04.alogic │ ├── bad_static_function_definition_05.alogic │ ├── bad_static_function_definition_06.alogic │ ├── bad_static_function_definition_07.alogic │ ├── bad_unsized_type_00.alogic │ ├── bad_unsized_type_01.alogic │ ├── bad_unsized_type_02.alogic │ ├── bad_void_type_00.alogic │ ├── bad_void_type_01.alogic │ ├── bad_void_type_02.alogic │ ├── bad_void_type_03.alogic │ ├── bad_void_type_04.alogic │ ├── bad_void_type_05.alogic │ ├── badly_unresolvable_name.alogic │ ├── bind │ ├── bind_00.alogic │ ├── bind_01.alogic │ ├── bind_02.alogic │ ├── bind_03.alogic │ ├── bind_04.alogic │ ├── bind_05.alogic │ ├── bind_06.alogic │ ├── bound_entity_with_outputs.alogic │ └── bound_entity_with_sync_ready_inputs.alogic │ ├── builtin_ex_00.alogic │ ├── builtin_sx_00.alogic │ ├── builtin_zx_00.alogic │ ├── cardinal_ports_0.alogic │ ├── cardinal_ports_1.alogic │ ├── cardinal_ports_2.alogic │ ├── cardinal_ports_3.alogic │ ├── checker_0.alogic │ ├── checker_1.alogic │ ├── checker_2.alogic │ ├── checker_3.alogic │ ├── circular_definition_0.alogic │ ├── circular_definition_1.alogic │ ├── circular_definition_2.alogic │ ├── circular_definition_3.alogic │ ├── circular_definition_4.alogic │ ├── circular_definition_5.alogic │ ├── circular_definition_6.alogic │ ├── circular_reference_0.alogic │ ├── circular_reference_1.alogic │ ├── comb_func │ ├── nested_in_comb_func_00.alogic │ ├── nested_in_comb_func_01.alogic │ ├── nested_in_comb_func_02.alogic │ ├── nested_in_comb_func_03.alogic │ ├── nested_in_comb_func_04.alogic │ ├── nested_in_ctrl_func_00.alogic │ ├── nested_in_ctrl_func_01.alogic │ ├── nested_in_ctrl_func_02.alogic │ ├── nested_in_ctrl_func_03.alogic │ ├── nested_in_ctrl_func_04.alogic │ ├── simple_00.alogic │ ├── simple_01.alogic │ ├── simple_02.alogic │ └── simple_03.alogic │ ├── comb_func_in_loop_cond_00.alogic │ ├── comb_return_00.alogic │ ├── compile_specialized_00.alogic │ ├── compile_specialized_01.alogic │ ├── compile_specialized_02.alogic │ ├── compile_wrapper_00.alogic │ ├── const_bad_00.alogic │ ├── const_in_stmt_due_to_elab.alogic │ ├── const_vector_concat.alogic │ ├── const_vector_rep.alogic │ ├── const_with_atbits.alogic │ ├── control_call_00.alogic │ ├── control_call_01.alogic │ ├── control_call_02.alogic │ ├── control_call_03.alogic │ ├── control_call_04.alogic │ ├── control_call_05.alogic │ ├── control_call_06.alogic │ ├── control_case_00.alogic │ ├── control_case_01.alogic │ ├── control_case_02.alogic │ ├── control_case_03.alogic │ ├── control_case_04.alogic │ ├── control_case_05.alogic │ ├── control_case_06.alogic │ ├── control_case_07.alogic │ ├── control_do_00.alogic │ ├── control_do_01.alogic │ ├── control_do_02.alogic │ ├── control_do_03.alogic │ ├── control_for_00.alogic │ ├── control_for_01.alogic │ ├── control_for_02.alogic │ ├── control_for_03.alogic │ ├── control_for_04.alogic │ ├── control_for_05.alogic │ ├── control_for_06.alogic │ ├── control_for_07.alogic │ ├── control_for_08.alogic │ ├── control_for_09.alogic │ ├── control_for_10.alogic │ ├── control_for_11.alogic │ ├── control_for_12.alogic │ ├── control_if_00.alogic │ ├── control_if_01.alogic │ ├── control_if_02.alogic │ ├── control_if_03.alogic │ ├── control_if_04.alogic │ ├── control_if_05.alogic │ ├── control_if_06.alogic │ ├── control_loop_00.alogic │ ├── control_loop_01.alogic │ ├── control_loop_02.alogic │ ├── control_loop_03.alogic │ ├── control_while_00.alogic │ ├── control_while_01.alogic │ ├── control_while_02.alogic │ ├── control_while_03.alogic │ ├── ctrl_argret_00.alogic │ ├── ctrl_argret_01.alogic │ ├── ctrl_argret_02.alogic │ ├── ctrl_argret_03.alogic │ ├── ctrl_argret_04.alogic │ ├── ctrl_argret_05.alogic │ ├── ctrl_argret_06.alogic │ ├── ctrl_argret_07.alogic │ ├── ctrl_argret_08.alogic │ ├── ctrl_argret_09.alogic │ ├── ctrl_argret_10.alogic │ ├── ctrl_argret_11.alogic │ ├── ctrl_func_local_00.alogic │ ├── ctrl_func_local_01.alogic │ ├── ctrl_func_local_02.alogic │ ├── ctrl_func_local_03.alogic │ ├── ctrl_func_local_04.alogic │ ├── ctrl_func_local_05.alogic │ ├── ctrl_func_local_06.alogic │ ├── ctrl_func_local_07.alogic │ ├── ctrl_func_local_08.alogic │ ├── ctrl_func_local_09.alogic │ ├── ctrl_func_local_10.alogic │ ├── ctrl_func_local_11.alogic │ ├── ctrl_func_local_12.alogic │ ├── ctrl_func_return_0.alogic │ ├── ctrl_func_return_1.alogic │ ├── ctrl_func_return_2.alogic │ ├── ctrl_func_return_3.alogic │ ├── ctrl_func_static_00.alogic │ ├── ctrl_func_static_01.alogic │ ├── ctrl_func_static_02.alogic │ ├── ctrl_func_static_03.alogic │ ├── def_ent_0.alogic │ ├── def_ent_1.alogic │ ├── def_ent_2.alogic │ ├── def_ent_3.alogic │ ├── defer │ ├── display_00.alogic │ ├── display_01.alogic │ ├── display_02.alogic │ ├── display_03.alogic │ ├── display_04.alogic │ ├── display_05.alogic │ ├── finish_00.alogic │ └── finish_01.alogic │ ├── definition_in_fence_block.alogic │ ├── dependent_gen_0.alogic │ ├── dependent_gen_1.alogic │ ├── dependent_gen_2.alogic │ ├── dependent_gen_3.alogic │ ├── dependent_param_size_0.alogic │ ├── dependent_param_size_1.alogic │ ├── dependent_param_size_2.alogic │ ├── dependent_param_size_3.alogic │ ├── dependent_param_size_4.alogic │ ├── dependent_param_size_5.alogic │ ├── dictident_adder_tree.alogic │ ├── dictident_decl_0.alogic │ ├── dictident_decl_1.alogic │ ├── dictident_decl_10.alogic │ ├── dictident_decl_11.alogic │ ├── dictident_decl_12.alogic │ ├── dictident_decl_13.alogic │ ├── dictident_decl_14.alogic │ ├── dictident_decl_15.alogic │ ├── dictident_decl_16.alogic │ ├── dictident_decl_17.alogic │ ├── dictident_decl_18.alogic │ ├── dictident_decl_2.alogic │ ├── dictident_decl_3.alogic │ ├── dictident_decl_4.alogic │ ├── dictident_decl_5.alogic │ ├── dictident_decl_6.alogic │ ├── dictident_decl_7.alogic │ ├── dictident_decl_8.alogic │ ├── dictident_decl_9.alogic │ ├── dictident_defn_0.alogic │ ├── dictident_defn_1.alogic │ ├── dictident_defn_10.alogic │ ├── dictident_defn_11.alogic │ ├── dictident_defn_2.alogic │ ├── dictident_defn_3.alogic │ ├── dictident_defn_4.alogic │ ├── dictident_defn_5.alogic │ ├── dictident_defn_6.alogic │ ├── dictident_defn_7.alogic │ ├── dictident_defn_8.alogic │ ├── dictident_defn_9.alogic │ ├── dictident_entity_0.alogic │ ├── dictident_entity_1.alogic │ ├── dictident_entity_2.alogic │ ├── dictident_entity_3.alogic │ ├── dictident_entity_4.alogic │ ├── dictident_entity_5.alogic │ ├── dictident_entity_6.alogic │ ├── dictident_entity_7.alogic │ ├── dictident_function_0.alogic │ ├── dictident_function_1.alogic │ ├── dictident_function_2.alogic │ ├── dictident_function_3.alogic │ ├── dictident_function_4.alogic │ ├── dictident_function_5.alogic │ ├── dictident_hard_0.alogic │ ├── dictident_hard_1.alogic │ ├── dictident_instance_0.alogic │ ├── dictident_instance_1.alogic │ ├── dictident_instance_2.alogic │ ├── dictident_instance_3.alogic │ ├── dictident_instance_4.alogic │ ├── dictident_instance_5.alogic │ ├── dictident_instance_6.alogic │ ├── dictident_main_fsm.alogic │ ├── dictident_negative_0.alogic │ ├── dictident_port_0.alogic │ ├── dictident_port_1.alogic │ ├── dictident_port_2.alogic │ ├── dictident_port_3.alogic │ ├── dictident_struct_0.alogic │ ├── dictident_struct_1.alogic │ ├── dictident_struct_10.alogic │ ├── dictident_struct_11.alogic │ ├── dictident_struct_2.alogic │ ├── dictident_struct_3.alogic │ ├── dictident_struct_4.alogic │ ├── dictident_struct_5.alogic │ ├── dictident_struct_6.alogic │ ├── dictident_struct_7.alogic │ ├── dictident_struct_8.alogic │ ├── dictident_struct_9.alogic │ ├── do_not_fold_index_into_const.alogic │ ├── double_typedef.alogic │ ├── elab_hang_00.alogic │ ├── elaborate_00.alogic │ ├── elaborate_01.alogic │ ├── elaborate_02.alogic │ ├── elaborate_03.alogic │ ├── elaborate_04.alogic │ ├── elaborate_05.alogic │ ├── elaborate_06.alogic │ ├── elaborate_07.alogic │ ├── elaborate_08.alogic │ ├── elaborate_09.alogic │ ├── empty.alogic │ ├── empty_fsm.alogic │ ├── empty_if_stmt.alogic │ ├── empty_main_with_out_sync.alogic │ ├── empty_state_replaced_with_redudant_state.alogic │ ├── ent_static_assert_0.alogic │ ├── ent_static_assert_1.alogic │ ├── ent_static_assert_2.alogic │ ├── ent_static_assert_3.alogic │ ├── ent_static_assert_4.alogic │ ├── ent_static_assert_5.alogic │ ├── ent_static_assert_6.alogic │ ├── ent_static_assert_7.alogic │ ├── ent_static_assert_8.alogic │ ├── expr_index_00.alogic │ ├── expr_index_01.alogic │ ├── expr_index_02.alogic │ ├── expr_slice_00.alogic │ ├── expr_slice_01.alogic │ ├── expr_slice_02.alogic │ ├── expr_slice_03.alogic │ ├── external_const_00.alogic │ ├── external_const_01.alogic │ ├── extract_assignments_00.alogic │ ├── fence_only_fsm.alogic │ ├── fold │ ├── default_case_00.alogic │ ├── default_case_01.alogic │ ├── default_case_02.alogic │ └── default_case_03.alogic │ ├── folding_before_lower_structs.alogic │ ├── folding_before_lower_vectors.alogic │ ├── foreign_func_00.alogic │ ├── foreign_func_01.alogic │ ├── foreign_func_02.alogic │ ├── foreign_func_03.alogic │ ├── foreign_func_04.alogic │ ├── foreign_func_05.alogic │ ├── foreign_func_06.alogic │ ├── foreign_func_07.alogic │ ├── foreign_func_08.alogic │ ├── foreign_func_09.alogic │ ├── foreign_func_10.alogic │ ├── foreign_func_11.alogic │ ├── foreign_func_12.alogic │ ├── foreign_func_13.alogic │ ├── foreign_func_14.alogic │ ├── foreign_func_15.alogic │ ├── foreign_func_16.alogic │ ├── foreign_func_17.alogic │ ├── foreign_func_18.alogic │ ├── foreign_func_19.alogic │ ├── foreign_func_20.alogic │ ├── full_width_plus_slice.alogic │ ├── gen_alt_autoinst_0.alogic │ ├── gen_alt_autoinst_1.alogic │ ├── gen_alt_autoinst_2.alogic │ ├── gen_alt_autoinst_3.alogic │ ├── gen_alt_defn_0.alogic │ ├── gen_alt_defn_1.alogic │ ├── gen_alt_defn_2.alogic │ ├── gen_alt_defn_3.alogic │ ├── gen_alt_defn_4.alogic │ ├── gen_alt_defn_5.alogic │ ├── gen_alt_defn_6.alogic │ ├── gen_alt_defn_7.alogic │ ├── gen_alt_defn_8.alogic │ ├── gen_alt_defn_9.alogic │ ├── gen_alt_entity_0.alogic │ ├── gen_alt_entity_1.alogic │ ├── gen_alt_entity_2.alogic │ ├── gen_alt_entity_3.alogic │ ├── gen_alt_func_0.alogic │ ├── gen_alt_func_1.alogic │ ├── gen_alt_func_2.alogic │ ├── gen_alt_func_3.alogic │ ├── gen_alt_main_0.alogic │ ├── gen_alt_main_1.alogic │ ├── gen_alt_port_0.alogic │ ├── gen_alt_port_1.alogic │ ├── gen_alt_port_2.alogic │ ├── gen_alt_port_3.alogic │ ├── gen_alt_port_4.alogic │ ├── gen_const_00.alogic │ ├── gen_const_01.alogic │ ├── gen_const_02.alogic │ ├── gen_const_03.alogic │ ├── gen_crazy_00.alogic │ ├── gen_decoder.alogic │ ├── gen_dict_index_type_error_0.alogic │ ├── gen_dict_index_type_error_1.alogic │ ├── gen_empty_ctrl_else.alogic │ ├── gen_ent_0.alogic │ ├── gen_ent_1.alogic │ ├── gen_ent_10.alogic │ ├── gen_ent_2.alogic │ ├── gen_ent_3.alogic │ ├── gen_ent_4.alogic │ ├── gen_ent_5.alogic │ ├── gen_ent_6.alogic │ ├── gen_ent_7.alogic │ ├── gen_ent_8.alogic │ ├── gen_ent_9.alogic │ ├── gen_ent_static_assert_0.alogic │ ├── gen_ent_static_assert_1.alogic │ ├── gen_for_bad_00.alogic │ ├── gen_for_bad_01.alogic │ ├── gen_for_bad_02.alogic │ ├── gen_for_bad_03.alogic │ ├── gen_for_bad_04.alogic │ ├── gen_for_bad_05.alogic │ ├── gen_for_bad_06.alogic │ ├── gen_for_case_0.alogic │ ├── gen_for_downwards_0.alogic │ ├── gen_for_downwards_1.alogic │ ├── gen_for_downwards_2.alogic │ ├── gen_for_downwards_3.alogic │ ├── gen_for_infinite_0.alogic │ ├── gen_for_infinite_1.alogic │ ├── gen_for_infinite_2.alogic │ ├── gen_for_named_00.alogic │ ├── gen_for_named_01.alogic │ ├── gen_for_named_02.alogic │ ├── gen_for_named_03.alogic │ ├── gen_for_named_04.alogic │ ├── gen_for_named_05.alogic │ ├── gen_for_named_06.alogic │ ├── gen_for_named_07.alogic │ ├── gen_for_named_08.alogic │ ├── gen_for_named_09.alogic │ ├── gen_for_named_10.alogic │ ├── gen_for_named_11.alogic │ ├── gen_for_negative_0.alogic │ ├── gen_for_prune_unused_0.alogic │ ├── gen_for_prune_unused_1.alogic │ ├── gen_for_prune_unused_2.alogic │ ├── gen_for_prune_unused_3.alogic │ ├── gen_for_scope_0.alogic │ ├── gen_for_scope_1.alogic │ ├── gen_for_scope_2.alogic │ ├── gen_for_stmt_0.alogic │ ├── gen_for_stmt_1.alogic │ ├── gen_for_stmt_2.alogic │ ├── gen_for_stmt_3.alogic │ ├── gen_for_stmt_4.alogic │ ├── gen_for_stmt_5.alogic │ ├── gen_if_bad_0.alogic │ ├── gen_if_bad_1.alogic │ ├── gen_if_bad_2.alogic │ ├── gen_if_bad_3.alogic │ ├── gen_if_bad_4.alogic │ ├── gen_if_case_0.alogic │ ├── gen_if_case_1.alogic │ ├── gen_if_elif_stmt_0.alogic │ ├── gen_if_named_00.alogic │ ├── gen_if_named_01.alogic │ ├── gen_if_named_02.alogic │ ├── gen_if_named_03.alogic │ ├── gen_if_named_04.alogic │ ├── gen_if_named_05.alogic │ ├── gen_if_named_06.alogic │ ├── gen_if_named_07.alogic │ ├── gen_if_named_08.alogic │ ├── gen_if_scope_0.alogic │ ├── gen_if_stmt_0.alogic │ ├── gen_if_stmt_1.alogic │ ├── gen_in_if_0.alogic │ ├── gen_in_singleton.alogic │ ├── gen_nest_stmt_0.alogic │ ├── gen_nest_stmt_1.alogic │ ├── gen_nest_stmt_2.alogic │ ├── gen_nest_stmt_3.alogic │ ├── gen_param_00.alogic │ ├── gen_range_bad_00.alogic │ ├── gen_range_bad_01.alogic │ ├── gen_range_bad_02.alogic │ ├── gen_range_bad_03.alogic │ ├── gen_range_case_0.alogic │ ├── gen_range_named_00.alogic │ ├── gen_range_named_01.alogic │ ├── gen_range_named_02.alogic │ ├── gen_range_named_03.alogic │ ├── gen_range_named_04.alogic │ ├── gen_range_named_05.alogic │ ├── gen_range_named_06.alogic │ ├── gen_range_named_07.alogic │ ├── gen_range_named_08.alogic │ ├── gen_range_named_09.alogic │ ├── gen_range_named_10.alogic │ ├── gen_range_named_11.alogic │ ├── gen_range_not_escaping_shadow_0.alogic │ ├── gen_range_not_escaping_shadow_1.alogic │ ├── gen_range_scope_0.alogic │ ├── gen_range_scope_1.alogic │ ├── gen_range_signed_00.alogic │ ├── gen_range_signed_01.alogic │ ├── gen_range_stmt_0.alogic │ ├── gen_range_stmt_1.alogic │ ├── gen_range_stmt_2.alogic │ ├── gen_range_stmt_3.alogic │ ├── gen_range_stmt_4.alogic │ ├── gen_range_stmt_5.alogic │ ├── gen_range_stmt_6.alogic │ ├── gen_range_stmt_7.alogic │ ├── gen_rec_static_assert_0.alogic │ ├── gen_rec_static_assert_1.alogic │ ├── gen_static_assert_0.alogic │ ├── gen_static_assert_1.alogic │ ├── gen_static_assert_3.alogic │ ├── gen_static_assert_4.alogic │ ├── gen_stmt_static_assert_0.alogic │ ├── gen_stmt_static_assert_1.alogic │ ├── generated_unsized_struct_member.alogic │ ├── huge_width_00.alogic │ ├── if_then_else_redef_0.alogic │ ├── if_then_else_redef_1.alogic │ ├── import_bad_00.alogic │ ├── import_bad_01.alogic │ ├── inline_known_port_00.alogic │ ├── inline_known_vars_00.alogic │ ├── inline_known_vars_01.alogic │ ├── inline_known_vars_02.alogic │ ├── inline_type_punned_struct_value.alogic │ ├── inlineunsizedconst_before_liftentities.alogic │ ├── instance_sel_struct_port.alogic │ ├── int_attribute.alogic │ ├── interconnect_check_00.alogic │ ├── interconnect_check_01.alogic │ ├── interconnect_check_02.alogic │ ├── interconnect_check_03.alogic │ ├── interconnect_check_04.alogic │ ├── interconnect_check_05.alogic │ ├── interconnect_check_06.alogic │ ├── interconnect_check_07.alogic │ ├── interconnect_check_08.alogic │ ├── interconnect_check_09.alogic │ ├── interconnect_check_10.alogic │ ├── interconnect_check_11.alogic │ ├── interconnect_check_12.alogic │ ├── interconnect_check_13.alogic │ ├── interconnect_check_14.alogic │ ├── interconnect_check_15.alogic │ ├── interconnect_check_16.alogic │ ├── interconnect_check_17.alogic │ ├── interconnect_check_18.alogic │ ├── lfsr_struct.alogic │ ├── lift_entities_0.alogic │ ├── lift_entities_1.alogic │ ├── lift_entities_2.alogic │ ├── lift_entities_3.alogic │ ├── lift_srams_00.alogic │ ├── lift_srams_01.alogic │ ├── lift_srams_02.alogic │ ├── lift_srams_03.alogic │ ├── lift_srams_04.alogic │ ├── lift_srams_05.alogic │ ├── lift_srams_06.alogic │ ├── lift_srams_07.alogic │ ├── lift_srams_08.alogic │ ├── lift_srams_09.alogic │ ├── lift_srams_10.alogic │ ├── lift_srams_11.alogic │ ├── lift_srams_12.alogic │ ├── lift_srams_13.alogic │ ├── lift_srams_14.alogic │ ├── lift_srams_15.alogic │ ├── lift_srams_16.alogic │ ├── line_directive_bad_00.alogic │ ├── line_directive_bad_01.alogic │ ├── line_directive_bad_02.alogic │ ├── line_directive_bad_03.alogic │ ├── lower_array_0.alogic │ ├── lower_array_1.alogic │ ├── lower_array_2.alogic │ ├── lower_array_3.alogic │ ├── lower_array_4.alogic │ ├── lower_flow_control_0.alogic │ ├── lower_flow_control_1.alogic │ ├── lower_flow_control_2.alogic │ ├── lower_flow_control_3.alogic │ ├── lower_flow_control_4.alogic │ ├── lower_flow_control_5.alogic │ ├── lower_variables_async_high_0.alogic │ ├── lower_variables_async_high_1.alogic │ ├── lower_variables_async_high_2.alogic │ ├── lower_variables_async_low_0.alogic │ ├── lower_variables_async_low_1.alogic │ ├── lower_variables_async_low_2.alogic │ ├── lower_variables_sync_high_0.alogic │ ├── lower_variables_sync_high_1.alogic │ ├── lower_variables_sync_high_2.alogic │ ├── lower_variables_sync_low_0.alogic │ ├── lower_variables_sync_low_1.alogic │ ├── lower_variables_sync_low_2.alogic │ ├── manifest_dictident_ports.alogic │ ├── manifest_ports_00.alogic │ ├── manifest_ports_01.alogic │ ├── manifest_ports_02.alogic │ ├── manifest_ports_03.alogic │ ├── method_bad_00.alogic │ ├── method_bad_01.alogic │ ├── method_bad_02.alogic │ ├── method_bad_03.alogic │ ├── method_bug_00.alogic │ ├── method_call_on_member_00.alogic │ ├── method_empty.alogic │ ├── method_input_00.alogic │ ├── method_normal_00.alogic │ ├── method_normal_01.alogic │ ├── method_normal_02.alogic │ ├── method_normal_03.alogic │ ├── method_normal_04.alogic │ ├── method_normal_05.alogic │ ├── method_output_00.alogic │ ├── method_pipeline_00.alogic │ ├── method_pipeline_01.alogic │ ├── method_pure_00.alogic │ ├── method_pure_01.alogic │ ├── method_pure_02.alogic │ ├── method_pure_03.alogic │ ├── method_pure_04.alogic │ ├── method_pure_05.alogic │ ├── method_pure_06.alogic │ ├── method_pure_07.alogic │ ├── method_pure_08.alogic │ ├── method_pure_09.alogic │ ├── method_pure_10.alogic │ ├── method_pure_11.alogic │ ├── method_pure_12.alogic │ ├── method_pure_13.alogic │ ├── method_pure_14.alogic │ ├── method_pure_15.alogic │ ├── method_pure_16.alogic │ ├── method_pure_17.alogic │ ├── method_pure_18.alogic │ ├── method_pure_19.alogic │ ├── method_pure_20.alogic │ ├── method_pure_21.alogic │ ├── method_pure_22.alogic │ ├── method_pure_23.alogic │ ├── method_pure_24.alogic │ ├── method_pure_25.alogic │ ├── method_pure_26.alogic │ ├── method_pure_27.alogic │ ├── method_pure_28.alogic │ ├── method_pure_29.alogic │ ├── method_pure_30.alogic │ ├── method_recursive_0.alogic │ ├── method_recursive_1.alogic │ ├── method_recursive_2.alogic │ ├── method_recursive_3.alogic │ ├── method_static_0.alogic │ ├── method_static_1.alogic │ ├── method_static_2.alogic │ ├── method_static_3.alogic │ ├── method_static_4.alogic │ ├── method_static_5.alogic │ ├── mixed_param_assign.alogic │ ├── multiple_main_fsm.alogic │ ├── multiple_top_entities_without_compile_directive_00.alogic │ ├── multiple_top_entities_without_compile_directive_01.alogic │ ├── name_shadowing_00.alogic │ ├── name_shadowing_01.alogic │ ├── nested_parametrized_00.alogic │ ├── nested_parametrized_01.alogic │ ├── nested_struct_00.alogic │ ├── no_such_param_00.alogic │ ├── no_such_param_01.alogic │ ├── no_such_param_02.alogic │ ├── no_target.alogic │ ├── out_reg_00.alogic │ ├── out_reg_01.alogic │ ├── out_sync_00.alogic │ ├── out_sync_01.alogic │ ├── out_sync_ready_00.alogic │ ├── out_sync_ready_01.alogic │ ├── out_sync_ready_02.alogic │ ├── out_sync_ready_03.alogic │ ├── out_sync_ready_04.alogic │ ├── out_sync_ready_05.alogic │ ├── out_sync_ready_06.alogic │ ├── out_sync_ready_07.alogic │ ├── out_sync_ready_08.alogic │ ├── out_sync_ready_09.alogic │ ├── output_as_index.alogic │ ├── output_name_max_length_0.alogic │ ├── output_name_max_length_1.alogic │ ├── output_name_max_length_2.alogic │ ├── package_params_00.alogic │ ├── package_params_01.alogic │ ├── package_params_02.alogic │ ├── package_params_03.alogic │ ├── package_params_04.alogic │ ├── package_params_05.alogic │ ├── package_params_06.alogic │ ├── package_params_07.alogic │ ├── package_params_08.alogic │ ├── package_params_09.alogic │ ├── package_params_10.alogic │ ├── param_assignment_required_0.alogic │ ├── param_assignment_required_1.alogic │ ├── param_assignment_required_2.alogic │ ├── param_assignment_required_3.alogic │ ├── param_bad_00.alogic │ ├── param_bad_01.alogic │ ├── param_bad_02.alogic │ ├── param_scope_00.alogic │ ├── param_spec_0.alogic │ ├── param_type_00.alogic │ ├── param_type_01.alogic │ ├── param_type_02.alogic │ ├── param_type_03.alogic │ ├── param_type_04.alogic │ ├── param_type_05.alogic │ ├── param_type_06.alogic │ ├── param_type_07.alogic │ ├── param_type_08.alogic │ ├── param_without_default.alogic │ ├── parametrized_top_entity_without_compile_directive.alogic │ ├── pipeline │ ├── degenerate_00.alogic │ ├── degenerate_01.alogic │ ├── degenerate_02.alogic │ ├── gen_pipeline_var_00.alogic │ ├── gen_pipeline_var_01.alogic │ ├── gen_pipeline_var_02.alogic │ ├── gen_pipeline_var_03.alogic │ ├── nested_00.alogic │ ├── pipeline_00.alogic │ ├── pipeline_01.alogic │ ├── pipeline_02.alogic │ ├── pipeline_03.alogic │ ├── pipeline_04.alogic │ ├── pipeline_05.alogic │ ├── pipeline_06.alogic │ ├── pipeline_07.alogic │ ├── pipeline_08.alogic │ ├── pipeline_09.alogic │ ├── port_access_00.alogic │ ├── port_access_01.alogic │ └── port_access_02.alogic │ ├── port_check_nested_00.alogic │ ├── port_check_nested_01.alogic │ ├── port_default_only.alogic │ ├── ports_only_fsm.alogic │ ├── ports_only_network.alogic │ ├── ports_only_verbatim.alogic │ ├── prune_unreachable_states.alogic │ ├── prune_unused_flops_0.alogic │ ├── prune_unused_flops_1.alogic │ ├── rec_static_assert_0.alogic │ ├── rec_static_assert_1.alogic │ ├── rec_static_assert_2.alogic │ ├── rec_static_assert_3.alogic │ ├── rec_static_assert_4.alogic │ ├── rec_static_assert_5.alogic │ ├── rec_static_assert_6.alogic │ ├── rec_static_assert_7.alogic │ ├── rec_static_assert_8.alogic │ ├── recursive_adder_tree.alogic │ ├── recursive_adder_tree_arb_connect.alogic │ ├── recursive_connect.alogic │ ├── recursive_goto_0.alogic │ ├── recursive_goto_1.alogic │ ├── recursive_goto_2.alogic │ ├── recursive_goto_3.alogic │ ├── recursive_type_00.alogic │ ├── recursive_type_01.alogic │ ├── rename_public_member.alogic │ ├── resolve_names_00.alogic │ ├── resolve_names_01.alogic │ ├── resolve_names_02.alogic │ ├── resolve_names_03.alogic │ ├── resolve_names_04.alogic │ ├── resolve_names_05.alogic │ ├── resolve_names_06.alogic │ ├── return_in_gen.alogic │ ├── reused_for_var.alogic │ ├── same_param.alogic │ ├── signoff_unused_out_of_bounds.alogic │ ├── simplify_cat_00.alogic │ ├── simplify_slice_over_index.alogic │ ├── single_param_entity_0.alogic │ ├── single_param_entity_1.alogic │ ├── single_param_entity_2.alogic │ ├── single_param_entity_3.alogic │ ├── single_param_entity_4.alogic │ ├── single_param_struct_0.alogic │ ├── single_param_struct_1.alogic │ ├── single_param_struct_2.alogic │ ├── single_param_struct_3.alogic │ ├── single_param_struct_4.alogic │ ├── singleton_is_singleton.alogic │ ├── sized_param_init_0.alogic │ ├── sized_param_init_1.alogic │ ├── snoop_ports │ ├── snoop_00.alogic │ ├── snoop_01.alogic │ ├── snoop_02.alogic │ ├── snoop_03.alogic │ ├── snoop_04.alogic │ ├── snoop_05.alogic │ ├── snoop_06.alogic │ ├── snoop_07.alogic │ ├── snoop_08.alogic │ ├── snoop_09.alogic │ ├── snoop_10.alogic │ ├── snoop_11.alogic │ └── snoop_12.alogic │ ├── specialize_hard_00.alogic │ ├── specialize_hard_01.alogic │ ├── specialize_hard_02.alogic │ ├── specialize_hard_03.alogic │ ├── specialize_same_0.alogic │ ├── specialize_same_1.alogic │ ├── specialize_same_2.alogic │ ├── specialize_same_3.alogic │ ├── split_struct_0.alogic │ ├── split_struct_1.alogic │ ├── split_struct_2.alogic │ ├── split_struct_3.alogic │ ├── sram_00.alogic │ ├── sram_01.alogic │ ├── sram_02.alogic │ ├── sram_03.alogic │ ├── sram_04.alogic │ ├── stmt_assert_0.alogic │ ├── stmt_assert_1.alogic │ ├── stmt_assert_2.alogic │ ├── stmt_assert_3.alogic │ ├── stmt_assert_4.alogic │ ├── stmt_assert_5.alogic │ ├── stmt_assert_6.alogic │ ├── stmt_assert_7.alogic │ ├── stmt_const_0.alogic │ ├── stmt_const_1.alogic │ ├── stmt_const_2.alogic │ ├── stmt_const_unsized.alogic │ ├── stmt_static_assert_0.alogic │ ├── stmt_static_assert_1.alogic │ ├── stmt_static_assert_2.alogic │ ├── stmt_static_assert_3.alogic │ ├── stmt_static_assert_4.alogic │ ├── stmt_static_assert_5.alogic │ ├── stmt_static_assert_6.alogic │ ├── stmt_static_assert_7.alogic │ ├── stmt_static_assert_8.alogic │ ├── stmt_wait_00.alogic │ ├── stmt_wait_01.alogic │ ├── stmt_wait_02.alogic │ ├── stmt_wait_03.alogic │ ├── stmt_wait_04.alogic │ ├── stmt_wait_05.alogic │ ├── stmt_wait_06.alogic │ ├── struct_in_struct_0.alogic │ ├── struct_in_struct_1.alogic │ ├── struct_index_00.alogic │ ├── struct_index_01.alogic │ ├── struct_param_0.alogic │ ├── struct_param_1.alogic │ ├── struct_param_2.alogic │ ├── struct_param_3.alogic │ ├── struct_slice_00.alogic │ ├── struct_slice_01.alogic │ ├── target_language_keyword_00.alogic │ ├── target_language_keyword_01.alogic │ ├── target_language_keyword_02.alogic │ ├── top_param_0.alogic │ ├── top_param_1.alogic │ ├── top_param_10.alogic │ ├── top_param_11.alogic │ ├── top_param_12.alogic │ ├── top_param_13.alogic │ ├── top_param_2.alogic │ ├── top_param_3.alogic │ ├── top_param_4.alogic │ ├── top_param_5.alogic │ ├── top_param_6.alogic │ ├── top_param_7.alogic │ ├── top_param_8.alogic │ ├── top_param_9.alogic │ ├── tripple_redundant_state.alogic │ ├── type_of_00.alogic │ ├── type_of_01.alogic │ ├── type_of_02.alogic │ ├── type_of_03.alogic │ ├── type_of_04.alogic │ ├── type_of_05.alogic │ ├── type_of_06.alogic │ ├── type_of_07.alogic │ ├── type_of_08.alogic │ ├── type_of_09.alogic │ ├── type_of_10.alogic │ ├── type_of_11.alogic │ ├── type_of_12.alogic │ ├── type_of_13.alogic │ ├── type_of_14.alogic │ ├── typechecker │ ├── case_default_unreachable_structural_sharing.alogic │ ├── display_gen_var.alogic │ ├── do_cond_00.alogic │ ├── for_cond_00.alogic │ ├── non_const_unsized_00.alogic │ ├── propagate_type_error_00.alogic │ ├── while_cond_00.alogic │ ├── zero_width_definition_00.alogic │ ├── zero_width_definition_01.alogic │ ├── zero_width_definition_02.alogic │ ├── zero_width_definition_03.alogic │ └── zero_width_return_00.alogic │ ├── unpacked_vector_generic.alogic │ ├── unpacked_vector_uint.alogic │ ├── unsized_case_values.alogic │ ├── unsized_const.alogic │ ├── unsized_param.alogic │ ├── unused_ctrl_func_0.alogic │ ├── unused_ctrl_func_1.alogic │ ├── unused_go.alogic │ ├── unused_signoff_00.alogic │ ├── unused_signoff_01.alogic │ ├── unused_signoff_02.alogic │ ├── unused_signoff_03.alogic │ ├── unused_signoff_04.alogic │ ├── used_elab_only_aliased_select_00.alogic │ ├── used_elab_only_aliased_select_01.alogic │ ├── using_all_bad_00.alogic │ ├── using_all_none_type_00.alogic │ ├── using_all_simple_00.alogic │ ├── using_all_simple_01.alogic │ ├── using_all_simple_02.alogic │ ├── using_all_simple_03.alogic │ ├── using_all_simple_04.alogic │ ├── using_all_simple_05.alogic │ ├── using_all_simple_06.alogic │ ├── using_one_simple_00.alogic │ ├── using_one_simple_01.alogic │ ├── using_one_simple_02.alogic │ ├── using_one_simple_03.alogic │ ├── using_one_simple_04.alogic │ ├── using_one_simple_05.alogic │ ├── using_one_simple_06.alogic │ ├── using_one_simple_07.alogic │ ├── using_one_simple_08.alogic │ ├── using_specialized_00.alogic │ ├── using_specialized_01.alogic │ ├── using_specialized_02.alogic │ ├── vector_0.alogic │ ├── vector_1.alogic │ ├── vector_2.alogic │ ├── vector_3.alogic │ ├── vector_slicing.alogic │ └── void_if_cond.alogic └── scala └── com └── argondesign └── alogic ├── AlogicTest.scala ├── CheckJson.scala ├── CompilationTest.scala ├── CompileMultiple.scala ├── CompileMultipleBase.scala ├── CompileMultipleParallel.scala ├── CompileSingle.scala ├── CompileSingleBase.scala ├── CompileSingleParallel.scala ├── ExprExtractors.scala ├── MockitoSugar.scala ├── SourceTextConverters.scala ├── UnaryTickSpec.scala ├── analysis ├── ReadSymbolBitsSpec.scala └── WrittenSymbolBitsSpec.scala ├── ast ├── ExprOpsSpec.scala ├── StatelessTreeTransformerSpec.scala └── TreeOpsSpec.scala ├── core └── TypeAssignerSpec.scala ├── frontend ├── ClarifySpec.scala ├── ElaborationSpec.scala ├── ParserLocSpec.scala ├── ParserParseAssertionSpec.scala ├── ParserParseAttrSpec.scala ├── ParserParseDescSpec.scala ├── ParserParseEntSpec.scala ├── ParserParseExprSpec.scala ├── ParserParseFromSpec.scala ├── ParserParseImportSpec.scala ├── ParserParsePkgSpec.scala ├── ParserParseRecSpec.scala ├── ParserParseStmtSpec.scala ├── ParserParseUsingSpec.scala ├── ParserSyntaxErrorSpec.scala ├── SyntaxCheckSpec.scala ├── TypeCheckerConnectSpec.scala ├── TypeCheckerExprSpec.scala ├── TypeCheckerOtherSpec.scala ├── TypeCheckerStmtSpec.scala └── UnusedCheckSpec.scala ├── gcp └── FunctionCompileSpec.scala ├── lib ├── MathSpec.scala └── MatrixSpec.scala ├── passes ├── AnalyseCallGraphSpec.scala ├── ConvertControlSpec.scala ├── DesugarSpec.scala └── PortCheckSpec.scala └── transform └── SimplifyExprSpec.scala /.gitattributes: -------------------------------------------------------------------------------- 1 | # Auto detect text files and perform LF normalization 2 | * text=auto 3 | 4 | # Custom for Visual Studio 5 | *.cs diff=csharp 6 | 7 | # Standard to msysgit 8 | *.doc diff=astextplain 9 | *.DOC diff=astextplain 10 | *.docx diff=astextplain 11 | *.DOCX diff=astextplain 12 | *.dot diff=astextplain 13 | *.DOT diff=astextplain 14 | *.pdf diff=astextplain 15 | *.PDF diff=astextplain 16 | *.rtf diff=astextplain 17 | *.RTF diff=astextplain 18 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # SBT 2 | /target 3 | /project/target 4 | /project/project/target 5 | /gen 6 | /.bsp 7 | 8 | # Antlr generated 9 | /src/main/antlr4/AlogicLexer.tokens 10 | 11 | # Testing tools 12 | /verilator 13 | /symbiyosys 14 | 15 | # Common debug output directory 16 | /tmp 17 | -------------------------------------------------------------------------------- /.sbtopts: -------------------------------------------------------------------------------- 1 | -Dsbt.supershell=false -J-Xmx2g -J-XX:+UseG1GC 2 | -------------------------------------------------------------------------------- /doc/README.md: -------------------------------------------------------------------------------- 1 | index.md -------------------------------------------------------------------------------- /doc/verilog-diffs.md: -------------------------------------------------------------------------------- 1 | # Notable differences from Verilog 2 | 3 | ### Integer literals 4 | 5 | Naked integer literals in Alogic and are unsigned. In Verilog they are signed. 6 | -------------------------------------------------------------------------------- /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.5.0-RC1 2 | -------------------------------------------------------------------------------- /project/build.sbt: -------------------------------------------------------------------------------- 1 | libraryDependencies += "com.google.cloud.functions.invoker" % "java-function-invoker" % "1.0.1" 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_dump_trees/not.alogic: -------------------------------------------------------------------------------- 1 | fsm not { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | o = ~i; 7 | fence; 8 | } 9 | } 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_dump_trees/top.alogic: -------------------------------------------------------------------------------- 1 | // @args: --dump-trees 2 | from "not" import not; 3 | 4 | network top { 5 | in bool i; 6 | out bool o; 7 | 8 | inst = new not; 9 | 10 | i -> inst.i; inst.o -> o; 11 | } 12 | // @expect-file {{{ 13 | // top.00.frontend.alogic 14 | // not.00.frontend.alogic 15 | // top.01.mark-top-levels.alogic 16 | // not.01.mark-top-levels.alogic 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_00/something_that_hopefully_does_not_exist_in_tmp.alogic: -------------------------------------------------------------------------------- 1 | network connect { 2 | in bool i; 3 | out bool o; 4 | 5 | i -> o; 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_00/top.alogic: -------------------------------------------------------------------------------- 1 | // @args: -y /tmp 2 | import "something_that_hopefully_does_not_exist_in_tmp" as p; 3 | 4 | compile p.connect; 5 | 6 | // .*/top.alogic:2: ERROR: Cannot find absolute import target "something_that_hopefully_does_not_exist_in_tmp" 7 | // .*/top.alogic:2: NOTE: Looked in: .* 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_01/something_that_hopefully_does_not_exist_in_tmp_nor_home.alogic: -------------------------------------------------------------------------------- 1 | network connect { 2 | in bool i; 3 | out bool o; 4 | 5 | i -> o; 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_01/top.alogic: -------------------------------------------------------------------------------- 1 | // @args: -y /tmp -y /home 2 | import "something_that_hopefully_does_not_exist_in_tmp_nor_home" as p; 3 | 4 | compile p.connect; 5 | 6 | // .*/top.alogic:2: ERROR: Cannot find absolute import target "something_that_hopefully_does_not_exist_in_tmp_nor_home" 7 | // .*/top.alogic:2: NOTE: Looked in: /tmp 8 | // .*/top.alogic:2: NOTE: Looked in: /home 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_02/this_is_the_correct_package.alogic: -------------------------------------------------------------------------------- 1 | network connect { 2 | in bool i; 3 | out bool o; 4 | 5 | i -> o; 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_02/top.alogic: -------------------------------------------------------------------------------- 1 | import "this_is_the_correct_package" as p; 2 | 3 | compile p.connect as top; 4 | 5 | // @fec/golden {{{ 6 | // module top( 7 | // input wire i, 8 | // output wire o 9 | // ); 10 | // assign o = i; 11 | // endmodule 12 | // }}} 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_03/top.alogic: -------------------------------------------------------------------------------- 1 | // @args: -y $TEST_DIR/ydir 2 | import "this_is_the_correct_package" as p; 3 | 4 | compile p.connect as top; 5 | 6 | // @fec/golden {{{ 7 | // module top( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/args_y_03/ydir/this_is_the_correct_package.alogic: -------------------------------------------------------------------------------- 1 | network connect { 2 | in bool i; 3 | out bool o; 4 | 5 | i -> o; 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_00/a.alogic: -------------------------------------------------------------------------------- 1 | network a { 2 | param u32 P = 64; 3 | in unknown_t i; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import a; 2 | 3 | compile a(P=64) as top; 4 | 5 | // .*/a\.alogic:3: ERROR: 'unknown_t' is undefined 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_01/top.alogic: -------------------------------------------------------------------------------- 1 | from "./types" import a_t; // Not OK 2 | 3 | typedef uint(@bits(a_t)) b_t; 4 | 5 | u5 f(b_t r) { 6 | gen for (uint i = @bits(r) - 1; i > 0; i--) { } 7 | return 0; 8 | } 9 | 10 | fsm example { 11 | void main() { 12 | fence; 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_01/types.alogic: -------------------------------------------------------------------------------- 1 | typedef i16 a_t; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_02/top.alogic: -------------------------------------------------------------------------------- 1 | from "./types" import a_t; // Not OK 2 | 3 | typedef uint(@bits(a_t)) b_t; 4 | 5 | u5 f(b_t r) { 6 | gen for (int i = 10; i > 0; i -= $signed(@bits(r))) { } 7 | return 0; 8 | } 9 | 10 | fsm example { 11 | void main() { 12 | fence; 13 | } 14 | } 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/elab_hang_02/types.alogic: -------------------------------------------------------------------------------- 1 | typedef i16 a_t; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/entity_name_collision/foo.alogic: -------------------------------------------------------------------------------- 1 | network foo { 2 | in bool i; 3 | out bool o; 4 | i -> o; 5 | } 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/entity_name_collision/top.alogic: -------------------------------------------------------------------------------- 1 | import "foo" as f; 2 | 3 | compile f.foo as foo; 4 | 5 | // @expect-file: foo__0.v 6 | // @fec/golden {{{ 7 | // module foo( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_00/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "a/b" import C; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_01/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 2; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_01/top.alogic: -------------------------------------------------------------------------------- 1 | from "a/b" import C as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + x; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd2; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_02/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_02/top.alogic: -------------------------------------------------------------------------------- 1 | from "a/b" import C as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'C' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_03/a/b.alogic: -------------------------------------------------------------------------------- 1 | gen if (true) : block { 2 | const u4 C = 1; 3 | } 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/nest_03/top.alogic: -------------------------------------------------------------------------------- 1 | from "a/b" import block.C; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_00/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import C; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_01/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 2; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_01/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import C as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + x; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd2; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_02/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 5; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_02/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import C as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'C' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_03/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_03/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | from "a" import C; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd4; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_04/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 5; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_04/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | from "a" import C as x; 6 | 7 | void main() { 8 | o = i + x; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd5; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_05/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 6; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_05/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | from "a" import C as x; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'C' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_06/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 7; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_06/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | from "a" import C; 7 | 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd7; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_07/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 8; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_07/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | from "a" import C as x; 7 | 8 | o = i + x; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd8; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_08/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 9; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_08/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | from "a" import C as x; 7 | 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'C' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_09/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 10; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_10/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 11; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_11/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 12; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_11/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | struct s { 6 | static u4 f() { 7 | from "a" import C as x; 8 | return C; 9 | } 10 | } 11 | 12 | void main() { 13 | o = i + s.f(); 14 | fence; 15 | } 16 | } 17 | 18 | // .*/top.alogic:8: ERROR: 'C' is undefined 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_12/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 13; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_12/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | gen if (true) { 6 | from "a" import C; 7 | 8 | void main() { 9 | o = i + C; 10 | fence; 11 | } 12 | } 13 | } 14 | 15 | // @fec/golden {{{ 16 | // module top( 17 | // input wire [3:0] i, 18 | // output wire [3:0] o 19 | // ); 20 | // assign o = i + 4'd13; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_13/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 14; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_13/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | gen if (true) { 6 | from "a" import C as x; 7 | 8 | void main() { 9 | o = i + x; 10 | fence; 11 | } 12 | } 13 | } 14 | 15 | // @fec/golden {{{ 16 | // module top( 17 | // input wire [3:0] i, 18 | // output wire [3:0] o 19 | // ); 20 | // assign o = i + 4'd14; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_14/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 15; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_14/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | gen if (true) { 6 | from "a" import C as x; 7 | 8 | void main() { 9 | o = i + C; 10 | fence; 11 | } 12 | } 13 | } 14 | 15 | // .*/top.alogic:9: ERROR: 'C' is undefined 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/simple_15/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import C; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | // .*/top.alogic:1: ERROR: Cannot find absolute import target "a" 13 | // .*/top.alogic:1: NOTE: Looked in: .*/from/simple_15 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_00/a.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | param uint WIDTH; 3 | uint(WIDTH) field; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import S(7) as T; 2 | 3 | network top { 4 | in T i; 5 | out T o; 6 | i -> o; 7 | } 8 | 9 | // @fec/golden {{{ 10 | // module top( 11 | // input wire [6:0] i__field, 12 | // output wire [6:0] o__field 13 | // ); 14 | // assign o__field = i__field; 15 | // endmodule 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_01/a.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | param uint WIDTH; 3 | uint(WIDTH) field; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_01/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import S(7); 2 | // :1: ERROR: 'from' requires 'as' clause 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_02/a/b.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | param uint WIDTH; 3 | uint(WIDTH) field; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/specialized_02/top.alogic: -------------------------------------------------------------------------------- 1 | from "a/b" import S(7) as T; 2 | 3 | network top { 4 | in T i; 5 | out T o; 6 | i -> o; 7 | } 8 | 9 | // @fec/golden {{{ 10 | // module top( 11 | // input wire [6:0] i__field, 12 | // output wire [6:0] o__field 13 | // ); 14 | // assign o__field = i__field; 15 | // endmodule 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_00/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_00/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import C; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:1: ERROR: No member named 'C' in value of type '.*/a.alogic' 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_01/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C as y; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_01/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 2; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_01/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import y as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + x; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:1: ERROR: No member named 'y' in value of type '.*/a.alogic' 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_02/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C; 2 | 3 | const u4 D = C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_02/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 3; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_02/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + D; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd3; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_03/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C; 2 | 3 | using C as D; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_03/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_03/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D; 2 | 3 | // .*/top.alogic:1: ERROR: No member named 'D' in value of type '.*/a.alogic' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_04/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C; 2 | 3 | gen if (true) { 4 | using C as D; 5 | } 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_04/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 5; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_04/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D; 2 | 3 | // .*/top.alogic:1: ERROR: No member named 'D' in value of type '.*/a.alogic' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_05/a.alogic: -------------------------------------------------------------------------------- 1 | from "b" import C; 2 | 3 | gen if (true) { 4 | gen if (true) { 5 | using C as D; 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_05/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 6; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_05/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D; 2 | 3 | // .*/top.alogic:1: ERROR: No member named 'D' in value of type '.*/a.alogic' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_06/a.alogic: -------------------------------------------------------------------------------- 1 | gen for (uint N < 1) { 2 | from "b" import C; 3 | using C as D#[N]; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_06/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 7; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_06/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D#[0]; 2 | 3 | // .*/top.alogic:1: ERROR: No member named 'D#\[0\]' in value of type '.*/a.alogic' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_07/a.alogic: -------------------------------------------------------------------------------- 1 | gen for (uint N < 1) { 2 | gen for (uint M < 1) { 3 | from "b" import C; 4 | using C as D#[N,M]; 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_07/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 8; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_07/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D#[0,0]; 2 | 3 | // .*/top.alogic:1: ERROR: No member named 'D#\[0,0\]' in value of type '.*/a.alogic' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_08/a.alogic: -------------------------------------------------------------------------------- 1 | gen for (uint N < 1) { 2 | from "b" import C; 3 | const u4 D#[N] = C; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_08/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 9; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_08/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D#[0]; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + D#[0]; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd9; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_09/a.alogic: -------------------------------------------------------------------------------- 1 | gen for (uint N < 1) { 2 | gen for (uint M < 1) { 3 | from "b" import C; 4 | const u4 D#[N, M] = C; 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_09/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 10; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/from/transitive_09/top.alogic: -------------------------------------------------------------------------------- 1 | from "a" import D#[0, 0]; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + D#[0, 0]; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd10; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/circular_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "top" as top; 2 | // :1: ERROR: Circular definition: imported file ".*/import/circular_00/top.alogic" 3 | // :1: NOTE: Depends on imported file ".*/import/circular_00/top.alogic" 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/circular_01/other.alogic: -------------------------------------------------------------------------------- 1 | import "top" as top; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/circular_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "other" as other; 2 | // .*/top.alogic:1: ERROR: Circular definition: imported file ".*/import/circular_01/other.alogic" 3 | // .*/other.alogic:1: NOTE: Depends on imported file ".*/import/circular_01/top.alogic" 4 | // .*/top.alogic:1: NOTE: Depends on imported file ".*/import/circular_01/other.alogic" 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_00/leaf.alogic: -------------------------------------------------------------------------------- 1 | network connect { 2 | param uint WIDTH; 3 | in uint(WIDTH) i; 4 | out uint(WIDTH) o; 5 | i -> o; 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_00/mid_a.alogic: -------------------------------------------------------------------------------- 1 | import "leaf" as leaf; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_00/mid_b.alogic: -------------------------------------------------------------------------------- 1 | import "leaf" as leaf; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_01/leaf.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_01/mid_a.alogic: -------------------------------------------------------------------------------- 1 | import "leaf" as leaf; 2 | 3 | const u4 C = leaf.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_01/mid_b.alogic: -------------------------------------------------------------------------------- 1 | import "leaf" as leaf; 2 | 3 | const u4 C = 2 * leaf.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/diamond_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "mid_a" as mid_a; 2 | import "mid_b" as mid_b; 3 | 4 | fsm top { 5 | in u4 i; 6 | out wire u4 o; 7 | 8 | void main() { 9 | o = i + mid_a.C + mid_b.C; 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module top( 16 | // input wire [3:0] i, 17 | // output wire [3:0] o 18 | // ); 19 | // assign o = i + 4'd3; 20 | // endmodule 21 | // }}} 22 | 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/line_directive/a.alogic: -------------------------------------------------------------------------------- 1 | const uint C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_00/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/b" as b; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + b.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_01/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 3; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/b" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'a' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_02/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/nest_02/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/b" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + b.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'b' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_00/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a.inc; 4 | 5 | // :3: ERROR: Parametrized package requires parameter list 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_01/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a(1).add as top; 4 | 5 | // @fec/golden {{{ 6 | // module top( 7 | // input wire [7:0] i, 8 | // output wire [7:0] o 9 | // ); 10 | // assign o = i + 8'd1; 11 | // endmodule 12 | // }}} 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_02/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_02/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a(2, 2).add as top; 4 | 5 | // :3: ERROR: Too many positional parameters 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_03/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_03/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a.add as top; 4 | 5 | // :3: ERROR: Parametrized package requires parameter list 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_04/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_04/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a(4).add as top; 4 | 5 | // @fec/golden {{{ 6 | // module top( 7 | // input wire [7:0] i, 8 | // output wire [7:0] o 9 | // ); 10 | // assign o = i + 8'd4; 11 | // endmodule 12 | // }}} 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_05/a.alogic: -------------------------------------------------------------------------------- 1 | const uint ADDEND = 5; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_05/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a(5).add as top; 4 | 5 | // :3: ERROR: Package does not take any parameters 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_06/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND = 6; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_06/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | compile a().add as top; 4 | 5 | // @fec/golden {{{ 6 | // module top( 7 | // input wire [7:0] i, 8 | // output wire [7:0] o 9 | // ); 10 | // assign o = i + 8'd6; 11 | // endmodule 12 | // }}} 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_07/a.alogic: -------------------------------------------------------------------------------- 1 | param uint ADDEND; 2 | 3 | fsm add { 4 | in u8 i; 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = i + ADDEND; 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/parametrized_07/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; // Leave un-referenced so no specializations exit 2 | 3 | network top { 4 | in bool i; 5 | out bool o; 6 | i -> o; 7 | } 8 | 9 | // @fec/golden {{{ 10 | // module top( 11 | // input wire i, 12 | // output wire o 13 | // ); 14 | // assign o = i; 15 | // endmodule 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_00/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "./a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_01/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_02/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as b; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_02/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 6; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_02/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.b.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/a.alogic:1: ERROR: Cannot find absolute import target "b" 14 | // .*/a.alogic:1: NOTE: Looked in: .*/import/relative_02 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_03/a.alogic: -------------------------------------------------------------------------------- 1 | import "./a/b" as b; 2 | 3 | const u4 C = b.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_03/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_03/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd4; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_04/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as b; 2 | 3 | const u4 C = b.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_04/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_04/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd4; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_05/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as b; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_05/a/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_05/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.b.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/a.alogic:1: ERROR: Cannot find absolute import target "b" 14 | // .*/a.alogic:1: NOTE: Looked in: .*/import/relative_05 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_06/a/a.alogic: -------------------------------------------------------------------------------- 1 | import "../b" as b; 2 | 3 | const u4 C = b.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_06/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_06/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd4; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_07/a/b/c.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 8; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_07/a/d/e.alogic: -------------------------------------------------------------------------------- 1 | import "b/c" as c; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_07/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/d/e" as e; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.d.e.c.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/a/d/e.alogic:1: ERROR: Cannot find absolute import target "b/c" 14 | // .*/a/d/e.alogic:1: NOTE: Looked in: .*/import/relative_07 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_08/a/b/c.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 8; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_08/a/d/e.alogic: -------------------------------------------------------------------------------- 1 | import "./b/c" as c; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_09/a/b/c.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 10; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_09/a/d/e.alogic: -------------------------------------------------------------------------------- 1 | import "../b/c" as c; 2 | 3 | const u4 C = c.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/relative_09/top.alogic: -------------------------------------------------------------------------------- 1 | import "a/d/e" as e; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + e.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd10; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_00/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_01/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 3; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'a' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_02/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 4; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_02/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | import "a" as a; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd4; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_03/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 6; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_03/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | import "a" as x; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'a' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_04/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 7; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_04/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | import "a" as a; 7 | 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module top( 15 | // input wire [3:0] i, 16 | // output wire [3:0] o 17 | // ); 18 | // assign o = i + 4'd7; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_05/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 9; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_05/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | import "a" as x; 7 | 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'a' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_06/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 10; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_07/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 12; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_07/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | struct s { 6 | static u4 f() { 7 | import "a" as x; 8 | return a.C; 9 | } 10 | } 11 | 12 | void main() { 13 | o = i + s.f(); 14 | fence; 15 | } 16 | } 17 | 18 | // .*/top.alogic:8: ERROR: 'a' is undefined 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_08/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 13; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_08/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | gen if (true) { 6 | import "a" as a; 7 | 8 | void main() { 9 | o = i + a.C; 10 | fence; 11 | } 12 | } 13 | } 14 | 15 | // @fec/golden {{{ 16 | // module top( 17 | // input wire [3:0] i, 18 | // output wire [3:0] o 19 | // ); 20 | // assign o = i + 4'd13; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_09/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 15; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_09/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | gen if (true) { 6 | import "a" as x; 7 | 8 | void main() { 9 | o = i + a.C; 10 | fence; 11 | } 12 | } 13 | } 14 | 15 | // .*/top.alogic:9: ERROR: 'a' is undefined 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/simple_10/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.C; 9 | fence; 10 | } 11 | } 12 | // .*/top.alogic:1: ERROR: Cannot find absolute import target "a" 13 | // .*/top.alogic:1: NOTE: Looked in: .*/import/simple_10 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_00/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as b; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_00/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.b.C; 9 | fence; 10 | } 11 | } 12 | // .*/top.alogic:8: ERROR: No member named 'b' in value of type '.*/a.alogic' 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_01/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as y; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_01/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 2; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + x.y.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: No member named 'y' in value of type '.*/a.alogic' 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_02/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as y; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_02/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_02/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + x.b.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: No member named 'b' in value of type 'package .*/a.alogic' 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_03/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as y; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_03/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_03/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as x; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.y.C; 9 | fence; 10 | } 11 | } 12 | 13 | // .*/top.alogic:8: ERROR: 'a' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_04/a.alogic: -------------------------------------------------------------------------------- 1 | import "b" as b; 2 | 3 | const u4 D = b.C; 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_04/b.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 5; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/transitive_04/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | fsm top { 4 | in u4 i; 5 | out wire u4 o; 6 | 7 | void main() { 8 | o = i + a.D; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module top( 14 | // input wire [3:0] i, 15 | // output wire [3:0] o 16 | // ); 17 | // assign o = i + 4'd5; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/unknown_file_type_00/a.notalogic: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ArgonDesign/alogic/914059911e73426fc2c3ad8cc117a221ffb7de11/src/test/resources/compile/multi/import/unknown_file_type_00/a.notalogic -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/unknown_file_type_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a.notalogic" as a; 2 | // :1: ERROR: Unable to import file .*/import/unknown_file_type_00/a.notalogic 3 | // :1: ERROR: ... unknown filename extension 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/unknown_file_type_01/a: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ArgonDesign/alogic/914059911e73426fc2c3ad8cc117a221ffb7de11/src/test/resources/compile/multi/import/unknown_file_type_01/a -------------------------------------------------------------------------------- /src/test/resources/compile/multi/import/unknown_file_type_01/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | // :1: ERROR: Unable to import file .*/import/unknown_file_type_01/a 3 | // :1: ERROR: ... unknown filename extension 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/propagate_param_value/inner.alogic: -------------------------------------------------------------------------------- 1 | from "inner_2" import *; 2 | 3 | network inner { 4 | param u10 WIDTH = 1; 5 | 6 | in uint(WIDTH) a; 7 | out uint(WIDTH) b; 8 | 9 | inst = new inner_2(WIDTH=WIDTH); 10 | 11 | a -> inst.a; 12 | inst.b -> b; 13 | } 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/propagate_param_value/inner_2.alogic: -------------------------------------------------------------------------------- 1 | fsm inner_2 { 2 | param u10 WIDTH = 1; 3 | 4 | in uint(WIDTH) a; 5 | out uint(WIDTH) b; 6 | 7 | void main() { 8 | b.write(a); 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/recursive_connect/recursive_connect.alogic: -------------------------------------------------------------------------------- 1 | network recursive_connect { 2 | param uint P; 3 | in bool i; 4 | out bool o; 5 | 6 | gen if (P > 0) { 7 | inst = new recursive_connect(P = P - 1); 8 | i -> inst.i; inst.o -> o; 9 | } else { 10 | i -> o; 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/recursive_connect/top.alogic: -------------------------------------------------------------------------------- 1 | network top { 2 | in bool i; 3 | out bool o; 4 | 5 | from "recursive_connect" import *; 6 | 7 | inst = new recursive_connect(P=10); 8 | 9 | i -> inst.i; inst.o -> o; 10 | } 11 | // @fec/golden {{{ 12 | // module top( 13 | // input wire i, 14 | // output wire o 15 | // ); 16 | // assign o = i; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/reference_to_global_in_gen/test_add.alogic: -------------------------------------------------------------------------------- 1 | fsm test_add { 2 | in u2 a; 3 | in u2 b; 4 | out wire u2 c; 5 | 6 | void main() { 7 | c.write(a.read() + b.read()); 8 | fence; 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/select_yielding_alias_to_package_member/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 11; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/select_yielding_package/a.alogic: -------------------------------------------------------------------------------- 1 | const u4 C = 1; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/select_yielding_package/top.alogic: -------------------------------------------------------------------------------- 1 | fsm top { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | struct s { 6 | import "a" as a; 7 | bool f; 8 | } 9 | 10 | s x; 11 | 12 | void main() { 13 | o = i + x.a.C; 14 | fence; 15 | } 16 | } 17 | 18 | // @fec/golden {{{ 19 | // module top( 20 | // input wire [3:0] i, 21 | // output wire [3:0] o 22 | // ); 23 | // assign o = i + 4'd1; 24 | // endmodule 25 | // }}} 26 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/target_language_keyword_00/always.alogic: -------------------------------------------------------------------------------- 1 | fsm always { 2 | in bool i; 3 | out wire bool o; 4 | void main() { 5 | o = i; 6 | fence; 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/target_language_keyword_00/top.alogic: -------------------------------------------------------------------------------- 1 | from "always" import *; 2 | 3 | network top { 4 | in bool i; 5 | out bool o; 6 | 7 | inst = new always; 8 | 9 | i -> inst.i; inst.o -> o; 10 | } 11 | // @expect-file: always_.v 12 | // @fec/golden {{{ 13 | // module top( 14 | // input wire i, 15 | // output wire o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/type_of_00/a.alogic: -------------------------------------------------------------------------------- 1 | param uint P; 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/type_of_00/top.alogic: -------------------------------------------------------------------------------- 1 | import "a" as a; 2 | 3 | network top { 4 | in a i; 5 | } 6 | 7 | // :4: ERROR: Parametrized package requires parameter list 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/unused_in_package/pkg.alogic: -------------------------------------------------------------------------------- 1 | struct a { 2 | bool f; 3 | } 4 | 5 | struct b { 6 | bool f; 7 | } 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/multi/unused_in_package/top.alogic: -------------------------------------------------------------------------------- 1 | from "pkg" import *; 2 | 3 | network top { 4 | in a i; 5 | out a o; 6 | i -> o; 7 | } 8 | 9 | // @fec/golden {{{ 10 | // module top( 11 | // input wire i__f, 12 | // output wire o__f 13 | // ); 14 | // assign o__f = i__f; 15 | // endmodule 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/access_outer_instance.alogic: -------------------------------------------------------------------------------- 1 | network access_outer_instance { 2 | in bool i; 3 | out bool o; 4 | 5 | new fsm a { 6 | out bool oo; 7 | void main() { 8 | oo = i; 9 | fence; 10 | } 11 | } 12 | 13 | new fsm b { 14 | void main() { 15 | o = a.oo; 16 | fence; 17 | } 18 | } 19 | } 20 | // :15: ERROR: Cannot access outer instance directly. 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_dump_trees.alogic: -------------------------------------------------------------------------------- 1 | // @args: --dump-trees 2 | network args_dump_trees {} 3 | // @expect-file: args_dump_trees.00.frontend.alogic 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_input_file_does_not_exist.alogic: -------------------------------------------------------------------------------- 1 | // @source-file: somethign-that-will-not-exist.alogic 2 | // ERROR: '.*/somethign-that-will-not-exist.alogic' does not exist 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_input_file_is_not_a_regular_file.alogic: -------------------------------------------------------------------------------- 1 | // @source-file: / 2 | // ERROR: '/' is not a regular file 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_profile.alogic: -------------------------------------------------------------------------------- 1 | // @args: --profile 2 | network args_profile {} 3 | // @expect-file: profile.txt 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_uninitialized_bad.alogic: -------------------------------------------------------------------------------- 1 | // @args: --uninitialized bad 2 | // ERROR: Bad arguments for option 'uninitialized': 'bad' - must be one of 'none', 'zeros', 'ones', 'random' 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_uninitialized_none.alogic: -------------------------------------------------------------------------------- 1 | // @args: --uninitialized none 2 | fsm args_uninitialized_none { 3 | out wire u2 o; 4 | 5 | void main() { 6 | u2 x; 7 | o = x; 8 | fence; 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/args_uninitialized_random.alogic: -------------------------------------------------------------------------------- 1 | // @args: --uninitialized random 2 | fsm args_uninitialized_random { 3 | out wire u1 ou1; 4 | out wire u1 oi1; 5 | out wire u2 ou2; 6 | out wire u2 oi2; 7 | 8 | void main() { 9 | u1 xu1; 10 | ou1 = xu1; 11 | i1 xi1; 12 | oi1 = xi1; 13 | u2 xu2; 14 | ou2 = xu2; 15 | i2 xi2; 16 | oi2 = xi2; 17 | fence; 18 | } 19 | } 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assert_false_0.alogic: -------------------------------------------------------------------------------- 1 | fsm assert_false_0 { 2 | void main() { 3 | assert false; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Assertion is always false 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assert_false_1.alogic: -------------------------------------------------------------------------------- 1 | fsm assert_false_1 { 2 | void main() { 3 | assert 8'h02 & 8'hf0; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Assertion is always false 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assert_false_2.alogic: -------------------------------------------------------------------------------- 1 | fsm assert_false_2 { 2 | in bool i; 3 | void main() { 4 | if (i) { 5 | assert !i; 6 | } 7 | fence; 8 | } 9 | } 10 | // :5: ERROR: Assertion is always false 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assert_false_3.alogic: -------------------------------------------------------------------------------- 1 | fsm assert_false_3 { 2 | in bool i; 3 | void main() { 4 | if (i) { 5 | } else { 6 | assert i; 7 | } 8 | fence; 9 | } 10 | } 11 | // :6: ERROR: Assertion is always false 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assert_false_4.alogic: -------------------------------------------------------------------------------- 1 | fsm assert_false_4 { 2 | void main() { 3 | assert false, "Statically known"; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Assertion is always false: Statically known 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_00.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_00 { 2 | void main() { 3 | unreachable; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: 'unreachable' statement is always reached 8 | // :4: WARNING: Statement is unreachable 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_01.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_01 { 2 | void main() { 3 | unreachable "Boom"; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: 'unreachable' statement is always reached: Boom 8 | // :4: WARNING: Statement is unreachable 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_02.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_02 { 2 | void unused() { 3 | unreachable; 4 | fence; 5 | } 6 | 7 | void main() { 8 | fence; 9 | } 10 | } 11 | // :2: WARNING: Function 'unused' is unused 12 | // :4: WARNING: Statement is unreachable 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_03.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_03 { 2 | void unused() { 3 | unreachable "Boom"; 4 | fence; 5 | } 6 | 7 | void main() { 8 | fence; 9 | } 10 | } 11 | // :2: WARNING: Function 'unused' is unused 12 | // :4: WARNING: Statement is unreachable 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_04.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_04 { 2 | void f() { 3 | unreachable; 4 | fence; 5 | } 6 | 7 | void main() { 8 | f(); 9 | } 10 | } 11 | // :3: ERROR: 'unreachable' statement is always reached 12 | // :4: WARNING: Statement is unreachable 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_05.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_05 { 2 | void f() { 3 | unreachable "Boom"; 4 | fence; 5 | } 6 | 7 | void main() { 8 | f(); 9 | } 10 | } 11 | // :3: ERROR: 'unreachable' statement is always reached: Boom 12 | // :4: WARNING: Statement is unreachable 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_06.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_06 { 2 | in bool i; 3 | void f() { 4 | if (i) { 5 | unreachable; 6 | } 7 | fence; 8 | } 9 | 10 | void main() { 11 | f(); 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_07.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_07 { 2 | in bool i; 3 | void f() { 4 | if (i) { 5 | unreachable "Boom"; 6 | } 7 | fence; 8 | } 9 | 10 | void main() { 11 | f(); 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_08.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_06 { 2 | in bool i; 3 | void f() { 4 | if (i) { 5 | unreachable; 6 | } 7 | fence; 8 | } 9 | 10 | void main() { 11 | f(); 12 | } 13 | } 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_09.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_09 { 2 | in bool i; 3 | void main() { 4 | if (~i) { 5 | unreachable; 6 | } 7 | fence; 8 | } 9 | } 10 | // @sim/test {{{ 11 | // wire i = 1'd1; 12 | // }}} 13 | // @sim/expect: TIMEOUT at 100ns 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_13.alogic: -------------------------------------------------------------------------------- 1 | fsm unreachable_13 { 2 | out wire bool o; 3 | 4 | void main() { 5 | if (true) { 6 | o = true; 7 | } else { 8 | unreachable; // Allow as comb statement 9 | } 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module unreachable_13( 16 | // output wire o 17 | // ); 18 | // assign o = 1'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_14.alogic: -------------------------------------------------------------------------------- 1 | fsm unreachable_14 { 2 | out wire bool o; 3 | 4 | void main() { 5 | if (true) { 6 | o = true; 7 | fence; 8 | } else { 9 | unreachable; // Allow as control statement 10 | } 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module unreachable_14( 16 | // output wire o 17 | // ); 18 | // assign o = 1'd1; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_17.alogic: -------------------------------------------------------------------------------- 1 | fsm unreachable_17 { 2 | out wire bool o; 3 | 4 | void main() { 5 | case (false) { 6 | true: 7 | o = true; 8 | false: 9 | gen if (true) { 10 | unreachable; // Allow as comb statement 11 | } 12 | } 13 | fence; 14 | } 15 | } 16 | // :10: ERROR: 'unreachable' statement is always reached 17 | // :13: WARNING: Statement is unreachable 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_18.alogic: -------------------------------------------------------------------------------- 1 | fsm unreachable_18 { 2 | out wire bool o; 3 | 4 | void main() { 5 | case (false) { 6 | true: 7 | { 8 | o = true; 9 | fence; 10 | } 11 | false: 12 | gen if (true) { 13 | unreachable; // Allow as control statement 14 | } 15 | } 16 | } 17 | } 18 | 19 | // :13: ERROR: 'unreachable' statement is always reached 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_19.alogic: -------------------------------------------------------------------------------- 1 | fsm unreachable_19 { 2 | out wire bool o; 3 | 4 | void main() { 5 | if (true) { 6 | o = true; 7 | fence; 8 | } else { 9 | { 10 | unreachable; // Allow as ctrl statement 11 | } 12 | } 13 | } 14 | } 15 | 16 | // @fec/golden {{{ 17 | // module unreachable_19( 18 | // output wire o 19 | // ); 20 | // assign o = 1'd1; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assertions/stmt_unreachable_22.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_unreachable_22 { 2 | void main() { 3 | u2 baz = 2; 4 | case (baz) { 5 | 0: baz = 0; 6 | default: unreachable; 7 | } 8 | fence; 9 | } 10 | } 11 | // :6: ERROR: 'unreachable' statement is always reached 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_05.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_05 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | assert i; 8 | o = i; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module assume_05( 14 | // input wire [1:0] i, 15 | // output wire [1:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_06.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_06 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | assert i == 0; 8 | o = i; 9 | fence; 10 | } 11 | } 12 | // @verilator-lint-off 13 | // @fec/golden {{{ 14 | // module assume_06( 15 | // input wire [1:0] i, 16 | // output wire [1:0] o 17 | // ); 18 | // assign o = 2'd0; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_07.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_07 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | assert i != 2'd2; 8 | o = i; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module assume_07( 14 | // input wire [1:0] i, 15 | // output wire [1:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_08.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_08 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | assert i == 2'd2; 8 | o = i; 9 | fence; 10 | } 11 | } 12 | // @verilator-lint-off 13 | // @fec/golden {{{ 14 | // module assume_08( 15 | // input wire [1:0] i, 16 | // output wire [1:0] o 17 | // ); 18 | // assign o = 2'd2; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_09.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_09 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | u2 tmp = i; 8 | assert tmp == 0; 9 | o = i; 10 | fence; 11 | } 12 | } 13 | // @verilator-lint-off 14 | // @fec/golden {{{ 15 | // module assume_09( 16 | // input wire [1:0] i, 17 | // output wire [1:0] o 18 | // ); 19 | // assign o = 2'd0; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/assume_10.alogic: -------------------------------------------------------------------------------- 1 | // @args: --no-assertions 2 | fsm assume_10 { 3 | in u2 i; 4 | out wire u2 o; 5 | 6 | void main() { 7 | u2 tmp = i; 8 | assert tmp; 9 | o = i; 10 | fence; 11 | } 12 | } 13 | // @fec/golden {{{ 14 | // module assume_10( 15 | // input wire [1:0] i, 16 | // output wire [1:0] o 17 | // ); 18 | // assign o = i; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/attributes/bad_liftsrams.alogic: -------------------------------------------------------------------------------- 1 | (* liftsrams = true *) 2 | network bad_liftsrams {} 3 | // :1: ERROR: 'liftsrams' attribute is a boolean flag 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/attributes/bad_reclimit.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_reclimit { 2 | (* reclimit *) 3 | void main() { 4 | fence; 5 | } 6 | } 7 | // :2: ERROR: 'reclimit' attribute must be an expression 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/attributes/bad_stacklimit.alogic: -------------------------------------------------------------------------------- 1 | (* stacklimit *) 2 | fsm bad_reclimit { 3 | void main() { 4 | fence; 5 | } 6 | } 7 | // :1: ERROR: 'stacklimit' attribute must be an expression 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/attributes/bad_unknown.alogic: -------------------------------------------------------------------------------- 1 | (* unknownAttribute *) 2 | network bad_unknown {} 3 | // :1: ERROR: Unknown attribute 'unknownAttribute' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_00.alogic: -------------------------------------------------------------------------------- 1 | gen if (true) { 2 | fence; 3 | } 4 | // :2: ERROR: Package content expected 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_01.alogic: -------------------------------------------------------------------------------- 1 | gen if (true) { 2 | gen for (uint n < 20) : block { 3 | fence; 4 | } 5 | } 6 | // :3: ERROR: Package content expected 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_02.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_gen_02 { 2 | gen if (true) { 3 | fence; 4 | } 5 | } 6 | // :3: ERROR: Entity content expected 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_03.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_gen_03 { 2 | gen if (true) { 3 | gen for (uint n < 20) { 4 | fence; 5 | } 6 | } 7 | } 8 | // :4: ERROR: Entity content expected 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_04.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | gen if (true) { 3 | fence; 4 | } 5 | } 6 | // :3: ERROR: Record content expected 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_05.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | gen for (uint n < 10) { 3 | gen if (true) { 4 | fence; 5 | } 6 | } 7 | } 8 | // :4: ERROR: Record content expected 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_06.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | void foo() { 3 | gen if (true) { 4 | compile S; 5 | } 6 | } 7 | } 8 | // :4: ERROR: Statement expected 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_07.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | void foo() { 3 | gen for (uint n < 20) { 4 | gen if (true) { 5 | 1 -> n; 6 | } 7 | } 8 | } 9 | } 10 | // :5: ERROR: Statement expected 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_08.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | void f() { 3 | case (5'd10) { 4 | gen if (true) { 5 | fence; 6 | } 7 | } 8 | } 9 | } 10 | // :5: ERROR: Case clause expected 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_09.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | void f() { 3 | case (5'd10) { 4 | gen for (uint n < 20) { 5 | gen if (true) { 6 | 1 -> n; 7 | } 8 | } 9 | } 10 | } 11 | } 12 | // :6: ERROR: Case clause expected 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_10.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_gen_10 { 2 | gen for (uint n < 2) { 3 | fence {} 4 | } 5 | } 6 | 7 | // :3: ERROR: Multiple fence blocks specified in entity 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_gen_11.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_gen_11 { 2 | void main () { 3 | case (1'd0) { 4 | gen for (uint n < 2) { 5 | default: {} 6 | } 7 | } 8 | fence; 9 | } 10 | } 11 | // :5: ERROR: Multiple 'default' clauses specified in case statement 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_00.alogic: -------------------------------------------------------------------------------- 1 | static void f() {} 2 | // :1: ERROR: No 'static' modifier is allowed here 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_01.alogic: -------------------------------------------------------------------------------- 1 | gen if (false) { 2 | static void f() {} 3 | } 4 | // :2: ERROR: No 'static' modifier is allowed here 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_02.alogic: -------------------------------------------------------------------------------- 1 | fsm a { 2 | static void f() {} 3 | } 4 | // :2: ERROR: No 'static' modifier is allowed here 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_03.alogic: -------------------------------------------------------------------------------- 1 | fsm a { 2 | gen if (false) { 3 | static void f() {} 4 | } 5 | } 6 | // :3: ERROR: No 'static' modifier is allowed here 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_04.alogic: -------------------------------------------------------------------------------- 1 | void a() { 2 | static void f() {} 3 | } 4 | // :2: ERROR: No 'static' modifier is allowed here 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_05.alogic: -------------------------------------------------------------------------------- 1 | void a() { 2 | gen if (false) { 3 | static void f() {} 4 | } 5 | } 6 | // :3: ERROR: No 'static' modifier is allowed here 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_06.alogic: -------------------------------------------------------------------------------- 1 | fsm a { 2 | void main() { 3 | static void f() {} 4 | } 5 | } 6 | // :3: ERROR: No 'static' modifier is allowed here 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_static_function_definition_07.alogic: -------------------------------------------------------------------------------- 1 | fsm a { 2 | void main() { 3 | gen if (false) { 4 | static void f() {} 5 | } 6 | } 7 | } 8 | // :4: ERROR: No 'static' modifier is allowed here 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_unsized_type_01.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_unsized_type_01 { 2 | static uint a; 3 | } 4 | // :2: ERROR: Static variable cannot have an unsized integer type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_unsized_type_02.alogic: -------------------------------------------------------------------------------- 1 | network bad_unsized_type_02 { 2 | pipeline uint a; 3 | } 4 | // :2: ERROR: Pipeline variable cannot have an unsized integer type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_void_type_01.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_void_type_01 { 2 | const void a = 0; 3 | } 4 | // :2: ERROR: Constant cannot have a 'void' type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_void_type_02.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_void_type_02 { 2 | param void a = 0; 3 | } 4 | 5 | compile bad_void_type_02() as top; 6 | 7 | // :2: ERROR: Parameter cannot have a 'void' type 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_void_type_03.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_void_type_03 { 2 | static void a; 3 | } 4 | // :2: ERROR: Static variable cannot have a 'void' type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_void_type_04.alogic: -------------------------------------------------------------------------------- 1 | network bad_void_type_04 { 2 | pipeline void a; 3 | } 4 | // :2: ERROR: Pipeline variable cannot have a 'void' type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bad_void_type_05.alogic: -------------------------------------------------------------------------------- 1 | fsm bad_void_type_05 { 2 | void main () { 3 | const void a = 0; 4 | } 5 | } 6 | // :3: ERROR: Constant cannot have a 'void' type 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/badly_unresolvable_name.alogic: -------------------------------------------------------------------------------- 1 | fsm badly_unresolvable_name { 2 | // To evalauate 'badly_unresolvable_name' we need it's type, but here we 3 | // can't even compute that because the type of the entity depends on its 4 | // contents, which we are computing right now.. 5 | out bool N = M#[badly_unresolvable_name]; 6 | } 7 | // :5: ERROR: identifier is undefined 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/bind/bound_entity_with_outputs.alogic: -------------------------------------------------------------------------------- 1 | fsm bound { 2 | out wire bool o; 3 | 4 | void main () { 5 | o = 0; 6 | fence; 7 | } 8 | } 9 | 10 | network bound_entity_with_outputs { 11 | out wire bool o; 12 | 13 | inst = bind bound; 14 | } 15 | 16 | compile bound_entity_with_outputs; 17 | 18 | // :13: ERROR: Entity instantiated with 'bind' cannot have any outputs 19 | // :2: NOTE: Output is defined here 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/cardinal_ports_0.alogic: -------------------------------------------------------------------------------- 1 | network cardinal_ports_0 { 2 | in bool; 3 | out bool; 4 | 5 | in -> out; 6 | } 7 | // @fec/golden {{{ 8 | // module cardinal_ports_0( 9 | // input wire in_, 10 | // output wire out_ 11 | // ); 12 | // 13 | // assign out_ = in_; 14 | // 15 | // endmodule 16 | // }}} 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/cardinal_ports_1.alogic: -------------------------------------------------------------------------------- 1 | network cardinal_ports_1 { 2 | in bool; 3 | out bool; 4 | 5 | new network inner { 6 | in bool; 7 | out bool; 8 | 9 | in -> out; 10 | } 11 | 12 | in -> inner.in; inner.out -> out; 13 | } 14 | // @fec/golden {{{ 15 | // module cardinal_ports_1( 16 | // input wire in_, 17 | // output wire out_ 18 | // ); 19 | // 20 | // assign out_ = in_; 21 | // 22 | // endmodule 23 | // }}} 24 | 25 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/cardinal_ports_2.alogic: -------------------------------------------------------------------------------- 1 | network cardinal_ports_2 { 2 | in bool; 3 | out bool; 4 | 5 | new network inner { 6 | in -> out; 7 | } 8 | } 9 | // @fec/golden {{{ 10 | // module cardinal_ports_2( 11 | // input wire in_, 12 | // output wire out_ 13 | // ); 14 | // 15 | // assign out_ = in_; 16 | // 17 | // endmodule 18 | // }}} 19 | 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_0.alogic: -------------------------------------------------------------------------------- 1 | fsm circular_definition_0 { 2 | uint(@bits(b)) a; 3 | uint(@bits(c)) b; 4 | uint(@bits(a)) c; 5 | } 6 | // :2: ERROR: Circular definition: type of symbol 'a' 7 | // :2: NOTE: Depends on type of symbol 'b' 8 | // :3: NOTE: Depends on type of symbol 'c' 9 | // :4: NOTE: Depends on type of symbol 'a' 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_1.alogic: -------------------------------------------------------------------------------- 1 | fsm circular_definition_1 { 2 | const uint x = @bits(a); 3 | uint(@bits(b)) a; 4 | uint(@bits(c)) b; 5 | uint(x) c; 6 | } 7 | // :2: ERROR: Circular definition: value of symbol 'x' 8 | // :2: NOTE: Depends on type of symbol 'a' 9 | // :3: NOTE: Depends on type of symbol 'b' 10 | // :4: NOTE: Depends on type of symbol 'c' 11 | // :5: NOTE: Depends on value of symbol 'x' 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_3.alogic: -------------------------------------------------------------------------------- 1 | network circular_definition_3 { 2 | same = new circular_definition_3; 3 | } 4 | // :1: ERROR: Circular definition: type of symbol 'circular_definition_3' 5 | // :2: NOTE: Depends on type of symbol 'same' 6 | // :2: NOTE: Depends on type of symbol 'circular_definition_3' 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_4.alogic: -------------------------------------------------------------------------------- 1 | // @ignore 2 | fsm circular_definition_4 { 3 | struct s { 4 | uint(@bits(this)) x; 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_5.alogic: -------------------------------------------------------------------------------- 1 | network circular_definition_5 { 2 | const u32 x = x < 1 ? 1 : x; 3 | } 4 | // :2: ERROR: Circular definition: value of symbol 'x' 5 | // :2: NOTE: Depends on value of symbol 'x' 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/circular_definition_6.alogic: -------------------------------------------------------------------------------- 1 | fsm circular_definition_6 { 2 | uint(C) a; 3 | const uint C = D; 4 | const uint D = @bits(a); 5 | } 6 | // :4: ERROR: Circular definition: value of symbol 'D' 7 | // :4: NOTE: Depends on type of symbol 'a' 8 | // :2: NOTE: Depends on value of symbol 'C' 9 | // :3: NOTE: Depends on value of symbol 'D' 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/comb_func/nested_in_ctrl_func_00.alogic: -------------------------------------------------------------------------------- 1 | fsm nested_in_ctrl_func_00 { 2 | in u2 i; 3 | out wire u2 o; 4 | 5 | void main() { 6 | u2 inv(u2 x) { 7 | return ~x; 8 | } 9 | o = inv(i); 10 | fence; 11 | } 12 | } 13 | // @fec/golden {{{ 14 | // module nested_in_ctrl_func_00( 15 | // input wire [1:0] i, 16 | // output wire [1:0] o 17 | // ); 18 | // assign o = ~i; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/comb_func/simple_00.alogic: -------------------------------------------------------------------------------- 1 | u2 inc(u2 x) { 2 | return x + 1; 3 | } 4 | 5 | fsm simple_00 { 6 | in u2 i; 7 | out wire u2 o; 8 | 9 | void main() { 10 | o = inc(i); 11 | fence; 12 | } 13 | } 14 | // @fec/golden {{{ 15 | // module simple_00( 16 | // input wire [1:0] i, 17 | // output wire [1:0] o 18 | // ); 19 | // assign o = i + 2'd1; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/comb_func/simple_02.alogic: -------------------------------------------------------------------------------- 1 | u4 inc(u4 x) { 2 | return x + 1; 3 | } 4 | 5 | fsm simple_02 { 6 | in u4 i; 7 | out wire u4 o; 8 | 9 | void main() { 10 | o = inc(inc(i)); 11 | fence; 12 | } 13 | } 14 | // @fec/golden {{{ 15 | // module simple_02( 16 | // input wire [3:0] i, 17 | // output wire [3:0] o 18 | // ); 19 | // assign o = i + 4'd2; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/comb_func/simple_03.alogic: -------------------------------------------------------------------------------- 1 | u4 inc(u4 x) { 2 | return x + 1; 3 | } 4 | 5 | fsm simple_03 { 6 | in u4 i; 7 | out wire u4 o; 8 | 9 | void main() { 10 | o = inc(inc(inc(i)) + inc(inc(inc(i)))); 11 | fence; 12 | } 13 | } 14 | // @fec/golden {{{ 15 | // module simple_03( 16 | // input wire [3:0] i, 17 | // output wire [3:0] o 18 | // ); 19 | // assign o = 2*i + 4'd6; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/compile_specialized_00.alogic: -------------------------------------------------------------------------------- 1 | network compile_specialized_00 { 2 | param uint WIDTH; 3 | 4 | in uint(WIDTH) i; 5 | out uint(WIDTH) o; 6 | 7 | i -> o; 8 | } 9 | 10 | compile compile_specialized_00(8) as top; 11 | 12 | // @fec/golden {{{ 13 | // module top( 14 | // input wire [7:0] i, 15 | // output wire [7:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/compile_specialized_01.alogic: -------------------------------------------------------------------------------- 1 | network compile_specialized_00 { 2 | param uint WIDTH; 3 | 4 | in uint(WIDTH) i; 5 | out uint(WIDTH) o; 6 | 7 | i -> o; 8 | } 9 | 10 | compile compile_specialized_00(8); 11 | 12 | // :10: ERROR: 'compile' requires 'as' clause 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/compile_wrapper_00.alogic: -------------------------------------------------------------------------------- 1 | network compile_wrapper_00 { 2 | // These names clash with the wrapper generated instance name 3 | in bool inst; 4 | out bool inst_; 5 | inst -> inst_; 6 | } 7 | 8 | compile compile_wrapper_00 as top; 9 | 10 | // @fec/golden {{{ 11 | // module top( 12 | // input wire inst, 13 | // output wire inst_ 14 | // ); 15 | // assign inst_ = inst; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/const_bad_00.alogic: -------------------------------------------------------------------------------- 1 | network const_bad_00 { 2 | in bool i; 3 | const bool a = i; 4 | } 5 | // :3: ERROR: Initializer of 'const' definition must be a compile time constant 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/const_vector_rep.alogic: -------------------------------------------------------------------------------- 1 | const bool[1] A = true; 2 | const bool[2] LUT = {2{A}}; 3 | 4 | fsm const_vector_rep { 5 | in bool i; 6 | out wire bool o; 7 | 8 | void main() { 9 | o = LUT[i]; 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module const_vector_rep( 16 | // input wire i, 17 | // output wire o 18 | // ); 19 | // assign o = 1'd1; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ctrl_func_static_03.alogic: -------------------------------------------------------------------------------- 1 | fsm ctrl_func_static_03 { 2 | in u8 i; 3 | 4 | void main() { 5 | static u8 x = i; 6 | fence; 7 | } 8 | } 9 | // :5: ERROR: Initializer of 'static' variable definition must be a compile time constant 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/def_ent_0.alogic: -------------------------------------------------------------------------------- 1 | fsm def_ent_0 { 2 | typedef u6 data_t; 3 | 4 | in data_t i; 5 | out wire data_t o; 6 | 7 | void main() { 8 | o = i; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module def_ent_0( 14 | // input wire [5:0] i, 15 | // output wire [5:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/def_ent_2.alogic: -------------------------------------------------------------------------------- 1 | compile def_ent_2() as top; 2 | fsm def_ent_2 { 3 | param uint W = 6; 4 | 5 | typedef uint(W) data_t; 6 | 7 | in data_t i; 8 | out wire data_t o; 9 | 10 | void main() { 11 | o = i; 12 | fence; 13 | } 14 | } 15 | // @fec/golden {{{ 16 | // module top( 17 | // input wire [5:0] i, 18 | // output wire [5:0] o 19 | // ); 20 | // assign o = i; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/defer/display_00.alogic: -------------------------------------------------------------------------------- 1 | fsm display_00 { 2 | in bool i; 3 | 4 | void main() { 5 | wait i; 6 | @display("Will not print this"); 7 | fence; 8 | } 9 | } 10 | 11 | // @sim/test {{{ 12 | // wire i = 1'b0; 13 | // wire _unused = &{1'd0, clk, rst}; 14 | // }}} 15 | // 16 | // @sim/expect: TIMEOUT at 100ns 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/defer/finish_00.alogic: -------------------------------------------------------------------------------- 1 | fsm finish_00 { 2 | in bool i; 3 | 4 | void main() { 5 | wait i; 6 | @finish(); 7 | fence; 8 | } 9 | } 10 | 11 | // @sim/test {{{ 12 | // wire i = 1'b0; 13 | // wire _unused = &{1'd0, clk, rst}; 14 | // }}} 15 | // 16 | // @sim/expect: TIMEOUT at 100ns 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_0.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_0 { 2 | in bool i#[0]; 3 | out bool o#[0]; 4 | i#[0] -> o#[0]; 5 | } 6 | // @fec/golden {{{ 7 | // module dictident_decl_0( 8 | // input wire i__0, 9 | // output wire o__0 10 | // ); 11 | // assign o__0 = i__0; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_10.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_10 { 2 | gen for (uint N < 2) { 3 | in bool i#[N]; 4 | out bool o#[2*N]; 5 | i#[N] -> o#[2*N]; 6 | } 7 | } 8 | // @fec/golden {{{ 9 | // module dictident_decl_10( 10 | // input wire i__0, 11 | // input wire i__1, 12 | // output wire o__0, 13 | // output wire o__2 14 | // ); 15 | // assign o__0 = i__0; 16 | // assign o__2 = i__1; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_13.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_13 { 2 | gen for (uint N < 2) { 3 | in bool i#[N, 0]; 4 | out bool o#[N]; 5 | i#[N] -> o#[N, 0]; 6 | } 7 | } 8 | // :5: ERROR: 'i#\[0\]' is undefined 9 | // :5: ERROR: 'i#\[1\]' is undefined 10 | // :5: ERROR: 'o#\[0,0\]' is undefined 11 | // :5: ERROR: 'o#\[1,0\]' is undefined 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_15.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_15 { 2 | gen for (uint N < 0) { 3 | in bool i#[N]; 4 | out bool o#[N]; 5 | } 6 | i#[0] -> o#[0]; 7 | } 8 | // :6: ERROR: 'i#\[0\]' is undefined 9 | // :6: ERROR: 'o#\[0\]' is undefined 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_16.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_16 { 2 | gen for (uint N < 0) { 3 | in bool i#[N]; 4 | out bool o#[N]; 5 | } 6 | i#[0] -> o#[0]; 7 | } 8 | // :6: ERROR: 'i#\[0\]' is undefined 9 | // :6: ERROR: 'o#\[0\]' is undefined 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_18.alogic: -------------------------------------------------------------------------------- 1 | // @verilator-lint-off 2 | network dictident_decl_18 { 3 | gen for (uint N < 3) { 4 | in bool i#[N]; 5 | out bool o#[N]; 6 | } 7 | i#[0] -> o#[0]; 8 | i#[1] -> o#[1]; 9 | } 10 | // :4: WARNING: Input port 'i#\[2\]' is unused 11 | // :5: WARNING: Output port 'o#\[2\]' is unused 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_2.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_2 { 2 | gen for (uint N < 2) { 3 | in bool i#[N]; 4 | out bool o#[N]; 5 | i#[N] -> o#[N]; 6 | } 7 | } 8 | // @fec/golden {{{ 9 | // module dictident_decl_2( 10 | // input wire i__0, 11 | // input wire i__1, 12 | // output wire o__0, 13 | // output wire o__1 14 | // ); 15 | // assign o__0 = i__0; 16 | // assign o__1 = i__1; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_6.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_6 { 2 | in u8 x; 3 | gen for (uint N < 2) { 4 | in bool i#[x]; 5 | out bool o#[x]; 6 | } 7 | i#[0] -> o#[0]; 8 | } 9 | // :4: ERROR: Identifier index must be a compile time constant 10 | // :5: ERROR: Identifier index must be a compile time constant 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_7.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_7 { 2 | in u8 x; 3 | gen for (uint N < 2) { 4 | in bool i#[N]; 5 | out bool o#[N]; 6 | } 7 | i#[x] -> o#[0]; 8 | i#[1] -> o#[x]; 9 | } 10 | // :7: ERROR: Identifier index must be a compile time constant 11 | // :8: ERROR: Identifier index must be a compile time constant 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_decl_8.alogic: -------------------------------------------------------------------------------- 1 | network dictident_decl_8 { 2 | gen for (uint N < 2) { 3 | in bool i#[0]; 4 | out bool o#[0]; 5 | } 6 | i#[0] -> o#[0]; 7 | } 8 | // :3: ERROR: 'i#\[0\]' has multiple definitions 9 | // :4: ERROR: 'o#\[0\]' has multiple definitions 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_defn_0.alogic: -------------------------------------------------------------------------------- 1 | network dictident_defn_0 { 2 | typedef bool i_t#[0]; 3 | typedef bool o_t#[0]; 4 | in i_t#[0] i; 5 | out o_t#[0] o; 6 | i -> o; 7 | } 8 | // @fec/golden {{{ 9 | // module dictident_defn_0( 10 | // input wire i, 11 | // output wire o 12 | // ); 13 | // assign o = i; 14 | // endmodule 15 | // }}} 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_defn_7.alogic: -------------------------------------------------------------------------------- 1 | network dictident_defn_7 { 2 | in u8 x; 3 | gen for (uint N < 2) { 4 | typedef uint(N+1) i_t#[N]; 5 | typedef uint(N+1) o_t#[N]; 6 | } 7 | in i_t#[x] i_0; 8 | out o_t#[x] o_0; 9 | i_0 -> o_0; 10 | } 11 | // :7: ERROR: Identifier index must be a compile time constant 12 | // :8: ERROR: Identifier index must be a compile time constant 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_defn_8.alogic: -------------------------------------------------------------------------------- 1 | network dictident_defn_8 { 2 | gen for (uint N < 2) { 3 | typedef uint(N+1) i_t#[0]; 4 | typedef uint(N+1) o_t#[0]; 5 | } 6 | in i_t#[0] i_0; 7 | out o_t#[0] o_0; 8 | i_0 -> o_0; 9 | } 10 | // :3: ERROR: 'i_t#\[0\]' has multiple definitions 11 | // :4: ERROR: 'o_t#\[0\]' has multiple definitions 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_entity_0.alogic: -------------------------------------------------------------------------------- 1 | network dictident_entity_0#[0] { 2 | in bool i; 3 | out bool o; 4 | i -> o; 5 | } 6 | // @fec/golden {{{ 7 | // module dictident_entity_0__0( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | // @manifest/top-levels|dictident_entity_0__0|source-name: "dictident_entity_0#[0]" 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/dictident_function_2.alogic: -------------------------------------------------------------------------------- 1 | fsm dictident_function_2 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | gen for (uint N < 1) { 6 | void func#[N]() { 7 | o = i; 8 | } 9 | } 10 | 11 | void main() { 12 | func#[0](); 13 | func#[1](); 14 | } 15 | } 16 | // :13: ERROR: 'func#\[1\]' is undefined 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/double_typedef.alogic: -------------------------------------------------------------------------------- 1 | typedef bool a; 2 | typedef a b; 3 | typedef a c; 4 | 5 | network double_typedef { 6 | in b i; 7 | out c o; 8 | i -> o; 9 | } 10 | 11 | // @fec/golden {{{ 12 | // module double_typedef( 13 | // input wire i, 14 | // output wire o 15 | // ); 16 | // 17 | // assign o = i; 18 | // 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elab_hang_00.alogic: -------------------------------------------------------------------------------- 1 | network inner { 2 | param uint Q; 3 | rf = new undefined(R=Q); 4 | } 5 | 6 | network top { 7 | const uint P = 16; 8 | inst = new inner(P); 9 | } 10 | 11 | compile top; 12 | 13 | // :3: ERROR: 'undefined' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_00.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_00 { 2 | in u1 i; 3 | out u1 o; 4 | i -> o; 5 | } 6 | // @fec/golden {{{ 7 | // module elaborate_00( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_01.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_01 { 2 | in u1 i; 3 | i -> o; 4 | out u1 o; 5 | } 6 | // @fec/golden {{{ 7 | // module elaborate_01( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_02.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_02 { 2 | i -> o; 3 | in u1 i; 4 | out u1 o; 5 | } 6 | // @fec/golden {{{ 7 | // module elaborate_02( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_03.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_03 { 2 | in uint(@bits(o)) i; 3 | out u1 o; 4 | i -> o; 5 | } 6 | // @fec/golden {{{ 7 | // module elaborate_03( 8 | // input wire i, 9 | // output wire o 10 | // ); 11 | // assign o = i; 12 | // endmodule 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_04.alogic: -------------------------------------------------------------------------------- 1 | fsm elaborate_04 { 2 | const u6[2] bits = {6'd1, 6'd2}; 3 | const uint num_bits = bits[0]; 4 | const uint(num_bits) bar = 3; 5 | } 6 | // :3: ERROR: Unsized integer declaration has packed initializer 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_05.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_05 { 2 | param u5[2] stage_bits = 5'd13; 3 | out int(stage_bits[0]) p_in; 4 | } 5 | 6 | compile elaborate_05() as top; 7 | 8 | // :2: ERROR: Parameter value yields 5 bits, a 10 bit value is expected 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_07.alogic: -------------------------------------------------------------------------------- 1 | network elaborate_07 { 2 | const uint V = 1; 3 | 4 | gen for (uint y = 0 ; y < 1; y += V) {} 5 | } 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/elaborate_08.alogic: -------------------------------------------------------------------------------- 1 | fsm elaborate_08 { 2 | struct s { 3 | u8 a; 4 | u4 b; 5 | } 6 | 7 | const s STRUCT = {8'd5, 4'd4}; 8 | 9 | out wire uint(STRUCT.a) o; 10 | 11 | void main() { 12 | o = 'STRUCT.b; 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module elaborate_08( 18 | // output wire [4:0] o 19 | // ); 20 | // assign o = 5'd4; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/empty.alogic: -------------------------------------------------------------------------------- 1 | network empty {} 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/empty_fsm.alogic: -------------------------------------------------------------------------------- 1 | fsm empty_fsm {} 2 | // :1: ERROR: No 'main' function in fsm. 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/empty_main_with_out_sync.alogic: -------------------------------------------------------------------------------- 1 | fsm empty_main_with_out_sync { 2 | out sync u1 o; 3 | void main() { 4 | fence; 5 | } 6 | } 7 | // @verilator-lint-off 8 | // :2: WARNING: Output port 'o' is unused 9 | 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_0 { 2 | static assert @bits(u8) == 8; 3 | } 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_1 { 2 | static assert @bits(u8) == @bits(i8); 3 | } 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_2.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_2 { 2 | static assert @bits(u8) == 9; 3 | } 4 | // :2: ERROR: Static assertion failure 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_3.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_3 { 2 | static assert @bits(u8) == 9, "u8 is not 9 bits"; 3 | } 4 | // :2: ERROR: Static assertion failure: u8 is not 9 bits 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_4.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_4 { 2 | in u32 i; 3 | static assert i; 4 | } 5 | // :3: ERROR: Condition of static assertion must be a compile time constant 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_5.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_5 { 2 | static assert 2'd0 + 3'd0; 3 | } 4 | // :2: ERROR: Both operands of binary '\+' must have the same width, but 5 | // :2: ERROR: ... left hand operand is 2 bits wide, and 6 | // :2: ERROR: ... right hand operand is 3 bits wide 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_6.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_6 { 2 | const uint P = 2; 3 | static assert P % 2 == 0, "P must be even"; 4 | } 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_7.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_7 { 2 | const uint P = 3; 3 | static assert P % 2 == 0, "P must be even"; 4 | } 5 | // :3: ERROR: Static assertion failure: P must be even 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ent_static_assert_8.alogic: -------------------------------------------------------------------------------- 1 | network ent_static_assert_8 { 2 | static assert @bits; 3 | } 4 | // :2: ERROR: Condition of 'static assert' is of neither numeric nor packed type 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/external_const_00.alogic: -------------------------------------------------------------------------------- 1 | const bool[2] C = {false, true}; 2 | 3 | fsm external_const_00 { 4 | in bool i; 5 | out wire bool o; 6 | 7 | void main() { 8 | o = C[i]; 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module external_const_00( 15 | // input wire i, 16 | // output wire o 17 | // ); 18 | // assign o = ~i; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/extract_assignments_00.alogic: -------------------------------------------------------------------------------- 1 | fsm extract_assignments_00 { 2 | out wire bool o; 3 | 4 | void main() { 5 | o = true; 6 | fence; 7 | } 8 | } 9 | 10 | // @fec/golden {{{ 11 | // module extract_assignments_00( 12 | // output wire o 13 | // ); 14 | // assign o = 1'd1; 15 | // endmodule 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/fence_only_fsm.alogic: -------------------------------------------------------------------------------- 1 | fsm fence_only_fsm { 2 | in bool i; 3 | out bool o; 4 | fence { 5 | o = i; 6 | } 7 | } 8 | // :1: ERROR: No 'main' function in fsm. 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/folding_before_lower_vectors.alogic: -------------------------------------------------------------------------------- 1 | fsm folding_before_lower_vectors { 2 | const u8[2] VECTOR = {8'd5, 8'd4}; 3 | const u8 VECTOR_ITEM = VECTOR[1]; 4 | 5 | out wire u8 o; 6 | 7 | void main() { 8 | o = VECTOR_ITEM; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module folding_before_lower_vectors( 14 | // output wire [7:0] o 15 | // ); 16 | // assign o = 8'd5; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_dict_index_type_error_0.alogic: -------------------------------------------------------------------------------- 1 | network gen_dict_index_type_error_0 { 2 | gen for (u8 n < 1) { 3 | in bool i#[n + 10'd0]; 4 | } 5 | } 6 | // :3: ERROR: Both operands of binary '\+' must have the same width, but 7 | // :3: ERROR: ... left hand operand is 8 bits wide, and 8 | // :3: ERROR: ... right hand operand is 10 bits wide 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_dict_index_type_error_1.alogic: -------------------------------------------------------------------------------- 1 | network gen_dict_index_type_error_1 { 2 | gen for (u8 n < 1) { 3 | in bool i#[n]; 4 | } 5 | out bool o; 6 | i#[8'd0 + 10'd0] -> o; 7 | } 8 | // :6: ERROR: Both operands of binary '\+' must have the same width, but 9 | // :6: ERROR: ... left hand operand is 8 bits wide, and 10 | // :6: ERROR: ... right hand operand is 10 bits wide 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_empty_ctrl_else.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_empty_ctrl_else { 2 | in bool i; 3 | 4 | void main() { 5 | if (i) { 6 | fence; 7 | } else { 8 | gen if (false) { // Generate producing empty else in control 'if' 9 | fence; 10 | } 11 | } 12 | } 13 | } 14 | // :5: ERROR: Either both or neither branches of 'if' statement must be control statements 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_ent_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | network gen_ent_static_assert_0 { 2 | gen if (false) { 3 | static assert false; 4 | } 5 | } 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_ent_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | network gen_ent_static_assert_1 { 2 | gen if (true) { 3 | static assert false; 4 | } 5 | } 6 | // :3: ERROR: Static assertion failure 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_00.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_00 { 2 | in u8 i; 3 | gen for (u8 n = i ; n < 10 ; n++) { 4 | } 5 | } 6 | // :3: ERROR: 'gen' variable initializer must be a compile time constant 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_01.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_01 { 2 | gen for (u8 n = 0 ; bool ; n++) { 3 | } 4 | } 5 | // :2: ERROR: Condition of 'gen for' is of non-packed type, a 1 bit value is expected 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_02.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_02 { 2 | gen for (u8 n = 0 ; 0 ; n++) { 3 | } 4 | } 5 | // :2: ERROR: Condition of 'gen for' yields an unsized value, a 1 bit value is expected 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_03.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_03 { 2 | gen for (u8 n = 0 ; n ; n++) { 3 | } 4 | } 5 | // :2: ERROR: Condition of 'gen for' yields 8 bits, a 1 bit value is expected 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_04.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_04 { 2 | in u8 i; 3 | gen for (u8 n = 0 ; n < i ; n++) { 4 | } 5 | } 6 | // :3: ERROR: 'gen' loop condition must be a compile time constant 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_05.alogic: -------------------------------------------------------------------------------- 1 | network gen_for_bad_05 { 2 | in u8 i; 3 | gen for (u8 n = 0 ; n < 10 ; {n, n} += {2{i}}) { 4 | } 5 | } 6 | // :3: ERROR: Cannot statically evaluate step statements 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_bad_06.alogic: -------------------------------------------------------------------------------- 1 | // @ignore 2 | network gen_for_bad_06 { 3 | in u8 i; 4 | gen for (u8 n = 0 ; n < 10 ; n += 2 - 3) { 5 | } 6 | } 7 | // :3: ERROR: Result of operator '-' is unsigned, but value is negative: -1 8 | // :3: ERROR: Cannot statically evaluate step statements 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_infinite_0.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_for_infinite_0 { 2 | in bool p_i; 3 | out bool p_o; 4 | 5 | void main() { 6 | bool b = p_i; 7 | gen for (uint N = 0; N < 2; N = N == 0 ? 1 : 0) { 8 | b = ~b; 9 | } 10 | p_o.write(b); 11 | fence; 12 | } 13 | } 14 | // :7: ERROR: 'gen for' exceeds 1024 iterations. Possibly an infinite loop, 15 | // :7: ERROR: ... otherwise set --gen-loop-limit to more than 1024 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_infinite_2.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_for_infinite_2 { 2 | in bool p_i; 3 | out bool p_o; 4 | 5 | void main() { 6 | bool b = p_i; 7 | gen for (uint N = 0; N % 2 == 0; N += 2) { 8 | b = ~b; 9 | } 10 | p_o.write(b); 11 | fence; 12 | } 13 | } 14 | // :7: ERROR: 'gen for' exceeds 1024 iterations. Possibly an infinite loop, 15 | // :7: ERROR: ... otherwise set --gen-loop-limit to more than 1024 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_named_01.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_for_named_01 { 2 | in u4 i; 3 | out wire u4 o_0; 4 | out wire u4 o_1; 5 | 6 | void main() { 7 | gen for (uint n = 0 ; n < 2 ; n++) : block { 8 | u4 b#[n] = i + n; 9 | } 10 | o_0 = b#[0]; 11 | o_1 = b#[1]; 12 | fence; 13 | } 14 | } 15 | // :10: ERROR: 'b#\[0\]' is undefined 16 | // :11: ERROR: 'b#\[1\]' is undefined 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_named_05.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_for_named_05 { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | gen for (uint n = 0 ; n < 2 ; n++) { 7 | u4 b = i + n; 8 | } 9 | o = b; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: 'b' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_for_scope_2.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_for_scope_2 { 2 | in bool i; 3 | out bool o; 4 | 5 | void main() { 6 | gen for (uint N = 0 ; N < 8; N++) { 7 | bool c = ~i; 8 | } 9 | o = c; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: 'c' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_bad_0.alogic: -------------------------------------------------------------------------------- 1 | network gen_if_bad_0 { 2 | const uint N = 1; 3 | gen if (N + 2) {} 4 | } 5 | // :3: ERROR: Condition of 'gen if' yields an unsized value, a 1 bit value is expected 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_bad_1.alogic: -------------------------------------------------------------------------------- 1 | network gen_if_bad_1 { 2 | gen if (2'd0) {} 3 | } 4 | // :2: ERROR: Condition of 'gen if' yields 2 bits, a 1 bit value is expected 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_bad_2.alogic: -------------------------------------------------------------------------------- 1 | network gen_if_bad_2 { 2 | gen if (bool) {} 3 | } 4 | // :2: ERROR: Condition of 'gen if' is of non-packed type, a 1 bit value is expected 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_bad_3.alogic: -------------------------------------------------------------------------------- 1 | network gen_if_bad_3 { 2 | gen if (i#[3'd0 + 2'd0]) {} 3 | } 4 | // :2: ERROR: Both operands of binary '\+' must have the same width, but 5 | // :2: ERROR: ... left hand operand is 3 bits wide, and 6 | // :2: ERROR: ... right hand operand is 2 bits wide 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_bad_4.alogic: -------------------------------------------------------------------------------- 1 | network gen_if_bad_4 { 2 | gen if (1) { 3 | } else if (@zx(1, 1'd1)) { 4 | } else if (N) { 5 | } 6 | } 7 | // :4: ERROR: 'N' is undefined 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_named_00.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_if_named_00 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | gen if (true) : block { 7 | bool x = ~i; 8 | } 9 | o = block.x; 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module gen_if_named_00( 16 | // input wire i, 17 | // output wire o 18 | // ); 19 | // assign o = ~i; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_named_01.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_if_named_01 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | gen if (false) : block {} else { 7 | bool x = i; 8 | } 9 | o = block.x; 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module gen_if_named_01( 16 | // input wire i, 17 | // output wire o 18 | // ); 19 | // assign o = i; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_if_named_03.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_if_named_03 { 2 | in u2 i; 3 | out wire u2 o; 4 | 5 | void main() { 6 | gen if (false) : block { 7 | u2 x = i + 1; 8 | } else if (true) { 9 | u2 x = i + 2; 10 | } else { 11 | u2 x = i + 3; 12 | } 13 | o = x; 14 | fence; 15 | } 16 | } 17 | // :13: ERROR: 'x' is undefined 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_bad_00.alogic: -------------------------------------------------------------------------------- 1 | network gen_range_bad_00 { 2 | in u8 i; 3 | gen for (u8 n < i) { 4 | } 5 | } 6 | // :3: ERROR: 'gen' loop end value must be a compile time constant 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_bad_01.alogic: -------------------------------------------------------------------------------- 1 | network gen_range_bad_01 { 2 | gen for (u8 n <= 256) { 3 | } 4 | } 5 | // :2: ERROR: End value 256 is out of range for variable 'n' with type 'u8' 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_bad_02.alogic: -------------------------------------------------------------------------------- 1 | network gen_range_bad_02 { 2 | gen for (u8 n < 257) { 3 | } 4 | } 5 | // :2: ERROR: End value 256 is out of range for variable 'n' with type 'u8' 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_bad_03.alogic: -------------------------------------------------------------------------------- 1 | network gen_range_bad_03 { 2 | gen for (i8 n <= 128) { 3 | } 4 | } 5 | // :2: ERROR: End value 128 is out of range for variable 'n' with type 'i8' 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_named_01.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_range_named_01 { 2 | in u4 i; 3 | out wire u4 o_0; 4 | out wire u4 o_1; 5 | 6 | void main() { 7 | gen for (uint n < 2) : block { 8 | u4 b#[n] = i + n; 9 | } 10 | o_0 = b#[0]; 11 | o_1 = b#[1]; 12 | fence; 13 | } 14 | } 15 | // :10: ERROR: 'b#\[0\]' is undefined 16 | // :11: ERROR: 'b#\[1\]' is undefined 17 | 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_named_05.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_range_named_05 { 2 | in u4 i; 3 | out wire u4 o; 4 | 5 | void main() { 6 | gen for (uint n < 2) { 7 | u4 b = i + n; 8 | } 9 | o = b; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: 'b' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_scope_1.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_range_scope_1 { 2 | in bool i; 3 | out bool o; 4 | 5 | void main() { 6 | gen for (uint N < 8) { 7 | bool c = ~i; 8 | } 9 | o = c; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: 'c' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_range_signed_00.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_range_signed_00 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | void main() { 6 | gen for (i4 n < 8) { 7 | o[n[2:0]] = ~i[n[2:0]]; 8 | } 9 | fence; 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module gen_range_signed_00( 15 | // input wire [7:0] i, 16 | // output wire [7:0] o 17 | // ); 18 | // assign o = ~i; 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_rec_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | gen if (false) { 3 | static assert false; 4 | } 5 | bool x; 6 | } 7 | 8 | network gen_rec_static_assert_0 { 9 | out t o; 10 | 1'd0 -> o; 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_rec_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | gen if (true) { 3 | static assert false; 4 | } 5 | bool x; 6 | } 7 | 8 | network gen_rec_static_assert_1 { 9 | out t o; 10 | 1'd0 -> o; 11 | } 12 | // :3: ERROR: Static assertion failure 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | network gen_static_assert_0 { 2 | gen if (true) { 3 | out u8 o; 4 | } else { 5 | out u7 o; 6 | } 7 | static assert @bits(o) == 8; 8 | 8'd0 -> o; 9 | } 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | network gen_static_assert_1 { 2 | gen if (false) { 3 | out u8 o; 4 | } else { 5 | out u7 o; 6 | } 7 | static assert @bits(o) == 8; 8 | 7'd0 -> o; 9 | } 10 | // :7: ERROR: Static assertion failure 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_static_assert_3.alogic: -------------------------------------------------------------------------------- 1 | network gen_static_assert_3 { 2 | gen if (true) { 3 | out u8 o; 4 | } else { 5 | out u7 o; 6 | } 7 | 8 | new fsm inner { 9 | static assert @bits(o) == 8; 10 | void main() { 11 | o = 8'd0; 12 | fence; 13 | } 14 | } 15 | } 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_static_assert_4.alogic: -------------------------------------------------------------------------------- 1 | network gen_static_assert_4 { 2 | gen if (false) { 3 | out u8 o; 4 | } else { 5 | out u7 o; 6 | } 7 | 8 | new fsm inner { 9 | static assert @bits(o) == 8; 10 | void main() { 11 | o = 8'd0; 12 | fence; 13 | } 14 | } 15 | } 16 | // :9: ERROR: Static assertion failure 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_stmt_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_stmt_static_assert_0 { 2 | void main() { 3 | gen if (false) { 4 | static assert false; 5 | } 6 | fence; 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/gen_stmt_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | fsm gen_stmt_static_assert_1 { 2 | void main() { 3 | gen if (true) { 4 | static assert false; 5 | } 6 | fence; 7 | } 8 | } 9 | // :4: ERROR: Static assertion failure 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/if_then_else_redef_0.alogic: -------------------------------------------------------------------------------- 1 | fsm if_then_else_redef_0 { 2 | void main() { 3 | if (false) { 4 | u8 a; 5 | } else { 6 | i7 a; 7 | } 8 | fence; 9 | } 10 | } 11 | // :4: WARNING: Variable 'a' is unused 12 | // :6: WARNING: Variable 'a' is unused 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/if_then_else_redef_1.alogic: -------------------------------------------------------------------------------- 1 | fsm if_then_else_redef_1 { 2 | void main() { 3 | if (false) 4 | u8 a; 5 | else 6 | i7 a; 7 | fence; 8 | } 9 | } 10 | // :4: WARNING: Variable 'a' is unused 11 | // :6: WARNING: Variable 'a' is unused 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/import_bad_00.alogic: -------------------------------------------------------------------------------- 1 | import "/a" as a; 2 | 3 | // :1: ERROR: Import path cannot start with a leading '/' 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/import_bad_01.alogic: -------------------------------------------------------------------------------- 1 | import "" as a; 2 | 3 | // :1: ERROR: Empty import path 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/inline_known_port_00.alogic: -------------------------------------------------------------------------------- 1 | fsm inline_known_port_00 { 2 | in bool i; 3 | out wire bool o; 4 | void main() { 5 | o = false; 6 | if (i) { 7 | o = i.read(); 8 | } 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module inline_known_port_00( 14 | // input wire i, 15 | // output wire o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/inline_known_vars_01.alogic: -------------------------------------------------------------------------------- 1 | fsm inline_known_vars_01 { 2 | out wire u1 o; 3 | 4 | void main() { 5 | i8 a; 6 | a = 8'd4; // Needs to preserve signedness 7 | o = -a < 8'sd3; 8 | fence; 9 | } 10 | } 11 | // @fec/golden {{{ 12 | // module inline_known_vars_01( 13 | // output wire o 14 | // ); 15 | // assign o = 1'd1; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/int_attribute.alogic: -------------------------------------------------------------------------------- 1 | // Signed unsized integer attribute. 2 | // Hits a code coverage line in Elaborate.scala. 3 | (* reclimit = 1s *) 4 | fsm int_attribute { 5 | void main() { 6 | main(); 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_00.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_00 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[3:0] -> o; 6 | i[4] -> o[0]; 7 | } 8 | // :3: ERROR: Bits 0 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_01.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_01 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[0] -> o[0], o[0]; 6 | } 7 | // :3: ERROR: Bits 0 of 'o' have multiple drivers 8 | // :5: NOTE: The 1st driver is here 9 | // :5: NOTE: The 2nd driver is here 10 | // :3: ERROR: Bits 3:1 of 'o' are undriven 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_02.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_02 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[2:0] -> o[2:0], o[3:1]; 6 | } 7 | // :3: ERROR: Bits 2:1 of 'o' have multiple drivers 8 | // :5: NOTE: The 1st driver is here 9 | // :5: NOTE: The 2nd driver is here 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_03.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_03 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[1:0] -> o[1:0], o[2:1]; 6 | } 7 | // :3: ERROR: Bits 1 of 'o' have multiple drivers 8 | // :5: NOTE: The 1st driver is here 9 | // :5: NOTE: The 2nd driver is here 10 | // :3: ERROR: Bits 3 of 'o' are undriven 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_04.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_04 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[1:0] -> o[1:0]; 6 | i[2] -> o[1]; 7 | } 8 | // :3: ERROR: Bits 1 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :3: ERROR: Bits 3:2 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_05.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_05 { 2 | in u8 i; 3 | out u2[2] o; 4 | 5 | i[1:0] -> o[0]; 6 | i[3:2] -> o[0]; 7 | } 8 | // :3: ERROR: Bits 1:0 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :3: ERROR: Bits 3:2 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_06.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_06 { 2 | in u8 i; 3 | out u2[2] o; 4 | 5 | i[0] -> o[0][0]; 6 | i[1] -> o[0][0]; 7 | } 8 | // :3: ERROR: Bits 0 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :3: ERROR: Bits 3:1 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_07.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_07 { 2 | in u8 i; 3 | out u2[2] o; 4 | 5 | i[0] -> o[0][0]; 6 | i[1:0] -> o[0][1:0]; 7 | } 8 | // :3: ERROR: Bits 0 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :3: ERROR: Bits 3:2 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_08.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_08 { 2 | in u8 i; 3 | out u2[2] o; 4 | 5 | i[1:0] -> o[0]; 6 | i[1] -> o[0][0]; 7 | } 8 | // :3: ERROR: Bits 0 of 'o' have multiple drivers 9 | // :5: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :3: ERROR: Bits 3:2 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_09.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_09 { 2 | struct ss { 3 | u2 z; 4 | } 5 | struct s { 6 | u2[2] x; 7 | ss y; 8 | } 9 | in u8 i; 10 | out s o; 11 | 12 | i[2+:4] -> o.x; 13 | i[0+:6] -> o; 14 | } 15 | // :10: ERROR: Bits 3:0 of 'o__x' have multiple drivers 16 | // :12: NOTE: The 1st driver is here 17 | // :13: NOTE: The 2nd driver is here 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_10.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_10 { 2 | struct ss { 3 | u2 z; 4 | } 5 | struct s { 6 | u2[2] x; 7 | ss y; 8 | } 9 | in u8 i; 10 | out s o; 11 | 12 | i[0+:2] -> o.y.z; 13 | i[2+:2] -> o.y; 14 | } 15 | // :10: ERROR: Bits 1:0 of 'o__y__z' have multiple drivers 16 | // :12: NOTE: The 1st driver is here 17 | // :13: NOTE: The 2nd driver is here 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_14.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_14 { 2 | const uint A = 1; 3 | in u8 i; 4 | out u2[2] o; 5 | 6 | i[0] -> o[1][0], o[A][0]; 7 | } 8 | // :4: ERROR: Bits 2 of 'o' have multiple drivers 9 | // :6: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :4: ERROR: Bits 3, 1:0 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_15.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_15 { 2 | const uint A = 1; 3 | in u8 i; 4 | out u2[2] o; 5 | 6 | i[0] -> o[0][1], o[0][A]; 7 | } 8 | // :4: ERROR: Bits 1 of 'o' have multiple drivers 9 | // :6: NOTE: The 1st driver is here 10 | // :6: NOTE: The 2nd driver is here 11 | // :4: ERROR: Bits 3:2, 0 of 'o' are undriven 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_16.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_16 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[0] -> o[0]; 6 | i[1] -> o[1]; 7 | i[2] -> o[1]; 8 | } 9 | // :3: ERROR: Bits 1 of 'o' have multiple drivers 10 | // :6: NOTE: The 1st driver is here 11 | // :7: NOTE: The 2nd driver is here 12 | // :3: ERROR: Bits 3:2 of 'o' are undriven 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/interconnect_check_17.alogic: -------------------------------------------------------------------------------- 1 | network interconnect_check_17 { 2 | in u8 i; 3 | out u8 o; 4 | 5 | i[0] -> o[1]; 6 | i[1] -> o[4]; 7 | } 8 | // :3: ERROR: Bits 7:5, 3:2, 0 of 'o' are undriven 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/lift_entities_0.alogic: -------------------------------------------------------------------------------- 1 | network lift_entities_0 { 2 | in bool i; 3 | out bool o; 4 | 5 | new network inner { 6 | i -> o; 7 | } 8 | } 9 | 10 | // @fec/golden {{{ 11 | // module lift_entities_0( 12 | // input wire i, 13 | // output wire o 14 | // ); 15 | // 16 | // assign o = i; 17 | // 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/lift_entities_1.alogic: -------------------------------------------------------------------------------- 1 | network lift_entities_1 { 2 | in bool i; 3 | out bool o; 4 | 5 | new network inner_a { 6 | new network inner_b { 7 | i -> o; 8 | } 9 | } 10 | } 11 | 12 | // @fec/golden {{{ 13 | // module lift_entities_1( 14 | // input wire i, 15 | // output wire o 16 | // ); 17 | // 18 | // assign o = i; 19 | // 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/lift_entities_2.alogic: -------------------------------------------------------------------------------- 1 | network lift_entities_2 { 2 | out wire u8 o; 3 | const u8 C = 8'd35; 4 | 5 | new fsm inner { 6 | void main() { 7 | o = C; 8 | fence; 9 | } 10 | } 11 | } 12 | 13 | // @fec/golden {{{ 14 | // module lift_entities_2( 15 | // output wire [7:0] o 16 | // ); 17 | // 18 | // assign o = 8'd35; 19 | // 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/lift_entities_3.alogic: -------------------------------------------------------------------------------- 1 | network lift_entities_3 { 2 | out wire u8 o; 3 | const u8 C = 8'd35; 4 | const u8 D = C; 5 | 6 | new fsm inner { 7 | void main() { 8 | o = D; 9 | fence; 10 | } 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module lift_entities_3( 16 | // output wire [7:0] o 17 | // ); 18 | // 19 | // assign o = 8'd35; 20 | // 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/line_directive_bad_00.alogic: -------------------------------------------------------------------------------- 1 | #line 2 | // :1: ERROR: '#line' requires a positive decimal integer as first argument 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/line_directive_bad_01.alogic: -------------------------------------------------------------------------------- 1 | 2 | #line 0x2 3 | // :2: ERROR: '#line' requires a positive decimal integer as first argument 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/line_directive_bad_02.alogic: -------------------------------------------------------------------------------- 1 | 2 | #line 10 not_string_literal 3 | // :2: ERROR: Second argument to '#line' must be a string literal 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/line_directive_bad_03.alogic: -------------------------------------------------------------------------------- 1 | 2 | 3 | #line 10 "a" "b" 4 | // :3: ERROR: Extraneous arguments to '#line' 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/lower_flow_control_2.alogic: -------------------------------------------------------------------------------- 1 | fsm lower_flow_control_2 { 2 | in sync void i; 3 | out sync wire void o; 4 | 5 | void main() { 6 | i.read(); 7 | o.write(); 8 | fence; 9 | } 10 | } 11 | 12 | // @fec/golden {{{ 13 | // module lower_flow_control_2( 14 | // input wire i__valid, 15 | // output wire o__valid 16 | // ); 17 | // 18 | // assign o__valid = i__valid; 19 | // 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_bad_01.alogic: -------------------------------------------------------------------------------- 1 | fsm method_bad_01 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | struct s { 6 | static bool inv(bool x) { 7 | if (x) { 8 | return false; 9 | } 10 | } 11 | } 12 | 13 | void main() { 14 | o = s.inv(i); 15 | fence; 16 | } 17 | } 18 | // :7: ERROR: Control reaches end of non-void function 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_bad_02.alogic: -------------------------------------------------------------------------------- 1 | fsm method_bad_02 { 2 | out wire bool o; 3 | 4 | struct s { 5 | static bool f() { 6 | // Empty 7 | } 8 | } 9 | 10 | void main() { 11 | o = s.f(); 12 | fence; 13 | } 14 | } 15 | // :5: ERROR: Control reaches end of non-void function 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_bad_03.alogic: -------------------------------------------------------------------------------- 1 | fsm method_bad_03 { 2 | out wire bool o; 3 | 4 | struct s { 5 | bool a; 6 | static bool get() { 7 | return a; 8 | } 9 | } 10 | 11 | void main() { 12 | o = s.get(); 13 | fence; 14 | } 15 | } 16 | // :7: ERROR: Static method cannot reference non-static members 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_empty.alogic: -------------------------------------------------------------------------------- 1 | struct s { 2 | void empty() {} 3 | bool f; 4 | } 5 | 6 | fsm method_empty { 7 | void main () { 8 | s x; 9 | x.empty(); 10 | fence; 11 | } 12 | } 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_00.alogic: -------------------------------------------------------------------------------- 1 | struct s { 2 | static bool inv(bool x) { 3 | return ~x; 4 | } 5 | } 6 | 7 | fsm method_pure_00 { 8 | in bool i; 9 | out wire bool o; 10 | 11 | void main() { 12 | o = s.inv(i); 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module method_pure_00( 18 | // input wire i, 19 | // output wire o 20 | // ); 21 | // assign o = ~i; 22 | // endmodule 23 | // }}} 24 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_01.alogic: -------------------------------------------------------------------------------- 1 | fsm method_pure_01 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | struct s { 6 | static bool inv(bool x) { 7 | return ~x; 8 | } 9 | } 10 | 11 | void main() { 12 | o = s.inv(i); 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module method_pure_01( 18 | // input wire i, 19 | // output wire o 20 | // ); 21 | // assign o = ~i; 22 | // endmodule 23 | // }}} 24 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_04.alogic: -------------------------------------------------------------------------------- 1 | fsm method_pure_04 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | struct s { 6 | static bool inv(bool x) { 7 | return ~x; 8 | } 9 | } 10 | 11 | void main() { 12 | o = s.inv(s.inv(i)); 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module method_pure_04( 18 | // input wire i, 19 | // output wire o 20 | // ); 21 | // assign o = i; 22 | // endmodule 23 | // }}} 24 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_08.alogic: -------------------------------------------------------------------------------- 1 | fsm method_pure_08 { 2 | out wire u2 o; 3 | 4 | struct s { 5 | static u2 add(u2 x, u2 y) { 6 | return x + y; 7 | } 8 | } 9 | 10 | void main() { 11 | o = s.add(2, 1); 12 | fence; 13 | } 14 | } 15 | // @fec/golden {{{ 16 | // module method_pure_08( 17 | // output wire [1:0] o 18 | // ); 19 | // assign o = 2'd3; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_10.alogic: -------------------------------------------------------------------------------- 1 | fsm method_pure_10 { 2 | out wire u8 o; 3 | 4 | struct s { 5 | static u8 f() { 6 | return 20; 7 | } 8 | } 9 | 10 | void main() { 11 | o = s.f(); 12 | fence; 13 | } 14 | } 15 | // @fec/golden {{{ 16 | // module method_pure_10( 17 | // output wire [7:0] o 18 | // ); 19 | // assign o = 8'd20; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_pure_11.alogic: -------------------------------------------------------------------------------- 1 | fsm method_pure_11 { 2 | in u2 i; 3 | out wire u4 o; 4 | 5 | struct s { 6 | static u4 f(u2 x) { 7 | return 'x; 8 | } 9 | } 10 | 11 | void main() { 12 | o = s.f(i); 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module method_pure_11( 18 | // input wire [1:0] i, 19 | // output wire [3:0] o 20 | // ); 21 | // assign o = {2'd0, i}; 22 | // endmodule 23 | // }}} 24 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_recursive_3.alogic: -------------------------------------------------------------------------------- 1 | fsm method_recursive_3 { 2 | struct s { 3 | static void f() { 4 | f(); 5 | } 6 | } 7 | 8 | void main() { 9 | s.f(); 10 | fence; 11 | } 12 | } 13 | // :4: ERROR: Combinational function call exceeds static recursion limit of 16 14 | // :4: ERROR: ... this can be increased with the '--comb-rec-limit' option 15 | // :4: ERROR: ... root call is at: .*method_recursive_3.alogic:9 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/method_static_2.alogic: -------------------------------------------------------------------------------- 1 | fsm method_static_2 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | struct s { 6 | static void f(bool x) { 7 | o = x; 8 | } 9 | } 10 | 11 | void main() { 12 | s.f(i); 13 | fence; 14 | } 15 | } 16 | // @fec/golden {{{ 17 | // module method_static_2( 18 | // input wire i, 19 | // output wire o 20 | // ); 21 | // 22 | // assign o = i; 23 | // 24 | // endmodule 25 | // }}} 26 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/mixed_param_assign.alogic: -------------------------------------------------------------------------------- 1 | network mixed_param_assign { 2 | struct s_t { 3 | param uint W; 4 | param uint V; 5 | uint(W + V) a; 6 | } 7 | 8 | in s_t(1, V=1) i; 9 | out s_t(1, V=1) o; 10 | i -> o; 11 | } 12 | // :8: ERROR: Mixing positional and named parameter assignments is not allowed 13 | // :9: ERROR: Mixing positional and named parameter assignments is not allowed 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/multiple_main_fsm.alogic: -------------------------------------------------------------------------------- 1 | fsm multiple_main_fsm { 2 | in u2 i; 3 | out u2 o; 4 | gen for (uint n < 2) { 5 | void main() { 6 | o[n] = i[n]; 7 | fence; 8 | } 9 | } 10 | } 11 | // :1: ERROR: Multiple 'main' functions in fsm at: 12 | // :1: ERROR: ... .*/multiple_main_fsm.alogic:5 13 | // :1: ERROR: ... .*/multiple_main_fsm.alogic:5 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/name_shadowing_00.alogic: -------------------------------------------------------------------------------- 1 | network name_shadowing_00 { 2 | out u2 o; 3 | 4 | fsm inner { 5 | param bool P; 6 | 7 | out wire bool o; 8 | 9 | void main() { 10 | o.write(P); 11 | fence; 12 | } 13 | } 14 | 15 | inst = new inner(false); 16 | 17 | inst.o -> o[0]; 18 | 1'b1 -> o[1]; 19 | } 20 | 21 | compile name_shadowing_00; 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/name_shadowing_01.alogic: -------------------------------------------------------------------------------- 1 | network name_shadowing_01 { 2 | out u2 o#[0]; 3 | 4 | fsm inner { 5 | param bool P; 6 | 7 | out wire bool o#[0]; 8 | 9 | void main() { 10 | o#[0].write(P); 11 | fence; 12 | } 13 | } 14 | 15 | inst = new inner(false); 16 | 17 | inst.o#[0] -> o#[0][0]; 18 | 1'b1 -> o#[0][1]; 19 | } 20 | 21 | compile name_shadowing_01; 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/no_such_param_00.alogic: -------------------------------------------------------------------------------- 1 | network no_such_param_00 { 2 | network inner { 3 | param uint A; 4 | param uint B; 5 | } 6 | inst = new inner(A=1, B=2, C=3); 7 | } 8 | // :6: ERROR: 'inner' has no parameter 'C' 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/no_such_param_01.alogic: -------------------------------------------------------------------------------- 1 | network no_such_param_01 { 2 | network inner { 3 | param uint A; 4 | param uint B; 5 | } 6 | inst = new inner(A=1, B=2, C#[0]=3); 7 | } 8 | // :6: ERROR: 'inner' has no parameter 'C#\[0\]' 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/no_such_param_02.alogic: -------------------------------------------------------------------------------- 1 | network no_such_param_02 { 2 | network inner { 3 | gen for (uint n < 2) { 4 | param uint A#[2*n]; 5 | } 6 | } 7 | inst = new inner(A#[0]=0, A#[1]=1, A#[2]=2, A#[3]=3); 8 | } 9 | // :7: ERROR: 'inner' has no parameter 'A#\[1\]' 10 | // :7: ERROR: 'inner' has no parameter 'A#\[3\]' 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/no_target.alogic: -------------------------------------------------------------------------------- 1 | // :1: ERROR: Input file 'no_target.alogic' does not contain any entity definitions nor 'compile' directives 2 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/output_name_max_length_2.alogic: -------------------------------------------------------------------------------- 1 | // @args: --output-name-max-length 16 2 | network output_name_max_length_2 { 3 | out wire u8 o; 4 | 5 | new fsm inner { 6 | void main() { o = 0; fence; } 7 | } 8 | } 9 | // @expect-file: _h3ceaa72efd28a1.v 10 | // @fec/golden {{{ 11 | // module output_name_max_length_2( 12 | // output wire [7:0] o 13 | // ); 14 | // 15 | // assign o = 0; 16 | // 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_00.alogic: -------------------------------------------------------------------------------- 1 | param uint WIDTH; 2 | 3 | network package_params_00 { 4 | in uint(WIDTH) i; 5 | out uint(WIDTH) o; 6 | 7 | i -> o; 8 | } 9 | 10 | // command-line:1: ERROR: 'WIDTH' requires actual parameter value 11 | // :1: NOTE: 'WIDTH' is defined here 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_01.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P 2 2 | 3 | param uint WIDTH; 4 | 5 | network package_params_01 { 6 | in uint(WIDTH) i; 7 | out uint(WIDTH) o; 8 | 9 | i -> o; 10 | } 11 | 12 | // @fec/golden {{{ 13 | // module package_params_01( 14 | // input wire [1:0] i, 15 | // output wire [1:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_02.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P WIDTH=3 2 | 3 | param uint WIDTH; 4 | 5 | network package_params_02 { 6 | in uint(WIDTH) i; 7 | out uint(WIDTH) o; 8 | 9 | i -> o; 10 | } 11 | 12 | // @fec/golden {{{ 13 | // module package_params_02( 14 | // input wire [2:0] i, 15 | // output wire [2:0] o 16 | // ); 17 | // assign o = i; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_03.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P X=2 -P WIDTH=2 2 | 3 | param uint WIDTH; 4 | 5 | network package_params_03 { 6 | in uint(WIDTH) i; 7 | out uint(WIDTH) o; 8 | 9 | i -> o; 10 | } 11 | 12 | // command-line:1: ERROR: '.*/package_params_03\.alogic' has no parameter 'X' 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_04.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P 2 -P 2 2 | 3 | param uint WIDTH; 4 | 5 | network package_params_04 { 6 | in uint(WIDTH) i; 7 | out uint(WIDTH) o; 8 | 9 | i -> o; 10 | } 11 | 12 | // command-line:1: ERROR: Too many positional parameters 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_05.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P fsm 2 | 3 | param uint WIDTH; 4 | 5 | network package_params_05 { 6 | in uint(WIDTH) i; 7 | out uint(WIDTH) o; 8 | 9 | i -> o; 10 | } 11 | 12 | // command-line:1: ERROR: Syntax error: mismatched input 'fsm' expecting.* 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_06.alogic: -------------------------------------------------------------------------------- 1 | param uint WIDTH = 6; 2 | 3 | network package_params_06 { 4 | in uint(WIDTH) i; 5 | out uint(WIDTH) o; 6 | 7 | i -> o; 8 | } 9 | 10 | // @fec/golden {{{ 11 | // module package_params_06( 12 | // input wire [5:0] i, 13 | // output wire [5:0] o 14 | // ); 15 | // assign o = i; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_07.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P 2 2 | // command-line:1: ERROR: Package defined in input file '.*/package_params_07\.alogic' does not take any parameters. 3 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_08.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P 2 -P FOO=2 2 | // command-line:1: ERROR: Package defined in input file '.*/package_params_08\.alogic' does not take any parameters. 3 | // command-line:1: ERROR: Package defined in input file '.*/package_params_08\.alogic' does not take any parameters. 4 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_09.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P foo 2 | 3 | const uint foo = 1; 4 | 5 | param uint WIDTH; 6 | 7 | network package_params_10 { 8 | in uint(WIDTH) i; 9 | out uint(WIDTH) o; 10 | 11 | i -> o; 12 | } 13 | 14 | // command-line:1: ERROR: 'foo' is undefined 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/package_params_10.alogic: -------------------------------------------------------------------------------- 1 | // @args: -P foo -P @zx(2,1'd1) 2 | 3 | const uint foo = 1; 4 | 5 | param uint WIDTH; 6 | 7 | network package_params_11 { 8 | in uint(WIDTH) i; 9 | out uint(WIDTH) o; 10 | 11 | i -> o; 12 | } 13 | 14 | // command-line:1: ERROR: 'foo' is undefined 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_assignment_required_2.alogic: -------------------------------------------------------------------------------- 1 | network param_assignment_required_2 { 2 | out u9 o; 3 | 4 | network t { 5 | param uint W = 0; 6 | } 7 | 8 | t -> o; 9 | } 10 | // :8: ERROR: Parametrized entity requires parameter list 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_assignment_required_3.alogic: -------------------------------------------------------------------------------- 1 | network param_assignment_required_3 { 2 | in bool i; 3 | out wire bool o; 4 | new fsm inner { 5 | struct s { 6 | param uint P; 7 | static uint(P) id(uint(P) x) { 8 | return x; 9 | } 10 | } 11 | 12 | void main() { 13 | o = s.id(i); 14 | fence; 15 | } 16 | } 17 | } 18 | // :13: ERROR: Parametrized struct requires parameter list 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_bad_00.alogic: -------------------------------------------------------------------------------- 1 | network param_bad_00 { 2 | in bool i; 3 | param bool P = i; 4 | } 5 | 6 | compile param_bad_00() as top; 7 | 8 | // :3: ERROR: Default initializer of 'param' definition must be a compile time constant 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_bad_01.alogic: -------------------------------------------------------------------------------- 1 | network param_bad_01 { 2 | in bool i; 3 | param bool P = i; 4 | } 5 | 6 | compile param_bad_01(P=@unknownu(1)) as top; 7 | 8 | // :3: ERROR: Default initializer of 'param' definition must be a compile time constant 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_bad_02.alogic: -------------------------------------------------------------------------------- 1 | network param_bad_02 { 2 | param bool P = true; 3 | } 4 | 5 | compile param_bad_02(P=@unknownu(1)) as top; 6 | 7 | // :5: ERROR: Actual parameter value must be a compile time constant 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_type_00.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | param type T; 3 | T x; 4 | } 5 | 6 | fsm param_type_00 { 7 | in t(u8) i; 8 | out wire t(u8) o; 9 | 10 | void main() { 11 | o = i; 12 | fence; 13 | } 14 | } 15 | // @fec/golden {{{ 16 | // module param_type_00( 17 | // input wire [7:0] i__x, 18 | // output wire [7:0] o__x 19 | // ); 20 | // 21 | // assign o__x = i__x; 22 | // 23 | // endmodule 24 | // }}} 25 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_type_02.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | param type T; 3 | T x; 4 | } 5 | 6 | fsm param_type_02 { 7 | in t(2) i; 8 | out wire t(3) o; 9 | 10 | void main() { 11 | o = i; 12 | fence; 13 | } 14 | } 15 | // :7: ERROR: Actual value of parameter 'T' does not name a type 16 | // :2: NOTE: 'T' is defined here 17 | // :8: ERROR: Actual value of parameter 'T' does not name a type 18 | // :2: NOTE: 'T' is defined here 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/param_type_03.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | param type T = 10; 3 | T x; 4 | } 5 | 6 | fsm param_type_03 { 7 | in t() i; 8 | out wire t() o; 9 | 10 | void main() { 11 | o = i; 12 | fence; 13 | } 14 | } 15 | // :2: ERROR: Type parameter default initializer does not name a type 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/parametrized_top_entity_without_compile_directive.alogic: -------------------------------------------------------------------------------- 1 | network top { 2 | param bool P; 3 | } 4 | // :1: ERROR: Parametrized top level definition requires an explicit 'compile' directive 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/pipeline/degenerate_02.alogic: -------------------------------------------------------------------------------- 1 | network degenerate_02 { 2 | pipeline bool[1 + 1] bar; 3 | 4 | new fsm stage0 { 5 | void main() { 6 | bar[0] |= false; 7 | fence; 8 | } 9 | } 10 | } 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/port_default_only.alogic: -------------------------------------------------------------------------------- 1 | fsm port_default_only { 2 | out u8 o = 5; 3 | void main() { 4 | fence; 5 | } 6 | } 7 | // :2: WARNING: Output port 'o' is unused 8 | // @fec/golden {{{ 9 | // module port_default_only( 10 | // output wire [7:0] o 11 | // ); 12 | // assign o = 8'd5; 13 | // endmodule 14 | // }}} 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/ports_only_verbatim.alogic: -------------------------------------------------------------------------------- 1 | // @verilator-lint-off 2 | verbatim entity ports_only_verbatim { 3 | in u8 ia; 4 | in sync u8 ib; 5 | in sync ready u8 ic; 6 | out u8 oa; 7 | out sync u8 ob; 8 | out sync ready u8 oc; 9 | } 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits(u8) == 8; 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_0 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits(u8) == @bits(i8); 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_1 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_2.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits(u8) == 9; 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_2 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | // :2: ERROR: Static assertion failure 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_3.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits(u8) == 9, "u8 is not 9 bits"; 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_3 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | // :2: ERROR: Static assertion failure: u8 is not 9 bits 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_4.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits(t) % 8 == 0, "@bits(t) must be a multiple of 8"; 3 | u8 x; 4 | u8 y; 5 | bool oops; 6 | } 7 | 8 | network rec_static_assert_4 { 9 | out t o; 10 | 17'd0 -> o; 11 | } 12 | // :2: ERROR: Static assertion failure: @bits\(t\) must be a multiple of 8 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_5.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert 2'd0 + 3'd0; 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_5 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | // :2: ERROR: Both operands of binary '\+' must have the same width, but 11 | // :2: ERROR: ... left hand operand is 2 bits wide, and 12 | // :2: ERROR: ... right hand operand is 3 bits wide 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_6.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | param uint P; 3 | static assert P % 2 == 0, "P must be even"; 4 | bool x; 5 | } 6 | 7 | network rec_static_assert_6 { 8 | out t(2) o; 9 | 1'd0 -> o; 10 | } 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_7.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | param uint P; 3 | static assert P % 2 == 0, "P must be even"; 4 | bool x; 5 | } 6 | 7 | network rec_static_assert_7 { 8 | out t(3) o; 9 | 1'd0 -> o; 10 | } 11 | // :3: ERROR: Static assertion failure: P must be even 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/rec_static_assert_8.alogic: -------------------------------------------------------------------------------- 1 | struct t { 2 | static assert @bits; 3 | bool x; 4 | } 5 | 6 | network rec_static_assert_8 { 7 | out t o; 8 | 1'd0 -> o; 9 | } 10 | // :2: ERROR: Condition of 'static assert' is of neither numeric nor packed type 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/recursive_goto_0.alogic: -------------------------------------------------------------------------------- 1 | fsm recursive_goto_0 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | o = i; 7 | goto main(); 8 | } 9 | } 10 | // @fec/golden {{{ 11 | // module recursive_goto_0( 12 | // input i, 13 | // output o 14 | // ); 15 | // assign o = i; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/resolve_names_00.alogic: -------------------------------------------------------------------------------- 1 | fsm resolve_names_00 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | const u8 C#[0] = 1; 6 | 7 | void main() { 8 | o = i + C#[N]; 9 | fence; 10 | } 11 | } 12 | // :8: ERROR: 'N' is undefined 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/resolve_names_01.alogic: -------------------------------------------------------------------------------- 1 | fsm resolve_names_01 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | const u8 C#[0, 0] = 1; 6 | const uint M = 0; 7 | 8 | void main() { 9 | o = i + C#[M, N]; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: 'N' is undefined 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/resolve_names_02.alogic: -------------------------------------------------------------------------------- 1 | fsm resolve_names_02 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | const u8 C#[0] = 1; 6 | 7 | void main() { 8 | o = i + C#[8'd0 + 2'd0]; 9 | fence; 10 | } 11 | } 12 | // :8: ERROR: Both operands of binary '\+' must have the same width, but 13 | // :8: ERROR: ... left hand operand is 8 bits wide, and 14 | // :8: ERROR: ... right hand operand is 2 bits wide 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/resolve_names_03.alogic: -------------------------------------------------------------------------------- 1 | fsm resolve_names_03 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | const u8 C#[0] = 1; 6 | const u8 D#[0] = 0; 7 | 8 | void main() { 9 | o = i + C#[D#[8'd0 + 2'd0]]; 10 | fence; 11 | } 12 | } 13 | // :9: ERROR: Both operands of binary '\+' must have the same width, but 14 | // :9: ERROR: ... left hand operand is 8 bits wide, and 15 | // :9: ERROR: ... right hand operand is 2 bits wide 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/resolve_names_05.alogic: -------------------------------------------------------------------------------- 1 | fsm resolve_names_05 { 2 | in u8 i; 3 | out wire u8 o; 4 | 5 | gen if (true) : block { 6 | const u8 C#[0, 0] = 1; 7 | } 8 | 9 | void main() { 10 | o = i + block.C#[N]; 11 | fence; 12 | } 13 | } 14 | // :10: ERROR: 'N' is undefined 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/return_in_gen.alogic: -------------------------------------------------------------------------------- 1 | fsm return_in_gen { 2 | void main() { 3 | gen if (true) { 4 | return; 5 | } 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/reused_for_var.alogic: -------------------------------------------------------------------------------- 1 | fsm reused_for_var { 2 | void main() { 3 | for (u4 i = 0; i < 10; i++) { 4 | } 5 | for (u4 i = 0; i < 10; i++) { 6 | } 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/signoff_unused_out_of_bounds.alogic: -------------------------------------------------------------------------------- 1 | // TODO: This should be caught by the type checker. This test just ensures 2 | // the compiler doesn't crash... 3 | fsm signoff_unused_out_of_bounds { 4 | in bool c; 5 | in u5 i; 6 | out wire bool o; 7 | 8 | void main() { 9 | o = |i; 10 | if (c) { 11 | o = i[5]; 12 | } 13 | fence; 14 | } 15 | } 16 | // @verilator-lint-off 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/simplify_cat_00.alogic: -------------------------------------------------------------------------------- 1 | fsm simplify_cat_00 { 2 | in u2 i; 3 | out wire u2 o; 4 | void main() { 5 | o = i; 6 | {o[1], o[0]} = {o[0], o[1]}; 7 | fence; 8 | } 9 | } 10 | // @fec/golden {{{ 11 | // module simplify_cat_00( 12 | // input wire [1:0] i, 13 | // output wire [1:0] o 14 | // ); 15 | // assign o = {i[0], i[1]}; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/single_param_entity_1.alogic: -------------------------------------------------------------------------------- 1 | network single_param_entity_1 { 2 | in u2 i; 3 | out u2 o; 4 | 5 | network inner { 6 | in u2 ii; 7 | out u2 oo; 8 | ii -> oo; 9 | } 10 | 11 | inst = new inner(2); 12 | i -> inst.ii; inst.oo -> o; 13 | } 14 | // :11: ERROR: Type does not take any parameters 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/single_param_struct_0.alogic: -------------------------------------------------------------------------------- 1 | network single_param_struct_0 { 2 | struct s_t { 3 | param uint W; 4 | uint(W) a; 5 | } 6 | 7 | in s_t(2) i; 8 | out s_t(2) o; 9 | i -> o; 10 | } 11 | // @fec/golden {{{ 12 | // module single_param_struct_0 ( 13 | // input wire [1:0] i__a, 14 | // output wire [1:0] o__a 15 | // ); 16 | // assign o__a = i__a; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/single_param_struct_1.alogic: -------------------------------------------------------------------------------- 1 | network single_param_struct_1 { 2 | struct s_t { 3 | uint(2) a; 4 | } 5 | 6 | in s_t(2) i; 7 | out s_t(2) o; 8 | i -> o; 9 | } 10 | // :6: ERROR: Type does not take any parameters 11 | // :7: ERROR: Type does not take any parameters 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/single_param_struct_2.alogic: -------------------------------------------------------------------------------- 1 | network single_param_struct_2 { 2 | struct s_t { 3 | param uint W; 4 | param uint V; 5 | uint(W + V) a; 6 | } 7 | 8 | in s_t(1, 1) i; 9 | out s_t(1, 1) o; 10 | i -> o; 11 | } 12 | // @fec/golden {{{ 13 | // module single_param_struct_2 ( 14 | // input wire [1:0] i__a, 15 | // output wire [1:0] o__a 16 | // ); 17 | // assign o__a = i__a; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/single_param_struct_3.alogic: -------------------------------------------------------------------------------- 1 | network single_param_struct_3 { 2 | struct s_t { 3 | param uint W; 4 | param uint V = 1; 5 | uint(W + V) a; 6 | } 7 | 8 | in s_t(1) i; 9 | out s_t(1) o; 10 | i -> o; 11 | } 12 | // @fec/golden {{{ 13 | // module single_param_struct_3 ( 14 | // input wire [1:0] i__a, 15 | // output wire [1:0] o__a 16 | // ); 17 | // assign o__a = i__a; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/sized_param_init_0.alogic: -------------------------------------------------------------------------------- 1 | compile sized_param_init_0() as top; 2 | 3 | fsm sized_param_init_0 { 4 | param u32 DEPTH = 32'd512; 5 | out wire uint(DEPTH*2) p_o; 6 | 7 | void main() { 8 | p_o = 0; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module top( 14 | // output wire [1023:0] p_o 15 | // ); 16 | // 17 | // assign p_o = 1024'b0; 18 | // 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/sized_param_init_1.alogic: -------------------------------------------------------------------------------- 1 | compile sized_param_init_1() as top; 2 | 3 | fsm sized_param_init_1 { 4 | param u32 DEPTH = 32'd512; 5 | out wire uint(DEPTH*32'd2) p_o; 6 | 7 | void main() { 8 | p_o = 0; 9 | fence; 10 | } 11 | } 12 | // @fec/golden {{{ 13 | // module top( 14 | // output wire [1023:0] p_o 15 | // ); 16 | // 17 | // assign p_o = 1024'b0; 18 | // 19 | // endmodule 20 | // }}} 21 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/snoop_ports/snoop_01.alogic: -------------------------------------------------------------------------------- 1 | fsm snoop_01 { 2 | snoop sync ready void s; 3 | 4 | out wire bool o; 5 | 6 | void main() { 7 | o = s.move; 8 | fence; 9 | } 10 | } 11 | // @fec/golden {{{ 12 | // module snoop_01( 13 | // input wire s__valid, 14 | // input wire s__ready, 15 | // output wire o 16 | // ); 17 | // assign o = s__valid & s__ready; 18 | // endmodule 19 | // }}} 20 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/snoop_ports/snoop_02.alogic: -------------------------------------------------------------------------------- 1 | network snoop_02 { 2 | snoop sync bool i; 3 | } 4 | // :2: ERROR: 'snoop' port must use 'sync ready' flow control 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/snoop_ports/snoop_03.alogic: -------------------------------------------------------------------------------- 1 | network snoop_03 { 2 | snoop bool s; 3 | } 4 | // :2: ERROR: 'snoop' port must use 'sync ready' flow control 5 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_assert_0.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_assert_0 { 2 | void main() { 3 | assert true; 4 | fence; 5 | } 6 | } 7 | // @sim/test {{{ 8 | // wire _unused = &{1'd0, clk, rst}; 9 | // }}} 10 | // @sim/expect: TIMEOUT at 100ns 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_assert_1.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_assert_1 { 2 | void main() { 3 | assert true, "Not boom"; 4 | fence; 5 | } 6 | } 7 | // @sim/test {{{ 8 | // wire _unused = &{1'd0, clk, rst}; 9 | // }}} 10 | // @sim/expect: TIMEOUT at 100ns 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_assert_3.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_assert_3 { 2 | in sync bool i; 3 | void main() { 4 | i.read(); 5 | fence; 6 | assert i.read(); 7 | fence; 8 | } 9 | } 10 | // @sim/test {{{ 11 | // wire i = 1'd0; 12 | // wire i__valid = 1'd1; 13 | // }}} 14 | // @sim/expect {{{ 15 | // \[3000\] %Error: stmt_assert_3\.v:\d+: Assertion failed in TOP\.testbench\.dut: 'assert' statement failed at .*stmt_assert_3\.alogic:6 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_assert_4.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_assert_4 { 2 | in sync bool i; 3 | void main() { 4 | assert i.read(); 5 | fence; 6 | assert i.read(); 7 | fence; 8 | } 9 | } 10 | // @sim/test {{{ 11 | // wire i = 1'd0; 12 | // wire i__valid = 1'd1; 13 | // }}} 14 | // @sim/expect {{{ 15 | // \[2000\] %Error: stmt_assert_4\.v:\d+: Assertion failed in TOP\.testbench\.dut: 'assert' statement failed at .*stmt_assert_4\.alogic:4 16 | // }}} 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_assert_5.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_assert_5 { 2 | in bool i; 3 | void main() { 4 | assert i, "Boom"; 5 | fence; 6 | } 7 | } 8 | // @sim/test {{{ 9 | // wire i = 0; 10 | // }}} 11 | // @sim/expect {{{ 12 | // \[2000\] %Error: stmt_assert_5\.v:\d+: Assertion failed in TOP\.testbench\.dut: Boom 13 | // }}} 14 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_const_0.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_const_0 { 2 | in u2 i; 3 | out wire u2 o; 4 | 5 | void main() { 6 | const u2 x = i + 2'd1; 7 | o = x; 8 | fence; 9 | } 10 | } 11 | // @fec/golden {{{ 12 | // module stmt_const_0( 13 | // input wire [1:0] i, 14 | // output wire [1:0] o 15 | // ); 16 | // assign o = i + 2'd1; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_const_unsized.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_const_unsized { 2 | out wire u8 o; 3 | void main() { 4 | const uint CONSTANT = 1; 5 | o = CONSTANT; 6 | fence; 7 | } 8 | } 9 | // @fec/golden {{{ 10 | // module stmt_const_unsized( 11 | // output wire [7:0] o 12 | // ); 13 | // assign o = 8'd1; 14 | // endmodule 15 | // }}} 16 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_0.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_0 { 2 | void main() { 3 | static assert @bits(u8) == 8; 4 | fence; 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_1.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_1 { 2 | void main() { 3 | static assert @bits(u8) == @bits(i8); 4 | fence; 5 | } 6 | } 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_2.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_2 { 2 | void main() { 3 | static assert @bits(u8) == 9; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Static assertion failure 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_3.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_3 { 2 | void main() { 3 | static assert @bits(u8) == 9, "u8 is not 9 bits"; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Static assertion failure: u8 is not 9 bits 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_4.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_4 { 2 | in u32 i; 3 | void main() { 4 | static assert i; 5 | fence; 6 | } 7 | } 8 | // :4: ERROR: Condition of static assertion must be a compile time constant 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_5.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_5 { 2 | void main() { 3 | static assert 2'd0 + 3'd0; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Both operands of binary '\+' must have the same width, but 8 | // :3: ERROR: ... left hand operand is 2 bits wide, and 9 | // :3: ERROR: ... right hand operand is 3 bits wide 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_6.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_6 { 2 | const uint P = 2; 3 | void main() { 4 | static assert P % 2 == 0, "P must be even"; 5 | fence; 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_7.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_7 { 2 | const uint P = 3; 3 | void main() { 4 | static assert P % 2 == 0, "P must be even"; 5 | fence; 6 | } 7 | } 8 | // :4: ERROR: Static assertion failure: P must be even 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_static_assert_8.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_static_assert_8 { 2 | void main() { 3 | static assert @bits; 4 | fence; 5 | } 6 | } 7 | // :3: ERROR: Condition of 'static assert' is of neither numeric nor packed type 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/stmt_wait_04.alogic: -------------------------------------------------------------------------------- 1 | fsm stmt_wait_04 { 2 | in bool i; 3 | out bool o; 4 | 5 | void main() { 6 | wait; 7 | o = i; 8 | fence; 9 | } 10 | } 11 | // :6: ERROR: Wait condition is always false 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/struct_in_struct_0.alogic: -------------------------------------------------------------------------------- 1 | struct a { 2 | bool a0; 3 | } 4 | 5 | struct b { 6 | a b0; 7 | } 8 | 9 | network struct_in_struct_0 { 10 | in b i; 11 | out b o; 12 | i -> o; 13 | } 14 | // @fec/golden {{{ 15 | // module struct_in_struct_0( 16 | // input wire i__b0__a0, 17 | // output wire o__b0__a0 18 | // ); 19 | // assign o__b0__a0 = i__b0__a0; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/struct_in_struct_1.alogic: -------------------------------------------------------------------------------- 1 | struct a { 2 | bool a0; 3 | } 4 | 5 | struct b { 6 | a b0; 7 | } 8 | 9 | network struct_in_struct_1 { 10 | in b i; 11 | out b o; 12 | i -> o; 13 | } 14 | // @fec/golden {{{ 15 | // module struct_in_struct_1( 16 | // input wire i__b0__a0, 17 | // output wire o__b0__a0 18 | // ); 19 | // assign o__b0__a0 = i__b0__a0; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/struct_param_0.alogic: -------------------------------------------------------------------------------- 1 | struct s_t { 2 | param uint W; 3 | uint(W) a; 4 | } 5 | 6 | network struct_param_0 { 7 | in s_t(W=10) i; 8 | out s_t(W=10) o; 9 | i -> o; 10 | } 11 | // @fec/golden {{{ 12 | // module struct_param_0 ( 13 | // input wire [9:0] i__a, 14 | // output wire [9:0] o__a 15 | // ); 16 | // assign o__a = i__a; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/struct_param_3.alogic: -------------------------------------------------------------------------------- 1 | network struct_param_3 { 2 | struct s_t { 3 | param uint W; 4 | uint(W) a; 5 | } 6 | 7 | in s_t(W=9) i; 8 | out s_t(W=9) o; 9 | i -> o; 10 | } 11 | // @fec/golden {{{ 12 | // module struct_param_3 ( 13 | // input wire [8:0] i__a, 14 | // output wire [8:0] o__a 15 | // ); 16 | // assign o__a = i__a; 17 | // endmodule 18 | // }}} 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/target_language_keyword_00.alogic: -------------------------------------------------------------------------------- 1 | fsm target_language_keyword_00 { 2 | in bool input; 3 | out wire bool output; 4 | 5 | void main() { 6 | output = input; 7 | fence; 8 | } 9 | } 10 | // @fec/golden {{{ 11 | // module target_language_keyword_00( 12 | // input wire input_, 13 | // output wire output_ 14 | // ); 15 | // assign output_ = input_; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_0.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_0; 2 | 3 | network top_param_0 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: Parametrized entity requires parameter list 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_1.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_1() as top; 2 | 3 | network top_param_1 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: 'W' requires actual parameter value 8 | // :4: NOTE: 'W' is defined here 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_10.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_10(a#[0]) as top; 2 | 3 | network top_param_10 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: 'a#\[0\]' is undefined 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_11.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_11(top_param_11) as top; 2 | 3 | network top_param_11 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: Parametrized entity requires parameter list 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_12.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_12(2'd0 + 3'd0) as top; 2 | 3 | network top_param_12 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: Both operands of binary '\+' must have the same width, but 8 | // :1: ERROR: ... left hand operand is 2 bits wide, and 9 | // :1: ERROR: ... right hand operand is 3 bits wide 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_2.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_2(1) as top; 2 | 3 | network top_param_2 { 4 | param uint W; 5 | 6 | typedef uint(W) uw_t; 7 | 8 | in uw_t i; 9 | out uw_t o; 10 | 11 | i -> o; 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module top( 16 | // input wire i, 17 | // output wire o 18 | // ); 19 | // assign o = i; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_3.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_3(W=2) as top; 2 | 3 | network top_param_3 { 4 | param uint W; 5 | 6 | typedef uint(W) uw_t; 7 | 8 | in uw_t i; 9 | out uw_t o; 10 | 11 | i -> o; 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module top( 16 | // input wire [1:0] i, 17 | // output wire [1:0] o 18 | // ); 19 | // assign o = i; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_4.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_4(1, 1) as top; 2 | 3 | network top_param_4 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: Too many positional parameters 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_5.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_5(1, W=1) as top; 2 | 3 | network top_param_5 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: Mixing positional and named parameter assignments is not allowed 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_6.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_6(W=4, C=3) as top; 2 | 3 | network top_param_6 { 4 | param uint W; 5 | 6 | typedef uint(W) uw_t; 7 | 8 | param uw_t C; 9 | 10 | out uw_t o; 11 | 12 | C -> o; 13 | } 14 | 15 | // @fec/golden {{{ 16 | // module top( 17 | // output wire [3:0] o 18 | // ); 19 | // assign o = 4'd3; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_7.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_7(W=4, C=$clog2(513)) as top; 2 | 3 | network top_param_7 { 4 | param uint W; 5 | 6 | typedef uint(W) uw_t; 7 | 8 | param uw_t C; 9 | 10 | out uw_t o; 11 | 12 | C -> o; 13 | } 14 | 15 | // @fec/golden {{{ 16 | // module top( 17 | // output wire [3:0] o 18 | // ); 19 | // assign o = 4'd10; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_8.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_8(foo) as top; 2 | 3 | network top_param_8 { 4 | param uint W; 5 | } 6 | 7 | // :1: ERROR: 'foo' is undefined 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/top_param_9.alogic: -------------------------------------------------------------------------------- 1 | compile top_param_9#[0](1) as top; 2 | 3 | network top_param_9#[0] { 4 | param uint W; 5 | } 6 | 7 | // :4: WARNING: Parameter 'W' is unused 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_00.alogic: -------------------------------------------------------------------------------- 1 | fsm foo {} 2 | 3 | network type_of_00 { 4 | in foo i; 5 | } 6 | 7 | compile type_of_00; 8 | 9 | // :4: ERROR: Type specifier refers to an entity 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_01.alogic: -------------------------------------------------------------------------------- 1 | struct foo { 2 | param uint P; 3 | } 4 | 5 | network type_of_01 { 6 | in foo i; 7 | } 8 | 9 | // :6: ERROR: Parametrized struct requires parameter list 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_02.alogic: -------------------------------------------------------------------------------- 1 | network type_of_02 { 2 | param uint P; 3 | } 4 | 5 | compile type_of_02() as top; 6 | 7 | // :5: ERROR: 'P' requires actual parameter value 8 | // :2: NOTE: 'P' is defined here 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_03.alogic: -------------------------------------------------------------------------------- 1 | network type_of_03 { 2 | param type P; 3 | } 4 | 5 | compile type_of_03() as top; 6 | 7 | // :5: ERROR: 'P' requires actual parameter value 8 | // :2: NOTE: 'P' is defined here 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_04.alogic: -------------------------------------------------------------------------------- 1 | fsm type_of_04 { 2 | in u8 i; 3 | out u8 o; 4 | 5 | sram bool s[i]; 6 | 7 | void main() { 8 | o = @bits(s[0]); 9 | fence; 10 | } 11 | } 12 | // :5: ERROR: Size of SRAM must be a compile time constant 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/type_of_05.alogic: -------------------------------------------------------------------------------- 1 | fsm type_of_05 { 2 | in u8 i; 3 | out u8 o; 4 | 5 | bool s[i]; 6 | 7 | void main() { 8 | o = @bits(s[0]); 9 | fence; 10 | } 11 | } 12 | // :5: ERROR: Size of array must be a compile time constant 13 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/case_default_unreachable_structural_sharing.alogic: -------------------------------------------------------------------------------- 1 | fsm case_default_unreachable_structural_sharing { 2 | void main() { 3 | gen for (uint i < 2) { // 'gen' can cause structural sharing of the body 4 | case (2'd0) { 5 | 2'd0: @display("..."); 6 | default: unreachable; 7 | } 8 | } 9 | fence; 10 | } 11 | } 12 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/display_gen_var.alogic: -------------------------------------------------------------------------------- 1 | fsm display_gen_var { 2 | void main() { 3 | gen for (uint b = 0; b < 2; b++) { 4 | @display("%d", b); 5 | } 6 | fence; 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/do_cond_00.alogic: -------------------------------------------------------------------------------- 1 | fsm do_cond_00 { 2 | void main() { 3 | u8 i = 1; 4 | do {} while (i); 5 | } 6 | } 7 | // :4: ERROR: Condition of 'do' loop yields 8 bits, a 1 bit value is expected 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/for_cond_00.alogic: -------------------------------------------------------------------------------- 1 | fsm for_cond_00 { 2 | void main() { 3 | for (u8 i = 1; i ; i++) {} 4 | } 5 | } 6 | // :3: ERROR: Condition of 'for' loop yields 8 bits, a 1 bit value is expected 7 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/non_const_unsized_00.alogic: -------------------------------------------------------------------------------- 1 | fsm non_const_unsized_00 { 2 | in u6 i; 3 | out u6 o; 4 | void main() { 5 | o = i - ((i==1) ? 1 : 2); 6 | fence; 7 | } 8 | } 9 | // :5: ERROR: Expression of unsized integer type must be a compile time constant 10 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/propagate_type_error_00.alogic: -------------------------------------------------------------------------------- 1 | struct s_t { 2 | param uint WIDTH; 3 | const uint(WIDTH) C = 12'd0; 4 | } 5 | 6 | fsm propagate_type_error_00 { 7 | void main() { 8 | if (true) { 9 | if (true) { 10 | s_t(WIDTH=6) blk_seq; 11 | const uint X = @bits(blk_seq); 12 | } 13 | } 14 | fence; 15 | } 16 | } 17 | 18 | // :3: ERROR: Initializer expression yields 12 bits, a 6 bit value is expected 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/while_cond_00.alogic: -------------------------------------------------------------------------------- 1 | fsm while_cond_00 { 2 | void main() { 3 | u8 i = 1; 4 | while (i) {} 5 | } 6 | } 7 | // :4: ERROR: Condition of 'while' loop yields 8 bits, a 1 bit value is expected 8 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/zero_width_definition_00.alogic: -------------------------------------------------------------------------------- 1 | struct empty_t {} 2 | 3 | fsm zero_width_definition_00 { 4 | void main() { 5 | empty_t x = 0; 6 | fence; 7 | } 8 | } 9 | 10 | // :5: ERROR: 'x' has width 0 11 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/zero_width_definition_01.alogic: -------------------------------------------------------------------------------- 1 | struct maybe_empty_t { 2 | param bool P; 3 | gen if (P) { 4 | bool x; 5 | } 6 | } 7 | 8 | fsm zero_width_definition_01 { 9 | void main() { 10 | maybe_empty_t(true) x; 11 | maybe_empty_t(false) y; 12 | fence; 13 | } 14 | } 15 | 16 | // :11: ERROR: 'y' has width 0 17 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/zero_width_definition_02.alogic: -------------------------------------------------------------------------------- 1 | struct empty_t {} 2 | 3 | const empty_t x = 0; 4 | 5 | // :3: ERROR: 'x' has width 0 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/zero_width_definition_03.alogic: -------------------------------------------------------------------------------- 1 | struct empty_t {} 2 | 3 | void f(empty_t x) {} 4 | 5 | // :3: ERROR: 'x' has width 0 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/typechecker/zero_width_return_00.alogic: -------------------------------------------------------------------------------- 1 | struct empty_t {} 2 | 3 | empty_t f() {} 4 | 5 | // :3: ERROR: return type of 'f' has width 0 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/unsized_case_values.alogic: -------------------------------------------------------------------------------- 1 | fsm unsized_case_values { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | case (1) { 7 | 0: o = i; 8 | 1: o = ~i; 9 | } 10 | fence; 11 | } 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module unsized_case_values( 16 | // input wire i, 17 | // output wire o 18 | // ); 19 | // assign o = ~i; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/unused_ctrl_func_0.alogic: -------------------------------------------------------------------------------- 1 | fsm unused_ctrl_func_0 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | o = i; 7 | fence; 8 | } 9 | 10 | void f() { 11 | fence; 12 | } 13 | } 14 | // :10: WARNING: Function 'f' is unused 15 | // @fec/golden {{{ 16 | // module unused_ctrl_func_0( 17 | // input wire i, 18 | // output wire o 19 | // ); 20 | // assign o = i; 21 | // endmodule 22 | // }}} 23 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/unused_ctrl_func_1.alogic: -------------------------------------------------------------------------------- 1 | fsm unused_ctrl_func_1 { 2 | in bool i; 3 | out wire bool o; 4 | 5 | void main() { 6 | o = i; 7 | fence; 8 | } 9 | 10 | void f() { 11 | g(); 12 | } 13 | 14 | void g() { 15 | f(); 16 | } 17 | } 18 | // @fec/golden {{{ 19 | // module unused_ctrl_func_1( 20 | // input wire i, 21 | // output wire o 22 | // ); 23 | // assign o = i; 24 | // endmodule 25 | // }}} 26 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/unused_signoff_00.alogic: -------------------------------------------------------------------------------- 1 | network unused_signoff_00 { 2 | in u8 i; 3 | out u4 o; 4 | 5 | i[2 +: 4] -> o; 6 | } 7 | // @fec/golden {{{ 8 | // module unused_signoff_00( 9 | // input wire [7:0] i, 10 | // output wire [3:0] o 11 | // ); 12 | // assign o = i[5:2]; 13 | // endmodule 14 | // }}} 15 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/unused_signoff_01.alogic: -------------------------------------------------------------------------------- 1 | network unused_signoff_01 { 2 | in u4 i; 3 | in u4 b; 4 | out u4 o; 5 | 6 | i -> o; 7 | } 8 | // :3: WARNING: Input port 'b' is unused 9 | // @fec/golden {{{ 10 | // module unused_signoff_01( 11 | // input wire [3:0] i, 12 | // input wire [3:0] b, 13 | // output wire [3:0] o 14 | // ); 15 | // assign o = i; 16 | // endmodule 17 | // }}} 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_all_bad_00.alogic: -------------------------------------------------------------------------------- 1 | fsm using_all_bad_00 { 2 | bool b; 3 | using b.*; 4 | } 5 | // :3: ERROR: Target of 'using \.\*;' must be a compound type 6 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_one_simple_05.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | static bool not(bool i) { return ~i; } 3 | } 4 | 5 | fsm using_one_simple_05 { 6 | in bool i; 7 | out bool o; 8 | 9 | void main() { 10 | { 11 | using S.not; 12 | } 13 | o = not(i); 14 | fence; 15 | } 16 | } 17 | 18 | // :13: ERROR: 'not' is undefined 19 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_one_simple_06.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | static bool not(bool i) { return ~i; } 3 | } 4 | 5 | using S; 6 | 7 | fsm using_one_simple_06 { 8 | in bool i; 9 | out wire bool o; 10 | 11 | void main() { 12 | o = not(i); 13 | fence; 14 | } 15 | } 16 | 17 | // :5: ERROR: Redundant 'using' directive 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_one_simple_08.alogic: -------------------------------------------------------------------------------- 1 | struct S { 2 | static bool not(bool i) { return ~i; } 3 | } 4 | 5 | using S.foo; 6 | 7 | fsm using_one_simple_08 { 8 | in bool i; 9 | out wire bool o; 10 | 11 | void main() { 12 | o = foo(i); 13 | fence; 14 | } 15 | } 16 | 17 | // :5: ERROR: No member named 'foo' in value of type 'type struct S' 18 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_specialized_00.alogic: -------------------------------------------------------------------------------- 1 | struct S{ 2 | param uint WIDTH; 3 | uint(WIDTH) field; 4 | } 5 | 6 | using S(10) as T; 7 | 8 | network using_specialized_00 { 9 | in T i; 10 | out T o; 11 | i -> o; 12 | } 13 | 14 | // @fec/golden {{{ 15 | // module using_specialized_00( 16 | // input wire [9:0] i__field, 17 | // output wire [9:0] o__field 18 | // ); 19 | // assign o__field = i__field; 20 | // endmodule 21 | // }}} 22 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/using_specialized_01.alogic: -------------------------------------------------------------------------------- 1 | struct S{ 2 | param uint WIDTH; 3 | uint(WIDTH) field; 4 | } 5 | 6 | using S(10); 7 | 8 | // :6: ERROR: 'using' requires 'as' clause 9 | -------------------------------------------------------------------------------- /src/test/resources/compile/single/void_if_cond.alogic: -------------------------------------------------------------------------------- 1 | fsm void_if_cond { 2 | 3 | in sync void done_i; 4 | in u64 data_i; 5 | out u32 data_o; 6 | 7 | void main() { 8 | if (done_i) { // Should be done_i.valid! 9 | data_o = data_i[ 0 +: 32 ]; 10 | } 11 | fence; 12 | } 13 | } 14 | // :8: ERROR: Condition of 'if' statement yields 0 bits, a 1 bit value is expected 15 | --------------------------------------------------------------------------------