├── PROJECT WORK.pdf ├── README.md ├── Verilog code ├── Verilog testbench ├── arjun.cache └── wt │ ├── gui_handlers.wdf │ ├── java_command_handlers.wdf │ ├── project.wpc │ ├── synthesis.wdf │ ├── synthesis_details.wdf │ ├── webtalk_pa.xml │ └── xsim.wdf ├── arjun.hw └── arjun.lpr ├── arjun.ip_user_files └── README.txt ├── arjun.runs ├── impl_1 │ ├── Traffic_Light_Controller_19516.backup.vdi │ ├── vivado_10556.backup.jou │ └── vivado_19516.backup.jou └── synth_1 │ ├── ISEWrap.js │ ├── ISEWrap.sh │ ├── Traffic_Light_Controller.dcp │ ├── Traffic_Light_Controller.tcl │ ├── Traffic_Light_Controller.vds │ ├── Traffic_Light_Controller_utilization_synth.pb │ ├── Traffic_Light_Controller_utilization_synth.rpt │ ├── fsm_encoding.os │ ├── gen_run.xml │ ├── htr.txt │ ├── project.wdf │ ├── rundef.js │ ├── runme.bat │ ├── runme.log │ ├── runme.sh │ ├── vivado.jou │ └── vivado.pb ├── arjun.sim └── sim_1 │ └── behav │ └── xsim │ ├── Traffic_Light_Controller.tcl │ ├── Traffic_Light_Controller_TB.tcl │ ├── Traffic_Light_Controller_TB_behav.wdb │ ├── Traffic_Light_Controller_TB_vlog.prj │ ├── Traffic_Light_Controller_behav.wdb │ ├── Traffic_Light_Controller_vlog.prj │ ├── compile.bat │ ├── compile.log │ ├── elaborate.bat │ ├── elaborate.log │ ├── glbl.v │ ├── simulate.bat │ ├── simulate.log │ ├── webtalk.jou │ ├── webtalk.log │ ├── webtalk_1628.backup.jou │ ├── webtalk_1628.backup.log │ ├── webtalk_16716.backup.jou │ ├── webtalk_16716.backup.log │ ├── webtalk_20208.backup.jou │ ├── webtalk_20208.backup.log │ ├── webtalk_8304.backup.jou │ ├── webtalk_8304.backup.log │ ├── xelab.pb │ └── xsim.dir │ └── Traffic_Light_Controller_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ ├── xsim_0.win64.obj │ ├── xsim_1.c │ └── xsim_1.win64.obj │ ├── webtalk │ ├── usage_statistics_ext_xsim.html │ ├── usage_statistics_ext_xsim.wdm │ ├── usage_statistics_ext_xsim.xml │ └── xsim_webtalk.tcl │ ├── xsim.dbg │ ├── xsim.mem │ ├── xsim.reloc │ ├── xsim.rlx │ ├── xsim.rtti │ ├── xsim.svtype │ ├── xsim.type │ └── xsim.xdbg ├── arjun.srcs ├── constrs_1 │ └── new │ │ └── abd.xdc ├── sim_1 │ └── new │ │ └── Traffic_Light_Controller_TB.v └── sources_1 │ └── new │ └── Traffic_Light_Controller.v ├── arjun.xpr ├── system design.png └── youtube video link /PROJECT WORK.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/PROJECT WORK.pdf -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Traffic-Light-Controller-using-Verilog 2 | YOUTUBE VIDEO LINK -https://www.youtube.com/watch?v=Yt7no6rwCVk 3 | the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite. 4 | -------------------------------------------------------------------------------- /Verilog code: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16.07.2020 12:53:25 7 | // Design Name: 8 | // Module Name: Traffic_Light_Controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Traffic_Light_Controller( 24 | 25 | 26 | input clk,rst, 27 | output reg [2:0]light_M1, 28 | output reg [2:0]light_S, 29 | output reg [2:0]light_MT, 30 | output reg [2:0]light_M2 31 | ); 32 | 33 | parameter S1=0, S2=1, S3 =2, S4=3, S5=4,S6=5; 34 | reg [3:0]count; 35 | reg[2:0] ps; 36 | parameter sec7=7,sec5=5,sec2=2,sec3=3; 37 | 38 | 39 | 40 | always@(posedge clk or posedge rst) 41 | begin 42 | if(rst==1) 43 | begin 44 | ps<=S1; 45 | count<=0; 46 | end 47 | else 48 | 49 | 50 | 51 | 52 | case(ps) 53 | S1: if(count 2 | 3 | 6 | 7 |
8 | 9 | 10 |
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70 | 71 | 72 | -------------------------------------------------------------------------------- /arjun.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:241934075 5 | -------------------------------------------------------------------------------- /arjun.hw/arjun.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /arjun.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /arjun.runs/impl_1/Traffic_Light_Controller_19516.backup.vdi: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 12:20:18 2020 6 | # Process ID: 19516 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.runs/impl_1 8 | # Command line: vivado.exe -log Traffic_Light_Controller.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Traffic_Light_Controller.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller.vdi 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source Traffic_Light_Controller.tcl -notrace 13 | Command: open_checkpoint D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller.dcp 14 | 15 | Starting open_checkpoint Task 16 | 17 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 232.063 ; gain = 0.000 18 | INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement 19 | INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds 20 | INFO: [Project 1-479] Netlist was created with Vivado 2017.4 21 | INFO: [Device 21-403] Loading part xc7a100tcsg324-1 22 | INFO: [Project 1-570] Preparing netlist for logic optimization 23 | Parsing XDC File [D:/Xilinx_projects/arjun/arjun.runs/impl_1/.Xil/Vivado-19516-LAPTOP-4TN0NJ6K/dcp1/Traffic_Light_Controller.xdc] 24 | Finished Parsing XDC File [D:/Xilinx_projects/arjun/arjun.runs/impl_1/.Xil/Vivado-19516-LAPTOP-4TN0NJ6K/dcp1/Traffic_Light_Controller.xdc] 25 | Reading XDEF placement. 26 | Reading placer database... 27 | Reading XDEF routing. 28 | Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.056 . Memory (MB): peak = 601.930 ; gain = 0.000 29 | Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | 30 | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 601.930 ; gain = 0.000 31 | INFO: [Project 1-111] Unisim Transformation Summary: 32 | No Unisim elements were transformed. 33 | 34 | INFO: [Project 1-604] Checkpoint was created with Vivado v2017.4 (64-bit) build 2086221 35 | open_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 601.930 ; gain = 376.598 36 | Command: opt_design 37 | Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' 38 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' 39 | Running DRC as a precondition to command opt_design 40 | 41 | Starting DRC Task 42 | INFO: [DRC 23-27] Running DRC with 2 threads 43 | INFO: [Project 1-461] DRC finished with 0 Errors 44 | INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. 45 | 46 | Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.690 . Memory (MB): peak = 617.289 ; gain = 15.172 47 | INFO: [Timing 38-35] Done setting XDC timing constraints. 48 | 49 | Starting Logic Optimization Task 50 | 51 | Phase 1 Retarget 52 | INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s). 53 | INFO: [Opt 31-49] Retargeted 0 cell(s). 54 | Phase 1 Retarget | Checksum: 1894d1af3 55 | 56 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.893 . Memory (MB): peak = 1166.164 ; gain = 0.000 57 | INFO: [Opt 31-389] Phase Retarget created 3 cells and removed 4 cells 58 | 59 | Phase 2 Constant propagation 60 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 61 | Phase 2 Constant propagation | Checksum: 1894d1af3 62 | 63 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.906 . Memory (MB): peak = 1166.164 ; gain = 0.000 64 | INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells 65 | 66 | Phase 3 Sweep 67 | Phase 3 Sweep | Checksum: 1894d1af3 68 | 69 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.955 . Memory (MB): peak = 1166.164 ; gain = 0.000 70 | INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells 71 | 72 | Phase 4 BUFG optimization 73 | Phase 4 BUFG optimization | Checksum: 1894d1af3 74 | 75 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.979 . Memory (MB): peak = 1166.164 ; gain = 0.000 76 | INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells 77 | 78 | Phase 5 Shift Register Optimization 79 | Phase 5 Shift Register Optimization | Checksum: 1894d1af3 80 | 81 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1166.164 ; gain = 0.000 82 | INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells 83 | 84 | Starting Connectivity Check Task 85 | 86 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1166.164 ; gain = 0.000 87 | Ending Logic Optimization Task | Checksum: 1894d1af3 88 | 89 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.993 . Memory (MB): peak = 1166.164 ; gain = 0.000 90 | 91 | Starting Power Optimization Task 92 | INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. 93 | Ending Power Optimization Task | Checksum: 14faa3fec 94 | 95 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.091 . Memory (MB): peak = 1166.164 ; gain = 0.000 96 | INFO: [Common 17-83] Releasing license: Implementation 97 | 22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 98 | opt_design completed successfully 99 | opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:14 . Memory (MB): peak = 1166.164 ; gain = 564.234 100 | Writing placer database... 101 | Writing XDEF routing. 102 | Writing XDEF routing logical nets. 103 | Writing XDEF routing special nets. 104 | Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.113 . Memory (MB): peak = 1166.164 ; gain = 0.000 105 | INFO: [Common 17-1381] The checkpoint 'D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_opt.dcp' has been generated. 106 | INFO: [runtcl-4] Executing : report_drc -file Traffic_Light_Controller_drc_opted.rpt -pb Traffic_Light_Controller_drc_opted.pb -rpx Traffic_Light_Controller_drc_opted.rpx 107 | Command: report_drc -file Traffic_Light_Controller_drc_opted.rpt -pb Traffic_Light_Controller_drc_opted.pb -rpx Traffic_Light_Controller_drc_opted.rpx 108 | INFO: [IP_Flow 19-234] Refreshing IP repositories 109 | INFO: [IP_Flow 19-1704] No user IP repositories specified 110 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Xilinx/Vivado/2017.4/data/ip'. 111 | INFO: [DRC 23-27] Running DRC with 2 threads 112 | INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_drc_opted.rpt. 113 | report_drc completed successfully 114 | report_drc: Time (s): cpu = 00:00:03 ; elapsed = 00:00:13 . Memory (MB): peak = 1166.164 ; gain = 0.000 115 | INFO: [Chipscope 16-241] No debug cores found in the current design. 116 | Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode) 117 | or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design. 118 | Command: place_design 119 | Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' 120 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' 121 | INFO: [DRC 23-27] Running DRC with 2 threads 122 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors 123 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 124 | Running DRC as a precondition to command place_design 125 | INFO: [DRC 23-27] Running DRC with 2 threads 126 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors 127 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 128 | 129 | Starting Placer Task 130 | INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs 131 | 132 | Phase 1 Placer Initialization 133 | 134 | Phase 1.1 Placer Initialization Netlist Sorting 135 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1166.164 ; gain = 0.000 136 | Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 12ea003ff 137 | 138 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.164 . Memory (MB): peak = 1166.164 ; gain = 0.000 139 | INFO: [Timing 38-35] Done setting XDC timing constraints. 140 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 141 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1166.867 ; gain = 0.000 142 | 143 | Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device 144 | INFO: [Timing 38-35] Done setting XDC timing constraints. 145 | Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d1a4e808 146 | 147 | Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1167.793 ; gain = 1.629 148 | 149 | Phase 1.3 Build Placer Netlist Model 150 | Phase 1.3 Build Placer Netlist Model | Checksum: 1bc4321de 151 | 152 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1167.793 ; gain = 1.629 153 | 154 | Phase 1.4 Constrain Clocks/Macros 155 | Phase 1.4 Constrain Clocks/Macros | Checksum: 1bc4321de 156 | 157 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1167.793 ; gain = 1.629 158 | Phase 1 Placer Initialization | Checksum: 1bc4321de 159 | 160 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1167.793 ; gain = 1.629 161 | 162 | Phase 2 Global Placement 163 | Phase 2 Global Placement | Checksum: 111de4ece 164 | 165 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1167.793 ; gain = 1.629 166 | 167 | Phase 3 Detail Placement 168 | 169 | Phase 3.1 Commit Multi Column Macros 170 | Phase 3.1 Commit Multi Column Macros | Checksum: 111de4ece 171 | 172 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1167.793 ; gain = 1.629 173 | 174 | Phase 3.2 Commit Most Macros & LUTRAMs 175 | Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 143aaff7a 176 | 177 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1167.793 ; gain = 1.629 178 | 179 | Phase 3.3 Area Swap Optimization 180 | Phase 3.3 Area Swap Optimization | Checksum: 190d9892f 181 | 182 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1167.793 ; gain = 1.629 183 | 184 | Phase 3.4 Pipeline Register Optimization 185 | Phase 3.4 Pipeline Register Optimization | Checksum: 190d9892f 186 | 187 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1167.793 ; gain = 1.629 188 | 189 | Phase 3.5 Small Shape Detail Placement 190 | Phase 3.5 Small Shape Detail Placement | Checksum: 12a825adf 191 | 192 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 193 | 194 | Phase 3.6 Re-assign LUT pins 195 | Phase 3.6 Re-assign LUT pins | Checksum: 12a825adf 196 | 197 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 198 | 199 | Phase 3.7 Pipeline Register Optimization 200 | Phase 3.7 Pipeline Register Optimization | Checksum: 12a825adf 201 | 202 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 203 | Phase 3 Detail Placement | Checksum: 12a825adf 204 | 205 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 206 | 207 | Phase 4 Post Placement Optimization and Clean-Up 208 | 209 | Phase 4.1 Post Commit Optimization 210 | Phase 4.1 Post Commit Optimization | Checksum: 12a825adf 211 | 212 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 213 | 214 | Phase 4.2 Post Placement Cleanup 215 | Phase 4.2 Post Placement Cleanup | Checksum: 12a825adf 216 | 217 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 218 | 219 | Phase 4.3 Placer Reporting 220 | Phase 4.3 Placer Reporting | Checksum: 12a825adf 221 | 222 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 223 | 224 | Phase 4.4 Final Placement Cleanup 225 | Phase 4.4 Final Placement Cleanup | Checksum: 14936a231 226 | 227 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 228 | Phase 4 Post Placement Optimization and Clean-Up | Checksum: 14936a231 229 | 230 | Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 231 | Ending Placer Task | Checksum: 10e14caee 232 | 233 | Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1168.184 ; gain = 2.020 234 | INFO: [Common 17-83] Releasing license: Implementation 235 | 42 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 236 | place_design completed successfully 237 | Writing placer database... 238 | Writing XDEF routing. 239 | Writing XDEF routing logical nets. 240 | Writing XDEF routing special nets. 241 | Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1168.184 ; gain = 0.000 242 | INFO: [Common 17-1381] The checkpoint 'D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_placed.dcp' has been generated. 243 | INFO: [runtcl-4] Executing : report_io -file Traffic_Light_Controller_io_placed.rpt 244 | report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.184 . Memory (MB): peak = 1168.184 ; gain = 0.000 245 | INFO: [runtcl-4] Executing : report_utilization -file Traffic_Light_Controller_utilization_placed.rpt -pb Traffic_Light_Controller_utilization_placed.pb 246 | report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.262 . Memory (MB): peak = 1168.184 ; gain = 0.000 247 | INFO: [runtcl-4] Executing : report_control_sets -verbose -file Traffic_Light_Controller_control_sets_placed.rpt 248 | report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1168.184 ; gain = 0.000 249 | Command: route_design 250 | Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' 251 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' 252 | Running DRC as a precondition to command route_design 253 | INFO: [DRC 23-27] Running DRC with 2 threads 254 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors 255 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. 256 | 257 | 258 | Starting Routing Task 259 | INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs 260 | Checksum: PlaceDB: 875e7fc9 ConstDB: 0 ShapeSum: 86b64b25 RouteDB: 0 261 | 262 | Phase 1 Build RT Design 263 | Phase 1 Build RT Design | Checksum: 104954346 264 | 265 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1320.551 ; gain = 152.367 266 | Post Restoration Checksum: NetGraph: a0b32519 NumContArr: 63e21e2d Constraints: 0 Timing: 0 267 | 268 | Phase 2 Router Initialization 269 | INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. 270 | 271 | Phase 2.1 Fix Topology Constraints 272 | Phase 2.1 Fix Topology Constraints | Checksum: 104954346 273 | 274 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.004 ; gain = 157.820 275 | 276 | Phase 2.2 Pre Route Cleanup 277 | Phase 2.2 Pre Route Cleanup | Checksum: 104954346 278 | 279 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1326.004 ; gain = 157.820 280 | Number of Nodes with overlaps = 0 281 | Phase 2 Router Initialization | Checksum: 159940136 282 | 283 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1333.816 ; gain = 165.633 284 | 285 | Phase 3 Initial Routing 286 | Phase 3 Initial Routing | Checksum: 13d2bff43 287 | 288 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1333.816 ; gain = 165.633 289 | 290 | Phase 4 Rip-up And Reroute 291 | 292 | Phase 4.1 Global Iteration 0 293 | Number of Nodes with overlaps = 0 294 | Phase 4.1 Global Iteration 0 | Checksum: 35f77bc7 295 | 296 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 297 | Phase 4 Rip-up And Reroute | Checksum: 35f77bc7 298 | 299 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 300 | 301 | Phase 5 Delay and Skew Optimization 302 | Phase 5 Delay and Skew Optimization | Checksum: 35f77bc7 303 | 304 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 305 | 306 | Phase 6 Post Hold Fix 307 | 308 | Phase 6.1 Hold Fix Iter 309 | Phase 6.1 Hold Fix Iter | Checksum: 35f77bc7 310 | 311 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 312 | Phase 6 Post Hold Fix | Checksum: 35f77bc7 313 | 314 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 315 | 316 | Phase 7 Route finalize 317 | 318 | Router Utilization Summary 319 | Global Vertical Routing Utilization = 0.0124908 % 320 | Global Horizontal Routing Utilization = 0.0024865 % 321 | Routable Net Status* 322 | *Does not include unroutable nets such as driverless and loadless. 323 | Run report_route_status for detailed report. 324 | Number of Failed Nets = 0 325 | Number of Unrouted Nets = 0 326 | Number of Partially Routed Nets = 0 327 | Number of Node Overlaps = 0 328 | 329 | Utilization threshold used for congestion level computation: 0.85 330 | Congestion Report 331 | North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. 332 | South Dir 1x1 Area, Max Cong = 23.4234%, No Congested Regions. 333 | East Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. 334 | West Dir 1x1 Area, Max Cong = 5.88235%, No Congested Regions. 335 | Phase 7 Route finalize | Checksum: 35f77bc7 336 | 337 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1333.816 ; gain = 165.633 338 | 339 | Phase 8 Verifying routed nets 340 | 341 | Verification completed successfully 342 | Phase 8 Verifying routed nets | Checksum: 35f77bc7 343 | 344 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.012 ; gain = 165.828 345 | 346 | Phase 9 Depositing Routes 347 | Phase 9 Depositing Routes | Checksum: d89c74f4 348 | 349 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.012 ; gain = 165.828 350 | INFO: [Route 35-16] Router Completed Successfully 351 | 352 | Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1334.012 ; gain = 165.828 353 | 354 | Routing Is Done. 355 | INFO: [Common 17-83] Releasing license: Implementation 356 | 54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. 357 | route_design completed successfully 358 | route_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1334.012 ; gain = 165.828 359 | Writing placer database... 360 | Writing XDEF routing. 361 | Writing XDEF routing logical nets. 362 | Writing XDEF routing special nets. 363 | Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.090 . Memory (MB): peak = 1334.012 ; gain = 0.000 364 | INFO: [Common 17-1381] The checkpoint 'D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_routed.dcp' has been generated. 365 | INFO: [runtcl-4] Executing : report_drc -file Traffic_Light_Controller_drc_routed.rpt -pb Traffic_Light_Controller_drc_routed.pb -rpx Traffic_Light_Controller_drc_routed.rpx 366 | Command: report_drc -file Traffic_Light_Controller_drc_routed.rpt -pb Traffic_Light_Controller_drc_routed.pb -rpx Traffic_Light_Controller_drc_routed.rpx 367 | INFO: [IP_Flow 19-1839] IP Catalog is up to date. 368 | INFO: [DRC 23-27] Running DRC with 2 threads 369 | INFO: [Coretcl 2-168] The results of DRC are in file D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_drc_routed.rpt. 370 | report_drc completed successfully 371 | INFO: [runtcl-4] Executing : report_methodology -file Traffic_Light_Controller_methodology_drc_routed.rpt -pb Traffic_Light_Controller_methodology_drc_routed.pb -rpx Traffic_Light_Controller_methodology_drc_routed.rpx 372 | Command: report_methodology -file Traffic_Light_Controller_methodology_drc_routed.rpt -pb Traffic_Light_Controller_methodology_drc_routed.pb -rpx Traffic_Light_Controller_methodology_drc_routed.rpx 373 | INFO: [Timing 38-35] Done setting XDC timing constraints. 374 | INFO: [Timing 38-35] Done setting XDC timing constraints. 375 | INFO: [DRC 23-133] Running Methodology with 2 threads 376 | INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller_methodology_drc_routed.rpt. 377 | report_methodology completed successfully 378 | INFO: [runtcl-4] Executing : report_power -file Traffic_Light_Controller_power_routed.rpt -pb Traffic_Light_Controller_power_summary_routed.pb -rpx Traffic_Light_Controller_power_routed.rpx 379 | Command: report_power -file Traffic_Light_Controller_power_routed.rpt -pb Traffic_Light_Controller_power_summary_routed.pb -rpx Traffic_Light_Controller_power_routed.rpx 380 | WARNING: [Power 33-232] No user defined clocks were found in the design! 381 | Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate 382 | INFO: [Timing 38-35] Done setting XDC timing constraints. 383 | Running Vector-less Activity Propagation... 384 | 385 | Finished Running Vector-less Activity Propagation 386 | 66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. 387 | report_power completed successfully 388 | INFO: [runtcl-4] Executing : report_route_status -file Traffic_Light_Controller_route_status.rpt -pb Traffic_Light_Controller_route_status.pb 389 | INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file Traffic_Light_Controller_timing_summary_routed.rpt -rpx Traffic_Light_Controller_timing_summary_routed.rpx -warn_on_violation 390 | INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. 391 | INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs 392 | WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis. 393 | INFO: [runtcl-4] Executing : report_incremental_reuse -file Traffic_Light_Controller_incremental_reuse_routed.rpt 394 | INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. 395 | INFO: [runtcl-4] Executing : report_clock_utilization -file Traffic_Light_Controller_clock_utilization_routed.rpt 396 | INFO: [Common 17-206] Exiting Vivado at Fri Jul 17 12:21:56 2020... 397 | -------------------------------------------------------------------------------- /arjun.runs/impl_1/vivado_10556.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 12:36:14 2020 6 | # Process ID: 10556 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.runs/impl_1 8 | # Command line: vivado.exe -log Traffic_Light_Controller.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Traffic_Light_Controller.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller.vdi 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source Traffic_Light_Controller.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.runs/impl_1/vivado_19516.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 12:20:18 2020 6 | # Process ID: 19516 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.runs/impl_1 8 | # Command line: vivado.exe -log Traffic_Light_Controller.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source Traffic_Light_Controller.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.runs/impl_1/Traffic_Light_Controller.vdi 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.runs/impl_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source Traffic_Light_Controller.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/ISEWrap.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | // GLOBAL VARIABLES 8 | var ISEShell = new ActiveXObject( "WScript.Shell" ); 9 | var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); 10 | var ISERunDir = ""; 11 | var ISELogFile = "runme.log"; 12 | var ISELogFileStr = null; 13 | var ISELogEcho = true; 14 | var ISEOldVersionWSH = false; 15 | 16 | 17 | 18 | // BOOTSTRAP 19 | ISEInit(); 20 | 21 | 22 | 23 | // 24 | // ISE FUNCTIONS 25 | // 26 | function ISEInit() { 27 | 28 | // 1. RUN DIR setup 29 | var ISEScrFP = WScript.ScriptFullName; 30 | var ISEScrN = WScript.ScriptName; 31 | ISERunDir = 32 | ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); 33 | 34 | // 2. LOG file setup 35 | ISELogFileStr = ISEOpenFile( ISELogFile ); 36 | 37 | // 3. LOG echo? 38 | var ISEScriptArgs = WScript.Arguments; 39 | for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; 106 | ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); 107 | ISELogFileStr = ISEOpenFile( ISELogFile ); 108 | 109 | } else { // WSH 5.6 110 | 111 | // LAUNCH! 112 | ISEShell.CurrentDirectory = ISERunDir; 113 | 114 | // Redirect STDERR to STDOUT 115 | ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; 116 | var ISEProcess = ISEShell.Exec( ISECmdLine ); 117 | 118 | // BEGIN file creation 119 | var ISENetwork = WScript.CreateObject( "WScript.Network" ); 120 | var ISEHost = ISENetwork.ComputerName; 121 | var ISEUser = ISENetwork.UserName; 122 | var ISEPid = ISEProcess.ProcessID; 123 | var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); 124 | ISEBeginFile.WriteLine( "" ); 125 | ISEBeginFile.WriteLine( "" ); 126 | ISEBeginFile.WriteLine( " " ); 131 | ISEBeginFile.WriteLine( " " ); 132 | ISEBeginFile.WriteLine( "" ); 133 | ISEBeginFile.Close(); 134 | 135 | var ISEOutStr = ISEProcess.StdOut; 136 | var ISEErrStr = ISEProcess.StdErr; 137 | 138 | // WAIT for ISEStep to finish 139 | while ( ISEProcess.Status == 0 ) { 140 | 141 | // dump stdout then stderr - feels a little arbitrary 142 | while ( !ISEOutStr.AtEndOfStream ) { 143 | ISEStdOut( ISEOutStr.ReadLine() ); 144 | } 145 | 146 | WScript.Sleep( 100 ); 147 | } 148 | 149 | ISEExitCode = ISEProcess.ExitCode; 150 | } 151 | 152 | ISELogFileStr.Close(); 153 | 154 | // END/ERROR file creation 155 | if ( ISEExitCode != 0 ) { 156 | ISETouchFile( ISEStep, "error" ); 157 | 158 | } else { 159 | ISETouchFile( ISEStep, "end" ); 160 | } 161 | 162 | return ISEExitCode; 163 | } 164 | 165 | 166 | // 167 | // UTILITIES 168 | // 169 | function ISEStdOut( ISELine ) { 170 | 171 | ISELogFileStr.WriteLine( ISELine ); 172 | 173 | if ( ISELogEcho ) { 174 | WScript.StdOut.WriteLine( ISELine ); 175 | } 176 | } 177 | 178 | function ISEStdErr( ISELine ) { 179 | 180 | ISELogFileStr.WriteLine( ISELine ); 181 | 182 | if ( ISELogEcho ) { 183 | WScript.StdErr.WriteLine( ISELine ); 184 | } 185 | } 186 | 187 | function ISETouchFile( ISERoot, ISEStatus ) { 188 | 189 | var ISETFile = 190 | ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); 191 | ISETFile.Close(); 192 | } 193 | 194 | function ISEOpenFile( ISEFilename ) { 195 | 196 | // This function has been updated to deal with a problem seen in CR #870871. 197 | // In that case the user runs a script that runs impl_1, and then turns around 198 | // and runs impl_1 -to_step write_bitstream. That second run takes place in 199 | // the same directory, which means we may hit some of the same files, and in 200 | // particular, we will open the runme.log file. Even though this script closes 201 | // the file (now), we see cases where a subsequent attempt to open the file 202 | // fails. Perhaps the OS is slow to release the lock, or the disk comes into 203 | // play? In any case, we try to work around this by first waiting if the file 204 | // is already there for an arbitrary 5 seconds. Then we use a try-catch block 205 | // and try to open the file 10 times with a one second delay after each attempt. 206 | // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. 207 | // If there is an unrecognized exception when trying to open the file, we output 208 | // an error message and write details to an exception.log file. 209 | var ISEFullPath = ISERunDir + "/" + ISEFilename; 210 | if (ISEFileSys.FileExists(ISEFullPath)) { 211 | // File is already there. This could be a problem. Wait in case it is still in use. 212 | WScript.Sleep(5000); 213 | } 214 | var i; 215 | for (i = 0; i < 10; ++i) { 216 | try { 217 | return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); 218 | } catch (exception) { 219 | var error_code = exception.number & 0xFFFF; // The other bits are a facility code. 220 | if (error_code == 52) { // 52 is bad file name or number. 221 | // Wait a second and try again. 222 | WScript.Sleep(1000); 223 | continue; 224 | } else { 225 | WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 226 | var exceptionFilePath = ISERunDir + "/exception.log"; 227 | if (!ISEFileSys.FileExists(exceptionFilePath)) { 228 | WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); 229 | var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); 230 | exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); 231 | exceptionFile.WriteLine("\tException name: " + exception.name); 232 | exceptionFile.WriteLine("\tException error code: " + error_code); 233 | exceptionFile.WriteLine("\tException message: " + exception.message); 234 | exceptionFile.Close(); 235 | } 236 | throw exception; 237 | } 238 | } 239 | } 240 | // If we reached this point, we failed to open the file after 10 attempts. 241 | // We need to error out. 242 | WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); 243 | WScript.Quit(1); 244 | } 245 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/ISEWrap.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # ISEWrap.sh: Vivado Runs Script for UNIX 6 | # Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | HD_LOG=$1 10 | shift 11 | 12 | # CHECK for a STOP FILE 13 | if [ -f .stop.rst ] 14 | then 15 | echo "" >> $HD_LOG 16 | echo "*** Halting run - EA reset detected ***" >> $HD_LOG 17 | echo "" >> $HD_LOG 18 | exit 1 19 | fi 20 | 21 | ISE_STEP=$1 22 | shift 23 | 24 | # WRITE STEP HEADER to LOG 25 | echo "" >> $HD_LOG 26 | echo "*** Running $ISE_STEP" >> $HD_LOG 27 | echo " with args $@" >> $HD_LOG 28 | echo "" >> $HD_LOG 29 | 30 | # LAUNCH! 31 | $ISE_STEP "$@" >> $HD_LOG 2>&1 & 32 | 33 | # BEGIN file creation 34 | ISE_PID=$! 35 | if [ X != X$HOSTNAME ] 36 | then 37 | ISE_HOST=$HOSTNAME #bash 38 | else 39 | ISE_HOST=$HOST #csh 40 | fi 41 | ISE_USER=$USER 42 | ISE_BEGINFILE=.$ISE_STEP.begin.rst 43 | /bin/touch $ISE_BEGINFILE 44 | echo "" >> $ISE_BEGINFILE 45 | echo "" >> $ISE_BEGINFILE 46 | echo " " >> $ISE_BEGINFILE 47 | echo " " >> $ISE_BEGINFILE 48 | echo "" >> $ISE_BEGINFILE 49 | 50 | # WAIT for ISEStep to finish 51 | wait $ISE_PID 52 | 53 | # END/ERROR file creation 54 | RETVAL=$? 55 | if [ $RETVAL -eq 0 ] 56 | then 57 | /bin/touch .$ISE_STEP.end.rst 58 | else 59 | /bin/touch .$ISE_STEP.error.rst 60 | fi 61 | 62 | exit $RETVAL 63 | 64 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/Traffic_Light_Controller.dcp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.runs/synth_1/Traffic_Light_Controller.dcp -------------------------------------------------------------------------------- /arjun.runs/synth_1/Traffic_Light_Controller.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # Synthesis run script generated by Vivado 3 | # 4 | 5 | proc create_report { reportName command } { 6 | set status "." 7 | append status $reportName ".fail" 8 | if { [file exists $status] } { 9 | eval file delete [glob $status] 10 | } 11 | send_msg_id runtcl-4 info "Executing : $command" 12 | set retval [eval catch { $command } msg] 13 | if { $retval != 0 } { 14 | set fp [open $status w] 15 | close $fp 16 | send_msg_id runtcl-5 warning "$msg" 17 | } 18 | } 19 | set_msg_config -id {Synth 8-256} -limit 10000 20 | set_msg_config -id {Synth 8-638} -limit 10000 21 | create_project -in_memory -part xc7a100tcsg324-1 22 | 23 | set_param project.singleFileAddWarning.threshold 0 24 | set_param project.compositeFile.enableAutoGeneration 0 25 | set_param synth.vivado.isSynthRun true 26 | set_property webtalk.parent_dir D:/Xilinx_projects/arjun/arjun.cache/wt [current_project] 27 | set_property parent.project_path D:/Xilinx_projects/arjun/arjun.xpr [current_project] 28 | set_property default_lib xil_defaultlib [current_project] 29 | set_property target_language Verilog [current_project] 30 | set_property ip_output_repo d:/Xilinx_projects/arjun/arjun.cache/ip [current_project] 31 | set_property ip_cache_permissions {read write} [current_project] 32 | read_verilog -library xil_defaultlib D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v 33 | # Mark all dcp files as not used in implementation to prevent them from being 34 | # stitched into the results of this synthesis run. Any black boxes in the 35 | # design are intentionally left as such for best results. Dcp files will be 36 | # stitched into the design at a later time, either when this synthesis run is 37 | # opened, or when it is stitched into a dependent implementation run. 38 | foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { 39 | set_property used_in_implementation false $dcp 40 | } 41 | read_xdc D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc 42 | set_property used_in_implementation false [get_files D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc] 43 | 44 | 45 | synth_design -top Traffic_Light_Controller -part xc7a100tcsg324-1 46 | 47 | 48 | # disable binary constraint mode for synth run checkpoints 49 | set_param constraints.enableBinaryConstraints false 50 | write_checkpoint -force -noxdef Traffic_Light_Controller.dcp 51 | create_report "synth_1_synth_report_utilization_0" "report_utilization -file Traffic_Light_Controller_utilization_synth.rpt -pb Traffic_Light_Controller_utilization_synth.pb" 52 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/Traffic_Light_Controller.vds: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 12:43:06 2020 6 | # Process ID: 11168 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.runs/synth_1 8 | # Command line: vivado.exe -log Traffic_Light_Controller.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl 9 | # Log file: D:/Xilinx_projects/arjun/arjun.runs/synth_1/Traffic_Light_Controller.vds 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source Traffic_Light_Controller.tcl -notrace 13 | Command: synth_design -top Traffic_Light_Controller -part xc7a100tcsg324-1 14 | Starting synth_design 15 | Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' 16 | INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' 17 | INFO: Launching helper process for spawning children vivado processes 18 | INFO: Helper process launched with PID 10896 19 | --------------------------------------------------------------------------------- 20 | Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 387.195 ; gain = 97.902 21 | --------------------------------------------------------------------------------- 22 | INFO: [Synth 8-638] synthesizing module 'Traffic_Light_Controller' [D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v:23] 23 | Parameter S1 bound to: 0 - type: integer 24 | Parameter S2 bound to: 1 - type: integer 25 | Parameter S3 bound to: 2 - type: integer 26 | Parameter S4 bound to: 3 - type: integer 27 | Parameter S5 bound to: 4 - type: integer 28 | Parameter S6 bound to: 5 - type: integer 29 | Parameter sec7 bound to: 7 - type: integer 30 | Parameter sec5 bound to: 5 - type: integer 31 | Parameter sec2 bound to: 2 - type: integer 32 | Parameter sec3 bound to: 3 - type: integer 33 | INFO: [Synth 8-256] done synthesizing module 'Traffic_Light_Controller' (1#1) [D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v:23] 34 | --------------------------------------------------------------------------------- 35 | Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 438.992 ; gain = 149.699 36 | --------------------------------------------------------------------------------- 37 | 38 | Report Check Netlist: 39 | +------+------------------+-------+---------+-------+------------------+ 40 | | |Item |Errors |Warnings |Status |Description | 41 | +------+------------------+-------+---------+-------+------------------+ 42 | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 43 | +------+------------------+-------+---------+-------+------------------+ 44 | --------------------------------------------------------------------------------- 45 | Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 438.992 ; gain = 149.699 46 | --------------------------------------------------------------------------------- 47 | INFO: [Device 21-403] Loading part xc7a100tcsg324-1 48 | INFO: [Project 1-570] Preparing netlist for logic optimization 49 | 50 | Processing XDC Constraints 51 | Initializing timing engine 52 | Parsing XDC File [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc] 53 | Finished Parsing XDC File [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc] 54 | INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Traffic_Light_Controller_propImpl.xdc]. 55 | Resolution: To avoid this warning, move constraints listed in [.Xil/Traffic_Light_Controller_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. 56 | Completed Processing XDC Constraints 57 | 58 | INFO: [Project 1-111] Unisim Transformation Summary: 59 | No Unisim elements were transformed. 60 | 61 | Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 765.352 ; gain = 0.000 62 | --------------------------------------------------------------------------------- 63 | Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 64 | --------------------------------------------------------------------------------- 65 | --------------------------------------------------------------------------------- 66 | Start Loading Part and Timing Information 67 | --------------------------------------------------------------------------------- 68 | Loading part: xc7a100tcsg324-1 69 | --------------------------------------------------------------------------------- 70 | Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 71 | --------------------------------------------------------------------------------- 72 | --------------------------------------------------------------------------------- 73 | Start Applying 'set_property' XDC Constraints 74 | --------------------------------------------------------------------------------- 75 | --------------------------------------------------------------------------------- 76 | Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 77 | --------------------------------------------------------------------------------- 78 | INFO: [Synth 8-802] inferred FSM for state register 'ps_reg' in module 'Traffic_Light_Controller' 79 | INFO: [Synth 8-5544] ROM "count" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 80 | INFO: [Synth 8-5544] ROM "light_M2" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 81 | INFO: [Synth 8-5544] ROM "light_MT" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 82 | INFO: [Synth 8-5544] ROM "light_S" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 83 | INFO: [Synth 8-5544] ROM "light_M1" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 84 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 85 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 86 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 87 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 88 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 89 | --------------------------------------------------------------------------------------------------- 90 | State | New Encoding | Previous Encoding 91 | --------------------------------------------------------------------------------------------------- 92 | S1 | 000 | 000 93 | S2 | 001 | 001 94 | S3 | 010 | 010 95 | S4 | 011 | 011 96 | S5 | 100 | 100 97 | S6 | 101 | 101 98 | --------------------------------------------------------------------------------------------------- 99 | INFO: [Synth 8-3354] encoded FSM with state register 'ps_reg' using encoding 'sequential' in module 'Traffic_Light_Controller' 100 | --------------------------------------------------------------------------------- 101 | Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 102 | --------------------------------------------------------------------------------- 103 | 104 | Report RTL Partitions: 105 | +-+--------------+------------+----------+ 106 | | |RTL Partition |Replication |Instances | 107 | +-+--------------+------------+----------+ 108 | +-+--------------+------------+----------+ 109 | --------------------------------------------------------------------------------- 110 | Start RTL Component Statistics 111 | --------------------------------------------------------------------------------- 112 | Detailed RTL Component Info : 113 | +---Adders : 114 | 2 Input 4 Bit Adders := 1 115 | +---Registers : 116 | 4 Bit Registers := 1 117 | +---Muxes : 118 | 2 Input 4 Bit Muxes := 3 119 | 6 Input 4 Bit Muxes := 1 120 | 6 Input 3 Bit Muxes := 4 121 | 13 Input 3 Bit Muxes := 1 122 | 6 Input 1 Bit Muxes := 1 123 | --------------------------------------------------------------------------------- 124 | Finished RTL Component Statistics 125 | --------------------------------------------------------------------------------- 126 | --------------------------------------------------------------------------------- 127 | Start RTL Hierarchical Component Statistics 128 | --------------------------------------------------------------------------------- 129 | Hierarchical RTL Component report 130 | Module Traffic_Light_Controller 131 | Detailed RTL Component Info : 132 | +---Adders : 133 | 2 Input 4 Bit Adders := 1 134 | +---Registers : 135 | 4 Bit Registers := 1 136 | +---Muxes : 137 | 2 Input 4 Bit Muxes := 3 138 | 6 Input 4 Bit Muxes := 1 139 | 6 Input 3 Bit Muxes := 4 140 | 13 Input 3 Bit Muxes := 1 141 | 6 Input 1 Bit Muxes := 1 142 | --------------------------------------------------------------------------------- 143 | Finished RTL Hierarchical Component Statistics 144 | --------------------------------------------------------------------------------- 145 | --------------------------------------------------------------------------------- 146 | Start Part Resource Summary 147 | --------------------------------------------------------------------------------- 148 | Part Resources: 149 | DSPs: 240 (col length:80) 150 | BRAMs: 270 (col length: RAMB18 80 RAMB36 40) 151 | --------------------------------------------------------------------------------- 152 | Finished Part Resource Summary 153 | --------------------------------------------------------------------------------- 154 | --------------------------------------------------------------------------------- 155 | Start Cross Boundary and Area Optimization 156 | --------------------------------------------------------------------------------- 157 | WARNING: [Synth 8-3917] design Traffic_Light_Controller has port light_S[1] driven by constant 0 158 | --------------------------------------------------------------------------------- 159 | Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:31 . Memory (MB): peak = 765.352 ; gain = 476.059 160 | --------------------------------------------------------------------------------- 161 | 162 | Report RTL Partitions: 163 | +-+--------------+------------+----------+ 164 | | |RTL Partition |Replication |Instances | 165 | +-+--------------+------------+----------+ 166 | +-+--------------+------------+----------+ 167 | --------------------------------------------------------------------------------- 168 | Start Applying XDC Timing Constraints 169 | --------------------------------------------------------------------------------- 170 | --------------------------------------------------------------------------------- 171 | Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 776.684 ; gain = 487.391 172 | --------------------------------------------------------------------------------- 173 | --------------------------------------------------------------------------------- 174 | Start Timing Optimization 175 | --------------------------------------------------------------------------------- 176 | --------------------------------------------------------------------------------- 177 | Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 776.758 ; gain = 487.465 178 | --------------------------------------------------------------------------------- 179 | 180 | Report RTL Partitions: 181 | +-+--------------+------------+----------+ 182 | | |RTL Partition |Replication |Instances | 183 | +-+--------------+------------+----------+ 184 | +-+--------------+------------+----------+ 185 | --------------------------------------------------------------------------------- 186 | Start Technology Mapping 187 | --------------------------------------------------------------------------------- 188 | INFO: [Synth 8-3333] propagating constant 0 across sequential element (\count_reg[3] ) 189 | WARNING: [Synth 8-3332] Sequential element (count_reg[3]) is unused and will be removed from module Traffic_Light_Controller. 190 | --------------------------------------------------------------------------------- 191 | Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 796.324 ; gain = 507.031 192 | --------------------------------------------------------------------------------- 193 | 194 | Report RTL Partitions: 195 | +-+--------------+------------+----------+ 196 | | |RTL Partition |Replication |Instances | 197 | +-+--------------+------------+----------+ 198 | +-+--------------+------------+----------+ 199 | --------------------------------------------------------------------------------- 200 | Start IO Insertion 201 | --------------------------------------------------------------------------------- 202 | --------------------------------------------------------------------------------- 203 | Start Flattening Before IO Insertion 204 | --------------------------------------------------------------------------------- 205 | --------------------------------------------------------------------------------- 206 | Finished Flattening Before IO Insertion 207 | --------------------------------------------------------------------------------- 208 | --------------------------------------------------------------------------------- 209 | Start Final Netlist Cleanup 210 | --------------------------------------------------------------------------------- 211 | --------------------------------------------------------------------------------- 212 | Finished Final Netlist Cleanup 213 | --------------------------------------------------------------------------------- 214 | --------------------------------------------------------------------------------- 215 | Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 216 | --------------------------------------------------------------------------------- 217 | 218 | Report Check Netlist: 219 | +------+------------------+-------+---------+-------+------------------+ 220 | | |Item |Errors |Warnings |Status |Description | 221 | +------+------------------+-------+---------+-------+------------------+ 222 | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 223 | +------+------------------+-------+---------+-------+------------------+ 224 | --------------------------------------------------------------------------------- 225 | Start Renaming Generated Instances 226 | --------------------------------------------------------------------------------- 227 | --------------------------------------------------------------------------------- 228 | Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 229 | --------------------------------------------------------------------------------- 230 | 231 | Report RTL Partitions: 232 | +-+--------------+------------+----------+ 233 | | |RTL Partition |Replication |Instances | 234 | +-+--------------+------------+----------+ 235 | +-+--------------+------------+----------+ 236 | --------------------------------------------------------------------------------- 237 | Start Rebuilding User Hierarchy 238 | --------------------------------------------------------------------------------- 239 | --------------------------------------------------------------------------------- 240 | Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 241 | --------------------------------------------------------------------------------- 242 | --------------------------------------------------------------------------------- 243 | Start Renaming Generated Ports 244 | --------------------------------------------------------------------------------- 245 | --------------------------------------------------------------------------------- 246 | Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 247 | --------------------------------------------------------------------------------- 248 | --------------------------------------------------------------------------------- 249 | Start Handling Custom Attributes 250 | --------------------------------------------------------------------------------- 251 | --------------------------------------------------------------------------------- 252 | Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 253 | --------------------------------------------------------------------------------- 254 | --------------------------------------------------------------------------------- 255 | Start Renaming Generated Nets 256 | --------------------------------------------------------------------------------- 257 | --------------------------------------------------------------------------------- 258 | Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 259 | --------------------------------------------------------------------------------- 260 | --------------------------------------------------------------------------------- 261 | Start Writing Synthesis Report 262 | --------------------------------------------------------------------------------- 263 | 264 | Report BlackBoxes: 265 | +-+--------------+----------+ 266 | | |BlackBox name |Instances | 267 | +-+--------------+----------+ 268 | +-+--------------+----------+ 269 | 270 | Report Cell Usage: 271 | +------+------+------+ 272 | | |Cell |Count | 273 | +------+------+------+ 274 | |1 |BUFG | 1| 275 | |2 |LUT1 | 2| 276 | |3 |LUT2 | 3| 277 | |4 |LUT3 | 7| 278 | |5 |LUT4 | 3| 279 | |6 |LUT5 | 5| 280 | |7 |LUT6 | 1| 281 | |8 |MUXF7 | 3| 282 | |9 |FDCE | 6| 283 | |10 |IBUF | 2| 284 | |11 |OBUF | 12| 285 | +------+------+------+ 286 | 287 | Report Instance Areas: 288 | +------+---------+-------+------+ 289 | | |Instance |Module |Cells | 290 | +------+---------+-------+------+ 291 | |1 |top | | 45| 292 | +------+---------+-------+------+ 293 | --------------------------------------------------------------------------------- 294 | Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 295 | --------------------------------------------------------------------------------- 296 | Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. 297 | Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 796.324 ; gain = 180.672 298 | Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 299 | INFO: [Project 1-571] Translating synthesized netlist 300 | INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement 301 | INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds 302 | INFO: [Project 1-570] Preparing netlist for logic optimization 303 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 304 | INFO: [Project 1-111] Unisim Transformation Summary: 305 | No Unisim elements were transformed. 306 | 307 | INFO: [Common 17-83] Releasing license: Synthesis 308 | 27 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. 309 | synth_design completed successfully 310 | synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:49 . Memory (MB): peak = 798.723 ; gain = 521.980 311 | INFO: [Common 17-1381] The checkpoint 'D:/Xilinx_projects/arjun/arjun.runs/synth_1/Traffic_Light_Controller.dcp' has been generated. 312 | INFO: [runtcl-4] Executing : report_utilization -file Traffic_Light_Controller_utilization_synth.rpt -pb Traffic_Light_Controller_utilization_synth.pb 313 | report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.554 . Memory (MB): peak = 798.723 ; gain = 0.000 314 | INFO: [Common 17-206] Exiting Vivado at Fri Jul 17 12:44:14 2020... 315 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/Traffic_Light_Controller_utilization_synth.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.runs/synth_1/Traffic_Light_Controller_utilization_synth.pb -------------------------------------------------------------------------------- /arjun.runs/synth_1/Traffic_Light_Controller_utilization_synth.rpt: -------------------------------------------------------------------------------- 1 | Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 2 | ------------------------------------------------------------------------------------------------------------------------------------------- 3 | | Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017 4 | | Date : Fri Jul 17 12:44:13 2020 5 | | Host : LAPTOP-4TN0NJ6K running 64-bit major release (build 9200) 6 | | Command : report_utilization -file Traffic_Light_Controller_utilization_synth.rpt -pb Traffic_Light_Controller_utilization_synth.pb 7 | | Design : Traffic_Light_Controller 8 | | Device : 7a100tcsg324-1 9 | | Design State : Synthesized 10 | ------------------------------------------------------------------------------------------------------------------------------------------- 11 | 12 | Utilization Design Information 13 | 14 | Table of Contents 15 | ----------------- 16 | 1. Slice Logic 17 | 1.1 Summary of Registers by Type 18 | 2. Memory 19 | 3. DSP 20 | 4. IO and GT Specific 21 | 5. Clocking 22 | 6. Specific Feature 23 | 7. Primitives 24 | 8. Black Boxes 25 | 9. Instantiated Netlists 26 | 27 | 1. Slice Logic 28 | -------------- 29 | 30 | +-------------------------+------+-------+-----------+-------+ 31 | | Site Type | Used | Fixed | Available | Util% | 32 | +-------------------------+------+-------+-----------+-------+ 33 | | Slice LUTs* | 21 | 0 | 63400 | 0.03 | 34 | | LUT as Logic | 21 | 0 | 63400 | 0.03 | 35 | | LUT as Memory | 0 | 0 | 19000 | 0.00 | 36 | | Slice Registers | 6 | 0 | 126800 | <0.01 | 37 | | Register as Flip Flop | 6 | 0 | 126800 | <0.01 | 38 | | Register as Latch | 0 | 0 | 126800 | 0.00 | 39 | | F7 Muxes | 3 | 0 | 31700 | <0.01 | 40 | | F8 Muxes | 0 | 0 | 15850 | 0.00 | 41 | +-------------------------+------+-------+-----------+-------+ 42 | * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. 43 | 44 | 45 | 1.1 Summary of Registers by Type 46 | -------------------------------- 47 | 48 | +-------+--------------+-------------+--------------+ 49 | | Total | Clock Enable | Synchronous | Asynchronous | 50 | +-------+--------------+-------------+--------------+ 51 | | 0 | _ | - | - | 52 | | 0 | _ | - | Set | 53 | | 0 | _ | - | Reset | 54 | | 0 | _ | Set | - | 55 | | 0 | _ | Reset | - | 56 | | 0 | Yes | - | - | 57 | | 0 | Yes | - | Set | 58 | | 6 | Yes | - | Reset | 59 | | 0 | Yes | Set | - | 60 | | 0 | Yes | Reset | - | 61 | +-------+--------------+-------------+--------------+ 62 | 63 | 64 | 2. Memory 65 | --------- 66 | 67 | +----------------+------+-------+-----------+-------+ 68 | | Site Type | Used | Fixed | Available | Util% | 69 | +----------------+------+-------+-----------+-------+ 70 | | Block RAM Tile | 0 | 0 | 135 | 0.00 | 71 | | RAMB36/FIFO* | 0 | 0 | 135 | 0.00 | 72 | | RAMB18 | 0 | 0 | 270 | 0.00 | 73 | +----------------+------+-------+-----------+-------+ 74 | * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 75 | 76 | 77 | 3. DSP 78 | ------ 79 | 80 | +-----------+------+-------+-----------+-------+ 81 | | Site Type | Used | Fixed | Available | Util% | 82 | +-----------+------+-------+-----------+-------+ 83 | | DSPs | 0 | 0 | 240 | 0.00 | 84 | +-----------+------+-------+-----------+-------+ 85 | 86 | 87 | 4. IO and GT Specific 88 | --------------------- 89 | 90 | +-----------------------------+------+-------+-----------+-------+ 91 | | Site Type | Used | Fixed | Available | Util% | 92 | +-----------------------------+------+-------+-----------+-------+ 93 | | Bonded IOB | 14 | 0 | 210 | 6.67 | 94 | | Bonded IPADs | 0 | 0 | 2 | 0.00 | 95 | | PHY_CONTROL | 0 | 0 | 6 | 0.00 | 96 | | PHASER_REF | 0 | 0 | 6 | 0.00 | 97 | | OUT_FIFO | 0 | 0 | 24 | 0.00 | 98 | | IN_FIFO | 0 | 0 | 24 | 0.00 | 99 | | IDELAYCTRL | 0 | 0 | 6 | 0.00 | 100 | | IBUFDS | 0 | 0 | 202 | 0.00 | 101 | | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 24 | 0.00 | 102 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 24 | 0.00 | 103 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 300 | 0.00 | 104 | | ILOGIC | 0 | 0 | 210 | 0.00 | 105 | | OLOGIC | 0 | 0 | 210 | 0.00 | 106 | +-----------------------------+------+-------+-----------+-------+ 107 | 108 | 109 | 5. Clocking 110 | ----------- 111 | 112 | +------------+------+-------+-----------+-------+ 113 | | Site Type | Used | Fixed | Available | Util% | 114 | +------------+------+-------+-----------+-------+ 115 | | BUFGCTRL | 1 | 0 | 32 | 3.13 | 116 | | BUFIO | 0 | 0 | 24 | 0.00 | 117 | | MMCME2_ADV | 0 | 0 | 6 | 0.00 | 118 | | PLLE2_ADV | 0 | 0 | 6 | 0.00 | 119 | | BUFMRCE | 0 | 0 | 12 | 0.00 | 120 | | BUFHCE | 0 | 0 | 96 | 0.00 | 121 | | BUFR | 0 | 0 | 24 | 0.00 | 122 | +------------+------+-------+-----------+-------+ 123 | 124 | 125 | 6. Specific Feature 126 | ------------------- 127 | 128 | +-------------+------+-------+-----------+-------+ 129 | | Site Type | Used | Fixed | Available | Util% | 130 | +-------------+------+-------+-----------+-------+ 131 | | BSCANE2 | 0 | 0 | 4 | 0.00 | 132 | | CAPTUREE2 | 0 | 0 | 1 | 0.00 | 133 | | DNA_PORT | 0 | 0 | 1 | 0.00 | 134 | | EFUSE_USR | 0 | 0 | 1 | 0.00 | 135 | | FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | 136 | | ICAPE2 | 0 | 0 | 2 | 0.00 | 137 | | PCIE_2_1 | 0 | 0 | 1 | 0.00 | 138 | | STARTUPE2 | 0 | 0 | 1 | 0.00 | 139 | | XADC | 0 | 0 | 1 | 0.00 | 140 | +-------------+------+-------+-----------+-------+ 141 | 142 | 143 | 7. Primitives 144 | ------------- 145 | 146 | +----------+------+---------------------+ 147 | | Ref Name | Used | Functional Category | 148 | +----------+------+---------------------+ 149 | | OBUF | 12 | IO | 150 | | LUT3 | 7 | LUT | 151 | | FDCE | 6 | Flop & Latch | 152 | | LUT5 | 5 | LUT | 153 | | MUXF7 | 3 | MuxFx | 154 | | LUT4 | 3 | LUT | 155 | | LUT2 | 3 | LUT | 156 | | LUT1 | 2 | LUT | 157 | | IBUF | 2 | IO | 158 | | LUT6 | 1 | LUT | 159 | | BUFG | 1 | Clock | 160 | +----------+------+---------------------+ 161 | 162 | 163 | 8. Black Boxes 164 | -------------- 165 | 166 | +----------+------+ 167 | | Ref Name | Used | 168 | +----------+------+ 169 | 170 | 171 | 9. Instantiated Netlists 172 | ------------------------ 173 | 174 | +----------+------+ 175 | | Ref Name | Used | 176 | +----------+------+ 177 | 178 | 179 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/fsm_encoding.os: -------------------------------------------------------------------------------- 1 | 2 | add_fsm_encoding \ 3 | {Traffic_Light_Controller.ps} \ 4 | { } \ 5 | {{000 000} {001 001} {010 010} {011 011} {100 100} {101 101} } 6 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/gen_run.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 39 | 40 | 41 | 42 | Vivado Synthesis Defaults 43 | 44 | 45 | 46 | 47 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/htr.txt: -------------------------------------------------------------------------------- 1 | REM 2 | REM Vivado(TM) 3 | REM htr.txt: a Vivado-generated description of how-to-repeat the 4 | REM the basic steps of a run. Note that runme.bat/sh needs 5 | REM to be invoked for Vivado to track run status. 6 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 7 | REM 8 | 9 | vivado -log Traffic_Light_Controller.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl 10 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/project.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 4 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 5 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 6 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 7 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 8 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 9 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 11 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 12 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 13 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 14 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 15 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 16 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:3232:00:00 17 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 18 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 19 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 20 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 21 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 22 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 23 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 24 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 25 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 26 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 27 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 28 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 29 | 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 30 | 5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3137313037353435393265343432356461313132646632663937653439626330:506172656e742050412070726f6a656374204944:00 31 | eof:3387047098 32 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/rundef.js: -------------------------------------------------------------------------------- 1 | // 2 | // Vivado(TM) 3 | // rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 4 | // Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 5 | // 6 | 7 | var WshShell = new ActiveXObject( "WScript.Shell" ); 8 | var ProcEnv = WshShell.Environment( "Process" ); 9 | var PathVal = ProcEnv("PATH"); 10 | if ( PathVal.length == 0 ) { 11 | PathVal = "D:/Xilinx/SDK/2017.4/bin;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2017.4/bin;"; 12 | } else { 13 | PathVal = "D:/Xilinx/SDK/2017.4/bin;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64;D:/Xilinx/Vivado/2017.4/bin;" + PathVal; 14 | } 15 | 16 | ProcEnv("PATH") = PathVal; 17 | 18 | var RDScrFP = WScript.ScriptFullName; 19 | var RDScrN = WScript.ScriptName; 20 | var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); 21 | var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; 22 | eval( EAInclude(ISEJScriptLib) ); 23 | 24 | 25 | ISEStep( "vivado", 26 | "-log Traffic_Light_Controller.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl" ); 27 | 28 | 29 | 30 | function EAInclude( EAInclFilename ) { 31 | var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); 32 | var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); 33 | var EAIFContents = EAInclFile.ReadAll(); 34 | EAInclFile.Close(); 35 | return EAIFContents; 36 | } 37 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/runme.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Vivado (TM) 4 | rem runme.bat: a Vivado-generated Script 5 | rem Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 6 | 7 | 8 | set HD_SDIR=%~dp0 9 | cd /d "%HD_SDIR%" 10 | cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* 11 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/runme.log: -------------------------------------------------------------------------------- 1 | 2 | *** Running vivado 3 | with args -log Traffic_Light_Controller.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl 4 | 5 | 6 | ****** Vivado v2017.4 (64-bit) 7 | **** SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 8 | **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 9 | ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 10 | 11 | source Traffic_Light_Controller.tcl -notrace 12 | Command: synth_design -top Traffic_Light_Controller -part xc7a100tcsg324-1 13 | Starting synth_design 14 | Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' 15 | INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' 16 | INFO: Launching helper process for spawning children vivado processes 17 | INFO: Helper process launched with PID 10896 18 | --------------------------------------------------------------------------------- 19 | Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:07 . Memory (MB): peak = 387.195 ; gain = 97.902 20 | --------------------------------------------------------------------------------- 21 | INFO: [Synth 8-638] synthesizing module 'Traffic_Light_Controller' [D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v:23] 22 | Parameter S1 bound to: 0 - type: integer 23 | Parameter S2 bound to: 1 - type: integer 24 | Parameter S3 bound to: 2 - type: integer 25 | Parameter S4 bound to: 3 - type: integer 26 | Parameter S5 bound to: 4 - type: integer 27 | Parameter S6 bound to: 5 - type: integer 28 | Parameter sec7 bound to: 7 - type: integer 29 | Parameter sec5 bound to: 5 - type: integer 30 | Parameter sec2 bound to: 2 - type: integer 31 | Parameter sec3 bound to: 3 - type: integer 32 | INFO: [Synth 8-256] done synthesizing module 'Traffic_Light_Controller' (1#1) [D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v:23] 33 | --------------------------------------------------------------------------------- 34 | Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 438.992 ; gain = 149.699 35 | --------------------------------------------------------------------------------- 36 | 37 | Report Check Netlist: 38 | +------+------------------+-------+---------+-------+------------------+ 39 | | |Item |Errors |Warnings |Status |Description | 40 | +------+------------------+-------+---------+-------+------------------+ 41 | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 42 | +------+------------------+-------+---------+-------+------------------+ 43 | --------------------------------------------------------------------------------- 44 | Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:10 . Memory (MB): peak = 438.992 ; gain = 149.699 45 | --------------------------------------------------------------------------------- 46 | INFO: [Device 21-403] Loading part xc7a100tcsg324-1 47 | INFO: [Project 1-570] Preparing netlist for logic optimization 48 | 49 | Processing XDC Constraints 50 | Initializing timing engine 51 | Parsing XDC File [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc] 52 | Finished Parsing XDC File [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc] 53 | INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Xilinx_projects/arjun/arjun.srcs/constrs_1/new/abd.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/Traffic_Light_Controller_propImpl.xdc]. 54 | Resolution: To avoid this warning, move constraints listed in [.Xil/Traffic_Light_Controller_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. 55 | Completed Processing XDC Constraints 56 | 57 | INFO: [Project 1-111] Unisim Transformation Summary: 58 | No Unisim elements were transformed. 59 | 60 | Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 765.352 ; gain = 0.000 61 | --------------------------------------------------------------------------------- 62 | Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 63 | --------------------------------------------------------------------------------- 64 | --------------------------------------------------------------------------------- 65 | Start Loading Part and Timing Information 66 | --------------------------------------------------------------------------------- 67 | Loading part: xc7a100tcsg324-1 68 | --------------------------------------------------------------------------------- 69 | Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 70 | --------------------------------------------------------------------------------- 71 | --------------------------------------------------------------------------------- 72 | Start Applying 'set_property' XDC Constraints 73 | --------------------------------------------------------------------------------- 74 | --------------------------------------------------------------------------------- 75 | Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 76 | --------------------------------------------------------------------------------- 77 | INFO: [Synth 8-802] inferred FSM for state register 'ps_reg' in module 'Traffic_Light_Controller' 78 | INFO: [Synth 8-5544] ROM "count" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 79 | INFO: [Synth 8-5544] ROM "light_M2" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 80 | INFO: [Synth 8-5544] ROM "light_MT" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 81 | INFO: [Synth 8-5544] ROM "light_S" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 82 | INFO: [Synth 8-5544] ROM "light_M1" won't be mapped to Block RAM because address size (3) smaller than threshold (5) 83 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 84 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 85 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 86 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 87 | INFO: [Synth 8-5544] ROM "ps" won't be mapped to Block RAM because address size (1) smaller than threshold (5) 88 | --------------------------------------------------------------------------------------------------- 89 | State | New Encoding | Previous Encoding 90 | --------------------------------------------------------------------------------------------------- 91 | S1 | 000 | 000 92 | S2 | 001 | 001 93 | S3 | 010 | 010 94 | S4 | 011 | 011 95 | S5 | 100 | 100 96 | S6 | 101 | 101 97 | --------------------------------------------------------------------------------------------------- 98 | INFO: [Synth 8-3354] encoded FSM with state register 'ps_reg' using encoding 'sequential' in module 'Traffic_Light_Controller' 99 | --------------------------------------------------------------------------------- 100 | Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:30 . Memory (MB): peak = 765.352 ; gain = 476.059 101 | --------------------------------------------------------------------------------- 102 | 103 | Report RTL Partitions: 104 | +-+--------------+------------+----------+ 105 | | |RTL Partition |Replication |Instances | 106 | +-+--------------+------------+----------+ 107 | +-+--------------+------------+----------+ 108 | --------------------------------------------------------------------------------- 109 | Start RTL Component Statistics 110 | --------------------------------------------------------------------------------- 111 | Detailed RTL Component Info : 112 | +---Adders : 113 | 2 Input 4 Bit Adders := 1 114 | +---Registers : 115 | 4 Bit Registers := 1 116 | +---Muxes : 117 | 2 Input 4 Bit Muxes := 3 118 | 6 Input 4 Bit Muxes := 1 119 | 6 Input 3 Bit Muxes := 4 120 | 13 Input 3 Bit Muxes := 1 121 | 6 Input 1 Bit Muxes := 1 122 | --------------------------------------------------------------------------------- 123 | Finished RTL Component Statistics 124 | --------------------------------------------------------------------------------- 125 | --------------------------------------------------------------------------------- 126 | Start RTL Hierarchical Component Statistics 127 | --------------------------------------------------------------------------------- 128 | Hierarchical RTL Component report 129 | Module Traffic_Light_Controller 130 | Detailed RTL Component Info : 131 | +---Adders : 132 | 2 Input 4 Bit Adders := 1 133 | +---Registers : 134 | 4 Bit Registers := 1 135 | +---Muxes : 136 | 2 Input 4 Bit Muxes := 3 137 | 6 Input 4 Bit Muxes := 1 138 | 6 Input 3 Bit Muxes := 4 139 | 13 Input 3 Bit Muxes := 1 140 | 6 Input 1 Bit Muxes := 1 141 | --------------------------------------------------------------------------------- 142 | Finished RTL Hierarchical Component Statistics 143 | --------------------------------------------------------------------------------- 144 | --------------------------------------------------------------------------------- 145 | Start Part Resource Summary 146 | --------------------------------------------------------------------------------- 147 | Part Resources: 148 | DSPs: 240 (col length:80) 149 | BRAMs: 270 (col length: RAMB18 80 RAMB36 40) 150 | --------------------------------------------------------------------------------- 151 | Finished Part Resource Summary 152 | --------------------------------------------------------------------------------- 153 | --------------------------------------------------------------------------------- 154 | Start Cross Boundary and Area Optimization 155 | --------------------------------------------------------------------------------- 156 | WARNING: [Synth 8-3917] design Traffic_Light_Controller has port light_S[1] driven by constant 0 157 | --------------------------------------------------------------------------------- 158 | Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:31 . Memory (MB): peak = 765.352 ; gain = 476.059 159 | --------------------------------------------------------------------------------- 160 | 161 | Report RTL Partitions: 162 | +-+--------------+------------+----------+ 163 | | |RTL Partition |Replication |Instances | 164 | +-+--------------+------------+----------+ 165 | +-+--------------+------------+----------+ 166 | --------------------------------------------------------------------------------- 167 | Start Applying XDC Timing Constraints 168 | --------------------------------------------------------------------------------- 169 | --------------------------------------------------------------------------------- 170 | Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 776.684 ; gain = 487.391 171 | --------------------------------------------------------------------------------- 172 | --------------------------------------------------------------------------------- 173 | Start Timing Optimization 174 | --------------------------------------------------------------------------------- 175 | --------------------------------------------------------------------------------- 176 | Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 776.758 ; gain = 487.465 177 | --------------------------------------------------------------------------------- 178 | 179 | Report RTL Partitions: 180 | +-+--------------+------------+----------+ 181 | | |RTL Partition |Replication |Instances | 182 | +-+--------------+------------+----------+ 183 | +-+--------------+------------+----------+ 184 | --------------------------------------------------------------------------------- 185 | Start Technology Mapping 186 | --------------------------------------------------------------------------------- 187 | INFO: [Synth 8-3333] propagating constant 0 across sequential element (\count_reg[3] ) 188 | WARNING: [Synth 8-3332] Sequential element (count_reg[3]) is unused and will be removed from module Traffic_Light_Controller. 189 | --------------------------------------------------------------------------------- 190 | Finished Technology Mapping : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 796.324 ; gain = 507.031 191 | --------------------------------------------------------------------------------- 192 | 193 | Report RTL Partitions: 194 | +-+--------------+------------+----------+ 195 | | |RTL Partition |Replication |Instances | 196 | +-+--------------+------------+----------+ 197 | +-+--------------+------------+----------+ 198 | --------------------------------------------------------------------------------- 199 | Start IO Insertion 200 | --------------------------------------------------------------------------------- 201 | --------------------------------------------------------------------------------- 202 | Start Flattening Before IO Insertion 203 | --------------------------------------------------------------------------------- 204 | --------------------------------------------------------------------------------- 205 | Finished Flattening Before IO Insertion 206 | --------------------------------------------------------------------------------- 207 | --------------------------------------------------------------------------------- 208 | Start Final Netlist Cleanup 209 | --------------------------------------------------------------------------------- 210 | --------------------------------------------------------------------------------- 211 | Finished Final Netlist Cleanup 212 | --------------------------------------------------------------------------------- 213 | --------------------------------------------------------------------------------- 214 | Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 215 | --------------------------------------------------------------------------------- 216 | 217 | Report Check Netlist: 218 | +------+------------------+-------+---------+-------+------------------+ 219 | | |Item |Errors |Warnings |Status |Description | 220 | +------+------------------+-------+---------+-------+------------------+ 221 | |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 222 | +------+------------------+-------+---------+-------+------------------+ 223 | --------------------------------------------------------------------------------- 224 | Start Renaming Generated Instances 225 | --------------------------------------------------------------------------------- 226 | --------------------------------------------------------------------------------- 227 | Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 228 | --------------------------------------------------------------------------------- 229 | 230 | Report RTL Partitions: 231 | +-+--------------+------------+----------+ 232 | | |RTL Partition |Replication |Instances | 233 | +-+--------------+------------+----------+ 234 | +-+--------------+------------+----------+ 235 | --------------------------------------------------------------------------------- 236 | Start Rebuilding User Hierarchy 237 | --------------------------------------------------------------------------------- 238 | --------------------------------------------------------------------------------- 239 | Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 240 | --------------------------------------------------------------------------------- 241 | --------------------------------------------------------------------------------- 242 | Start Renaming Generated Ports 243 | --------------------------------------------------------------------------------- 244 | --------------------------------------------------------------------------------- 245 | Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 246 | --------------------------------------------------------------------------------- 247 | --------------------------------------------------------------------------------- 248 | Start Handling Custom Attributes 249 | --------------------------------------------------------------------------------- 250 | --------------------------------------------------------------------------------- 251 | Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 252 | --------------------------------------------------------------------------------- 253 | --------------------------------------------------------------------------------- 254 | Start Renaming Generated Nets 255 | --------------------------------------------------------------------------------- 256 | --------------------------------------------------------------------------------- 257 | Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 258 | --------------------------------------------------------------------------------- 259 | --------------------------------------------------------------------------------- 260 | Start Writing Synthesis Report 261 | --------------------------------------------------------------------------------- 262 | 263 | Report BlackBoxes: 264 | +-+--------------+----------+ 265 | | |BlackBox name |Instances | 266 | +-+--------------+----------+ 267 | +-+--------------+----------+ 268 | 269 | Report Cell Usage: 270 | +------+------+------+ 271 | | |Cell |Count | 272 | +------+------+------+ 273 | |1 |BUFG | 1| 274 | |2 |LUT1 | 2| 275 | |3 |LUT2 | 3| 276 | |4 |LUT3 | 7| 277 | |5 |LUT4 | 3| 278 | |6 |LUT5 | 5| 279 | |7 |LUT6 | 1| 280 | |8 |MUXF7 | 3| 281 | |9 |FDCE | 6| 282 | |10 |IBUF | 2| 283 | |11 |OBUF | 12| 284 | +------+------+------+ 285 | 286 | Report Instance Areas: 287 | +------+---------+-------+------+ 288 | | |Instance |Module |Cells | 289 | +------+---------+-------+------+ 290 | |1 |top | | 45| 291 | +------+---------+-------+------+ 292 | --------------------------------------------------------------------------------- 293 | Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 294 | --------------------------------------------------------------------------------- 295 | Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. 296 | Synthesis Optimization Runtime : Time (s): cpu = 00:00:15 ; elapsed = 00:00:27 . Memory (MB): peak = 796.324 ; gain = 180.672 297 | Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 796.324 ; gain = 507.031 298 | INFO: [Project 1-571] Translating synthesized netlist 299 | INFO: [Netlist 29-17] Analyzing 5 Unisim elements for replacement 300 | INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds 301 | INFO: [Project 1-570] Preparing netlist for logic optimization 302 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). 303 | INFO: [Project 1-111] Unisim Transformation Summary: 304 | No Unisim elements were transformed. 305 | 306 | INFO: [Common 17-83] Releasing license: Synthesis 307 | 27 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. 308 | synth_design completed successfully 309 | synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:49 . Memory (MB): peak = 798.723 ; gain = 521.980 310 | INFO: [Common 17-1381] The checkpoint 'D:/Xilinx_projects/arjun/arjun.runs/synth_1/Traffic_Light_Controller.dcp' has been generated. 311 | INFO: [runtcl-4] Executing : report_utilization -file Traffic_Light_Controller_utilization_synth.rpt -pb Traffic_Light_Controller_utilization_synth.pb 312 | report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.554 . Memory (MB): peak = 798.723 ; gain = 0.000 313 | INFO: [Common 17-206] Exiting Vivado at Fri Jul 17 12:44:14 2020... 314 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/runme.sh: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | # 4 | # Vivado(TM) 5 | # runme.sh: a Vivado-generated Runs Script for UNIX 6 | # Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 7 | # 8 | 9 | echo "This script was generated under a different operating system." 10 | echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" 11 | exit 12 | 13 | if [ -z "$PATH" ]; then 14 | PATH=D:/Xilinx/SDK/2017.4/bin;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2017.4/bin 15 | else 16 | PATH=D:/Xilinx/SDK/2017.4/bin;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/bin/nt64;D:/Xilinx/Vivado/2017.4/ids_lite/ISE/lib/nt64:D:/Xilinx/Vivado/2017.4/bin:$PATH 17 | fi 18 | export PATH 19 | 20 | if [ -z "$LD_LIBRARY_PATH" ]; then 21 | LD_LIBRARY_PATH= 22 | else 23 | LD_LIBRARY_PATH=:$LD_LIBRARY_PATH 24 | fi 25 | export LD_LIBRARY_PATH 26 | 27 | HD_PWD='D:/Xilinx_projects/arjun/arjun.runs/synth_1' 28 | cd "$HD_PWD" 29 | 30 | HD_LOG=runme.log 31 | /bin/touch $HD_LOG 32 | 33 | ISEStep="./ISEWrap.sh" 34 | EAStep() 35 | { 36 | $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 37 | if [ $? -ne 0 ] 38 | then 39 | exit 40 | fi 41 | } 42 | 43 | EAStep vivado -log Traffic_Light_Controller.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl 44 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/vivado.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Vivado v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 12:43:06 2020 6 | # Process ID: 11168 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.runs/synth_1 8 | # Command line: vivado.exe -log Traffic_Light_Controller.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source Traffic_Light_Controller.tcl 9 | # Log file: D:/Xilinx_projects/arjun/arjun.runs/synth_1/Traffic_Light_Controller.vds 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.runs/synth_1\vivado.jou 11 | #----------------------------------------------------------- 12 | source Traffic_Light_Controller.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.runs/synth_1/vivado.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.runs/synth_1/vivado.pb -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_TB.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_TB_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_TB_behav.wdb -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_TB_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../arjun.srcs/sources_1/new/Traffic_Light_Controller.v" \ 4 | "../../../../arjun.srcs/sim_1/new/Traffic_Light_Controller_TB.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_defaultlib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_behav.wdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_behav.wdb -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/Traffic_Light_Controller_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../arjun.srcs/sources_1/new/Traffic_Light_Controller.v" \ 4 | 5 | # compile glbl module 6 | verilog xil_defaultlib "glbl.v" 7 | 8 | # Do not sort compile order 9 | nosort 10 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2017.4 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Fri Jul 17 01:43:29 +0530 2020 10 | REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 11 | REM 12 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | echo "xvlog --incr --relax -prj Traffic_Light_Controller_TB_vlog.prj" 18 | call xvlog --incr --relax -prj Traffic_Light_Controller_TB_vlog.prj -log xvlog.log 19 | call type xvlog.log > compile.log 20 | if "%errorlevel%"=="1" goto END 21 | if "%errorlevel%"=="0" goto SUCCESS 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/compile.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_projects/arjun/arjun.srcs/sources_1/new/Traffic_Light_Controller.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module Traffic_Light_Controller 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "D:/Xilinx_projects/arjun/arjun.srcs/sim_1/new/Traffic_Light_Controller_TB.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module Traffic_Light_Controller_TB 5 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2017.4 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Fri Jul 17 01:43:30 +0530 2020 10 | REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 11 | REM 12 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | call xelab -wto 1710754592e4425da112df2f97e49bc0 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Traffic_Light_Controller_TB_behav xil_defaultlib.Traffic_Light_Controller_TB xil_defaultlib.glbl -log elaborate.log 18 | if "%errorlevel%"=="0" goto SUCCESS 19 | if "%errorlevel%"=="1" goto END 20 | :END 21 | exit 1 22 | :SUCCESS 23 | exit 0 24 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2017.4 2 | Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. 3 | Running: D:/Xilinx/Vivado/2017.4/bin/unwrapped/win64.o/xelab.exe -wto 1710754592e4425da112df2f97e49bc0 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Traffic_Light_Controller_TB_behav xil_defaultlib.Traffic_Light_Controller_TB xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Completed static elaboration 7 | Starting simulation data flow analysis 8 | Completed simulation data flow analysis 9 | Time Resolution for simulation is 1ps 10 | Compiling module xil_defaultlib.Traffic_Light_Controller 11 | Compiling module xil_defaultlib.Traffic_Light_Controller_TB 12 | WARNING: [XSIM 43-3368] "D:/Xilinx_projects/arjun/arjun.srcs/sim_1/new/Traffic_Light_Controller_TB.v" Line 43. Negative delay (-1863462912000.000000) treated as 0. 13 | Compiling module xil_defaultlib.glbl 14 | Built simulation snapshot Traffic_Light_Controller_TB_behav 15 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | 11 | //-------- STARTUP Globals -------------- 12 | wire GSR; 13 | wire GTS; 14 | wire GWE; 15 | wire PRLD; 16 | tri1 p_up_tmp; 17 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 18 | 19 | wire PROGB_GLBL; 20 | wire CCLKO_GLBL; 21 | wire FCSBO_GLBL; 22 | wire [3:0] DO_GLBL; 23 | wire [3:0] DI_GLBL; 24 | 25 | reg GSR_int; 26 | reg GTS_int; 27 | reg PRLD_int; 28 | 29 | //-------- JTAG Globals -------------- 30 | wire JTAG_TDO_GLBL; 31 | wire JTAG_TCK_GLBL; 32 | wire JTAG_TDI_GLBL; 33 | wire JTAG_TMS_GLBL; 34 | wire JTAG_TRST_GLBL; 35 | 36 | reg JTAG_CAPTURE_GLBL; 37 | reg JTAG_RESET_GLBL; 38 | reg JTAG_SHIFT_GLBL; 39 | reg JTAG_UPDATE_GLBL; 40 | reg JTAG_RUNTEST_GLBL; 41 | 42 | reg JTAG_SEL1_GLBL = 0; 43 | reg JTAG_SEL2_GLBL = 0 ; 44 | reg JTAG_SEL3_GLBL = 0; 45 | reg JTAG_SEL4_GLBL = 0; 46 | 47 | reg JTAG_USER_TDO1_GLBL = 1'bz; 48 | reg JTAG_USER_TDO2_GLBL = 1'bz; 49 | reg JTAG_USER_TDO3_GLBL = 1'bz; 50 | reg JTAG_USER_TDO4_GLBL = 1'bz; 51 | 52 | assign (strong1, weak0) GSR = GSR_int; 53 | assign (strong1, weak0) GTS = GTS_int; 54 | assign (weak1, weak0) PRLD = PRLD_int; 55 | 56 | initial begin 57 | GSR_int = 1'b1; 58 | PRLD_int = 1'b1; 59 | #(ROC_WIDTH) 60 | GSR_int = 1'b0; 61 | PRLD_int = 1'b0; 62 | end 63 | 64 | initial begin 65 | GTS_int = 1'b1; 66 | #(TOC_WIDTH) 67 | GTS_int = 1'b0; 68 | end 69 | 70 | endmodule 71 | `endif 72 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2017.4 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Fri Jul 17 01:43:33 +0530 2020 10 | REM SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 11 | REM 12 | REM Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | call xsim Traffic_Light_Controller_TB_behav -key {Behavioral:sim_1:Functional:Traffic_Light_Controller_TB} -tclbatch Traffic_Light_Controller_TB.tcl -log simulate.log 18 | if "%errorlevel%"=="0" goto SUCCESS 19 | if "%errorlevel%"=="1" goto END 20 | :END 21 | exit 1 22 | :SUCCESS 23 | exit 0 24 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2017.4 2 | Time resolution is 1 ps 3 | $finish called at time : 2 s : File "D:/Xilinx_projects/arjun/arjun.srcs/sim_1/new/Traffic_Light_Controller_TB.v" Line 44 4 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Sat Jul 18 08:36:47 2020 6 | # Process ID: 11392 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Sat Jul 18 08:36:47 2020 6 | # Process ID: 11392 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Sat Jul 18 08:36:48 2020... 14 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_1628.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 00:09:12 2020 6 | # Process ID: 1628 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_1628.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 00:09:12 2020 6 | # Process ID: 1628 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri Jul 17 00:09:13 2020... 14 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_16716.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Thu Jul 16 13:23:14 2020 6 | # Process ID: 16716 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_16716.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Thu Jul 16 13:23:14 2020 6 | # Process ID: 16716 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Thu Jul 16 13:23:15 2020... 14 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_20208.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 00:10:44 2020 6 | # Process ID: 20208 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_20208.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Fri Jul 17 00:10:44 2020 6 | # Process ID: 20208 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_TB_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Fri Jul 17 00:10:45 2020... 14 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_8304.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Thu Jul 16 12:54:20 2020 6 | # Process ID: 8304 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 13 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/webtalk_8304.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2017.4 (64-bit) 3 | # SW Build 2086221 on Fri Dec 15 20:55:39 MST 2017 4 | # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 5 | # Start of session at: Thu Jul 16 12:54:20 2020 6 | # Process ID: 8304 7 | # Current directory: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl -notrace 13 | INFO: [Common 17-206] Exiting Webtalk at Thu Jul 16 12:54:22 2020... 14 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "1710754592e4425da112df2f97e49bc0" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "Traffic_Light_Controller_behav" "xil_defaultlib.Traffic_Light_Controller" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | 14 | #include "iki.h" 15 | #include 16 | #include 17 | #ifdef __GNUC__ 18 | #include 19 | #else 20 | #include 21 | #define alloca _alloca 22 | #endif 23 | /**********************************************************************/ 24 | /* ____ ____ */ 25 | /* / /\/ / */ 26 | /* /___/ \ / */ 27 | /* \ \ \/ */ 28 | /* \ \ Copyright (c) 2003-2013 Xilinx, Inc. */ 29 | /* / / All Right Reserved. */ 30 | /* /---/ /\ */ 31 | /* \ \ / \ */ 32 | /* \___\/\___\ */ 33 | /**********************************************************************/ 34 | 35 | 36 | #include "iki.h" 37 | #include 38 | #include 39 | #ifdef __GNUC__ 40 | #include 41 | #else 42 | #include 43 | #define alloca _alloca 44 | #endif 45 | typedef void (*funcp)(char *, char *); 46 | extern int main(int, char**); 47 | extern void execute_2(char*, char *); 48 | extern void execute_3(char*, char *); 49 | extern void execute_5(char*, char *); 50 | extern void execute_6(char*, char *); 51 | extern void execute_7(char*, char *); 52 | extern void execute_8(char*, char *); 53 | extern void execute_9(char*, char *); 54 | extern void execute_10(char*, char *); 55 | extern void execute_11(char*, char *); 56 | extern void execute_12(char*, char *); 57 | extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 58 | funcp funcTab[11] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)vlog_transfunc_eventcallback}; 59 | const int NumRelocateId= 11; 60 | 61 | void relocate(char *dp) 62 | { 63 | iki_relocate(dp, "xsim.dir/Traffic_Light_Controller_behav/xsim.reloc", (void **)funcTab, 11); 64 | 65 | /*Populate the transaction function pointer field in the whole net structure */ 66 | } 67 | 68 | void sensitize(char *dp) 69 | { 70 | iki_sensitize(dp, "xsim.dir/Traffic_Light_Controller_behav/xsim.reloc"); 71 | } 72 | 73 | void simulate(char *dp) 74 | { 75 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/Traffic_Light_Controller_behav/xsim.reloc"); 76 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 77 | iki_execute_processes(); 78 | 79 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 80 | // Schedule transaction functions for the singly driven Verilog nets that have strength 81 | 82 | } 83 | #include "iki_bridge.h" 84 | void relocate(char *); 85 | 86 | void sensitize(char *); 87 | 88 | void simulate(char *); 89 | 90 | int main(int argc, char **argv) 91 | { 92 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 93 | iki_set_sv_type_file_path_name("xsim.dir/Traffic_Light_Controller_behav/xsim.svtype"); 94 | iki_set_crvs_dump_file_path_name("xsim.dir/Traffic_Light_Controller_behav/xsim.crvsdump"); 95 | void* design_handle = iki_create_design("xsim.dir/Traffic_Light_Controller_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, 0, isimBridge_getWdbWriter(), 0, argc, argv); 96 | iki_set_rc_trial_count(100); 97 | (void) design_handle; 98 | return iki_simulate_design(); 99 | } 100 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/obj/xsim_1.win64.obj -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.html: -------------------------------------------------------------------------------- 1 | Device Usage Statistics Report 2 |

XSIM Usage Report


3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
software_version_and_target_device
betaFALSEbuild_version2086221
date_generatedThu Jul 16 13:23:13 2020os_platformWIN64
product_versionXSIM v2017.4 (64-bit)project_id1710754592e4425da112df2f97e49bc0
project_iteration2random_id17779454-d7a0-4951-828b-1a8b9c87ef39
registration_id211978392_0_0_327route_designFALSE
target_devicenot_applicabletarget_familynot_applicable
target_packagenot_applicabletarget_speednot_applicable
tool_flowxsim_vivado

21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 |
user_environment
cpu_nameIntel(R) Core(TM) i5-8300H CPU @ 2.30GHzcpu_speed2304 MHz
os_nameMicrosoft Windows 8 or later , 64-bitos_releasemajor release (build 9200)
system_ram8.000 GBtotal_processors1

30 | 31 | 32 |
vivado_usage

33 | 34 | 35 | 41 | 51 |
xsim
36 | 37 | 38 | 39 |
command_line_options
command=xsim
40 |
42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 |
usage
iteration=1runtime=100 nssimulation_memory=10232_KBsimulation_time=0.17_sec
trace_waveform=true
50 |

52 | 53 | 54 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.wdm: -------------------------------------------------------------------------------- 1 | version = "1.0"; 2 | clients = 3 | ( 4 | { client_name = "project"; 5 | rules = ( 6 | { 7 | context="software_version_and_target_device"; 8 | xml_map="software_version_and_target_device"; 9 | html_map="software_version_and_target_device"; 10 | html_format="UserEnvStyle"; 11 | }, 12 | { 13 | context="user_environment"; 14 | xml_map="user_environment"; 15 | html_map="user_environment"; 16 | html_format="UserEnvStyle"; 17 | } 18 | ); 19 | }, 20 | 21 | { client_name = "xsim"; 22 | rules = ( 23 | { 24 | context="xsim\\command_line_options"; 25 | xml_map="xsim\\command_line_options"; 26 | html_map="xsim\\command_line_options"; 27 | html_format="UnisimStatsStyle"; 28 | }, 29 | { 30 | context="xsim\\usage"; 31 | xml_map="xsim\\usage"; 32 | html_map="xsim\\usage"; 33 | html_format="UnisimStatsStyle"; 34 | } 35 | ); 36 | } 37 | ); 38 | 39 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 |
4 |
5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 |
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22 | 23 | 24 | 25 | 26 | 27 | 28 |
29 |
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35 |
36 | 37 | 38 | 39 | 40 | 41 |
42 |
43 |
44 | 45 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Fri Jul 17 00:07:34 2020" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2017.4 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "2086221" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "211978392_0_0_327" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "17779454-d7a0-4951-828b-1a8b9c87ef39" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "1710754592e4425da112df2f97e49bc0" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "27" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Microsoft Windows 8 or later , 64-bit" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "Intel(R) Core(TM) i5-8300H CPU @ 2.30GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "2304 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "8.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "200 ps" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "1" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.09_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "7116_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 2414319453 -regid "211978392_0_0_327" -xml D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.xml -html D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.html -wdm D:/Xilinx_projects/arjun/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.dbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.dbg -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.mem: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.mem -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.reloc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.reloc -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 2127833895890005499 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 1710754592e4425da112df2f97e49bc0 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot Traffic_Light_Controller_behav xil_defaultlib.Traffic_Light_Controller xil_defaultlib.glbl" , 6 | buildDate : "Dec 15 2017" , 7 | buildTime : "21:07:18" , 8 | linkCmd : "D:\\Xilinx\\Vivado\\2017.4\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/Traffic_Light_Controller_behav/xsimk.exe\" \"xsim.dir/Traffic_Light_Controller_behav/obj/xsim_0.win64.obj\" \"xsim.dir/Traffic_Light_Controller_behav/obj/xsim_1.win64.obj\" \"D:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simulator_kernel.dll\" \"D:\\Xilinx\\Vivado\\2017.4\\lib\\win64.o\\\\librdi_simbridge_kernel.dll\"" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.rtti: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.rtti -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.svtype: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.svtype -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.type: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.xdbg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/arjun.sim/sim_1/behav/xsim/xsim.dir/Traffic_Light_Controller_behav/xsim.xdbg -------------------------------------------------------------------------------- /arjun.srcs/constrs_1/new/abd.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN H17 [get_ports {light_M1[2]}] 2 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M1[2]}] 3 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M1[1]}] 4 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M1[0]}] 5 | set_property PACKAGE_PIN K15 [get_ports {light_M1[1]}] 6 | set_property PACKAGE_PIN J13 [get_ports {light_M1[0]}] 7 | set_property PACKAGE_PIN N14 [get_ports {light_M2[2]}] 8 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M2[2]}] 9 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M2[1]}] 10 | set_property IOSTANDARD LVCMOS33 [get_ports {light_M2[0]}] 11 | set_property IOSTANDARD LVCMOS33 [get_ports {light_MT[2]}] 12 | set_property IOSTANDARD LVCMOS33 [get_ports {light_MT[1]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {light_MT[0]}] 14 | set_property IOSTANDARD LVCMOS33 [get_ports {light_S[2]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {light_S[1]}] 16 | set_property IOSTANDARD LVCMOS33 [get_ports {light_S[0]}] 17 | set_property PACKAGE_PIN R18 [get_ports {light_M2[1]}] 18 | set_property PACKAGE_PIN V17 [get_ports {light_M2[0]}] 19 | set_property PACKAGE_PIN U17 [get_ports {light_MT[2]}] 20 | set_property PACKAGE_PIN V16 [get_ports {light_MT[1]}] 21 | set_property PACKAGE_PIN T15 [get_ports {light_MT[0]}] 22 | set_property PACKAGE_PIN U14 [get_ports {light_S[2]}] 23 | set_property PACKAGE_PIN T16 [get_ports {light_S[1]}] 24 | set_property PACKAGE_PIN V15 [get_ports {light_S[0]}] 25 | -------------------------------------------------------------------------------- /arjun.srcs/sim_1/new/Traffic_Light_Controller_TB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16.07.2020 23:44:40 7 | // Design Name: 8 | // Module Name: Traffic_Light_Controller_TB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | module Traffic_Light_Controller_TB; 23 | reg clk,rst; 24 | wire [2:0]light_M1; 25 | wire [2:0]light_S; 26 | wire [2:0]light_MT; 27 | wire [2:0]light_M2; 28 | Traffic_Light_Controller dut(.clk(clk) , .rst(rst) , .light_M1(light_M1) , .light_S(light_S) ,.light_M2(light_M2),.light_MT(light_MT) ); 29 | initial 30 | begin 31 | clk=1'b0; 32 | forever #(1000000000/2) clk=~clk; 33 | end 34 | // initial 35 | // $stop;//to add ps 36 | initial 37 | begin 38 | rst=0; 39 | #1000000000; 40 | rst=1; 41 | #1000000000; 42 | rst=0; 43 | #(1000000000*200); 44 | $finish; 45 | end 46 | 47 | 48 | 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /arjun.srcs/sources_1/new/Traffic_Light_Controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 16.07.2020 12:53:25 7 | // Design Name: 8 | // Module Name: Traffic_Light_Controller 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | module Traffic_Light_Controller( 24 | 25 | 26 | input clk,rst, 27 | output reg [2:0]light_M1, 28 | output reg [2:0]light_S, 29 | output reg [2:0]light_MT, 30 | output reg [2:0]light_M2 31 | ); 32 | 33 | parameter S1=0, S2=1, S3 =2, S4=3, S5=4,S6=5; 34 | reg [3:0]count; 35 | reg[2:0] ps; 36 | parameter sec7=7,sec5=5,sec2=2,sec3=3; 37 | 38 | 39 | 40 | always@(posedge clk or posedge rst) 41 | begin 42 | if(rst==1) 43 | begin 44 | ps<=S1; 45 | count<=0; 46 | end 47 | else 48 | 49 | 50 | 51 | 52 | case(ps) 53 | S1: if(count 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 107 | 108 | 109 | 110 | 111 | 114 | 115 | 117 | 118 | 120 | 121 | 123 | 124 | 126 | 127 | 128 | 129 | 130 | 131 | Vivado Synthesis Defaults 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | Default settings for Implementation. 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | -------------------------------------------------------------------------------- /system design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Arjun-Narula/Traffic-Light-Controller-using-Verilog/42c0fcb273f7a4e1a738311a2d76d0615042e803/system design.png -------------------------------------------------------------------------------- /youtube video link: -------------------------------------------------------------------------------- 1 | https://www.youtube.com/watch?v=Yt7no6rwCVk 2 | --------------------------------------------------------------------------------