├── Day-10 Full_Subtractor ├── Full_subtractor.v ├── full_sub - [C__Xilinx_Vivado_full_sub_full_sub.xpr] - Vivado 2018.2 31-05-2023 23_04_47.png ├── full_sub - [C__Xilinx_Vivado_full_sub_full_sub.xpr] - Vivado 2018.2 31-05-2023 23_08_46.png └── tb_fS.v ├── Day-11 N_bit Full_Adder ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 02-06-2023 13_17_18.png ├── N(32)bit_adder - [C__Xilinx_Vivado_Nbit_adder_Nbit_adder.xpr] - Vivado 2018.2 02-06-2023 13_29_53.png ├── Nbit_adder - [C__Xilinx_Vivado_Nbit_adder_Nbit_adder.xpr] - Vivado 2018.2 02-06-2023 13_24_53.png ├── nbit_adder.v └── nbit_tb.v ├── Day-12 full_subtraotor using half_subtractor ├── Full_sub_Halfsub.v ├── fs_hs_tb.v ├── fullsub_halfsub - [C__Xilinx_Vivado_fullsub_halfsub_fullsub_halfsub.xpr] - Vivado 2018.2 04-06-2023 09_47_00.png ├── fullsub_halfsub - [C__Xilinx_Vivado_fullsub_halfsub_fullsub_halfsub.xpr] - Vivado 2018.2 04-06-2023 09_48_40.png ├── fullsub_halfsub - [C__Xilinx_Vivado_fullsub_halfsub_fullsub_halfsub.xpr] - Vivado 2018.2 04-06-2023 09_56_31.png └── run1.do ├── Day-12 n bit fulladder(done) ├── Nbit_adder - [C__Xilinx_Vivado_Nbit_adder_Nbit_adder.xpr] - Vivado 2018.2 02-06-2023 14_11_56.png ├── Nbit_adder - [C__Xilinx_Vivado_Nbit_adder_Nbit_adder.xpr] - Vivado 2018.2 02-06-2023 14_21_06.png ├── nbit_fulladder.v ├── nbit_tb.v └── runb.do ├── Day-14_Half_subtractor_dbg ├── HS_bhav.v ├── HS_data.v ├── HS_gate.v ├── Half_Sub - [C__Xilinx_Vivado_Half_Sub_Half_Sub.xpr] - Vivado 2018.2 06-06-2023 19_59_14.png ├── Half_Sub - [C__Xilinx_Vivado_Half_Sub_Half_Sub.xpr] - Vivado 2018.2 06-06-2023 20_12_30.png └── tb_halfsubtractor.v ├── Day-15(mux8x1_2x1) ├── mux8x1_2x1 - [C__Xilinx_Vivado_mux8x1_2x1_mux8x1_2x1.xpr] - Vivado 2018.2 06-06-2023 20_27_21.png ├── mux8x1_2x1 - [C__Xilinx_Vivado_mux8x1_2x1_mux8x1_2x1.xpr] - Vivado 2018.2 06-06-2023 20_30_06.png ├── mux8x1_2x1 - [C__Xilinx_Vivado_mux8x1_2x1_mux8x1_2x1.xpr] - Vivado 2018.2 06-06-2023 20_41_16.png ├── mux8x1_2x1.v ├── mux8x1_data.v ├── mux8x1_mux2x1.v └── tb_mux8x1_2x1.v ├── Day-16_Decoder_2x4 ├── decoder2x4_bhav.v ├── decoder_2_to_4 - [C__Xilinx_Vivado.png ├── decoder_2x4 - [C__Xilinx_Vivado_decoder_2x4_decoder_2x4.xpr] - Vivado 2018.2 07-06-2023 13_05_02 (1).png ├── decoder_2x4 - [C__Xilinx_Vivado_decoder_2x4_decoder_2x4.xpr] - Vivado 2018.2 07-06-2023 13_22_32.png ├── decoder_2x4_data.v └── run2.do ├── Day-17_Decoder_3x8 ├── decoder_3x8 - [C__Xilinx_Vivado_decoder_3x8_decoder_3x8.xpr] - Vivado 2018.2 07-06-2023 14_27_02.png ├── decoder_3x8.v └── tb_decoder_3x8.v ├── Day-18_1 bit comparter_all abstraction level ├── 1bit_comparator_bhv │ ├── comp_bhv.v │ └── tb_1bhv.v ├── 1bit_comparator_data │ ├── 1bit_data.v │ └── tb_1b.v ├── 1bit_comparator_gate │ ├── 1bitc_gate.v │ └── tb_1b.v ├── Comparator_1bit - [C__Xilinx_Vivado_Comparator_1bit_Comparator_1bit.xpr] - Vivado 2018.2 08-06-2023 08_08_32.png ├── Comparator_1bit - [C__Xilinx_Vivado_Comparator_1bit_Comparator_1bit.xpr] - Vivado 2018.2 08-06-2023 08_17_52.png └── Untitled.png ├── Day-19_comparator(2_bit and 4_bit) ├── 2_bit comparator │ ├── comparator_2_bit .png │ ├── comparator_2bit - [C__Xilinx_Vivado_comparator_2bit_comparator_2bit.xpr] - Vivado 2018.2 08-06-2023 09_43_12.png │ ├── comparator_2bit.v │ └── tb_comparator_2bit.v └── 4_bit comparator │ ├── comparator_4_bit - [C__Xilinx_Vivado_comparator_2bit_comparator_2bit.xpr] - Vivado 2018.2 08-06-2023 10_51_35.png │ ├── comparator_4bit - [C__Xilinx_Vivado_comparator_2bit_comparator_2bit.xpr] - Vivado 2018.2 08-06-2023 10_09_25.png │ ├── comparator_4bit - [C__Xilinx_Vivado_comparator_4bit_comparator_4bit.xpr] - Vivado 2018.2 08-06-2023 11_18_28.png │ ├── comparator_4bit.v │ ├── comparator_4bit_data.v │ └── tb_comparator_4bit.v ├── Day-1_Half adder_db ├── 1675507687084.jpg ├── 1675507687108.jpg ├── ha_bhv.v ├── ha_data.v └── hf_tb.v ├── Day-20_Decoder 4x16 using 2x4 ├── Decoder_4x16_2x4 - [C__Xilinx_Vivado_Decoder_4x16_2x4_Decoder_4x16_2x4.xpr] - Vivado 2018.2 09-06-2023 13_38_34.png ├── Decoder_4x16_2x4 - [C__Xilinx_Vivado_Decoder_4x16_2x4_Decoder_4x16_2x4.xpr] - Vivado 2018.2 09-06-2023 13_40_31.png ├── Decoder_4x16_2x4 - [C__Xilinx_Vivado_Decoder_4x16_2x4_Decoder_4x16_2x4.xpr] - Vivado 2018.2 09-06-2023 14_51_04.png ├── Decoder_4x16_2x4.v └── tb_decoder_4x16_2x4.v ├── Day-21 (Binary to gray or Gray to binary) ├── Binary to gray - [C__Xilinx_Vivado_Binary to gray_Binary to gray.xpr] - Vivado 2018.2 10-06-2023 23_30_14.png ├── Untitled.png ├── binary_gray_behv │ ├── gray_binary_bhav.v │ ├── run2.do │ └── tb_bg.v ├── binary_gray_data │ ├── binary_grayCode.v │ ├── run1.do │ └── tb_gtob.v └── binary_gray_gate │ └── binary_gray_gate.v ├── Day-22_Mux(Parameterizable_mux) ├── Untitled.png ├── mux - [C__Xilinx_Vivado_mux_mux.xpr] - Vivado 2018.2 09-06-2023 21_26_46.png ├── mux - [C__Xilinx_Vivado_mux_mux.xpr] - Vivado 2018.2 09-06-2023 22_52_34.png ├── mux.v └── tb_mux.v ├── Day-23_gray to binary code ├── gray_binary1 - [C__Xilinx_Vivado_gray_binary1_gray_binary1.xpr] - Vivado 2018.2 12-06-2023 16_49_59.png ├── gray_binary1 - [C__Xilinx_Vivado_gray_binary1_gray_binary1.xpr] - Vivado 2018.2 14-06-2023 10_00_52.png ├── gray_binary1.v └── tb_gray_binary.v ├── Day-24 Pattern_in_Verilog ├── New Text Document.txt ├── Untitled.png ├── Untitled2.png ├── Untitled5.png ├── pattern1.v ├── pattern2.v ├── pattern3.v ├── pattern4.v ├── pattern5.v ├── pattern6.v ├── pattern7.png ├── pattern7.v └── run1.do ├── Day-26 clock_generation ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 20-06-2023 16_46_04.png ├── clk2.v └── run.do ├── Day-27_D_flipflop ├── async_downcount - [C__Xilinx_Vivado_async_downcount_async_downcount.xpr] - Vivado 2018.2 22-06-2023 12_50_49.png ├── d-flipflop - [C__Xilinx_Vivado_d-flipflop_d-flipflop.xpr] - Vivado 2018.2 22-06-2023 10_09_14.png ├── d-flipflop - [C__Xilinx_Vivado_d-flipflop_d-flipflop.xpr] - Vivado 2018.2 22-06-2023 10_41_08.png ├── d_flipflop.v └── tb_d_flipflop.v ├── Day-28_T_Flip Flop ├── WhatsApp Image 2023-06-24 at 11.45.58 PM.jpeg ├── t_flipflop - [C__Xilinx_Vivado_t_flipflop_t_flipflop.xpr] - Vivado 2018.2 23-06-2023 09_33_50.png ├── t_flipflop - [C__Xilinx_Vivado_t_flipflop_t_flipflop.xpr] - Vivado 2018.2 23-06-2023 11_15_55.png ├── t_flipflop.v └── tb_flipflop.v ├── Day-29_sync_UPcounter(4bit) ├── sync_upcounter - [C__Xilinx_Vivado_sync_upcounter_sync_upcounter.xpr] - Vivado 2018.2 23-06-2023 11_34_42.png ├── sync_upcounter - [C__Xilinx_Vivado_sync_upcounter_sync_upcounter.xpr] - Vivado 2018.2 23-06-2023 13_35_18.png ├── sync_upcounter.v └── tb_sync_upcounter.v ├── Day-2_Full Adder_all abstraction(dbg) ├── 1675588475668.jpg ├── FA_data.v ├── Full_Adder1 - [C__Xilinx_Vivado_Full_Adder1_Full_Adder1.xpr] - Vivado 2018.2 07-06-2023 21_37_55.png ├── full_adder.v └── full_adder_tb.v ├── Day-3 Mux_2x1 ├── Mux_2x1 - [C__Xilinx_Vivado_Mux_2x1_Mux_2x1.xpr] - Vivado 2018.2 14-08-2023 16_52_16.png ├── Mux_2x1 - [C__Xilinx_Vivado_Mux_2x1_Mux_2x1.xpr] - Vivado 2018.2 14-08-2023 16_59_04.png ├── mux_2x1.v └── testbench_mux2x1.v ├── Day-30_sync_4bit_downcounter ├── sync_downcounter - [C__Xilinx_Vivado_sync_upcounter_sync_upcounter.xpr] - Vivado 2018.2 23-06-2023 13_52_31.png ├── sync_downcounter - [C__Xilinx_Vivado_sync_upcounter_sync_upcounter.xpr] - Vivado 2018.2 23-06-2023 14_03_42.png ├── sync_downcounter.v └── tb_sync_downcounter.v ├── Day-31_UP_Down_counter ├── Untitled 6 23-06-2023 16_04_40.png ├── sync_up-down_counter - [C__Xilinx_Vivado_sync_up-down_counter_sync_up-down_counter.xpr] - Vivado 2018.2 23-06-2023 16_05_59.png ├── sync_up-down_counter.v └── tb_up_down_counter.v ├── Day-32_swapping and with non-blocking ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 26-06-2023 23_52_53.png ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 27-06-2023 00_12_30.png ├── Swaping_blockingAssignment_without_temp.v ├── Swapping_nonblocking.v ├── run.do └── swapping using temp.v ├── Day-33 Mod_N_Counter ├── Mod_N_Counter - [C__Xilinx_Vivado_Mod_N_Counter_Mod_N_Counter.xpr] - Vivado 2018.2 16-08-2023 13_26_41.png ├── Mod_N_Counter - [C__Xilinx_Vivado_Mod_N_Counter_Mod_N_Counter.xpr] - Vivado 2018.2 16-08-2023 13_27_35.png ├── Mod_N_Counter.v └── tb_Mod_n_counter.v ├── Day-34 Array_in verilog_using_random_repetation ├── Array(with_repeation) │ ├── output.png │ ├── ques2(a).v │ └── run.do ├── Parameter_using_Array_without_repetition │ ├── Output.png │ ├── array.v │ └── run.do ├── array_how to declare │ ├── run1.do │ ├── task1.v │ └── vsim.wlf └── uniq_random_array │ ├── ques(c).v │ └── run.do ├── Day-35 D-latch_flipflop ├── WhatsApp Image 2023-07-07 at 12.23.04 AM.jpeg ├── WhatsApp Image 2023-07-07 at 12.23.05 AM.jpeg ├── d_flipflop with synchronous_reset │ ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 06-07-2023 23_43_32.png │ ├── d_ff_synchronous_reset - [C__Xilinx_Vivado_d_ff_synchronous_reset_d_ff_synchronous_reset.xpr] - Vivado 2018.2 06-07-2023 13_44_37.png │ ├── dff_synchronous_reset.v │ ├── run.do │ └── tb_dff_synchronous_reset.v ├── d_flipflop_with_inAsynchronous_reset(clear)_ │ ├── d_ff_asynchronous_reset - [C__Xilinx_Vivado_d_ff_asynchronous_reset_d_ff_asynchronous_reset.xpr] - Vivado 2018.2 06-07-2023 22_08_42.png │ ├── d_ff_asynchronous_reset - [C__Xilinx_Vivado_d_ff_asynchronous_reset_d_ff_asynchronous_reset.xpr] - Vivado 2018.2 06-07-2023 22_12_29.png │ ├── dff_asynchronous_reset.v │ └── tb_dff_asynchronous_reset.v └── d_latch │ ├── d_latch - [C__Xilinx_Vivado_d_latch_d_latch.xpr] - Vivado 2018.2 06-07-2023 07_24_13.png │ ├── d_latch - [C__Xilinx_Vivado_d_latch_d_latch.xpr] - Vivado 2018.2 06-07-2023 07_59_24.png │ ├── d_latch.v │ └── tb_d_latch.v ├── Day-36_Async_UpCounter using JKFlipFlop ├── Asyn_upCounter - [C__Xilinx_Vivado_Asyn_upCounter_Asyn_upCounter.xpr] - Vivado 2018.2 16-10-2023 11_45_14.png ├── Asyn_upCounter - [C__Xilinx_Vivado_Asyn_upCounter_Asyn_upCounter.xpr] - Vivado 2018.2 16-10-2023 11_46_00.png ├── Asyn_upCounter_waveform.png ├── Async_UpCounter.v ├── JK_FlipFlop.v └── tb_Async_UpCounter.v ├── Day-37_Up_counter_down_counter_using_dff_data_flow_modling ├── down_counter_df_dataflow_modling │ ├── RTL_diagram.png │ ├── dff_data.v │ ├── down_count_data.v │ ├── downcounter_dff_data_waveform.png │ ├── rtl_implement.png │ └── tb_down_count.v └── up_counter_dff_dataflow_modling │ ├── dff_upcount_data.v │ ├── tb_upcount_data.v │ ├── up_counter.v │ ├── up_counter_dataflow - [C__Xilinx_Vivado_up_counter_dataflow_up_counter_dataflow.xpr] - Vivado 2018.2 10-07-2023 15_21_36.png │ └── up_counter_dataflow - [C__Xilinx_Vivado_up_counter_dataflow_up_counter_dataflow.xpr] - Vivado 2018.2 10-07-2023 15_23_38.png ├── Day-38_Memory_design ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 12-07-2023 13_27_49.png ├── Schematic 12-07-2023 13_08_57.png ├── mem1.v ├── run.do ├── tb.v └── vsim.wlf ├── Day-39 Synchronous_FIFO ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 16-07-2023 00_00_02.png ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 16-07-2023 00_50_34.png ├── fifo.v ├── run.do └── tb_fifo.v ├── Day-4 Fulladder using Halfsubtractor ├── Full_Addr_HAlf_Sub - [C__Xilinx_Vivado_Full_Addr_HAlf_Sub_Full_Addr_HAlf_Sub.xpr] - Vivado 2018.2 14-10-2023 15_04_27.png ├── Full_Addr_HAlf_Sub - [C__Xilinx_Vivado_Full_Addr_HAlf_Sub_Full_Addr_HAlf_Sub.xpr] - Vivado 2018.2 14-10-2023 15_05_43.png ├── Full_Addr_HAlf_Sub - [C__Xilinx_Vivado_Full_Addr_HAlf_Sub_Full_Addr_HAlf_Sub.xpr] - Vivado 2018.2 14-10-2023 15_06_01.png ├── HalfSub.v ├── fulladdr_using_halfSub.v └── tb_fulladdr_HS.v ├── Day-40 Priority_Encoder ├── Tb_Priority_Encoder.v ├── pariti encoder.v └── project_5 - [C__Xilinx_Vivado_project_5_project_5.xpr] - Vivado 2018.2 18-08-2023 16_32_46.png ├── Day-41 N-Bit_Up_Down_counter ├── N_BIT UPDOWN_COUNTER - [C__Xilinx_Vivado_N_BIT UPDOWN_COUNTER_N_BIT UPDOWN_COUNTER.xpr] - Vivado 2018.2 16-08-2023 12_17_22.png ├── N_BIT UPDOWN_COUNTER - [C__Xilinx_Vivado_N_BIT UPDOWN_COUNTER_N_BIT UPDOWN_COUNTER.xpr] - Vivado 2018.2 16-08-2023 12_18_27.png ├── N_Bit updowncounter.v └── tb_nbit_updowncounter.v ├── Day-42_Gray_code_counter ├── gray_code_counter - [C__Xilinx_Vivado_gray_code_counter_gray_code_counter.xpr] - Vivado 2018.2 16-08-2023 15_18_52.png ├── gray_code_counter - [C__Xilinx_Vivado_gray_code_counter_gray_code_counter.xpr] - Vivado 2018.2 16-08-2023 15_20_05.png ├── gray_code_counter.v └── tb_gray_counter.v ├── Day-43 Ring_counter ├── ring_counters - [C__Xilinx_Vivado_ring_counters_ring_counters.xpr] - Vivado 2018.2 16-08-2023 17_21_11.png ├── ring_counters - [C__Xilinx_Vivado_ring_counters_ring_counters.xpr] - Vivado 2018.2 16-08-2023 17_21_43.png ├── ring_counters.v └── tb_ring_counters.v ├── Day-44 Twisted_counter ├── Twister_ring_counter - [C__Xilinx_Vivado_Twister_ring_counter_Twister_ring_counter.xpr] - Vivado 2018.2 17-08-2023 22_39_23.png ├── Twister_ring_counter - [C__Xilinx_Vivado_Twister_ring_counter_Twister_ring_counter.xpr] - Vivado 2018.2 17-08-2023 22_45_29.png ├── tb_twisted_counter.v └── twisted_counter.v ├── Day-45_LFSR ├── LFSR - [C__Xilinx_Vivado_LFSR_LFSR.xpr] - Vivado 2018.2 18-08-2023 11_12_22.png ├── LFSR - [C__Xilinx_Vivado_LFSR_LFSR.xpr] - Vivado 2018.2 18-08-2023 11_12_32.png ├── LFSR - [C__Xilinx_Vivado_LFSR_LFSR.xpr] - Vivado 2018.2 18-08-2023 11_13_39.png ├── LFSR.v └── tb_LFSR.v ├── Day-46_Syncronous_FIFO(Single_wr_rd_tb) └── Single_read_write_fifo with testbench │ ├── run.do │ ├── sinlge_wr_rd_output.png │ ├── sync_fifo.v │ ├── tb_wr_rd.v │ └── vsim.wlf ├── Day-47_ALU[16-Bit] ├── ALU - [C__Xilinx_Vivado_ALU_ALU.xpr] - Vivado 2018.2 17-10-2023 20_32_17.png ├── ALU - waveform.png ├── ALU.v └── tb_ALU.v ├── Day-49_Prime_number ├── Transcript 29-10-2023 07_32_58.png ├── prime_num.v └── run.do ├── Day-6_mux4x1_dbg ├── mux4x1_bhv.v ├── mux4x1_data.v ├── mux4x1_g.v ├── mux_4to1 - [C__Xilinx_Vivado_mux_4to1_mux_4to1.xpr] - Vivado 2018.2 21-02-2023 09_55_46.png ├── mux_4to1 - [C__Xilinx_Vivado_mux_4to1_mux_4to1.xpr] - Vivado 2018.2 21-02-2023 10_08_09.png └── mux_4to1_tb.v ├── Day-7_Mux8x1_dbg ├── mux8x1_bhv(vector) │ ├── mux8x1_b.v │ └── mux8x1_tb.v ├── mux8x1_data(vector) │ ├── mux8x1_data.v │ └── mux8x1_tb.v ├── mux8x1_gate(vector) │ ├── mux8x1_g.v │ └── mux8x1_tb.v ├── mux_8to1 - [C__Xilinx_Vivado_mux_8to1_mux_8to1.xpr] - Vivado 2018.2 22-02-2023 08_59_40.png └── mux_8to1 - [C__Xilinx_Vivado_mux_8to1_mux_8to1.xpr] - Vivado 2018.2 22-02-2023 10_53_36.png ├── Day-8_Async_Upcounter using T_flipFlop ├── Async_UpCounter_RTL.png ├── Async_UpCounter_output.png ├── Async_UpCounter_tff.png ├── Async_UpCounter_waveform.png ├── T_flipflops.v ├── async_UpCounter.v └── tb_aync_UpCounter.v ├── Day-9 Ripple Carry Adder ├── ModelSim - INTEL FPGA STARTER EDITION 2020.1 31-05-2023 21_25_59.png ├── RPL [C__Xilinx_Vivado_fulladd4_fulladd4.xpr] - Vivado 2018.2 28-02-2023 16_31_06.png ├── Ripple_carry(4bit_adder).v └── tb_pa.v ├── Day_19 4bit Comparator Using 2bit Comparator ├── design.v └── tb_comparator.v ├── Day_25_Mux8x1 using 4x1_2x1 ├── mux8x1_4x1_2x1.v ├── mux8x1_mux4x1_2x1 - [C__Xilinx_Vivado_mux8x1_mux4x1_2x1_mux8x1_mux4x1_2x1.xpr] - Vivado 2018.2 16-06-2023 19_34_30.png ├── mux8x1_mux4x1_2x1 - [C__Xilinx_Vivado_mux8x1_mux4x1_2x1_mux8x1_mux4x1_2x1.xpr] - Vivado 2018.2 16-06-2023 19_36_34.png ├── mux8x1_mux4x1_2x1 - [C__Xilinx_Vivado_mux8x1_mux4x1_2x1_mux8x1_mux4x1_2x1.xpr] - Vivado 2018.2 18-06-2023 11_30_10.png └── tb_mux8x1_4x1-2x1.v ├── Day_51 RAM Verilog ├── RAM.sv - EDA Playground - Google Chrome 13-01-2024 02_32_14 PM.png ├── design.sv └── testbench.sv ├── README.md ├── Ripple Carry Adder ├── PA.v ├── RPL [C__Xilinx_Vivado_fulladd4_fulladd4.xpr] - Vivado 2018.2 28-02-2023 16_31_06.png ├── tb_pa.v └── work │ └── _lib1_0.qpg ├── mux_8to1 - [C__Xilinx_Vivado_mux_8to1_mux_8to1.xpr] - Vivado 2018.2 22-02-2023 10_53_36.png ├── mux_8to1.v └── mux_8to1_tb.v /Day-10 Full_Subtractor/Full_subtractor.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Artityagi123456789/100DaysofRTL/HEAD/Day-10 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