├── generate - m2.bat ├── generate – 100T.bat ├── generate - squirrel.bat ├── generate – enigma - x1.bat ├── generate – captain - 75T.bat ├── generate - immmortal - 75Ts .bat ├── generate – immortal - 75T.bat ├── README.md ├── vivado_build.tcl ├── vivado_build_100t.tcl ├── pcie_7x ├── pcie_7x_0_gtp_cpllpd_ovrd.v ├── pcie_7x_0_gtx_cpllpd_ovrd.v ├── zdma │ ├── pcie_7x_0_gtp_cpllpd_ovrd.v │ ├── pcie_7x_0_gtx_cpllpd_ovrd.v │ ├── ip_xilinx_pcie_2_1_7x_late.xdc │ ├── pcie_7x_0_gt_common.v │ ├── pcie_7x_0_axi_basic_rx.v │ ├── pcie_7x_0_pcie_bram_top_7x.v │ ├── pcie_7x_0_pcie_pipe_misc.v │ └── pcie_7x_0_pcie_bram_7x.v ├── pcie_7x_0_gt_common.v ├── pcie_7x_0_axi_basic_rx.v ├── pcie_7x_0_pcie_bram_top_7x.v ├── pcie_7x_0_pcie_pipe_misc.v └── pcie_7x_0_pcie_bram_7x.v ├── src ├── pcileech_pcie_cfgspace_shadow.sv ├── pcileech_screamer_m2_top.sv ├── pcileech_squirrel_top.sv ├── pcileech_enigma_x1_top.sv ├── 75immt.xdc ├── pcileech_captain_75T.xdc ├── pcileech_enigma_x1.xdc ├── pcileech_squirrel.xdc ├── pcileech_tbx4_100t_top.sv ├── pcileech_screamer_m2.xdc ├── pcileech_mux.sv ├── pcileech_ft601.sv └── pcileech_tbx4_100t.xdc └── ip ├── 100t └── drom_pcie_cfgspace_writemask.xci └── drom_pcie_cfgspace_writemask.xci /generate - m2.bat: -------------------------------------------------------------------------------- 1 | C:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_m2.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate – 100T.bat: -------------------------------------------------------------------------------- 1 | C:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_100t.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate - squirrel.bat: -------------------------------------------------------------------------------- 1 | E:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_squirrel.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate – enigma - x1.bat: -------------------------------------------------------------------------------- 1 | C:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_enigma_x1.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate – captain - 75T.bat: -------------------------------------------------------------------------------- 1 | e:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_captain_75T.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate - immmortal - 75Ts .bat: -------------------------------------------------------------------------------- 1 | C:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_immortal_75Ts.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /generate – immortal - 75T.bat: -------------------------------------------------------------------------------- 1 | C:\Xilinx\Vivado\2023.2\bin\vivado -source vivado_generate_project_immortal_75T.tcl -notrace -nolog -nojournal -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # pcileech-sata 2 | FPGA card looks like an sata/ata controller, but hides inside pcileech-fpga researching tool. (ASM1061/ASM1062 Serial ATA Controller) 3 | 4 | ![device manager](https://github.com/user-attachments/assets/2292e843-8029-4e7e-8a42-7f4f198477ae) 5 | ![drv](https://github.com/user-attachments/assets/b667b244-ac22-42bf-b3dd-ad1c8feba29a) 6 | # Usage 7 | This firmware was created for researching purposes only. 8 | # Original project by ekknod based on Ulf Frisk pcileech-fpga project 9 | Original project can be found from https://github.com/ekknod/pcileech-wifi 10 | # Contacts 11 | - Selling some sources rn, contact me at discord if you're interested (astrality_blade) 12 | # Features 13 | - Operting with all IO bars 14 | - Self builded core with ip 15 | - MSI interrupt logic 16 | - Emulation of "Fake/Virtual" disk 17 | # Notice 18 | - This version have some sort of anti-paste to prevent it from selling by idiots like(Shalfey/Decoded) 19 | - There's some bug with long boot (If you have a bsods on startup, disavle fastboot in bios) and that interrupts can't handle properly on win10 (If you dont know how to fix it, just use win11) 20 | # Credits 21 | - Ekknod 22 | - Ulf Frisk 23 | - Scopolamine 24 | -------------------------------------------------------------------------------- /vivado_build.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # RUN FROM WITHIN "Vivado Tcl Shell" WITH COMMAND: 3 | # source vivado_build.tcl -notrace 4 | # 5 | puts "-------------------------------------------------------" 6 | puts " STARTING SYNTHESIS STEP. " 7 | puts "-------------------------------------------------------" 8 | launch_runs synth_1 9 | puts "-------------------------------------------------------" 10 | puts " WAITING FOR SYNTHESIS STEP TO FINISH ... " 11 | puts " THIS IS LIKELY TO TAKE A VERY LONG TIME. " 12 | puts "-------------------------------------------------------" 13 | wait_on_run synth_1 14 | puts "-------------------------------------------------------" 15 | puts " STARTING IMPLEMENTATION STEP. " 16 | puts "-------------------------------------------------------" 17 | launch_runs impl_1 -to_step write_bitstream 18 | puts "-------------------------------------------------------" 19 | puts " WAITING FOR IMPLEMENTATION STEP TO FINISH ... " 20 | puts " THIS IS LIKELY TO TAKE A VERY LONG TIME. " 21 | puts "-------------------------------------------------------" 22 | wait_on_run impl_1 23 | file copy -force ./pcileech_squirrel/pcileech_squirrel.runs/impl_1/pcileech_squirrel_top.bin pcileech_squirrel.bin 24 | puts "-------------------------------------------------------" 25 | puts " BUILD HOPEFULLY COMPLETED. " 26 | puts "-------------------------------------------------------" -------------------------------------------------------------------------------- /vivado_build_100t.tcl: -------------------------------------------------------------------------------- 1 | # 2 | # RUN FROM WITHIN "Vivado Tcl Shell" WITH COMMAND: 3 | # source vivado_build.tcl -notrace 4 | # 5 | puts "-------------------------------------------------------" 6 | puts " STARTING SYNTHESIS STEP. " 7 | puts "-------------------------------------------------------" 8 | launch_runs -jobs 6 synth_1 9 | puts "-------------------------------------------------------" 10 | puts " WAITING FOR SYNTHESIS STEP TO FINISH ... " 11 | puts " THIS IS LIKELY TO TAKE A VERY LONG TIME. " 12 | puts "-------------------------------------------------------" 13 | wait_on_run synth_1 14 | puts "-------------------------------------------------------" 15 | puts " STARTING IMPLEMENTATION STEP. " 16 | puts "-------------------------------------------------------" 17 | launch_runs -jobs 4 impl_1 -to_step write_bitstream 18 | puts "-------------------------------------------------------" 19 | puts " WAITING FOR IMPLEMENTATION STEP TO FINISH ... " 20 | puts " THIS IS LIKELY TO TAKE A VERY LONG TIME. " 21 | puts "-------------------------------------------------------" 22 | wait_on_run impl_1 23 | file copy -force ./pcileech_tbx4_100t/pcileech_tbx4_100t.runs/impl_1/pcileech_tbx4_100t_top.bin pcileech_zdma_100t_fpga0.bin 24 | puts "-------------------------------------------------------" 25 | puts " BUILD HOPEFULLY COMPLETED. " 26 | puts "-------------------------------------------------------" -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_gtp_cpllpd_ovrd.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_gtp_cpllpd_ovrd.v 52 | // Version : 3.3 53 | `timescale 1ns / 1ps 54 | module pcie_7x_0_gtp_cpllpd_ovrd ( 55 | input i_ibufds_gte2, 56 | output o_cpllpd_ovrd, 57 | output o_cpllreset_ovrd 58 | ); 59 | (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; 60 | (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; 61 | always @(posedge i_ibufds_gte2) 62 | begin 63 | cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; 64 | cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; 65 | end 66 | assign o_cpllpd_ovrd = cpllpd_wait[95]; 67 | assign o_cpllreset_ovrd = cpllreset_wait[127]; 68 | endmodule 69 | -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_gtx_cpllpd_ovrd.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_gtx_cpllpd_ovrd.v 52 | // Version : 3.3 53 | `timescale 1ns / 1ps 54 | module pcie_7x_0_gtx_cpllpd_ovrd ( 55 | input i_ibufds_gte2, 56 | output o_cpllpd_ovrd, 57 | output o_cpllreset_ovrd 58 | ); 59 | (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; 60 | (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; 61 | always @(posedge i_ibufds_gte2) 62 | begin 63 | cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; 64 | cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; 65 | end 66 | assign o_cpllpd_ovrd = cpllpd_wait[95]; 67 | assign o_cpllreset_ovrd = cpllreset_wait[127]; 68 | endmodule 69 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_gtp_cpllpd_ovrd.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_gtp_cpllpd_ovrd.v 53 | // Version : 3.3 54 | `timescale 1ns / 1ps 55 | module pcie_7x_0_gtp_cpllpd_ovrd ( 56 | input i_ibufds_gte2, 57 | output o_cpllpd_ovrd, 58 | output o_cpllreset_ovrd 59 | ); 60 | (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; 61 | (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; 62 | always @(posedge i_ibufds_gte2) 63 | begin 64 | cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; 65 | cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; 66 | end 67 | assign o_cpllpd_ovrd = cpllpd_wait[95]; 68 | assign o_cpllreset_ovrd = cpllreset_wait[127]; 69 | endmodule 70 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_gtx_cpllpd_ovrd.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_gtx_cpllpd_ovrd.v 53 | // Version : 3.3 54 | `timescale 1ns / 1ps 55 | module pcie_7x_0_gtx_cpllpd_ovrd ( 56 | input i_ibufds_gte2, 57 | output o_cpllpd_ovrd, 58 | output o_cpllreset_ovrd 59 | ); 60 | (* equivalent_register_removal="no" *) reg [95:0] cpllpd_wait = 96'hFFFFFFFFFFFFFFFFFFFFFFFF; 61 | (* equivalent_register_removal="no" *) reg [127:0] cpllreset_wait = 128'h000000000000000000000000000000FF; 62 | always @(posedge i_ibufds_gte2) 63 | begin 64 | cpllpd_wait <= {cpllpd_wait[94:0], 1'b0}; 65 | cpllreset_wait <= {cpllreset_wait[126:0], 1'b0}; 66 | end 67 | assign o_cpllpd_ovrd = cpllpd_wait[95]; 68 | assign o_cpllreset_ovrd = cpllreset_wait[127]; 69 | endmodule 70 | -------------------------------------------------------------------------------- /src/pcileech_pcie_cfgspace_shadow.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // PCIe custom shadow configuration space. 5 | // Xilinx PCIe core will take configuration space priority; if Xilinx PCIe core 6 | // is configured to forward configuration requests to user application such TLP 7 | // will end up being processed by this module. 8 | // 9 | // (c) Ulf Frisk, 2021-2022 10 | // Author: Ulf Frisk, pcileech@frizk.net 11 | // 12 | 13 | `timescale 1ns / 1ps 14 | 15 | module pcileech_pcie_cfgspace_shadow( 16 | input rst, 17 | input clk, 18 | IfShadow2Fifo.src dshadow2fifo, 19 | IfShadow2Tlp.shadow dshadow2tlp 20 | ); 21 | 22 | wire int_rden; 23 | wire int_wren; 24 | wire [9:0] int_wr_addr; 25 | wire [31:0] int_wr_data; 26 | wire [9:0] int_rd_addr; 27 | 28 | // ---------------------------------------------------------------------------- 29 | // WRITE multiplexor: simple naive multiplexor which will prioritize in order: 30 | // (1) PCIe (if enabled), (2) USB, (3) INTERNAL. 31 | // Collisions will be discarded (it's assumed that they'll be very rare) 32 | // ---------------------------------------------------------------------------- 33 | wire bram_wr_1_tlp = dshadow2tlp.rx_wren; 34 | wire bram_wr_2_usb = ~bram_wr_1_tlp & dshadow2fifo.rx_wren; 35 | wire bram_wr_3_int = ~bram_wr_1_tlp & ~bram_wr_2_usb & int_wren; 36 | wire [3:0] bram_wr_be = bram_wr_1_tlp ? (dshadow2fifo.cfgtlp_wren ? dshadow2tlp.rx_be : 4'b0000) : (bram_wr_2_usb ? dshadow2fifo.rx_be : (bram_wr_3_int ? 4'b1111 : 4'b0000)); 37 | wire [9:0] bram_wr_addr = bram_wr_1_tlp ? dshadow2tlp.rx_addr : (bram_wr_2_usb ? dshadow2fifo.rx_addr : int_wr_addr); 38 | wire [31:0] bram_wr_data = bram_wr_1_tlp ? dshadow2tlp.rx_data : (bram_wr_2_usb ? dshadow2fifo.rx_data : int_wr_data); 39 | 40 | // ---------------------------------------------------------------------------- 41 | // WRITE multiplexor and state machine: simple naive multiplexor which will prioritize in order: 42 | // (1) PCIe (if enabled), (2) USB, (3) INTERNAL. 43 | // Collisions will be discarded (it's assumed that they'll be very rare) 44 | // ---------------------------------------------------------------------------- 45 | `define S_SHADOW_CFGSPACE_IDLE 2'b00 46 | `define S_SHADOW_CFGSPACE_TLP 2'b01 47 | `define S_SHADOW_CFGSPACE_USB 2'b10 48 | `define S_SHADOW_CFGSPACE_INT 2'b11 49 | 50 | wire [31:0] bram_rd_data; 51 | wire bram_rd_1_tlp = dshadow2tlp.rx_rden; 52 | wire bram_rd_2_usb = ~bram_rd_1_tlp & dshadow2fifo.rx_rden; 53 | wire bram_rd_3_int = ~bram_rd_1_tlp & ~bram_rd_2_usb & int_rden; 54 | wire [1:0] bram_rd_tp_3 = bram_rd_1_tlp ? `S_SHADOW_CFGSPACE_TLP : ( 55 | bram_rd_2_usb ? `S_SHADOW_CFGSPACE_USB : ( 56 | bram_rd_3_int ? `S_SHADOW_CFGSPACE_INT : `S_SHADOW_CFGSPACE_IDLE)); 57 | wire [9:0] bram_rd_addr_3 = bram_rd_1_tlp ? dshadow2tlp.rx_addr : ( 58 | bram_rd_2_usb ? dshadow2fifo.rx_addr : int_rd_addr); 59 | wire [7:0] bram_rd_tag_3 = bram_rd_1_tlp ? dshadow2tlp.rx_tag : {7'h00, dshadow2fifo.rx_addr_lo}; 60 | bit [9:0] bram_rd_addr, bram_rd_addr_2; 61 | bit [7:0] bram_rd_tag, bram_rd_tag_2; 62 | bit [1:0] bram_rd_tp, bram_rd_tp_2; 63 | 64 | always @ ( posedge clk ) 65 | begin 66 | bram_rd_addr <= bram_rd_addr_2; 67 | bram_rd_tag <= bram_rd_tag_2; 68 | bram_rd_tp <= bram_rd_tp_2; 69 | bram_rd_addr_2 <= bram_rd_addr_3; 70 | bram_rd_tag_2 <= bram_rd_tag_3; 71 | bram_rd_tp_2 <= bram_rd_tp_3; 72 | end 73 | 74 | // BRAM MEMORY ACCESS for the 4kB / 0x1000 byte shadow configuration space. 75 | bram_pcie_cfgspace i_bram_pcie_cfgspace( 76 | .clka ( clk ), 77 | .clkb ( clk ), 78 | .wea ( bram_wr_be ), 79 | .addra ( bram_wr_addr ), 80 | .dina ( bram_wr_data ), 81 | .addrb ( bram_rd_addr_3 ), 82 | .doutb ( bram_rd_data ) 83 | ); 84 | 85 | assign dshadow2tlp.tx_valid = bram_wr_1_tlp | (bram_rd_tp == `S_SHADOW_CFGSPACE_TLP); 86 | assign dshadow2tlp.tx_tlprd = ~bram_wr_1_tlp; 87 | assign dshadow2tlp.tx_tag = bram_wr_1_tlp ? dshadow2tlp.rx_tag : bram_rd_tag; 88 | assign dshadow2tlp.tx_data = dshadow2fifo.cfgtlp_zero ? 32'h00000000 : bram_rd_data; 89 | 90 | assign dshadow2fifo.tx_valid = (bram_rd_tp == `S_SHADOW_CFGSPACE_USB); 91 | assign dshadow2fifo.tx_addr = bram_rd_addr; 92 | assign dshadow2fifo.tx_addr_lo = bram_rd_tag[0]; 93 | assign dshadow2fifo.tx_data = dshadow2fifo.cfgtlp_zero ? 32'h00000000 : bram_rd_data; 94 | 95 | // ---------------------------------------------------------------------------- 96 | // INTERNAL LOGIC BELOW: 97 | // ---------------------------------------------------------------------------- 98 | 99 | assign int_rden = 0; 100 | assign int_wren = 0; 101 | assign int_wr_addr = 0; 102 | assign int_wr_data = 0; 103 | assign int_rd_addr = 0; 104 | 105 | endmodule 106 | -------------------------------------------------------------------------------- /src/pcileech_screamer_m2_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // Top module for various 35T-325 x1 Artix-7 boards. 5 | // 6 | // (c) Ulf Frisk, 2019-2024 7 | // Author: Ulf Frisk, pcileech@frizk.net 8 | // 9 | 10 | `timescale 1ns / 1ps 11 | `include "pcileech_header.svh" 12 | 13 | module pcileech_screamer_m2_top #( 14 | parameter PARAM_DEVICE_ID = 4, 15 | parameter PARAM_VERSION_NUMBER_MAJOR = 4, 16 | parameter PARAM_VERSION_NUMBER_MINOR = 13, 17 | parameter PARAM_CUSTOM_VALUE = 32'hffffffff 18 | ) ( 19 | // SYS 20 | input clk, 21 | input ft601_clk, 22 | 23 | // SYSTEM LEDs and BUTTONs 24 | output user_ld1, 25 | output user_ld2, 26 | 27 | // PCI-E FABRIC 28 | output [0:0] pcie_tx_p, 29 | output [0:0] pcie_tx_n, 30 | input [0:0] pcie_rx_p, 31 | input [0:0] pcie_rx_n, 32 | input pcie_clk_p, 33 | input pcie_clk_n, 34 | input pcie_present, 35 | input pcie_perst_n, 36 | output reg pcie_wake_n = 1'b1, 37 | 38 | // TO/FROM FT601 PADS 39 | output ft601_rst_n, 40 | 41 | inout [31:0] ft601_data, 42 | output [3:0] ft601_be, 43 | input ft601_rxf_n, 44 | input ft601_txe_n, 45 | output ft601_wr_n, 46 | output ft601_siwu_n, 47 | output ft601_rd_n, 48 | output ft601_oe_n 49 | ); 50 | 51 | // SYS 52 | wire rst; 53 | 54 | // FIFO CTL <--> COM CTL 55 | wire [63:0] com_dout; 56 | wire com_dout_valid; 57 | wire [255:0] com_din; 58 | wire com_din_wr_en; 59 | wire com_din_ready; 60 | wire led_com; 61 | wire led_pcie; 62 | 63 | // FIFO CTL <--> COM CTL 64 | IfComToFifo dcom_fifo(); 65 | 66 | // FIFO CTL <--> PCIe 67 | IfPCIeFifoCfg dcfg(); 68 | IfPCIeFifoTlp dtlp(); 69 | IfPCIeFifoCore dpcie(); 70 | IfShadow2Fifo dshadow2fifo(); 71 | 72 | // ---------------------------------------------------- 73 | // TickCount64 CLK 74 | // ---------------------------------------------------- 75 | 76 | time tickcount64 = 0; 77 | always @ ( posedge clk ) 78 | tickcount64 <= tickcount64 + 1; 79 | 80 | assign rst = (tickcount64 < 64) ? 1'b1 : 1'b0; 81 | assign ft601_rst_n = ~rst; 82 | wire led_pwronblink = tickcount64[24] & (tickcount64[63:27] == 0); 83 | 84 | OBUF led_ld1_obuf(.O(user_ld1), .I(led_pcie)); 85 | OBUF led_ld2_obuf(.O(user_ld2), .I(led_com)); 86 | 87 | // ---------------------------------------------------- 88 | // BUFFERED COMMUNICATION DEVICE (FT601) 89 | // ---------------------------------------------------- 90 | 91 | pcileech_com i_pcileech_com ( 92 | // SYS 93 | .clk ( clk ), 94 | .clk_com ( ft601_clk ), 95 | .rst ( rst ), 96 | .led_state_txdata ( led_com ), // -> 97 | .led_state_invert ( led_pwronblink ), // <- 98 | // FIFO CTL <--> COM CTL 99 | .dfifo ( dcom_fifo.mp_com ), 100 | // TO/FROM FT601 PADS 101 | .ft601_data ( ft601_data ), // <> [31:0] 102 | .ft601_be ( ft601_be ), // -> [3:0] 103 | .ft601_txe_n ( ft601_txe_n ), // <- 104 | .ft601_rxf_n ( ft601_rxf_n ), // <- 105 | .ft601_siwu_n ( ft601_siwu_n ), // -> 106 | .ft601_wr_n ( ft601_wr_n ), // -> 107 | .ft601_rd_n ( ft601_rd_n ), // -> 108 | .ft601_oe_n ( ft601_oe_n ) // -> 109 | ); 110 | 111 | // ---------------------------------------------------- 112 | // FIFO CTL 113 | // ---------------------------------------------------- 114 | 115 | pcileech_fifo #( 116 | .PARAM_DEVICE_ID ( PARAM_DEVICE_ID ), 117 | .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR ), 118 | .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR ), 119 | .PARAM_CUSTOM_VALUE ( PARAM_CUSTOM_VALUE ) 120 | ) i_pcileech_fifo ( 121 | .clk ( clk ), 122 | .rst ( rst ), 123 | .rst_cfg_reload ( 1'b0 ), 124 | .pcie_present ( pcie_present ), 125 | .pcie_perst_n ( pcie_perst_n ), 126 | // FIFO CTL <--> COM CTL 127 | .dcom ( dcom_fifo.mp_fifo ), 128 | // FIFO CTL <--> PCIe 129 | .dcfg ( dcfg.mp_fifo ), 130 | .dtlp ( dtlp.mp_fifo ), 131 | .dpcie ( dpcie.mp_fifo ), 132 | .dshadow2fifo ( dshadow2fifo.fifo ) 133 | ); 134 | 135 | // ---------------------------------------------------- 136 | // PCIe 137 | // ---------------------------------------------------- 138 | 139 | pcileech_pcie_a7 i_pcileech_pcie_a7( 140 | .clk_sys ( clk ), 141 | .rst ( rst ), 142 | // PCIe fabric 143 | .pcie_tx_p ( pcie_tx_p ), 144 | .pcie_tx_n ( pcie_tx_n ), 145 | .pcie_rx_p ( pcie_rx_p ), 146 | .pcie_rx_n ( pcie_rx_n ), 147 | .pcie_clk_p ( pcie_clk_p ), 148 | .pcie_clk_n ( pcie_clk_n ), 149 | .pcie_perst_n ( pcie_perst_n ), 150 | // State and Activity LEDs 151 | .led_state ( led_pcie ), 152 | // FIFO CTL <--> PCIe 153 | .dfifo_cfg ( dcfg.mp_pcie ), 154 | .dfifo_tlp ( dtlp.mp_pcie ), 155 | .dfifo_pcie ( dpcie.mp_pcie ), 156 | .dshadow2fifo ( dshadow2fifo.shadow ) 157 | ); 158 | 159 | endmodule 160 | -------------------------------------------------------------------------------- /pcie_7x/zdma/ip_xilinx_pcie_2_1_7x_late.xdc: -------------------------------------------------------------------------------- 1 | 2 | ##----------------------------------------------------------------------------- 3 | ## 4 | ## (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | ## 6 | ## This file contains confidential and proprietary information 7 | ## of AMD and is protected under U.S. and 8 | ## international copyright and other intellectual property 9 | ## laws. 10 | ## 11 | ## DISCLAIMER 12 | ## This disclaimer is not a license and does not grant any 13 | ## rights to the materials distributed herewith. Except as 14 | ## otherwise provided in a valid license issued to you by 15 | ## AMD, and to the maximum extent permitted by applicable 16 | ## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | ## WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | ## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | ## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | ## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | ## (2) AMD shall not be liable (whether in contract or tort, 22 | ## including negligence, or under any other theory of 23 | ## liability) for any loss or damage of any kind or nature 24 | ## related to, arising under or in connection with these 25 | ## materials, including for any direct, or any indirect, 26 | ## special, incidental, or consequential loss or damage 27 | ## (including loss of data, profits, goodwill, or any type of 28 | ## loss or damage suffered as a result of any action brought 29 | ## by a third party) even if such damage or loss was 30 | ## reasonably foreseeable or AMD had been advised of the 31 | ## possibility of the same. 32 | ## 33 | ## CRITICAL APPLICATIONS 34 | ## AMD products are not designed or intended to be fail- 35 | ## safe, or for use in any application requiring fail-safe 36 | ## performance, such as life-support or safety devices or 37 | ## systems, Class III medical devices, nuclear facilities, 38 | ## applications related to the deployment of airbags, or any 39 | ## other applications that could lead to death, personal 40 | ## injury, or severe property or environmental damage 41 | ## (individually and collectively, "Critical 42 | ## Applications"). Customer assumes the sole risk and 43 | ## liability of any use of AMD products in Critical 44 | ## Applications, subject only to applicable laws and 45 | ## regulations governing limitations on product liability. 46 | ## 47 | ## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | ## PART OF THIS FILE AT ALL TIMES. 49 | ## 50 | ##----------------------------------------------------------------------------- 51 | ## Project : Series-7 Integrated Block for PCI Express 52 | ## File : ip_xilinx_pcie_2_1_7x_late.xdc 53 | ## Version : 3.3 54 | # 55 | ############################################################################### 56 | # User Time Names / User Time Groups / Time Specs 57 | ############################################################################### 58 | 59 | ############################################################################### 60 | # User Physical Constraints 61 | ############################################################################### 62 | 63 | 64 | ############################################################################### 65 | # Pinout and Related I/O Constraints 66 | ############################################################################### 67 | 68 | 69 | ############################################################################### 70 | # Physical Constraints 71 | ############################################################################### 72 | 73 | ############################################################################### 74 | # Timing Constraints 75 | ############################################################################### 76 | 77 | #------------------------- Adding waiver -------------------------# 78 | 79 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/pl_phy_lnk_up_q_reg/R}}] 80 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/user_lnk_up_int_reg/R}}] 81 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/pl_received_hot_rst_q_reg/R}}] 82 | create_waiver -type CDC -id CDC-7 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/bridge_reset_int_reg/PRE}}] 83 | create_waiver -type CDC -id CDC-7 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/user_reset_int_reg/PRE}}] 84 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async sys_reset - safe to ignore" -scope -internal -to [get_pins -hier -filter {NAME =~ {*/inst/user_lnk_up_mux_reg/R}}] 85 | 86 | 87 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async reset - safe to ignore" -scope -internal -from [get_pins -hier -filter {NAME =~ {*pr_loader_i/PIO_FPC_i/tandem_ctl_arb_i/user_app_rdy_gnt_reg/C}}] -to [get_pins -hier -filter {NAME =~ {*/inst/icap_pipeline_i/CSIB_OUT_reg/D}}] 88 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async reset - safe to ignore" -scope -internal -from [get_pins -hier -filter {NAME =~ {*pr_loader_i/PIO_FPC_i/tandem_ctl_arb_i/user_app_rdy_gnt_reg/C}}] -to [get_pins -hier -filter {NAME =~ {*/inst/icap_pipeline_i/I_OUT_reg[*]/D}}] 89 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async reset - safe to ignore" -scope -internal -from [get_pins -hier -filter {NAME =~ {*pr_loader_i/PIO_FPC_i/tandem_ctl_arb_i/user_app_rdy_gnt_reg/C}}] -to [get_pins -hier -filter {NAME =~ {*/inst/icap_pipeline_i/RDWRB_OUT_*/D}}] 90 | create_waiver -type CDC -id CDC-1 -user "pcie_7x" -tags "1165856" -desc "async reset - safe to ignore" -scope -internal -from [get_pins -hier -filter {NAME =~ {*pr_loader_i/PIO_FPC_i/PIO_EP_FPC_inst/data_transfer_i/eoc_1_fd_2dly_reg/C}}] -to [get_pins -hier -filter {NAME =~ {*/pr_loader_i/PIO_FPC_i/PIO_EP_FPC_inst/data_transfer_i/end_config_reg/D}}] 91 | 92 | ############################################################################### 93 | # End 94 | ############################################################################### 95 | -------------------------------------------------------------------------------- /src/pcileech_squirrel_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // Top module for various 35T-484 x1 Artix-7 boards. 5 | // 6 | // (c) Ulf Frisk, 2019-2024 7 | // Author: Ulf Frisk, pcileech@frizk.net 8 | // 9 | 10 | `timescale 1ns / 1ps 11 | `include "pcileech_header.svh" 12 | 13 | module pcileech_squirrel_top #( 14 | parameter PARAM_DEVICE_ID = 4, 15 | parameter PARAM_VERSION_NUMBER_MAJOR = 4, 16 | parameter PARAM_VERSION_NUMBER_MINOR = 13, 17 | parameter PARAM_CUSTOM_VALUE = 32'hffffffff 18 | ) ( 19 | // SYS 20 | input clk, 21 | input ft601_clk, 22 | 23 | // SYSTEM LEDs and BUTTONs 24 | output user_ld1, 25 | output user_ld2, 26 | input user_sw1_n, 27 | input user_sw2_n, 28 | 29 | output ft2232_rst_n, 30 | 31 | // PCI-E FABRIC 32 | output [0:0] pcie_tx_p, 33 | output [0:0] pcie_tx_n, 34 | input [0:0] pcie_rx_p, 35 | input [0:0] pcie_rx_n, 36 | input pcie_clk_p, 37 | input pcie_clk_n, 38 | input pcie_present, 39 | input pcie_perst_n, 40 | output reg pcie_wake_n = 1'b1, 41 | 42 | // TO/FROM FT601 PADS 43 | output ft601_rst_n, 44 | inout [31:0] ft601_data, 45 | output [3:0] ft601_be, 46 | input ft601_rxf_n, 47 | input ft601_txe_n, 48 | output ft601_wr_n, 49 | output ft601_siwu_n, 50 | output ft601_rd_n, 51 | output ft601_oe_n 52 | ); 53 | 54 | // SYS 55 | wire rst; 56 | 57 | // FIFO CTL <--> COM CTL 58 | wire [63:0] com_dout; 59 | wire com_dout_valid; 60 | wire [255:0] com_din; 61 | wire com_din_wr_en; 62 | wire com_din_ready; 63 | wire led_com; 64 | wire led_pcie; 65 | 66 | // FIFO CTL <--> COM CTL 67 | IfComToFifo dcom_fifo(); 68 | 69 | // FIFO CTL <--> PCIe 70 | IfPCIeFifoCfg dcfg(); 71 | IfPCIeFifoTlp dtlp(); 72 | IfPCIeFifoCore dpcie(); 73 | IfShadow2Fifo dshadow2fifo(); 74 | 75 | // ---------------------------------------------------- 76 | // TickCount64 CLK 77 | // ---------------------------------------------------- 78 | 79 | time tickcount64 = 0; 80 | time tickcount64_reload = 0; 81 | always @ ( posedge clk ) begin 82 | tickcount64 <= user_sw2_n ? (tickcount64 + 1) : 0; 83 | tickcount64_reload <= user_sw2_n ? 0 : (tickcount64_reload + 1); 84 | end 85 | 86 | assign rst = ~user_sw2_n || ((tickcount64 < 64) ? 1'b1 : 1'b0); 87 | assign ft601_rst_n = ~rst; 88 | wire led_pwronblink = ~user_sw1_n ^ (tickcount64[24] & (tickcount64[63:27] == 0)); 89 | 90 | OBUF led_ld1_obuf(.O(user_ld1), .I(led_pcie)); 91 | OBUF led_ld2_obuf(.O(user_ld2), .I(led_com)); 92 | OBUF ft2232_rst_obuf(.O(ft2232_rst_n), .I(user_sw2_n)); 93 | 94 | // ---------------------------------------------------- 95 | // BUFFERED COMMUNICATION DEVICE (FT601) 96 | // ---------------------------------------------------- 97 | 98 | pcileech_com i_pcileech_com ( 99 | // SYS 100 | .clk ( clk ), 101 | .clk_com ( ft601_clk ), 102 | .rst ( rst ), 103 | .led_state_txdata ( led_com ), // -> 104 | .led_state_invert ( led_pwronblink ), // <- 105 | // FIFO CTL <--> COM CTL 106 | .dfifo ( dcom_fifo.mp_com ), 107 | // TO/FROM FT601 PADS 108 | .ft601_data ( ft601_data ), // <> [31:0] 109 | .ft601_be ( ft601_be ), // -> [3:0] 110 | .ft601_txe_n ( ft601_txe_n ), // <- 111 | .ft601_rxf_n ( ft601_rxf_n ), // <- 112 | .ft601_siwu_n ( ft601_siwu_n ), // -> 113 | .ft601_wr_n ( ft601_wr_n ), // -> 114 | .ft601_rd_n ( ft601_rd_n ), // -> 115 | .ft601_oe_n ( ft601_oe_n ) // -> 116 | ); 117 | 118 | // ---------------------------------------------------- 119 | // FIFO CTL 120 | // ---------------------------------------------------- 121 | 122 | pcileech_fifo #( 123 | .PARAM_DEVICE_ID ( PARAM_DEVICE_ID ), 124 | .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR ), 125 | .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR ), 126 | .PARAM_CUSTOM_VALUE ( PARAM_CUSTOM_VALUE ) 127 | ) i_pcileech_fifo ( 128 | .clk ( clk ), 129 | .rst ( rst ), 130 | .rst_cfg_reload ( (tickcount64_reload > 500000000) ? 1'b1 : 1'b0 ), // config reload after 5s button press 131 | .pcie_present ( pcie_present ), 132 | .pcie_perst_n ( pcie_perst_n ), 133 | // FIFO CTL <--> COM CTL 134 | .dcom ( dcom_fifo.mp_fifo ), 135 | // FIFO CTL <--> PCIe 136 | .dcfg ( dcfg.mp_fifo ), 137 | .dtlp ( dtlp.mp_fifo ), 138 | .dpcie ( dpcie.mp_fifo ), 139 | .dshadow2fifo ( dshadow2fifo.fifo ) 140 | ); 141 | 142 | // ---------------------------------------------------- 143 | // PCIe 144 | // ---------------------------------------------------- 145 | 146 | pcileech_pcie_a7 i_pcileech_pcie_a7( 147 | .clk_sys ( clk ), 148 | .rst ( rst ), 149 | // PCIe fabric 150 | .pcie_tx_p ( pcie_tx_p ), 151 | .pcie_tx_n ( pcie_tx_n ), 152 | .pcie_rx_p ( pcie_rx_p ), 153 | .pcie_rx_n ( pcie_rx_n ), 154 | .pcie_clk_p ( pcie_clk_p ), 155 | .pcie_clk_n ( pcie_clk_n ), 156 | .pcie_perst_n ( pcie_perst_n ), 157 | // State and Activity LEDs 158 | .led_state ( led_pcie ), 159 | // FIFO CTL <--> PCIe 160 | .dfifo_cfg ( dcfg.mp_pcie ), 161 | .dfifo_tlp ( dtlp.mp_pcie ), 162 | .dfifo_pcie ( dpcie.mp_pcie ), 163 | .dshadow2fifo ( dshadow2fifo.shadow ) 164 | ); 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /src/pcileech_enigma_x1_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // Top module for the Enigma X1 Artix-7 board. 5 | // 6 | // (c) Ulf Frisk, 2019-2024 7 | // Author: Ulf Frisk, pcileech@frizk.net 8 | // 9 | 10 | `timescale 1ns / 1ps 11 | `include "pcileech_header.svh" 12 | 13 | module pcileech_enigma_x1_top #( 14 | // DEVICE IDs as follows: 15 | // 0 = SP605, 1 = PCIeScreamer R1, 2 = AC701, 3 = PCIeScreamer R2, 4 = Screamer, 5 = NeTV2 16 | parameter PARAM_DEVICE_ID = 9, 17 | parameter PARAM_VERSION_NUMBER_MAJOR = 4, 18 | parameter PARAM_VERSION_NUMBER_MINOR = 13, 19 | parameter PARAM_CUSTOM_VALUE = 32'hffffffff 20 | ) ( 21 | // SYS 22 | input clk, 23 | input ft601_clk, 24 | 25 | // SYSTEM LEDs and BUTTONs 26 | output user_ld1_n, 27 | output user_ld2_n, 28 | input user_sw1_n, 29 | input user_sw2_n, 30 | 31 | // PCI-E FABRIC 32 | output [0:0] pcie_tx_p, 33 | output [0:0] pcie_tx_n, 34 | input [0:0] pcie_rx_p, 35 | input [0:0] pcie_rx_n, 36 | input pcie_clk_p, 37 | input pcie_clk_n, 38 | input pcie_present, 39 | input pcie_perst_n, 40 | output reg pcie_wake_n = 1'b1, 41 | 42 | // TO/FROM FT601 PADS 43 | output ft601_rst_n, 44 | 45 | inout [31:0] ft601_data, 46 | output [3:0] ft601_be, 47 | input ft601_rxf_n, 48 | input ft601_txe_n, 49 | output ft601_wr_n, 50 | output ft601_siwu_n, 51 | output ft601_rd_n, 52 | output ft601_oe_n 53 | ); 54 | 55 | // SYS 56 | wire rst; 57 | 58 | // FIFO CTL <--> COM CTL 59 | wire [63:0] com_dout; 60 | wire com_dout_valid; 61 | wire [255:0] com_din; 62 | wire com_din_wr_en; 63 | wire com_din_ready; 64 | wire led_com; 65 | wire led_pcie; 66 | 67 | // FIFO CTL <--> COM CTL 68 | IfComToFifo dcom_fifo(); 69 | 70 | // FIFO CTL <--> PCIe 71 | IfPCIeFifoCfg dcfg(); 72 | IfPCIeFifoTlp dtlp(); 73 | IfPCIeFifoCore dpcie(); 74 | IfShadow2Fifo dshadow2fifo(); 75 | 76 | // ---------------------------------------------------- 77 | // TickCount64 CLK 78 | // ---------------------------------------------------- 79 | 80 | time tickcount64 = 0; 81 | time tickcount64_reload = 0; 82 | always @ ( posedge clk ) begin 83 | tickcount64 <= user_sw2_n ? (tickcount64 + 1) : 0; 84 | tickcount64_reload <= user_sw2_n ? 0 : (tickcount64_reload + 1); 85 | end 86 | 87 | assign rst = ~user_sw2_n || ((tickcount64 < 64) ? 1'b1 : 1'b0); 88 | assign ft601_rst_n = ~rst; 89 | wire led_pwronblink = ~user_sw1_n ^ (tickcount64[24] & (tickcount64[63:27] == 0)); 90 | 91 | OBUF led_ld1_obuf(.O(user_ld1_n), .I(~led_pcie)); 92 | OBUF led_ld2_obuf(.O(user_ld2_n), .I(~led_com)); 93 | 94 | // ---------------------------------------------------- 95 | // BUFFERED COMMUNICATION DEVICE (FT601) 96 | // ---------------------------------------------------- 97 | 98 | pcileech_com i_pcileech_com ( 99 | // SYS 100 | .clk ( clk ), 101 | .clk_com ( ft601_clk ), 102 | .rst ( rst ), 103 | .led_state_txdata ( led_com ), // -> 104 | .led_state_invert ( led_pwronblink ), // <- 105 | // FIFO CTL <--> COM CTL 106 | .dfifo ( dcom_fifo.mp_com ), 107 | // TO/FROM FT601 PADS 108 | .ft601_data ( ft601_data ), // <> [31:0] 109 | .ft601_be ( ft601_be ), // -> [3:0] 110 | .ft601_txe_n ( ft601_txe_n ), // <- 111 | .ft601_rxf_n ( ft601_rxf_n ), // <- 112 | .ft601_siwu_n ( ft601_siwu_n ), // -> 113 | .ft601_wr_n ( ft601_wr_n ), // -> 114 | .ft601_rd_n ( ft601_rd_n ), // -> 115 | .ft601_oe_n ( ft601_oe_n ) // -> 116 | ); 117 | 118 | // ---------------------------------------------------- 119 | // FIFO CTL 120 | // ---------------------------------------------------- 121 | 122 | pcileech_fifo #( 123 | .PARAM_DEVICE_ID ( PARAM_DEVICE_ID ), 124 | .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR ), 125 | .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR ), 126 | .PARAM_CUSTOM_VALUE ( PARAM_CUSTOM_VALUE ) 127 | ) i_pcileech_fifo ( 128 | .clk ( clk ), 129 | .rst ( rst ), 130 | .rst_cfg_reload ( (tickcount64_reload > 500000000) ? 1'b1 : 1'b0 ), // config reload after 5s button press 131 | .pcie_present ( pcie_present ), 132 | .pcie_perst_n ( pcie_perst_n ), 133 | // FIFO CTL <--> COM CTL 134 | .dcom ( dcom_fifo.mp_fifo ), 135 | // FIFO CTL <--> PCIe 136 | .dcfg ( dcfg.mp_fifo ), 137 | .dtlp ( dtlp.mp_fifo ), 138 | .dpcie ( dpcie.mp_fifo ), 139 | .dshadow2fifo ( dshadow2fifo.fifo ) 140 | ); 141 | 142 | // ---------------------------------------------------- 143 | // PCIe 144 | // ---------------------------------------------------- 145 | 146 | pcileech_pcie_a7 i_pcileech_pcie_a7( 147 | .clk_sys ( clk ), 148 | .rst ( rst ), 149 | // PCIe fabric 150 | .pcie_tx_p ( pcie_tx_p ), 151 | .pcie_tx_n ( pcie_tx_n ), 152 | .pcie_rx_p ( pcie_rx_p ), 153 | .pcie_rx_n ( pcie_rx_n ), 154 | .pcie_clk_p ( pcie_clk_p ), 155 | .pcie_clk_n ( pcie_clk_n ), 156 | .pcie_perst_n ( pcie_perst_n ), 157 | // State and Activity LEDs 158 | .led_state ( led_pcie ), 159 | // FIFO CTL <--> PCIe 160 | .dfifo_cfg ( dcfg.mp_pcie ), 161 | .dfifo_tlp ( dtlp.mp_pcie ), 162 | .dfifo_pcie ( dpcie.mp_pcie ), 163 | .dshadow2fifo ( dshadow2fifo.shadow ) 164 | ); 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /src/75immt.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN V20 [get_ports ft601_be[0]] 2 | set_property PACKAGE_PIN V19 [get_ports ft601_be[1]] 3 | set_property PACKAGE_PIN W20 [get_ports ft601_be[2]] 4 | set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]] 5 | set_property PACKAGE_PIN H20 [get_ports ft601_data[0]] 6 | set_property PACKAGE_PIN H22 [get_ports ft601_data[1]] 7 | set_property PACKAGE_PIN J21 [get_ports ft601_data[2]] 8 | set_property PACKAGE_PIN J22 [get_ports ft601_data[3]] 9 | set_property PACKAGE_PIN K21 [get_ports ft601_data[4]] 10 | set_property PACKAGE_PIN K22 [get_ports ft601_data[5]] 11 | set_property PACKAGE_PIN L21 [get_ports ft601_data[6]] 12 | set_property PACKAGE_PIN N18 [get_ports ft601_data[7]] 13 | set_property PACKAGE_PIN M18 [get_ports ft601_data[8]] 14 | set_property PACKAGE_PIN L20 [get_ports ft601_data[9]] 15 | set_property PACKAGE_PIN L19 [get_ports ft601_data[10]] 16 | set_property PACKAGE_PIN M20 [get_ports ft601_data[11]] 17 | set_property PACKAGE_PIN M22 [get_ports ft601_data[12]] 18 | set_property PACKAGE_PIN M21 [get_ports ft601_data[13]] 19 | set_property PACKAGE_PIN N22 [get_ports ft601_data[14]] 20 | set_property PACKAGE_PIN N20 [get_ports ft601_data[15]] 21 | set_property PACKAGE_PIN P15 [get_ports ft601_data[16]] 22 | set_property PACKAGE_PIN T21 [get_ports ft601_data[17]] 23 | set_property PACKAGE_PIN R16 [get_ports ft601_data[18]] 24 | # OLD ft601_data[19] 25 | set_property PACKAGE_PIN T20 [get_ports ft601_data[19]] 26 | 27 | set_property PACKAGE_PIN U17 [get_ports ft601_data[20]] 28 | set_property PACKAGE_PIN U20 [get_ports ft601_data[21]] 29 | set_property PACKAGE_PIN U21 [get_ports ft601_data[22]] 30 | set_property PACKAGE_PIN V22 [get_ports ft601_data[23]] 31 | set_property PACKAGE_PIN W22 [get_ports ft601_data[24]] 32 | set_property PACKAGE_PIN W21 [get_ports ft601_data[25]] 33 | set_property PACKAGE_PIN Y22 [get_ports ft601_data[26]] 34 | set_property PACKAGE_PIN Y21 [get_ports ft601_data[27]] 35 | set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]] 36 | set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]] 37 | set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]] 38 | set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]] 39 | set_property PACKAGE_PIN W17 [get_ports ft601_oe_n] 40 | set_property PACKAGE_PIN P16 [get_ports ft601_rd_n] 41 | set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n] 42 | set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n] 43 | set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n] 44 | set_property PACKAGE_PIN W19 [get_ports ft601_wr_n] 45 | set_property PACKAGE_PIN N13 [get_ports ft601_rst_n] 46 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 49 | set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}] 50 | set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 51 | 52 | set_property PACKAGE_PIN G21 [get_ports user_ld1_n] 53 | set_property PACKAGE_PIN G22 [get_ports user_ld2_n] 54 | set_property PACKAGE_PIN F19 [get_ports user_sw1_n] 55 | set_property PACKAGE_PIN F20 [get_ports user_sw2_n] 56 | set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}] 57 | 58 | # SYSCLK 59 | set_property PACKAGE_PIN J19 [get_ports clk] 60 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 61 | create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk] 62 | 63 | # FT601 CLK 64 | create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk] 65 | set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk] 66 | set_property PACKAGE_PIN K18 [get_ports ft601_clk] 67 | 68 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}] 69 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}] 70 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n] 71 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n] 72 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n] 73 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n] 74 | 75 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 76 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 77 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 78 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 79 | 80 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg] 81 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg] 82 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg] 83 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/txo_dout_reg[*]] 84 | 85 | set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/oe_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}] 86 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 87 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 88 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 89 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 90 | 91 | #PCIe signals 92 | set_property PACKAGE_PIN A13 [get_ports pcie_present] 93 | set_property PACKAGE_PIN C13 [get_ports pcie_perst_n] 94 | set_property PACKAGE_PIN B13 [get_ports pcie_wake_n] 95 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_present] 96 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n] 97 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n] 98 | 99 | set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}] 100 | set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}] 101 | set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}] 102 | set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}] 103 | 104 | set_property PACKAGE_PIN E10 [get_ports pcie_clk_n] 105 | set_property PACKAGE_PIN F10 [get_ports pcie_clk_p] 106 | 107 | create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p] 108 | 109 | set_property CFGBVS Vcco [current_design] 110 | set_property CONFIG_VOLTAGE 3.3 [current_design] 111 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 112 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 113 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 114 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] -------------------------------------------------------------------------------- /src/pcileech_captain_75T.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN V20 [get_ports ft601_be[0]] 2 | set_property PACKAGE_PIN V19 [get_ports ft601_be[1]] 3 | set_property PACKAGE_PIN W20 [get_ports ft601_be[2]] 4 | set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]] 5 | set_property PACKAGE_PIN H20 [get_ports ft601_data[0]] 6 | set_property PACKAGE_PIN H22 [get_ports ft601_data[1]] 7 | set_property PACKAGE_PIN J21 [get_ports ft601_data[2]] 8 | set_property PACKAGE_PIN J22 [get_ports ft601_data[3]] 9 | set_property PACKAGE_PIN K21 [get_ports ft601_data[4]] 10 | set_property PACKAGE_PIN K22 [get_ports ft601_data[5]] 11 | set_property PACKAGE_PIN L21 [get_ports ft601_data[6]] 12 | set_property PACKAGE_PIN N18 [get_ports ft601_data[7]] 13 | set_property PACKAGE_PIN M18 [get_ports ft601_data[8]] 14 | set_property PACKAGE_PIN L20 [get_ports ft601_data[9]] 15 | set_property PACKAGE_PIN L19 [get_ports ft601_data[10]] 16 | set_property PACKAGE_PIN M20 [get_ports ft601_data[11]] 17 | set_property PACKAGE_PIN M22 [get_ports ft601_data[12]] 18 | set_property PACKAGE_PIN M21 [get_ports ft601_data[13]] 19 | set_property PACKAGE_PIN N22 [get_ports ft601_data[14]] 20 | set_property PACKAGE_PIN N20 [get_ports ft601_data[15]] 21 | set_property PACKAGE_PIN P15 [get_ports ft601_data[16]] 22 | set_property PACKAGE_PIN T21 [get_ports ft601_data[17]] 23 | set_property PACKAGE_PIN R16 [get_ports ft601_data[18]] 24 | # OLD ft601_data[19] 25 | set_property PACKAGE_PIN T20 [get_ports ft601_data[19]] 26 | # NEW ft601_data[19] 27 | # set_property PACKAGE_PIN T18 [get_ports ft601_data[19]] 28 | set_property PACKAGE_PIN U17 [get_ports ft601_data[20]] 29 | set_property PACKAGE_PIN U20 [get_ports ft601_data[21]] 30 | set_property PACKAGE_PIN U21 [get_ports ft601_data[22]] 31 | set_property PACKAGE_PIN V22 [get_ports ft601_data[23]] 32 | set_property PACKAGE_PIN W22 [get_ports ft601_data[24]] 33 | set_property PACKAGE_PIN W21 [get_ports ft601_data[25]] 34 | set_property PACKAGE_PIN Y22 [get_ports ft601_data[26]] 35 | set_property PACKAGE_PIN Y21 [get_ports ft601_data[27]] 36 | set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]] 37 | set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]] 38 | set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]] 39 | set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]] 40 | set_property PACKAGE_PIN W17 [get_ports ft601_oe_n] 41 | set_property PACKAGE_PIN P16 [get_ports ft601_rd_n] 42 | set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n] 43 | set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n] 44 | set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n] 45 | set_property PACKAGE_PIN W19 [get_ports ft601_wr_n] 46 | set_property PACKAGE_PIN N13 [get_ports ft601_rst_n] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 50 | set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}] 51 | set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 52 | 53 | set_property PACKAGE_PIN G21 [get_ports user_ld1_n] 54 | set_property PACKAGE_PIN G22 [get_ports user_ld2_n] 55 | set_property PACKAGE_PIN F19 [get_ports user_sw1_n] 56 | set_property PACKAGE_PIN F20 [get_ports user_sw2_n] 57 | set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}] 58 | 59 | # SYSCLK 60 | set_property PACKAGE_PIN J19 [get_ports clk] 61 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 62 | create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk] 63 | 64 | # FT601 CLK 65 | create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk] 66 | set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk] 67 | set_property PACKAGE_PIN K18 [get_ports ft601_clk] 68 | 69 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}] 70 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}] 71 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n] 72 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n] 73 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n] 74 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n] 75 | 76 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 77 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 78 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 79 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 80 | 81 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg] 82 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg] 83 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg] 84 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]] 85 | 86 | set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}] 87 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 88 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 89 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 90 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 91 | 92 | #PCIe signals 93 | set_property PACKAGE_PIN A13 [get_ports pcie_present] 94 | set_property PACKAGE_PIN C13 [get_ports pcie_perst_n] 95 | set_property PACKAGE_PIN B13 [get_ports pcie_wake_n] 96 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_present] 97 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n] 98 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n] 99 | 100 | set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}] 101 | set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}] 102 | set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}] 103 | set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}] 104 | 105 | set_property PACKAGE_PIN E10 [get_ports pcie_clk_n] 106 | set_property PACKAGE_PIN F10 [get_ports pcie_clk_p] 107 | 108 | create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p] 109 | 110 | set_property CFGBVS Vcco [current_design] 111 | set_property CONFIG_VOLTAGE 3.3 [current_design] 112 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 113 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 114 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 115 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] -------------------------------------------------------------------------------- /src/pcileech_enigma_x1.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN V20 [get_ports ft601_be[0]] 2 | set_property PACKAGE_PIN V19 [get_ports ft601_be[1]] 3 | set_property PACKAGE_PIN W20 [get_ports ft601_be[2]] 4 | set_property PACKAGE_PIN AB20 [get_ports ft601_be[3]] 5 | set_property PACKAGE_PIN H20 [get_ports ft601_data[0]] 6 | set_property PACKAGE_PIN H22 [get_ports ft601_data[1]] 7 | set_property PACKAGE_PIN J21 [get_ports ft601_data[2]] 8 | set_property PACKAGE_PIN J22 [get_ports ft601_data[3]] 9 | set_property PACKAGE_PIN K21 [get_ports ft601_data[4]] 10 | set_property PACKAGE_PIN K22 [get_ports ft601_data[5]] 11 | set_property PACKAGE_PIN L21 [get_ports ft601_data[6]] 12 | set_property PACKAGE_PIN N18 [get_ports ft601_data[7]] 13 | set_property PACKAGE_PIN M18 [get_ports ft601_data[8]] 14 | set_property PACKAGE_PIN L20 [get_ports ft601_data[9]] 15 | set_property PACKAGE_PIN L19 [get_ports ft601_data[10]] 16 | set_property PACKAGE_PIN M20 [get_ports ft601_data[11]] 17 | set_property PACKAGE_PIN M22 [get_ports ft601_data[12]] 18 | set_property PACKAGE_PIN M21 [get_ports ft601_data[13]] 19 | set_property PACKAGE_PIN N22 [get_ports ft601_data[14]] 20 | set_property PACKAGE_PIN N20 [get_ports ft601_data[15]] 21 | set_property PACKAGE_PIN P15 [get_ports ft601_data[16]] 22 | set_property PACKAGE_PIN T21 [get_ports ft601_data[17]] 23 | set_property PACKAGE_PIN R16 [get_ports ft601_data[18]] 24 | # OLD ft601_data[19] 25 | #set_property PACKAGE_PIN T20 [get_ports ft601_data[19]] 26 | # NEW ft601_data[19] 27 | set_property PACKAGE_PIN T18 [get_ports ft601_data[19]] 28 | set_property PACKAGE_PIN U17 [get_ports ft601_data[20]] 29 | set_property PACKAGE_PIN U20 [get_ports ft601_data[21]] 30 | set_property PACKAGE_PIN U21 [get_ports ft601_data[22]] 31 | set_property PACKAGE_PIN V22 [get_ports ft601_data[23]] 32 | set_property PACKAGE_PIN W22 [get_ports ft601_data[24]] 33 | set_property PACKAGE_PIN W21 [get_ports ft601_data[25]] 34 | set_property PACKAGE_PIN Y22 [get_ports ft601_data[26]] 35 | set_property PACKAGE_PIN Y21 [get_ports ft601_data[27]] 36 | set_property PACKAGE_PIN AB22 [get_ports ft601_data[28]] 37 | set_property PACKAGE_PIN AA21 [get_ports ft601_data[29]] 38 | set_property PACKAGE_PIN AB21 [get_ports ft601_data[30]] 39 | set_property PACKAGE_PIN AA20 [get_ports ft601_data[31]] 40 | set_property PACKAGE_PIN W17 [get_ports ft601_oe_n] 41 | set_property PACKAGE_PIN P16 [get_ports ft601_rd_n] 42 | set_property PACKAGE_PIN AA18 [get_ports ft601_rxf_n] 43 | set_property PACKAGE_PIN AB18 [get_ports ft601_siwu_n] 44 | set_property PACKAGE_PIN AA19 [get_ports ft601_txe_n] 45 | set_property PACKAGE_PIN W19 [get_ports ft601_wr_n] 46 | set_property PACKAGE_PIN N13 [get_ports ft601_rst_n] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}] 48 | set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 50 | set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}] 51 | set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 52 | 53 | set_property PACKAGE_PIN G21 [get_ports user_ld1_n] 54 | set_property PACKAGE_PIN G22 [get_ports user_ld2_n] 55 | set_property PACKAGE_PIN F19 [get_ports user_sw1_n] 56 | set_property PACKAGE_PIN F20 [get_ports user_sw2_n] 57 | set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1_n user_ld2_n user_sw1_n user_sw2_n}] 58 | 59 | # SYSCLK 60 | set_property PACKAGE_PIN J19 [get_ports clk] 61 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 62 | create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk] 63 | 64 | # FT601 CLK 65 | create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk] 66 | set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk] 67 | set_property PACKAGE_PIN K18 [get_ports ft601_clk] 68 | 69 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}] 70 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}] 71 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n] 72 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n] 73 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n] 74 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n] 75 | 76 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 77 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 78 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 79 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 80 | 81 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg] 82 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg] 83 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg] 84 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]] 85 | 86 | set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}] 87 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 88 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 89 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 90 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 91 | 92 | #PCIe signals 93 | set_property PACKAGE_PIN A13 [get_ports pcie_present] 94 | set_property PACKAGE_PIN C13 [get_ports pcie_perst_n] 95 | set_property PACKAGE_PIN B13 [get_ports pcie_wake_n] 96 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_present] 97 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n] 98 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n] 99 | 100 | set_property PACKAGE_PIN C9 [get_ports {pcie_rx_n[0]}] 101 | set_property PACKAGE_PIN D9 [get_ports {pcie_rx_p[0]}] 102 | set_property PACKAGE_PIN C7 [get_ports {pcie_tx_n[0]}] 103 | set_property PACKAGE_PIN D7 [get_ports {pcie_tx_p[0]}] 104 | 105 | set_property PACKAGE_PIN E10 [get_ports pcie_clk_n] 106 | set_property PACKAGE_PIN F10 [get_ports pcie_clk_p] 107 | 108 | create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p] 109 | 110 | set_property CFGBVS Vcco [current_design] 111 | set_property CONFIG_VOLTAGE 3.3 [current_design] 112 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 113 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 114 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 115 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] -------------------------------------------------------------------------------- /src/pcileech_squirrel.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN Y18 [get_ports ft601_be[0]] 2 | set_property PACKAGE_PIN AA18 [get_ports ft601_be[1]] 3 | set_property PACKAGE_PIN AB18 [get_ports ft601_be[2]] 4 | set_property PACKAGE_PIN W17 [get_ports ft601_be[3]] 5 | set_property PACKAGE_PIN N13 [get_ports ft601_data[0]] 6 | set_property PACKAGE_PIN N14 [get_ports ft601_data[1]] 7 | set_property PACKAGE_PIN N15 [get_ports ft601_data[2]] 8 | set_property PACKAGE_PIN P15 [get_ports ft601_data[3]] 9 | set_property PACKAGE_PIN P16 [get_ports ft601_data[4]] 10 | set_property PACKAGE_PIN N17 [get_ports ft601_data[5]] 11 | set_property PACKAGE_PIN P17 [get_ports ft601_data[6]] 12 | set_property PACKAGE_PIN R17 [get_ports ft601_data[7]] 13 | set_property PACKAGE_PIN P19 [get_ports ft601_data[8]] 14 | set_property PACKAGE_PIN R18 [get_ports ft601_data[9]] 15 | set_property PACKAGE_PIN R19 [get_ports ft601_data[10]] 16 | set_property PACKAGE_PIN T18 [get_ports ft601_data[11]] 17 | set_property PACKAGE_PIN U18 [get_ports ft601_data[12]] 18 | set_property PACKAGE_PIN V18 [get_ports ft601_data[13]] 19 | set_property PACKAGE_PIN V19 [get_ports ft601_data[14]] 20 | set_property PACKAGE_PIN V17 [get_ports ft601_data[15]] 21 | set_property PACKAGE_PIN W20 [get_ports ft601_data[16]] 22 | set_property PACKAGE_PIN Y19 [get_ports ft601_data[17]] 23 | set_property PACKAGE_PIN T21 [get_ports ft601_data[18]] 24 | set_property PACKAGE_PIN T20 [get_ports ft601_data[19]] 25 | set_property PACKAGE_PIN U21 [get_ports ft601_data[20]] 26 | set_property PACKAGE_PIN V20 [get_ports ft601_data[21]] 27 | set_property PACKAGE_PIN W22 [get_ports ft601_data[22]] 28 | set_property PACKAGE_PIN W21 [get_ports ft601_data[23]] 29 | set_property PACKAGE_PIN Y22 [get_ports ft601_data[24]] 30 | set_property PACKAGE_PIN Y21 [get_ports ft601_data[25]] 31 | set_property PACKAGE_PIN AA21 [get_ports ft601_data[26]] 32 | set_property PACKAGE_PIN AB22 [get_ports ft601_data[27]] 33 | set_property PACKAGE_PIN AA20 [get_ports ft601_data[28]] 34 | set_property PACKAGE_PIN AB21 [get_ports ft601_data[29]] 35 | set_property PACKAGE_PIN AA19 [get_ports ft601_data[30]] 36 | set_property PACKAGE_PIN AB20 [get_ports ft601_data[31]] 37 | set_property PACKAGE_PIN AB6 [get_ports ft601_oe_n] 38 | set_property PACKAGE_PIN AA6 [get_ports ft601_rd_n] 39 | set_property PACKAGE_PIN AB8 [get_ports ft601_rxf_n] 40 | set_property PACKAGE_PIN Y8 [get_ports ft601_siwu_n] 41 | set_property PACKAGE_PIN AA8 [get_ports ft601_txe_n] 42 | set_property PACKAGE_PIN AB7 [get_ports ft601_wr_n] 43 | set_property PACKAGE_PIN Y9 [get_ports ft601_rst_n] 44 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}] 45 | set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 46 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 47 | set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}] 48 | set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 49 | 50 | set_property PACKAGE_PIN Y6 [get_ports user_ld1] 51 | set_property PACKAGE_PIN AB5 [get_ports user_ld2] 52 | set_property PACKAGE_PIN AB3 [get_ports user_sw1_n] 53 | set_property PACKAGE_PIN AA5 [get_ports user_sw2_n] 54 | set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1 user_ld2 user_sw1_n user_sw2_n}] 55 | 56 | set_property PACKAGE_PIN F21 [get_ports ft2232_rst_n] 57 | set_property IOSTANDARD LVCMOS33 [get_ports ft2232_rst_n] 58 | 59 | # SYSCLK 60 | set_property PACKAGE_PIN H4 [get_ports clk] 61 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 62 | create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk] 63 | 64 | # FT601 CLK 65 | create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk] 66 | set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk] 67 | set_property PACKAGE_PIN W19 [get_ports ft601_clk] 68 | 69 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}] 70 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}] 71 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n] 72 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n] 73 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n] 74 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n] 75 | 76 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 77 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 78 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 79 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 80 | 81 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg] 82 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg] 83 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg] 84 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]] 85 | 86 | set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}] 87 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 88 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 89 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 90 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 91 | 92 | #PCIe signals 93 | set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells {i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 94 | set_property PACKAGE_PIN A13 [get_ports pcie_present] 95 | set_property PACKAGE_PIN B13 [get_ports pcie_perst_n] 96 | set_property PACKAGE_PIN A14 [get_ports pcie_wake_n] 97 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_present] 98 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n] 99 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n] 100 | 101 | set_property PACKAGE_PIN A10 [get_ports {pcie_rx_n[0]}] 102 | set_property PACKAGE_PIN B10 [get_ports {pcie_rx_p[0]}] 103 | set_property PACKAGE_PIN A6 [get_ports {pcie_tx_n[0]}] 104 | set_property PACKAGE_PIN B6 [get_ports {pcie_tx_p[0]}] 105 | 106 | set_property PACKAGE_PIN E6 [get_ports pcie_clk_n] 107 | set_property PACKAGE_PIN F6 [get_ports pcie_clk_p] 108 | 109 | create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p] 110 | 111 | set_property CFGBVS Vcco [current_design] 112 | set_property CONFIG_VOLTAGE 3.3 [current_design] 113 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 114 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 115 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 116 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] -------------------------------------------------------------------------------- /src/pcileech_tbx4_100t_top.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // Top module for PCILeech TB x4 5 | // 6 | // (c) Ulf Frisk, 2019-2024 7 | // Author: Ulf Frisk, pcileech@frizk.net 8 | // 9 | 10 | `timescale 1ns / 1ps 11 | `include "pcileech_header.svh" 12 | 13 | module pcileech_tbx4_100t_top #( 14 | // DEVICE IDs as follows: 15 | parameter PARAM_DEVICE_ID = 17, 16 | parameter PARAM_VERSION_NUMBER_MAJOR = 4, 17 | parameter PARAM_VERSION_NUMBER_MINOR = 15, 18 | parameter PARAM_CUSTOM_VALUE = 32'hffffffff, 19 | parameter POWER_SW_MODE = 0, // disable_pcie_on_thunderbolt_noconnect_not_enabled(0), disable_pcie_on_thunderbolt_noconnect_enabled(1) 20 | parameter POWER_SW_TIME = 60*125_000_000 // detection sample time in ticks of 125MHz (125M=1s) 21 | ) ( 22 | // SYS 23 | input clk_in, 24 | 25 | // SYSTEM LEDs and BUTTONs 26 | output pcie_led, 27 | input power_sw, 28 | 29 | // TO/FROM FPGA IO BRIDGE 30 | input [36:0] BUS_DO, 31 | output [68:0] BUS_DI, 32 | input BUS_DI_PROG_FULL, 33 | 34 | // PCI-E FABRIC 35 | output [3:0] pcie_tx_p, 36 | output [3:0] pcie_tx_n, 37 | input [3:0] pcie_rx_p, 38 | input [3:0] pcie_rx_n, 39 | input pcie_clk_p, 40 | input pcie_clk_n, 41 | input pcie_present1, 42 | input pcie_present2, 43 | input pcie_perst1_n, 44 | input pcie_perst2_n 45 | ); 46 | 47 | // SYS 48 | wire rst; 49 | wire clk; 50 | wire clk_com; 51 | reg rst_sw = 0; 52 | 53 | // FIFO CTL <--> COM CTL 54 | wire [63:0] com_dout; 55 | wire com_dout_valid; 56 | wire [255:0] com_din; 57 | wire com_din_wr_en; 58 | wire com_din_ready; 59 | 60 | // FIFO CTL <--> COM CTL 61 | IfComToFifo dcom_fifo(); 62 | 63 | // FIFO CTL <--> PCIe 64 | IfPCIeFifoCfg dcfg(); 65 | IfPCIeFifoTlp dtlp(); 66 | IfPCIeFifoCore dpcie(); 67 | IfShadow2Fifo dshadow2fifo(); 68 | 69 | // PCIe 70 | wire pcie_present = pcie_present1 && pcie_present2; 71 | wire pcie_perst_n = pcie_perst1_n && pcie_perst2_n && ~rst_sw; 72 | 73 | // ---------------------------------------------------- 74 | // CLK: INPUT (clkin): 50MHz 75 | // COM (clk_com): 250MHz 76 | // SYS (clk): 125MHz 77 | // ---------------------------------------------------- 78 | 79 | wire clk_locked, clk_out1, clk_out2; 80 | clk_wiz_0 i_clk_wiz_0( 81 | .clk_in1 ( clk_in ), // <- 50MHz 82 | .clk_out1 ( clk_out1 ), // -> 250MHz 83 | .clk_out2 ( clk_out2 ), // -> 125MHz 84 | .locked ( clk_locked ) 85 | ); 86 | 87 | BUFG i_BUFG_1 ( .I( clk_locked ? clk_out1 : clk_in ), .O( clk_com ) ); 88 | BUFG i_BUFG_2 ( .I( clk_locked ? clk_out2 : clk_in ), .O( clk ) ); 89 | 90 | // ---------------------------------------------------- 91 | // TickCount64 CLK 92 | // ---------------------------------------------------- 93 | 94 | time tickcount64 = 0; 95 | always @ ( posedge clk ) 96 | tickcount64 <= tickcount64 + 1; 97 | assign rst = (tickcount64 < 64) ? 1'b1 : 1'b0; 98 | 99 | wire led_pcie; 100 | OBUF led_ld1_obuf(.O(pcie_led), .I(led_pcie)); 101 | 102 | // ---------------------------------------------------- 103 | // POWER SWITCH MODE (DISABLE PCIE WHEN THUNDERBOLT NOT CONNECTED) 104 | // ---------------------------------------------------- 105 | 106 | always @ ( posedge clk ) begin 107 | if ( rst ) begin 108 | rst_sw <= 0; 109 | end 110 | else if ( (POWER_SW_MODE == 1) && (tickcount64 == POWER_SW_TIME) ) begin 111 | rst_sw <= ~power_sw; 112 | end 113 | end 114 | 115 | // ---------------------------------------------------- 116 | // BUFFERED COMMUNICATION DEVICE (FPGA IO BRIDGE) 117 | // ---------------------------------------------------- 118 | 119 | pcileech_com i_pcileech_com ( 120 | // SYS 121 | .clk ( clk ), 122 | .clk_com ( clk_com ), 123 | .rst ( rst ), 124 | // TO/FROM FPGA IO BRIDGE 125 | .BUS_DO ( BUS_DO ), 126 | .BUS_DI ( BUS_DI ), 127 | .BUS_DI_PROG_FULL ( BUS_DI_PROG_FULL ), 128 | // FIFO CTL <--> COM CTL 129 | .com_dout ( dcom_fifo.com_dout ), 130 | .com_dout_valid ( dcom_fifo.com_dout_valid ), 131 | .com_din_ready ( dcom_fifo.com_din_ready ), 132 | .com_din ( dcom_fifo.com_din ), 133 | .com_din_wr_en ( dcom_fifo.com_din_wr_en ) 134 | ); 135 | 136 | // ---------------------------------------------------- 137 | // FIFO CTL 138 | // ---------------------------------------------------- 139 | 140 | pcileech_fifo #( 141 | .PARAM_DEVICE_ID ( PARAM_DEVICE_ID ), 142 | .PARAM_VERSION_NUMBER_MAJOR ( PARAM_VERSION_NUMBER_MAJOR ), 143 | .PARAM_VERSION_NUMBER_MINOR ( PARAM_VERSION_NUMBER_MINOR ), 144 | .PARAM_CUSTOM_VALUE ( PARAM_CUSTOM_VALUE ) 145 | ) i_pcileech_fifo ( 146 | .clk ( clk ), 147 | .rst ( rst ), 148 | .rst_cfg_reload ( 1'b0 ), 149 | .pcie_present ( pcie_present ), 150 | .pcie_perst_n ( pcie_perst_n ), 151 | // FIFO CTL <--> COM CTL 152 | .dcom ( dcom_fifo.mp_fifo ), 153 | // FIFO CTL <--> PCIe 154 | .dcfg ( dcfg.mp_fifo ), 155 | .dtlp ( dtlp.mp_fifo ), 156 | .dpcie ( dpcie.mp_fifo ), 157 | .dshadow2fifo ( dshadow2fifo.fifo ) 158 | ); 159 | 160 | // ---------------------------------------------------- 161 | // PCIe 162 | // ---------------------------------------------------- 163 | 164 | pcileech_pcie_a7x4 i_pcileech_pcie_a7x4( 165 | .clk_sys ( clk ), 166 | .rst ( rst ), 167 | // PCIe fabric 168 | .pcie_tx_p ( pcie_tx_p ), 169 | .pcie_tx_n ( pcie_tx_n ), 170 | .pcie_rx_p ( pcie_rx_p ), 171 | .pcie_rx_n ( pcie_rx_n ), 172 | .pcie_clk_p ( pcie_clk_p ), 173 | .pcie_clk_n ( pcie_clk_n ), 174 | .pcie_perst_n ( pcie_perst_n ), 175 | // State and Activity LEDs 176 | .led_state ( led_pcie ), 177 | // FIFO CTL <--> PCIe 178 | .dfifo_cfg ( dcfg.mp_pcie ), 179 | .dfifo_tlp ( dtlp.mp_pcie ), 180 | .dfifo_pcie ( dpcie.mp_pcie ), 181 | .dshadow2fifo ( dshadow2fifo.shadow ) 182 | ); 183 | 184 | endmodule -------------------------------------------------------------------------------- /src/pcileech_screamer_m2.xdc: -------------------------------------------------------------------------------- 1 | set_property PACKAGE_PIN L18 [get_ports {ft601_be[0]}] 2 | set_property PACKAGE_PIN M17 [get_ports {ft601_be[1]}] 3 | set_property PACKAGE_PIN N18 [get_ports {ft601_be[2]}] 4 | set_property PACKAGE_PIN N17 [get_ports {ft601_be[3]}] 5 | set_property PACKAGE_PIN B9 [get_ports {ft601_data[0]}] 6 | set_property PACKAGE_PIN A9 [get_ports {ft601_data[1]}] 7 | set_property PACKAGE_PIN C9 [get_ports {ft601_data[2]}] 8 | set_property PACKAGE_PIN A10 [get_ports {ft601_data[3]}] 9 | set_property PACKAGE_PIN B10 [get_ports {ft601_data[4]}] 10 | set_property PACKAGE_PIN B11 [get_ports {ft601_data[5]}] 11 | set_property PACKAGE_PIN A12 [get_ports {ft601_data[6]}] 12 | set_property PACKAGE_PIN B12 [get_ports {ft601_data[7]}] 13 | set_property PACKAGE_PIN A13 [get_ports {ft601_data[8]}] 14 | set_property PACKAGE_PIN A14 [get_ports {ft601_data[9]}] 15 | set_property PACKAGE_PIN B14 [get_ports {ft601_data[10]}] 16 | set_property PACKAGE_PIN A15 [get_ports {ft601_data[11]}] 17 | set_property PACKAGE_PIN B15 [get_ports {ft601_data[12]}] 18 | set_property PACKAGE_PIN B16 [get_ports {ft601_data[13]}] 19 | set_property PACKAGE_PIN A17 [get_ports {ft601_data[14]}] 20 | set_property PACKAGE_PIN B17 [get_ports {ft601_data[15]}] 21 | set_property PACKAGE_PIN C17 [get_ports {ft601_data[16]}] 22 | set_property PACKAGE_PIN C18 [get_ports {ft601_data[17]}] 23 | set_property PACKAGE_PIN D18 [get_ports {ft601_data[18]}] 24 | set_property PACKAGE_PIN E17 [get_ports {ft601_data[19]}] 25 | set_property PACKAGE_PIN E18 [get_ports {ft601_data[20]}] 26 | set_property PACKAGE_PIN E16 [get_ports {ft601_data[21]}] 27 | set_property PACKAGE_PIN F18 [get_ports {ft601_data[22]}] 28 | set_property PACKAGE_PIN F17 [get_ports {ft601_data[23]}] 29 | set_property PACKAGE_PIN G17 [get_ports {ft601_data[24]}] 30 | set_property PACKAGE_PIN H18 [get_ports {ft601_data[25]}] 31 | set_property PACKAGE_PIN D13 [get_ports {ft601_data[26]}] 32 | set_property PACKAGE_PIN C14 [get_ports {ft601_data[27]}] 33 | set_property PACKAGE_PIN D14 [get_ports {ft601_data[28]}] 34 | set_property PACKAGE_PIN D15 [get_ports {ft601_data[29]}] 35 | set_property PACKAGE_PIN C16 [get_ports {ft601_data[30]}] 36 | set_property PACKAGE_PIN D16 [get_ports {ft601_data[31]}] 37 | set_property PACKAGE_PIN T15 [get_ports ft601_oe_n] 38 | set_property PACKAGE_PIN R16 [get_ports ft601_rd_n] 39 | set_property PACKAGE_PIN R18 [get_ports ft601_rxf_n] 40 | set_property PACKAGE_PIN R17 [get_ports ft601_siwu_n] 41 | set_property PACKAGE_PIN P18 [get_ports ft601_txe_n] 42 | set_property PACKAGE_PIN T18 [get_ports ft601_wr_n] 43 | set_property PACKAGE_PIN U15 [get_ports ft601_rst_n] 44 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_txe_n ft601_rxf_n}] 45 | set_property IOSTANDARD LVCMOS33 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 46 | set_property IOSTANDARD LVCMOS33 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 47 | set_property SLEW FAST [get_ports {{ft601_be[*]} {ft601_data[*]}}] 48 | set_property SLEW FAST [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n ft601_siwu_n ft601_rst_n}] 49 | 50 | set_property PACKAGE_PIN V17 [get_ports user_ld1] 51 | set_property PACKAGE_PIN U17 [get_ports user_ld2] 52 | set_property IOSTANDARD LVCMOS33 [get_ports {user_ld1 user_ld2}] 53 | 54 | # SYSCLK 55 | set_property PACKAGE_PIN R2 [get_ports clk] 56 | set_property IOSTANDARD LVCMOS33 [get_ports clk] 57 | create_clock -period 10.000 -name net_clk -waveform {0.000 5.000} [get_ports clk] 58 | 59 | # FT601 CLK 60 | create_clock -period 10.000 -name net_ft601_clk -waveform {0.000 5.000} [get_ports ft601_clk] 61 | set_property IOSTANDARD LVCMOS33 [get_ports ft601_clk] 62 | set_property PACKAGE_PIN E13 [get_ports ft601_clk] 63 | 64 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports {ft601_data[*]}] 65 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports {ft601_data[*]}] 66 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_rxf_n] 67 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_rxf_n] 68 | set_input_delay -clock [get_clocks net_ft601_clk] -min 6.5 [get_ports ft601_txe_n] 69 | set_input_delay -clock [get_clocks net_ft601_clk] -max 7.0 [get_ports ft601_txe_n] 70 | 71 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 72 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {ft601_wr_n ft601_rd_n ft601_oe_n}] 73 | set_output_delay -clock [get_clocks net_ft601_clk] -max 1.0 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 74 | set_output_delay -clock [get_clocks net_ft601_clk] -min 4.8 [get_ports {{ft601_be[*]} {ft601_data[*]}}] 75 | 76 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_OE_N_reg] 77 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_RD_N_reg] 78 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_WR_N_reg] 79 | set_property IOB TRUE [get_cells i_pcileech_com/i_pcileech_ft601/FT601_DATA_OUT_reg[0][*]] 80 | 81 | set_multicycle_path 2 -from [get_pins i_pcileech_com/i_pcileech_ft601/OE_reg/C] -to [get_ports {{ft601_be[*]} {ft601_data[*]}}] 82 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 83 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 84 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 85 | set_false_path -from [get_pins i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 86 | 87 | #PCIe signals 88 | set_property PACKAGE_PIN K1 [get_ports pcie_present] 89 | set_property PACKAGE_PIN M1 [get_ports pcie_perst_n] 90 | set_property PACKAGE_PIN L2 [get_ports pcie_wake_n] 91 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_present] 92 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_perst_n] 93 | set_property IOSTANDARD LVCMOS33 [get_ports pcie_wake_n] 94 | 95 | set_property LOC GTPE2_CHANNEL_X0Y2 [get_cells {i_pcileech_pcie_a7/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 96 | set_property PACKAGE_PIN E3 [get_ports pcie_rx_n[0]] 97 | set_property PACKAGE_PIN E4 [get_ports pcie_rx_p[0]] 98 | set_property PACKAGE_PIN H1 [get_ports pcie_tx_n[0]] 99 | set_property PACKAGE_PIN H2 [get_ports pcie_tx_p[0]] 100 | 101 | #set_property PACKAGE_PIN A3 [get_ports pcie_rx_n[1]] 102 | #set_property PACKAGE_PIN A4 [get_ports pcie_rx_p[1]] 103 | #set_property PACKAGE_PIN F1 [get_ports pcie_tx_n[1]] 104 | #set_property PACKAGE_PIN F2 [get_ports pcie_tx_p[1]] 105 | 106 | #set_property PACKAGE_PIN C3 [get_ports pcie_rx_n[2]] 107 | #set_property PACKAGE_PIN C4 [get_ports pcie_rx_p[2]] 108 | #set_property PACKAGE_PIN D1 [get_ports pcie_tx_n[2]] 109 | #set_property PACKAGE_PIN D2 [get_ports pcie_tx_p[2]] 110 | 111 | #set_property PACKAGE_PIN G3 [get_ports pcie_rx_n[3]] 112 | #set_property PACKAGE_PIN G4 [get_ports pcie_rx_p[3]] 113 | #set_property PACKAGE_PIN B1 [get_ports pcie_tx_n[3]] 114 | #set_property PACKAGE_PIN B2 [get_ports pcie_tx_p[3]] 115 | 116 | set_property PACKAGE_PIN D5 [get_ports pcie_clk_n] 117 | set_property PACKAGE_PIN D6 [get_ports pcie_clk_p] 118 | 119 | create_clock -name pcie_sys_clk_p -period 10.0 [get_nets pcie_clk_p] 120 | 121 | set_property CFGBVS Vcco [current_design] 122 | set_property CONFIG_VOLTAGE 3.3 [current_design] 123 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 124 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 125 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 126 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] 127 | -------------------------------------------------------------------------------- /src/pcileech_mux.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // Merge multiple 32-bit words into a 256-bit word consisting of one (1) 32-bit 5 | // status word and seven (7) data words. This is done to enable relatively 6 | // efficient transmission over the FT601 together with some additional info. 7 | // 8 | // (c) Ulf Frisk, 2017-2024 9 | // Author: Ulf Frisk, pcileech@frizk.net 10 | // 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module pcileech_mux( 15 | input clk, 16 | input rst, 17 | // output 18 | output [255:0] dout, 19 | output valid, 20 | input rd_en, 21 | // port0: input highest priority 22 | input [31:0] p0_din, 23 | input [1:0] p0_tag, 24 | input [1:0] p0_ctx, 25 | input p0_wr_en, 26 | output p0_req_data, 27 | // port1: 28 | input [31:0] p1_din, 29 | input [1:0] p1_tag, 30 | input [1:0] p1_ctx, 31 | input p1_wr_en, 32 | output p1_req_data, 33 | // port2: 34 | input [31:0] p2_din, 35 | input [1:0] p2_tag, 36 | input [1:0] p2_ctx, 37 | input p2_wr_en, 38 | output p2_req_data, 39 | // port3: 40 | input [31:0] p3_din, 41 | input [1:0] p3_tag, 42 | input [1:0] p3_ctx, 43 | input p3_wr_en, 44 | output p3_req_data, 45 | // port4: 46 | input [31:0] p4_din, 47 | input [1:0] p4_tag, 48 | input [1:0] p4_ctx, 49 | input p4_wr_en, 50 | output p4_req_data, 51 | // port5: 52 | input [31:0] p5_din, 53 | input [1:0] p5_tag, 54 | input [1:0] p5_ctx, 55 | input p5_wr_en, 56 | output p5_req_data, 57 | // port6: 58 | input [31:0] p6_din, 59 | input [1:0] p6_tag, 60 | input [1:0] p6_ctx, 61 | input p6_wr_en, 62 | output p6_req_data, 63 | // port7: 64 | input [31:0] p7_din, 65 | input [1:0] p7_tag, 66 | input [1:0] p7_ctx, 67 | input p7_wr_en, 68 | output p7_req_data 69 | ); 70 | 71 | // 'en' is delayed 1CLK so it's in synch with inputs. 72 | // output integrity is handled by extra register. 73 | reg en; 74 | always @ ( posedge clk ) 75 | en <= rd_en && !rst; 76 | 77 | assign p0_req_data = rd_en; 78 | assign p1_req_data = rd_en; 79 | assign p2_req_data = rd_en; 80 | assign p3_req_data = rd_en; 81 | assign p4_req_data = rd_en; 82 | assign p5_req_data = rd_en; 83 | assign p6_req_data = rd_en; 84 | assign p7_req_data = rd_en; 85 | 86 | reg [31:0] data_reg[14]; 87 | reg [3:0] ctx_reg[14]; 88 | 89 | wire p8_wr_en; 90 | reg [3:0] idx_base; 91 | wire [3:0] p0_idx = idx_base; 92 | wire [3:0] p1_idx = p0_idx + p0_wr_en; 93 | wire [3:0] p2_idx = p1_idx + p1_wr_en; 94 | wire [3:0] p3_idx = p2_idx + p2_wr_en; 95 | wire [3:0] p4_idx = p3_idx + p3_wr_en; 96 | wire [3:0] p5_idx = p4_idx + p4_wr_en; 97 | wire [3:0] p6_idx = p5_idx + p5_wr_en; 98 | wire [3:0] p7_idx = p6_idx + p6_wr_en; 99 | wire [3:0] p8_idx = p7_idx + p7_wr_en; // idle port 100 | wire [3:0] idx_max = p8_idx + p8_wr_en; // max index 101 | 102 | // P8: INTERNAL "IDLE PORT" 103 | reg [3:0] idle_count; 104 | wire [31:0] p8_din = 32'hffffffff; 105 | wire [1:0] p8_tag = 2'b11; 106 | wire [1:0] p8_ctx = 2'b11; 107 | assign p8_wr_en = en && (idx_base > 0) && (idle_count > 7) && (idx_base == p8_idx); 108 | 109 | 110 | 111 | // output buffer logic, when rd_en is deasserted the output data must be 112 | // buffered not to cause data loss. 113 | reg dout_valid; 114 | wire [255:0] dout_data = { ctx_reg[1], ctx_reg[0], ctx_reg[3], ctx_reg[2], ctx_reg[5], ctx_reg[4], 4'hE, ctx_reg[6], data_reg[0], data_reg[1], data_reg[2], data_reg[3], data_reg[4], data_reg[5], data_reg[6] }; 115 | reg dout_buf_valid; 116 | reg [255:0] dout_buf_data; 117 | assign valid = rd_en && (dout_buf_valid || dout_valid); 118 | assign dout = dout_buf_valid ? dout_buf_data : dout_data; 119 | 120 | 121 | 122 | always @ ( posedge clk ) begin 123 | if( rst ) 124 | begin 125 | idx_base <= 0; 126 | idle_count <= 0; 127 | dout_valid <= 0; 128 | dout_buf_valid <= 0; 129 | end 130 | else 131 | begin 132 | // OUTPUT BUFFER LOGIC: 133 | 134 | if( en ) begin 135 | dout_buf_valid <= 0; 136 | end else if( dout_valid ) begin 137 | dout_buf_data <= dout_data; 138 | dout_buf_valid <= 1; 139 | end 140 | 141 | // OUTPUT VALID: 142 | dout_valid <= en && (idx_max >= 7); 143 | 144 | if( en ) begin 145 | // NEXT INDEX BASE: 146 | idx_base <= idx_max - ((idx_max >= 7) ? 7 : 0); 147 | // IDLE COUNT: 148 | idle_count <= ((idx_base > 0) && (idx_base == p8_idx)) ? (idle_count + 1) : 0; 149 | // DATA/CTX writes into index [0-8]: 150 | if( p0_wr_en ) begin data_reg[p0_idx] <= p0_din; ctx_reg[p0_idx] <= {p0_ctx, p0_tag}; end 151 | if( p1_wr_en ) begin data_reg[p1_idx] <= p1_din; ctx_reg[p1_idx] <= {p1_ctx, p1_tag}; end 152 | if( p2_wr_en ) begin data_reg[p2_idx] <= p2_din; ctx_reg[p2_idx] <= {p2_ctx, p2_tag}; end 153 | if( p3_wr_en ) begin data_reg[p3_idx] <= p3_din; ctx_reg[p3_idx] <= {p3_ctx, p3_tag}; end 154 | if( p4_wr_en ) begin data_reg[p4_idx] <= p4_din; ctx_reg[p4_idx] <= {p4_ctx, p4_tag}; end 155 | if( p5_wr_en ) begin data_reg[p5_idx] <= p5_din; ctx_reg[p5_idx] <= {p5_ctx, p5_tag}; end 156 | if( p6_wr_en ) begin data_reg[p6_idx] <= p6_din; ctx_reg[p6_idx] <= {p6_ctx, p6_tag}; end 157 | if( p7_wr_en ) begin data_reg[p7_idx] <= p7_din; ctx_reg[p7_idx] <= {p7_ctx, p7_tag}; end 158 | if( p8_wr_en ) begin data_reg[p8_idx] <= p8_din; ctx_reg[p8_idx] <= {p8_ctx, p8_tag}; end 159 | end 160 | 161 | if( dout_valid ) begin 162 | // DATA/CTX previous move: 163 | if( idx_base > 0) begin data_reg[0] <= data_reg[7+0]; ctx_reg[0] <= ctx_reg[7+0]; end 164 | if( idx_base > 1) begin data_reg[1] <= data_reg[7+1]; ctx_reg[1] <= ctx_reg[7+1]; end 165 | if( idx_base > 2) begin data_reg[2] <= data_reg[7+2]; ctx_reg[2] <= ctx_reg[7+2]; end 166 | if( idx_base > 3) begin data_reg[3] <= data_reg[7+3]; ctx_reg[3] <= ctx_reg[7+3]; end 167 | if( idx_base > 4) begin data_reg[4] <= data_reg[7+4]; ctx_reg[4] <= ctx_reg[7+4]; end 168 | if( idx_base > 5) begin data_reg[5] <= data_reg[7+5]; ctx_reg[5] <= ctx_reg[7+5]; end 169 | if( idx_base > 6) begin data_reg[6] <= data_reg[7+6]; ctx_reg[6] <= ctx_reg[7+6]; end 170 | end 171 | 172 | 173 | end 174 | end 175 | endmodule 176 | -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_gt_common.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_gt_common.v 52 | // Version : 3.3 53 | `timescale 1ns / 1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module pcie_7x_0_gt_common #( 57 | 58 | parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode 59 | parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device 60 | parameter PCIE_USE_MODE = "2.1", // PCIe use mode 61 | parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only 62 | parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency 63 | ) 64 | 65 | ( 66 | input CPLLPDREFCLK, 67 | input PIPE_CLK, 68 | input QPLL_QPLLPD, 69 | input QPLL_QPLLRESET, 70 | input QPLL_DRP_CLK, 71 | input QPLL_DRP_RST_N, 72 | input QPLL_DRP_OVRD, 73 | input QPLL_DRP_GEN3, 74 | input QPLL_DRP_START, 75 | output [5:0] QPLL_DRP_CRSCODE, 76 | output [8:0] QPLL_DRP_FSM, 77 | output QPLL_DRP_DONE, 78 | output QPLL_DRP_RESET, 79 | output QPLL_QPLLLOCK, 80 | output QPLL_QPLLOUTCLK, 81 | output QPLL_QPLLOUTREFCLK 82 | ); 83 | 84 | //---------- QPLL DRP Module Output -------------------- 85 | 86 | wire [7:0] qpll_drp_addr; 87 | wire qpll_drp_en; 88 | wire [15:0] qpll_drp_di; 89 | wire qpll_drp_we; 90 | 91 | //---------- QPLL Wrapper Output ----------------------- 92 | 93 | wire [15:0] qpll_drp_do; 94 | wire qpll_drp_rdy; 95 | 96 | //---------- QPLL Resets ----------------------- 97 | 98 | 99 | //---------- QPLL DRP Module --------------------------------------- 100 | 101 | pcie_7x_0_qpll_drp # 102 | ( 103 | 104 | .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device 105 | .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode 106 | .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only 107 | .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency 108 | 109 | ) 110 | qpll_drp_i 111 | ( 112 | 113 | //---------- Input ------------------------- 114 | .DRP_CLK (QPLL_DRP_CLK), 115 | .DRP_RST_N (!QPLL_DRP_RST_N), 116 | .DRP_OVRD (QPLL_DRP_OVRD), 117 | .DRP_GEN3 (&QPLL_DRP_GEN3), 118 | .DRP_QPLLLOCK (QPLL_QPLLLOCK), 119 | .DRP_START (QPLL_DRP_START), 120 | .DRP_DO (qpll_drp_do), 121 | .DRP_RDY (qpll_drp_rdy), 122 | 123 | //---------- Output ------------------------ 124 | .DRP_ADDR (qpll_drp_addr), 125 | .DRP_EN (qpll_drp_en), 126 | .DRP_DI (qpll_drp_di), 127 | .DRP_WE (qpll_drp_we), 128 | .DRP_DONE (QPLL_DRP_DONE), 129 | .DRP_QPLLRESET (QPLL_DRP_RESET), 130 | .DRP_CRSCODE (QPLL_DRP_CRSCODE), 131 | .DRP_FSM (QPLL_DRP_FSM) 132 | ); 133 | 134 | 135 | //---------- QPLL Wrapper ------------------------------------------ 136 | pcie_7x_0_qpll_wrapper # 137 | ( 138 | .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode 139 | .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device 140 | .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode 141 | .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only 142 | .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency 143 | ) 144 | qpll_wrapper_i 145 | ( 146 | //---------- QPLL Clock Ports -------------- 147 | .QPLL_CPLLPDREFCLK (CPLLPDREFCLK), 148 | .QPLL_GTGREFCLK (PIPE_CLK), 149 | .QPLL_QPLLLOCKDETCLK (1'd0), 150 | .QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK), 151 | .QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), 152 | .QPLL_QPLLLOCK (QPLL_QPLLLOCK), 153 | //---------- QPLL Reset Ports -------------- 154 | .QPLL_QPLLPD (QPLL_QPLLPD), 155 | .QPLL_QPLLRESET (QPLL_QPLLRESET), 156 | //---------- QPLL DRP Ports ---------------- 157 | .QPLL_DRPCLK (QPLL_DRP_CLK), 158 | .QPLL_DRPADDR (qpll_drp_addr), 159 | .QPLL_DRPEN (qpll_drp_en), 160 | .QPLL_DRPDI (qpll_drp_di), 161 | .QPLL_DRPWE (qpll_drp_we), 162 | .QPLL_DRPDO (qpll_drp_do), 163 | .QPLL_DRPRDY (qpll_drp_rdy) 164 | ); 165 | 166 | endmodule 167 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_gt_common.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_gt_common.v 53 | // Version : 3.3 54 | `timescale 1ns / 1ps 55 | 56 | (* DowngradeIPIdentifiedWarnings = "yes" *) 57 | module pcie_7x_0_gt_common #( 58 | 59 | parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode 60 | parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device 61 | parameter PCIE_USE_MODE = "2.1", // PCIe use mode 62 | parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only 63 | parameter PCIE_REFCLK_FREQ = 0 // PCIe reference clock frequency 64 | ) 65 | 66 | ( 67 | input CPLLPDREFCLK, 68 | input PIPE_CLK, 69 | input QPLL_QPLLPD, 70 | input QPLL_QPLLRESET, 71 | input QPLL_DRP_CLK, 72 | input QPLL_DRP_RST_N, 73 | input QPLL_DRP_OVRD, 74 | input QPLL_DRP_GEN3, 75 | input QPLL_DRP_START, 76 | output [5:0] QPLL_DRP_CRSCODE, 77 | output [8:0] QPLL_DRP_FSM, 78 | output QPLL_DRP_DONE, 79 | output QPLL_DRP_RESET, 80 | output QPLL_QPLLLOCK, 81 | output QPLL_QPLLOUTCLK, 82 | output QPLL_QPLLOUTREFCLK 83 | ); 84 | 85 | //---------- QPLL DRP Module Output -------------------- 86 | 87 | wire [7:0] qpll_drp_addr; 88 | wire qpll_drp_en; 89 | wire [15:0] qpll_drp_di; 90 | wire qpll_drp_we; 91 | 92 | //---------- QPLL Wrapper Output ----------------------- 93 | 94 | wire [15:0] qpll_drp_do; 95 | wire qpll_drp_rdy; 96 | 97 | //---------- QPLL Resets ----------------------- 98 | 99 | 100 | //---------- QPLL DRP Module --------------------------------------- 101 | 102 | pcie_7x_0_qpll_drp # 103 | ( 104 | 105 | .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device 106 | .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode 107 | .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only 108 | .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency 109 | 110 | ) 111 | qpll_drp_i 112 | ( 113 | 114 | //---------- Input ------------------------- 115 | .DRP_CLK (QPLL_DRP_CLK), 116 | .DRP_RST_N (!QPLL_DRP_RST_N), 117 | .DRP_OVRD (QPLL_DRP_OVRD), 118 | .DRP_GEN3 (&QPLL_DRP_GEN3), 119 | .DRP_QPLLLOCK (QPLL_QPLLLOCK), 120 | .DRP_START (QPLL_DRP_START), 121 | .DRP_DO (qpll_drp_do), 122 | .DRP_RDY (qpll_drp_rdy), 123 | 124 | //---------- Output ------------------------ 125 | .DRP_ADDR (qpll_drp_addr), 126 | .DRP_EN (qpll_drp_en), 127 | .DRP_DI (qpll_drp_di), 128 | .DRP_WE (qpll_drp_we), 129 | .DRP_DONE (QPLL_DRP_DONE), 130 | .DRP_QPLLRESET (QPLL_DRP_RESET), 131 | .DRP_CRSCODE (QPLL_DRP_CRSCODE), 132 | .DRP_FSM (QPLL_DRP_FSM) 133 | ); 134 | 135 | 136 | //---------- QPLL Wrapper ------------------------------------------ 137 | pcie_7x_0_qpll_wrapper # 138 | ( 139 | .PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode 140 | .PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device 141 | .PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode 142 | .PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only 143 | .PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency 144 | ) 145 | qpll_wrapper_i 146 | ( 147 | //---------- QPLL Clock Ports -------------- 148 | .QPLL_CPLLPDREFCLK (CPLLPDREFCLK), 149 | .QPLL_GTGREFCLK (PIPE_CLK), 150 | .QPLL_QPLLLOCKDETCLK (1'd0), 151 | .QPLL_QPLLOUTCLK (QPLL_QPLLOUTCLK), 152 | .QPLL_QPLLOUTREFCLK (QPLL_QPLLOUTREFCLK), 153 | .QPLL_QPLLLOCK (QPLL_QPLLLOCK), 154 | //---------- QPLL Reset Ports -------------- 155 | .QPLL_QPLLPD (QPLL_QPLLPD), 156 | .QPLL_QPLLRESET (QPLL_QPLLRESET), 157 | //---------- QPLL DRP Ports ---------------- 158 | .QPLL_DRPCLK (QPLL_DRP_CLK), 159 | .QPLL_DRPADDR (qpll_drp_addr), 160 | .QPLL_DRPEN (qpll_drp_en), 161 | .QPLL_DRPDI (qpll_drp_di), 162 | .QPLL_DRPWE (qpll_drp_we), 163 | .QPLL_DRPDO (qpll_drp_do), 164 | .QPLL_DRPRDY (qpll_drp_rdy) 165 | ); 166 | 167 | endmodule 168 | -------------------------------------------------------------------------------- /src/pcileech_ft601.sv: -------------------------------------------------------------------------------- 1 | // 2 | // PCILeech FPGA. 3 | // 4 | // FT601 / FT245 controller module (v4). 5 | // 6 | // (c) Ulf Frisk, 2017-2024 7 | // Author: Ulf Frisk, pcileech@frizk.net 8 | // 9 | 10 | `timescale 1ns / 1ps 11 | 12 | module pcileech_ft601( 13 | input clk, 14 | input rst, 15 | // TO/FROM PADS 16 | output [3:0] FT601_BE, 17 | inout [31:0] FT601_DATA, 18 | input FT601_RXF_N, 19 | input FT601_TXE_N, 20 | output bit FT601_OE_N, 21 | output bit FT601_RD_N, 22 | output bit FT601_WR_N, 23 | output bit FT601_SIWU_N, 24 | // TO/FROM FIFO 25 | output bit [31:0] dout, 26 | output bit dout_valid, 27 | input [31:0] din, 28 | input din_wr_en, 29 | output din_req_data 30 | ); 31 | 32 | initial begin 33 | FT601_OE_N <= 1'b1; 34 | FT601_RD_N <= 1'b1; 35 | FT601_WR_N <= 1'b1; 36 | FT601_SIWU_N <= 1'b1; 37 | dout_valid <= 1'b0; 38 | dout <= 32'h00000000; 39 | end 40 | 41 | `define S_FT601_IDLE 4'h0 42 | `define S_FT601_RX_WAIT1 4'h2 43 | `define S_FT601_RX_WAIT2 4'h3 44 | `define S_FT601_RX_WAIT3 4'h4 45 | `define S_FT601_RX_ACTIVE 4'h5 46 | `define S_FT601_RX_COOLDOWN1 4'h6 47 | `define S_FT601_RX_COOLDOWN2 4'h7 48 | `define S_FT601_TX_WAIT1 4'h8 49 | `define S_FT601_TX_WAIT2 4'h9 50 | `define S_FT601_TX_ACTIVE 4'ha 51 | `define S_FT601_TX_COOLDOWN1 4'hb 52 | `define S_FT601_TX_COOLDOWN2 4'hc 53 | 54 | bit [31:0] FT601_DATA_OUT[5]; 55 | (* KEEP = "TRUE" *) wire FWD; 56 | (* KEEP = "TRUE" *) bit OE = 1'b1; 57 | (* KEEP = "TRUE" *) bit [3:0] data_cooldown_count = 0; 58 | (* KEEP = "TRUE" *) bit [2:0] data_queue_count = 0; 59 | (* KEEP = "TRUE" *) bit [3:0] state = `S_FT601_IDLE; 60 | 61 | 62 | 63 | // ------------------------------------------------------------------------- 64 | // FT245 RX / DATA INPUT BELOW: 65 | // ------------------------------------------------------------------------- 66 | 67 | always @ ( posedge clk ) 68 | begin 69 | dout_valid <= !rst && !FT601_RXF_N && (state == `S_FT601_RX_ACTIVE); 70 | dout[7:0] <= FT601_DATA[31:24]; 71 | dout[15:8] <= FT601_DATA[23:16]; 72 | dout[23:16] <= FT601_DATA[15:8]; 73 | dout[31:24] <= FT601_DATA[7:0]; 74 | end 75 | 76 | 77 | 78 | // ------------------------------------------------------------------------- 79 | // FT245 TX / DATA OUTPUT BELOW: 80 | // ------------------------------------------------------------------------- 81 | 82 | assign FT601_BE = OE ? 4'b1111 : 4'bzzzz; 83 | assign FT601_DATA = OE ? {FT601_DATA_OUT[0][7:0], FT601_DATA_OUT[0][15:8], FT601_DATA_OUT[0][23:16], FT601_DATA_OUT[0][31:24]} : 32'hzzzzzzzz; 84 | assign din_req_data = !rst && (data_queue_count == 2) || (data_queue_count == 3); 85 | assign FWD = !rst && !FT601_TXE_N && (data_queue_count != 0) && (state == `S_FT601_TX_ACTIVE); 86 | 87 | always @ ( posedge clk ) begin 88 | if ( rst || (data_cooldown_count == 4'hf) ) begin 89 | data_cooldown_count <= 0; 90 | data_queue_count <= 5; 91 | FT601_DATA_OUT[0] <= 32'h66665555; 92 | FT601_DATA_OUT[1] <= 32'h66665555; 93 | FT601_DATA_OUT[2] <= 32'h66665555; 94 | FT601_DATA_OUT[3] <= 32'h66665555; 95 | FT601_DATA_OUT[4] <= 32'h66665555; 96 | end 97 | else begin 98 | data_cooldown_count <= (data_queue_count == 0) ? (data_cooldown_count + 1) : 0; 99 | data_queue_count <= data_queue_count + (din_wr_en ? 3'b001 : 3'b000) - (FWD ? 3'b001 : 3'b000); 100 | if ( FWD ) begin 101 | if ( data_queue_count > 1 ) begin 102 | FT601_DATA_OUT[0] <= FT601_DATA_OUT[1]; 103 | end 104 | if ( data_queue_count > 2 ) begin 105 | FT601_DATA_OUT[1] <= FT601_DATA_OUT[2]; 106 | end 107 | if ( data_queue_count > 3 ) begin 108 | FT601_DATA_OUT[2] <= FT601_DATA_OUT[3]; 109 | end 110 | if ( data_queue_count > 4 ) begin 111 | FT601_DATA_OUT[3] <= FT601_DATA_OUT[4]; 112 | end 113 | end 114 | if ( din_wr_en ) begin 115 | FT601_DATA_OUT[data_queue_count - (FWD ? 3'b001 : 3'b000)] <= din; 116 | end 117 | end 118 | end 119 | 120 | 121 | 122 | // ------------------------------------------------------------------------- 123 | // FT245 main control below: 124 | // ------------------------------------------------------------------------- 125 | 126 | always @ ( posedge clk ) 127 | begin 128 | OE <= (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3) && (state != `S_FT601_RX_WAIT2) && (state != `S_FT601_RX_COOLDOWN1) && (state != `S_FT601_RX_COOLDOWN2))); 129 | FT601_OE_N <= (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3) && (state != `S_FT601_RX_WAIT2))); 130 | FT601_RD_N <= (rst || FT601_RXF_N || ((state != `S_FT601_RX_ACTIVE) && (state != `S_FT601_RX_WAIT3))); 131 | FT601_WR_N <= !(!rst && !FT601_TXE_N && ((state == `S_FT601_TX_WAIT2) || ((state == `S_FT601_TX_ACTIVE) && (din_wr_en || (data_queue_count > 1))))); 132 | end 133 | 134 | always @ ( posedge clk ) 135 | if ( rst ) 136 | begin 137 | state <= `S_FT601_IDLE; 138 | end 139 | else case ( state ) 140 | // ---------------------------------------------------------------- 141 | // IDLE STATE: 142 | // RX are prioritized above TX in case both options are available. 143 | // ---------------------------------------------------------------- 144 | `S_FT601_IDLE: 145 | if ( !FT601_RXF_N ) 146 | state <= `S_FT601_RX_WAIT1; 147 | else if ( !FT601_TXE_N && (data_queue_count > 0) ) 148 | state <= `S_FT601_TX_WAIT1; 149 | // ---------------------------------------------------------------- 150 | // RX DATA FROM THE FT601: 151 | // The receiver FIFO is assumed to always be non-full. 152 | // If receiver FIFO is full data will still be received but lost. 153 | // ---------------------------------------------------------------- 154 | `S_FT601_RX_WAIT1: 155 | state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_WAIT2; 156 | `S_FT601_RX_WAIT2: 157 | state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_WAIT3; 158 | `S_FT601_RX_WAIT3: 159 | state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_ACTIVE; 160 | `S_FT601_RX_ACTIVE: 161 | state <= FT601_RXF_N ? `S_FT601_RX_COOLDOWN1 : `S_FT601_RX_ACTIVE; 162 | `S_FT601_RX_COOLDOWN1: 163 | state <= `S_FT601_RX_COOLDOWN2; 164 | `S_FT601_RX_COOLDOWN2: 165 | state <= `S_FT601_IDLE; 166 | // ---------------------------------------------------------------- 167 | // TX DATA TO THE FT601: 168 | // ---------------------------------------------------------------- 169 | `S_FT601_TX_WAIT1: 170 | state <= FT601_TXE_N ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_WAIT2; 171 | `S_FT601_TX_WAIT2: 172 | state <= FT601_TXE_N ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_ACTIVE; 173 | `S_FT601_TX_ACTIVE: 174 | state <= (FT601_TXE_N || (!din_wr_en && (data_queue_count <= 1))) ? `S_FT601_TX_COOLDOWN1 : `S_FT601_TX_ACTIVE; 175 | `S_FT601_TX_COOLDOWN1: 176 | state <= `S_FT601_TX_COOLDOWN2; 177 | `S_FT601_TX_COOLDOWN2: 178 | state <= `S_FT601_IDLE; 179 | endcase 180 | 181 | endmodule 182 | -------------------------------------------------------------------------------- /ip/100t/drom_pcie_cfgspace_writemask.xci: -------------------------------------------------------------------------------- 1 | { 2 | "schema": "xilinx.com:schema:json_instance:1.0", 3 | "ip_inst": { 4 | "xci_name": "drom_pcie_cfgspace_writemask", 5 | "component_reference": "xilinx.com:ip:dist_mem_gen:8.0", 6 | "ip_revision": "14", 7 | "gen_directory": "../../../../pcileech_tbx4.gen/sources_1/ip/drom_pcie_cfgspace_writemask", 8 | "parameters": { 9 | "component_parameters": { 10 | "depth": [ { "value": "1024", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], 11 | "data_width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], 12 | "Component_Name": [ { "value": "drom_pcie_cfgspace_writemask", "resolve_type": "user", "usage": "all" } ], 13 | "memory_type": [ { "value": "rom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], 14 | "input_options": [ { "value": "non_registered", "resolve_type": "user", "usage": "all" } ], 15 | "input_clock_enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 16 | "qualify_we_with_i_ce": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 17 | "dual_port_address": [ { "value": "non_registered", "resolve_type": "user", "usage": "all" } ], 18 | "simple_dual_port_address": [ { "value": "non_registered", "resolve_type": "user", "usage": "all" } ], 19 | "output_options": [ { "value": "non_registered", "resolve_type": "user", "usage": "all" } ], 20 | "Pipeline_Stages": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], 21 | "common_output_clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 22 | "single_port_output_clock_enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 23 | "common_output_ce": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 24 | "dual_port_output_clock_enable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], 25 | "simple_dual_port_output_clock_enable": [ { "value": "false", "resolve_type": "user", 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-------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_axi_basic_rx.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_axi_basic_rx.v 52 | // Version : 3.3 53 | // // 54 | // Description: // 55 | // TRN to AXI RX module. Instantiates pipeline and null generator RX // 56 | // submodules. // 57 | // // 58 | // Notes: // 59 | // Optional notes section. // 60 | // // 61 | // Hierarchical: // 62 | // axi_basic_top // 63 | // axi_basic_rx // 64 | // // 65 | //----------------------------------------------------------------------------// 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* DowngradeIPIdentifiedWarnings = "yes" *) 70 | module pcie_7x_0_axi_basic_rx #( 71 | parameter C_DATA_WIDTH = 128, // RX/TX interface data width 72 | parameter C_FAMILY = "X7", // Targeted FPGA family 73 | parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode 74 | parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl 75 | parameter TCQ = 1, // Clock to Q time 76 | 77 | // Do not override parameters below this line 78 | parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width 79 | parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width 80 | ) ( 81 | //---------------------------------------------// 82 | // User Design I/O // 83 | //---------------------------------------------// 84 | 85 | // AXI RX 86 | //----------- 87 | output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user 88 | output m_axis_rx_tvalid, // RX data is valid 89 | input m_axis_rx_tready, // RX ready for data 90 | output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables 91 | output m_axis_rx_tlast, // RX data is last 92 | output [21:0] m_axis_rx_tuser, // RX user signals 93 | 94 | //---------------------------------------------// 95 | // PCIe Block I/O // 96 | //---------------------------------------------// 97 | 98 | // TRN RX 99 | //----------- 100 | input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block 101 | input trn_rsof, // RX start of packet 102 | input trn_reof, // RX end of packet 103 | input trn_rsrc_rdy, // RX source ready 104 | output trn_rdst_rdy, // RX destination ready 105 | input trn_rsrc_dsc, // RX source discontinue 106 | input [REM_WIDTH-1:0] trn_rrem, // RX remainder 107 | input trn_rerrfwd, // RX error forward 108 | input [6:0] trn_rbar_hit, // RX BAR hit 109 | input trn_recrc_err, // RX ECRC error 110 | 111 | // System 112 | //----------- 113 | output [2:0] np_counter, // Non-posted counter 114 | input user_clk, // user clock from block 115 | input user_rst // user reset from block 116 | ); 117 | 118 | 119 | // Wires 120 | wire null_rx_tvalid; 121 | wire null_rx_tlast; 122 | wire [KEEP_WIDTH-1:0] null_rx_tkeep; 123 | wire null_rdst_rdy; 124 | wire [4:0] null_is_eof; 125 | 126 | //---------------------------------------------// 127 | // RX Data Pipeline // 128 | //---------------------------------------------// 129 | 130 | pcie_7x_0_axi_basic_rx_pipeline #( 131 | .C_DATA_WIDTH( C_DATA_WIDTH ), 132 | .C_FAMILY( C_FAMILY ), 133 | .TCQ( TCQ ), 134 | 135 | .REM_WIDTH( REM_WIDTH ), 136 | .KEEP_WIDTH( KEEP_WIDTH ) 137 | 138 | ) rx_pipeline_inst ( 139 | 140 | // Outgoing AXI TX 141 | //----------- 142 | .m_axis_rx_tdata( m_axis_rx_tdata ), 143 | .m_axis_rx_tvalid( m_axis_rx_tvalid ), 144 | .m_axis_rx_tready( m_axis_rx_tready ), 145 | .m_axis_rx_tkeep( m_axis_rx_tkeep ), 146 | .m_axis_rx_tlast( m_axis_rx_tlast ), 147 | .m_axis_rx_tuser( m_axis_rx_tuser ), 148 | 149 | // Incoming TRN RX 150 | //----------- 151 | .trn_rd( trn_rd ), 152 | .trn_rsof( trn_rsof ), 153 | .trn_reof( trn_reof ), 154 | .trn_rsrc_rdy( trn_rsrc_rdy ), 155 | .trn_rdst_rdy( trn_rdst_rdy ), 156 | .trn_rsrc_dsc( trn_rsrc_dsc ), 157 | .trn_rrem( trn_rrem ), 158 | .trn_rerrfwd( trn_rerrfwd ), 159 | .trn_rbar_hit( trn_rbar_hit ), 160 | .trn_recrc_err( trn_recrc_err ), 161 | 162 | // Null Inputs 163 | //----------- 164 | .null_rx_tvalid( null_rx_tvalid ), 165 | .null_rx_tlast( null_rx_tlast ), 166 | .null_rx_tkeep( null_rx_tkeep ), 167 | .null_rdst_rdy( null_rdst_rdy ), 168 | .null_is_eof( null_is_eof ), 169 | 170 | // System 171 | //----------- 172 | .np_counter( np_counter ), 173 | .user_clk( user_clk ), 174 | .user_rst( user_rst ) 175 | ); 176 | 177 | 178 | //---------------------------------------------// 179 | // RX Null Packet Generator // 180 | //---------------------------------------------// 181 | 182 | pcie_7x_0_axi_basic_rx_null_gen #( 183 | .C_DATA_WIDTH( C_DATA_WIDTH ), 184 | .TCQ( TCQ ), 185 | 186 | .KEEP_WIDTH( KEEP_WIDTH ) 187 | 188 | ) rx_null_gen_inst ( 189 | 190 | // Inputs 191 | //----------- 192 | .m_axis_rx_tdata( m_axis_rx_tdata ), 193 | .m_axis_rx_tvalid( m_axis_rx_tvalid ), 194 | .m_axis_rx_tready( m_axis_rx_tready ), 195 | .m_axis_rx_tlast( m_axis_rx_tlast ), 196 | .m_axis_rx_tuser( m_axis_rx_tuser ), 197 | 198 | // Null Outputs 199 | //----------- 200 | .null_rx_tvalid( null_rx_tvalid ), 201 | .null_rx_tlast( null_rx_tlast ), 202 | .null_rx_tkeep( null_rx_tkeep ), 203 | .null_rdst_rdy( null_rdst_rdy ), 204 | .null_is_eof( null_is_eof ), 205 | 206 | // System 207 | //----------- 208 | .user_clk( user_clk ), 209 | .user_rst( user_rst ) 210 | ); 211 | 212 | endmodule 213 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_axi_basic_rx.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_axi_basic_rx.v 53 | // Version : 3.3 54 | // // 55 | // Description: // 56 | // TRN to AXI RX module. Instantiates pipeline and null generator RX // 57 | // submodules. // 58 | // // 59 | // Notes: // 60 | // Optional notes section. // 61 | // // 62 | // Hierarchical: // 63 | // axi_basic_top // 64 | // axi_basic_rx // 65 | // // 66 | //----------------------------------------------------------------------------// 67 | 68 | `timescale 1ps/1ps 69 | 70 | (* DowngradeIPIdentifiedWarnings = "yes" *) 71 | module pcie_7x_0_axi_basic_rx #( 72 | parameter C_DATA_WIDTH = 128, // RX/TX interface data width 73 | parameter C_FAMILY = "X7", // Targeted FPGA family 74 | parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode 75 | parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl 76 | parameter TCQ = 1, // Clock to Q time 77 | 78 | // Do not override parameters below this line 79 | parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width 80 | parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width 81 | ) ( 82 | //---------------------------------------------// 83 | // User Design I/O // 84 | //---------------------------------------------// 85 | 86 | // AXI RX 87 | //----------- 88 | output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user 89 | output m_axis_rx_tvalid, // RX data is valid 90 | input m_axis_rx_tready, // RX ready for data 91 | output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables 92 | output m_axis_rx_tlast, // RX data is last 93 | output [21:0] m_axis_rx_tuser, // RX user signals 94 | 95 | //---------------------------------------------// 96 | // PCIe Block I/O // 97 | //---------------------------------------------// 98 | 99 | // TRN RX 100 | //----------- 101 | input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block 102 | input trn_rsof, // RX start of packet 103 | input trn_reof, // RX end of packet 104 | input trn_rsrc_rdy, // RX source ready 105 | output trn_rdst_rdy, // RX destination ready 106 | input trn_rsrc_dsc, // RX source discontinue 107 | input [REM_WIDTH-1:0] trn_rrem, // RX remainder 108 | input trn_rerrfwd, // RX error forward 109 | input [6:0] trn_rbar_hit, // RX BAR hit 110 | input trn_recrc_err, // RX ECRC error 111 | 112 | // System 113 | //----------- 114 | output [2:0] np_counter, // Non-posted counter 115 | input user_clk, // user clock from block 116 | input user_rst // user reset from block 117 | ); 118 | 119 | 120 | // Wires 121 | wire null_rx_tvalid; 122 | wire null_rx_tlast; 123 | wire [KEEP_WIDTH-1:0] null_rx_tkeep; 124 | wire null_rdst_rdy; 125 | wire [4:0] null_is_eof; 126 | 127 | //---------------------------------------------// 128 | // RX Data Pipeline // 129 | //---------------------------------------------// 130 | 131 | pcie_7x_0_axi_basic_rx_pipeline #( 132 | .C_DATA_WIDTH( C_DATA_WIDTH ), 133 | .C_FAMILY( C_FAMILY ), 134 | .TCQ( TCQ ), 135 | 136 | .REM_WIDTH( REM_WIDTH ), 137 | .KEEP_WIDTH( KEEP_WIDTH ) 138 | 139 | ) rx_pipeline_inst ( 140 | 141 | // Outgoing AXI TX 142 | //----------- 143 | .m_axis_rx_tdata( m_axis_rx_tdata ), 144 | .m_axis_rx_tvalid( m_axis_rx_tvalid ), 145 | .m_axis_rx_tready( m_axis_rx_tready ), 146 | .m_axis_rx_tkeep( m_axis_rx_tkeep ), 147 | .m_axis_rx_tlast( m_axis_rx_tlast ), 148 | .m_axis_rx_tuser( m_axis_rx_tuser ), 149 | 150 | // Incoming TRN RX 151 | //----------- 152 | .trn_rd( trn_rd ), 153 | .trn_rsof( trn_rsof ), 154 | .trn_reof( trn_reof ), 155 | .trn_rsrc_rdy( trn_rsrc_rdy ), 156 | .trn_rdst_rdy( trn_rdst_rdy ), 157 | .trn_rsrc_dsc( trn_rsrc_dsc ), 158 | .trn_rrem( trn_rrem ), 159 | .trn_rerrfwd( trn_rerrfwd ), 160 | .trn_rbar_hit( trn_rbar_hit ), 161 | .trn_recrc_err( trn_recrc_err ), 162 | 163 | // Null Inputs 164 | //----------- 165 | .null_rx_tvalid( null_rx_tvalid ), 166 | .null_rx_tlast( null_rx_tlast ), 167 | .null_rx_tkeep( null_rx_tkeep ), 168 | .null_rdst_rdy( null_rdst_rdy ), 169 | .null_is_eof( null_is_eof ), 170 | 171 | // System 172 | //----------- 173 | .np_counter( np_counter ), 174 | .user_clk( user_clk ), 175 | .user_rst( user_rst ) 176 | ); 177 | 178 | 179 | //---------------------------------------------// 180 | // RX Null Packet Generator // 181 | //---------------------------------------------// 182 | 183 | pcie_7x_0_axi_basic_rx_null_gen #( 184 | .C_DATA_WIDTH( C_DATA_WIDTH ), 185 | .TCQ( TCQ ), 186 | 187 | .KEEP_WIDTH( KEEP_WIDTH ) 188 | 189 | ) rx_null_gen_inst ( 190 | 191 | // Inputs 192 | //----------- 193 | .m_axis_rx_tdata( m_axis_rx_tdata ), 194 | .m_axis_rx_tvalid( m_axis_rx_tvalid ), 195 | .m_axis_rx_tready( m_axis_rx_tready ), 196 | .m_axis_rx_tlast( m_axis_rx_tlast ), 197 | .m_axis_rx_tuser( m_axis_rx_tuser ), 198 | 199 | // Null Outputs 200 | //----------- 201 | .null_rx_tvalid( null_rx_tvalid ), 202 | .null_rx_tlast( null_rx_tlast ), 203 | .null_rx_tkeep( null_rx_tkeep ), 204 | .null_rdst_rdy( null_rdst_rdy ), 205 | .null_is_eof( null_is_eof ), 206 | 207 | // System 208 | //----------- 209 | .user_clk( user_clk ), 210 | .user_rst( user_rst ) 211 | ); 212 | 213 | endmodule 214 | -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_pcie_bram_top_7x.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_pcie_bram_top_7x.v 52 | // Version : 3.3 53 | // Description : bram wrapper for Tx and Rx 54 | // given the pcie block attributes calculate the number of brams 55 | // and pipeline stages and instantiate the brams 56 | // 57 | // Hierarchy: 58 | // pcie_bram_top top level 59 | // pcie_brams pcie_bram instantiations, 60 | // pipeline stages (if any), 61 | // address decode logic (if any), 62 | // datapath muxing (if any) 63 | // pcie_bram bram library cell wrapper 64 | // the pcie_bram module can have a paramter that 65 | // specifies the family (V6, V5, V4) 66 | // 67 | //----------------------------------------------------------------------------- 68 | 69 | `timescale 1ps/1ps 70 | 71 | (* DowngradeIPIdentifiedWarnings = "yes" *) 72 | module pcie_7x_0_pcie_bram_top_7x 73 | #( 74 | parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT 75 | parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B 76 | parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s 77 | parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 78 | 79 | parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit 80 | parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit) 81 | parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit) 82 | parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit) 83 | parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit) 84 | 85 | parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive) 86 | parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive) 87 | parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive) 88 | parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive) 89 | ) 90 | ( 91 | input user_clk_i, // Clock input 92 | input reset_i, // Reset input 93 | 94 | input mim_tx_wen, // Write Enable for Transmit path BRAM 95 | input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM 96 | input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM 97 | input mim_tx_ren, // Read Enable for Transmit path BRAM 98 | input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM 99 | input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM 100 | output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM 101 | 102 | input mim_rx_wen, // Write Enable for Receive path BRAM 103 | input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM 104 | input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM 105 | input mim_rx_ren, // Read Enable for Receive path BRAM 106 | input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM 107 | input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM 108 | output [71:0] mim_rx_rdata // Read Data for Receive path BRAM 109 | ); 110 | 111 | // TX calculations 112 | localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 : 113 | (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 : 114 | (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 : 115 | 1024 ); 116 | 117 | localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD); 118 | 119 | localparam ROWS_TX = 1; 120 | localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 : 121 | (BYTES_TX <= 8192) ? 2 : 122 | (BYTES_TX <= 16384) ? 4 : 123 | (BYTES_TX <= 32768) ? 8 : 124 | 18 125 | ); 126 | 127 | // RX calculations 128 | localparam ROWS_RX = 1; 129 | 130 | localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 : 131 | (VC0_RX_RAM_LIMIT < 'h0400) ? 2 : 132 | (VC0_RX_RAM_LIMIT < 'h0800) ? 4 : 133 | (VC0_RX_RAM_LIMIT < 'h1000) ? 8 : 134 | 18 135 | ); 136 | 137 | initial begin 138 | $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX); 139 | $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX); 140 | end 141 | 142 | pcie_7x_0_pcie_brams_7x #( 143 | .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), 144 | .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), 145 | .IMPL_TARGET ( IMPL_TARGET ), 146 | .NUM_BRAMS ( COLS_TX ), 147 | .RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), 148 | .RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), 149 | .RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ) 150 | ) 151 | pcie_brams_tx ( 152 | .user_clk_i ( user_clk_i ), 153 | .reset_i ( reset_i ), 154 | .waddr ( mim_tx_waddr ), 155 | .wen ( mim_tx_wen ), 156 | .ren ( mim_tx_ren ), 157 | .rce ( mim_tx_rce ), 158 | .wdata ( mim_tx_wdata ), 159 | .raddr ( mim_tx_raddr ), 160 | .rdata ( mim_tx_rdata ) 161 | ); 162 | 163 | pcie_7x_0_pcie_brams_7x #( 164 | .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), 165 | .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), 166 | .IMPL_TARGET ( IMPL_TARGET ), 167 | .NUM_BRAMS ( COLS_RX ), 168 | .RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), 169 | .RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), 170 | .RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ) 171 | ) pcie_brams_rx ( 172 | .user_clk_i ( user_clk_i ), 173 | .reset_i ( reset_i ), 174 | .waddr ( mim_rx_waddr ), 175 | .wen ( mim_rx_wen ), 176 | .ren ( mim_rx_ren ), 177 | .rce ( mim_rx_rce ), 178 | .wdata ( mim_rx_wdata ), 179 | .raddr ( mim_rx_raddr ), 180 | .rdata ( mim_rx_rdata ) 181 | ); 182 | 183 | endmodule // pcie_bram_top 184 | 185 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_pcie_bram_top_7x.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_pcie_bram_top_7x.v 53 | // Version : 3.3 54 | // Description : bram wrapper for Tx and Rx 55 | // given the pcie block attributes calculate the number of brams 56 | // and pipeline stages and instantiate the brams 57 | // 58 | // Hierarchy: 59 | // pcie_bram_top top level 60 | // pcie_brams pcie_bram instantiations, 61 | // pipeline stages (if any), 62 | // address decode logic (if any), 63 | // datapath muxing (if any) 64 | // pcie_bram bram library cell wrapper 65 | // the pcie_bram module can have a paramter that 66 | // specifies the family (V6, V5, V4) 67 | // 68 | //----------------------------------------------------------------------------- 69 | 70 | `timescale 1ps/1ps 71 | 72 | (* DowngradeIPIdentifiedWarnings = "yes" *) 73 | module pcie_7x_0_pcie_bram_top_7x 74 | #( 75 | parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT 76 | parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0, // MPS Supported : 0 - 128 B, 1 - 256 B, 2 - 512 B, 3 - 1024 B 77 | parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s 78 | parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 79 | 80 | parameter VC0_TX_LASTPACKET = 31, // Number of Packets in Transmit 81 | parameter TLM_TX_OVERHEAD = 24, // Overhead Bytes for Packets (Transmit) 82 | parameter TL_TX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Transmit) 83 | parameter TL_TX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Transmit) 84 | parameter TL_TX_RAM_WRITE_LATENCY = 1, // BRAM Write Latency (Transmit) 85 | 86 | parameter VC0_RX_RAM_LIMIT = 'h1FFF, // RAM Size (Receive) 87 | parameter TL_RX_RAM_RADDR_LATENCY = 1, // BRAM Read Address Latency (Receive) 88 | parameter TL_RX_RAM_RDATA_LATENCY = 2, // BRAM Read Data Latency (Receive) 89 | parameter TL_RX_RAM_WRITE_LATENCY = 1 // BRAM Write Latency (Receive) 90 | ) 91 | ( 92 | input user_clk_i, // Clock input 93 | input reset_i, // Reset input 94 | 95 | input mim_tx_wen, // Write Enable for Transmit path BRAM 96 | input [12:0] mim_tx_waddr, // Write Address for Transmit path BRAM 97 | input [71:0] mim_tx_wdata, // Write Data for Transmit path BRAM 98 | input mim_tx_ren, // Read Enable for Transmit path BRAM 99 | input mim_tx_rce, // Read Output Register Clock Enable for Transmit path BRAM 100 | input [12:0] mim_tx_raddr, // Read Address for Transmit path BRAM 101 | output [71:0] mim_tx_rdata, // Read Data for Transmit path BRAM 102 | 103 | input mim_rx_wen, // Write Enable for Receive path BRAM 104 | input [12:0] mim_rx_waddr, // Write Enable for Receive path BRAM 105 | input [71:0] mim_rx_wdata, // Write Enable for Receive path BRAM 106 | input mim_rx_ren, // Read Enable for Receive path BRAM 107 | input mim_rx_rce, // Read Output Register Clock Enable for Receive path BRAM 108 | input [12:0] mim_rx_raddr, // Read Address for Receive path BRAM 109 | output [71:0] mim_rx_rdata // Read Data for Receive path BRAM 110 | ); 111 | 112 | // TX calculations 113 | localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 : 114 | (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 : 115 | (DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 : 116 | 1024 ); 117 | 118 | localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD); 119 | 120 | localparam ROWS_TX = 1; 121 | localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 : 122 | (BYTES_TX <= 8192) ? 2 : 123 | (BYTES_TX <= 16384) ? 4 : 124 | (BYTES_TX <= 32768) ? 8 : 125 | 18 126 | ); 127 | 128 | // RX calculations 129 | localparam ROWS_RX = 1; 130 | 131 | localparam COLS_RX = ((VC0_RX_RAM_LIMIT < 'h0200) ? 1 : 132 | (VC0_RX_RAM_LIMIT < 'h0400) ? 2 : 133 | (VC0_RX_RAM_LIMIT < 'h0800) ? 4 : 134 | (VC0_RX_RAM_LIMIT < 'h1000) ? 8 : 135 | 18 136 | ); 137 | 138 | initial begin 139 | $display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX); 140 | $display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX); 141 | end 142 | 143 | pcie_7x_0_pcie_brams_7x #( 144 | .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), 145 | .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), 146 | .IMPL_TARGET ( IMPL_TARGET ), 147 | .NUM_BRAMS ( COLS_TX ), 148 | .RAM_RADDR_LATENCY ( TL_TX_RAM_RADDR_LATENCY ), 149 | .RAM_RDATA_LATENCY ( TL_TX_RAM_RDATA_LATENCY ), 150 | .RAM_WRITE_LATENCY ( TL_TX_RAM_WRITE_LATENCY ) 151 | ) 152 | pcie_brams_tx ( 153 | .user_clk_i ( user_clk_i ), 154 | .reset_i ( reset_i ), 155 | .waddr ( mim_tx_waddr ), 156 | .wen ( mim_tx_wen ), 157 | .ren ( mim_tx_ren ), 158 | .rce ( mim_tx_rce ), 159 | .wdata ( mim_tx_wdata ), 160 | .raddr ( mim_tx_raddr ), 161 | .rdata ( mim_tx_rdata ) 162 | ); 163 | 164 | pcie_7x_0_pcie_brams_7x #( 165 | .LINK_CAP_MAX_LINK_WIDTH ( LINK_CAP_MAX_LINK_WIDTH ), 166 | .LINK_CAP_MAX_LINK_SPEED ( LINK_CAP_MAX_LINK_SPEED ), 167 | .IMPL_TARGET ( IMPL_TARGET ), 168 | .NUM_BRAMS ( COLS_RX ), 169 | .RAM_RADDR_LATENCY ( TL_RX_RAM_RADDR_LATENCY ), 170 | .RAM_RDATA_LATENCY ( TL_RX_RAM_RDATA_LATENCY ), 171 | .RAM_WRITE_LATENCY ( TL_RX_RAM_WRITE_LATENCY ) 172 | ) pcie_brams_rx ( 173 | .user_clk_i ( user_clk_i ), 174 | .reset_i ( reset_i ), 175 | .waddr ( mim_rx_waddr ), 176 | .wen ( mim_rx_wen ), 177 | .ren ( mim_rx_ren ), 178 | .rce ( mim_rx_rce ), 179 | .wdata ( mim_rx_wdata ), 180 | .raddr ( mim_rx_raddr ), 181 | .rdata ( mim_rx_rdata ) 182 | ); 183 | 184 | endmodule // pcie_bram_top 185 | 186 | -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_pcie_pipe_misc.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_pcie_pipe_misc.v 52 | // Version : 3.3 53 | // 54 | // Description: Misc PIPE module for 7-Series PCIe Block 55 | // 56 | // 57 | // 58 | //-------------------------------------------------------------------------------- 59 | 60 | `timescale 1ps/1ps 61 | 62 | (* DowngradeIPIdentifiedWarnings = "yes" *) 63 | module pcie_7x_0_pcie_pipe_misc # 64 | ( 65 | parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages 66 | parameter TCQ = 1 // synthesis warning solved: parameter declaration becomes local 67 | ) 68 | ( 69 | 70 | input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect 71 | input wire pipe_tx_reset_i , // PIPE Tx Reset 72 | input wire pipe_tx_rate_i , // PIPE Tx Rate 73 | input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis 74 | input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin 75 | input wire pipe_tx_swing_i , // PIPE Tx Swing 76 | 77 | output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect 78 | output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset 79 | output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate 80 | output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis 81 | output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin 82 | output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing 83 | 84 | input wire pipe_clk , // PIPE Clock 85 | input wire rst_n // Reset 86 | ); 87 | 88 | //******************************************************************// 89 | // Reality check. // 90 | //******************************************************************// 91 | 92 | // parameter TCQ = 1; // clock to out delay model 93 | 94 | generate 95 | 96 | if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0 97 | 98 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i; 99 | assign pipe_tx_reset_o = pipe_tx_reset_i; 100 | assign pipe_tx_rate_o = pipe_tx_rate_i; 101 | assign pipe_tx_deemph_o = pipe_tx_deemph_i; 102 | assign pipe_tx_margin_o = pipe_tx_margin_i; 103 | assign pipe_tx_swing_o = pipe_tx_swing_i; 104 | 105 | end // if (PIPE_PIPELINE_STAGES == 0) 106 | else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1 107 | 108 | reg pipe_tx_rcvr_det_q ; 109 | reg pipe_tx_reset_q ; 110 | reg pipe_tx_rate_q ; 111 | reg pipe_tx_deemph_q ; 112 | reg [2:0] pipe_tx_margin_q ; 113 | reg pipe_tx_swing_q ; 114 | 115 | always @(posedge pipe_clk) begin 116 | 117 | if (rst_n) 118 | begin 119 | 120 | pipe_tx_rcvr_det_q <= #TCQ 0; 121 | pipe_tx_reset_q <= #TCQ 1'b1; 122 | pipe_tx_rate_q <= #TCQ 0; 123 | pipe_tx_deemph_q <= #TCQ 1'b1; 124 | pipe_tx_margin_q <= #TCQ 0; 125 | pipe_tx_swing_q <= #TCQ 0; 126 | 127 | end 128 | else 129 | begin 130 | 131 | pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; 132 | pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; 133 | pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; 134 | pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; 135 | pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; 136 | pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; 137 | 138 | end 139 | 140 | end 141 | 142 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q; 143 | assign pipe_tx_reset_o = pipe_tx_reset_q; 144 | assign pipe_tx_rate_o = pipe_tx_rate_q; 145 | assign pipe_tx_deemph_o = pipe_tx_deemph_q; 146 | assign pipe_tx_margin_o = pipe_tx_margin_q; 147 | assign pipe_tx_swing_o = pipe_tx_swing_q; 148 | 149 | end // if (PIPE_PIPELINE_STAGES == 1) 150 | else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2 151 | 152 | reg pipe_tx_rcvr_det_q ; 153 | reg pipe_tx_reset_q ; 154 | reg pipe_tx_rate_q ; 155 | reg pipe_tx_deemph_q ; 156 | reg [2:0] pipe_tx_margin_q ; 157 | reg pipe_tx_swing_q ; 158 | 159 | reg pipe_tx_rcvr_det_qq ; 160 | reg pipe_tx_reset_qq ; 161 | reg pipe_tx_rate_qq ; 162 | reg pipe_tx_deemph_qq ; 163 | reg [2:0] pipe_tx_margin_qq ; 164 | reg pipe_tx_swing_qq ; 165 | 166 | always @(posedge pipe_clk) begin 167 | 168 | if (rst_n) 169 | begin 170 | 171 | pipe_tx_rcvr_det_q <= #TCQ 0; 172 | pipe_tx_reset_q <= #TCQ 1'b1; 173 | pipe_tx_rate_q <= #TCQ 0; 174 | pipe_tx_deemph_q <= #TCQ 1'b1; 175 | pipe_tx_margin_q <= #TCQ 0; 176 | pipe_tx_swing_q <= #TCQ 0; 177 | 178 | pipe_tx_rcvr_det_qq <= #TCQ 0; 179 | pipe_tx_reset_qq <= #TCQ 1'b1; 180 | pipe_tx_rate_qq <= #TCQ 0; 181 | pipe_tx_deemph_qq <= #TCQ 1'b1; 182 | pipe_tx_margin_qq <= #TCQ 0; 183 | pipe_tx_swing_qq <= #TCQ 0; 184 | 185 | end 186 | else 187 | begin 188 | 189 | pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; 190 | pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; 191 | pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; 192 | pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; 193 | pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; 194 | pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; 195 | 196 | pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q; 197 | pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q; 198 | pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q; 199 | pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q; 200 | pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q; 201 | pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q; 202 | 203 | end 204 | 205 | end 206 | 207 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq; 208 | assign pipe_tx_reset_o = pipe_tx_reset_qq; 209 | assign pipe_tx_rate_o = pipe_tx_rate_qq; 210 | assign pipe_tx_deemph_o = pipe_tx_deemph_qq; 211 | assign pipe_tx_margin_o = pipe_tx_margin_qq; 212 | assign pipe_tx_swing_o = pipe_tx_swing_qq; 213 | 214 | end // if (PIPE_PIPELINE_STAGES == 2) 215 | 216 | endgenerate 217 | 218 | endmodule 219 | 220 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_pcie_pipe_misc.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_pcie_pipe_misc.v 53 | // Version : 3.3 54 | // 55 | // Description: Misc PIPE module for 7-Series PCIe Block 56 | // 57 | // 58 | // 59 | //-------------------------------------------------------------------------------- 60 | 61 | `timescale 1ps/1ps 62 | 63 | (* DowngradeIPIdentifiedWarnings = "yes" *) 64 | module pcie_7x_0_pcie_pipe_misc # 65 | ( 66 | parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages 67 | parameter TCQ = 1 // synthesis warning solved: parameter declaration becomes local 68 | ) 69 | ( 70 | 71 | input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect 72 | input wire pipe_tx_reset_i , // PIPE Tx Reset 73 | input wire pipe_tx_rate_i , // PIPE Tx Rate 74 | input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis 75 | input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin 76 | input wire pipe_tx_swing_i , // PIPE Tx Swing 77 | 78 | output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect 79 | output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset 80 | output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate 81 | output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis 82 | output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin 83 | output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing 84 | 85 | input wire pipe_clk , // PIPE Clock 86 | input wire rst_n // Reset 87 | ); 88 | 89 | //******************************************************************// 90 | // Reality check. // 91 | //******************************************************************// 92 | 93 | // parameter TCQ = 1; // clock to out delay model 94 | 95 | generate 96 | 97 | if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0 98 | 99 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i; 100 | assign pipe_tx_reset_o = pipe_tx_reset_i; 101 | assign pipe_tx_rate_o = pipe_tx_rate_i; 102 | assign pipe_tx_deemph_o = pipe_tx_deemph_i; 103 | assign pipe_tx_margin_o = pipe_tx_margin_i; 104 | assign pipe_tx_swing_o = pipe_tx_swing_i; 105 | 106 | end // if (PIPE_PIPELINE_STAGES == 0) 107 | else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1 108 | 109 | reg pipe_tx_rcvr_det_q ; 110 | reg pipe_tx_reset_q ; 111 | reg pipe_tx_rate_q ; 112 | reg pipe_tx_deemph_q ; 113 | reg [2:0] pipe_tx_margin_q ; 114 | reg pipe_tx_swing_q ; 115 | 116 | always @(posedge pipe_clk) begin 117 | 118 | if (rst_n) 119 | begin 120 | 121 | pipe_tx_rcvr_det_q <= #TCQ 0; 122 | pipe_tx_reset_q <= #TCQ 1'b1; 123 | pipe_tx_rate_q <= #TCQ 0; 124 | pipe_tx_deemph_q <= #TCQ 1'b1; 125 | pipe_tx_margin_q <= #TCQ 0; 126 | pipe_tx_swing_q <= #TCQ 0; 127 | 128 | end 129 | else 130 | begin 131 | 132 | pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; 133 | pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; 134 | pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; 135 | pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; 136 | pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; 137 | pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; 138 | 139 | end 140 | 141 | end 142 | 143 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q; 144 | assign pipe_tx_reset_o = pipe_tx_reset_q; 145 | assign pipe_tx_rate_o = pipe_tx_rate_q; 146 | assign pipe_tx_deemph_o = pipe_tx_deemph_q; 147 | assign pipe_tx_margin_o = pipe_tx_margin_q; 148 | assign pipe_tx_swing_o = pipe_tx_swing_q; 149 | 150 | end // if (PIPE_PIPELINE_STAGES == 1) 151 | else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2 152 | 153 | reg pipe_tx_rcvr_det_q ; 154 | reg pipe_tx_reset_q ; 155 | reg pipe_tx_rate_q ; 156 | reg pipe_tx_deemph_q ; 157 | reg [2:0] pipe_tx_margin_q ; 158 | reg pipe_tx_swing_q ; 159 | 160 | reg pipe_tx_rcvr_det_qq ; 161 | reg pipe_tx_reset_qq ; 162 | reg pipe_tx_rate_qq ; 163 | reg pipe_tx_deemph_qq ; 164 | reg [2:0] pipe_tx_margin_qq ; 165 | reg pipe_tx_swing_qq ; 166 | 167 | always @(posedge pipe_clk) begin 168 | 169 | if (rst_n) 170 | begin 171 | 172 | pipe_tx_rcvr_det_q <= #TCQ 0; 173 | pipe_tx_reset_q <= #TCQ 1'b1; 174 | pipe_tx_rate_q <= #TCQ 0; 175 | pipe_tx_deemph_q <= #TCQ 1'b1; 176 | pipe_tx_margin_q <= #TCQ 0; 177 | pipe_tx_swing_q <= #TCQ 0; 178 | 179 | pipe_tx_rcvr_det_qq <= #TCQ 0; 180 | pipe_tx_reset_qq <= #TCQ 1'b1; 181 | pipe_tx_rate_qq <= #TCQ 0; 182 | pipe_tx_deemph_qq <= #TCQ 1'b1; 183 | pipe_tx_margin_qq <= #TCQ 0; 184 | pipe_tx_swing_qq <= #TCQ 0; 185 | 186 | end 187 | else 188 | begin 189 | 190 | pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i; 191 | pipe_tx_reset_q <= #TCQ pipe_tx_reset_i; 192 | pipe_tx_rate_q <= #TCQ pipe_tx_rate_i; 193 | pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i; 194 | pipe_tx_margin_q <= #TCQ pipe_tx_margin_i; 195 | pipe_tx_swing_q <= #TCQ pipe_tx_swing_i; 196 | 197 | pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q; 198 | pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q; 199 | pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q; 200 | pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q; 201 | pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q; 202 | pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q; 203 | 204 | end 205 | 206 | end 207 | 208 | assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq; 209 | assign pipe_tx_reset_o = pipe_tx_reset_qq; 210 | assign pipe_tx_rate_o = pipe_tx_rate_qq; 211 | assign pipe_tx_deemph_o = pipe_tx_deemph_qq; 212 | assign pipe_tx_margin_o = pipe_tx_margin_qq; 213 | assign pipe_tx_swing_o = pipe_tx_swing_qq; 214 | 215 | end // if (PIPE_PIPELINE_STAGES == 2) 216 | 217 | endgenerate 218 | 219 | endmodule 220 | 221 | -------------------------------------------------------------------------------- /pcie_7x/pcie_7x_0_pcie_bram_7x.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | // 3 | // (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. 4 | // 5 | // This file contains confidential and proprietary information 6 | // of Xilinx, Inc. and is protected under U.S. and 7 | // international copyright and other intellectual property 8 | // laws. 9 | // 10 | // DISCLAIMER 11 | // This disclaimer is not a license and does not grant any 12 | // rights to the materials distributed herewith. Except as 13 | // otherwise provided in a valid license issued to you by 14 | // Xilinx, and to the maximum extent permitted by applicable 15 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | // (2) Xilinx shall not be liable (whether in contract or tort, 21 | // including negligence, or under any other theory of 22 | // liability) for any loss or damage of any kind or nature 23 | // related to, arising under or in connection with these 24 | // materials, including for any direct, or any indirect, 25 | // special, incidental, or consequential loss or damage 26 | // (including loss of data, profits, goodwill, or any type of 27 | // loss or damage suffered as a result of any action brought 28 | // by a third party) even if such damage or loss was 29 | // reasonably foreseeable or Xilinx had been advised of the 30 | // possibility of the same. 31 | // 32 | // CRITICAL APPLICATIONS 33 | // Xilinx products are not designed or intended to be fail- 34 | // safe, or for use in any application requiring fail-safe 35 | // performance, such as life-support or safety devices or 36 | // systems, Class III medical devices, nuclear facilities, 37 | // applications related to the deployment of airbags, or any 38 | // other applications that could lead to death, personal 39 | // injury, or severe property or environmental damage 40 | // (individually and collectively, "Critical 41 | // Applications"). Customer assumes the sole risk and 42 | // liability of any use of Xilinx products in Critical 43 | // Applications, subject only to applicable laws and 44 | // regulations governing limitations on product liability. 45 | // 46 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | // PART OF THIS FILE AT ALL TIMES. 48 | // 49 | //----------------------------------------------------------------------------- 50 | // Project : Series-7 Integrated Block for PCI Express 51 | // File : pcie_7x_0_pcie_bram_7x.v 52 | // Version : 3.3 53 | // Description : single bram wrapper for the mb pcie block 54 | // The bram A port is the write port 55 | // the B port is the read port 56 | // 57 | // 58 | //-----------------------------------------------------------------------------// 59 | 60 | `timescale 1ps/1ps 61 | 62 | (* DowngradeIPIdentifiedWarnings = "yes" *) 63 | module pcie_7x_0_pcie_bram_7x 64 | #( 65 | parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s 66 | parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 67 | parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT 68 | parameter DOB_REG = 0, // 1 - use the output register; 69 | // 0 - don't use the output register 70 | parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36 71 | // 72 - uses RAMB36SDP 72 | ) 73 | ( 74 | input user_clk_i,// user clock 75 | input reset_i, // bram reset 76 | 77 | input wen_i, // write enable 78 | input [12:0] waddr_i, // write address 79 | input [WIDTH - 1:0] wdata_i, // write data 80 | 81 | input ren_i, // read enable 82 | input rce_i, // output register clock enable 83 | input [12:0] raddr_i, // read address 84 | 85 | output [WIDTH - 1:0] rdata_o // read data 86 | ); 87 | 88 | // map the address bits 89 | localparam ADDR_MSB = ((WIDTH == 4) ? 12 : 90 | (WIDTH == 9) ? 11 : 91 | (WIDTH == 18) ? 10 : 92 | (WIDTH == 36) ? 9 : 93 | 8 94 | ); 95 | 96 | // set the width of the tied off low address bits 97 | localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 : 98 | (WIDTH == 9) ? 3 : 99 | (WIDTH == 18) ? 4 : 100 | (WIDTH == 36) ? 5 : 101 | 0 // for WIDTH 72 use RAMB36SDP 102 | ); 103 | 104 | // map the data bits 105 | localparam D_MSB = ((WIDTH == 4) ? 3 : 106 | (WIDTH == 9) ? 7 : 107 | (WIDTH == 18) ? 15 : 108 | (WIDTH == 36) ? 31 : 109 | 63 110 | ); 111 | 112 | // map the data parity bits 113 | localparam DP_LSB = D_MSB + 1; 114 | 115 | localparam DP_MSB = ((WIDTH == 4) ? 4 : 116 | (WIDTH == 9) ? 8 : 117 | (WIDTH == 18) ? 17 : 118 | (WIDTH == 36) ? 35 : 119 | 71 120 | ); 121 | 122 | localparam DPW = DP_MSB - DP_LSB + 1; 123 | localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" : 124 | ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE"; 125 | 126 | localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6"; 127 | localparam BRAM_SIZE = "36Kb"; 128 | 129 | localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ? 130 | ((WIDTH <= 9) ? 1 : 131 | (WIDTH > 9 && WIDTH <= 18) ? 2 : 132 | (WIDTH > 18 && WIDTH <= 36) ? 4 : 133 | (WIDTH > 36 && WIDTH <= 72) ? 8 : 134 | (BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8; 135 | 136 | //synthesis translate_off 137 | initial begin 138 | //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d", 139 | // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB); 140 | 141 | case (WIDTH) 142 | 4,9,18,36,72:; 143 | default: 144 | begin 145 | $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH); 146 | $finish; 147 | end 148 | endcase // case (WIDTH) 149 | end 150 | //synthesis translate_on 151 | 152 | generate 153 | if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp 154 | BRAM_SDP_MACRO #( 155 | .DEVICE (DEVICE), 156 | .BRAM_SIZE (BRAM_SIZE), 157 | .DO_REG (DOB_REG), 158 | .READ_WIDTH (WIDTH), 159 | .WRITE_WIDTH (WIDTH), 160 | .WRITE_MODE (WRITE_MODE) 161 | ) 162 | ramb36sdp( 163 | .DO (rdata_o[WIDTH-1:0]), 164 | .DI (wdata_i[WIDTH-1:0]), 165 | .RDADDR (raddr_i[ADDR_MSB:0]), 166 | .RDCLK (user_clk_i), 167 | .RDEN (ren_i), 168 | .REGCE (rce_i), 169 | .RST (reset_i), 170 | .WE ({WE_WIDTH{1'b1}}), 171 | .WRADDR (waddr_i[ADDR_MSB:0]), 172 | .WRCLK (user_clk_i), 173 | .WREN (wen_i) 174 | ); 175 | 176 | end // block: use_sdp 177 | else if (WIDTH <= 36) begin : use_tdp 178 | // use RAMB36's if the width is 4, 9, 18, or 36 179 | BRAM_TDP_MACRO #( 180 | .DEVICE (DEVICE), 181 | .BRAM_SIZE (BRAM_SIZE), 182 | .DOA_REG (0), 183 | .DOB_REG (DOB_REG), 184 | .READ_WIDTH_A (WIDTH), 185 | .READ_WIDTH_B (WIDTH), 186 | .WRITE_WIDTH_A (WIDTH), 187 | .WRITE_WIDTH_B (WIDTH), 188 | .WRITE_MODE_A (WRITE_MODE) 189 | ) 190 | ramb36( 191 | .DOA (), 192 | .DOB (rdata_o[WIDTH-1:0]), 193 | .ADDRA (waddr_i[ADDR_MSB:0]), 194 | .ADDRB (raddr_i[ADDR_MSB:0]), 195 | .CLKA (user_clk_i), 196 | .CLKB (user_clk_i), 197 | .DIA (wdata_i[WIDTH-1:0]), 198 | .DIB ({WIDTH{1'b0}}), 199 | .ENA (wen_i), 200 | .ENB (ren_i), 201 | .REGCEA (1'b0), 202 | .REGCEB (rce_i), 203 | .RSTA (reset_i), 204 | .RSTB (reset_i), 205 | .WEA ({WE_WIDTH{1'b1}}), 206 | .WEB ({WE_WIDTH{1'b0}}) 207 | ); 208 | end // block: use_tdp 209 | endgenerate 210 | 211 | endmodule // pcie_bram_7x 212 | 213 | -------------------------------------------------------------------------------- /pcie_7x/zdma/pcie_7x_0_pcie_bram_7x.v: -------------------------------------------------------------------------------- 1 | 2 | //----------------------------------------------------------------------------- 3 | // 4 | // (c) Copyright 2020-2024 Advanced Micro Devices, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of AMD and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // AMD, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) AMD shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or AMD had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // AMD products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of AMD products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //----------------------------------------------------------------------------- 51 | // Project : Series-7 Integrated Block for PCI Express 52 | // File : pcie_7x_0_pcie_bram_7x.v 53 | // Version : 3.3 54 | // Description : single bram wrapper for the mb pcie block 55 | // The bram A port is the write port 56 | // the B port is the read port 57 | // 58 | // 59 | //-----------------------------------------------------------------------------// 60 | 61 | `timescale 1ps/1ps 62 | 63 | (* DowngradeIPIdentifiedWarnings = "yes" *) 64 | module pcie_7x_0_pcie_bram_7x 65 | #( 66 | parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s 67 | parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8 68 | parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT 69 | parameter DOB_REG = 0, // 1 - use the output register; 70 | // 0 - don't use the output register 71 | parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36 72 | // 72 - uses RAMB36SDP 73 | ) 74 | ( 75 | input user_clk_i,// user clock 76 | input reset_i, // bram reset 77 | 78 | input wen_i, // write enable 79 | input [12:0] waddr_i, // write address 80 | input [WIDTH - 1:0] wdata_i, // write data 81 | 82 | input ren_i, // read enable 83 | input rce_i, // output register clock enable 84 | input [12:0] raddr_i, // read address 85 | 86 | output [WIDTH - 1:0] rdata_o // read data 87 | ); 88 | 89 | // map the address bits 90 | localparam ADDR_MSB = ((WIDTH == 4) ? 12 : 91 | (WIDTH == 9) ? 11 : 92 | (WIDTH == 18) ? 10 : 93 | (WIDTH == 36) ? 9 : 94 | 8 95 | ); 96 | 97 | // set the width of the tied off low address bits 98 | localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 : 99 | (WIDTH == 9) ? 3 : 100 | (WIDTH == 18) ? 4 : 101 | (WIDTH == 36) ? 5 : 102 | 0 // for WIDTH 72 use RAMB36SDP 103 | ); 104 | 105 | // map the data bits 106 | localparam D_MSB = ((WIDTH == 4) ? 3 : 107 | (WIDTH == 9) ? 7 : 108 | (WIDTH == 18) ? 15 : 109 | (WIDTH == 36) ? 31 : 110 | 63 111 | ); 112 | 113 | // map the data parity bits 114 | localparam DP_LSB = D_MSB + 1; 115 | 116 | localparam DP_MSB = ((WIDTH == 4) ? 4 : 117 | (WIDTH == 9) ? 8 : 118 | (WIDTH == 18) ? 17 : 119 | (WIDTH == 36) ? 35 : 120 | 71 121 | ); 122 | 123 | localparam DPW = DP_MSB - DP_LSB + 1; 124 | localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" : 125 | ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE"; 126 | 127 | localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6"; 128 | localparam BRAM_SIZE = "36Kb"; 129 | 130 | localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ? 131 | ((WIDTH <= 9) ? 1 : 132 | (WIDTH > 9 && WIDTH <= 18) ? 2 : 133 | (WIDTH > 18 && WIDTH <= 36) ? 4 : 134 | (WIDTH > 36 && WIDTH <= 72) ? 8 : 135 | (BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8; 136 | 137 | //synthesis translate_off 138 | initial begin 139 | //$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d", 140 | // $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB); 141 | 142 | case (WIDTH) 143 | 4,9,18,36,72:; 144 | default: 145 | begin 146 | $display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH); 147 | $finish; 148 | end 149 | endcase // case (WIDTH) 150 | end 151 | //synthesis translate_on 152 | 153 | generate 154 | if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp 155 | BRAM_SDP_MACRO #( 156 | .DEVICE (DEVICE), 157 | .BRAM_SIZE (BRAM_SIZE), 158 | .DO_REG (DOB_REG), 159 | .READ_WIDTH (WIDTH), 160 | .WRITE_WIDTH (WIDTH), 161 | .WRITE_MODE (WRITE_MODE) 162 | ) 163 | ramb36sdp( 164 | .DO (rdata_o[WIDTH-1:0]), 165 | .DI (wdata_i[WIDTH-1:0]), 166 | .RDADDR (raddr_i[ADDR_MSB:0]), 167 | .RDCLK (user_clk_i), 168 | .RDEN (ren_i), 169 | .REGCE (rce_i), 170 | .RST (reset_i), 171 | .WE ({WE_WIDTH{1'b1}}), 172 | .WRADDR (waddr_i[ADDR_MSB:0]), 173 | .WRCLK (user_clk_i), 174 | .WREN (wen_i) 175 | ); 176 | 177 | end // block: use_sdp 178 | else if (WIDTH <= 36) begin : use_tdp 179 | // use RAMB36's if the width is 4, 9, 18, or 36 180 | BRAM_TDP_MACRO #( 181 | .DEVICE (DEVICE), 182 | .BRAM_SIZE (BRAM_SIZE), 183 | .DOA_REG (0), 184 | .DOB_REG (DOB_REG), 185 | .READ_WIDTH_A (WIDTH), 186 | .READ_WIDTH_B (WIDTH), 187 | .WRITE_WIDTH_A (WIDTH), 188 | .WRITE_WIDTH_B (WIDTH), 189 | .WRITE_MODE_A (WRITE_MODE) 190 | ) 191 | ramb36( 192 | .DOA (), 193 | .DOB (rdata_o[WIDTH-1:0]), 194 | .ADDRA (waddr_i[ADDR_MSB:0]), 195 | .ADDRB (raddr_i[ADDR_MSB:0]), 196 | .CLKA (user_clk_i), 197 | .CLKB (user_clk_i), 198 | .DIA (wdata_i[WIDTH-1:0]), 199 | .DIB ({WIDTH{1'b0}}), 200 | .ENA (wen_i), 201 | .ENB (ren_i), 202 | .REGCEA (1'b0), 203 | .REGCEB (rce_i), 204 | .RSTA (reset_i), 205 | .RSTB (reset_i), 206 | .WEA ({WE_WIDTH{1'b1}}), 207 | .WEB ({WE_WIDTH{1'b0}}) 208 | ); 209 | end // block: use_tdp 210 | endgenerate 211 | 212 | endmodule // pcie_bram_7x 213 | 214 | -------------------------------------------------------------------------------- /src/pcileech_tbx4_100t.xdc: -------------------------------------------------------------------------------- 1 | # SW 2 | set_property PACKAGE_PIN F21 [get_ports power_sw] 3 | set_property IOSTANDARD LVCMOS18 [get_ports power_sw] 4 | set_property PULLTYPE PULLUP [get_ports power_sw] 5 | 6 | # LED 7 | set_property PACKAGE_PIN AA5 [get_ports pcie_led] 8 | set_property IOSTANDARD LVCMOS18 [get_ports pcie_led] 9 | 10 | # SYSCLK 11 | set_property PACKAGE_PIN J19 [get_ports clk_in] 12 | set_property IOSTANDARD LVCMOS33 [get_ports clk_in] 13 | create_clock -period 8.000 [get_nets clk] 14 | 15 | #BUS DO 16 | set_property PACKAGE_PIN A21 [get_ports {BUS_DO[0]}] 17 | set_property PACKAGE_PIN A20 [get_ports {BUS_DO[1]}] 18 | set_property PACKAGE_PIN A19 [get_ports {BUS_DO[2]}] 19 | set_property PACKAGE_PIN A18 [get_ports {BUS_DO[3]}] 20 | set_property PACKAGE_PIN A16 [get_ports {BUS_DO[4]}] 21 | set_property PACKAGE_PIN A15 [get_ports {BUS_DO[5]}] 22 | set_property PACKAGE_PIN A14 [get_ports {BUS_DO[6]}] 23 | set_property PACKAGE_PIN A13 [get_ports {BUS_DO[7]}] 24 | set_property PACKAGE_PIN B22 [get_ports {BUS_DO[8]}] 25 | set_property PACKAGE_PIN B21 [get_ports {BUS_DO[9]}] 26 | set_property PACKAGE_PIN B20 [get_ports {BUS_DO[10]}] 27 | set_property PACKAGE_PIN B18 [get_ports {BUS_DO[11]}] 28 | set_property PACKAGE_PIN B17 [get_ports {BUS_DO[12]}] 29 | set_property PACKAGE_PIN B16 [get_ports {BUS_DO[13]}] 30 | set_property PACKAGE_PIN B15 [get_ports {BUS_DO[14]}] 31 | set_property PACKAGE_PIN B13 [get_ports {BUS_DO[15]}] 32 | set_property PACKAGE_PIN C22 [get_ports {BUS_DO[16]}] 33 | set_property PACKAGE_PIN C20 [get_ports {BUS_DO[17]}] 34 | set_property PACKAGE_PIN C19 [get_ports {BUS_DO[18]}] 35 | set_property PACKAGE_PIN C18 [get_ports {BUS_DO[19]}] 36 | set_property PACKAGE_PIN V7 [get_ports {BUS_DO[20]}] 37 | set_property PACKAGE_PIN Y4 [get_ports {BUS_DO[21]}] 38 | set_property PACKAGE_PIN AA4 [get_ports {BUS_DO[22]}] 39 | set_property PACKAGE_PIN V4 [get_ports {BUS_DO[23]}] 40 | set_property PACKAGE_PIN W4 [get_ports {BUS_DO[24]}] 41 | set_property PACKAGE_PIN R4 [get_ports {BUS_DO[25]}] 42 | set_property PACKAGE_PIN T4 [get_ports {BUS_DO[26]}] 43 | set_property PACKAGE_PIN T5 [get_ports {BUS_DO[27]}] 44 | set_property PACKAGE_PIN U5 [get_ports {BUS_DO[28]}] 45 | set_property PACKAGE_PIN W6 [get_ports {BUS_DO[29]}] 46 | set_property PACKAGE_PIN W5 [get_ports {BUS_DO[30]}] 47 | set_property PACKAGE_PIN U6 [get_ports {BUS_DO[31]}] 48 | set_property PACKAGE_PIN V5 [get_ports {BUS_DO[32]}] 49 | set_property PACKAGE_PIN R6 [get_ports {BUS_DO[33]}] 50 | set_property PACKAGE_PIN T6 [get_ports {BUS_DO[34]}] 51 | set_property PACKAGE_PIN Y6 [get_ports {BUS_DO[35]}] 52 | set_property PACKAGE_PIN AA6 [get_ports {BUS_DO[36]}] 53 | set_property IOSTANDARD LVCMOS18 [get_ports {BUS_DO[*]}] 54 | 55 | #BUS DI 56 | set_property PACKAGE_PIN F4 [get_ports {BUS_DI[0]}] 57 | set_property PACKAGE_PIN B1 [get_ports {BUS_DI[1]}] 58 | set_property PACKAGE_PIN A1 [get_ports {BUS_DI[2]}] 59 | set_property PACKAGE_PIN C2 [get_ports {BUS_DI[3]}] 60 | set_property PACKAGE_PIN B2 [get_ports {BUS_DI[4]}] 61 | set_property PACKAGE_PIN E1 [get_ports {BUS_DI[5]}] 62 | set_property PACKAGE_PIN D1 [get_ports {BUS_DI[6]}] 63 | set_property PACKAGE_PIN E2 [get_ports {BUS_DI[7]}] 64 | set_property PACKAGE_PIN D2 [get_ports {BUS_DI[8]}] 65 | set_property PACKAGE_PIN G1 [get_ports {BUS_DI[9]}] 66 | set_property PACKAGE_PIN F1 [get_ports {BUS_DI[10]}] 67 | set_property PACKAGE_PIN F3 [get_ports {BUS_DI[11]}] 68 | set_property PACKAGE_PIN E3 [get_ports {BUS_DI[12]}] 69 | set_property PACKAGE_PIN K1 [get_ports {BUS_DI[13]}] 70 | set_property PACKAGE_PIN J1 [get_ports {BUS_DI[14]}] 71 | set_property PACKAGE_PIN H2 [get_ports {BUS_DI[15]}] 72 | set_property PACKAGE_PIN G2 [get_ports {BUS_DI[16]}] 73 | set_property PACKAGE_PIN K2 [get_ports {BUS_DI[17]}] 74 | set_property PACKAGE_PIN J2 [get_ports {BUS_DI[18]}] 75 | set_property PACKAGE_PIN J5 [get_ports {BUS_DI[19]}] 76 | set_property PACKAGE_PIN H5 [get_ports {BUS_DI[20]}] 77 | set_property PACKAGE_PIN H3 [get_ports {BUS_DI[21]}] 78 | set_property PACKAGE_PIN G3 [get_ports {BUS_DI[22]}] 79 | set_property PACKAGE_PIN H4 [get_ports {BUS_DI[23]}] 80 | set_property PACKAGE_PIN G4 [get_ports {BUS_DI[24]}] 81 | set_property PACKAGE_PIN K4 [get_ports {BUS_DI[25]}] 82 | set_property PACKAGE_PIN J4 [get_ports {BUS_DI[26]}] 83 | set_property PACKAGE_PIN L3 [get_ports {BUS_DI[27]}] 84 | set_property PACKAGE_PIN K3 [get_ports {BUS_DI[28]}] 85 | set_property PACKAGE_PIN M1 [get_ports {BUS_DI[29]}] 86 | set_property PACKAGE_PIN L1 [get_ports {BUS_DI[30]}] 87 | set_property PACKAGE_PIN M3 [get_ports {BUS_DI[31]}] 88 | set_property PACKAGE_PIN M2 [get_ports {BUS_DI[32]}] 89 | set_property PACKAGE_PIN K6 [get_ports {BUS_DI[33]}] 90 | set_property PACKAGE_PIN J6 [get_ports {BUS_DI[34]}] 91 | set_property PACKAGE_PIN L5 [get_ports {BUS_DI[35]}] 92 | set_property PACKAGE_PIN L4 [get_ports {BUS_DI[36]}] 93 | set_property PACKAGE_PIN N4 [get_ports {BUS_DI[37]}] 94 | set_property PACKAGE_PIN N3 [get_ports {BUS_DI[38]}] 95 | set_property PACKAGE_PIN R1 [get_ports {BUS_DI[39]}] 96 | set_property PACKAGE_PIN P1 [get_ports {BUS_DI[40]}] 97 | set_property PACKAGE_PIN P5 [get_ports {BUS_DI[41]}] 98 | set_property PACKAGE_PIN P4 [get_ports {BUS_DI[42]}] 99 | set_property PACKAGE_PIN P2 [get_ports {BUS_DI[43]}] 100 | set_property PACKAGE_PIN N2 [get_ports {BUS_DI[44]}] 101 | set_property PACKAGE_PIN M6 [get_ports {BUS_DI[45]}] 102 | set_property PACKAGE_PIN M5 [get_ports {BUS_DI[46]}] 103 | set_property PACKAGE_PIN P6 [get_ports {BUS_DI[47]}] 104 | set_property PACKAGE_PIN N5 [get_ports {BUS_DI[48]}] 105 | set_property PACKAGE_PIN L6 [get_ports {BUS_DI[49]}] 106 | set_property PACKAGE_PIN T3 [get_ports {BUS_DI[50]}] 107 | set_property PACKAGE_PIN T1 [get_ports {BUS_DI[51]}] 108 | set_property PACKAGE_PIN U1 [get_ports {BUS_DI[52]}] 109 | set_property PACKAGE_PIN U2 [get_ports {BUS_DI[53]}] 110 | set_property PACKAGE_PIN V2 [get_ports {BUS_DI[54]}] 111 | set_property PACKAGE_PIN R3 [get_ports {BUS_DI[55]}] 112 | set_property PACKAGE_PIN R2 [get_ports {BUS_DI[56]}] 113 | set_property PACKAGE_PIN W2 [get_ports {BUS_DI[57]}] 114 | set_property PACKAGE_PIN Y2 [get_ports {BUS_DI[58]}] 115 | set_property PACKAGE_PIN W1 [get_ports {BUS_DI[59]}] 116 | set_property PACKAGE_PIN Y1 [get_ports {BUS_DI[60]}] 117 | set_property PACKAGE_PIN U3 [get_ports {BUS_DI[61]}] 118 | set_property PACKAGE_PIN V3 [get_ports {BUS_DI[62]}] 119 | set_property PACKAGE_PIN AA1 [get_ports {BUS_DI[63]}] 120 | set_property PACKAGE_PIN AB1 [get_ports {BUS_DI[64]}] 121 | set_property PACKAGE_PIN AB3 [get_ports {BUS_DI[65]}] 122 | set_property PACKAGE_PIN AB2 [get_ports {BUS_DI[66]}] 123 | set_property PACKAGE_PIN Y3 [get_ports {BUS_DI[67]}] 124 | set_property PACKAGE_PIN AA3 [get_ports {BUS_DI[68]}] 125 | set_property IOSTANDARD LVCMOS18 [get_ports {BUS_DI[*]}] 126 | 127 | set_property PACKAGE_PIN AB6 [get_ports BUS_DI_PROG_FULL] 128 | set_property IOSTANDARD LVCMOS18 [get_ports BUS_DI_PROG_FULL] 129 | 130 | #TIMING FALSE PATHS 131 | set_false_path -from [get_pins {tickcount64_reg[*]/C}] 132 | set_false_path -from [get_pins {i_pcileech_fifo/_pcie_core_config_reg[*]/C}] 133 | set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_lnk_up_int_reg/C] -to [get_pins {i_pcileech_fifo/_cmd_tx_din_reg[16]/D}] 134 | set_false_path -from [get_pins i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/user_reset_out_reg/C] 135 | 136 | #PCIe signals 137 | set_property PACKAGE_PIN J14 [get_ports pcie_present1] 138 | set_property PACKAGE_PIN AB16 [get_ports pcie_present2] 139 | set_property PACKAGE_PIN J22 [get_ports pcie_perst1_n] 140 | set_property PACKAGE_PIN AB10 [get_ports pcie_perst2_n] 141 | set_property IOSTANDARD LVCMOS33 [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}] 142 | set_property PULLTYPE PULLUP [get_ports {pcie_present1 pcie_present2 pcie_perst1_n pcie_perst2_n}] 143 | 144 | set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 145 | set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 146 | set_property LOC GTPE2_CHANNEL_X0Y6 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 147 | set_property LOC GTPE2_CHANNEL_X0Y7 [get_cells {i_pcileech_pcie_a7x4/i_pcie_7x_0/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i}] 148 | 149 | set_property PACKAGE_PIN A8 [get_ports pcie_rx_n[0]] 150 | set_property PACKAGE_PIN B8 [get_ports pcie_rx_p[0]] 151 | set_property PACKAGE_PIN A4 [get_ports pcie_tx_n[0]] 152 | set_property PACKAGE_PIN B4 [get_ports pcie_tx_p[0]] 153 | 154 | set_property PACKAGE_PIN C11 [get_ports pcie_rx_n[1]] 155 | set_property PACKAGE_PIN D11 [get_ports pcie_rx_p[1]] 156 | set_property PACKAGE_PIN C5 [get_ports pcie_tx_n[1]] 157 | set_property PACKAGE_PIN D5 [get_ports pcie_tx_p[1]] 158 | 159 | set_property PACKAGE_PIN A10 [get_ports pcie_rx_n[2]] 160 | set_property PACKAGE_PIN B10 [get_ports pcie_rx_p[2]] 161 | set_property PACKAGE_PIN A6 [get_ports pcie_tx_n[2]] 162 | set_property PACKAGE_PIN B6 [get_ports pcie_tx_p[2]] 163 | 164 | set_property PACKAGE_PIN C9 [get_ports pcie_rx_n[3]] 165 | set_property PACKAGE_PIN D9 [get_ports pcie_rx_p[3]] 166 | set_property PACKAGE_PIN C7 [get_ports pcie_tx_n[3]] 167 | set_property PACKAGE_PIN D7 [get_ports pcie_tx_p[3]] 168 | 169 | set_property PACKAGE_PIN F10 [get_ports pcie_clk_p] 170 | set_property PACKAGE_PIN E10 [get_ports pcie_clk_n] 171 | create_clock -period 10.000 -name pcie_sys_clk_p [get_nets pcie_clk_p] 172 | 173 | #GENRAL CONFIG 174 | set_property CFGBVS Vcco [current_design] 175 | set_property CONFIG_VOLTAGE 3.3 [current_design] 176 | set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 177 | set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] 178 | set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] 179 | set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] 180 | --------------------------------------------------------------------------------