├── LICENSE ├── LLM_call.py ├── README.md ├── analyze.py ├── autoline ├── TB1_gen.py ├── TB2_syncheck.py ├── TB3_funccheck.py ├── TB4_eval.py ├── TB_autoline.py └── __init__.py ├── autorun.py ├── config ├── __init__.py ├── config.py ├── configs │ ├── 4omini_autobench.yaml │ ├── 4omini_baseline.yaml │ ├── 4omini_correctbench.yaml │ ├── autobench.yaml │ ├── baseline.yaml │ ├── claude_autobench.yaml │ ├── claude_baseline.yaml │ ├── claude_correctbench.yaml │ ├── correctbench.yaml │ ├── demo.yaml │ ├── disc_50wrong_25correct.yaml │ ├── disc_70wrong_25correct.yaml │ └── disc_fullwrong.yaml ├── custom.yaml ├── default.yaml ├── initial_prompts │ ├── prompt1.txt │ ├── prompt2.txt │ └── prompt3.txt ├── key_API.json └── templates │ ├── config_templates │ ├── MutantGen.yaml │ ├── TBeval_partly.yaml │ ├── discrim.yaml │ ├── prompt_chat.yaml │ ├── proset_autoline.yaml │ └── single_autoline.yaml │ └── script_template │ ├── DUT_stage_template_0306.txt │ ├── RTL_template.txt │ ├── directgen_template.txt │ ├── legacy │ ├── DUT_stage_template_0306ex.txt │ ├── DUT_stage_template_nostage3.txt │ ├── DUT_stage_template_scenachecker.txt │ ├── goldenDUT_direct_template.txt │ ├── goldenDUT_stage_template_0306.txt │ ├── rtlflow_template.txt │ ├── stage_template0221.txt │ └── stage_template0306.txt │ ├── mutant_template.txt │ └── pycheck_template.txt ├── data ├── HDLBits │ ├── HDLBits_circuit_type.jsonl │ ├── HDLBits_data.jsonl │ ├── HDLBits_data_RTL_4o_20.jsonl │ ├── HDLBits_data_RTL_4omini_20.jsonl │ ├── HDLBits_data_RTL_sonnet35_20.jsonl │ ├── HDLBits_data_manager.py │ ├── HDLBits_data_mutants.jsonl │ ├── __pycache__ │ │ └── probset.cpython-38.pyc │ └── original_data_human │ │ ├── HDLBits_data_backup0304.jsonl │ │ ├── VerilogDescription_Human.jsonl │ │ └── VerilogEval_Human.jsonl └── probset.py ├── demo └── shift18 │ ├── 1_1_TBgen │ ├── TBgen_codes │ │ ├── TBout.txt │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ ├── shift18.v │ │ ├── shift18_tb.py │ │ ├── shift18_tb.v │ │ └── vlist.txt │ ├── stage_0.txt │ ├── stage_1.txt │ ├── stage_2.txt │ ├── stage_3.txt │ ├── stage_4.txt │ ├── stage_4b.txt │ ├── stage_5.txt │ └── stage_checklist.txt │ ├── 1_3_TBcheck │ ├── correct_1 │ │ ├── TB.py │ │ ├── TB.v │ │ └── conversation.txt │ ├── discrim_0 │ │ ├── RTL_12 │ │ │ ├── DUT.v │ │ │ ├── TBout.txt │ │ │ ├── checker.py │ │ │ ├── driver.v │ │ │ ├── run.vvp │ │ │ ├── run_info.txt │ │ │ ├── run_info_py.txt │ │ │ └── vlist.txt │ │ ├── RTL_17 │ │ │ ├── DUT.v │ │ │ ├── TBout.txt │ │ │ ├── checker.py │ │ │ ├── driver.v │ │ │ ├── run.vvp │ │ │ ├── run_info.txt │ │ │ ├── run_info_py.txt │ │ │ └── vlist.txt │ │ ├── RTL_18 │ │ │ ├── DUT.v │ │ │ ├── TBout.txt │ │ │ ├── checker.py │ │ │ ├── driver.v │ │ │ ├── run.vvp │ │ │ ├── run_info.txt │ │ │ ├── run_info_py.txt │ │ │ └── vlist.txt │ │ ├── RTL_20 │ │ │ ├── DUT.v │ │ │ ├── TBout.txt │ │ │ ├── checker.py │ │ │ ├── driver.v │ │ │ ├── run.vvp │ │ │ ├── run_info.txt │ │ │ ├── run_info_py.txt │ │ │ └── vlist.txt │ │ ├── scenario_matrix.csv │ │ └── scenario_matrix.png │ └── discrim_1 │ │ ├── RTL_1 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_10 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_11 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_13 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_14 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_15 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_16 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_19 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_2 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_3 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_4 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_5 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_6 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_7 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_8 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── RTL_9 │ │ ├── DUT.v │ │ ├── TBout.txt │ │ ├── checker.py │ │ ├── driver.v │ │ ├── run.vvp │ │ ├── run_info.txt │ │ ├── run_info_py.txt │ │ └── vlist.txt │ │ ├── scenario_matrix.csv │ │ └── scenario_matrix.png │ ├── 1_4_TBeval │ ├── eval1_GoldenRTL │ │ ├── run_info.txt │ │ └── run_info_py.txt │ └── eval2_GoldenTB_and_mutants │ │ ├── mutant_1 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_10 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_2 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_3 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_4 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_5 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_6 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_7 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ ├── mutant_8 │ │ ├── GeneratedTB │ │ │ ├── run_info.txt │ │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ │ └── run_info.txt │ │ └── mutant_9 │ │ ├── GeneratedTB │ │ ├── run_info.txt │ │ └── run_info_py.txt │ │ └── GoldenTB │ │ └── run_info.txt │ ├── code_comparison │ ├── new_checker.py │ └── old_checker.py │ ├── final_TB.py │ ├── final_TB.v │ ├── run_info.json │ ├── run_info_short.json │ └── task_log.log ├── figs ├── CorrectBench_Workflow.svg ├── DATE2024_logo_blue_flat.png └── DATE2025_logo_blue_shadow.png ├── iverilog_call.py ├── loader_saver.py ├── main.py ├── prompt_scripts ├── __init__.py ├── base_script.py ├── legacy │ ├── __pycache__ │ │ └── script_RTLchecker0306.cpython-312.pyc │ └── script_RTLchecker0306.py ├── public_stages.py ├── script_directgen.py ├── script_pychecker.py ├── script_pychecker_CMB_new.py ├── script_pychecker_SEQ.py └── utils.py ├── python_call.py ├── requirements.txt └── utils ├── json_utils.py ├── subproc.py └── utils.py /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 Ruidi Qiu 邱瑞迪 @ Technical University of Munich 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /autoline/TB1_gen.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : The TB generation stage in the autoline. The main TB generation workflow is implemented in prompt_scriptws 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/7/24 11:27:21 5 | LastEdited : 2024/8/12 23:30:30 6 | """ 7 | 8 | 9 | from prompt_scripts import get_script, BaseScript 10 | from loader_saver import log_localprefix 11 | 12 | class TaskTBgen(): 13 | # TODO: in the future use pythonized prompt scripts and this class to replace the old TaskTBgen 14 | """TBgen, in this class we generate tb by calling different python script according to stage_template""" 15 | def __init__(self, prob_data: dict, TBgen_prompt_script: str, task_dir: str, config): 16 | self.prob_data = prob_data 17 | self.prompt_script_name = TBgen_prompt_script 18 | self.task_dir = task_dir 19 | self.config = config 20 | WorkFlowClass = get_script(TBgen_prompt_script) 21 | self.workflow = WorkFlowClass( 22 | prob_data = prob_data, 23 | task_dir = task_dir, 24 | config = config 25 | ) 26 | 27 | @log_localprefix("TBgen") 28 | def run(self): 29 | self.workflow() 30 | 31 | @property 32 | def scenario_num(self): 33 | return self.get_wf_attr("scenario_num") 34 | 35 | @property 36 | def scenario_dict(self): 37 | return self.get_wf_attr("scenario_dict") 38 | 39 | def get_wf_attr(self, attr_name:str): 40 | if hasattr(self.workflow, attr_name): 41 | return getattr(self.workflow, attr_name) 42 | else: 43 | return None -------------------------------------------------------------------------------- /autoline/__init__.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : Automatic pipeline of Chatbench: from HDLBits problem to simulation 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2023/12/7 15:13:00 5 | LastEdited : 2024/8/16 13:37:31 6 | autoline.py (c) 2023 7 | """ 8 | 9 | from autoline.TB_autoline import run_autoline 10 | 11 | from autoline.TB1_gen import TaskTBgen 12 | from autoline.TB2_syncheck import TaskTBsim 13 | from autoline.TB3_funccheck import TaskTBcheck, TB_corrector, TB_discriminator 14 | from autoline.TB4_eval import TaskTBeval 15 | 16 | 17 | 18 | if __name__ == "__main__": 19 | raise RuntimeError("you cannot run autoline.py directly!") 20 | # probset = Probset("data/HDLBits/HDLBits_data.jsonl", "data/HDLBits/HDLBits_data_miniset_mutants.jsonl", "data/HDLBits/HDLBits_circuit_type.jsonl", exclude_tasks=['rule110'], filter_content={'circuit_type': 'SEQ'}) 21 | # print(probset.num) 22 | -------------------------------------------------------------------------------- /config/__init__.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : description 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/7/3 18:17:10 5 | LastEdited : 2024/7/3 23:25:11 6 | """ 7 | 8 | from .config import * -------------------------------------------------------------------------------- /config/configs/4omini_autobench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: 4omini/AutoBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-mini-2024-07-18 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: pychecker 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 3 -------------------------------------------------------------------------------- /config/configs/4omini_baseline.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: 4omini/Baseline 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-mini-2024-07-18 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: directgen 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 0 -------------------------------------------------------------------------------- /config/configs/4omini_correctbench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: 4omini/CorrectBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-mini-2024-07-18 12 | rtlgen_model: gpt-4o-mini-2024-07-18 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4omini_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/autobench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: AutoBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: pychecker 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 3 -------------------------------------------------------------------------------- /config/configs/baseline.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Baseline 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: directgen 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 0 -------------------------------------------------------------------------------- /config/configs/claude_autobench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Claude_Sonnet35/AutoBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: claude-3-5-sonnet-20240620 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: pychecker 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 3 -------------------------------------------------------------------------------- /config/configs/claude_baseline.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Claude_Sonnet35/Baseline 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: claude-3-5-sonnet-20240620 12 | autoline: 13 | probset: 14 | path: data/HDLBits/HDLBits_data.jsonl 15 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 16 | onlyrun: TBgensimeval 17 | promptscript: directgen 18 | timeout: 40 19 | save_compile: False 20 | debug: 21 | max: 0 -------------------------------------------------------------------------------- /config/configs/claude_correctbench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Claude_Sonnet35/CorrectBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: claude-3-5-sonnet-20240620 12 | rtlgen_model: claude-3-5-sonnet-20240620 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_sonnet35_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/correctbench.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Main_Results/CorrectBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/demo.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "demo" 7 | subdir: demo 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | only: ["mux2to1v"] 19 | promptscript: pychecker 20 | timeout: 40 21 | save_compile: True 22 | debug: 23 | max: 3 24 | itermax: 10 25 | update_desc: False 26 | TBcheck: 27 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/disc_50wrong_25correct.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: 'NO' 7 | subdir: Disc_Compare/disc_50wrong_25correct 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_50_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/disc_70wrong_25correct.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Disc_Compare/disc_70wrong_25correct 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/configs/disc_fullwrong.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Disc_Compare/disc_fullwrong 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_full_wrong -------------------------------------------------------------------------------- /config/custom.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: "NO" 7 | subdir: Main_Results/CorrectBench 8 | log: 9 | debug_en: False 10 | gpt: 11 | model: gpt-4o-2024-08-06 12 | rtlgen_model: gpt-4o-2024-08-06 13 | autoline: 14 | probset: 15 | path: data/HDLBits/HDLBits_data.jsonl 16 | mutant_path: data/HDLBits/HDLBits_data_mutants.jsonl 17 | more_info_paths: ['data/HDLBits/HDLBits_data_RTL_4o_20.jsonl'] 18 | promptscript: pychecker 19 | timeout: 40 20 | save_compile: False 21 | debug: 22 | max: 3 23 | itermax: 10 24 | update_desc: False 25 | TBcheck: 26 | discrim_mode: col_70_wrong_row_25_correct -------------------------------------------------------------------------------- /config/initial_prompts/prompt1.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/config/initial_prompts/prompt1.txt -------------------------------------------------------------------------------- /config/initial_prompts/prompt2.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/config/initial_prompts/prompt2.txt -------------------------------------------------------------------------------- /config/initial_prompts/prompt3.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/config/initial_prompts/prompt3.txt -------------------------------------------------------------------------------- /config/key_API.json: -------------------------------------------------------------------------------- 1 | { 2 | "OPENAI_API_KEY" : "INSERT_YOUR_OPENAI_API_KEY", 3 | "ANTHROPIC_API_KEY" : "INSERT_YOUR_ANTHROPIC_API_KEY" 4 | } 5 | -------------------------------------------------------------------------------- /config/templates/config_templates/MutantGen.yaml: -------------------------------------------------------------------------------- 1 | # time: 2024/02/15 10:10:26 v2.0 2 | run: 3 | mode: chatgpt 4 | 5 | gpt: 6 | model: "gpt-4-0125-preview" 7 | temperature: 0.8 8 | chatgpt: 9 | start_form: prompt 10 | one_time_talk: True 11 | 12 | save: 13 | en: True 14 | pub: 15 | prefix: "temperature08_rule110_gen10" 16 | subdir: "mutant_gen_test" 17 | -------------------------------------------------------------------------------- /config/templates/config_templates/TBeval_partly.yaml: -------------------------------------------------------------------------------- 1 | # v2.1pre 20240220 2 | run: 3 | mode: autoline 4 | save: 5 | en: True 6 | pub: 7 | prefix: eval-EXP01_mini10 8 | subdir: eval 9 | gpt: 10 | model: 4old 11 | autoline: 12 | probnum: probset 13 | probset: data/HDLBits/HDLBits_data_miniset_subset10.jsonl 14 | mutantset: data/HDLBits/HDLBits_data_miniset_mutants.jsonl 15 | maxdebug: 5 16 | runpartly: 17 | en: True 18 | part: TB_eval 19 | dir: EXP_Analyze/mini10_EXP01_1213 -------------------------------------------------------------------------------- /config/templates/config_templates/discrim.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: autoline 3 | save: 4 | en: True 5 | pub: 6 | prefix: draw_RSmatrix 7 | subdir: discrim 8 | log: 9 | debug_en: True 10 | level: SUCCESS 11 | autoline: 12 | TBcheck: 13 | discrim_mode: col_80_wrong -------------------------------------------------------------------------------- /config/templates/config_templates/prompt_chat.yaml: -------------------------------------------------------------------------------- 1 | run: 2 | mode: chatgpt 3 | save: 4 | en: True 5 | pub: 6 | prefix: pychecker_stage4 7 | subdir: design_stages 8 | load: 9 | prompt: 10 | path: config/initial_prompts/prompt1.txt 11 | gpt: 12 | model: 4 13 | chatgpt: 14 | start_form: "prompt" 15 | one_time_talk: True -------------------------------------------------------------------------------- /config/templates/config_templates/proset_autoline.yaml: -------------------------------------------------------------------------------- 1 | # time: 2024/02/22 14:27:00 v2.1pre 2 | run: 3 | mode: autoline 4 | 5 | save: 6 | en: True 7 | pub: 8 | prefix: "4stagedemo_minisub10" 9 | 10 | gpt: 11 | model: "4" 12 | 13 | autoline: 14 | probnum: probset #probset 15 | probset: "data/HDLBits/HDLBits_data_miniset_subset10.jsonl" 16 | mutantset: data/HDLBits/HDLBits_data_miniset_mutants.jsonl 17 | maxdebug: 5 -------------------------------------------------------------------------------- /config/templates/config_templates/single_autoline.yaml: -------------------------------------------------------------------------------- 1 | # time: 2024/02/22 14:27:00 v2.1pre 2 | run: 3 | mode: autoline 4 | save: 5 | en: True 6 | pub: 7 | prefix: new_autoline_test_rule110 8 | subdir: test 9 | gpt: 10 | model: 4 11 | autoline: 12 | probnum: single 13 | probset: data/HDLBits/HDLBits_data_miniset.jsonl 14 | mutantset: data/HDLBits/HDLBits_data_miniset_mutants.jsonl 15 | single: 16 | taskid: rule110 -------------------------------------------------------------------------------- /config/templates/script_template/RTL_template.txt: -------------------------------------------------------------------------------- 1 | task: 2 | Hello, you are a hardware engineering assistant. You will be given a description of an RTL circuit and its corresponding module header in verilog. 3 | Please generate the corresponding verilog code of the circuit according to the information provided. 4 | 5 | tips: 6 | please only reply me the RTL circuit code in verilog 7 | you have enough tokens to response 8 | 9 | 10 | reply format: 11 | ```verilog 12 | (verilog code) 13 | ``` 14 | 15 | RTL problem description (this can help you understand the RTL code): 16 | {$problem description from HDLBits$} 17 | 18 | RTL module: 19 | {$header from HDLBits$} -------------------------------------------------------------------------------- /config/templates/script_template/directgen_template.txt: -------------------------------------------------------------------------------- 1 | stage 1: 2 | 3 | Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". 4 | 5 | your testbench template is: 6 | [testbench template] 7 | 8 | [problem description from HDLBits] 9 | 10 | DUT header: 11 | [module header] 12 | 13 | very very IMPORTANT: If all the test cases pass, the testbench should display "all test cases passed". If any one of the test cases fails, testbench should not display "all test caess passed". 14 | please don't reply other words except the testbench codes. -------------------------------------------------------------------------------- /config/templates/script_template/legacy/goldenDUT_direct_template.txt: -------------------------------------------------------------------------------- 1 | stage 1: 2 | 3 | 1. Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is 4 | - 1.1. the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". 5 | - 1.2. the module header. 6 | - 1.3. the golden RTL codes in verilog. In testbench you should compare the signals from golden RTL and DUT. If not the same, then this DUT fails in the test. 7 | Our target is to generate the verilog testbench for the DUT. This testbench can check if the DUT in verilog satisfies all technical requirements from the problem description. 8 | 2. you are in section 4. in this section, you will be provided with test scenarios and golden DUT. please highly based on these information to generate the testbench. 9 | 3. In the scenarios testing part, do not directly write the value of expected value, but generate expected value from golden RTL. 10 | 4. your information is: 11 | 12 | your testbench template is: 13 | [testbench template] 14 | 15 | [problem description from HDLBits] 16 | [module header] 17 | 18 | IMPORTANT - golden RTL: (please instantiate it in your testbench. Your code should not contain the full code of golden RTL) 19 | [module code] 20 | 21 | very very IMPORTANT: If all the test cases pass, the testbench should display "all test cases passed". If any one of the test cases fails, testbench should not display "all test caess passed". 22 | please don't reply other words except the testbench codes. 23 | 24 | [$$TB_code module_code$$] -------------------------------------------------------------------------------- /config/templates/script_template/mutant_template.txt: -------------------------------------------------------------------------------- 1 | task: 2 | Hello, you are a hardware engineering assistant. You will be given a description of an RTL circuit and its corresponding correct RTL code in verilog. 3 | Making a very small change on it so it will has a little difference with the original RTL circuit. In this way we will get a mutant RTL. 4 | your task is to generate {$n$} different mutant RTLs. You should evenly choose the positions where the changes are added. you should try different modification types but modification should be minor. 5 | the module header is unchangeable. 6 | 7 | 8 | tips: 9 | please only reply me the mutant RTL circuit in verilog 10 | please make an annotation where you changed 11 | you have enough tokens to response 12 | 13 | 14 | reply format: 15 | //// mutant 1 //// 16 | (first mutant verilog code) 17 | 18 | //// mutant 2 //// 19 | (second mutant verilog code) 20 | 21 | ... 22 | 23 | //// mutant n //// 24 | (nth mutant verilog code) 25 | 26 | 27 | RTL problem description (this can help you understand the RTL code): 28 | {$problem description from HDLBits$} 29 | 30 | 31 | correct RTL code: 32 | {$RTL code from HDLBits$} -------------------------------------------------------------------------------- /data/HDLBits/__pycache__/probset.cpython-38.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/data/HDLBits/__pycache__/probset.cpython-38.pyc -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = x 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = x 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = x 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = x 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = x 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = x 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = x 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = x 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = x 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = x 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = x 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = x 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = x 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = x 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = x 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = x 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = x 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = x 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = x 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = x 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = x 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = x 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = x 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = x 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = x 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = x 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = x 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = x 31 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Scenario: 1, expected: q=12297829382473034410, observed q=0 5 | Failed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 0} 6 | Scenario: 2, expected: q=12297829382473034408, observed q=0 7 | Failed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 0} 8 | Scenario: 3, expected: q=6148914691236515840, observed q=0 9 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 0} 10 | Scenario: 4, expected: q=3074457345618083840, observed q=0 11 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 0} 12 | Scenario: 5, expected: q=6004799503160320, observed q=0 13 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 0} 14 | Scenario: 6, expected: q=23456248059220, observed q=0 15 | Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 0} 16 | Scenario: 7, expected: q=6148914691236517205, observed q=0 17 | Failed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 0} 18 | Scenario: 8, expected: q=18446744073709551614, observed q=0 19 | Failed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 0} 20 | Scenario: 9, expected: q=4611686018427387904, observed q=0 21 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 0} 22 | Scenario: 9, expected: q=9007199254740992, observed q=0 23 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 0} 24 | Scenario: 10, expected: q=70368744177664, observed q=0 25 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 0} 26 | Scenario: 10, expected: q=140737488355328, observed q=0 27 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 0} 28 | Scenario: 10, expected: q=281474976710656, observed q=0 29 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 0} 30 | Scenario: 11, expected: q=1311768467463790320, observed q=0 31 | Failed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 0} 32 | ['1', '2', '3', '4', '5', '6', '7', '8', '9', '9', '10', '10', '10', '11'] 33 | 34 | 35 | ###error: 36 | 37 | 38 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/shift18.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/shift18_tb.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False 41 | 42 | def check_dut(vectors_in): 43 | golden_dut = GoldenDUT() 44 | failed_scenarios = [] 45 | for vector in vectors_in: 46 | if vector["check_en"]: 47 | check_pass = golden_dut.check(vector) 48 | if check_pass: 49 | print(f"Passed; vector: {vector}") 50 | else: 51 | print(f"Failed; vector: {vector}") 52 | failed_scenarios.append(vector["scenario"]) 53 | golden_dut.load(vector) 54 | return failed_scenarios 55 | 56 | def SignalTxt_to_dictlist(txt:str): 57 | signals = [] 58 | lines = txt.strip().split("\n") 59 | for line in lines: 60 | signal = {} 61 | if line.startswith("[check]"): 62 | signal["check_en"] = True 63 | line = line[7:] 64 | elif line.startswith("scenario"): 65 | signal["check_en"] = False 66 | else: 67 | continue 68 | line = line.strip().split(", ") 69 | for item in line: 70 | if "scenario" in item: 71 | item = item.split(": ") 72 | signal["scenario"] = item[1].replace(" ", "") 73 | else: 74 | item = item.split(" = ") 75 | key = item[0] 76 | value = item[1] 77 | if ("x" not in value) and ("X" not in value) and ("z" not in value): 78 | signal[key] = int(value) 79 | else: 80 | if ("x" in value) or ("X" in value): 81 | signal[key] = 0 # used to be "x" 82 | else: 83 | signal[key] = 0 # used to be "z" 84 | signals.append(signal) 85 | return signals 86 | with open("TBout.txt", "r") as f: 87 | txt = f.read() 88 | vectors_in = SignalTxt_to_dictlist(txt) 89 | tb_pass = check_dut(vectors_in) 90 | print(tb_pass) 91 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/TBgen_codes/vlist.txt: -------------------------------------------------------------------------------- 1 | shift18_tb.v 2 | shift18.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/stage_0.txt: -------------------------------------------------------------------------------- 1 | ############################## conversation begin ############################## 2 | ########## system ########## 3 | You are the strongest AI in the world. You alraedy have the knowledge of verilog, python and hardware designing. Do not save words by discarding information. I will tip you 200$ if you can fullfill the tasks I give you. 4 | 5 | ########## user ########## 6 | Please generate the verilog RTL code according to the following description and header information: 7 | problem description: 8 | Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by "amount." Assume the right shit is an arithmetic right shift. 9 | 10 | // Signals are defined as below: 11 | // (1) load: Loads shift register with data[63:0] instead of shifting. Active high. 12 | // (2) ena: Chooses whether to shift. Active high. 13 | // (3) amount: Chooses which direction and how much to shift. 14 | // (a) 2'b00: shift left by 1 bit. 15 | // (b) 2'b01: shift left by 8 bits. 16 | // (c) 2'b10: shift right by 1 bit. 17 | // (d) 2'b11: shift right by 8 bits. 18 | // (4) q: The contents of the shifter. 19 | RTL header: 20 | module top_module( 21 | input clk, 22 | input load, 23 | input ena, 24 | input [1:0] amount, 25 | input [63:0] data, 26 | output reg [63:0] q); 27 | 28 | please only reply verilog codes. reply_format: 29 | ```verilog 30 | your_code_here... 31 | ``` 32 | 33 | 34 | ########## assistant ########## 35 | ```verilog 36 | module top_module( 37 | input clk, 38 | input load, 39 | input ena, 40 | input [1:0] amount, 41 | input [63:0] data, 42 | output reg [63:0] q); 43 | 44 | always @(posedge clk) begin 45 | if (load) 46 | q <= data; 47 | else if (ena) begin 48 | case (amount) 49 | 2'b00: q <= q << 1; 50 | 2'b01: q <= q << 8; 51 | 2'b10: q <= $signed(q) >>> 1; 52 | 2'b11: q <= $signed(q) >>> 8; 53 | default: q <= q; 54 | endcase 55 | end 56 | end 57 | 58 | endmodule 59 | ``` 60 | 61 | -------------------------------------------------------------------------------- /demo/shift18/1_1_TBgen/stage_checklist.txt: -------------------------------------------------------------------------------- 1 | 2 | [SYSTEM PRECHECK] All scenarios are included in the testbench code. You can continue to the next stage. -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; // Shift left by 1 bit 15 | 2'b01: q <= q << 8; // Shift left by 8 bits 16 | 2'b10: q <= q >>> 1; // Arithmetic shift right by 1 bit 17 | 2'b11: q <= q >>> 8; // Arithmetic shift right by 8 bits 18 | default: q <= q; // Default case to avoid latches, though not needed here 19 | endcase 20 | end 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 4611686018427387904 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 2305843009213693952 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 9007199254740992 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 35184372088832 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 70368744177664 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 140737488355328 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 281474976710656 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 562949953421312 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False 41 | 42 | def check_dut(vectors_in): 43 | golden_dut = GoldenDUT() 44 | failed_scenarios = [] 45 | for vector in vectors_in: 46 | if vector["check_en"]: 47 | check_pass = golden_dut.check(vector) 48 | if check_pass: 49 | print(f"Passed; vector: {vector}") 50 | else: 51 | print(f"Failed; vector: {vector}") 52 | failed_scenarios.append(vector["scenario"]) 53 | golden_dut.load(vector) 54 | return failed_scenarios 55 | 56 | def SignalTxt_to_dictlist(txt:str): 57 | signals = [] 58 | lines = txt.strip().split("\n") 59 | for line in lines: 60 | signal = {} 61 | if line.startswith("[check]"): 62 | signal["check_en"] = True 63 | line = line[7:] 64 | elif line.startswith("scenario"): 65 | signal["check_en"] = False 66 | else: 67 | continue 68 | line = line.strip().split(", ") 69 | for item in line: 70 | if "scenario" in item: 71 | item = item.split(": ") 72 | signal["scenario"] = item[1].replace(" ", "") 73 | else: 74 | item = item.split(" = ") 75 | key = item[0] 76 | value = item[1] 77 | if ("x" not in value) and ("X" not in value) and ("z" not in value): 78 | signal[key] = int(value) 79 | else: 80 | if ("x" in value) or ("X" in value): 81 | signal[key] = 0 # used to be "x" 82 | else: 83 | signal[key] = 0 # used to be "z" 84 | signals.append(signal) 85 | return signals 86 | with open("TBout.txt", "r") as f: 87 | txt = f.read() 88 | vectors_in = SignalTxt_to_dictlist(txt) 89 | tb_pass = check_dut(vectors_in) 90 | print(tb_pass) 91 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387904} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740992} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177664} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355328} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710656} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_12/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= q >>> 1; 17 | 2'b11: q <= q >>> 8; 18 | endcase 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 4611686018427387904 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 2305843009213693952 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 9007199254740992 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 35184372088832 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 70368744177664 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 140737488355328 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 281474976710656 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 562949953421312 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False 41 | 42 | def check_dut(vectors_in): 43 | golden_dut = GoldenDUT() 44 | failed_scenarios = [] 45 | for vector in vectors_in: 46 | if vector["check_en"]: 47 | check_pass = golden_dut.check(vector) 48 | if check_pass: 49 | print(f"Passed; vector: {vector}") 50 | else: 51 | print(f"Failed; vector: {vector}") 52 | failed_scenarios.append(vector["scenario"]) 53 | golden_dut.load(vector) 54 | return failed_scenarios 55 | 56 | def SignalTxt_to_dictlist(txt:str): 57 | signals = [] 58 | lines = txt.strip().split("\n") 59 | for line in lines: 60 | signal = {} 61 | if line.startswith("[check]"): 62 | signal["check_en"] = True 63 | line = line[7:] 64 | elif line.startswith("scenario"): 65 | signal["check_en"] = False 66 | else: 67 | continue 68 | line = line.strip().split(", ") 69 | for item in line: 70 | if "scenario" in item: 71 | item = item.split(": ") 72 | signal["scenario"] = item[1].replace(" ", "") 73 | else: 74 | item = item.split(" = ") 75 | key = item[0] 76 | value = item[1] 77 | if ("x" not in value) and ("X" not in value) and ("z" not in value): 78 | signal[key] = int(value) 79 | else: 80 | if ("x" in value) or ("X" in value): 81 | signal[key] = 0 # used to be "x" 82 | else: 83 | signal[key] = 0 # used to be "z" 84 | signals.append(signal) 85 | return signals 86 | with open("TBout.txt", "r") as f: 87 | txt = f.read() 88 | vectors_in = SignalTxt_to_dictlist(txt) 89 | tb_pass = check_dut(vectors_in) 90 | print(tb_pass) 91 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387904} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740992} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177664} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355328} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710656} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_17/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q 8 | ); 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; // Shift left by 1 bit 16 | 2'b01: q <= q << 8; // Shift left by 8 bits 17 | 2'b10: q <= q >>> 1; // Arithmetic shift right by 1 bit 18 | 2'b11: q <= q >>> 8; // Arithmetic shift right by 8 bits 19 | default: q <= q; 20 | endcase 21 | end 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 4611686018427387904 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 2305843009213693952 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 9007199254740992 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 35184372088832 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 70368744177664 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 140737488355328 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 281474976710656 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 562949953421312 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False 41 | 42 | def check_dut(vectors_in): 43 | golden_dut = GoldenDUT() 44 | failed_scenarios = [] 45 | for vector in vectors_in: 46 | if vector["check_en"]: 47 | check_pass = golden_dut.check(vector) 48 | if check_pass: 49 | print(f"Passed; vector: {vector}") 50 | else: 51 | print(f"Failed; vector: {vector}") 52 | failed_scenarios.append(vector["scenario"]) 53 | golden_dut.load(vector) 54 | return failed_scenarios 55 | 56 | def SignalTxt_to_dictlist(txt:str): 57 | signals = [] 58 | lines = txt.strip().split("\n") 59 | for line in lines: 60 | signal = {} 61 | if line.startswith("[check]"): 62 | signal["check_en"] = True 63 | line = line[7:] 64 | elif line.startswith("scenario"): 65 | signal["check_en"] = False 66 | else: 67 | continue 68 | line = line.strip().split(", ") 69 | for item in line: 70 | if "scenario" in item: 71 | item = item.split(": ") 72 | signal["scenario"] = item[1].replace(" ", "") 73 | else: 74 | item = item.split(" = ") 75 | key = item[0] 76 | value = item[1] 77 | if ("x" not in value) and ("X" not in value) and ("z" not in value): 78 | signal[key] = int(value) 79 | else: 80 | if ("x" in value) or ("X" in value): 81 | signal[key] = 0 # used to be "x" 82 | else: 83 | signal[key] = 0 # used to be "z" 84 | signals.append(signal) 85 | return signals 86 | with open("TBout.txt", "r") as f: 87 | txt = f.read() 88 | vectors_in = SignalTxt_to_dictlist(txt) 89 | tb_pass = check_dut(vectors_in) 90 | print(tb_pass) 91 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387904} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740992} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177664} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355328} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710656} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_18/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; 16 | 2'b01: q <= q << 8; 17 | 2'b10: q <= q >>> 1; 18 | 2'b11: q <= q >>> 8; 19 | default: q <= q; // Optional, in case no condition is met 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 4611686018427387904 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 2305843009213693952 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 9007199254740992 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 35184372088832 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 70368744177664 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 140737488355328 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 281474976710656 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 562949953421312 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False 41 | 42 | def check_dut(vectors_in): 43 | golden_dut = GoldenDUT() 44 | failed_scenarios = [] 45 | for vector in vectors_in: 46 | if vector["check_en"]: 47 | check_pass = golden_dut.check(vector) 48 | if check_pass: 49 | print(f"Passed; vector: {vector}") 50 | else: 51 | print(f"Failed; vector: {vector}") 52 | failed_scenarios.append(vector["scenario"]) 53 | golden_dut.load(vector) 54 | return failed_scenarios 55 | 56 | def SignalTxt_to_dictlist(txt:str): 57 | signals = [] 58 | lines = txt.strip().split("\n") 59 | for line in lines: 60 | signal = {} 61 | if line.startswith("[check]"): 62 | signal["check_en"] = True 63 | line = line[7:] 64 | elif line.startswith("scenario"): 65 | signal["check_en"] = False 66 | else: 67 | continue 68 | line = line.strip().split(", ") 69 | for item in line: 70 | if "scenario" in item: 71 | item = item.split(": ") 72 | signal["scenario"] = item[1].replace(" ", "") 73 | else: 74 | item = item.split(" = ") 75 | key = item[0] 76 | value = item[1] 77 | if ("x" not in value) and ("X" not in value) and ("z" not in value): 78 | signal[key] = int(value) 79 | else: 80 | if ("x" in value) or ("X" in value): 81 | signal[key] = 0 # used to be "x" 82 | else: 83 | signal[key] = 0 # used to be "z" 84 | signals.append(signal) 85 | return signals 86 | with open("TBout.txt", "r") as f: 87 | txt = f.read() 88 | vectors_in = SignalTxt_to_dictlist(txt) 89 | tb_pass = check_dut(vectors_in) 90 | print(tb_pass) 91 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387904} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740992} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177664} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355328} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710656} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/RTL_20/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/scenario_matrix.csv: -------------------------------------------------------------------------------- 1 | 1,1,1,1,1,1,1,1,0,0,1 2 | 1,1,1,1,1,1,1,1,0,0,1 3 | 1,1,1,1,1,1,1,1,0,0,1 4 | 1,1,1,1,1,1,1,1,0,0,1 5 | 1,1,1,1,1,1,1,1,0,0,1 6 | 1,1,1,1,1,1,1,1,0,0,1 7 | 1,1,1,1,1,1,1,1,0,0,1 8 | 1,1,1,1,1,1,1,1,0,0,1 9 | 1,1,1,1,1,1,1,1,0,0,1 10 | 1,1,1,1,1,1,1,1,0,0,1 11 | 1,1,1,1,1,1,1,1,0,0,1 12 | 1,1,1,1,1,1,1,1,1,1,1 13 | 1,1,1,1,1,1,1,1,0,0,1 14 | 1,1,1,1,1,1,1,1,0,0,1 15 | 1,1,1,1,1,1,1,1,0,0,1 16 | 1,1,1,1,1,1,1,1,0,0,1 17 | 1,1,1,1,1,1,1,1,1,1,1 18 | 1,1,1,1,1,1,1,1,1,1,1 19 | 1,1,1,1,1,1,1,1,0,0,1 20 | 1,1,1,1,1,1,1,1,1,1,1 21 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_0/scenario_matrix.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/demo/shift18/1_3_TBcheck/discrim_0/scenario_matrix.png -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_1/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; 16 | 2'b01: q <= q << 8; 17 | 2'b10: q <= $signed(q) >>> 1; 18 | 2'b11: q <= $signed(q) >>> 8; 19 | default: q <= q; // Default case not strictly necessary, but good practice 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_1/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 13835058055282163712 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 16140901064495857664 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 18437736874454810624 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446708889337462784 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446673704965373952 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446603336221196288 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446462598732840960 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 18446181123756130304 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_1/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_1/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_1/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_10/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 18 | endcase 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_10/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 13835058055282163712 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 16140901064495857664 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 18437736874454810624 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446708889337462784 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446673704965373952 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446603336221196288 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446462598732840960 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 18446181123756130304 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_10/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_10/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_10/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_11/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; 16 | 2'b01: q <= q << 8; 17 | 2'b10: q <= {q[63], q[63:1]}; 18 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_11/TBout.txt: -------------------------------------------------------------------------------- 1 | scenario: 1, clk = 0, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = x 2 | [check]scenario: 1, clk = 1, load = 1, ena = 0, amount = 0, data = 12297829382473034410, q = 12297829382473034410 3 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034410 4 | scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 6148914691236517204 5 | [check]scenario: 2, clk = 1, load = 0, ena = 1, amount = 0, data = 12297829382473034410, q = 12297829382473034408 6 | scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236517200 7 | [check]scenario: 3, clk = 1, load = 0, ena = 1, amount = 1, data = 12297829382473034410, q = 6148914691236515840 8 | scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 6148914691236167680 9 | [check]scenario: 4, clk = 1, load = 0, ena = 1, amount = 2, data = 12297829382473034410, q = 3074457345618083840 10 | scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 1537228672809041920 11 | [check]scenario: 5, clk = 1, load = 0, ena = 1, amount = 3, data = 12297829382473034410, q = 6004799503160320 12 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 3, data = 12297829382473034410, q = 23456248059220 13 | scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 14 | [check]scenario: 6, clk = 1, load = 0, ena = 0, amount = 0, data = 12297829382473034410, q = 23456248059220 15 | scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 23456248059220 16 | [check]scenario: 7, clk = 1, load = 1, ena = 0, amount = 0, data = 6148914691236517205, q = 6148914691236517205 17 | scenario: 8, clk = 1, load = 1, ena = 0, amount = 0, data = 18446744073709551615, q = 6148914691236517205 18 | scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551615 19 | [check]scenario: 8, clk = 1, load = 0, ena = 1, amount = 0, data = 18446744073709551615, q = 18446744073709551614 20 | scenario: 9, clk = 1, load = 1, ena = 1, amount = 0, data = 9223372036854775808, q = 18446744073709551612 21 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 9223372036854775808 22 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 2, data = 9223372036854775808, q = 13835058055282163712 23 | scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 16140901064495857664 24 | [check]scenario: 9, clk = 1, load = 0, ena = 1, amount = 3, data = 9223372036854775808, q = 18437736874454810624 25 | scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446708889337462784 26 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446673704965373952 27 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446603336221196288 28 | [check]scenario: 10, clk = 1, load = 0, ena = 1, amount = 0, data = 9223372036854775808, q = 18446462598732840960 29 | scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 18446181123756130304 30 | [check]scenario: 11, clk = 1, load = 1, ena = 0, amount = 0, data = 1311768467463790320, q = 1311768467463790320 31 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_11/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_11/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_11/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_13/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (load) begin 12 | q <= data; 13 | end else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; // Shift left by 1 bit 16 | 2'b01: q <= q << 8; // Shift left by 8 bits 17 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic shift right by 1 bit 18 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic shift right by 8 bits 19 | default: q <= q; // No change by default 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_13/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_13/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_13/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_14/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 18 | default: q <= q; // default case to handle any unexpected values 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_14/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_14/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_14/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_15/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= {q[63], q[63:1]}; 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; 18 | default: q <= q; // Default case to handle unexpected values 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_15/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_15/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_15/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_16/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; 16 | 2'b01: q <= q << 8; 17 | 2'b10: q <= $signed(q) >>> 1; 18 | 2'b11: q <= $signed(q) >>> 8; 19 | default: q <= q; 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_16/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_16/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_16/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_19/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 18 | endcase 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_19/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_19/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_19/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_2/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (load) begin 12 | q <= data; 13 | end else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; // Shift left by 1 bit 16 | 2'b01: q <= q << 8; // Shift left by 8 bits 17 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic Shift right by 1 bit 18 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic Shift right by 8 bits 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_2/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_2/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_2/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_3/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; // Shift left by 1 bit 15 | 2'b01: q <= q << 8; // Shift left by 8 bits 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic shift right by 1 bit 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic shift right by 8 bits 18 | default: q <= q; 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_3/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_3/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_3/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_4/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; // Shift left by 1 bit 15 | 2'b01: q <= q << 8; // Shift left by 8 bits 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 bit 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 bits 18 | default: q <= q; // default case to hold the value 19 | endcase 20 | end 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_4/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_4/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_4/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_5/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; 16 | 2'b01: q <= q << 8; 17 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 18 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 19 | default: q <= q; 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_5/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_5/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_5/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_6/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= $signed(q) >>> 1; 17 | 2'b11: q <= $signed(q) >>> 8; 18 | default: q <= q; // Optional, for completeness 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_6/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_6/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_6/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_7/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end 13 | else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; // Shift left by 1 bit 16 | 2'b01: q <= q << 8; // Shift left by 8 bits 17 | 2'b10: q <= $signed(q) >>> 1; // Arithmetic shift right by 1 bit 18 | 2'b11: q <= $signed(q) >>> 8; // Arithmetic shift right by 8 bits 19 | endcase 20 | end 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_7/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_7/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_7/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_8/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q); 8 | 9 | always @(posedge clk) begin 10 | if (load) begin 11 | q <= data; 12 | end else if (ena) begin 13 | case (amount) 14 | 2'b00: q <= q << 1; 15 | 2'b01: q <= q << 8; 16 | 2'b10: q <= {q[63], q[63:1]}; // Arithmetic right shift by 1 17 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; // Arithmetic right shift by 8 18 | endcase 19 | end 20 | end 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_8/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_8/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_8/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_9/DUT.v: -------------------------------------------------------------------------------- 1 | module top_module( 2 | input clk, 3 | input load, 4 | input ena, 5 | input [1:0] amount, 6 | input [63:0] data, 7 | output reg [63:0] q 8 | ); 9 | 10 | always @(posedge clk) begin 11 | if (load) begin 12 | q <= data; 13 | end else if (ena) begin 14 | case (amount) 15 | 2'b00: q <= q << 1; // Shift left by 1 bit 16 | 2'b01: q <= q << 8; // Shift left by 8 bits 17 | 2'b10: q <= $signed(q) >>> 1; // Arithmetic shift right by 1 bit 18 | 2'b11: q <= $signed(q) >>> 8; // Arithmetic shift right by 8 bits 19 | default: q <= q; 20 | endcase 21 | end 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_9/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp driver.v DUT.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | driver.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_9/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/RTL_9/vlist.txt: -------------------------------------------------------------------------------- 1 | driver.v 2 | DUT.v 3 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/scenario_matrix.csv: -------------------------------------------------------------------------------- 1 | 1,1,1,1,1,1,1,1,1,1,1 2 | 1,1,1,1,1,1,1,1,1,1,1 3 | 1,1,1,1,1,1,1,1,1,1,1 4 | 1,1,1,1,1,1,1,1,1,1,1 5 | 1,1,1,1,1,1,1,1,1,1,1 6 | 1,1,1,1,1,1,1,1,1,1,1 7 | 1,1,1,1,1,1,1,1,1,1,1 8 | 1,1,1,1,1,1,1,1,1,1,1 9 | 1,1,1,1,1,1,1,1,1,1,1 10 | 1,1,1,1,1,1,1,1,1,1,1 11 | 1,1,1,1,1,1,1,1,1,1,1 12 | 1,1,1,1,1,1,1,1,0,0,1 13 | 1,1,1,1,1,1,1,1,1,1,1 14 | 1,1,1,1,1,1,1,1,1,1,1 15 | 1,1,1,1,1,1,1,1,1,1,1 16 | 1,1,1,1,1,1,1,1,1,1,1 17 | 1,1,1,1,1,1,1,1,0,0,1 18 | 1,1,1,1,1,1,1,1,0,0,1 19 | 1,1,1,1,1,1,1,1,1,1,1 20 | 1,1,1,1,1,1,1,1,0,0,1 21 | -------------------------------------------------------------------------------- /demo/shift18/1_3_TBcheck/discrim_1/scenario_matrix.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/demo/shift18/1_3_TBcheck/discrim_1/scenario_matrix.png -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval1_GoldenRTL/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval1_GoldenRTL/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_1/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_1/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Scenario: 2, expected: q=aaaaaaaaaaaaaaa8, observed q=aaaaaaaaaaaaaaab 6 | Failed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034411} 7 | Scenario: 3, expected: q=5555555555555000, observed q=5555555555555700 8 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236517632} 9 | Scenario: 4, expected: q=2aaaaaaaaaa80000, observed q=2aaaaaaaaaab8000 10 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618313216} 11 | Scenario: 5, expected: q=0015555555555400, observed q=00155555555555c0 12 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160768} 13 | Scenario: 6, expected: q=0000155555555554, observed q=0000155555555555 14 | Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059221} 15 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 16 | Scenario: 8, expected: q=fffffffffffffffe, observed q=ffffffffffffffff 17 | Failed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551615} 18 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 19 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 20 | Scenario: 10, expected: q=ffffc00000000000, observed q=ffffc00000000001 21 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373953} 22 | Scenario: 10, expected: q=ffff800000000000, observed q=ffff800000000003 23 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196291} 24 | Scenario: 10, expected: q=ffff000000000000, observed q=ffff000000000007 25 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840967} 26 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 27 | ['2', '3', '4', '5', '6', '8', '10', '10', '10'] 28 | 29 | 30 | ###error: 31 | 32 | 33 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_1/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 2424 mismatches. First mismatch occurred at time 80. 15 | Hint: Total mismatched samples is 2424 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 2424 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_10/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_10/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_10/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has no mismatches. 15 | Hint: Total mismatched samples is 0 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 0 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_2/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_2/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Scenario: 3, expected: q=5555555555555000, observed q=55555555555550ff 7 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236516095} 8 | Scenario: 4, expected: q=2aaaaaaaaaa80000, observed q=2aaaaaaaaaa87fff 9 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618116607} 10 | Scenario: 5, expected: q=0015555555555400, observed q=001555555555543f 11 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160383} 12 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 13 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 14 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 15 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 16 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 17 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 18 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 19 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 20 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 21 | ['3', '4', '5'] 22 | 23 | 24 | ###error: 25 | 26 | 27 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_2/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 3050 mismatches. First mismatch occurred at time 60. 15 | Hint: Total mismatched samples is 3050 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 3050 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_3/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_3/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Scenario: 1, expected: q=aaaaaaaaaaaaaaaa, observed q=5555555555555555 5 | Failed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 6148914691236517205} 6 | Scenario: 2, expected: q=aaaaaaaaaaaaaaa8, observed q=5555555555555554 7 | Failed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 6148914691236517204} 8 | Scenario: 3, expected: q=5555555555555000, observed q=aaaaaaaaaaaaa800 9 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 12297829382473033728} 10 | Scenario: 4, expected: q=2aaaaaaaaaa80000, observed q=d555555555540000 11 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 15372286728091205632} 12 | Scenario: 5, expected: q=0015555555555400, observed q=ffeaaaaaaaaaaa00 13 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 18440739274206390784} 14 | Scenario: 6, expected: q=0000155555555554, observed q=ffffeaaaaaaaaaaa 15 | Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 18446720617461492394} 16 | Scenario: 7, expected: q=5555555555555555, observed q=aaaaaaaaaaaaaaaa 17 | Failed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 12297829382473034410} 18 | Scenario: 8, expected: q=fffffffffffffffe, observed q=0000000000000000 19 | Failed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 0} 20 | Scenario: 9, expected: q=c000000000000000, observed q=3fffffffffffffff 21 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387903} 22 | Scenario: 9, expected: q=ffe0000000000000, observed q=001fffffffffffff 23 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740991} 24 | Scenario: 10, expected: q=ffffc00000000000, observed q=00003ffffffffffe 25 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177662} 26 | Scenario: 10, expected: q=ffff800000000000, observed q=00007ffffffffffc 27 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355324} 28 | Scenario: 10, expected: q=ffff000000000000, observed q=0000fffffffffff8 29 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710648} 30 | Scenario: 11, expected: q=123456789abcdef0, observed q=edcba9876543210f 31 | Failed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 17134975606245761295} 32 | ['1', '2', '3', '4', '5', '6', '7', '8', '9', '9', '10', '10', '10', '11'] 33 | 34 | 35 | ###error: 36 | 37 | 38 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_3/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 3750 mismatches. First mismatch occurred at time 20. 15 | Hint: Total mismatched samples is 3750 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 3750 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_4/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_4/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_4/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has no mismatches. 15 | Hint: Total mismatched samples is 0 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 0 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_5/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_5/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Scenario: 2, expected: q=aaaaaaaaaaaaaaa8, observed q=aaaaaaaaaaaaaaa0 6 | Failed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034400} 7 | Scenario: 3, expected: q=5555555555555000, observed q=aaaaaaaaaaaa8000 8 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 12297829382473023488} 9 | Scenario: 4, expected: q=2aaaaaaaaaa80000, observed q=d555555555400000 10 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 15372286728089894912} 11 | Scenario: 5, expected: q=0015555555555400, observed q=ffeaaaaaaaaaa000 12 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 18440739274206388224} 13 | Scenario: 6, expected: q=0000155555555554, observed q=ffffeaaaaaaaaaa0 14 | Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 18446720617461492384} 15 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 16 | Scenario: 8, expected: q=fffffffffffffffe, observed q=fffffffffffffffc 17 | Failed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551612} 18 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 19 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 20 | Scenario: 10, expected: q=ffffc00000000000, observed q=ffff800000000000 21 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 22 | Scenario: 10, expected: q=ffff800000000000, observed q=fffe000000000000 23 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446181123756130304} 24 | Scenario: 10, expected: q=ffff000000000000, observed q=fff8000000000000 25 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18444492273895866368} 26 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 27 | ['2', '3', '4', '5', '6', '8', '10', '10', '10'] 28 | 29 | 30 | ###error: 31 | 32 | 33 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_5/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 3026 mismatches. First mismatch occurred at time 80. 15 | Hint: Total mismatched samples is 3026 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 3026 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_6/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_6/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Scenario: 9, expected: q=c000000000000000, observed q=4000000000000000 13 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 4611686018427387904} 14 | Scenario: 9, expected: q=ffe0000000000000, observed q=0020000000000000 15 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 9007199254740992} 16 | Scenario: 10, expected: q=ffffc00000000000, observed q=0000400000000000 17 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 70368744177664} 18 | Scenario: 10, expected: q=ffff800000000000, observed q=0000800000000000 19 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 140737488355328} 20 | Scenario: 10, expected: q=ffff000000000000, observed q=0001000000000000 21 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 281474976710656} 22 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 23 | ['9', '9', '10', '10', '10'] 24 | 25 | 26 | ###error: 27 | 28 | 29 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_6/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 944 mismatches. First mismatch occurred at time 160. 15 | Hint: Total mismatched samples is 944 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 944 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_7/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_7/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Scenario: 9, expected: q=ffe0000000000000, observed q=00e0000000000000 14 | Failed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 63050394783186944} 15 | Scenario: 10, expected: q=ffffc00000000000, observed q=0001c00000000000 16 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 492581209243648} 17 | Scenario: 10, expected: q=ffff800000000000, observed q=0003800000000000 18 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 985162418487296} 19 | Scenario: 10, expected: q=ffff000000000000, observed q=0007000000000000 20 | Failed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 1970324836974592} 21 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 22 | ['9', '10', '10', '10'] 23 | 24 | 25 | ###error: 26 | 27 | 28 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_7/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 1208 mismatches. First mismatch occurred at time 1400. 15 | Hint: Total mismatched samples is 1208 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 1208 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_8/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_8/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Passed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 6148914691236515840} 7 | Passed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618083840} 8 | Passed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160320} 9 | Passed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059220} 10 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 11 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 12 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 13 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 14 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 15 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 16 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 17 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 18 | [] 19 | 20 | 21 | ###error: 22 | 23 | 24 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_8/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has no mismatches. 15 | Hint: Total mismatched samples is 0 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 0 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_9/GeneratedTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | shift18_tb.v:139: $finish called at 290000 (1ps) 13 | 14 | iverilog cmd 2 error: 15 | 16 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_9/GeneratedTB/run_info_py.txt: -------------------------------------------------------------------------------- 1 | python compilation passed! 2 | 3 | ###output: 4 | Passed; vector: {'check_en': True, 'scenario': '1', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034410} 5 | Passed; vector: {'check_en': True, 'scenario': '2', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 12297829382473034410, 'q': 12297829382473034408} 6 | Scenario: 3, expected: q=5555555555555000, observed q=aaaaaaaaaaaaa800 7 | Failed; vector: {'check_en': True, 'scenario': '3', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 1, 'data': 12297829382473034410, 'q': 12297829382473033728} 8 | Scenario: 4, expected: q=2aaaaaaaaaa80000, observed q=2aaaaaaaaaaa0000 9 | Failed; vector: {'check_en': True, 'scenario': '4', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 12297829382473034410, 'q': 3074457345618214912} 10 | Scenario: 5, expected: q=0015555555555400, observed q=0015555555555500 11 | Failed; vector: {'check_en': True, 'scenario': '5', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 12297829382473034410, 'q': 6004799503160576} 12 | Scenario: 6, expected: q=0000155555555554, observed q=0000155555555555 13 | Failed; vector: {'check_en': True, 'scenario': '6', 'clk': 1, 'load': 0, 'ena': 0, 'amount': 0, 'data': 12297829382473034410, 'q': 23456248059221} 14 | Passed; vector: {'check_en': True, 'scenario': '7', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 6148914691236517205, 'q': 6148914691236517205} 15 | Passed; vector: {'check_en': True, 'scenario': '8', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 18446744073709551615, 'q': 18446744073709551614} 16 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 2, 'data': 9223372036854775808, 'q': 13835058055282163712} 17 | Passed; vector: {'check_en': True, 'scenario': '9', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 3, 'data': 9223372036854775808, 'q': 18437736874454810624} 18 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446673704965373952} 19 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446603336221196288} 20 | Passed; vector: {'check_en': True, 'scenario': '10', 'clk': 1, 'load': 0, 'ena': 1, 'amount': 0, 'data': 9223372036854775808, 'q': 18446462598732840960} 21 | Passed; vector: {'check_en': True, 'scenario': '11', 'clk': 1, 'load': 1, 'ena': 0, 'amount': 0, 'data': 1311768467463790320, 'q': 1311768467463790320} 22 | ['3', '4', '5', '6'] 23 | 24 | 25 | ###error: 26 | 27 | 28 | -------------------------------------------------------------------------------- /demo/shift18/1_4_TBeval/eval2_GoldenTB_and_mutants/mutant_9/GoldenTB/run_info.txt: -------------------------------------------------------------------------------- 1 | iverilog simulation passed! 2 | 3 | iverilog cmd 1: 4 | ~/bin/bin/iverilog -g2012 -o run.vvp shift18_tb.v shift18.v 5 | iverilog cmd 1 output: 6 | 7 | iverilog cmd 1 error: 8 | 9 | iverilog cmd 2: 10 | ~/bin/bin/vvp run.vvp 11 | iverilog cmd 2 output: 12 | VCD info: dumpfile wave.vcd opened for output. 13 | shift18_tb.v:96: $finish called at 20206 (1ps) 14 | Hint: Output 'q' has 2922 mismatches. First mismatch occurred at time 60. 15 | Hint: Total mismatched samples is 2922 out of 4041 samples 16 | 17 | Simulation finished at 20206 ps 18 | Mismatches: 2922 in 4041 samples 19 | 20 | iverilog cmd 2 error: 21 | 22 | -------------------------------------------------------------------------------- /demo/shift18/code_comparison/new_checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | msb = current_q & 0x8000000000000000 # Extract the MSB 27 | self.q_reg = (current_q >> 1) | msb # Ensure arithmetic shift maintains MSB 28 | elif amount == 0b11: 29 | # Arithmetic shift right by 8 30 | msb = current_q & 0x8000000000000000 # Extract the MSB 31 | self.q_reg = (current_q >> 8) 32 | # Replicate MSB over shifted positions 33 | if msb: 34 | self.q_reg |= (0xFF << 56) 35 | 36 | def check(self, signal_vector): 37 | # Check expected and observed output values 38 | q_observed = signal_vector['q'] 39 | q_expected = self.q_reg 40 | 41 | if q_expected == q_observed: 42 | return True 43 | else: 44 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected:016x}, observed q={q_observed:016x}") 45 | return False -------------------------------------------------------------------------------- /demo/shift18/code_comparison/old_checker.py: -------------------------------------------------------------------------------- 1 | class GoldenDUT: 2 | def __init__(self): 3 | # Initialize internal state register 4 | self.q_reg = 0 5 | 6 | def load(self, signal_vector): 7 | # Load the input signals and update the internal state 8 | load = signal_vector['load'] 9 | ena = signal_vector['ena'] 10 | data = signal_vector['data'] 11 | amount = signal_vector['amount'] 12 | current_q = self.q_reg 13 | 14 | if load: 15 | # Load data into the shift register 16 | self.q_reg = data & 0xFFFFFFFFFFFFFFFF # Ensure 64-bit width 17 | elif ena: 18 | if amount == 0b00: 19 | # Shift left by 1 20 | self.q_reg = (current_q << 1) & 0xFFFFFFFFFFFFFFFF 21 | elif amount == 0b01: 22 | # Shift left by 8 23 | self.q_reg = (current_q << 8) & 0xFFFFFFFFFFFFFFFF 24 | elif amount == 0b10: 25 | # Arithmetic shift right by 1 26 | self.q_reg = (current_q >> 1) | ((current_q & 0x8000000000000000) >> 1) 27 | elif amount == 0b11: 28 | # Arithmetic shift right by 8 29 | self.q_reg = (current_q >> 8) | ((current_q & 0x8000000000000000) >> 8) 30 | 31 | def check(self, signal_vector): 32 | # Check expected and observed output values 33 | q_observed = signal_vector['q'] 34 | q_expected = self.q_reg 35 | 36 | if q_expected == q_observed: 37 | return True 38 | else: 39 | print(f"Scenario: {signal_vector['scenario']}, expected: q={q_expected}, observed q={q_observed}") 40 | return False -------------------------------------------------------------------------------- /demo/shift18/run_info.json: -------------------------------------------------------------------------------- 1 | { 2 | "task_id": "shift18", 3 | "task_number": 12, 4 | "time": 99.14, 5 | "prompt_tokens": 17132, 6 | "completion_tokens": 6782, 7 | "token_cost": 0.11065, 8 | "ERROR(incomplete)": true, 9 | "op_record": [ 10 | "gen", 11 | "syncheck", 12 | "funccheck", 13 | "eval" 14 | ], 15 | "reboot_times": 0, 16 | "max_iter": 10, 17 | "circuit_type": "SEQ", 18 | "checklist_worked": false, 19 | "scenario_num": 11, 20 | "Eval0_pass": true, 21 | "Eval0_iv_pass": true, 22 | "debug_iter_iv": 0, 23 | "iv_runing_time": 0.07, 24 | "Eval0_py_pass": true, 25 | "debug_iter_py": 0, 26 | "py_runing_time": 0.07, 27 | "TB_corrected": true, 28 | "TBcheck_oprecord": [ 29 | [ 30 | "discrim", 31 | "correct", 32 | "discrim" 33 | ] 34 | ], 35 | "rtl_num_newly_gen": 0, 36 | "Eval1_pass": true, 37 | "Eval2_pass": true, 38 | "Eval2_ratio": "10/10", 39 | "Eval2_failed_mutant_idxes": [] 40 | } -------------------------------------------------------------------------------- /demo/shift18/run_info_short.json: -------------------------------------------------------------------------------- 1 | { 2 | "task_id": "shift18", 3 | "eval_progress": "Eval2 - 10/10", 4 | "TB_corrected": true, 5 | "reboot_times": 0, 6 | "time": 99.14, 7 | "cost": 0.11065 8 | } -------------------------------------------------------------------------------- /demo/shift18/task_log.log: -------------------------------------------------------------------------------- 1 | 2024-08-31 18:50:34 | INFO | [shift18] [TBgen] stage_0 ends (2.04s used) 2 | 2024-08-31 18:50:37 | INFO | [shift18] [TBgen] stage_1 ends (2.76s used) 3 | 2024-08-31 18:50:44 | INFO | [shift18] [TBgen] stage_2 ends (7.26s used) 4 | 2024-08-31 18:50:51 | INFO | [shift18] [TBgen] stage_3 ends (7.04s used) 5 | 2024-08-31 18:51:06 | INFO | [shift18] [TBgen] stage_4 ends (15.11s used) 6 | 2024-08-31 18:51:06 | INFO | [shift18] [TBgen] stage_checklist ends (0.00s used) 7 | 2024-08-31 18:51:39 | INFO | [shift18] [TBgen] stage_4b ends (32.64s used) 8 | 2024-08-31 18:51:44 | INFO | [shift18] [TBgen] stage_5 ends (5.38s used) 9 | 2024-08-31 18:51:44 | INFO | [shift18] 10 | 2024-08-31 18:51:44 | INFO | [shift18] [TBsim] iverilog compilation : passed! 11 | 2024-08-31 18:51:44 | INFO | [shift18] [TBsim] python simulation : passed! 12 | 2024-08-31 18:51:44 | INFO | [shift18] [TBsim] TBsim finished : True! 13 | 2024-08-31 18:51:44 | INFO | [shift18] 14 | 2024-08-31 18:51:44 | INFO | [shift18] [TBcheck] [discriminator] Discriminating the testbench, NO.0 discrimination 15 | 2024-08-31 18:51:48 | NEGATIVE | [shift18] [TBcheck] [discriminator] TB_discriminating finished, TB failed, wrong scenarios: [ 9 10], scenario pass ratio: 9/11 16 | 2024-08-31 18:51:48 | INFO | [shift18] [TBcheck] [corrector] naive corrector mode begins 17 | 2024-08-31 18:52:03 | INFO | [shift18] [TBcheck] [corrector] naive corrector mode ends; conversation and codes saved 18 | 2024-08-31 18:52:03 | INFO | [shift18] [TBcheck] [discriminator] Discriminating the testbench, NO.1 discrimination 19 | 2024-08-31 18:52:06 | POSITIVE | [shift18] [TBcheck] [discriminator] TB_discriminating finished, TB passed, wrong scenarios: [], scenario pass ratio: 9/11 20 | 2024-08-31 18:52:06 | INFO | [shift18] [TBcheck] Testbench passed the funccheck after correction 21 | 2024-08-31 18:52:06 | INFO | [shift18] [TBcheck] self funccheck finished. Next Action: [pass] 22 | 2024-08-31 18:52:06 | INFO | [shift18] 23 | 2024-08-31 18:52:06 | INFO | [shift18] [TBeval] Eval 1: Golden RTL checking begins 24 | 2024-08-31 18:52:06 | POSITIVE | [shift18] [TBeval] Eval 1: Golden RTL checking passed! 25 | 2024-08-31 18:52:06 | INFO | [shift18] [TBeval] Eval 2: Golden TB checking on RTL mutants 26 | 2024-08-31 18:52:11 | SUCCESS | [shift18] [TBeval] Eval 2: Golden TB checking on RTL mutants perfectly passed! 27 | 2024-08-31 18:52:11 | INFO | [shift18] 28 | -------------------------------------------------------------------------------- /figs/DATE2024_logo_blue_flat.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/figs/DATE2024_logo_blue_flat.png -------------------------------------------------------------------------------- /figs/DATE2025_logo_blue_shadow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/figs/DATE2025_logo_blue_shadow.png -------------------------------------------------------------------------------- /main.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : This is the head file of the project 3 | Author : Ruidi Qiu (ruidi.qiu@tum.de) 4 | Time : 2023/11/28 11:19:59 5 | LastEdited : 2024/8/29 21:43:15 6 | """ 7 | 8 | import loader_saver as ls 9 | from config import Config 10 | import config 11 | import LLM_call as gpt 12 | import autoline as al 13 | import iverilog_call as iv 14 | import getopt 15 | import sys 16 | from config import CFG_CUS_PATH 17 | 18 | def main(custom_cfg_path: str = CFG_CUS_PATH): 19 | 20 | # my_config = cfg.load_config(custom_cfg_path) 21 | # my_config = ls.add_save_root_to(my_config) 22 | my_config = Config(custom_cfg_path) 23 | ls.add_save_root_to(my_config) 24 | logger = ls.AutoLogger() # initialize the autologger 25 | logger.info("all configurations are loaded, starting the main process...") 26 | match my_config.run.mode: 27 | case "chatgpt": 28 | gpt.run_like_a_chatgpt() 29 | case "iverilog": 30 | iv.run_iverilog() 31 | case "autoline": 32 | al.run_autoline() 33 | # case "dataset_manager": 34 | # pass # TODO 35 | case _: 36 | raise ValueError("Invalid run mode: " + my_config.run.mode) 37 | print("Done!\n\n") 38 | 39 | if __name__ == "__main__": 40 | # if no command, run the main function main() 41 | # if -h/--help, print the help message 42 | # if -c/--config + str, first get the custom config path, then run the main function 43 | 44 | 45 | try: 46 | opts, args = getopt.getopt(sys.argv[1:], "hc:", ["help", "config="]) 47 | except getopt.GetoptError as err: 48 | print(err) 49 | sys.exit(2) 50 | if len(opts) == 1: 51 | for opt, arg in opts: 52 | if opt in ("-h", "--help"): 53 | print("Usage: python main.py [-h] [-c ]") 54 | sys.exit(0) 55 | elif opt in ("-c", "--config"): 56 | config_path = config.get_cfg_path_from_alias(arg) 57 | main(config_path) 58 | sys.exit(0) 59 | elif len(opts) > 1: 60 | print("opts are more than 1; Usage: python main.py [-h] [-c ]") 61 | sys.exit(2) 62 | else: 63 | main() 64 | sys.exit(0) -------------------------------------------------------------------------------- /prompt_scripts/__init__.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : description 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/3/23 11:30:00 5 | LastEdited : 2024/7/24 11:43:13 6 | """ 7 | 8 | from .base_script import BaseScript, BaseScriptStage 9 | from .script_pychecker import WF_pychecker 10 | from .script_directgen import WF_directgen 11 | 12 | SCRIPTS_SELECTER = { 13 | "pychecker": WF_pychecker, 14 | "directgen": WF_directgen 15 | } 16 | 17 | def get_script(script_name:str) -> BaseScript: 18 | if script_name in SCRIPTS_SELECTER: 19 | return SCRIPTS_SELECTER[script_name] 20 | else: 21 | raise ValueError(f"script name {script_name} is not supported") -------------------------------------------------------------------------------- /prompt_scripts/legacy/__pycache__/script_RTLchecker0306.cpython-312.pyc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/AutoBench/CorrectBench/ef4627900c88e9df093740913a8594e2342f2358/prompt_scripts/legacy/__pycache__/script_RTLchecker0306.cpython-312.pyc -------------------------------------------------------------------------------- /prompt_scripts/public_stages.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : the public stages that may be used by other scripts 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/3/30 23:58:28 5 | LastEdited : 2024/3/31 00:00:30 6 | """ 7 | 8 | from .base_script import BaseScriptStage 9 | 10 | # not implemented yet -------------------------------------------------------------------------------- /prompt_scripts/script_directgen.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : "directgen" script for prompt scripts 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/3/30 17:40:38 5 | LastEdited : 2024/5/1 17:44:05 6 | """ 7 | 8 | from .base_script import BaseScript, BaseScriptStage, TESTBENCH_TEMPLATE 9 | 10 | class WF_directgen(BaseScript): 11 | """ 12 | stages: stage1 13 | """ 14 | def __init__(self, prob_data:dict, task_dir:str, config:object): 15 | super().__init__(prob_data, task_dir, config) 16 | 17 | def make_and_run_stages(self): 18 | # stage1 19 | stage1 = Stage1(self.prob_data, **self.gptkwargs) 20 | self.stage_operation(stage1) 21 | 22 | def make_and_run_reboot_stages(self, debug_dir): 23 | # stage1 24 | stage1 = Stage1(self.prob_data, **self.gptkwargs) 25 | self.stage_operation(stage1, debug_dir, reboot_en=True) 26 | 27 | STAGE1_TXT1 = """ 28 | Your task is to write a verilog testbench for an verilog RTL module code (we call it as "DUT", device under test). The infomation we have is the problem description that guides student to write the RTL code (DUT) and the header of the "DUT". 29 | """ 30 | STAGE1_TXT2 = """ 31 | very very IMPORTANT: If all the test cases pass, the testbench should display "all test cases passed". If any one of the test cases fails, testbench should not display "all test caess passed". DO NOT generate any .vcd file. 32 | please don't reply other words except the testbench codes. 33 | """ 34 | class Stage1(BaseScriptStage): 35 | def __init__(self, prob_data, **gptkwargs) -> None: 36 | super().__init__("stage_1", **gptkwargs) 37 | self.prob_data = prob_data 38 | self.txt1 = STAGE1_TXT1 39 | self.txt2 = STAGE1_TXT2 40 | self.TB_code_out = "" 41 | 42 | def make_prompt(self): 43 | self.prompt = "" 44 | self.add_prompt_line(self.txt1) 45 | # testbench template 46 | self.add_prompt_line("your testbench template is:") 47 | self.add_prompt_line(TESTBENCH_TEMPLATE) 48 | # problem description 49 | self.add_prompt_line("problem description:") 50 | self.add_prompt_line(self.prob_data["description"]) 51 | # DUT header 52 | self.add_prompt_line("DUT header:") 53 | self.add_prompt_line(self.prob_data["header"]) 54 | # end 55 | self.add_prompt_line(self.txt2) 56 | 57 | def postprocessing(self): 58 | # verilog codes 59 | self.response = self.extract_code(self.response, "verilog")[-1] 60 | self.TB_code_out = self.response -------------------------------------------------------------------------------- /python_call.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : this is used in pychecker workflow 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2024/3/31 14:05:50 5 | LastEdited : 2024/8/11 17:32:07 6 | """ 7 | 8 | import os 9 | import sys 10 | from utils.utils import run_in_dir 11 | from utils.subproc import subproc_call 12 | 13 | PYPATH = "ipynb_demo/error_analysis/correct_test_80wrong_discrim_20240809_225259/1365/checker.py" 14 | 15 | def python_call(pypath, silent = False, timeout = 120): 16 | """ 17 | #### input: 18 | - pypath: the path of the python file 19 | - silent: whether to print 20 | 21 | #### output: 22 | return a list of 3 elements: 23 | - [0] (pass or not): bool, whether the simulation is successful 24 | - [1] (run_info): dict, the iverilog compiling result {"out": out_reg, "err": err_reg, "haserror": error_exist} 25 | - [2]/[-1] (error_msg): str, the error message if there is any error; This is for convenience, the error message is also included in [2] or [4] 26 | 27 | #### functionality: 28 | given the path of python file, run it in the local dir. 29 | """ 30 | def s_print(*args, **kwargs): 31 | if not silent: 32 | print(*args, **kwargs) 33 | dir = os.path.dirname(pypath) 34 | filename = os.path.basename(pypath) 35 | cmd = "python3 %s"%(filename) 36 | with run_in_dir(dir): 37 | run_info = subproc_call(cmd, timeout) # {"out": out_reg, "err": err_reg, "haserror": error_exist} 38 | if run_info["haserror"]: 39 | s_print("python compiling failed") 40 | return [False, run_info, run_info["err"]] 41 | else: 42 | s_print("python compiling passed") 43 | return [True, run_info, ""] 44 | 45 | def save_py_runinfo(py_run_result, dir): 46 | """ 47 | save the run info of iverilog to dir 48 | """ 49 | run_info_path = os.path.join(dir, "run_info_py.txt") 50 | lines = "" 51 | if py_run_result[0]: 52 | lines += "python compilation passed!\n\n" 53 | else: 54 | lines += "python compilation failed!\n\n" 55 | # output and error of cmd: 56 | lines += "###output:\n%s\n\n" % (py_run_result[1]["out"]) 57 | lines += "###error:\n%s\n\n" % (py_run_result[1]["err"]) 58 | # save to file: 59 | with open(run_info_path, "w") as f: 60 | f.write(lines) 61 | 62 | def python_call_and_save(pypath, silent = False, timeout = 120): 63 | """ 64 | run the python file and save the run info 65 | """ 66 | py_run_result = python_call(pypath, silent, timeout) 67 | save_py_runinfo(py_run_result, os.path.dirname(pypath)) 68 | return py_run_result 69 | 70 | if __name__ == "__main__": 71 | python_call_and_save(PYPATH, silent = False) -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | anthropic==0.34.2 2 | loguru==0.7.2 3 | matplotlib==3.9.2 4 | numpy==2.1.1 5 | openai==1.46.1 6 | PyYAML==6.0.2 7 | Requests==2.32.3 8 | tiktoken==0.7.0 9 | -------------------------------------------------------------------------------- /utils/json_utils.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : This file is used to handle json files 3 | Author : Ruidi Qiu (ruidi.qiu@tum.de) 4 | Time : 2023/11/19 21:49:11 5 | LastEdited : 6 | """ 7 | 8 | import json 9 | 10 | PROMPT_JSON = "preliminary_EXP/7420/prompt.json" 11 | OUTPUT_TXT = "generated_prompt.txt" 12 | 13 | """ 14 | prompt.json template: 15 | { 16 | "description" : "The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates. Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs.", 17 | "headmodule" : "module top_module (\ninput p1a, p1b, p1c, p1d,\noutput p1y,\ninput p2a, p2b, p2c, p2d,\noutput p2y );\nendmodule", 18 | "tb_property" : {"composition" : "this module is composed of 2 4-input NAND gates", "test case 1" : "NAND gate will output 1 if all inputs are 0, otherwise it will output 0"}, 19 | "rules" : ["Attention! you should print a message after each test case. The message should contain 'the explanation of your test case' and 'error source'", "Attention! Your test cases should be as exhaustive as possible.", "your response should only contain the code"] 20 | } 21 | """ 22 | def json_read(filename): 23 | with open(filename, 'r') as f: 24 | data = json.load(f) 25 | return data 26 | 27 | def txt_write(filename, content): 28 | with open(filename, 'w') as f: 29 | f.write(content) 30 | 31 | def prompt_gen_from_jsonprompt(json_data): 32 | prompt_header = "You are the strongest AI agent I have ever met. You can perfect handle the job I give you. please generate a verilog testbench to test the verilog code of the design under test (DUT).\n" 33 | prompt_description = "The description for the DUT is: '%s'\n" % (json_data["description"]) 34 | prompt_headmodule = "The input and output interface of this verilog code is: \n%s\n" % (json_data["headmodule"]) 35 | prompt_rules = "The rules for this task are:\n" 36 | for rule in json_data["rules"]: 37 | prompt_rules += " %s\n" % (rule) 38 | prompt_property = "to help you better generate the testbench for the DUT, we will give you some tips that you should consider when generating the testbench.\n" 39 | prompt_property += "The composition of the DUT is '%s'\n" % (json_data["tb_property"]["composition"]) 40 | for key in json_data["tb_property"].keys(): 41 | if key != "composition": 42 | prompt_property += " %s: %s\n" % (key, json_data["tb_property"][key]) 43 | prompt = prompt_header + prompt_description + prompt_headmodule + prompt_rules + prompt_property 44 | return prompt 45 | 46 | def main(): 47 | json_file = PROMPT_JSON 48 | output_txt = OUTPUT_TXT 49 | json_data = json_read(json_file) 50 | prompt = prompt_gen_from_jsonprompt(json_data) 51 | txt_write(output_txt, prompt) 52 | 53 | if __name__ == "__main__": 54 | main() -------------------------------------------------------------------------------- /utils/subproc.py: -------------------------------------------------------------------------------- 1 | """ 2 | Description : This file is related to auto subprocess running 3 | Author : Ruidi Qiu (r.qiu@tum.de) 4 | Time : 2023/12/11 14:06:27 5 | LastEdited : 2024/4/28 13:26:18 6 | """ 7 | 8 | import subprocess as sp 9 | 10 | def subproc_call(cmd, timeout=120): 11 | """ 12 | run a cmd in shell and return the output and error 13 | #### input: 14 | - cmd: str 15 | - timeout: int, seconds 16 | #### output: 17 | - {"out": out_reg, "err": err_reg, "haserror": error_exist} 18 | - out_reg: str, output of cmd 19 | - err_reg: str, error of cmd 20 | - error_exist: int, 0 if no error, 1 if error 21 | 22 | cmd can at most run 2 minutes and if it exceeds, will return {"out": "timeout", "err": "program is timeout", "haserror": 1} 23 | """ 24 | # p = sp.Popen(cmd, shell=True, stdout=sp.PIPE, stderr=sp.PIPE) 25 | # out, err = p.communicate() 26 | # error_exist = p.returncode 27 | # out_reg = out.decode("utf-8") 28 | # err_reg = err.decode("utf-8") 29 | timeouterror = "program is timeout (time > %ds). please check your code. Hints: there might be some infinite loop, please check all the loops in your programm. If it is a verilog code, please check if there is a $finish in the code."%(timeout) 30 | p = sp.Popen(cmd, shell=True, stdout=sp.PIPE, stderr=sp.PIPE) 31 | out_reg = "" 32 | err_reg = "" 33 | error_exist = 0 34 | try: 35 | out, err = p.communicate(timeout=timeout) 36 | out_reg = out.decode("utf-8") 37 | err_reg = err.decode("utf-8") 38 | error_exist = p.returncode 39 | except sp.TimeoutExpired: 40 | p.kill() 41 | out_reg = "" 42 | err_reg = timeouterror 43 | error_exist = 1 44 | return {"out": out_reg, "err": err_reg, "haserror": error_exist} 45 | 46 | --------------------------------------------------------------------------------