├── .gitignore ├── Config ├── Circuits │ ├── CSVA.yaml │ ├── CVA.yaml │ ├── LNA.yaml │ ├── Mixer.yaml │ ├── PA.yaml │ ├── Receiver.yaml │ ├── TSVA.yaml │ ├── Transmitter.yaml │ └── VCO.yaml ├── sim_config.yml ├── train_config.yaml └── visual_config.yaml ├── Dataset ├── CSVA │ └── CSVA.csv ├── CVA │ └── CVA.csv ├── LNA │ └── LNA.csv ├── Mixer │ └── Mixer.csv ├── PA │ └── PA.csv ├── Receiver │ └── Receiver.csv ├── TSVA │ └── TSVA.csv ├── Transmitter │ └── Transmitter.csv └── VCO │ └── VCO.csv ├── Images ├── TSVA.png └── Transmitter.png ├── LICENSE ├── Model ├── model_evaluator.py ├── model_wrapper.py └── models.py ├── Pipeline ├── dataset.py ├── modules.py └── pipeline.py ├── README.md ├── Simulation ├── Model │ └── 45n270AModels.sp ├── Netlists │ ├── CSVA │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── CVA │ │ ├── amap │ │ │ ├── Cascode.inst │ │ │ ├── Cascode.net │ │ │ ├── Cascode.port │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ ├── analogLib_res_spectre.inst │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ ├── designData.json │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── LNA │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── Mixer │ │ ├── VoltageSwing │ │ │ ├── amap │ │ │ │ ├── Gilbert_Cell.inst │ │ │ │ ├── Gilbert_Cell.net │ │ │ │ ├── Mixer_testbench.inst │ │ │ │ ├── Mixer_testbench.net │ │ │ │ ├── Mixer_testbench.port │ │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ │ ├── __dspf_information__. │ │ │ │ ├── __multiplefiles_amap_format__ │ │ │ │ ├── __new_amap_format__ │ │ │ │ ├── __nmp_amap_format__ │ │ │ │ ├── __simulator_information__ │ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ │ ├── analogLib_idc_spectre.inst │ │ │ │ ├── analogLib_port_spectre.inst │ │ │ │ ├── analogLib_res_spectre.inst │ │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ │ ├── designData.json │ │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ │ ├── top_level_map.inst │ │ │ │ ├── top_level_map.net │ │ │ │ └── top_level_map.port │ │ │ ├── netlist │ │ │ ├── netlistFooter │ │ │ └── netlistHeader │ │ ├── amap │ │ │ ├── Gilbert_Cell.inst │ │ │ ├── Gilbert_Cell.net │ │ │ ├── Mixer_testbench.inst │ │ │ ├── Mixer_testbench.net │ │ │ ├── Mixer_testbench.port │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ ├── analogLib_idc_spectre.inst │ │ │ ├── analogLib_port_spectre.inst │ │ │ ├── analogLib_res_spectre.inst │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ ├── designData.json │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── PA │ │ ├── amap │ │ │ ├── Diff_twostage_PA.inst │ │ │ ├── Diff_twostage_PA.net │ │ │ ├── NCSU_Analog_Parts_cap_spectre.inst │ │ │ ├── NCSU_Analog_Parts_ind_spectre.inst │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── NCSU_Analog_Parts_vdc_spectre.inst │ │ │ ├── PA_testbench.inst │ │ │ ├── PA_testbench.net │ │ │ ├── PA_testbench.port │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── analogLib_indq_spectre.inst │ │ │ ├── analogLib_mind_spectre.inst │ │ │ ├── analogLib_port_spectre.inst │ │ │ ├── analogLib_res_spectre.inst │ │ │ ├── designData.json │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── Receiver │ │ ├── Individual │ │ │ ├── amap │ │ │ │ ├── Cascode.inst │ │ │ │ ├── Cascode.net │ │ │ │ ├── Gilbert_Cell.inst │ │ │ │ ├── Gilbert_Cell.net │ │ │ │ ├── LNA.inst │ │ │ │ ├── LNA.net │ │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ │ ├── Receiver_System_IndividualMetrics.inst │ │ │ │ ├── Receiver_System_IndividualMetrics.net │ │ │ │ ├── Receiver_System_IndividualMetrics.port │ │ │ │ ├── __dspf_information__. │ │ │ │ ├── __multiplefiles_amap_format__ │ │ │ │ ├── __new_amap_format__ │ │ │ │ ├── __nmp_amap_format__ │ │ │ │ ├── __simulator_information__ │ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ │ ├── analogLib_idc_spectre.inst │ │ │ │ ├── analogLib_ind_spectre.inst │ │ │ │ ├── analogLib_port_spectre.inst │ │ │ │ ├── analogLib_res_spectre.inst │ │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ │ ├── designData.json │ │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ │ ├── top_level_map.inst │ │ │ │ ├── top_level_map.net │ │ │ │ └── top_level_map.port │ │ │ ├── netlist │ │ │ ├── netlistFooter │ │ │ └── netlistHeader │ │ ├── amap │ │ │ ├── Cascode.inst │ │ │ ├── Cascode.net │ │ │ ├── Gilbert_Cell.inst │ │ │ ├── Gilbert_Cell.net │ │ │ ├── LNA.inst │ │ │ ├── LNA.net │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── Receiver_System_CombinationPerformance.inst │ │ │ ├── Receiver_System_CombinationPerformance.net │ │ │ ├── Receiver_System_CombinationPerformance.port │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ ├── analogLib_idc_spectre.inst │ │ │ ├── analogLib_ind_spectre.inst │ │ │ ├── analogLib_port_spectre.inst │ │ │ ├── analogLib_res_spectre.inst │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ ├── designData.json │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── TSVA │ │ ├── amap │ │ │ ├── NCSU_Analog_Parts_cap_spectre.inst │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── NCSU_Analog_Parts_pmos4_spectre.inst │ │ │ ├── NCSU_Analog_Parts_vdc_spectre.inst │ │ │ ├── TwoStage.inst │ │ │ ├── TwoStage.net │ │ │ ├── TwoStage.port │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── designData.json │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ ├── Transmitter │ │ ├── amap │ │ │ ├── Cross_coupled_VCO.inst │ │ │ ├── Cross_coupled_VCO.net │ │ │ ├── Cross_coupled_VCO_schematic.inst │ │ │ ├── Cross_coupled_VCO_schematic.net │ │ │ ├── Diff_twostage_PA.inst │ │ │ ├── Diff_twostage_PA.net │ │ │ ├── Diff_twostage_PA_schematic.inst │ │ │ ├── Diff_twostage_PA_schematic.net │ │ │ ├── NCSU_Analog_Parts_cap_spectre.inst │ │ │ ├── NCSU_Analog_Parts_idc_spectre.inst │ │ │ ├── NCSU_Analog_Parts_ind_spectre.inst │ │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ │ ├── NCSU_Analog_Parts_res_spectre.inst │ │ │ ├── NCSU_Analog_Parts_vdc_spectre.inst │ │ │ ├── VCO_PA.inst │ │ │ ├── VCO_PA.net │ │ │ ├── VCO_PA.port │ │ │ ├── VCO_PA_schematic.inst │ │ │ ├── VCO_PA_schematic.net │ │ │ ├── VCO_PA_schematic.port │ │ │ ├── __dspf_information__. │ │ │ ├── __multiplefiles_amap_format__ │ │ │ ├── __new_amap_format__ │ │ │ ├── __nmp_amap_format__ │ │ │ ├── __simulator_information__ │ │ │ ├── analogLib_cap_spectre.inst │ │ │ ├── analogLib_ind_spectre.inst │ │ │ ├── analogLib_indq_spectre.inst │ │ │ ├── analogLib_mind_spectre.inst │ │ │ ├── analogLib_port_spectre.inst │ │ │ ├── analogLib_res_spectre.inst │ │ │ ├── analogLib_vdc_spectre.inst │ │ │ ├── designData.json │ │ │ ├── rfLib_balun_veriloga.inst │ │ │ ├── top_level_map.inst │ │ │ ├── top_level_map.net │ │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader │ └── VCO │ │ ├── amap │ │ ├── NCSU_Analog_Parts_nmos4_spectre.inst │ │ ├── VCO.inst │ │ ├── VCO.net │ │ ├── VCO.port │ │ ├── __dspf_information__. │ │ ├── __multiplefiles_amap_format__ │ │ ├── __new_amap_format__ │ │ ├── __nmp_amap_format__ │ │ ├── __simulator_information__ │ │ ├── analogLib_cap_spectre.inst │ │ ├── analogLib_idc_spectre.inst │ │ ├── analogLib_ind_spectre.inst │ │ ├── analogLib_res_spectre.inst │ │ ├── analogLib_vdc_spectre.inst │ │ ├── designData.json │ │ ├── top_level_map.inst │ │ ├── top_level_map.net │ │ └── top_level_map.port │ │ ├── netlist │ │ ├── netlistFooter │ │ └── netlistHeader ├── Ocean │ ├── CSVA │ │ └── oceanScript.ocn │ ├── CVA │ │ └── oceanScript.ocn │ ├── LNA │ │ └── oceanScript.ocn │ ├── Mixer │ │ ├── oceanScript.ocn │ │ └── oceanScriptVoltageSwing.ocn │ ├── PA │ │ └── oceanScript.ocn │ ├── Receiver │ │ ├── oceanScript.ocn │ │ └── oceanScriptIndividual.ocn │ ├── TSVA │ │ └── oceanScript.ocn │ ├── Transmitter │ │ └── oceanScript.ocn │ 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