├── README.md ├── _images ├── 1.png ├── 10.png ├── 11.jpg ├── 11.png ├── 12.png ├── 2.png ├── 3.png ├── 4.png ├── 5.png ├── 6.png ├── 7.png ├── 8.png ├── 9.png ├── branchcode.png ├── memcode.png ├── regfile.png ├── riscv-encoding.png ├── riscvisa.png └── rv32isingle.png ├── five_pipeline_cpu ├── design │ ├── add_4.v │ ├── add_pc.v │ ├── alu.v │ ├── controller.v │ ├── cpu.v │ ├── data_mem.v │ ├── ex_me.v │ ├── forward_unit.v │ ├── hazard_detection_unit.v │ ├── id.v │ ├── id_ex.v │ ├── if_id.v │ ├── imm.v │ ├── instruction_mem.v │ ├── me_wb.v │ ├── mux_2.v │ ├── mux_3.v │ ├── next_pc.v │ ├── pc.v │ └── reg_file.v └── sim │ ├── cpu_tb.v │ ├── main.c │ ├── main.s │ └── script.py └── single_cycle_cpu ├── design ├── alu.v ├── controller.v ├── cpu.v ├── data_mem.v ├── id.v ├── imm.v ├── instruction_mem.v ├── mux_2.v ├── mux_3.v ├── next_pc.v ├── pc.v └── reg_file.v └── sim └── cpu_tb.v /README.md: -------------------------------------------------------------------------------- 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