├── Bluespec_for_High_Level_HW_Design.pdf ├── Historical └── Bluespec_Offer_to_Donate_BSV_to_IEEE_P1800_SystemVerilog.pdf ├── LICENSE ├── Language_Spec ├── Bluespec_Classic.pdf ├── bsv-reference-guide.pdf └── bsv-user-guide.pdf ├── README.md ├── Tutorials ├── BSV_Training │ ├── Build │ │ └── Makefile │ ├── Example_Programs │ │ ├── Common │ │ │ ├── C_import_decls.bsv │ │ │ ├── C_imports.c │ │ │ ├── C_imports.h │ │ │ ├── Fabric.bsv │ │ │ ├── Memory_Model.bsv │ │ │ ├── Reorder_Buffer.bsv │ │ │ ├── Req_Rsp.bsv │ │ │ └── Utils.bsv │ │ ├── Eg02_HelloWorld.pdf │ │ ├── Eg02a_HelloWorld │ │ │ └── src_BSV │ │ │ │ └── Testbench.bsv │ │ ├── Eg02b_HelloWorld │ │ │ └── src_BSV │ │ │ │ ├── DeepThought.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg02c_HelloWorld │ │ │ ├── Waves.tiff │ │ │ ├── dump.vcd │ │ │ └── src_BSV │ │ │ │ ├── DeepThought.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg03_Bubblesort.pdf │ │ ├── Eg03a_Bubblesort │ │ │ ├── Waves_screenshot.tiff │ │ │ ├── dump.vcd │ │ │ └── src_BSV │ │ │ │ ├── Bubblesort.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg03b_Bubblesort │ │ │ ├── Waves_screenshot.tiff │ │ │ ├── dump.vcd │ │ │ ├── gtkwave.sav │ │ │ └── src_BSV │ │ │ │ ├── Bubblesort.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg03c_Bubblesort │ │ │ └── src_BSV │ │ │ │ ├── Bubblesort.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg03d_Bubblesort │ │ │ └── src_BSV │ │ │ │ ├── Bubblesort.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg03e_Bubblesort │ │ │ └── src_BSV │ │ │ │ ├── Bubblesort.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg04_MicroArchs.pdf │ │ ├── Eg04a_MicroArchs │ │ │ ├── dump.vcd │ │ │ └── src_BSV │ │ │ │ ├── Shifter.bsv │ │ │ │ ├── Shifter_IFC.bsv │ │ │ │ ├── Shifter_iterative.bsv │ │ │ │ ├── Shifter_pipe_elastic.bsv │ │ │ │ ├── Shifter_pipe_rigid.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg04b_MicroArchs │ │ │ └── src_BSV │ │ │ │ ├── Shifter.bsv │ │ │ │ ├── Shifter_IFC.bsv │ │ │ │ ├── Shifter_iterative.bsv │ │ │ │ ├── Shifter_pipe_elastic.bsv │ │ │ │ ├── Shifter_pipe_rigid.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg05_CRegs_Greater_Concurrency.pdf │ │ ├── Eg05a_CRegs_Greater_Concurrency │ │ │ ├── Waves_CReg.tiff │ │ │ ├── Waves_Reg.tiff │ │ │ ├── dump_CReg.vcd │ │ │ ├── dump_Reg.vcd │ │ │ └── src_BSV │ │ │ │ ├── Counter2.bsv │ │ │ │ ├── Counter2_CReg.bsv │ │ │ │ ├── Counter2_IFC.bsv │ │ │ │ ├── Counter2_Reg.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg05b_CRegs_Greater_Concurrency │ │ │ ├── Waves_CReg.tiff │ │ │ ├── Waves_Reg.tiff │ │ │ ├── dump_CReg.vcd │ │ │ ├── dump_Reg.vcd │ │ │ └── src_BSV │ │ │ │ ├── MyFIFOF.bsv │ │ │ │ ├── MyFIFOF_CReg.bsv │ │ │ │ ├── MyFIFOF_Reg.bsv │ │ │ │ ├── Shifter.bsv │ │ │ │ ├── Shifter_IFC.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg06_Mergesort.pdf │ │ ├── Eg06a_Mergesort │ │ │ ├── objdump │ │ │ └── src_BSV │ │ │ │ ├── Mergesort.bsv │ │ │ │ ├── Sys_Configs.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg06b_Mergesort │ │ │ ├── objdump │ │ │ └── src_BSV │ │ │ │ ├── CPU.bsv │ │ │ │ ├── Mergesort.bsv │ │ │ │ ├── Sys_Configs.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg06c_Mergesort │ │ │ ├── objdump │ │ │ └── src_BSV │ │ │ │ ├── CPU.bsv │ │ │ │ ├── Mergesort.bsv │ │ │ │ ├── Sys_Configs.bsv │ │ │ │ └── Testbench.bsv │ │ ├── Eg09_AXI4_Stream.pdf │ │ └── Eg09a_AXI4_Stream │ │ │ ├── Waves_screenshot.tiff │ │ │ └── src_BSV │ │ │ ├── AXI4_Stream.bsv │ │ │ └── Testbench.bsv │ ├── README.md │ ├── Reference │ │ ├── Lec01_Intro.pdf │ │ ├── Lec02_Basic_Syntax.pdf │ │ ├── Lec03_Rule_Semantics.pdf │ │ ├── Lec04_CRegs.pdf │ │ ├── Lec05_Interfaces_TLM.pdf │ │ ├── Lec06_StmtFSM.pdf │ │ ├── Lec07_Types.pdf │ │ ├── Lec08_Typeclasses.pdf │ │ ├── Lec09_BSV_to_Verilog.pdf │ │ ├── Lec10_Interop_RTL.pdf │ │ ├── Lec11_Interop_C.pdf │ │ ├── Lec12_Multiple_Clock_Domains.pdf │ │ ├── Lec13_RWires.pdf │ │ └── README.txt │ └── START_HERE.pdf ├── BSV_by_Example_Book │ ├── bsv_by_example.pdf │ └── bsv_by_example_appendix.tar.gz ├── Bluespec_Classic_Training │ ├── Examples │ │ ├── C_programs_RV32 │ │ │ ├── Makefile │ │ │ ├── README │ │ │ ├── hello │ │ │ │ ├── Makefile │ │ │ │ ├── hello │ │ │ │ ├── hello.c │ │ │ │ ├── hello.map │ │ │ │ ├── hello.text │ │ │ │ └── hello_Mem.hex │ │ │ ├── lib │ │ │ │ ├── bare.lds │ │ │ │ ├── bare.specs │ │ │ │ ├── lib_cc.c │ │ │ │ ├── ns16550.c │ │ │ │ ├── ns16550.h │ │ │ │ ├── ns16550.o │ │ │ │ ├── ns16550.o.text │ │ │ │ ├── riscv_counters.c │ │ │ │ ├── riscv_counters.h │ │ │ │ ├── riscv_counters.o │ │ │ │ ├── riscv_counters.o.text │ │ │ │ ├── startup.S │ │ │ │ ├── startup.o │ │ │ │ ├── startup.o.text │ │ │ │ ├── syscalls.c │ │ │ │ ├── syscalls.o │ │ │ │ └── syscalls.o.text │ │ │ └── mergesort │ │ │ │ ├── mergesort │ │ │ │ ├── mergesort.c │ │ │ │ ├── mergesort.map │ │ │ │ ├── mergesort.text │ │ │ │ └── mergesort_Mem.hex │ │ ├── Eg02_HelloWorld.pdf │ │ ├── Eg02a_HelloWorld │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ └── Top.bs │ │ ├── Eg02b_HelloWorld │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── DeepThought.bs │ │ │ │ └── Top.bs │ │ ├── Eg02c_HelloWorld │ │ │ ├── Makefile │ │ │ ├── Waves.tiff │ │ │ └── src │ │ │ │ ├── DeepThought.bs │ │ │ │ └── Top.bs │ │ ├── Eg03_Bubblesort.pdf │ │ ├── Eg03a_Bubblesort │ │ │ ├── Makefile │ │ │ ├── Waves_screenshot.tiff │ │ │ └── src │ │ │ │ ├── Bubblesort.bs │ │ │ │ └── Top.bs │ │ ├── Eg03b_Bubblesort │ │ │ ├── Makefile │ │ │ ├── Waves_screenshot.tiff │ │ │ └── src │ │ │ │ ├── Bubblesort.bs │ │ │ │ └── Top.bs │ │ ├── Eg03c_Bubblesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Bubblesort.bs │ │ │ │ └── Top.bs │ │ ├── Eg03d_Bubblesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Bubblesort.bs │ │ │ │ └── Top.bs │ │ ├── Eg03e_Bubblesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Bubblesort.bs │ │ │ │ └── Top.bs │ │ ├── Eg06_Mergesort.pdf │ │ ├── Eg06a_Mergesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Fabric_Defs.bs │ │ │ │ ├── Merge_Engine.bs │ │ │ │ ├── Mergesort.bs │ │ │ │ ├── SoC_Map.bs │ │ │ │ ├── Test_Driver.bs │ │ │ │ └── Top.bs │ │ ├── Eg06b_Mergesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Fabric_Defs.bs │ │ │ │ ├── Merge_Engine.bs │ │ │ │ ├── Mergesort.bs │ │ │ │ ├── SoC_Fabric.bs │ │ │ │ ├── SoC_Map.bs │ │ │ │ ├── Test_Driver.bs │ │ │ │ └── Top.bs │ │ ├── Eg06c_Mergesort │ │ │ ├── Makefile │ │ │ └── src │ │ │ │ ├── Merge_Engine.bs │ │ │ │ ├── Mergesort.bs │ │ │ │ ├── SoC_Fabric.bs │ │ │ │ ├── SoC_Map.bs │ │ │ │ └── Top.bs │ │ └── Resources │ │ │ ├── Adapters_Req_Rsp_AXI4.bs │ │ │ ├── CReg_Classic.bsv │ │ │ ├── Fabric_Req_Rsp.bs │ │ │ ├── Gen_Mem_Hex │ │ │ ├── Descending_Mem.hex │ │ │ ├── Makefile │ │ │ └── gen_mem_hex.c │ │ │ ├── Include_Makefile.mk │ │ │ ├── Memory_Model.bs │ │ │ ├── Req_Rsp.bs │ │ │ ├── Utils.bs │ │ │ └── elf_to_hex │ │ │ ├── Makefile │ │ │ ├── README.txt │ │ │ └── elf_to_hex.c │ ├── README.md │ ├── Reference │ │ ├── Lec03_Rule_Semantics.pdf │ │ ├── Lec04_CRegs.pdf │ │ ├── Lec09_BSV_to_Verilog.pdf │ │ ├── Lec10_Interop_RTL.pdf │ │ ├── Lec11_Interop_C.pdf │ │ └── Lec12_Multiple_Clock_Domains.pdf │ └── START_HERE.pdf └── Modeling_Memory │ ├── EG_Function │ ├── Gen_ROM_Function │ │ ├── Gen_ROM_Function.c │ │ └── Makefile │ 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