├── Libraries ├── GenC │ ├── .gitignore │ ├── Makefile │ ├── GenCRepr │ │ ├── Makefile │ │ └── State.bs │ ├── GenCMsg │ │ ├── Makefile │ │ └── msgclient.py │ └── build_ffi.py ├── AMBA_TLM2 │ ├── AHB │ │ ├── AHB.pdf │ │ ├── doc │ │ │ ├── AHBex2.png │ │ │ ├── AHBSlaveFC.png │ │ │ ├── AHBMasterIFC.png │ │ │ ├── AHBMasterXActor.png │ │ │ └── AHBSlaveXActor.png │ │ ├── Makefile │ │ ├── AHBArbiter.bsv │ │ └── AHB.bsv │ ├── Axi │ │ ├── Axi.pdf │ │ ├── doc │ │ │ ├── AXIWrTLM.png │ │ │ ├── AXIWrExample.png │ │ │ ├── AXIMasterXActor.png │ │ │ └── AXISlaveXActor.png │ │ ├── Axi.defines │ │ ├── Makefile │ │ ├── Axi.bsv │ │ └── AxiMonitor.bsv │ ├── TLM │ │ ├── TLM.pdf │ │ ├── doc │ │ │ ├── TLMRAM.png │ │ │ ├── TLMinterfaces.png │ │ │ ├── TLMReadWriteRAM.png │ │ │ ├── TLMTransformIFC.png │ │ │ └── TLMrwinterfaces.png │ │ ├── Makefile │ │ ├── TLM.bsv │ │ ├── TLM2.bsv │ │ ├── TLM.defines │ │ ├── ram_init.text │ │ ├── TLM2Utils.bsv │ │ ├── TLMUtils.bsv │ │ ├── TLMRam.bsv │ │ ├── TLMReduce.bsv │ │ ├── TLM2Reduce.bsv │ │ └── TLMReadWriteRam.bsv │ └── Makefile ├── AMBA_Fabrics │ ├── Doc │ │ └── Figs │ │ │ ├── RSN_2024-12-07.000.00.png │ │ │ └── IMG_Under_Construction.png │ ├── Makefile │ ├── AXI4_Stream │ │ ├── Makefile │ │ └── README_AXI4S.adoc │ ├── Utils │ │ └── Makefile │ ├── Adapters │ │ ├── Makefile │ │ └── README_AXI_Adapters.adoc │ ├── AXI4_Lite │ │ ├── Makefile │ │ └── AXI4L_ClockCrossing.bsv │ └── AXI4 │ │ └── Makefile ├── FPGA │ ├── Makefile │ ├── Misc │ │ ├── Makefile │ │ ├── FPGA_Misc.bsv │ │ └── PTMClocks.bsv │ ├── DDR2 │ │ ├── Makefile │ │ ├── DDR2.bsv │ │ ├── DDR2FakeBurst.bsv │ │ ├── DDR2Types.bsv │ │ └── ML507_mig_33_wrapper.bsv │ ├── Altera │ │ ├── Makefile │ │ └── Altera.bsv │ └── Xilinx │ │ ├── Makefile │ │ ├── Xilinx.bsv │ │ ├── XilinxUtils.bsv │ │ └── DIPSwitch.bsv ├── AMBA_TLM3 │ ├── Makefile │ ├── Axi │ │ ├── Axi.defines │ │ ├── Makefile │ │ ├── Axi.bsv │ │ └── AxiMonitor.bsv │ ├── Apb │ │ ├── Apb.defines │ │ ├── Makefile │ │ └── Apb.bsv │ ├── Ahb │ │ ├── Makefile │ │ ├── AhbArbiter.bsv │ │ ├── Ahb.bsv │ │ ├── AhbAddressRangeMatch.bsv │ │ ├── Readable.bsv │ │ └── AhbToAhbBridge.bsv │ ├── Axi4 │ │ ├── Makefile │ │ └── Axi4.bsv │ └── TLM3 │ │ ├── Makefile │ │ ├── TLM3.bsv │ │ ├── ram_init.text │ │ ├── TLM3Utils.bsv │ │ ├── TLM3Stream.bsv │ │ ├── TLM3FlowControl.bsv │ │ └── TLM.defines ├── Makefile ├── COBS │ └── Makefile ├── Bus │ ├── Makefile │ ├── Bus.bsv │ └── BusDefines.bsv ├── SequenceRules │ ├── Makefile │ └── MList.bs ├── VerilogRepr │ ├── Makefile │ └── Json.bs ├── Misc │ ├── Makefile │ ├── Cur_Cycle.bsv │ ├── CreditCounter.bsv │ ├── VectorFIFOF.bsv │ └── EdgeFIFOFs.bsv └── common.mk ├── Verilog ├── ASSIGN1.v ├── Makefile └── ClockGater.v ├── testing └── bsc.contrib │ ├── GenC │ ├── GenCRepr │ │ ├── TestFn.bsv │ │ ├── Makefile │ │ ├── CalculatorIface.bsv │ │ ├── sysCalculator.out.expected │ │ ├── gencrepr.exp │ │ ├── sysTest.out.expected │ │ ├── test_func.c.keep │ │ ├── calculator_driver.c.keep │ │ ├── Test.bs │ │ └── Calculator.bs │ ├── Makefile │ └── GenCMsg │ │ ├── Makefile │ │ ├── CounterIface.bsv │ │ ├── gencmsg.exp │ │ ├── CounterB2C.bs │ │ ├── sysCounterB2B.out.expected │ │ └── counter_driver.c.keep │ ├── Makefile │ ├── AzureIP │ ├── Makefile │ ├── azureip.exp │ ├── AHBOneToOne.bsv │ ├── ram_init.text │ ├── DMAConfigRegs.bsv │ ├── AxiReadBus.bsv │ ├── AxiWriteBus.bsv │ ├── BackPressureAHBBus.bsv │ └── DMADefines.bsv │ ├── COBS │ ├── Makefile │ ├── cobs.exp │ └── COBSTests.bs │ ├── Misc │ ├── Makefile │ ├── TestSched_VectorFIFOF.bsv │ ├── Test_VectorFIFOF.bsv │ ├── misc.exp │ └── sysTest_VectorFIFOF.out.expected │ ├── AMBA_Fabrics │ ├── Makefile │ ├── AXI4 │ │ ├── Makefile │ │ ├── sysTest_AXI4_Fabric.out.expected │ │ ├── axi4.exp │ │ ├── sysTest_AXI4_Mem_Model.out.expected │ │ └── sysTest_AXI4_Deburster.out.expected │ └── AXI4_Lite │ │ ├── Makefile │ │ ├── axi4_lite.exp │ │ └── sysTest_Fabric.out.expected │ ├── SequenceRules │ ├── Makefile │ ├── sequence_rules.exp │ ├── SequenceRulesTest.bs │ └── sysSequenceRulesTest.out.expected │ ├── VerilogRepr │ ├── Makefile │ ├── verilogrepr.exp │ ├── Chess.bs │ └── chess.svh.expected │ └── contrib.tcl ├── .github └── workflows │ ├── install_dependencies_testsuite_macos.sh │ ├── install_dependencies_testsuite_ubuntu.sh │ └── check_whitespace.sh ├── .gitignore ├── doc └── Makefile ├── Makefile ├── LICENSES └── LICENSE.BSD-3-Clause └── README.md /Libraries/GenC/.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__/ -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/AHB.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/AHB.pdf -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/Axi.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/Axi/Axi.pdf -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/TLM.pdf -------------------------------------------------------------------------------- /Verilog/ASSIGN1.v: -------------------------------------------------------------------------------- 1 | module ASSIGN1(IN, OUT); 2 | output OUT; 3 | input IN; 4 | assign OUT = IN; 5 | endmodule 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/TestFn.bsv: -------------------------------------------------------------------------------- 1 | 2 | import "BDPI" function ActionValue#(Bit#(48)) test_fn(Bit#(64) arg); 3 | -------------------------------------------------------------------------------- /.github/workflows/install_dependencies_testsuite_macos.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | brew install ccache deja-gnu icarus-verilog 4 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/doc/AHBex2.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/doc/AHBex2.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/doc/AXIWrTLM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/Axi/doc/AXIWrTLM.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/doc/TLMRAM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/doc/TLMRAM.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/doc/AHBSlaveFC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/doc/AHBSlaveFC.png -------------------------------------------------------------------------------- /testing/bsc.contrib/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/doc/AHBMasterIFC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/doc/AHBMasterIFC.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/doc/AXIWrExample.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/Axi/doc/AXIWrExample.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/doc/TLMinterfaces.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/doc/TLMinterfaces.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/doc/AHBMasterXActor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/doc/AHBMasterXActor.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/doc/AHBSlaveXActor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/AHB/doc/AHBSlaveXActor.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/doc/AXIMasterXActor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/Axi/doc/AXIMasterXActor.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/doc/AXISlaveXActor.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/Axi/doc/AXISlaveXActor.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/doc/TLMReadWriteRAM.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/doc/TLMReadWriteRAM.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/doc/TLMTransformIFC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/doc/TLMTransformIFC.png -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/doc/TLMrwinterfaces.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_TLM2/TLM/doc/TLMrwinterfaces.png -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/COBS/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/Misc/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Ignore editor backup files 2 | *~ 3 | 4 | # Ignore the inst directory 5 | inst 6 | 7 | # And the build directory 8 | build 9 | 10 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/SequenceRules/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/VerilogRepr/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Doc/Figs/RSN_2024-12-07.000.00.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_Fabrics/Doc/Figs/RSN_2024-12-07.000.00.png -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4_Lite/Makefile: -------------------------------------------------------------------------------- 1 | # for "make clean" to work everywhere 2 | 3 | CONFDIR = $(realpath ../../..) 4 | 5 | include $(CONFDIR)/clean.mk 6 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Doc/Figs/IMG_Under_Construction.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/B-Lang-org/bsc-contrib/HEAD/Libraries/AMBA_Fabrics/Doc/Figs/IMG_Under_Construction.png -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/CalculatorIface.bsv: -------------------------------------------------------------------------------- 1 | 2 | import "BDPI" function ActionValue#(Bit#(48)) getInstr(); 3 | import "BDPI" function Action putResult(Bit#(48) res); 4 | 5 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/sysCalculator.out.expected: -------------------------------------------------------------------------------- 1 | ========= Result aaaa: 100 ========= 2 | ========= Result bbbb: 25 ========= 3 | ========= Result cccc: 240000 ========= 4 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/CounterIface.bsv: -------------------------------------------------------------------------------- 1 | 2 | import "BDPI" function Bool messageAvailable(); 3 | import "BDPI" function ActionValue#(Bit#(64)) getMessage(); 4 | import "BDPI" function Action putMessage(Bit#(64) res); 5 | -------------------------------------------------------------------------------- /.github/workflows/install_dependencies_testsuite_ubuntu.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | apt-get update 4 | 5 | apt-get install -y \ 6 | ccache \ 7 | build-essential \ 8 | lld \ 9 | tcsh \ 10 | dejagnu \ 11 | iverilog 12 | -------------------------------------------------------------------------------- /Libraries/GenC/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BUILD_ORDER = \ 3 | GenCRepr \ 4 | GenCMsg \ 5 | 6 | .PHONY: all 7 | all: install 8 | 9 | .PHONY: install clean full_clean 10 | install clean full_clean: 11 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 12 | 13 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BUILD_ORDER = \ 3 | TLM \ 4 | AHB \ 5 | Axi \ 6 | 7 | .PHONY: all 8 | all: install 9 | 10 | .PHONY: install clean full_clean 11 | install clean full_clean: 12 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 13 | 14 | -------------------------------------------------------------------------------- /doc/Makefile: -------------------------------------------------------------------------------- 1 | .PHONY: help 2 | help: 3 | @echo "Available 'make' targets" 4 | @echo " all Converts .adoc to .html using the 'asciidoctor' tool" 5 | 6 | .PHONY: all 7 | all: 8 | asciidoctor How_to_Contribute.adoc 9 | 10 | clean full_clean: 11 | rm -r -f *~ 12 | -------------------------------------------------------------------------------- /testing/bsc.contrib/Misc/TestSched_VectorFIFOF.bsv: -------------------------------------------------------------------------------- 1 | import FIFOF ::*; 2 | import VectorFIFOF ::*; 3 | 4 | (* synthesize *) 5 | module mkVectorFIFOF_4_Bool(VectorFIFOF#(4,Bool)); 6 | (* hide *) 7 | VectorFIFOF#(4,Bool) __i <- mkVectorFIFOF; 8 | return __i; 9 | endmodule 10 | -------------------------------------------------------------------------------- /Libraries/FPGA/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BUILD_ORDER = \ 3 | Misc \ 4 | DDR2 \ 5 | Altera \ 6 | Xilinx \ 7 | 8 | .PHONY: all 9 | all: install 10 | 11 | .PHONY: install clean full_clean 12 | install clean full_clean: 13 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 14 | 15 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BUILD_ORDER = \ 3 | TLM3 \ 4 | Ahb \ 5 | Apb \ 6 | Axi \ 7 | Axi4 \ 8 | 9 | .PHONY: all 10 | all: install 11 | 12 | .PHONY: install clean full_clean 13 | install clean full_clean: 14 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 15 | 16 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Makefile: -------------------------------------------------------------------------------- 1 | # Enumerate all sub-dirs for recursive traversal 2 | BUILD_ORDER = \ 3 | Utils \ 4 | AXI4 \ 5 | AXI4_Lite \ 6 | AXI4_Stream \ 7 | Adapters \ 8 | 9 | .PHONY: all 10 | all: install 11 | 12 | .PHONY: install clean full_clean 13 | install clean full_clean: 14 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 15 | -------------------------------------------------------------------------------- /Libraries/Makefile: -------------------------------------------------------------------------------- 1 | 2 | BUILD_ORDER = \ 3 | Bus \ 4 | AMBA_TLM2 \ 5 | AMBA_TLM3 \ 6 | FPGA \ 7 | GenC \ 8 | COBS \ 9 | VerilogRepr \ 10 | Misc \ 11 | AMBA_Fabrics \ 12 | SequenceRules \ 13 | 14 | .PHONY: all 15 | all: install 16 | 17 | .PHONY: install clean full_clean 18 | install clean full_clean: 19 | $(foreach dir, $(BUILD_ORDER), $(MAKE) -C $(dir) $@ &&) true 20 | -------------------------------------------------------------------------------- /Libraries/COBS/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../.. 3 | 4 | LIBNAME=COBS 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bs 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | -------------------------------------------------------------------------------- /testing/bsc.contrib/SequenceRules/sequence_rules.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { SequenceRules } 8 | 9 | # Run the basic test 10 | test_c_veri_bs_modules SequenceRulesTest {} 11 | 12 | restore_path 13 | 14 | } 15 | -------------------------------------------------------------------------------- /Libraries/Bus/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../.. 3 | 4 | LIBNAME=Bus 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | 18 | -------------------------------------------------------------------------------- /Libraries/FPGA/Misc/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=FPGA/Misc 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) FPGA_Misc.bsv 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | 18 | -------------------------------------------------------------------------------- /Libraries/SequenceRules/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../.. 3 | 4 | LIBNAME=SequenceRules 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bs 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | -------------------------------------------------------------------------------- /Libraries/FPGA/DDR2/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=FPGA/DDR2 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | 18 | -------------------------------------------------------------------------------- /Libraries/VerilogRepr/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../.. 3 | 4 | LIBNAME=VerilogRepr 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bs 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | 18 | -------------------------------------------------------------------------------- /testing/bsc.contrib/VerilogRepr/verilogrepr.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { VerilogRepr } 8 | 9 | compile_verilog_pass Chess.bs 10 | compare_file chess.svh 11 | compare_file chess_types.json 12 | 13 | restore_path 14 | 15 | } 16 | -------------------------------------------------------------------------------- /Libraries/FPGA/Altera/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=FPGA/Altera 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | 18 | -------------------------------------------------------------------------------- /Libraries/GenC/GenCRepr/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=GenC/GenCRepr 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bs 14 | 15 | .PHONY: clean full_clean 16 | clean full_clean: 17 | -------------------------------------------------------------------------------- /Libraries/FPGA/DDR2/DDR2.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package DDR2; 6 | 7 | import DDR2Types::*; 8 | import DDR2FakeBurst::*; 9 | import ML507_DDR2::*; 10 | import ML507_mig_33_wrapper::*; 11 | 12 | export DDR2Types::*; 13 | export DDR2FakeBurst::*; 14 | export ML507_DDR2::*; 15 | export ML507_mig_33_wrapper::*; 16 | 17 | endpackage 18 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi/Axi.defines: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | `include "TLM.defines" 6 | 7 | 8 | `define AXI_PRM_STD 4, \ 9 | 32, \ 10 | 32, \ 11 | 8 12 | 13 | `define AXI_RR_STD TLMRequest#(`AXI_PRM_STD), \ 14 | TLMResponse#(`AXI_PRM_STD) \ 15 | 16 | `define AXI_XTR_STD `AXI_RR_STD, `AXI_PRM_STD 17 | 18 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/Axi.defines: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | `include "TLM.defines" 6 | 7 | 8 | `define AXI_PRM_STD 4, \ 9 | 32, \ 10 | 32, \ 11 | 10, \ 12 | AxiCustom 13 | 14 | `define AXI_RR_STD TLMRequest#(`AXI_PRM_STD), \ 15 | TLMResponse#(`AXI_PRM_STD) \ 16 | 17 | `define AXI_XTR_STD `AXI_RR_STD, `AXI_PRM_STD 18 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Apb/Apb.defines: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | `include "TLM.defines" 6 | 7 | 8 | `define APB_PRM_STD 4, \ 9 | 32, \ 10 | 32, \ 11 | 10, \ 12 | Bit#(0) 13 | 14 | `define APB_RR_STD TLMRequest#(`APB_PRM_STD), \ 15 | TLMResponse#(`APB_PRM_STD) \ 16 | 17 | `define APB_XTR_STD `APB_RR_STD, `APB_PRM_STD 18 | -------------------------------------------------------------------------------- /Libraries/FPGA/Xilinx/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=FPGA/Xilinx 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc 12 | BSCFLAGS += -p $(BUILDDIR)/../Misc:+ 13 | 14 | .PHONY: build 15 | build: 16 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 17 | 18 | .PHONY: clean full_clean 19 | clean full_clean: 20 | 21 | -------------------------------------------------------------------------------- /Libraries/GenC/GenCMsg/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=GenC/GenCMsg 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in GenCRepr 12 | BSCFLAGS += -p $(BUILDDIR)/../GenCRepr:+ 13 | 14 | .PHONY: build 15 | build: 16 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bs 17 | 18 | .PHONY: clean full_clean 19 | clean full_clean: 20 | -------------------------------------------------------------------------------- /Verilog/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/.. 3 | 4 | INSTALL?=install -c 5 | 6 | PREFIX?=$(TOP)/inst 7 | INSTALLDIR=$(PREFIX)/lib/$(INSTALL_NAME) 8 | 9 | INSTALL_NAME = Verilog 10 | 11 | # ------------------------- 12 | 13 | VERI_FILES = \ 14 | ASSIGN1.v \ 15 | ClockGater.v \ 16 | 17 | .PHONY: install 18 | install: 19 | $(INSTALL) -m 755 -d $(INSTALLDIR) 20 | $(INSTALL) -m 644 $(VERI_FILES) $(INSTALLDIR) 21 | 22 | .PHONY: clean full_clean 23 | clean full_clean: 24 | 25 | # ------------------------- 26 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM3/Ahb 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus and TLM3 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM3:+ 13 | 14 | .PHONY: build 15 | build: 16 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 17 | 18 | .PHONY: clean full_clean 19 | clean full_clean: 20 | 21 | -------------------------------------------------------------------------------- /Libraries/GenC/build_ffi.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | from cffi import FFI 4 | import sys 5 | 6 | def buildFFI(module): 7 | ffibuilder = FFI() 8 | ffibuilder.cdef("\n".join(line for line in open(module + ".h") if not line.startswith('#'))) 9 | ffibuilder.set_source("_" + module, '#include "{}.h"'.format(module), sources=[module + ".c"]) 10 | ffibuilder.compile(verbose=True) 11 | 12 | if __name__ == "__main__": 13 | if len(sys.argv) != 2: 14 | sys.exit("Expected module name") 15 | buildFFI(sys.argv[1]) 16 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi4/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM3/Axi4 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus, TLM3, and Axi 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM3:$(BUILDDIR)/../Axi:+ 13 | 14 | .PHONY: build 15 | build: 16 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 17 | 18 | .PHONY: clean full_clean 19 | clean full_clean: 20 | 21 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/AXI4_Stream/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_Fabrics/AXI4_Stream 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc and AMBA_Fabrics/AXI4 12 | BSCFLAGS += -p $(BUILDDIR)/../../Misc:$(BUILDDIR)/../../AMBA_Fabrics/AXI4:+ 13 | 14 | .PHONY: build 15 | build: 16 | $(BSC) -u $(BSCFLAGS) AXI4_Stream.bsv 17 | 18 | .PHONY: clean full_clean 19 | clean full_clean: 20 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM2/AHB 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus and TLM 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM:+ 13 | 14 | INSTALLFILES = \ 15 | AHB.pdf \ 16 | 17 | .PHONY: build 18 | build: 19 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 20 | 21 | .PHONY: clean full_clean 22 | clean full_clean: 23 | 24 | -------------------------------------------------------------------------------- /testing/bsc.contrib/COBS/cobs.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { COBS } 8 | 9 | # Workaround a Bluespec codegen issue that causes problems on macOS 10 | set link_options {} 11 | if { [which_os] == "Darwin" } { 12 | set link_options {-Xc++ -fbracket-depth=260} 13 | } 14 | 15 | test_c_veri_bs_modules_options COBSTests {} {} {} {} {} $link_options 16 | 17 | restore_path 18 | 19 | } 20 | -------------------------------------------------------------------------------- /Libraries/GenC/GenCRepr/State.bs: -------------------------------------------------------------------------------- 1 | package State where 2 | 3 | -- State monad helper 4 | -- TODO: should this be a bsc library? 5 | data State s a = State (s -> (a, s)) 6 | 7 | instance Monad (State s) where 8 | return x = State $ \ s -> (x, s) 9 | bind (State f) g = State $ \ s1 -> 10 | case f s1 of 11 | (x, s2) -> 12 | case g x of 13 | State h -> h s2 14 | 15 | runState :: State s a -> s -> (a, s) 16 | runState (State f) = f 17 | 18 | get :: State s s 19 | get = State $ \ s -> (s, s) 20 | 21 | put :: s -> State s () 22 | put s = State $ \ _ -> ((), s) 23 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Utils/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_Fabrics/Utils 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc in Utils 12 | BSCFLAGS += -p $(BUILDDIR)/../../Misc:+ 13 | BSCFLAGS += -p $(BUILDDIR)/../Utils:+ 14 | 15 | .PHONY: build 16 | build: 17 | $(BSC) -u $(BSCFLAGS) ByteLane.bsv 18 | $(BSC) -u $(BSCFLAGS) AXIx_SyncBuffer.bsv 19 | 20 | .PHONY: clean full_clean 21 | clean full_clean: 22 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/gencmsg.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { GenC/GenCRepr GenC/GenCMsg } 8 | 9 | compile_pass CounterB2C.bs 10 | copy counter_driver.c.keep counter_driver.c 11 | test_c_only_multi CounterB2C sysCounterB2C { messageAvailable.ba getMessage.ba putMessage.ba counter_driver.c counter.c } "" "" 1 12 | 13 | test_c_veri CounterB2B "" "" "" 1 14 | 15 | restore_path 16 | 17 | } 18 | -------------------------------------------------------------------------------- /Libraries/Misc/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../.. 3 | 4 | LIBNAME=Misc 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../common.mk 10 | 11 | .PHONY: build 12 | build: 13 | $(BSC) -u $(BSCFLAGS) CreditCounter.bsv 14 | $(BSC) -u $(BSCFLAGS) Cur_Cycle.bsv 15 | $(BSC) -u $(BSCFLAGS) EdgeFIFOFs.bsv 16 | $(BSC) -u $(BSCFLAGS) GetPut_Aux.bsv 17 | $(BSC) -u $(BSCFLAGS) Semi_FIFOF.bsv 18 | $(BSC) -u $(BSCFLAGS) VectorFIFOF.bsv 19 | 20 | .PHONY: clean full_clean 21 | clean full_clean: 22 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4_Lite/axi4_lite.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { AMBA_Fabrics/AXI4_Lite Misc } 8 | 9 | # Because we use 'genC' to correct the 'cur_cycle', the .ba file 10 | # is specific to the backend and cannot be reused for the other, 11 | # so we use the '_separately' variant of the test procedure 12 | # 13 | test_c_veri_bsv_separately Test_Fabric 14 | 15 | restore_path 16 | 17 | } 18 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Apb/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM3/Apb 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus and TLM3 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM3:+ 13 | 14 | INSTALLFILES = \ 15 | Apb.defines \ 16 | 17 | .PHONY: build 18 | build: 19 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 20 | cp $(INSTALLFILES) $(BUILDDIR) 21 | 22 | .PHONY: clean full_clean 23 | clean full_clean: 24 | 25 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM3/Axi 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus and TLM3 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM3:+ 13 | 14 | INSTALLFILES = \ 15 | Axi.defines \ 16 | 17 | .PHONY: build 18 | build: 19 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 20 | cp $(INSTALLFILES) $(BUILDDIR) 21 | 22 | .PHONY: clean full_clean 23 | clean full_clean: 24 | 25 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | PWD := $(shell pwd) 2 | TOP := $(PWD) 3 | 4 | PREFIX ?= $(TOP)/inst 5 | BUILDDIR ?= $(TOP)/build 6 | 7 | .PHONY: all 8 | all: install 9 | 10 | # ------------------------- 11 | 12 | .PHONY: rem_inst 13 | rem_inst: 14 | rm -fr $(PREFIX) 15 | 16 | .PHONY: rem_build 17 | rem_build: 18 | rm -fr $(BUILDDIR) 19 | 20 | # ------------------------- 21 | 22 | .PHONY: install clean full_clean 23 | install clean full_clean: 24 | $(MAKE) -C Libraries PREFIX=$(PREFIX) $@ 25 | $(MAKE) -C Verilog PREFIX=$(PREFIX) $@ 26 | 27 | clean full_clean: rem_inst rem_build 28 | 29 | # ------------------------- 30 | -------------------------------------------------------------------------------- /Libraries/Bus/Bus.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Bus; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import BusDefines::*; 12 | import BusFIFO::*; 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | export BusDefines::*; 19 | export BusFIFO::*; 20 | 21 | endpackage 22 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4/sysTest_AXI4_Fabric.out.expected: -------------------------------------------------------------------------------- 1 | M0: COMPLETED stimulus generation 2 | M1: COMPLETED stimulus generation 3 | All Ms: stimulus generation complete. 4 | Lingering to allow in-flight transactions to finish. 5 | M0: total requests:10000 6 | ARs: 4312 AWs: 4387 to supported addrs 7 | ARs: 661 AWs: 640 to wild (unsupported) addrs 8 | RS: 4973 BS: 5027 9 | M1: total requests:10000 10 | ARs: 4305 AWs: 4330 to supported addrs 11 | ARs: 686 AWs: 679 to wild (unsupported) addrs 12 | RS: 4991 BS: 5009 13 | PASS 14 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM2/Axi 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus and TLM 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:$(BUILDDIR)/../TLM:+ 13 | 14 | INSTALLFILES = \ 15 | Axi.defines \ 16 | Axi.pdf \ 17 | 18 | .PHONY: build 19 | build: 20 | -rm -f $(BUILDDIR)/Axi.defines 21 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 22 | cp $(INSTALLFILES) $(BUILDDIR) 23 | 24 | .PHONY: clean full_clean 25 | clean full_clean: 26 | 27 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM3/TLM3 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Bus 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:+ 13 | 14 | INSTALLFILES = \ 15 | ram_init.text \ 16 | SYN.defines \ 17 | TLM.defines \ 18 | 19 | .PHONY: build 20 | build: 21 | -rm -f $(BUILDDIR)/TLM.defines 22 | $(BSC) -u $(BSCFLAGS) $(notdir $(LIBNAME)).bsv 23 | cp $(INSTALLFILES) $(BUILDDIR) 24 | 25 | .PHONY: clean full_clean 26 | clean full_clean: 27 | 28 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/gencrepr.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { GenC/GenCRepr } 8 | 9 | compile_pass Test.bs 10 | copy test_func.c.keep test_func.c 11 | test_c_veri_multi Test sysTest { test_fn.ba test_func.c test.c } 12 | 13 | compile_pass Calculator.bs 14 | copy calculator_driver.c.keep calculator_driver.c 15 | test_c_only_multi Calculator sysCalculator { getInstr.ba putResult.ba calculator_driver.c calculator.c } 16 | 17 | restore_path 18 | 19 | } 20 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_TLM2/TLM 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # TLM2 requires files in Bus 12 | BSCFLAGS += -p $(BUILDDIR)/../../Bus:+ 13 | 14 | INSTALLFILES = \ 15 | ram_init.text \ 16 | TLM.defines \ 17 | TLM.pdf \ 18 | 19 | .PHONY: build 20 | build: 21 | -rm -f $(BUILDDIR)/TLM.defines 22 | $(BSC) -u $(BSCFLAGS) TLM.bsv 23 | $(BSC) -u $(BSCFLAGS) TLM2.bsv 24 | cp $(INSTALLFILES) $(BUILDDIR) 25 | 26 | .PHONY: clean full_clean 27 | clean full_clean: 28 | 29 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/AhbArbiter.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AhbArbiter; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AhbArbiterSupport::*; 12 | import Arbiter::*; 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | export AhbArbiterSupport::*; 19 | export Arbiter::*; 20 | endpackage 21 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/AHBArbiter.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AHBArbiter; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AHBArbiterSupport::*; 12 | import Arbiter::*; 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | export AHBArbiterSupport::*; 19 | export Arbiter::*; 20 | 21 | endpackage 22 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Adapters/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_Fabrics/Adapters 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc and AMBA_Fabrics/AXI4 and AMBA_Fabrics/AXI4_Lite 12 | BSCFLAGS += -p $(BUILDDIR)/../../AMBA_Fabrics/AXI4:+ \ 13 | -p $(BUILDDIR)/../../AMBA_Fabrics/AXI4_Lite:+ \ 14 | -p $(BUILDDIR)/../../Misc:+ 15 | 16 | .PHONY: build 17 | build: 18 | $(BSC) -u $(BSCFLAGS) AXI4L_S_to_AXI4_M_Adapter.bsv 19 | $(BSC) -u $(BSCFLAGS) AXI4_AXI4L_Adapters.bsv 20 | 21 | .PHONY: clean full_clean 22 | clean full_clean: 23 | -------------------------------------------------------------------------------- /Libraries/SequenceRules/MList.bs: -------------------------------------------------------------------------------- 1 | package MList where 2 | 3 | import List 4 | 5 | -- Copyright (c) 2025 MatX, Inc. All Rights Reserved 6 | 7 | -- SPDX-License-Identifier: BSD-3-Clause 8 | 9 | -- A generic monadic List type that allows for the use of the "do" notation to 10 | -- build lists 11 | 12 | data MList_ t a = MList_ (a, List t) 13 | 14 | instance Monad (MList_ t) where 15 | return x = MList_ (x, Nil) 16 | bind (MList_ (a, as)) f = 17 | case f a of 18 | MList_ (b, bs) -> MList_ (b, append as bs) 19 | 20 | type MList t = MList_ t () 21 | 22 | mList :: List t -> MList t 23 | mList as = MList_ ((), as) 24 | 25 | unMList :: MList_ t a -> List t 26 | unMList (MList_ (_, as)) = as 27 | 28 | m :: t -> MList t 29 | m x = mList $ Cons x Nil 30 | -------------------------------------------------------------------------------- /testing/bsc.contrib/Misc/Test_VectorFIFOF.bsv: -------------------------------------------------------------------------------- 1 | import Cur_Cycle ::*; 2 | import FIFOF ::*; 3 | import VectorFIFOF ::*; 4 | 5 | (* synthesize *) 6 | module sysTest_VectorFIFOF(); 7 | VectorFIFOF#(3,Bit#(4)) vf <- mkVectorFIFOF; 8 | 9 | Reg#(Bit#(4)) rg_send <- mkReg(0); 10 | 11 | rule do_enq (rg_send < 8); 12 | vf.fifo.enq(rg_send); 13 | rg_send <= rg_send + 1; 14 | $display("[%d] Contents: ", cur_cycle, fshow(vf.vector)); 15 | $display("[%d] Enq %d", cur_cycle, rg_send); 16 | endrule 17 | 18 | Reg#(Bit#(4)) rg_recv <- mkReg(0); 19 | 20 | rule do_deq; 21 | vf.fifo.deq(); 22 | $display("[%d] Deq %d", cur_cycle, vf.fifo.first); 23 | rg_recv <= rg_recv + 1; 24 | if (rg_recv == 7) 25 | $finish(0); 26 | endrule 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/AXI4_Lite/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_Fabrics/AXI4_Lite 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc and Utils 12 | BSCFLAGS += -p $(BUILDDIR)/../../Misc:+ 13 | BSCFLAGS += -p $(BUILDDIR)/../Utils:+ 14 | 15 | .PHONY: build 16 | build: 17 | $(BSC) -u $(BSCFLAGS) AXI4L_ClockCrossing.bsv 18 | $(BSC) -u $(BSCFLAGS) AXI4L_Clock_Crossers.bsv 19 | $(BSC) -u $(BSCFLAGS) AXI4L_Gate.bsv 20 | $(BSC) -u $(BSCFLAGS) AXI4L_Xactors.bsv 21 | $(BSC) -u $(BSCFLAGS) AXI4L_Fabric.bsv 22 | $(BSC) -u $(BSCFLAGS) AXI4L_Types.bsv 23 | 24 | .PHONY: clean full_clean 25 | clean full_clean: 26 | -------------------------------------------------------------------------------- /Libraries/FPGA/Misc/FPGA_Misc.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package FPGA_Misc; 6 | 7 | // Imports 8 | import ClkCtrlServer ::*; 9 | import DDR3 ::*; 10 | import DDR4 ::*; 11 | import I2C ::*; 12 | import PCIE ::*; 13 | import PTMClocks ::*; 14 | import RS232 ::*; 15 | import Video ::*; 16 | 17 | // Exports 18 | export ClkCtrlServer ::*; 19 | export DDR3 ::*; 20 | export DDR4 ::*; 21 | export I2C ::*; 22 | export PCIE ::*; 23 | export PTMClocks ::*; 24 | export RS232 ::*; 25 | export Video ::*; 26 | 27 | endpackage: FPGA_Misc 28 | -------------------------------------------------------------------------------- /Libraries/common.mk: -------------------------------------------------------------------------------- 1 | # Requires that TOP and LIBNAME be set 2 | 3 | PREFIX?=$(TOP)/inst 4 | 5 | # Where files are ultimately installed 6 | INSTALLDIR=$(PREFIX)/lib/Libraries/$(LIBNAME) 7 | 8 | # Where files are built 9 | BUILDDIR=$(abspath $(TOP)/build/bsvlib/$(LIBNAME)) 10 | 11 | # Put the generated object files in BUILDDIR 12 | BSCFLAGS_EXT += -bdir $(BUILDDIR) 13 | # Increase the RTS stack 14 | #BSCFLAGS_EXT += +RTS -K32M -RTS 15 | 16 | BSCFLAGS ?= $(BSCFLAGS_EXT) 17 | 18 | BSC ?= bsc 19 | 20 | .PHONY: all 21 | all: install 22 | 23 | .PHONY: install 24 | install: build 25 | install -d $(INSTALLDIR) 26 | install -m644 $(BUILDDIR)/* $(INSTALLDIR) 27 | 28 | .PHONY: build 29 | build: $(BUILDDIR) 30 | 31 | $(BUILDDIR): 32 | mkdir -p $@ 33 | 34 | .PHONY: full_clean 35 | full_clean: 36 | rm -rf $(BUILDDIR) 37 | 38 | -------------------------------------------------------------------------------- /testing/bsc.contrib/Misc/misc.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { Misc } 8 | 9 | # --------------- 10 | # VectorFIFOF 11 | 12 | # Check that the method scheduling relationships are as expected 13 | compile_verilog_schedule_pass TestSched_VectorFIFOF.bsv 14 | compare_file_filter_ids TestSched_VectorFIFOF.bsv.bsc-sched-out 15 | 16 | # Test that the module operates as a FIFO 17 | # and confirm that enq and deq occur in the same cycle 18 | # Note: The use of Cur_Cycle requires separate .ba elaboration 19 | test_c_veri_bsv_separately Test_VectorFIFOF 20 | 21 | # --------------- 22 | 23 | restore_path 24 | 25 | } 26 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/AHB/AHB.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AHB; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AHBArbiter::*; 12 | import AHBBus::*; 13 | import AHBDefines::*; 14 | import AHBMaster::*; 15 | import AHBPC::*; 16 | import AHBSlave::*; 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | export AHBArbiter::*; 23 | export AHBBus::*; 24 | export AHBDefines::*; 25 | export AHBMaster::*; 26 | export AHBPC::*; 27 | export AHBSlave::*; 28 | 29 | endpackage 30 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import TLMCBusAdapter::*; 12 | import TLMDefines::*; 13 | import TLMRam::*; 14 | import TLMReadWriteRam::*; 15 | import TLMReduce::*; 16 | import TLMUtils::*; 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | export TLMCBusAdapter::*; 23 | export TLMDefines::*; 24 | export TLMRam::*; 25 | export TLMReadWriteRam::*; 26 | export TLMReduce::*; 27 | export TLMUtils::*; 28 | 29 | endpackage 30 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/Axi.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Axi; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AxiDefines::*; 12 | import AxiMaster::*; 13 | import AxiSlave::*; 14 | import AxiRdBus::*; 15 | import AxiWrBus::*; 16 | import AxiPC::*; 17 | import AxiMonitor::*; 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | /// 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | export AxiDefines::*; 24 | export AxiMaster::*; 25 | export AxiSlave::*; 26 | export AxiRdBus::*; 27 | export AxiWrBus::*; 28 | export AxiPC::*; 29 | export AxiMonitor::*; 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/Ahb.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Ahb; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AhbArbiter::*; 12 | import AhbBus::*; 13 | import AhbDefines::*; 14 | import AhbMaster::*; 15 | import AhbPC::*; 16 | import AhbSlave::*; 17 | import AhbToAhbBridge::*; 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | /// 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | export AhbArbiter::*; 24 | export AhbBus::*; 25 | export AhbDefines::*; 26 | export AhbMaster::*; 27 | export AhbPC::*; 28 | export AhbSlave::*; 29 | export AhbToAhbBridge::*; 30 | 31 | endpackage 32 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4/axi4.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { AMBA_Fabrics/AXI4 AMBA_Fabrics/Utils Misc } 8 | 9 | # Because we use 'genC' to correct the 'cur_cycle', the .ba file 10 | # is specific to the backend and cannot be reused for the other, 11 | # so we use the '_separately' variant of the test procedure 12 | # 13 | test_c_only_bsv_modules_options Test_AXI4_Fabric {} {-aggressive-conditions} 14 | test_veri_only_bsv_modules_options Test_AXI4_Fabric {} {-aggressive-conditions} 15 | test_c_veri_bsv_separately Test_AXI4_Mem_Model 16 | test_c_veri_bsv_separately Test_AXI4_to_LDST 17 | test_c_veri_bsv_separately Test_AXI4_Deburster 18 | 19 | restore_path 20 | 21 | } 22 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi/Axi.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Axi; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AxiDefines::*; 12 | import AxiExtend::*; 13 | import AxiMaster::*; 14 | import AxiSlave::*; 15 | import AxiRdBus::*; 16 | import AxiWrBus::*; 17 | import AxiPC::*; 18 | // import AxiMonitor::*; 19 | 20 | //////////////////////////////////////////////////////////////////////////////// 21 | /// 22 | //////////////////////////////////////////////////////////////////////////////// 23 | 24 | export AxiDefines::*; 25 | export AxiExtend::*; 26 | export AxiMaster::*; 27 | export AxiSlave::*; 28 | export AxiRdBus::*; 29 | export AxiWrBus::*; 30 | export AxiPC::*; 31 | // export AxiMonitor::*; 32 | 33 | endpackage 34 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi4/Axi4.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Axi4; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import Axi4Defines::*; 12 | import Axi4Master::*; 13 | import Axi4Slave::*; 14 | import Axi4PC::*; 15 | 16 | import Axi4LDefines::*; 17 | import Axi4LMaster::*; 18 | import Axi4LSlave::*; 19 | import Axi4LPC::*; 20 | 21 | //////////////////////////////////////////////////////////////////////////////// 22 | /// 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | export Axi4Defines::*; 26 | export Axi4Master::*; 27 | export Axi4Slave::*; 28 | export Axi4PC::*; 29 | 30 | export Axi4LDefines::*; 31 | export Axi4LMaster::*; 32 | export Axi4LSlave::*; 33 | export Axi4LPC::*; 34 | 35 | endpackage 36 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM2.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM2; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import TLM2BRAM::*; 12 | import TLM2CBusAdapter::*; 13 | import TLM2Defines::*; 14 | import TLM2Ram::*; 15 | import TLM2ReadWriteRam::*; 16 | import TLM2Reduce::*; 17 | import TLM2Utils::*; 18 | import BusSwitch::*; 19 | 20 | //////////////////////////////////////////////////////////////////////////////// 21 | /// 22 | //////////////////////////////////////////////////////////////////////////////// 23 | 24 | export TLM2BRAM::*; 25 | export TLM2CBusAdapter::*; 26 | export TLM2Defines::*; 27 | export TLM2Ram::*; 28 | export TLM2ReadWriteRam::*; 29 | export TLM2Reduce::*; 30 | export TLM2Utils::*; 31 | export BusSwitch::*; 32 | 33 | endpackage 34 | -------------------------------------------------------------------------------- /Libraries/FPGA/Altera/Altera.bsv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 3 | // 4 | // SPDX-License-Identifier: BSD-3-Clause 5 | // 6 | //////////////////////////////////////////////////////////////////////////////// 7 | // Filename : Altera.bsv 8 | // Description : Altera specific libraries 9 | //////////////////////////////////////////////////////////////////////////////// 10 | package Altera; 11 | 12 | // Notes : 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// Imports 16 | //////////////////////////////////////////////////////////////////////////////// 17 | import AlteraCells ::*; 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | /// Exports 21 | //////////////////////////////////////////////////////////////////////////////// 22 | export AlteraCells ::*; 23 | 24 | endpackage: Altera 25 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/AhbAddressRangeMatch.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AhbAddressRangeMatch; 6 | import Ahb::*; 7 | 8 | `include "TLM.defines" 9 | 10 | //This is the same function as AhbDefinesSupport::addAddrMatch 11 | //but isolated from the rest of the file, which currently does 12 | //not compile 13 | 14 | //This also avoids the name collision with APB/APBDefines.bsv::addAddrMatch 15 | function AhbXtorSlaveWM#(`TLM_PRM) ahbAddAddrMatch(function Bool addr_match(AhbAddr#(`TLM_PRM) addr), 16 | AhbXtorSlave#(`TLM_PRM) ifc); 17 | let ifc_wm = (interface AhbXtorSlaveWM; 18 | interface AhbSlave bus = ifc.bus; 19 | interface AhbSlaveSelector selector = ifc.selector; 20 | method addrMatch = addr_match; 21 | endinterface); 22 | 23 | return ifc_wm; 24 | endfunction 25 | 26 | endpackage 27 | -------------------------------------------------------------------------------- /testing/bsc.contrib/Misc/sysTest_VectorFIFOF.out.expected: -------------------------------------------------------------------------------- 1 | [ 1] Contents: 2 | [ 1] Enq 0 3 | [ 2] Contents: 4 | [ 2] Enq 1 5 | [ 2] Deq 0 6 | [ 3] Contents: 7 | [ 3] Enq 2 8 | [ 3] Deq 1 9 | [ 4] Contents: 10 | [ 4] Enq 3 11 | [ 4] Deq 2 12 | [ 5] Contents: 13 | [ 5] Enq 4 14 | [ 5] Deq 3 15 | [ 6] Contents: 16 | [ 6] Enq 5 17 | [ 6] Deq 4 18 | [ 7] Contents: 19 | [ 7] Enq 6 20 | [ 7] Deq 5 21 | [ 8] Contents: 22 | [ 8] Enq 7 23 | [ 8] Deq 6 24 | [ 9] Deq 7 25 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/AXI4/Makefile: -------------------------------------------------------------------------------- 1 | PWD:=$(shell pwd) 2 | TOP:=$(PWD)/../../.. 3 | 4 | LIBNAME=AMBA_Fabrics/AXI4 5 | 6 | # Requires that TOP and LIBNAME be set 7 | # Sets BUILDDIR, and BSC and BSCFLAGS if not set 8 | # and defines the install target 9 | include ../../common.mk 10 | 11 | # Requires files in Misc and Utils 12 | BSCFLAGS += -p $(BUILDDIR)/../../Misc:+ 13 | BSCFLAGS += -p $(BUILDDIR)/../Utils:+ 14 | 15 | .PHONY: build 16 | build: 17 | $(BSC) -u $(BSCFLAGS) AXI4_Types.bsv 18 | $(BSC) -u $(BSCFLAGS) AXI4_BSV_RTL.bsv 19 | $(BSC) -u $(BSCFLAGS) AXI4_Mem_Model.bsv 20 | $(BSC) -u $(BSCFLAGS) AXI4_to_LD.bsv 21 | $(BSC) -u $(BSCFLAGS) AXI4_to_LDST.bsv 22 | $(BSC) -u $(BSCFLAGS) AXI4_to_LDST_utils.bsv 23 | $(BSC) -u $(BSCFLAGS) AXI4_to_ST.bsv 24 | $(BSC) -u $(BSCFLAGS) AXI4_Addr_Translator.bsv 25 | $(BSC) -u $(BSCFLAGS) AXI4_Clock_Crossers.bsv 26 | $(BSC) -u $(BSCFLAGS) AXI4_Deburster.bsv 27 | $(BSC) -u $(BSCFLAGS) AXI4_Fabric.bsv 28 | $(BSC) -u $(BSCFLAGS) AXI4_Gate.bsv 29 | $(BSC) -u $(BSCFLAGS) AXI4_Widener.bsv 30 | 31 | .PHONY: clean full_clean 32 | clean full_clean: 33 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/sysTest.out.expected: -------------------------------------------------------------------------------- 1 | Cons 0x00 Nil 2 | Cons 0x01 Nil 3 | Cons 0x02 Nil 4 | Cons 0x03 Nil 5 | ThingMsg {thing=Thing {w=[ 1, 2]; x= 1; y= 2; z= 4660}; swapXY=False; deltaZ= 8} 6 | Cons 0x01 (Cons 0x02 (Cons 0x01 (Cons 0x02 (Cons 0x12 (Cons 0x34 (Cons 0x00 (Cons 0x08 Nil))))))) 7 | 0x0102010212340008 8 | Called test_fn 102010212340008 9 | Unpacked msg: 1 2 1 2 4660 0 8 10 | res: 9 10 1 2 4668 11 | Packed res: 90a0102123c 12 | 0x090a0102123c 13 | Cons 0x09 (Cons 0x0a (Cons 0x01 (Cons 0x02 (Cons 0x12 (Cons 0x3c Nil))))) 14 | Thing {w=[ 9, 10]; x= 1; y= 2; z= 4668} 15 | ThingMsg {thing=Thing {w=[ 1, 2]; x= 1; y= 2; z= 4660}; swapXY=True; deltaZ= -8} 16 | Cons 0x01 (Cons 0x02 (Cons 0x01 (Cons 0x02 (Cons 0x12 (Cons 0x34 (Cons 0x01 (Cons 0x18 Nil))))))) 17 | 0x0102010212340118 18 | Called test_fn 102010212340118 19 | Unpacked msg: 1 2 1 2 4660 1 -8 20 | res: -7 -6 2 1 4652 21 | Packed res: f9fa0201122c 22 | 0xf9fa0201122c 23 | Cons 0xf9 (Cons 0xfa (Cons 0x02 (Cons 0x01 (Cons 0x12 (Cons 0x2c Nil))))) 24 | Thing {w=[ -7, -6]; x= 2; y= 1; z= 4652} 25 | -------------------------------------------------------------------------------- /Libraries/FPGA/Xilinx/Xilinx.bsv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 3 | // 4 | // SPDX-License-Identifier: BSD-3-Clause 5 | // 6 | //////////////////////////////////////////////////////////////////////////////// 7 | // Filename : Xilinx.bsv 8 | // Description : Xilinx specific libraries 9 | //////////////////////////////////////////////////////////////////////////////// 10 | package Xilinx; 11 | 12 | // Notes : 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// Imports 16 | //////////////////////////////////////////////////////////////////////////////// 17 | import XilinxCells ::*; 18 | import XilinxClocks ::*; 19 | import XilinxUtils ::*; 20 | 21 | //////////////////////////////////////////////////////////////////////////////// 22 | /// Exports 23 | //////////////////////////////////////////////////////////////////////////////// 24 | export XilinxCells ::*; 25 | import XilinxClocks ::*; 26 | export XilinxUtils ::*; 27 | 28 | endpackage: Xilinx 29 | -------------------------------------------------------------------------------- /.github/workflows/check_whitespace.sh: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env bash 2 | 3 | set -e 4 | 5 | RESULT=0 6 | 7 | # ----- 8 | # Check for trailing whitespace 9 | 10 | # For now, restrict to Bluespec code 11 | 12 | # We should at least look for both trailing space (' ') and tab ('\t'). 13 | # By using '\s' in the grep pattern, we also check for CR ('\r') and 14 | # LF ('\f'). If we wanted to allow DOS files (that end lines with \r\n) 15 | # then the grep pattern would need to be '( |\t|\f)\r?$' so that we detect 16 | # spaces and tabs that are followed by CR (and thus not fully trailing). 17 | 18 | ALLOWFILE=${SCRIPTDIR}/allow_whitespace.pats 19 | CMD="git ls-files | egrep '\.(bs|bsv)$' | xargs grep -H -n -e '\s$'" 20 | if [ $(eval "$CMD -l -- | wc -l") -ne 0 ]; then 21 | eval "$CMD --" || true 22 | echo "Trailing whitespace found!" 23 | RESULT=1 24 | fi 25 | 26 | # ----- 27 | # Check for tabs 28 | 29 | # Don't allow tabs in BH/Classic code, where formatting matters 30 | CMD="git ls-files | egrep '\.bs$' | xargs grep -H -n -e $'\t'" 31 | if [ $(eval "$CMD -l -- | wc -l") -ne 0 ]; then 32 | eval "$CMD --" || true 33 | echo "Tabs found!" 34 | RESULT=1 35 | fi 36 | 37 | # ----- 38 | 39 | exit $RESULT 40 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4/sysTest_AXI4_Mem_Model.out.expected: -------------------------------------------------------------------------------- 1 | ================================ 2 | AXI4_Mem_Model[0]: initialization 3 | addr_base: 0x2000 addr_lim: 0x3000 (byte addrs) 4 | addrMW_base:0x800 addrMW_lim:0xc00 (word addrs) 5 | AXI4 params: wd_id:5 wd_addr:14 wd_data:32 wd_user:30 6 | Memory contains 1024 words, each wd_data bits (4 bytes) wide 7 | Zeroing memory 8 | ================================ 9 | ================================ 10 | Test_AXI4_Mem_Model: initialization 11 | addr_base:0x2000 addr_lim:0x3000 12 | addrMW_base:0x800 addrMW_lim:0xc00 (word addrs) 13 | AXI4 params: Wd_Id:5 Wd_Addr:14 Wd_Data:32 Wd_User:30 14 | Memory contains 1024 words, each wd_data bits (4 bytes) wide 15 | Zeroing reference memory 16 | ================================ 17 | AXI4_Mem_Model[0]: zero'd memory 18 | Test_AXI4_Mem_Model: zero'd reference memory 19 | sysTest_AXI4_Mem_Model: All Ms: stimulus generation complete. 20 | Lingering to allow in-flight transactions to finish. 21 | mkMBox0: total requests:10000 22 | ARs: 4977 AWs: 5023 to supported addrs 23 | ARs: 0 AWs: 0 to wild (unsupported) addrs 24 | RS: 4977 BS: 5023 25 | PASS 26 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/TLM3.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM3; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import TLM3Api::*; 12 | import TLM3BRAM::*; 13 | import TLM3CBusAdapter::*; 14 | import TLM3Defines::*; 15 | import TLM3Limit::*; 16 | import TLM3Reorder::*; 17 | import TLM3FlowControl::*; 18 | import TLM3Ram::*; 19 | import TLM3ReadWriteRam::*; 20 | import TLM3Reduce::*; 21 | import TLM3Stream::*; 22 | import TLM3Utils::*; 23 | import BusSwitch::*; 24 | 25 | 26 | //////////////////////////////////////////////////////////////////////////////// 27 | /// 28 | //////////////////////////////////////////////////////////////////////////////// 29 | 30 | export TLM3Api::*; 31 | export TLM3BRAM::*; 32 | export TLM3CBusAdapter::*; 33 | export TLM3Defines::*; 34 | export TLM3Limit::*; 35 | export TLM3Reorder::*; 36 | export TLM3FlowControl::*; 37 | export TLM3Ram::*; 38 | export TLM3ReadWriteRam::*; 39 | export TLM3Reduce::*; 40 | export TLM3Stream::*; 41 | export TLM3Utils::*; 42 | export BusSwitch::*; 43 | 44 | endpackage 45 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Apb/Apb.bsv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 3 | // 4 | // SPDX-License-Identifier: BSD-3-Clause 5 | // 6 | //////////////////////////////////////////////////////////////////////////////// 7 | // Filename : APB.bsv 8 | // Description : APB4 Bus Defintion 9 | //////////////////////////////////////////////////////////////////////////////// 10 | package Apb; 11 | 12 | // Notes : 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// Imports 16 | //////////////////////////////////////////////////////////////////////////////// 17 | import ApbDefines ::*; 18 | //import ApbMasterAxi ::*; 19 | import ApbMaster ::*; 20 | import ApbSlave ::*; 21 | import ApbBus ::*; 22 | 23 | //////////////////////////////////////////////////////////////////////////////// 24 | /// Exports 25 | //////////////////////////////////////////////////////////////////////////////// 26 | export ApbDefines ::*; 27 | //export ApbMasterAxi ::*; 28 | export ApbMaster ::*; 29 | export ApbSlave ::*; 30 | export ApbBus ::*; 31 | 32 | endpackage: Apb 33 | 34 | -------------------------------------------------------------------------------- /Verilog/ClockGater.v: -------------------------------------------------------------------------------- 1 | 2 | `ifdef BSV_ASSIGNMENT_DELAY 3 | `else 4 | `define BSV_ASSIGNMENT_DELAY 5 | `endif 6 | 7 | `ifdef BSV_POSITIVE_RESET 8 | `define BSV_RESET_VALUE 1'b1 9 | `define BSV_RESET_EDGE posedge 10 | `else 11 | `define BSV_RESET_VALUE 1'b0 12 | `define BSV_RESET_EDGE negedge 13 | `endif 14 | 15 | 16 | // Bluespec primitive module which gates a clock 17 | // To avoid glitches, CLK_GATE_OUT only changes when CLK_IN is low. 18 | // CLK_GATE_OUT follows CLK_GATE_IN in the same cycle, but COND is first 19 | // registered, thus delaying the gate condition by one cycle. 20 | // In this model, the oscillator CLK_OUT does *not* stop when the CLK_GATE_IN or 21 | // COND are deasserted. 22 | module ClockGater( 23 | // ports for the internal register 24 | CLK, 25 | RST, 26 | COND, 27 | // ports for the output clock 28 | CLK_OUT, 29 | CLK_GATE_OUT ); 30 | 31 | parameter init = 1 ; 32 | 33 | input CLK ; 34 | input RST ; 35 | input COND ; 36 | output CLK_OUT ; 37 | output CLK_GATE_OUT ; 38 | 39 | // BUFG buf_gC(.I(CLK), .O(CLK_OUT)); 40 | assign CLK_OUT = CLK; 41 | //BUFG buf_gG(.I(COND), .O(CLK_GATE_OUT)); 42 | assign CLK_GATE_OUT = COND; 43 | endmodule // GatedClock 44 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/test_func.c.keep: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "test.h" 4 | 5 | unsigned long long test_fn(unsigned long long in) { 6 | printf("Called test_fn %llx\n", in); 7 | uint8_t in_buf[size_ThingMsg], *in_ptr = &in_buf[0]; 8 | for (int i = size_ThingMsg - 1; i >= 0; i--) { 9 | in_buf[i] = in & 0xFF; 10 | in >>= 8; 11 | } 12 | ThingMsg msg = unpack_ThingMsg(&in_ptr); 13 | printf("Unpacked msg: %hhd %hhd %hhu %hhu %hd %hhd %hhd\n", msg.thing.w[0], msg.thing.w[1], msg.thing.x, msg.thing.y, msg.thing.z, msg.swapXY, msg.deltaZ); 14 | 15 | Thing res = {0}; 16 | for (unsigned i = 0; i < 2; i++) { 17 | res.w[i] = msg.thing.w[i] + msg.deltaZ; 18 | } 19 | if (msg.swapXY) { 20 | res.x = msg.thing.y; 21 | res.y = msg.thing.x; 22 | } else { 23 | res.x = msg.thing.x; 24 | res.y = msg.thing.y; 25 | } 26 | res.z = msg.thing.z + msg.deltaZ; 27 | printf("res: %hhd %hhd %hhu %hhu %hd\n", res.w[0], res.w[1], res.x, res.y, res.z); 28 | 29 | unsigned long long out = 0; 30 | uint8_t out_buf[size_Thing], *out_ptr = &out_buf[0]; 31 | pack_Thing(res, &out_ptr); 32 | for (int i = 0; i < size_Thing; i++) { 33 | out <<= 8; 34 | out |= out_buf[i]; 35 | } 36 | printf("Packed res: %llx\n", out); 37 | return out; 38 | } 39 | -------------------------------------------------------------------------------- /Libraries/FPGA/Xilinx/XilinxUtils.bsv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 3 | // 4 | // SPDX-License-Identifier: BSD-3-Clause 5 | // 6 | //////////////////////////////////////////////////////////////////////////////// 7 | // Filename : XilinxUtils.bsv 8 | // Description : Xilinx evaluation board utilities 9 | //////////////////////////////////////////////////////////////////////////////// 10 | package XilinxUtils; 11 | 12 | //////////////////////////////////////////////////////////////////////////////// 13 | /// Imports 14 | //////////////////////////////////////////////////////////////////////////////// 15 | import DIPSwitch ::*; 16 | import ButtonController ::*; 17 | import LEDController ::*; 18 | import LCDController ::*; 19 | import DVIController ::*; 20 | import GPIOController ::*; 21 | import HDMIController ::*; 22 | 23 | //////////////////////////////////////////////////////////////////////////////// 24 | /// Exports 25 | //////////////////////////////////////////////////////////////////////////////// 26 | export DIPSwitch ::*; 27 | export ButtonController ::*; 28 | export LEDController ::*; 29 | export LCDController ::*; 30 | export DVIController ::*; 31 | export GPIOController ::*; 32 | export HDMIController ::*; 33 | 34 | endpackage: XilinxUtils 35 | -------------------------------------------------------------------------------- /Libraries/FPGA/DDR2/DDR2FakeBurst.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | import GetPut::*; 6 | import FIFO::*; 7 | 8 | import DDR2Types::*; 9 | 10 | 11 | // Module adapts a non-bursting DDR2Client to a 4-burst DRR2Client. 12 | // Non-bursting means for each command there is one 64 bit data word read or 13 | // written. 4-burst means for each command there are four 64 bit data words 14 | // read or written. 15 | module mkDDR2FakeBurst#(DDR2Client nb) (DDR2Client); 16 | 17 | FIFO#(DDR2ReqData) wdata <- mkFIFO(); 18 | FIFO#(DDR2Data) rdata <- mkFIFO(); 19 | 20 | Reg#(Bit#(2)) wcount <- mkReg(0); 21 | Reg#(Bit#(2)) rcount <- mkReg(0); 22 | 23 | rule write (True); 24 | if (wcount == 0) begin 25 | let x <- nb.request.data.get(); 26 | wdata.enq(x); 27 | end else begin 28 | wdata.enq(DDR2ReqData { data: ?, be: 8'h00 }); 29 | end 30 | wcount <= wcount+1; 31 | endrule 32 | 33 | rule read (True); 34 | if (rcount == 0) begin 35 | nb.response.put(rdata.first()); 36 | end 37 | rcount <= rcount+1; 38 | rdata.deq(); 39 | endrule 40 | 41 | interface DDR2RequestClient request; 42 | interface Get command = nb.request.command; 43 | interface Get data = toGet(wdata); 44 | endinterface 45 | 46 | interface Put response = toPut(rdata); 47 | 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/azureip.exp: -------------------------------------------------------------------------------- 1 | # Include the boilerplate for bsc-contrib tests 2 | set here [file join [absolute $srcdir] $subdir] 3 | source $here/../contrib.tcl 4 | 5 | if { $contribtest } { 6 | 7 | add_contrib_dirs_to_path { Bus AMBA_TLM2/TLM AMBA_TLM2/AHB AMBA_TLM2/Axi } 8 | 9 | # The Verilog and Bluesim expected files are different because the randomizer 10 | # in AzureIP is different, so different traffic is generated. 11 | 12 | # We sort the output because rules that contain $display but are otherwise CF 13 | # can be scheduled in any order. 14 | set sort_output 1 15 | 16 | test_c_only_bsv TestDMA sysTestDMA.c.out.expected 17 | test_veri_only_bsv TestDMA sysTestDMA.v.out.expected 18 | 19 | test_c_only_bsv AHBOneToOne sysAHBOneToOne.c.out.expected "" $sort_output 20 | test_veri_only_bsv AHBOneToOne sysAHBOneToOne.v.out.expected "" $sort_output 21 | 22 | test_c_only_bsv BackPressureAHBBus \ 23 | sysBackPressureAHBBus.c.out.expected "" $sort_output 24 | test_veri_only_bsv BackPressureAHBBus \ 25 | sysBackPressureAHBBus.v.out.expected "" $sort_output 26 | 27 | test_c_only_bsv AxiReadBus sysAxiReadBus.c.out.expected 28 | test_veri_only_bsv AxiReadBus sysAxiReadBus.v.out.expected 29 | 30 | test_c_only_bsv AxiWriteBus sysAxiWriteBus.c.out.expected 31 | test_veri_only_bsv AxiWriteBus sysAxiWriteBus.v.out.expected 32 | 33 | restore_path 34 | 35 | } 36 | -------------------------------------------------------------------------------- /testing/bsc.contrib/contrib.tcl: -------------------------------------------------------------------------------- 1 | #################### 2 | 3 | if { ! [info exists contribtest] } then { 4 | 5 | # Look for this environment variable 6 | set var BSCCONTRIBDIR 7 | 8 | if { [info exists env($var)] && [file isdirectory $env($var)] } then { 9 | set contrib_inst $env($var) 10 | set contribtest 1 11 | } else { 12 | set contrib_inst "" 13 | set contribtest 0 14 | } 15 | 16 | verbose -log "Do contrib tests is $contribtest" 1 17 | if { $contribtest } { 18 | verbose -log "Contrib inst is $contrib_inst" 1 19 | } 20 | 21 | } 22 | 23 | #################### 24 | 25 | proc add_contrib_dirs_to_path { dirs } { 26 | global old_option 27 | global contrib_inst 28 | 29 | # Make sure the tools are initialized first 30 | # so that they aren't initialized with the new path 31 | # (in case the caller gave bad values) 32 | bsc_initialize 33 | bluetcl_initialize 34 | 35 | # Record the current path 36 | set old_option "" 37 | if { [info exists ::env(BSC_OPTIONS)] } { 38 | set old_option $::env(BSC_OPTIONS) 39 | } 40 | 41 | set libdir "$contrib_inst/lib/Libraries" 42 | 43 | if { [llength $dirs] > 0 } { 44 | append ::env(BSC_OPTIONS) " -p " 45 | foreach d $dirs { 46 | append ::env(BSC_OPTIONS) "$libdir/$d:" 47 | } 48 | append ::env(BSC_OPTIONS) "+" 49 | } 50 | } 51 | 52 | proc restore_path { } { 53 | global old_option 54 | 55 | set ::env(BSC_OPTIONS) $old_option 56 | } 57 | 58 | #################### 59 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/AHBOneToOne.bsv: -------------------------------------------------------------------------------- 1 | package AHBOneToOne; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import AHB::*; 8 | import Connectable::*; 9 | import TLM2::*; 10 | 11 | `include "TLM.defines" 12 | 13 | //////////////////////////////////////////////////////////////////////////////// 14 | /// 15 | //////////////////////////////////////////////////////////////////////////////// 16 | 17 | (* synthesize *) 18 | module sysAHBOneToOne (); 19 | 20 | Reg#(Bit#(16)) count <- mkReg(0); 21 | 22 | TLMSendIFC#(`TLM_RR_STD) source <- mkTLM2Source(tagged Invalid, True); 23 | 24 | AHBMasterXActor#(`TLM_RR_STD, `TLM_PRM_STD) master <- mkAHBMasterStd; 25 | AHBSlaveXActor#(`TLM_RR_STD, `TLM_PRM_STD) slave <- mkAHBSlaveStd(alwaysAddrMatch); 26 | 27 | TLMRecvIFC#(`TLM_RR_STD) mem <- mkTLMRam_unbuffered(0, True); 28 | 29 | mkConnection(source, master.tlm); 30 | mkConnection(master.fabric.bus, slave.fabric.bus); 31 | mkConnection(slave.tlm, mem); 32 | 33 | // AHBMonitor#(`TLM_PRM_STD) monitor <- mkAHBMonitor(False, master.fabric.bus, slave.fabric.bus); 34 | 35 | // a simple "arbiter" that gives the one master the grant whenever he asks for it. 36 | rule give_grant; 37 | master.fabric.arbiter.hGRANT(master.fabric.arbiter.hBUSREQ); 38 | endrule 39 | 40 | rule every; 41 | // always select the one slave 42 | slave.fabric.selector.select(True); 43 | count <= count + 1; 44 | if (count == 500) $finish; 45 | endrule 46 | 47 | endmodule 48 | 49 | endpackage 50 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/calculator_driver.c.keep: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "calculator.h" 4 | 5 | Instr instrs[] = { 6 | {Instr_Put, {.Put = {0, 10}}}, 7 | {Instr_Put, {.Put = {1, 20}}}, 8 | {Instr_Put, {.Put = {2, 30}}}, 9 | {Instr_Put, {.Put = {3, 40}}}, 10 | 11 | // Compute sum 12 | {Instr_Op, {.Op = {{Op_Add}, 0, 1, 4}}}, 13 | {Instr_Op, {.Op = {{Op_Add}, 2, 4, 4}}}, 14 | {Instr_Op, {.Op = {{Op_Add}, 3, 4, 4}}}, 15 | {Instr_Get, {.Get = {4, 0xAAAA}}}, 16 | 17 | // Compute mean 18 | {Instr_Put, {.Put = {5, 4}}}, 19 | {Instr_Op, {.Op = {{Op_Div}, 4, 5, 4}}}, 20 | {Instr_Get, {.Get = {4, 0xBBBB}}}, 21 | 22 | // Compute product 23 | {Instr_Op, {.Op = {{Op_Mul}, 0, 1, 5}}}, 24 | {Instr_Op, {.Op = {{Op_Mul}, 2, 5, 5}}}, 25 | {Instr_Op, {.Op = {{Op_Mul}, 3, 5, 5}}}, 26 | {Instr_Get, {.Get = {5, 0xCCCC}}}, 27 | 28 | Instr_Halt 29 | }; 30 | 31 | unsigned ic = 0; 32 | 33 | unsigned long long getInstr() { 34 | Instr i = ic < sizeof(instrs) / sizeof(Instr)? instrs[ic] : (Instr){Instr_NoOp}; 35 | ic++; 36 | 37 | unsigned long long out = 0; 38 | uint8_t out_buf[size_Instr], *out_ptr = &out_buf[0]; 39 | pack_Instr(i, &out_ptr); 40 | for (int i = 0; i < size_Instr; i++) { 41 | out <<= 8; 42 | out |= out_buf[i]; 43 | } 44 | return out; 45 | } 46 | 47 | void putResult(unsigned long long in) { 48 | uint8_t in_buf[size_Result], *in_ptr = &in_buf[0]; 49 | for (int i = size_Result - 1; i >= 0; i--) { 50 | in_buf[i] = in & 0xFF; 51 | in >>= 8; 52 | } 53 | Result res = unpack_Result(&in_ptr); 54 | 55 | printf("========= Result %hx: %d =========\n", res.id, res.result); 56 | } 57 | -------------------------------------------------------------------------------- /LICENSES/LICENSE.BSD-3-Clause: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------- 2 | 3 | Redistribution and use in source and binary forms, with or without 4 | modification, are permitted provided that the following conditions are 5 | met: 6 | 7 | 1. Redistributions of source code must retain the above copyright 8 | notice, this list of conditions and the following disclaimer. 9 | 10 | 2. Redistributions in binary form must reproduce the above copyright 11 | notice, this list of conditions and the following disclaimer in the 12 | documentation and/or other materials provided with the 13 | distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its 16 | contributors may be used to endorse or promote products derived 17 | from this software without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 | "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 22 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 23 | HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 24 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 25 | LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 | DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 | THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 29 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 | 31 | --------------------------------------------------------------------------- 32 | -------------------------------------------------------------------------------- /Libraries/Misc/Cur_Cycle.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2013-2024 Bluespec, Inc. All Rights Reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Cur_Cycle; 6 | 7 | // ================================================================ 8 | // A convenience function to return the current cycle number during BSV simulations 9 | // The if-then-else is because in Verilog our $displays work on the 10 | // opposide edge (in the middle of the clock). 11 | 12 | ActionValue #(Bit #(32)) cur_cycle = actionvalue 13 | Bit #(32) t <- $stime; 14 | if (genC) 15 | return t / 10; 16 | else 17 | return (t + 5) / 10; 18 | endactionvalue; 19 | 20 | // ================================================================ 21 | // fa_debug_show_location 22 | // Shows module hierarchy and current cycle 23 | 24 | // Note: each invocation looks like this: 25 | // fa_debug_show_location; if (verbosity != 0) $display (""); 26 | 27 | // Why not define the function as: 28 | // function Action fa_debug_show_location (Integer verbosity, String location_s); 29 | // and just print the location as part of this function? 30 | 31 | // This is a workaround, because there's some bug in Verilog codegen 32 | // and/or Verilator, where that version core dumps. 33 | 34 | function Action fa_debug_show_location (Integer verbosity); 35 | action 36 | if (verbosity != 0) begin 37 | $write (" %0d: ", cur_cycle); 38 | end 39 | endaction 40 | endfunction 41 | 42 | // ================================================================ 43 | 44 | endpackage 45 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4_Lite/sysTest_Fabric.out.expected: -------------------------------------------------------------------------------- 1 | 1: M.rl_step0_wra 2 | AXI4L_Wr_Addr { awaddr: 'h00001000, awprot: 'h0, awuser: 'h0 } 3 | 2: M.rl_step2_wra 4 | AXI4L_Wr_Addr { awaddr: 'h00001004, awprot: 'h0, awuser: 'h0 } 5 | 2: M.rl_wr_data 6 | AXI4L_Wr_Data { wdata: 'h0000000000001000, wstrb: 'hff } 7 | 3: M.rl_step2_rda 8 | AXI4L_Rd_Addr { araddr: 'h00002000, arprot: 'h0, aruser: 'h0 } 9 | 3: M.rl_wr_data 10 | AXI4L_Wr_Data { wdata: 'h0000000000001004, wstrb: 'hff } 11 | 4: M.rl_step3_rda 12 | AXI4L_Rd_Addr { araddr: 'h00002004, arprot: 'h0, aruser: 'h0 } 13 | 5: M.rl_step4_rda 14 | AXI4L_Rd_Addr { araddr: 'h00030000, arprot: 'h0, aruser: 'h0 } 15 | 6: rl_S_IP_model_wr_addr 16 | AXI4L_Wr_Addr { awaddr: 'h00001000, awprot: 'h0, awuser: 'h0 } 17 | 6: rl_S_IP_model_wr_data 18 | AXI4L_Wr_Data { wdata: 'h0000000000001000, wstrb: 'hff } 19 | 7: rl_S_IP_model_wr_addr 20 | AXI4L_Wr_Addr { awaddr: 'h00001004, awprot: 'h0, awuser: 'h0 } 21 | 7: rl_S_IP_model_wr_data 22 | AXI4L_Wr_Data { wdata: 'h0000000000001004, wstrb: 'hff } 23 | 7: rl_S_IP_model_rd_addr 24 | AXI4L_Rd_Addr { araddr: 'h00002000, arprot: 'h0, aruser: 'h0 } 25 | 8: rl_S_IP_model_rd_addr 26 | AXI4L_Rd_Addr { araddr: 'h00002004, arprot: 'h0, aruser: 'h0 } 27 | 10: M.rl_wr_resps 28 | AXI4L_Wr_Resp { bresp: AXI4L_OKAY, buser: 'h0 } 29 | 11: M.rl_rd_resps 30 | AXI4L_Rd_Data { rresp: AXI4L_OKAY, rdata: 'h0000000000012000, ruser: 'h0 } 31 | 11: M.rl_wr_resps 32 | AXI4L_Wr_Resp { bresp: AXI4L_OKAY, buser: 'h0 } 33 | 12: M.rl_rd_resps 34 | AXI4L_Rd_Data { rresp: AXI4L_OKAY, rdata: 'h0000000000012004, ruser: 'h0 } 35 | 13: M.rl_rd_resps 36 | AXI4L_Rd_Data { rresp: AXI4L_DECERR, rdata: 'h0000000000000000, ruser: 'h0 } 37 | 114: rl_idle_quit 38 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM.defines: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | `define TLM_PRM_DCL numeric type id_size, \ 6 | numeric type addr_size, \ 7 | numeric type data_size, \ 8 | numeric type uint_size, \ 9 | type cstm_type 10 | 11 | `define TLM_PRM id_size, \ 12 | addr_size, \ 13 | data_size, \ 14 | uint_size, \ 15 | cstm_type 16 | 17 | `define TLM_PRM_STD 4, \ 18 | 32, \ 19 | 32, \ 20 | 10, \ 21 | Bit#(0) 22 | 23 | //////////////////////////////////////////////////////////////////////////////// 24 | /// 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | `define TLM_RR_DCL type req_t, \ 28 | type resp_t 29 | 30 | `define TLM_RR req_t, \ 31 | resp_t 32 | 33 | `define TLM_RR_STD TLMRequest#(`TLM_PRM_STD), \ 34 | TLMResponse#(`TLM_PRM_STD) \ 35 | 36 | //////////////////////////////////////////////////////////////////////////////// 37 | /// 38 | //////////////////////////////////////////////////////////////////////////////// 39 | 40 | `define TLM_XTR_DCL `TLM_RR_DCL, `TLM_PRM_DCL 41 | `define TLM_XTR `TLM_RR, `TLM_PRM 42 | `define TLM_XTR_STD `TLM_RR_STD, `TLM_PRM_STD 43 | 44 | //////////////////////////////////////////////////////////////////////////////// 45 | /// 46 | //////////////////////////////////////////////////////////////////////////////// 47 | 48 | `define TLM_TYPE_PRMS `TLM_PRM_DCL 49 | `define TLM_TYPES `TLM_PRM 50 | `define TLM_STD_TYPES `TLM_PRM_STD 51 | 52 | //////////////////////////////////////////////////////////////////////////////// 53 | /// 54 | //////////////////////////////////////////////////////////////////////////////// 55 | 56 | `define dv deriving(Bits,Eq) 57 | -------------------------------------------------------------------------------- /Libraries/FPGA/Xilinx/DIPSwitch.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package DIPSwitch; 6 | 7 | 8 | // This is a simple controller for using the DIP switches on 9 | // Xilinx evaluation boards. 10 | 11 | import Clocks :: *; 12 | 13 | // This is the interface for the FPGA boundary 14 | interface DIP#(numeric type n); 15 | (* always_ready, always_enabled *) 16 | method Action switch(Bit#(n) setting); 17 | endinterface 18 | 19 | // This is the full DIP switch interface 20 | interface DIPSwitch#(numeric type n); 21 | // Returns True for one cycle when the DIP switch settings change 22 | (* always_ready *) 23 | method Bool changed(); 24 | // The current DIP switch settings 25 | (* always_ready *) 26 | method Bit#(n) _read(); 27 | // The interface for connecting to the FPGA pins for the DIP switch 28 | (* prefix = "" *) 29 | interface DIP#(n) ifc; 30 | endinterface 31 | 32 | // This creates a controller for a single bank of n DIP switches 33 | module mkDIPSwitch#(Clock fpga_clk)(DIPSwitch#(n)); 34 | 35 | Clock clk <- exposeCurrentClock(); 36 | CrossingReg#(Bit#(n)) value <- mkNullCrossingReg(clk, 0, clocked_by fpga_clk, reset_by noReset); 37 | 38 | Reg#(Bit#(n)) prev_value <- mkReg(0); 39 | Reg#(UInt#(2)) init <- mkReg(3); 40 | 41 | rule do_init if (init != 0); 42 | init <= init - 1; 43 | endrule 44 | 45 | rule history; 46 | prev_value <= value.crossed(); 47 | endrule 48 | 49 | method Bool changed(); 50 | return (init == 1) || (prev_value != value.crossed()); 51 | endmethod 52 | 53 | method Bit#(n) _read = value.crossed(); 54 | 55 | interface DIP ifc; 56 | method Action switch(Bit#(n) setting); 57 | value <= setting; 58 | endmethod 59 | endinterface 60 | 61 | endmodule 62 | 63 | endpackage: DIPSwitch 64 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/Readable.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package Readable; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import Vector::*; 12 | 13 | //////////////////////////////////////////////////////////////////////////////// 14 | /// 15 | //////////////////////////////////////////////////////////////////////////////// 16 | 17 | typeclass Readable#(type a, type b); 18 | function a read(b value); 19 | endtypeclass 20 | 21 | instance Readable#(a, Reg#(a)); 22 | function a read(Reg#(a) ifc); 23 | return ifc._read; 24 | endfunction 25 | endinstance 26 | 27 | instance Readable#(Bool, PulseWire); 28 | function Bool read(PulseWire ifc); 29 | return ifc._read; 30 | endfunction 31 | endinstance 32 | 33 | instance Readable#(a, ReadOnly#(a)); 34 | function a read(ReadOnly#(a) ifc); 35 | return ifc._read; 36 | endfunction 37 | endinstance 38 | 39 | instance Readable#(Vector#(n, a), Vector#(n, b)) 40 | provisos(Readable#(a,b)); 41 | function Vector#(n, a) read(Vector#(n, b) value); 42 | return map(read,value); 43 | endfunction 44 | endinstance 45 | 46 | typeclass Writable#(type a, type b); 47 | function Action write(b ifc, a value); 48 | endtypeclass 49 | 50 | instance Writable#(a, Reg#(a)); 51 | function Action write(Reg#(a) ifc, a value); 52 | action 53 | ifc <= value; 54 | endaction 55 | endfunction 56 | endinstance 57 | 58 | instance Writable#(Vector#(n, a), Vector#(n, b)) 59 | provisos(Writable#(a,b)); 60 | function Action write(Vector#(n, b) ifc, Vector#(n, a) value); 61 | action 62 | joinActions(zipWith(write, ifc, value)); 63 | endaction 64 | endfunction 65 | endinstance 66 | 67 | endpackage 68 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/Test.bs: -------------------------------------------------------------------------------- 1 | package Test where 2 | 3 | import GenCRepr 4 | import TestFn 5 | import CShow 6 | import Vector 7 | import qualified ListN 8 | 9 | struct Foo = 10 | x :: UInt 8 11 | y :: Int 16 12 | z :: Bit 256 13 | 14 | struct Bar = 15 | b :: Bool 16 | bs :: Bit 13 17 | f :: Foo 18 | 19 | struct Baz = {} 20 | 21 | data Qux = QF Foo | QFB Foo Bar | Q | QI { x :: Int 8; y :: Int 8} | QU { u :: UInt 16 } 22 | 23 | data Kaz = Kaz (UInt 12) 24 | 25 | struct Tux = 26 | us :: ListN.ListN 8 (UInt 16) 27 | bs :: Vector 8 Bar 28 | qs :: Vector 11 Qux 29 | 30 | data Enum = E1 | E2 | E3 | E4 31 | 32 | struct Thing = 33 | w :: Vector 2 (Int 8) 34 | x :: UInt 8 35 | y :: UInt 8 36 | z :: Int 16 37 | 38 | struct ThingMsg = 39 | thing :: Thing 40 | swapXY :: Bool 41 | deltaZ :: Int 5 42 | 43 | actTestThing :: ThingMsg -> Action 44 | actTestThing tm = do 45 | $display (cshow tm) 46 | $display (cshow $ GenCRepr.packBytes tm) 47 | let input = GenCRepr.pack tm 48 | $display (cshow input) 49 | output <- test_fn input 50 | $display (cshow output) 51 | $display (cshow $ GenCRepr.toByteList output) 52 | let res = (GenCRepr.unpack output) :: Thing 53 | $display (cshow res) 54 | 55 | {-# verilog sysTest #-} 56 | sysTest :: Module Empty 57 | sysTest = module 58 | writeCDecls "test" (_ :: (Baz, Qux, Kaz, Tux, Enum, Maybe (Int 16), Maybe (Bit 32), Either Bool (Vector 3 (UInt 8)), ThingMsg)) 59 | 60 | rules 61 | when True ==> do 62 | $display (cshow $ GenCRepr.packBytes E1) 63 | $display (cshow $ GenCRepr.packBytes E2) 64 | $display (cshow $ GenCRepr.packBytes E3) 65 | $display (cshow $ GenCRepr.packBytes E4) 66 | actTestThing (ThingMsg {thing=Thing {w=1:>2:>nil; x=1; y=2; z=0x1234;}; swapXY=False; deltaZ=8;}) 67 | actTestThing (ThingMsg {thing=Thing {w=1:>2:>nil; x=1; y=2; z=0x1234;}; swapXY=True; deltaZ=negate 8;}) 68 | $finish 69 | -------------------------------------------------------------------------------- /Libraries/Misc/CreditCounter.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2015-2019 Bluespec, Inc., All Rights Reserved 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | // A "credit counter" which can be incremented and decremented 6 | // concurrently in the same clock (by using CRegs). 7 | // Author: Rishiyur S. Nikhil 8 | 9 | package CreditCounter; 10 | 11 | // ================================================================ 12 | // BSV library imports 13 | 14 | import Cur_Cycle :: *; 15 | 16 | // ================================================================ 17 | // Interface 18 | 19 | interface CreditCounter_IFC #(numeric type w); 20 | // Current value of internal count 21 | method UInt #(w) value; 22 | 23 | // Increment internal count 24 | method Action incr; 25 | 26 | // Decrement internal count 27 | method Action decr; 28 | 29 | // Clear internal count to 0 30 | method Action clear; 31 | endinterface 32 | 33 | // ================================================================ 34 | // Module implementation 35 | // Scheduling: value < incr < decr < clear 36 | 37 | module mkCreditCounter (CreditCounter_IFC #(w)); 38 | 39 | Reg #(UInt #(w)) crg [3] <- mkCReg (3, 0); 40 | 41 | method UInt #(w) value = crg [1]; 42 | 43 | method Action incr if (crg [0] != maxBound); 44 | if (crg [0] == maxBound) begin 45 | $display ("%0d: ERROR: CreditCounter: overflow", cur_cycle); 46 | $finish (1); // Assertion failure 47 | end 48 | crg [0] <= crg [0] + 1; 49 | endmethod 50 | 51 | method Action decr () if (crg [1] != 0); 52 | if (crg [1] == 0) begin 53 | $display ("%0d: ERROR: CreditCounter: underflow", cur_cycle); 54 | $finish (1); // Assertion failure 55 | end 56 | crg [1] <= crg [1] - 1; 57 | endmethod 58 | 59 | method Action clear; 60 | crg [2] <= 0; 61 | endmethod 62 | endmodule 63 | 64 | // ================================================================ 65 | 66 | endpackage 67 | -------------------------------------------------------------------------------- /testing/bsc.contrib/COBS/COBSTests.bs: -------------------------------------------------------------------------------- 1 | package COBSTests where 2 | 3 | import COBS 4 | import Vector 5 | import qualified List 6 | import GetPut 7 | import Connectable 8 | import CShow 9 | import FIFO 10 | 11 | msg :: (Add n p m) => Vector n (Bit 8) -> (UInt (TLog (TAdd m 1)), Vector m (Bit 8)) 12 | msg v = (fromInteger $ valueOf n, v `append` replicate 0) 13 | 14 | {-# verilog sysCOBSTests #-} 15 | sysCOBSTests :: Module Empty 16 | sysCOBSTests = module 17 | let testMsgs = 18 | msg (0x00 :> nil) :> 19 | msg (0x00 :> 0x00 :> nil) :> 20 | msg (0x11 :> 0x22 :> 0x00 :> 0x33 :> nil) :> 21 | msg (0x11 :> 0x22 :> 0x33 :> 0x44 :> nil) :> 22 | msg (0x11 :> 0x00 :> 0x00 :> 0x00 :> nil) :> 23 | msg (map (\ i -> fromInteger i + 1) (genVector :: Vector 254 Integer)) :> 24 | msg (map fromInteger (genVector :: Vector 255 Integer)) :> 25 | msg (map (\ i -> fromInteger i + 1) (genVector :: Vector 255 Integer)) :> 26 | msg (map (\ i -> fromInteger i + 2) (genVector :: Vector 255 Integer)) :> 27 | msg (map (\ i -> fromInteger i + 3) (genVector :: Vector 255 Integer)) :> 28 | msg (map fromInteger (genVector :: Vector 256 Integer)) :> 29 | nil 30 | let n = 11 31 | 32 | enc :: COBSEncoder 260 <- mkCOBSEncoder 33 | dec :: COBSDecoder 260 <- mkCOBSDecoder 34 | 35 | enc.byte <-> dec.byte 36 | 37 | i <- mkReg 0 38 | j <- mkReg 0 39 | expected :: FIFO (UInt 9, Vector 260 (Bit 8)) <- mkFIFO 40 | 41 | rules 42 | when i < n ==> do 43 | let m = select testMsgs i 44 | enc.msg.put m 45 | expected.enq m 46 | i := i + 1 47 | 48 | when True ==> do 49 | let m1 = expected.first 50 | m2 <- dec.msg.get 51 | if m1 == m2 52 | then $display "Pass %d" j 53 | else $display "Fail %d" j 54 | $display "Expected " (cshow m1) 55 | $display "Actual " (cshow m2) 56 | expected.deq 57 | j := j + 1 58 | 59 | when j >= n ==> $finish 60 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/ram_init.text: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 2 4 | 3 5 | 4 6 | 5 7 | 6 8 | 7 9 | 8 10 | 9 11 | A 12 | B 13 | C 14 | D 15 | E 16 | F 17 | 0 18 | 1 19 | 2 20 | 3 21 | 4 22 | 5 23 | 6 24 | 7 25 | 8 26 | 9 27 | A 28 | B 29 | C 30 | D 31 | E 32 | F 33 | 0 34 | 1 35 | 2 36 | 3 37 | 4 38 | 5 39 | 6 40 | 7 41 | 8 42 | 9 43 | A 44 | B 45 | C 46 | D 47 | E 48 | F 49 | 0 50 | 1 51 | 2 52 | 3 53 | 4 54 | 5 55 | 6 56 | 7 57 | 8 58 | 9 59 | A 60 | B 61 | C 62 | D 63 | E 64 | F 65 | 0 66 | 1 67 | 2 68 | 3 69 | 4 70 | 5 71 | 6 72 | 7 73 | 8 74 | 9 75 | A 76 | B 77 | C 78 | D 79 | E 80 | F 81 | 0 82 | 1 83 | 2 84 | 3 85 | 4 86 | 5 87 | 6 88 | 7 89 | 8 90 | 9 91 | A 92 | B 93 | C 94 | D 95 | E 96 | F 97 | 0 98 | 1 99 | 2 100 | 3 101 | 4 102 | 5 103 | 6 104 | 7 105 | 8 106 | 9 107 | A 108 | B 109 | C 110 | D 111 | E 112 | F 113 | 0 114 | 1 115 | 2 116 | 3 117 | 4 118 | 5 119 | 6 120 | 7 121 | 8 122 | 9 123 | A 124 | B 125 | C 126 | D 127 | E 128 | F 129 | 0 130 | 1 131 | 2 132 | 3 133 | 4 134 | 5 135 | 6 136 | 7 137 | 8 138 | 9 139 | A 140 | B 141 | C 142 | D 143 | E 144 | F 145 | 0 146 | 1 147 | 2 148 | 3 149 | 4 150 | 5 151 | 6 152 | 7 153 | 8 154 | 9 155 | A 156 | B 157 | C 158 | D 159 | E 160 | F 161 | 0 162 | 1 163 | 2 164 | 3 165 | 4 166 | 5 167 | 6 168 | 7 169 | 8 170 | 9 171 | A 172 | B 173 | C 174 | D 175 | E 176 | F 177 | 0 178 | 1 179 | 2 180 | 3 181 | 4 182 | 5 183 | 6 184 | 7 185 | 8 186 | 9 187 | A 188 | B 189 | C 190 | D 191 | E 192 | F 193 | 0 194 | 1 195 | 2 196 | 3 197 | 4 198 | 5 199 | 6 200 | 7 201 | 8 202 | 9 203 | A 204 | B 205 | C 206 | D 207 | E 208 | F 209 | 0 210 | 1 211 | 2 212 | 3 213 | 4 214 | 5 215 | 6 216 | 7 217 | 8 218 | 9 219 | A 220 | B 221 | C 222 | D 223 | E 224 | F 225 | 0 226 | 1 227 | 2 228 | 3 229 | 4 230 | 5 231 | 6 232 | 7 233 | 8 234 | 9 235 | A 236 | B 237 | C 238 | D 239 | E 240 | F 241 | 0 242 | 1 243 | 2 244 | 3 245 | 4 246 | 5 247 | 6 248 | 7 249 | 8 250 | 9 251 | A 252 | B 253 | C 254 | D 255 | E 256 | F 257 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/ram_init.text: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 2 4 | 3 5 | 4 6 | 5 7 | 6 8 | 7 9 | 8 10 | 9 11 | A 12 | B 13 | C 14 | D 15 | E 16 | F 17 | 0 18 | 1 19 | 2 20 | 3 21 | 4 22 | 5 23 | 6 24 | 7 25 | 8 26 | 9 27 | A 28 | B 29 | C 30 | D 31 | E 32 | F 33 | 0 34 | 1 35 | 2 36 | 3 37 | 4 38 | 5 39 | 6 40 | 7 41 | 8 42 | 9 43 | A 44 | B 45 | C 46 | D 47 | E 48 | F 49 | 0 50 | 1 51 | 2 52 | 3 53 | 4 54 | 5 55 | 6 56 | 7 57 | 8 58 | 9 59 | A 60 | B 61 | C 62 | D 63 | E 64 | F 65 | 0 66 | 1 67 | 2 68 | 3 69 | 4 70 | 5 71 | 6 72 | 7 73 | 8 74 | 9 75 | A 76 | B 77 | C 78 | D 79 | E 80 | F 81 | 0 82 | 1 83 | 2 84 | 3 85 | 4 86 | 5 87 | 6 88 | 7 89 | 8 90 | 9 91 | A 92 | B 93 | C 94 | D 95 | E 96 | F 97 | 0 98 | 1 99 | 2 100 | 3 101 | 4 102 | 5 103 | 6 104 | 7 105 | 8 106 | 9 107 | A 108 | B 109 | C 110 | D 111 | E 112 | F 113 | 0 114 | 1 115 | 2 116 | 3 117 | 4 118 | 5 119 | 6 120 | 7 121 | 8 122 | 9 123 | A 124 | B 125 | C 126 | D 127 | E 128 | F 129 | 0 130 | 1 131 | 2 132 | 3 133 | 4 134 | 5 135 | 6 136 | 7 137 | 8 138 | 9 139 | A 140 | B 141 | C 142 | D 143 | E 144 | F 145 | 0 146 | 1 147 | 2 148 | 3 149 | 4 150 | 5 151 | 6 152 | 7 153 | 8 154 | 9 155 | A 156 | B 157 | C 158 | D 159 | E 160 | F 161 | 0 162 | 1 163 | 2 164 | 3 165 | 4 166 | 5 167 | 6 168 | 7 169 | 8 170 | 9 171 | A 172 | B 173 | C 174 | D 175 | E 176 | F 177 | 0 178 | 1 179 | 2 180 | 3 181 | 4 182 | 5 183 | 6 184 | 7 185 | 8 186 | 9 187 | A 188 | B 189 | C 190 | D 191 | E 192 | F 193 | 0 194 | 1 195 | 2 196 | 3 197 | 4 198 | 5 199 | 6 200 | 7 201 | 8 202 | 9 203 | A 204 | B 205 | C 206 | D 207 | E 208 | F 209 | 0 210 | 1 211 | 2 212 | 3 213 | 4 214 | 5 215 | 6 216 | 7 217 | 8 218 | 9 219 | A 220 | B 221 | C 222 | D 223 | E 224 | F 225 | 0 226 | 1 227 | 2 228 | 3 229 | 4 230 | 5 231 | 6 232 | 7 233 | 8 234 | 9 235 | A 236 | B 237 | C 238 | D 239 | E 240 | F 241 | 0 242 | 1 243 | 2 244 | 3 245 | 4 246 | 5 247 | 6 248 | 7 249 | 8 250 | 9 251 | A 252 | B 253 | C 254 | D 255 | E 256 | F 257 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/ram_init.text: -------------------------------------------------------------------------------- 1 | 0 2 | 1 3 | 2 4 | 3 5 | 4 6 | 5 7 | 6 8 | 7 9 | 8 10 | 9 11 | A 12 | B 13 | C 14 | D 15 | E 16 | F 17 | 0 18 | 1 19 | 2 20 | 3 21 | 4 22 | 5 23 | 6 24 | 7 25 | 8 26 | 9 27 | A 28 | B 29 | C 30 | D 31 | E 32 | F 33 | 0 34 | 1 35 | 2 36 | 3 37 | 4 38 | 5 39 | 6 40 | 7 41 | 8 42 | 9 43 | A 44 | B 45 | C 46 | D 47 | E 48 | F 49 | 0 50 | 1 51 | 2 52 | 3 53 | 4 54 | 5 55 | 6 56 | 7 57 | 8 58 | 9 59 | A 60 | B 61 | C 62 | D 63 | E 64 | F 65 | 0 66 | 1 67 | 2 68 | 3 69 | 4 70 | 5 71 | 6 72 | 7 73 | 8 74 | 9 75 | A 76 | B 77 | C 78 | D 79 | E 80 | F 81 | 0 82 | 1 83 | 2 84 | 3 85 | 4 86 | 5 87 | 6 88 | 7 89 | 8 90 | 9 91 | A 92 | B 93 | C 94 | D 95 | E 96 | F 97 | 0 98 | 1 99 | 2 100 | 3 101 | 4 102 | 5 103 | 6 104 | 7 105 | 8 106 | 9 107 | A 108 | B 109 | C 110 | D 111 | E 112 | F 113 | 0 114 | 1 115 | 2 116 | 3 117 | 4 118 | 5 119 | 6 120 | 7 121 | 8 122 | 9 123 | A 124 | B 125 | C 126 | D 127 | E 128 | F 129 | 0 130 | 1 131 | 2 132 | 3 133 | 4 134 | 5 135 | 6 136 | 7 137 | 8 138 | 9 139 | A 140 | B 141 | C 142 | D 143 | E 144 | F 145 | 0 146 | 1 147 | 2 148 | 3 149 | 4 150 | 5 151 | 6 152 | 7 153 | 8 154 | 9 155 | A 156 | B 157 | C 158 | D 159 | E 160 | F 161 | 0 162 | 1 163 | 2 164 | 3 165 | 4 166 | 5 167 | 6 168 | 7 169 | 8 170 | 9 171 | A 172 | B 173 | C 174 | D 175 | E 176 | F 177 | 0 178 | 1 179 | 2 180 | 3 181 | 4 182 | 5 183 | 6 184 | 7 185 | 8 186 | 9 187 | A 188 | B 189 | C 190 | D 191 | E 192 | F 193 | 0 194 | 1 195 | 2 196 | 3 197 | 4 198 | 5 199 | 6 200 | 7 201 | 8 202 | 9 203 | A 204 | B 205 | C 206 | D 207 | E 208 | F 209 | 0 210 | 1 211 | 2 212 | 3 213 | 4 214 | 5 215 | 6 216 | 7 217 | 8 218 | 9 219 | A 220 | B 221 | C 222 | D 223 | E 224 | F 225 | 0 226 | 1 227 | 2 228 | 3 229 | 4 230 | 5 231 | 6 232 | 7 233 | 8 234 | 9 235 | A 236 | B 237 | C 238 | D 239 | E 240 | F 241 | 0 242 | 1 243 | 2 244 | 3 245 | 4 246 | 5 247 | 6 248 | 7 249 | 8 250 | 9 251 | A 252 | B 253 | C 254 | D 255 | E 256 | F 257 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/DMAConfigRegs.bsv: -------------------------------------------------------------------------------- 1 | package DMAConfigRegs; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import CBus::*; 8 | import DMADefines::*; 9 | import Vector::*; 10 | 11 | //////////////////////////////////////////////////////////////////////////////// 12 | /// 13 | //////////////////////////////////////////////////////////////////////////////// 14 | 15 | interface ConfigRegs; 16 | interface Reg#(Bit#(8)) status; 17 | interface Vector#(NumChannels, Reg#(Bit#(1))) active; 18 | interface Vector#(NumChannels, Reg#(Bit#(32))) descriptor; 19 | endinterface 20 | 21 | //////////////////////////////////////////////////////////////////////////////// 22 | /// 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | (* synthesize *) 26 | module [Module] mkDMAConfigRegs(IWithCBus#(DCBus, ConfigRegs)); 27 | let ifc <- exposeCBusIFC(mkDMAConfigRegsInternal); 28 | return ifc; 29 | endmodule 30 | 31 | module [DModWithCBus] mkDMAConfigRegsInternal (ConfigRegs); 32 | 33 | let icount = valueOf(NumChannels); 34 | 35 | Vector#(NumChannels, Reg#(Bit#(32))) desc_vector = newVector; 36 | Vector#(NumChannels, Reg#(Bit#(1))) active_vector = newVector; 37 | 38 | for (Integer i = 0; i < icount; i = i + 1) 39 | begin 40 | 41 | let delta = DCAddr { a: (fromInteger(i) * 12'h020), o: 0}; 42 | let descriptorAddr = descriptorAddrBase + delta; 43 | let activeAddr = activeAddrBase + delta; 44 | desc_vector[i] <- mkCBRegRW(descriptorAddr, 0); 45 | active_vector[i] <- mkCBRegRW(activeAddr, 0); 46 | end 47 | 48 | Reg#(Bit#(8)) reg_status <- mkCBRegRW(statusAddr, 0); 49 | 50 | interface Reg status = reg_status; 51 | interface descriptor = desc_vector; 52 | interface active = active_vector; 53 | 54 | endmodule 55 | 56 | 57 | //////////////////////////////////////////////////////////////////////////////// 58 | /// 59 | //////////////////////////////////////////////////////////////////////////////// 60 | 61 | endpackage 62 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/AXI4_Stream/README_AXI4S.adoc: -------------------------------------------------------------------------------- 1 | = About `bsc-contrib/Libraries/AMBA_Fabrics/AXI4_Stream` 2 | :revnumber: v1.00 3 | :revdate: 2024-12-07 4 | :sectnums: 5 | :imagesdir: ../Doc/Figs 6 | :toc: 7 | :toclevels: 3 8 | :toc-title: Contents 9 | :keywords: Bluespec, B-Lang, BSV, BH, AMBA, ARM AXI, AXI4, AXI4-Lite, AXI4-Stream 10 | 11 | // ================================================================ 12 | 13 | Copyright (C) 2017-2023 Bluespec, Inc. All Rights Reserved + 14 | Copyright (C) 2024-2025 B-Lang.org. All Rights Reserved 15 | 16 | SPDX-License-Identifier: BSD-3-Clause 17 | 18 | // ================================================================ 19 | 20 | Pleae see README in parent directory 21 | (link:../README_AMBA_Fabrics.adoc[adoc],link:../README_AMBA_Fabrics.html[html]) 22 | for general introduction and about compiling/building/testing. 23 | 24 | This directory describes AXI4-Stream facilities. 25 | 26 | These source codes may import other `bsv-contrib` libraries; be sure 27 | they are visible in your _bsc_ compiler paths: 28 | 29 | bsc-contrib/Libraries/AMBA_Fabrics/Utils/ 30 | bsc-contrib/Libraries/Misc/ 31 | 32 | // ================================================================ 33 | 34 | image::IMG_Under_Construction.png[align="left", width=100] 35 | 36 | The packages in this directory can be used as-is, but are expected to 37 | be restructured to be more like their AXI4 siblings (more consistent 38 | naming, clean separation of B-Lang-style and RTL-style, etc.) 39 | 40 | This documentation will be updated after that restructuring. 41 | 42 | // ================================================================ 43 | == `AXI4_Stream.bsv` 44 | 45 | (... To be written ...) 46 | 47 | // ================================================================ 48 | == Unit tests 49 | 50 | Unit tests will be found in: 51 | 52 | bsc-contrib/testing/bsc.contrib/AMBA_Fabrics/AXI4_Stream/Test_*.bsv 53 | 54 | The conventions for unit tests are described in more detail in the 55 | README in the parent directory 56 | (link:../README_AMBA_Fabrics.adoc[adoc],link:../README_AMBA_Fabrics.html[html]). 57 | 58 | // ================================================================ 59 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 |
2 | 3 | # Bluespec Compiler - Contributed libraries and utilities 4 | 5 | --- 6 | 7 |
8 | 9 | This is a place to share libraries and utilities that don't belong 10 | (or don't yet belong) in the core [bsc repository]. 11 | 12 | Files can be installed in the same way as in the [bsc repository]: 13 | 14 | $ make PREFIX=/tools/bluespec 15 | 16 | If the `PREFIX` variable is not specified, the default is `inst`. 17 | 18 | Each set of libraries is installed into its own subdirectory, so that 19 | they are not in the path by default, but instead are only available 20 | when explicitly added on the command line: 21 | 22 | $ bsc -p +:%/Libraries/FPGA/Xilinx/ 23 | 24 | Until a more sophisicated library system is available, this repository 25 | can be used for sharing useful code. Contributions are welcome. 26 | No guarantees are made about the quality of this code. 27 | Tests for some libraries can be found in the `testing` directory. 28 | 29 | --- 30 | 31 | ## Testing 32 | 33 | The directory `testing/bsc.contrib` contains tests that can be run 34 | using the testing infrastructure of the [bsc repository]. 35 | Simply copy the directory to a clone of that repo, set 36 | `BSCCONTRIBDIR` in the environment to point to the installation 37 | to be tested, and run the testsuite as usual: 38 | 39 | $ cp -r testing/bsc.contrib /path/to/bsc/testsuite/ 40 | $ cd /path/to/bsc/testsuite/bsc.contrib/ 41 | $ export BSCCONTRIBDIR=/path/to/bsc-contrib/inst 42 | $ make check 43 | 44 | 45 | [bsc repository]: https://github.com/B-Lang-org/bsc 46 | [bsc-testsuite]: https://github.com/B-Lang-org/bsc-testsuite 47 | [Bluespec Inc]: https://bluespec.com 48 | 49 | --- 50 | 51 | ## License 52 | 53 | Individual contributions are responsible for specifying their own 54 | copyright and license. Libraries provided by [Bluespec Inc] have a 55 | header comment that states the copyright and the license as an SPDX 56 | short identifier (BSD-3-Clause) with the full license text given in 57 | the `LICENSES` directory. 58 | 59 | --- 60 | 61 | ## Contributing 62 | 63 | Please see the following document in the `doc` directory for advice on 64 | how to contribute new libraries to this repository. 65 | 66 | [How to Contribute](doc/How_to_Contribute.adoc) 67 | 68 | --- 69 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AMBA_Fabrics/AXI4/sysTest_AXI4_Deburster.out.expected: -------------------------------------------------------------------------------- 1 | 1: M.rl_rd_burst_addr_0 2 | AXI4_AR { arid: 'h1, araddr: 'h00001000, arlen: 'h01, arsize: 'h3, arburst: 'h1, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 3 | 2: M.rl_rd_burst_addr_1 4 | AXI4_AR { arid: 'h1, araddr: 'h00002000, arlen: 'h03, arsize: 'h3, arburst: 'h1, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 5 | 3: S.rl_S_IP_model_AR 6 | AXI4_AR { arid: 'h1, araddr: 'h00001000, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 7 | 4: S.rl_S_IP_model_AR 8 | AXI4_AR { arid: 'h1, araddr: 'h00001008, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 9 | 5: S.rl_S_IP_model_AR 10 | AXI4_AR { arid: 'h1, araddr: 'h00002000, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 11 | 5: M.rl_rd_resps 12 | AXI4_R { rid: 'h1, rdata: 'h0000000000011000, rresp: 'h0, rlast: False, ruser: 'h001 } 13 | 6: S.rl_S_IP_model_AR 14 | AXI4_AR { arid: 'h1, araddr: 'h00002008, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 15 | 6: M.rl_rd_resps 16 | AXI4_R { rid: 'h1, rdata: 'h0000000000011008, rresp: 'h0, rlast: True, ruser: 'h001 } 17 | 7: S.rl_S_IP_model_AR 18 | AXI4_AR { arid: 'h1, araddr: 'h00002010, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 19 | 7: M.rl_rd_resps 20 | AXI4_R { rid: 'h1, rdata: 'h0000000000012000, rresp: 'h0, rlast: False, ruser: 'h001 } 21 | 8: S.rl_S_IP_model_AR 22 | AXI4_AR { arid: 'h1, araddr: 'h00002018, arlen: 'h00, arsize: 'h3, arburst: 'h0, arlock: 'h0, arcache: 'h0, arprot: 'h0, arqos: 'h0, arregion: 'h0, aruser: 'h001 } 23 | 8: M.rl_rd_resps 24 | AXI4_R { rid: 'h1, rdata: 'h0000000000012008, rresp: 'h0, rlast: False, ruser: 'h001 } 25 | 9: M.rl_rd_resps 26 | AXI4_R { rid: 'h1, rdata: 'h0000000000012010, rresp: 'h0, rlast: False, ruser: 'h001 } 27 | 10: M.rl_rd_resps 28 | AXI4_R { rid: 'h1, rdata: 'h0000000000012018, rresp: 'h0, rlast: True, ruser: 'h001 } 29 | 111: rl_idle_quit 30 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/AXI4_Lite/AXI4L_ClockCrossing.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2022 Bluespec, Inc. All Rights Reserved 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AXI4L_ClockCrossing; 6 | 7 | import Clocks ::*; 8 | import Connectable ::*; 9 | import Semi_FIFOF ::*; 10 | import GetPut ::*; 11 | 12 | import AXI4L_Types ::*; 13 | import AXI4L_Xactors ::*; 14 | 15 | // ================================================================ 16 | 17 | interface AXI4L_ClockCrossing_IFC #( 18 | numeric type addr_, 19 | numeric type data_, 20 | numeric type user_); 21 | interface AXI4L_S_IFC #(addr_, data_, user_) from_M; 22 | interface AXI4L_M_IFC #(addr_, data_, user_) to_S; 23 | endinterface 24 | 25 | // ================================================================ 26 | 27 | module mkAXI4L_ClockCrossing #(Clock clock_M, 28 | Reset reset_M, 29 | Clock clock_S, 30 | Reset reset_S) 31 | (AXI4L_ClockCrossing_IFC #(addr_, data_, user_)); 32 | 33 | SyncFIFOIfc #(AXI4L_Wr_Addr #(addr_, user_)) 34 | f_aw <- mkSyncFIFO (4, clock_M, reset_M, clock_S); 35 | 36 | SyncFIFOIfc #(AXI4L_Wr_Data #(data_)) 37 | f_w <- mkSyncFIFO (4, clock_M, reset_M, clock_S); 38 | 39 | SyncFIFOIfc #(AXI4L_Wr_Resp #(user_)) 40 | f_b <- mkSyncFIFO (4, clock_S, reset_S, clock_M); 41 | 42 | SyncFIFOIfc #(AXI4L_Rd_Addr #(addr_, user_)) 43 | f_ar <- mkSyncFIFO (4, clock_M, reset_M, clock_S); 44 | 45 | SyncFIFOIfc #(AXI4L_Rd_Data #(data_, user_)) 46 | f_r <- mkSyncFIFO (4, clock_S, reset_S, clock_M); 47 | 48 | AXI4L_S_IFC #(addr_, data_, user_) 49 | s_xactor <- mkAXI4L_Xactor_S_3 (f_aw, f_w, f_b, f_ar, f_r, 50 | clocked_by clock_M, 51 | reset_by reset_M); 52 | 53 | AXI4L_M_IFC #(addr_, data_, user_) 54 | m_xactor <- mkAXI4L_Xactor_M_3 (f_aw, f_w, f_b, f_ar, f_r, 55 | clocked_by clock_S, 56 | reset_by reset_S); 57 | 58 | interface AXI4L_S_IFC from_M = s_xactor; 59 | interface AXI4L_M_IFC to_S = m_xactor; 60 | endmodule 61 | 62 | module mkAXI4L_ClockCrossingToCC #(Clock clock_M, Reset reset_M) 63 | (AXI4L_ClockCrossing_IFC #(addr_, data_, user_)); 64 | let clock_S <- exposeCurrentClock; 65 | let reset_S <- exposeCurrentReset; 66 | let crossing <- mkAXI4L_ClockCrossing (clock_M, reset_M, clock_S, reset_S); 67 | 68 | return crossing; 69 | endmodule 70 | 71 | endpackage 72 | -------------------------------------------------------------------------------- /Libraries/Bus/BusDefines.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package BusDefines; 6 | 7 | import Arbiter::*; 8 | import Connectable::*; 9 | import FIFO::*; 10 | 11 | //////////////////////////////////////////////////////////////////////////////// 12 | /// 13 | //////////////////////////////////////////////////////////////////////////////// 14 | 15 | interface BusSender#(type a); 16 | interface FIFO#(a) in; 17 | interface BusSend#(a) out; 18 | endinterface 19 | 20 | interface BusReceiver#(type a); 21 | interface BusRecv#(a) in; 22 | interface FIFO#(a) out; 23 | endinterface 24 | 25 | (* always_ready, always_enabled *) 26 | interface BusSend#(type a); 27 | method a data; 28 | method Bool valid; 29 | method Action ready(Bool value); 30 | endinterface 31 | 32 | (* always_ready, always_enabled *) 33 | interface BusRecv#(type a); 34 | method Action data(a value); 35 | method Action valid(Bool value); 36 | method Bool ready; 37 | endinterface 38 | 39 | //////////////////////////////////////////////////////////////////////////////// 40 | /// 41 | //////////////////////////////////////////////////////////////////////////////// 42 | 43 | instance Connectable#( BusSend#(td), BusRecv#(td) ); 44 | module mkConnection#( BusSend#(td) m, BusRecv#(td) s )(Empty); 45 | (* fire_when_enabled, no_implicit_conditions *) 46 | rule connect1; s.data( m.data() ) ; endrule 47 | rule connect2; s.valid( m.valid() ) ; endrule 48 | rule connect3; m.ready( s.ready() ) ; endrule 49 | endmodule 50 | endinstance 51 | 52 | //////////////////////////////////////////////////////////////////////////////// 53 | /// 54 | //////////////////////////////////////////////////////////////////////////////// 55 | 56 | typeclass BusPayload#(type a, type b) dependencies(a determines b); 57 | function Bool isLast (a payload); 58 | function b getId(a payload); 59 | function a setId(a payload, b id); 60 | endtypeclass 61 | 62 | 63 | instance Arbitable#(BusSend#(a)); 64 | module mkArbiterRequest#(BusSend#(a) bus_send) (ArbiterRequest_IFC); 65 | 66 | method Bool request; 67 | return bus_send.valid; 68 | endmethod 69 | method Bool lock; 70 | return False; 71 | endmethod 72 | method Action grant; 73 | // a noop 74 | endmethod 75 | 76 | endmodule 77 | endinstance 78 | 79 | 80 | endpackage 81 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM2Utils.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM2Utils; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import BUtils::*; 12 | import DefaultValue::*; 13 | import TLM2Defines::*; 14 | import Vector::*; 15 | 16 | `include "TLM.defines" 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | function RequestDescriptor#(`TLM_PRM) createBasicRequestDescriptor() 23 | provisos(DefaultValue#(RequestDescriptor#(`TLM_PRM))); 24 | return defaultValue; 25 | endfunction 26 | 27 | /* -----\/----- EXCLUDED -----\/----- 28 | function TLMResponse#(`TLM_PRM) createTLMResponse(TLMId#(`TLM_PRM) id, TLMStatus status) 29 | provisos(Bits#(TLMResponse#(`TLM_PRM), s0)); 30 | TLMResponse#(`TLM_PRM) response = unpack(0); 31 | response.status = status; 32 | response.transaction_id = id; 33 | return response; 34 | endfunction 35 | -----/\----- EXCLUDED -----/\----- */ 36 | 37 | function TLMResponse#(`TLM_PRM) createBasicTLMResponse () 38 | provisos(DefaultValue#(TLMResponse#(`TLM_PRM))); 39 | return defaultValue; 40 | endfunction 41 | 42 | //////////////////////////////////////////////////////////////////////////////// 43 | /// 44 | //////////////////////////////////////////////////////////////////////////////// 45 | 46 | 47 | function TLMData#(`TLM_PRM) createTLMBitMask (TLMByteEn#(`TLM_PRM) enable_bits); 48 | 49 | 50 | Vector#(TDiv#(data_size, 8),Bit#(1)) enable = unpack(enable_bits); 51 | Vector#(TDiv#(data_size, 8),Bit#(8)) mask = map(signExtend, enable); 52 | 53 | return cExtend(mask); 54 | 55 | endfunction 56 | 57 | function TLMData#(`TLM_PRM) maskTLMData(TLMByteEn#(`TLM_PRM) byte_enable, TLMData#(`TLM_PRM) data); 58 | 59 | TLMData#(`TLM_PRM) mask = createTLMBitMask(byte_enable); 60 | 61 | return mask & data; 62 | 63 | endfunction 64 | 65 | function TLMData#(`TLM_PRM) overwriteTLMData(TLMByteEn#(`TLM_PRM) byte_enable, TLMData#(`TLM_PRM) data_orig, TLMData#(`TLM_PRM) data); 66 | 67 | TLMData#(`TLM_PRM) mask = createTLMBitMask(byte_enable); 68 | 69 | return (~mask & data_orig) | (mask & data); 70 | 71 | endfunction 72 | 73 | endpackage 74 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/AxiReadBus.bsv: -------------------------------------------------------------------------------- 1 | package AxiReadBus; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import Axi::*; 8 | import Connectable::*; 9 | import TLM2::*; 10 | import Vector::*; 11 | 12 | `include "Axi.defines" 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | (* synthesize *) 19 | module sysAxiReadBus (); 20 | 21 | Reg#(Bit#(16)) count <- mkReg(0); 22 | 23 | function Bool addrMatch0(AxiAddr#(`TLM_PRM) a); 24 | return (a[12] == 0); 25 | endfunction 26 | 27 | function Bool addrMatch1(AxiAddr#(`TLM_PRM) a); 28 | return (a[12] == 1); 29 | endfunction 30 | 31 | TLMSendIFC#(`AXI_RR_STD) source_0 <- mkTLMSource(tagged Valid READ, True); 32 | TLMSendIFC#(`AXI_RR_STD) source_1 <- mkTLMSource(tagged Valid READ, True); 33 | 34 | AxiRdMasterXActorIFC#(`AXI_XTR_STD) master_0 <- mkAxiRdMasterStd; 35 | AxiRdMasterXActorIFC#(`AXI_XTR_STD) master_1 <- mkAxiRdMasterStd; 36 | 37 | AxiRdSlaveXActorIFC#(`AXI_XTR_STD) slave_0 <- mkAxiRdSlaveStd(addrMatch0); 38 | AxiRdSlaveXActorIFC#(`AXI_XTR_STD) slave_1 <- mkAxiRdSlaveStd(addrMatch1); 39 | 40 | TLMRecvIFC#(`AXI_RR_STD) mem_0 <- mkTLMRam(0, True); 41 | TLMRecvIFC#(`AXI_RR_STD) mem_1 <- mkTLMRam(1, True); 42 | 43 | mkConnection(source_0, master_0.tlm); 44 | mkConnection(source_1, master_1.tlm); 45 | 46 | Vector#(2, AxiRdFabricMaster#(`AXI_PRM_STD)) masters = newVector; 47 | Vector#(2, AxiRdFabricSlave#(`AXI_PRM_STD)) slaves = newVector; 48 | 49 | masters[0] = master_0.fabric; 50 | masters[1] = master_1.fabric; 51 | slaves[0] = slave_0.fabric; 52 | slaves[1] = slave_1.fabric; 53 | 54 | mkAxiRdBus(masters, slaves); 55 | 56 | mkConnection(slave_0.tlm, mem_0); 57 | mkConnection(slave_1.tlm, mem_1); 58 | 59 | /* -----\/----- EXCLUDED -----\/----- 60 | let monitor_m0 <- mkMonitor(master_0.fabric.bus); 61 | let monitor_m1 <- mkMonitor(master_1.fabric.bus); 62 | let monitor_s0 <- mkMonitor(slave_0.fabric.bus); 63 | let monitor_s1 <- mkMonitor(slave_1.fabric.bus); 64 | -----/\----- EXCLUDED -----/\----- */ 65 | 66 | rule every; 67 | count <= count + 1; 68 | if (count == 500) $finish; 69 | endrule 70 | 71 | endmodule 72 | 73 | endpackage 74 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/AxiWriteBus.bsv: -------------------------------------------------------------------------------- 1 | package AxiWriteBus; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import Axi::*; 8 | import Connectable::*; 9 | import TLM2::*; 10 | import Vector::*; 11 | 12 | `include "Axi.defines" 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// 16 | //////////////////////////////////////////////////////////////////////////////// 17 | 18 | (* synthesize *) 19 | module sysAxiWriteBus (); 20 | 21 | Reg#(Bit#(16)) count <- mkReg(0); 22 | 23 | function Bool addrMatch0(AxiAddr#(`TLM_PRM) a); 24 | return (a[12] == 0); 25 | endfunction 26 | 27 | function Bool addrMatch1(AxiAddr#(`TLM_PRM) a); 28 | return (a[12] == 1); 29 | endfunction 30 | 31 | TLMSendIFC#(`AXI_RR_STD) source_0 <- mkTLMSource(tagged Valid WRITE, True); 32 | TLMSendIFC#(`AXI_RR_STD) source_1 <- mkTLMSource(tagged Valid WRITE, True); 33 | 34 | AxiWrMasterXActorIFC#(`AXI_XTR_STD) master_0 <- mkAxiWrMasterStd; 35 | AxiWrMasterXActorIFC#(`AXI_XTR_STD) master_1 <- mkAxiWrMasterStd; 36 | 37 | AxiWrSlaveXActorIFC#(`AXI_XTR_STD) slave_0 <- mkAxiWrSlaveStd(addrMatch0); 38 | AxiWrSlaveXActorIFC#(`AXI_XTR_STD) slave_1 <- mkAxiWrSlaveStd(addrMatch1); 39 | 40 | TLMRecvIFC#(`AXI_RR_STD) mem_0 <- mkTLMRam(0, True); 41 | TLMRecvIFC#(`AXI_RR_STD) mem_1 <- mkTLMRam(1, True); 42 | 43 | mkConnection(source_0, master_0.tlm); 44 | mkConnection(source_1, master_1.tlm); 45 | 46 | Vector#(2, AxiWrFabricMaster#(`AXI_PRM_STD)) masters = newVector; 47 | Vector#(2, AxiWrFabricSlave#(`AXI_PRM_STD)) slaves = newVector; 48 | 49 | masters[0] = master_0.fabric; 50 | masters[1] = master_1.fabric; 51 | slaves[0] = slave_0.fabric; 52 | slaves[1] = slave_1.fabric; 53 | 54 | mkAxiWrBus(masters, slaves); 55 | 56 | mkConnection(slave_0.tlm, mem_0); 57 | mkConnection(slave_1.tlm, mem_1); 58 | 59 | /* -----\/----- EXCLUDED -----\/----- 60 | let monitor_m0 <- mkMonitor(master_0.fabric.bus); 61 | let monitor_m1 <- mkMonitor(master_1.fabric.bus); 62 | let monitor_s0 <- mkMonitor(slave_0.fabric.bus); 63 | let monitor_s1 <- mkMonitor(slave_1.fabric.bus); 64 | -----/\----- EXCLUDED -----/\----- */ 65 | 66 | rule every; 67 | count <= count + 1; 68 | if (count == 500) $finish; 69 | endrule 70 | 71 | endmodule 72 | 73 | endpackage 74 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/CounterB2C.bs: -------------------------------------------------------------------------------- 1 | package CounterB2C where 2 | 3 | import GenCRepr 4 | import GenCMsg 5 | import CounterIface 6 | import CShow 7 | import Vector 8 | import GetPut 9 | 10 | -- Note that changing the message data definitions in this file may affect the 11 | -- packed message sizes as determined by the GenCMsg type class. 12 | -- These unfourtunately must be hardcoded in CounterIface.bsv as well, so any 13 | -- change to these types that affects the packed message sizes must be reflected 14 | -- in that file as well. 15 | 16 | type Id = Bit 16 -- Try changing the size 17 | 18 | -- Try adding/reordering constructors 19 | data Command = Num { id :: Id; val :: Int 16; } 20 | | Reset (Int 16) 21 | | Halt 22 | deriving (Bits) 23 | 24 | struct Result a = 25 | id :: Id 26 | val :: a 27 | deriving (Bits) 28 | 29 | interface CounterMsgs = 30 | -- In order of highest to lowest urgency 31 | -- Try changing the order and FIFO sizes 32 | commands :: Rx 128 16 Command 33 | sums :: Tx 128 2 (Result (Int 16)) 34 | products :: Tx 128 2 (Result (Int 32)) 35 | 36 | {-# verilog sysCounterB2C #-} 37 | sysCounterB2C :: Module Empty 38 | sysCounterB2C = module 39 | writeCMsgDecls "counter" (_ :: CounterMsgs) 40 | 41 | msgMgr <- mkMsgManager 42 | let msgs :: CounterMsgs = msgMgr.fifos 43 | 44 | sum :: Reg (Int 16) <- mkReg 0 45 | product :: Reg (Int 32) <- mkReg 1 46 | 47 | rules 48 | "handle_command": when True ==> do 49 | let c :: Command = msgs.commands.first 50 | msgs.commands.deq 51 | -- $display "Handling command " (cshow c) 52 | case c of 53 | Num { id = id; val = val; } -> do 54 | let newSum = sum + val 55 | let newProduct = product * signExtend val 56 | msgs.sums.enq (Result { id = id; val = newSum; }) 57 | msgs.products.enq (Result { id = id; val = newProduct; }) 58 | sum := newSum 59 | product := newProduct 60 | Reset val -> do 61 | sum := val 62 | product := signExtend val 63 | Halt -> $finish 64 | 65 | "receive_message": when messageAvailable ==> do 66 | m <- getMessage 67 | let mBytes = unpack m 68 | -- $display "B received message " (cshow (mBytes :: Vector 8 (Bit 8))) 69 | msgMgr.rxMsg.put mBytes 70 | 71 | "send_message": when True ==> do 72 | (_, mBytes) <- msgMgr.txMsg.get 73 | -- $display "B sending message " (cshow (mBytes :: Vector 8 (Bit 8))) 74 | putMessage (pack mBytes) 75 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCRepr/Calculator.bs: -------------------------------------------------------------------------------- 1 | package Calculator where 2 | 3 | import GenCRepr 4 | import CalculatorIface 5 | import FIFO 6 | import RegFile 7 | import CShow 8 | 9 | -- Note that changing the instruction/result type definitions in this file may 10 | -- affect the packed data sizes as determined by the GenCRepr type class. 11 | -- These unfortunately must be hardcoded in CalculatorIface.bsv as well, so any 12 | -- change to these types that affects the packed data sizes must be reflected in 13 | -- that file as well. 14 | 15 | type Addr = UInt 3 16 | type Val = Int 32 17 | type Id = UInt 16 18 | 19 | data Op = Add | Sub | Mul | Div 20 | deriving (Eq, Bits) 21 | 22 | data Instr = Op { op :: Op; in1 :: Addr; in2 :: Addr; out :: Addr; } 23 | | Put { a :: Addr; val :: Val; } 24 | | Get { a :: Addr; id :: Id; } 25 | | NoOp 26 | | Halt 27 | deriving (Eq, Bits) 28 | 29 | struct Result = 30 | result :: Val 31 | id :: Id 32 | deriving (Eq, Bits) 33 | 34 | eval :: Op -> Val -> Val -> Val 35 | eval Add x y = x + y 36 | eval Sub x y = x - y 37 | eval Mul x y = x * y 38 | eval Div x y = x / y 39 | 40 | -- Check that encodings have the expected number of bytes: 41 | instrSize :: (GenCRepr Instr 6) => () 42 | instrSize = () 43 | 44 | resultSize :: (GenCRepr Result 6) => () 45 | resultSize = () 46 | 47 | {-# verilog sysCalculator #-} 48 | sysCalculator :: Module Empty 49 | sysCalculator = module 50 | writeCDecls "calculator" (_ :: (Instr, Result)) 51 | 52 | haltIn :: Reg Bool <- mkReg False 53 | instrs :: FIFO Instr <- mkFIFO 54 | results :: FIFO Result <- mkFIFO 55 | regs :: RegFile Addr Val <- mkRegFile 0 7 56 | 57 | rules 58 | when not haltIn ==> do 59 | ibs <- getInstr 60 | let i :: Instr = GenCRepr.unpack ibs 61 | -- $display "Got instruction " (cshow i) 62 | instrs.enq i 63 | if i == Halt 64 | then haltIn := True 65 | else return () 66 | 67 | when True ==> do 68 | let r :: Result = results.first 69 | putResult (GenCRepr.pack r) 70 | -- $display "Putting result " (cshow r) 71 | results.deq 72 | 73 | when True ==> do 74 | let i :: Instr = instrs.first 75 | -- $display "Evaluating instruction " (cshow i) 76 | case i of 77 | Op { op; in1; in2; out; } -> regs.upd out $ eval op (regs.sub in1) (regs.sub in2) 78 | Put { a; val; } -> regs.upd a val 79 | Get { a; id; } -> results.enq (Result { result = regs.sub a; id = id; }) 80 | NoOp -> return () 81 | Halt -> $finish 82 | instrs.deq 83 | -------------------------------------------------------------------------------- /Libraries/AMBA_Fabrics/Adapters/README_AXI_Adapters.adoc: -------------------------------------------------------------------------------- 1 | = About `bsc-contrib/Libraries/AMBA_Fabrics/Adapters` 2 | :revnumber: v1.00 3 | :revdate: 2024-12-07 4 | :sectnums: 5 | :imagesdir: ../Doc/Figs 6 | :toc: 7 | :toclevels: 3 8 | :toc-title: Contents 9 | :keywords: Bluespec, B-Lang, BSV, BH, AMBA, ARM AXI, AXI4, AXI4-Lite, AXI4-Stream 10 | 11 | // ================================================================ 12 | 13 | Copyright (C) 2017-2023 Bluespec, Inc. All Rights Reserved + 14 | Copyright (C) 2024-2025 B-Lang.org. All Rights Reserved 15 | 16 | SPDX-License-Identifier: BSD-3-Clause 17 | 18 | // ================================================================ 19 | 20 | Pleae see README in parent directory 21 | (link:../README_AMBA_Fabrics.adoc[adoc],link:../README_AMBA_Fabrics.html[html]) 22 | for general introduction and about compiling/building/testing. 23 | 24 | This directory describes adapters between AXI4 and AXI4-Lite. 25 | 26 | These source codes may import other `bsv-contrib` libraries; be sure 27 | they are visible in your _bsc_ compiler paths: 28 | 29 | bsc-contrib/Libraries/AMBA_Fabrics/Utils/ 30 | bsc-contrib/Libraries/Misc/ 31 | 32 | These source codes may import other `bsv-contrib` libraries; be sure 33 | they are visible in your _bsc_ compiler paths: 34 | 35 | bsc-contrib/Libraries/AMBA_Fabrics/Utils/ 36 | bsc-contrib/Libraries/Misc/ 37 | 38 | // ================================================================ 39 | 40 | image::IMG_Under_Construction.png[align="left", width=100] 41 | 42 | The packages in this directory can be used as-is, but are expected to 43 | be restructured to be more like their AXI4 siblings (more consistent 44 | naming, clean separation of B-Lang-style and RTL-style, etc.) 45 | 46 | This documentation will be updated after that restructuring. 47 | 48 | // ================================================================ 49 | == `AXI4L_S_to_AXI4_M_Adapter.bsv` 50 | 51 | A module to bridge from an AXI4-Lite S to an AXI4 M. 52 | 53 | (... To be written ...) 54 | 55 | // ================================================================ 56 | == `AXI4_AXI4_Lite_Adapters.bsv` 57 | 58 | (... To be written ...) 59 | 60 | // ================================================================ 61 | == Unit tests 62 | 63 | Unit tests will be found in: 64 | 65 | bsc-contrib/testing/bsc.contrib/AMBA_Fabrics/Adapters/Test_*.bsv 66 | 67 | The conventions for unit tests are described in more detail in the 68 | README in the parent directory 69 | (link:../README_AMBA_Fabrics.adoc[adoc],link:../README_AMBA_Fabrics.html[html]). 70 | 71 | // ================================================================ 72 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/TLM3Utils.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM3Utils; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import BUtils::*; 12 | import DefaultValue::*; 13 | import TLM3Defines::*; 14 | import Vector::*; 15 | 16 | `include "TLM.defines" 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// 20 | //////////////////////////////////////////////////////////////////////////////// 21 | 22 | function RequestDescriptor#(`TLM_PRM) createBasicRequestDescriptor() 23 | provisos(DefaultValue#(RequestDescriptor#(`TLM_PRM))); 24 | return defaultValue; 25 | endfunction 26 | 27 | /* -----\/----- EXCLUDED -----\/----- 28 | function TLMResponse#(`TLM_PRM) createTLMResponse(TLMId#(`TLM_PRM) id, TLMStatus status) 29 | provisos(Bits#(TLMResponse#(`TLM_PRM), s0)); 30 | TLMResponse#(`TLM_PRM) response = unpack(0); 31 | response.status = status; 32 | response.transaction_id = id; 33 | return response; 34 | endfunction 35 | -----/\----- EXCLUDED -----/\----- */ 36 | 37 | function TLMResponse#(`TLM_PRM) createBasicTLMResponse () 38 | provisos(DefaultValue#(TLMResponse#(`TLM_PRM))); 39 | return defaultValue; 40 | endfunction 41 | 42 | //////////////////////////////////////////////////////////////////////////////// 43 | /// 44 | //////////////////////////////////////////////////////////////////////////////// 45 | 46 | 47 | function Bit#(data_size) createTLMBitMask ( TLMBEKind#(`TLM_PRM) byte_enable) 48 | // provisos(Div#(data_size, 8, b)) 49 | ; 50 | 51 | Vector#(TDiv#(data_size, 8),Bit#(8)) mask = replicate('1); 52 | if (byte_enable matches tagged Specify .enable_bits) begin 53 | Vector#(TDiv#(data_size, 8),Bit#(1)) enable = unpack(enable_bits); 54 | mask = map(signExtend, enable); 55 | end 56 | 57 | return cExtend(mask); 58 | 59 | endfunction 60 | 61 | function Bit#(data_size) maskTLMData( TLMBEKind#(`TLM_PRM) byte_enable, Bit#(data_size) data) 62 | // provisos(Div#(f, 8, b)); 63 | ; 64 | 65 | Bit#(data_size) mask = createTLMBitMask(byte_enable); 66 | 67 | return mask & data; 68 | 69 | endfunction 70 | 71 | function Bit#(n) overwriteTLMData( TLMBEKind#(`TLM_PRM) byte_enable, Bit#(n) data_orig, Bit#(n) data) 72 | provisos(NumAlias#(n, data_size), 73 | Div#(n, 8, b)); 74 | 75 | Bit#(n) mask = createTLMBitMask(byte_enable); 76 | 77 | return (~mask & data_orig) | (mask & data); 78 | 79 | endfunction 80 | 81 | endpackage 82 | -------------------------------------------------------------------------------- /Libraries/FPGA/Misc/PTMClocks.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package PTMClocks; 6 | 7 | import Clocks::*; 8 | 9 | // ====================================================== 10 | 11 | (* always_ready, always_enabled *) 12 | interface OutputBit; 13 | method Bit#(1) out; 14 | endinterface 15 | 16 | import "BVI" ASSIGN1 = 17 | module packClock#(Clock clk)(OutputBit); 18 | 19 | default_clock no_clock; 20 | default_reset no_reset; 21 | 22 | input_clock clk(IN) = clk; 23 | 24 | method OUT out; 25 | 26 | schedule (out) CF (out); 27 | 28 | endmodule 29 | 30 | // ====================================================== 31 | 32 | interface EnabledClock; 33 | interface Clock clock_out; 34 | endinterface 35 | 36 | import "BVI" ClockGater = 37 | module mkClockGater (Bool en, EnabledClock ifcout) ; 38 | default_clock xclk(CLK, (*unused*)CLKGATE) ; 39 | no_reset; 40 | port COND = en; 41 | output_clock clock_out(CLK_OUT, CLK_GATE_OUT); 42 | endmodule 43 | 44 | // ====================================================== 45 | 46 | interface EdgeDetector; 47 | method Bool b; 48 | endinterface 49 | 50 | module mkEdgeDetector#(Clock xtor_clk)(EdgeDetector); 51 | let clk <- exposeCurrentClock; 52 | 53 | let packedXtorClk <- packClock(xtor_clk); 54 | Bool x_clk = unpack(packedXtorClk.out); 55 | 56 | Reg#(Bool) r1 <- mkRegU; 57 | Reg#(Bool) r2 <- mkRegU; 58 | Reg#(Bool) r3 <- mkRegU; 59 | Reg#(Bool) r4 <- mkRegU; 60 | 61 | (*no_implicit_conditions, fire_when_enabled*) 62 | rule setR1; 63 | r1 <= x_clk; 64 | endrule 65 | (*no_implicit_conditions, fire_when_enabled*) 66 | rule setR2; 67 | r2 <= (x_clk && !r1); 68 | r3 <= r2; 69 | r4 <= r3; 70 | endrule 71 | 72 | method b = r4; 73 | endmodule 74 | 75 | module mkEdgeDetectorSim#(Clock xtor_clk)(EdgeDetector); 76 | let clk <- exposeCurrentClock; 77 | 78 | let packedXtorClk <- packClock(xtor_clk); 79 | Bool x_clk = unpack(packedXtorClk.out); 80 | 81 | Reg#(Bool) r1 <- mkRegU; 82 | Reg#(UInt#(4)) r2 <- mkReg(0); 83 | Reg#(UInt#(4)) r3 <- mkReg(0); 84 | Reg#(Bool) r4 <- mkRegU; 85 | 86 | (*no_implicit_conditions, fire_when_enabled*) 87 | rule every; 88 | r1 <= x_clk; 89 | if (x_clk && !r1) begin 90 | r2 <= 0; 91 | end 92 | else begin 93 | let n = r2 + 1; 94 | r2 <= n; 95 | r3 <= max(r3, n); 96 | r4 <= (r2 == r3-2); 97 | end 98 | endrule 99 | 100 | //warningM("Sim version of Edge Detector"); 101 | method b = r4; 102 | endmodule 103 | 104 | endpackage 105 | -------------------------------------------------------------------------------- /testing/bsc.contrib/SequenceRules/SequenceRulesTest.bs: -------------------------------------------------------------------------------- 1 | package SequenceRulesTest where 2 | 3 | import SequenceRules 4 | 5 | {-# verilog sysSequenceRulesTest #-} 6 | sysSequenceRulesTest :: Module Empty 7 | sysSequenceRulesTest = module 8 | cycle :: UInt 8 <- mkCycleCounter 9 | 10 | let asUint3 :: Integer -> UInt 3 11 | asUint3 = fromInteger 12 | 13 | mkSequenceRules "SequenceRulesTest" cycle do 14 | r $ $display "Cycle %d: rule 1" cycle 15 | r $ $display "Cycle %d: rule 2" cycle 16 | noR -- Skip a cycle 17 | r $ $display "Cycle %d: rule 4" cycle 18 | rRepeat 3 $ r $ $display "Cycle %d: repeated rule" cycle 19 | rDelay 3 -- Skip 3 cycles 20 | rLoopUpTo 2 4 $ \i -> r $ $display "Cycle %d: rLoopUpTo 2 4 (%d)" cycle (asUint3 i) 21 | rLoop 3 $ \i -> r $ $display "Cycle %d: rLoop 3 (%d)" cycle (asUint3 i) 22 | rPar do 23 | t do 24 | r $ $display "Cycle %d: rPar, thread 1, rule 1" cycle 25 | r $ $display "Cycle %d: rPar, thread 1, rule 2" cycle 26 | r $ $display "Cycle %d: rPar, thread 1, rule 3" cycle 27 | noR 28 | r $ $display "Cycle %d: rPar, thread 1, rule 4" cycle 29 | t do 30 | r $ $display "Cycle %d: rPar, thread 2, rule 1" cycle 31 | r $ $display "Cycle %d: rPar, thread 2, rule 2" cycle 32 | t $ rRepeat 3 do 33 | noR 34 | r $ $display "Cycle %d: rPar, thread 3, rule 1" cycle 35 | rParLoopUpTo 1 3 $ \i -> do 36 | r $ $display "Cycle %d: rParLoopUpTo 1 3, rule 1 (%d)" cycle (asUint3 i) 37 | r $ $display "Cycle %d: rParLoopUpTo 1 3, rule 2 (%d)" cycle (asUint3 i) 38 | rParLoop 4 $ \i -> do 39 | r $ $display "Cycle %d: rParLoop 4, rule 1 (%d)" cycle (asUint3 i) 40 | r $ $display "Cycle %d: rParLoop 4, rule 2 (%d)" cycle (asUint3 i) 41 | rPar do 42 | t do 43 | r $ $display "Cycle %d: rPar, rParLoop 4, subThread 1, rule 1 (%d)" cycle (asUint3 i) 44 | r $ $display "Cycle %d: rPar, rParLoop 4, subThread 1, rule 2 (%d)" cycle (asUint3 i) 45 | t do 46 | r $ $display "Cycle %d: rPar, rParLoop 4, subThread 2, rule 1 (%d)" cycle (asUint3 i) 47 | r $ $display "Cycle %d: rPar, rParLoop 4, subThread 2, rule 2 (%d)" cycle (asUint3 i) 48 | do 49 | r $ $display "Cycle %d: subsequence rule 1" cycle 50 | r $ $display "Cycle %d: subsequence rule 2" cycle 51 | rLoop 2 $ \i -> 52 | rLoop 3 $ \j -> 53 | r $ $display "Cycle %d: rLoop 2, rLoop 3 (%d, %d)" cycle (asUint3 i) (asUint3 j) 54 | rParLoop 2 $ \i -> 55 | rParLoop 3 $ \j -> 56 | r $ $display "Cycle %d: rParLoop 2, rParLoop 3 (%d, %d)" cycle (asUint3 i) (asUint3 j) 57 | 58 | r $ $display "Cycle %d: last rule" cycle 59 | r $ pass 60 | 61 | alwaysFailAtMaxCycleCount cycle 62 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLMUtils.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLMUtils; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import TLMDefines::*; 12 | import Vector::*; 13 | import BUtils::*; 14 | 15 | `include "TLM.defines" 16 | 17 | //////////////////////////////////////////////////////////////////////////////// 18 | /// 19 | //////////////////////////////////////////////////////////////////////////////// 20 | 21 | function RequestDescriptor#(`TLM_TYPES) createBasicRequestDescriptor() 22 | provisos(Bits#(RequestDescriptor#(`TLM_TYPES), s0)); 23 | RequestDescriptor#(`TLM_TYPES) request = unpack(0); 24 | request.command = READ; 25 | request.transaction_id = 0; 26 | request.burst_length = 1; 27 | request.burst_size = 3; // assume 32 bits for now. 28 | request.burst_mode = INCR; 29 | request.byte_enable = '1; 30 | return request; 31 | endfunction 32 | 33 | /* -----\/----- EXCLUDED -----\/----- 34 | function TLMResponse#(`TLM_TYPES) createTLMResponse(TLMId#(`TLM_TYPES) id, TLMStatus status) 35 | provisos(Bits#(TLMResponse#(`TLM_TYPES), s0)); 36 | TLMResponse#(`TLM_TYPES) response = unpack(0); 37 | response.status = status; 38 | response.transaction_id = id; 39 | return response; 40 | endfunction 41 | -----/\----- EXCLUDED -----/\----- */ 42 | 43 | function TLMResponse#(`TLM_TYPES) createBasicTLMResponse() 44 | provisos(Bits#(TLMResponse#(`TLM_TYPES), s0)); 45 | TLMResponse#(`TLM_TYPES) response = unpack(0); 46 | return response; 47 | endfunction 48 | 49 | //////////////////////////////////////////////////////////////////////////////// 50 | /// 51 | //////////////////////////////////////////////////////////////////////////////// 52 | 53 | 54 | function TLMData#(`TLM_TYPES) createTLMBitMask (TLMByteEn#(`TLM_TYPES) enable_bits); 55 | 56 | 57 | Vector#(TDiv#(data_size, 8),Bit#(1)) enable = unpack(enable_bits); 58 | Vector#(TDiv#(data_size, 8),Bit#(8)) mask = map(signExtend, enable); 59 | 60 | return cExtend(mask); 61 | 62 | endfunction 63 | 64 | function TLMData#(`TLM_TYPES) maskTLMData(TLMByteEn#(`TLM_TYPES) byte_enable, TLMData#(`TLM_TYPES) data); 65 | 66 | TLMData#(`TLM_TYPES) mask = createTLMBitMask(byte_enable); 67 | 68 | return mask & data; 69 | 70 | endfunction 71 | 72 | function TLMData#(`TLM_TYPES) overwriteTLMData(TLMByteEn#(`TLM_TYPES) byte_enable, TLMData#(`TLM_TYPES) data_orig, TLMData#(`TLM_TYPES) data); 73 | 74 | TLMData#(`TLM_TYPES) mask = createTLMBitMask(byte_enable); 75 | 76 | return (~mask & data_orig) | (mask & data); 77 | 78 | endfunction 79 | 80 | endpackage 81 | -------------------------------------------------------------------------------- /testing/bsc.contrib/SequenceRules/sysSequenceRulesTest.out.expected: -------------------------------------------------------------------------------- 1 | Cycle 0: rule 1 2 | Cycle 1: rule 2 3 | Cycle 3: rule 4 4 | Cycle 4: repeated rule 5 | Cycle 5: repeated rule 6 | Cycle 6: repeated rule 7 | Cycle 10: rLoopUpTo 2 4 (2) 8 | Cycle 11: rLoopUpTo 2 4 (3) 9 | Cycle 12: rLoopUpTo 2 4 (4) 10 | Cycle 13: rLoop 3 (0) 11 | Cycle 14: rLoop 3 (1) 12 | Cycle 15: rLoop 3 (2) 13 | Cycle 16: rPar, thread 1, rule 1 14 | Cycle 16: rPar, thread 2, rule 1 15 | Cycle 17: rPar, thread 1, rule 2 16 | Cycle 17: rPar, thread 2, rule 2 17 | Cycle 17: rPar, thread 3, rule 1 18 | Cycle 18: rPar, thread 1, rule 3 19 | Cycle 19: rPar, thread 3, rule 1 20 | Cycle 20: rPar, thread 1, rule 4 21 | Cycle 21: rPar, thread 3, rule 1 22 | Cycle 22: rParLoopUpTo 1 3, rule 1 (1) 23 | Cycle 22: rParLoopUpTo 1 3, rule 1 (2) 24 | Cycle 22: rParLoopUpTo 1 3, rule 1 (3) 25 | Cycle 23: rParLoopUpTo 1 3, rule 2 (1) 26 | Cycle 23: rParLoopUpTo 1 3, rule 2 (2) 27 | Cycle 23: rParLoopUpTo 1 3, rule 2 (3) 28 | Cycle 24: rParLoop 4, rule 1 (0) 29 | Cycle 24: rParLoop 4, rule 1 (1) 30 | Cycle 24: rParLoop 4, rule 1 (2) 31 | Cycle 24: rParLoop 4, rule 1 (3) 32 | Cycle 25: rParLoop 4, rule 2 (0) 33 | Cycle 25: rParLoop 4, rule 2 (1) 34 | Cycle 25: rParLoop 4, rule 2 (2) 35 | Cycle 25: rParLoop 4, rule 2 (3) 36 | Cycle 26: rPar, rParLoop 4, subThread 1, rule 1 (0) 37 | Cycle 26: rPar, rParLoop 4, subThread 2, rule 1 (0) 38 | Cycle 26: rPar, rParLoop 4, subThread 1, rule 1 (1) 39 | Cycle 26: rPar, rParLoop 4, subThread 2, rule 1 (1) 40 | Cycle 26: rPar, rParLoop 4, subThread 1, rule 1 (2) 41 | Cycle 26: rPar, rParLoop 4, subThread 2, rule 1 (2) 42 | Cycle 26: rPar, rParLoop 4, subThread 1, rule 1 (3) 43 | Cycle 26: rPar, rParLoop 4, subThread 2, rule 1 (3) 44 | Cycle 27: rPar, rParLoop 4, subThread 1, rule 2 (0) 45 | Cycle 27: rPar, rParLoop 4, subThread 2, rule 2 (0) 46 | Cycle 27: rPar, rParLoop 4, subThread 1, rule 2 (1) 47 | Cycle 27: rPar, rParLoop 4, subThread 2, rule 2 (1) 48 | Cycle 27: rPar, rParLoop 4, subThread 1, rule 2 (2) 49 | Cycle 27: rPar, rParLoop 4, subThread 2, rule 2 (2) 50 | Cycle 27: rPar, rParLoop 4, subThread 1, rule 2 (3) 51 | Cycle 27: rPar, rParLoop 4, subThread 2, rule 2 (3) 52 | Cycle 28: subsequence rule 1 53 | Cycle 29: subsequence rule 2 54 | Cycle 30: rLoop 2, rLoop 3 (0, 0) 55 | Cycle 31: rLoop 2, rLoop 3 (0, 1) 56 | Cycle 32: rLoop 2, rLoop 3 (0, 2) 57 | Cycle 33: rLoop 2, rLoop 3 (1, 0) 58 | Cycle 34: rLoop 2, rLoop 3 (1, 1) 59 | Cycle 35: rLoop 2, rLoop 3 (1, 2) 60 | Cycle 36: rParLoop 2, rParLoop 3 (0, 0) 61 | Cycle 36: rParLoop 2, rParLoop 3 (0, 1) 62 | Cycle 36: rParLoop 2, rParLoop 3 (0, 2) 63 | Cycle 36: rParLoop 2, rParLoop 3 (1, 0) 64 | Cycle 36: rParLoop 2, rParLoop 3 (1, 1) 65 | Cycle 36: rParLoop 2, rParLoop 3 (1, 2) 66 | Cycle 37: last rule 67 | PASS 68 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/TLM3Stream.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM3Stream; 6 | 7 | import DefaultValue::*; 8 | import TLM3Defines::*; 9 | 10 | `include "TLM.defines" 11 | 12 | //////////////////////////////////////////////////////////////////////////////// 13 | /// 14 | //////////////////////////////////////////////////////////////////////////////// 15 | 16 | //////////////////////////////////////////////////////////////////////////////// 17 | /// repurpose unused length_size parameter to set keep/strobe configuration 18 | //////////////////////////////////////////////////////////////////////////////// 19 | 20 | typedef 0 DFLT; 21 | typedef 1 STRB; 22 | typedef 2 KEEP; 23 | typedef 3 KEEPSTRB; 24 | 25 | typedef Bit#(TMul#(TMin#(1, TMax#(0, TSub#(TMax#(1, length_size), 1))), TDiv#(data_size, 8))) TLMKeep#(`TLM_PRM_DCL); 26 | typedef Bit#(TMul#(TSub#(TMax#(length_size, TAdd#(TDiv#(length_size, 2), TDiv#(length_size, 2))), length_size), TDiv#(data_size, 8))) TLMStrb#(`TLM_PRM_DCL); 27 | 28 | typedef struct {TLMData#(`TLM_PRM) data; 29 | TLMAddr#(`TLM_PRM) dest; 30 | TLMUser#(`TLM_PRM) user; 31 | TLMId#(`TLM_PRM) transaction_id; 32 | TLMByteEn#(`TLM_PRM) keep; 33 | TLMByteEn#(`TLM_PRM) strb; 34 | Bool is_last; 35 | } TLMTransfer#(`TLM_PRM_DCL) deriving (Eq, Bits, Bounded, FShow); 36 | 37 | //////////////////////////////////////////////////////////////////////////////// 38 | /// 39 | //////////////////////////////////////////////////////////////////////////////// 40 | 41 | instance DefaultValue #(TLMTransfer#(`TLM_PRM)); 42 | function defaultValue (); 43 | TLMTransfer#(`TLM_PRM) transfer; 44 | transfer.data = 0; 45 | transfer.dest = 0; 46 | transfer.user = 0; 47 | transfer.transaction_id = 0; 48 | transfer.keep = '1; 49 | transfer.strb = '1; 50 | transfer.is_last = False; 51 | return transfer; 52 | endfunction 53 | endinstance 54 | 55 | //////////////////////////////////////////////////////////////////////////////// 56 | /// 57 | //////////////////////////////////////////////////////////////////////////////// 58 | 59 | typeclass TLMTransferTC#(type a, `TLM_PRM_DCL) 60 | dependencies (a determines (`TLM_PRM)); 61 | function TLMTransfer#(`TLM_PRM) toTLMTransfer(a value); 62 | function a fromTLMTransfer(TLMTransfer#(`TLM_PRM) value); 63 | endtypeclass 64 | 65 | instance TLMTransferTC#(TLMTransfer#(`TLM_PRM), `TLM_PRM); 66 | function toTLMTransfer = id; 67 | function fromTLMTransfer = id; 68 | endinstance 69 | 70 | //////////////////////////////////////////////////////////////////////////////// 71 | /// 72 | //////////////////////////////////////////////////////////////////////////////// 73 | 74 | 75 | endpackage 76 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/Axi/AxiMonitor.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AxiMonitor; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AxiDefines::*; 12 | import AxiPC::*; 13 | import TLM2::*; 14 | 15 | `include "TLM.defines" 16 | 17 | //////////////////////////////////////////////////////////////////////////////// 18 | /// 19 | //////////////////////////////////////////////////////////////////////////////// 20 | 21 | interface AxiMonitor#(`TLM_PRM_DCL); 22 | endinterface 23 | 24 | module mkAxiMonitor#(Bool include_pc, 25 | AxiWrMaster#(`TLM_PRM) master_wr, 26 | AxiWrSlave#(`TLM_PRM) slave_wr, 27 | AxiRdMaster#(`TLM_PRM) master_rd, 28 | AxiRdSlave#(`TLM_PRM) slave_rd) (AxiMonitor#(`TLM_PRM)); 29 | 30 | if (include_pc && genVerilog) 31 | begin 32 | 33 | AxiPC_Ifc#(`TLM_PRM) checker <- mkAxiPC; 34 | 35 | //////////////////////////////////////////////////////////////////////////////// 36 | /// Protocol Checker connections; 37 | //////////////////////////////////////////////////////////////////////////////// 38 | 39 | rule connect_checker; 40 | 41 | checker.aw_id(master_wr.awID); 42 | checker.aw_len(master_wr.awLEN); 43 | checker.aw_size(master_wr.awSIZE); 44 | checker.aw_burst(master_wr.awBURST); 45 | checker.aw_lock(master_wr.awLOCK); 46 | checker.aw_cache(master_wr.awCACHE); 47 | checker.aw_prot(master_wr.awPROT); 48 | checker.aw_addr(master_wr.awADDR); 49 | checker.aw_valid(master_wr.awVALID); 50 | checker.aw_ready(slave_wr.awREADY); 51 | 52 | checker.w_id(master_wr.wID); 53 | checker.w_data(master_wr.wDATA); 54 | checker.w_strb(master_wr.wSTRB); 55 | checker.w_last(master_wr.wLAST); 56 | checker.w_valid(master_wr.wVALID); 57 | checker.w_ready(slave_wr.wREADY); 58 | 59 | checker.b_id(slave_wr.bID); 60 | checker.b_resp(slave_wr.bRESP); 61 | checker.b_valid(slave_wr.bVALID); 62 | checker.b_ready(master_wr.bREADY); 63 | 64 | checker.ar_id(master_rd.arID); 65 | checker.ar_len(master_rd.arLEN); 66 | checker.ar_size(master_rd.arSIZE); 67 | checker.ar_burst(master_rd.arBURST); 68 | checker.ar_lock(master_rd.arLOCK); 69 | checker.ar_cache(master_rd.arCACHE); 70 | checker.ar_prot(master_rd.arPROT); 71 | checker.ar_addr(master_rd.arADDR); 72 | checker.ar_valid(master_rd.arVALID); 73 | checker.ar_ready(slave_rd.arREADY); 74 | 75 | checker.r_id(slave_rd.rID); 76 | checker.r_data(slave_rd.rDATA); 77 | checker.r_resp(slave_rd.rRESP); 78 | checker.r_last(slave_rd.rLAST); 79 | checker.r_valid(slave_rd.rVALID); 80 | checker.r_ready(master_rd.rREADY); 81 | 82 | endrule 83 | end 84 | 85 | endmodule 86 | 87 | endpackage 88 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Axi/AxiMonitor.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package AxiMonitor; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import AxiDefines::*; 12 | import AxiPC::*; 13 | import TLM3::*; 14 | 15 | `include "TLM.defines" 16 | 17 | //////////////////////////////////////////////////////////////////////////////// 18 | /// 19 | //////////////////////////////////////////////////////////////////////////////// 20 | 21 | interface AxiMonitor#(`TLM_PRM_DCL); 22 | endinterface 23 | 24 | module mkAxiMonitor#(Bool include_pc, 25 | AxiWrMaster#(`TLM_PRM) master_wr, 26 | AxiWrSlave#(`TLM_PRM) slave_wr, 27 | AxiRdMaster#(`TLM_PRM) master_rd, 28 | AxiRdSlave#(`TLM_PRM) slave_rd) (AxiMonitor#(`TLM_PRM)); 29 | 30 | if (include_pc && genVerilog) 31 | begin 32 | 33 | AxiPC_Ifc#(`TLM_PRM) checker <- mkAxiPC; 34 | 35 | //////////////////////////////////////////////////////////////////////////////// 36 | /// Protocol Checker connections; 37 | //////////////////////////////////////////////////////////////////////////////// 38 | 39 | rule connect_checker; 40 | 41 | checker.aw_id(master_wr.awID); 42 | checker.aw_len(master_wr.awLEN); 43 | checker.aw_size(master_wr.awSIZE); 44 | checker.aw_burst(master_wr.awBURST); 45 | checker.aw_lock(master_wr.awLOCK); 46 | checker.aw_cache(master_wr.awCACHE); 47 | checker.aw_prot(master_wr.awPROT); 48 | checker.aw_addr(master_wr.awADDR); 49 | checker.aw_valid(master_wr.awVALID); 50 | checker.aw_ready(slave_wr.awREADY); 51 | 52 | checker.w_id(master_wr.wID); 53 | checker.w_data(master_wr.wDATA); 54 | checker.w_strb(master_wr.wSTRB); 55 | checker.w_last(master_wr.wLAST); 56 | checker.w_valid(master_wr.wVALID); 57 | checker.w_ready(slave_wr.wREADY); 58 | 59 | checker.b_id(slave_wr.bID); 60 | checker.b_resp(slave_wr.bRESP); 61 | checker.b_valid(slave_wr.bVALID); 62 | checker.b_ready(master_wr.bREADY); 63 | 64 | checker.ar_id(master_rd.arID); 65 | checker.ar_len(master_rd.arLEN); 66 | checker.ar_size(master_rd.arSIZE); 67 | checker.ar_burst(master_rd.arBURST); 68 | checker.ar_lock(master_rd.arLOCK); 69 | checker.ar_cache(master_rd.arCACHE); 70 | checker.ar_prot(master_rd.arPROT); 71 | checker.ar_addr(master_rd.arADDR); 72 | checker.ar_valid(master_rd.arVALID); 73 | checker.ar_ready(slave_rd.arREADY); 74 | 75 | checker.r_id(slave_rd.rID); 76 | checker.r_data(slave_rd.rDATA); 77 | checker.r_resp(slave_rd.rRESP); 78 | checker.r_last(slave_rd.rLAST); 79 | checker.r_valid(slave_rd.rVALID); 80 | checker.r_ready(master_rd.rREADY); 81 | 82 | endrule 83 | end 84 | 85 | endmodule 86 | 87 | endpackage 88 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/Ahb/AhbToAhbBridge.bsv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 3 | // 4 | // SPDX-License-Identifier: BSD-3-Clause 5 | // 6 | //////////////////////////////////////////////////////////////////////////////// 7 | // Filename : AhbToAhbBridge.bsv 8 | // Description : 9 | //////////////////////////////////////////////////////////////////////////////// 10 | package AhbToAhbBridge; 11 | 12 | // Notes : 13 | 14 | //////////////////////////////////////////////////////////////////////////////// 15 | /// Imports 16 | //////////////////////////////////////////////////////////////////////////////// 17 | import AhbDefines ::*; 18 | import AhbSlave ::*; 19 | import AhbMaster ::*; 20 | import TLM3 ::*; 21 | import DefaultValue ::*; 22 | import Connectable ::*; 23 | 24 | `include "TLM.defines" 25 | 26 | //////////////////////////////////////////////////////////////////////////////// 27 | /// Interfaces 28 | //////////////////////////////////////////////////////////////////////////////// 29 | interface AhbToAhbBridge#(`TLM_XTR_DCL); 30 | interface AhbXtorSlaveWM#(`TLM_PRM) slave; 31 | interface AhbXtorMaster#(`TLM_PRM) master; 32 | endinterface 33 | 34 | //////////////////////////////////////////////////////////////////////////////// 35 | //////////////////////////////////////////////////////////////////////////////// 36 | /// 37 | /// Implementation 38 | /// 39 | //////////////////////////////////////////////////////////////////////////////// 40 | //////////////////////////////////////////////////////////////////////////////// 41 | module mkAhbToAhbBridgeWM#(function Bool addr_match(AhbAddr#(`TLM_PRM) addr))(AhbToAhbBridge#(`TLM_XTR)) 42 | provisos ( Bits#(req_t, s0) 43 | , Bits#(resp_t, s1) 44 | , DefaultValue#(TLMResponse#(`TLM_PRM)) 45 | , DefaultValue#(RequestDescriptor#(`TLM_PRM)) 46 | , TLMRequestTC#(req_t, `TLM_PRM) 47 | , TLMResponseTC#(resp_t, `TLM_PRM) 48 | ); 49 | 50 | //////////////////////////////////////////////////////////////////////////////// 51 | /// Design Elements 52 | //////////////////////////////////////////////////////////////////////////////// 53 | AhbSlaveXActorWM#(`TLM_XTR) ahb_slave <- mkAhbSlaveWM( addr_match ); 54 | AhbMasterXActor#(`TLM_XTR) ahb_master <- mkAhbMaster(10); 55 | 56 | //////////////////////////////////////////////////////////////////////////////// 57 | /// Submodule Connections 58 | //////////////////////////////////////////////////////////////////////////////// 59 | mkConnection(ahb_slave.tlm, ahb_master.tlm); 60 | 61 | //////////////////////////////////////////////////////////////////////////////// 62 | /// Interface Connections / Methods 63 | //////////////////////////////////////////////////////////////////////////////// 64 | interface slave = ahb_slave.fabric; 65 | interface master = ahb_master.fabric; 66 | 67 | endmodule 68 | 69 | endpackage: AhbToAhbBridge 70 | 71 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLMRam.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLMRam; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import GetPut::*; 12 | import RegFile::*; 13 | import TLMDefines::*; 14 | import TLMUtils::*; 15 | import BUtils::*; 16 | import FShow::*; 17 | 18 | `include "TLM.defines" 19 | 20 | //////////////////////////////////////////////////////////////////////////////// 21 | /// 22 | //////////////////////////////////////////////////////////////////////////////// 23 | 24 | module mkTLMRam#(parameter Bit#(4) id, Bool verbose) (TLMRecvIFC#(`TLM_TYPES)) 25 | provisos(Bits#(TLMRequest#(`TLM_TYPES), s0), 26 | Bits#(TLMResponse#(`TLM_TYPES), s1), 27 | FShow#(TLMRequest#(`TLM_TYPES))); 28 | 29 | Wire#(TLMRequest#(`TLM_TYPES)) in_wire <- mkWire; 30 | Wire#(TLMResponse#(`TLM_TYPES)) out_wire <- mkWire; 31 | 32 | RegFile#(Bit#(8), Bit#(data_size)) ram <- mkRegFileLoad("ram_init.text", 0, 255); 33 | 34 | rule read_op (in_wire matches tagged Descriptor .d 35 | &&& d.command matches READ 36 | &&& d.burst_length matches 1); 37 | 38 | TLMResponse#(`TLM_TYPES) response = createBasicTLMResponse(); 39 | Bit#(10) addr = zExtend(d.addr); 40 | Bit#(8) mem_addr = grab_left(addr); 41 | TLMData#(`TLM_TYPES) data = ram.sub(mem_addr); 42 | response.data = maskTLMData(d.byte_enable, data); 43 | response.status = SUCCESS; 44 | response.transaction_id = d.transaction_id; 45 | response.command = READ; 46 | 47 | out_wire <= response; 48 | 49 | if (verbose) $display("(%0d) TM (%0d) Read Op %h %h", $time, id, d.addr, response.data); 50 | 51 | endrule 52 | 53 | 54 | rule write_op (in_wire matches tagged Descriptor .d 55 | &&& d.command matches WRITE 56 | &&& d.burst_length matches 1); 57 | 58 | Bit#(10) addr = zExtend(d.addr); 59 | Bit#(8) mem_addr = grab_left(addr); 60 | TLMData#(`TLM_TYPES) data_orig = ram.sub(mem_addr); 61 | TLMData#(`TLM_TYPES) data_new = overwriteTLMData(d.byte_enable, data_orig, d.data); 62 | ram.upd(mem_addr, data_new); 63 | 64 | TLMResponse#(`TLM_TYPES) response = createBasicTLMResponse(); 65 | response.status = SUCCESS; 66 | response.transaction_id = d.transaction_id; 67 | response.command = WRITE; 68 | 69 | out_wire <= response; 70 | 71 | if (verbose) $display("(%0d) TM (%0d) Write Op %h %h", $time, id, d.addr, d.data); 72 | 73 | endrule 74 | 75 | rule error_op (in_wire matches tagged Descriptor .d 76 | &&& (d.burst_length > 1)); 77 | $display("(%0d) ERROR: TLMRAM (%0d) (cannot handle ops with burst length > 1).", $time, id); 78 | endrule 79 | 80 | interface Get tx; 81 | method get; 82 | actionvalue 83 | return out_wire; 84 | endactionvalue 85 | endmethod 86 | endinterface 87 | interface Put rx; 88 | method Action put (x); 89 | in_wire <= x; 90 | endmethod 91 | endinterface 92 | 93 | endmodule 94 | 95 | endpackage 96 | -------------------------------------------------------------------------------- /testing/bsc.contrib/VerilogRepr/Chess.bs: -------------------------------------------------------------------------------- 1 | package Chess where 2 | 3 | import Vector 4 | import VerilogRepr 5 | 6 | -- From https://github.com/krame505/hardware-chess 7 | 8 | data PieceKind 9 | = Pawn 10 | | Knight 11 | | Bishop 12 | | Rook 13 | | Queen 14 | | King 15 | deriving (Eq, Bits) 16 | 17 | data Color = White | Black 18 | deriving (Eq, Bits) 19 | 20 | struct Piece = 21 | color :: Color 22 | kind :: PieceKind 23 | deriving (Eq, Bits) 24 | 25 | type Board = Vector 8 (Vector 8 (Maybe Piece)) 26 | 27 | struct Position = 28 | rank :: UInt 3 29 | file :: UInt 3 30 | deriving (Eq, Bits) 31 | 32 | struct PlayerHistory = 33 | pawnMoved2 :: Maybe (UInt 3) 34 | kingMoved :: Bool 35 | kRookMoved :: Bool 36 | qRookMoved :: Bool 37 | castled :: Bool 38 | deriving (Eq, Bits) 39 | 40 | struct State = 41 | turn :: Color 42 | board :: Board 43 | whiteHist :: PlayerHistory 44 | blackHist :: PlayerHistory 45 | lastProgressMove :: UInt 6 46 | deriving (Eq, Bits) 47 | 48 | data Move 49 | = Move { from :: Position; to :: Position } 50 | | EnPassant { from :: Position; to :: Position } 51 | | Promote { kind :: PieceKind; from :: Position; to :: Position } 52 | | Castle {kingSide :: Bool} 53 | deriving (Eq, Bits) 54 | 55 | data Outcome = NoOutcome | Check | CheckMate | Draw 56 | deriving (Bits) 57 | 58 | type Score maxScore = Int (TLog (TAdd 1 maxScore)) 59 | type RequestId = UInt 8 60 | 61 | struct SearchQuery config maxScore maxDepth = 62 | rid :: RequestId 63 | state :: State 64 | depth :: UInt (TLog maxDepth) 65 | getMoves :: Bool 66 | alpha :: Maybe (Score maxScore) 67 | beta :: Maybe (Score maxScore) 68 | conf :: config 69 | deriving (Bits) 70 | 71 | struct SearchResult maxScore maxDepth = 72 | rid :: RequestId 73 | outcome :: Outcome 74 | bestMove :: Maybe Move 75 | forcedOutcome :: Bool -- Can either player force a win 76 | score :: (Score maxScore) 77 | depth :: UInt (TLog maxDepth) 78 | deriving (Bits) 79 | 80 | struct Config weight = 81 | materialValue :: weight 82 | centerControlValue :: weight 83 | extendedCenterControlValue :: weight 84 | castleValue :: weight 85 | pawnStructureValue :: weight 86 | deriving (Bits) 87 | 88 | type MaxScore = 500 89 | type MaxWeight = 4 90 | type MaxDepth = 16 91 | 92 | type DefaultSearchQuery = SearchQuery (Config (UInt (TLog MaxWeight))) MaxScore MaxDepth 93 | type DefaultSearchResult = SearchResult MaxScore MaxDepth 94 | 95 | type SVTypes = (DefaultSearchQuery, DefaultSearchResult) 96 | 97 | renderAll :: RenderVerilog () 98 | renderAll = do 99 | emitDecl "Chess" $ VLocalParam "MAX_SCORE" (log2 $ 1 + valueOf MaxScore) $ valueOf MaxScore 100 | emitDecl "Chess" $ VLocalParam "MAX_WEIGHT" (log2 $ 1 + valueOf MaxWeight) $ valueOf MaxWeight 101 | emitDecl "Chess" $ VLocalParam "MAX_DEPTH" (log2 $ 1 + valueOf MaxDepth) $ valueOf MaxDepth 102 | verilogImpls (prx :: SVTypes) 103 | 104 | svFileName :: String 105 | svFileName = "chess.svh" 106 | 107 | jsonFileName :: String 108 | jsonFileName = "chess_types.json" 109 | 110 | {-# synthesize main #-} 111 | main :: Module Empty 112 | main = writeVerilogAndJsonFile 113 | svFileName jsonFileName 114 | "package chess;\n\n" 115 | "endpackage" 116 | renderAll 117 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/TLM3FlowControl.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM3FlowControl; 6 | 7 | import TLM3Defines::*; 8 | import FIFOF::*; 9 | import GetPut::*; 10 | 11 | `include "TLM.defines" 12 | 13 | //////////////////////////////////////////////////////////////////////////////// 14 | /// 15 | //////////////////////////////////////////////////////////////////////////////// 16 | 17 | typeclass FlowPayload#(type a); 18 | function Bool lastOne (a payload); 19 | function Bool canStall(a payload); 20 | endtypeclass 21 | 22 | //////////////////////////////////////////////////////////////////////////////// 23 | /// 24 | //////////////////////////////////////////////////////////////////////////////// 25 | 26 | instance FlowPayload#(TLMRequest#(`TLM_PRM)); 27 | function Bool lastOne (TLMRequest#(`TLM_PRM) request); 28 | let is_last = False; 29 | if (request matches tagged Descriptor .d) 30 | is_last = d.b_length == 0 || d.command == READ; 31 | if (request matches tagged Data .d) 32 | is_last = d.is_last; 33 | return is_last; 34 | endfunction 35 | function Bool canStall (TLMRequest#(`TLM_PRM) request); 36 | let can_stall = False; 37 | if (request matches tagged Descriptor .d) 38 | can_stall = d.cntrl_flow && d.command == WRITE; 39 | if (request matches tagged Data .d) 40 | can_stall = False; 41 | return can_stall; 42 | endfunction 43 | endinstance 44 | 45 | instance FlowPayload#(TLMResponse#(`TLM_PRM)); 46 | function Bool lastOne (TLMResponse#(`TLM_PRM) response); 47 | return response.is_last; 48 | endfunction 49 | function Bool canStall (TLMResponse#(`TLM_PRM) response); 50 | return False; 51 | endfunction 52 | endinstance 53 | 54 | //////////////////////////////////////////////////////////////////////////////// 55 | /// 56 | //////////////////////////////////////////////////////////////////////////////// 57 | 58 | interface TLMFlow#(type a); 59 | interface Get#(a) tx; 60 | interface Put#(a) rx; 61 | endinterface 62 | 63 | module mkTLMFlow#(parameter UInt#(32) depth) (TLMFlow#(a)) 64 | provisos(FlowPayload#(a), Bits#(a, sa)); 65 | 66 | let d = max(3, depth); 67 | 68 | FIFOF#(a) fifo <- mkSafeDepthParamFIFOF(d); 69 | 70 | FIFOF#(void) cntr <- mkSafeDepthParamFIFOF(paramLog(d)); 71 | 72 | Bool can_deq = !canStall(fifo.first) || !fifo.notFull || cntr.notEmpty || depth == 0; 73 | 74 | interface Get tx; 75 | method ActionValue#(a) get if (can_deq); 76 | if (lastOne(fifo.first)) cntr.deq; 77 | fifo.deq; 78 | return fifo.first; 79 | endmethod 80 | endinterface 81 | 82 | interface Put rx; 83 | method Action put (a value); 84 | fifo.enq(value); 85 | if (lastOne(value)) cntr.enq(?); 86 | endmethod 87 | endinterface 88 | 89 | endmodule 90 | 91 | function UInt#(32) paramLog (UInt#(32) n); 92 | UInt#(32) result = ?; 93 | if (n <= 4) result = (2 + 1); 94 | else if (n <= 16) result = (4 + 1); 95 | else if (n <= 256) result = (8 + 1); 96 | else if (n <= 65536) result = (16 + 1); 97 | else result = 32; 98 | return result; 99 | endfunction 100 | 101 | endpackage 102 | -------------------------------------------------------------------------------- /Libraries/Misc/VectorFIFOF.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2025 Bluespec, Inc. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package VectorFIFOF; 6 | 7 | // This package implements a fifo like module with a parameterized 8 | // depth and standard FIFOF interface. The module also provides 9 | // parallel access to all items in the fifo, for example, to allow 10 | // searching for hazards before enqueueing new items. 11 | // 12 | // The enq, deq, and clear methods may be called in any order. enq 13 | // and deq may not occur in the same cycle if the fifo is empty or 14 | // full. 15 | 16 | import FIFOF ::*; 17 | import RevertingVirtualReg ::*; 18 | import Vector ::*; 19 | 20 | interface VectorFIFOF#(numeric type depth, type t); 21 | interface FIFOF#(t) fifo; 22 | method Vector#(depth, Maybe#(t)) vector(); 23 | endinterface 24 | 25 | module mkVectorFIFOF(VectorFIFOF#(depth, t)) 26 | provisos( 27 | Bits#(t, tsz) 28 | ); 29 | 30 | Vector#(depth, Reg#(t)) vr_data <- replicateM(mkRegU); 31 | Reg#(UInt#(TLog#(TAdd#(depth,1)))) r_count <- mkReg(0); 32 | 33 | RWire#(t) w_enq <- mkRWire; 34 | PulseWire pw_deq <- mkPulseWire; 35 | PulseWire pw_clear <- mkPulseWire; 36 | 37 | (* fire_when_enabled, no_implicit_conditions *) 38 | rule rl_magic; 39 | if (pw_clear) 40 | r_count <= 0; 41 | else if (isValid(w_enq.wget) && !pw_deq) 42 | r_count <= r_count + 1; 43 | else if (!isValid(w_enq.wget) && pw_deq) 44 | r_count <= r_count - 1; 45 | 46 | Vector#(depth, t) newdata = readVReg(vr_data); 47 | 48 | if (pw_deq) 49 | for (Integer i = 0; i < fromInteger(valueOf(depth)) - 1; i = i + 1) 50 | newdata[i] = newdata[i + 1]; 51 | 52 | if (w_enq.wget matches tagged Valid .x) 53 | newdata[pw_deq ? r_count - 1 : r_count] = x; 54 | 55 | writeVReg(vr_data, newdata); 56 | endrule 57 | 58 | function Bool notFull; 59 | return r_count < fromInteger(valueOf(depth)); 60 | endfunction 61 | 62 | function Bool notEmpty; 63 | return r_count != 0; 64 | endfunction 65 | 66 | function Maybe#(t) valid(Integer x, t a); 67 | if (fromInteger(x) < r_count) 68 | return tagged Valid a; 69 | else 70 | return tagged Invalid; 71 | endfunction 72 | 73 | Reg#(Bool) beforeEnq <- mkRevertingVirtualReg(True); 74 | Reg#(Bool) beforeDeq <- mkRevertingVirtualReg(True); 75 | Reg#(Bool) beforeClear <- mkRevertingVirtualReg(True); 76 | 77 | Bool beforeActions = beforeEnq && beforeDeq && beforeClear; 78 | 79 | interface FIFOF fifo; 80 | method Action enq(t x) if (notFull && beforeClear); 81 | w_enq.wset(x); 82 | beforeEnq <= False; 83 | endmethod 84 | method Action deq if (notEmpty && beforeClear); 85 | pw_deq.send; 86 | beforeDeq <= False; 87 | endmethod 88 | method t first if (beforeDeq && beforeClear && (r_count > 0)) = vr_data[0]; 89 | method Action clear(); 90 | pw_clear.send; 91 | beforeClear <= False; 92 | endmethod 93 | method Bool notFull() if (beforeActions) = notFull; 94 | method Bool notEmpty() if (beforeActions) = notEmpty; 95 | endinterface 96 | 97 | method vector() if (beforeActions) = zipWith(valid, genVector, readVReg(vr_data)); 98 | 99 | endmodule 100 | 101 | endpackage 102 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/BackPressureAHBBus.bsv: -------------------------------------------------------------------------------- 1 | package BackPressureAHBBus; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import AHB::*; 8 | import Connectable::*; 9 | import FIFO::*; 10 | import FShow::*; 11 | import GetPut::*; 12 | import Probe::*; 13 | import Randomizable::*; 14 | import TLM2::*; 15 | import Vector::*; 16 | 17 | `include "TLM.defines" 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | /// 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | (* synthesize *) 24 | module sysBackPressureAHBBus (); 25 | 26 | function Bool addrMatch0(AHBAddr#(`TLM_PRM) a); 27 | return (a[12] == 0); 28 | endfunction 29 | 30 | function Bool addrMatch1(AHBAddr#(`TLM_PRM) a); 31 | return (a[12] == 1); 32 | endfunction 33 | 34 | Reg#(Bit#(16)) count <- mkReg(0); 35 | 36 | TLMSendIFC#(`TLM_RR_STD) source_0 <- mkSource(tagged Invalid, True); 37 | TLMSendIFC#(`TLM_RR_STD) source_1 <- mkSource(tagged Invalid, True); 38 | 39 | AHBMasterXActor#(`TLM_RR_STD, `TLM_PRM_STD) master_0 <- mkAHBMasterStd; 40 | AHBMasterXActor#(`TLM_RR_STD, `TLM_PRM_STD) master_1 <- mkAHBMasterStd; 41 | AHBSlaveXActor#(`TLM_RR_STD, `TLM_PRM_STD) slave_0 <- mkAHBSlaveStd(addrMatch0); 42 | AHBSlaveXActor#(`TLM_RR_STD, `TLM_PRM_STD) slave_1 <- mkAHBSlaveStd(addrMatch1); 43 | 44 | TLMRecvIFC#(`TLM_RR_STD) mem_0 <- mkTLMRam_unbuffered(0,True); 45 | TLMRecvIFC#(`TLM_RR_STD) mem_1 <- mkTLMRam_unbuffered(1,True); 46 | 47 | Vector#(2, AHBFabricMaster#(`TLM_PRM_STD)) masters = newVector; 48 | Vector#(2, AHBFabricSlave#(`TLM_PRM_STD)) slaves = newVector; 49 | 50 | masters[0] = master_0.fabric; 51 | masters[1] = master_1.fabric; 52 | slaves[0] = slave_0.fabric; 53 | slaves[1] = slave_1.fabric; 54 | 55 | mkAHBBus(masters, slaves); 56 | 57 | mkConnection(source_0, master_0.tlm); 58 | mkConnection(source_1, master_1.tlm); 59 | mkConnection(slave_0.tlm, mem_0); 60 | mkConnection(slave_1.tlm, mem_1); 61 | 62 | rule every; 63 | count <= count + 1; 64 | if (count == 500) $finish; 65 | endrule 66 | 67 | endmodule 68 | 69 | 70 | (* synthesize *) 71 | module mkSource#(Maybe#(TLMCommand) m_command, Bool verbose) (TLMSendIFC#(`TLM_RR_STD)); 72 | 73 | Reg#(Bool) initialized <- mkReg(False); 74 | FIFO#(TLMResponseStd) response_fifo <- mkFIFO; 75 | Randomize#(TLMRequestStd) gen <- mkTLMRandomizer(m_command); 76 | Reg#(Bit#(2)) count <- mkReg(0); 77 | 78 | rule every; 79 | count <= count + 1; 80 | endrule 81 | 82 | rule start (!initialized); 83 | gen.cntrl.init; 84 | initialized <= True; 85 | endrule 86 | 87 | rule grab_responses (count == 0); 88 | let value = response_fifo.first; 89 | response_fifo.deq; 90 | if (verbose) $display("(%0d) Response is: ", $time, fshow(value)); 91 | endrule 92 | 93 | interface Get tx; 94 | method ActionValue#(TLMRequestStd) get; 95 | let value <- gen.next; 96 | if (value matches tagged Descriptor .d) 97 | if (verbose) $display("(%0d) Request is: ", $time, fshow(d)); 98 | return value; 99 | endmethod 100 | endinterface 101 | 102 | interface Put rx = toPut(response_fifo); 103 | 104 | endmodule 105 | 106 | endpackage 107 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLMReduce.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLMReduce; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import SpecialFIFOs::*; 12 | import FIFO::*; 13 | import GetPut::*; 14 | import TLMDefines::*; 15 | 16 | `include "TLM.defines" 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// Convert a stream of (arbitrary) TLM ops into a stream with only single 20 | /// reads and single writes. 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | module mkTLMReducer (TLMTransformIFC#(`TLM_TYPES)) 24 | provisos(Bits#(TLMRequest#(`TLM_TYPES), s0), 25 | Bits#(TLMResponse#(`TLM_TYPES), s1), 26 | Bits#(RequestDescriptor#(`TLM_TYPES), s2)); 27 | 28 | Reg#(RequestDescriptor#(`TLM_TYPES)) desc_reg <- mkReg(?); 29 | Reg#(TLMUInt#(`TLM_TYPES)) count <- mkReg(0); 30 | 31 | FIFO#(TLMResponse#(`TLM_TYPES)) fifo_in_tx <- mkBypassFIFO; 32 | FIFO#(TLMRequest#(`TLM_TYPES)) fifo_in_rx <- mkBypassFIFO; 33 | FIFO#(TLMRequest#(`TLM_TYPES)) fifo_out_tx <- mkBypassFIFO; 34 | FIFO#(TLMResponse#(`TLM_TYPES)) fifo_out_rx <- mkBypassFIFO; 35 | 36 | rule read_op_first (fifo_in_rx.first matches tagged Descriptor .d 37 | &&& d.command matches READ 38 | &&& (count == 0)); 39 | let desc_current = d; 40 | desc_current.burst_length = 1; 41 | fifo_out_tx.enq(tagged Descriptor desc_current); 42 | desc_reg <= incrTLMAddr(desc_current); 43 | 44 | let remaining = d.burst_length - 1; 45 | count <= remaining; 46 | if (remaining == 0) fifo_in_rx.deq; 47 | endrule 48 | 49 | rule read_op_rest (fifo_in_rx.first matches tagged Descriptor .d 50 | &&& d.command matches READ 51 | &&& (count > 0)); 52 | fifo_out_tx.enq(tagged Descriptor desc_reg); 53 | desc_reg <= incrTLMAddr(desc_reg); 54 | 55 | let remaining = count - 1; 56 | count <= remaining; 57 | if (remaining == 0) fifo_in_rx.deq; 58 | endrule 59 | 60 | rule write_op_first (fifo_in_rx.first matches tagged Descriptor .d 61 | &&& d.command matches WRITE); 62 | let desc_current = d; 63 | desc_current.burst_length = 1; 64 | fifo_out_tx.enq(tagged Descriptor desc_current); 65 | desc_reg <= incrTLMAddr(desc_current); 66 | 67 | fifo_in_rx.deq; 68 | endrule 69 | 70 | rule write_op_rest (fifo_in_rx.first matches tagged Data .d); 71 | let desc_current = desc_reg; 72 | desc_current.data = d.data; 73 | fifo_out_tx.enq(tagged Descriptor desc_current); 74 | desc_reg <= incrTLMAddr(desc_reg); 75 | 76 | fifo_in_rx.deq; 77 | endrule 78 | 79 | // for now just pass on responses 80 | rule pass_on_responses; 81 | let response = fifo_out_rx.first; 82 | fifo_in_tx.enq(response); 83 | fifo_out_rx.deq; 84 | endrule 85 | 86 | interface TLMRecvIFC in; 87 | interface Get tx = toGet(fifo_in_tx); 88 | interface Put rx = toPut(fifo_in_rx); 89 | endinterface 90 | 91 | interface TLMSendIFC out; 92 | interface Get tx = toGet(fifo_out_tx); 93 | interface Put rx = toPut(fifo_out_rx); 94 | endinterface 95 | 96 | endmodule 97 | 98 | 99 | endpackage 100 | -------------------------------------------------------------------------------- /Libraries/Misc/EdgeFIFOFs.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2016-2019 Bluespec, Inc. All Rights Reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | // EdgeFIFOFs are 1-element FIFOFs used as generic interfaces by IPs 6 | // where they connect to interconnect fabrics. The overall interface 7 | // is a standard FIFOF interface. The IP-side is guarded. The 8 | // Fabric-side is unguarded, so that it's easy to attach transactors 9 | // for some particular bus interface such as AXI4-Lite, AHB-Lite, etc. 10 | 11 | package EdgeFIFOFs; 12 | 13 | // ================================================================ 14 | // BSV library imports 15 | 16 | import FIFOF :: *; 17 | 18 | // ================================================================ 19 | // FIFOFs for IPs that send requests (M = manager, master) 20 | // enq (IP-side) is guarded, deq (Fabric-side) is not. 21 | 22 | module mkM_EdgeFIFOF (FIFOF #(t)) 23 | provisos (Bits #(t, tsz)); 24 | 25 | Integer port_deq = 0; 26 | Integer port_enq = 1; 27 | Integer port_clear = 2; 28 | 29 | Array #(Reg #(Bool)) crg_full <- mkCReg (3, False); 30 | Reg #(t) rg_payload <- mkRegU; 31 | 32 | // ---------------- 33 | // Clear 34 | 35 | method Action clear; 36 | crg_full [port_clear] <= False; 37 | endmethod 38 | 39 | // ---------------- 40 | // Enq side (IP-side; guarded) 41 | 42 | method Bool notFull (); 43 | return (! crg_full [port_enq]); 44 | endmethod 45 | 46 | method Action enq (t x) if (! crg_full [port_enq]); 47 | crg_full [port_enq] <= True; 48 | rg_payload <= x; 49 | endmethod 50 | 51 | // ---------------- 52 | // Deq side (Fabric-side; unguarded) 53 | 54 | method Bool notEmpty (); 55 | return crg_full [port_deq]; 56 | endmethod 57 | 58 | method t first (); // unguarded 59 | return rg_payload; 60 | endmethod 61 | 62 | method Action deq (); // unguarded 63 | crg_full [port_deq] <= False; 64 | endmethod 65 | 66 | endmodule 67 | 68 | // ================================================================ 69 | // FIFOFs for IPs that receive requests (S = subordinate, slave) 70 | // enq (Fabric-side) is unguarded, deq (IP-side) is guarded. 71 | 72 | module mkS_EdgeFIFOF (FIFOF #(t)) 73 | provisos (Bits #(t, tsz)); 74 | 75 | Integer port_deq = 0; 76 | Integer port_enq = 1; 77 | Integer port_clear = 2; 78 | 79 | Array #(Reg #(Bool)) crg_full <- mkCReg (3, False); 80 | Reg #(t) rg_payload <- mkRegU; 81 | 82 | // ---------------- 83 | // Clear 84 | 85 | method Action clear; 86 | crg_full [port_clear] <= False; 87 | endmethod 88 | 89 | // ---------------- 90 | // Enq side (IP-side; unguarded) 91 | 92 | method Bool notFull (); 93 | return (! crg_full [port_enq]); 94 | endmethod 95 | 96 | method Action enq (t x); // unguarded 97 | crg_full [port_enq] <= True; 98 | rg_payload <= x; 99 | endmethod 100 | 101 | // ---------------- 102 | // Deq side (Fabric-side; guarded) 103 | 104 | method Bool notEmpty (); 105 | return crg_full [port_deq]; 106 | endmethod 107 | 108 | method t first () if (crg_full [port_deq]); 109 | return rg_payload; 110 | endmethod 111 | 112 | method Action deq () if (crg_full [port_deq]); 113 | crg_full [port_deq] <= False; 114 | endmethod 115 | 116 | endmodule 117 | 118 | // ================================================================ 119 | 120 | endpackage 121 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/sysCounterB2B.out.expected: -------------------------------------------------------------------------------- 1 | Sending command Reset {id=0x0000; newSum= 0; newProduct= 0} 2 | Sending command Num {id=0x0001; val= 1} 3 | Sending command Num {id=0x0002; val= 2} 4 | Sending command Num {id=0x0003; val= 3} 5 | Sending command Num {id=0x0004; val= 4} 6 | Sending command Reset {id=0x0005; newSum= 5; newProduct= 50} 7 | Handling command Reset {id=0x0000; newSum= 0; newProduct= 0} 8 | Sending command Num {id=0x0006; val= 6} 9 | Handling command Num {id=0x0001; val= 1} 10 | Sending command Num {id=0x0007; val= 7} 11 | Sending command Num {id=0x0008; val= 8} 12 | Sending command Num {id=0x0009; val= 9} 13 | Handling command Num {id=0x0002; val= 2} 14 | Got sum 0 0 15 | Handling command Num {id=0x0003; val= 3} 16 | Sending command Reset {id=0x000a; newSum= 10; newProduct= 100} 17 | Got sum 1 1 18 | Sending command Num {id=0x000b; val= 11} 19 | Got product 0 0 20 | Got product 1 0 21 | Handling command Num {id=0x0004; val= 4} 22 | Got sum 2 3 23 | Handling command Reset {id=0x0005; newSum= 5; newProduct= 50} 24 | Sending command Num {id=0x000c; val= 12} 25 | Got sum 3 6 26 | Sending command Num {id=0x000d; val= 13} 27 | Got product 2 0 28 | Got product 3 0 29 | Handling command Num {id=0x0006; val= 6} 30 | Got sum 4 10 31 | Handling command Num {id=0x0007; val= 7} 32 | Sending command Num {id=0x000e; val= 14} 33 | Got sum 5 5 34 | Sending command Reset {id=0x000f; newSum= 15; newProduct= 150} 35 | Got product 4 0 36 | Got product 5 50 37 | Handling command Num {id=0x0008; val= 8} 38 | Got sum 6 11 39 | Handling command Num {id=0x0009; val= 9} 40 | Sending command Num {id=0x0010; val= 16} 41 | Got sum 7 18 42 | Sending command Num {id=0x0011; val= 17} 43 | Got product 6 300 44 | Got product 7 2100 45 | Handling command Reset {id=0x000a; newSum= 10; newProduct= 100} 46 | Got sum 8 26 47 | Handling command Num {id=0x000b; val= 11} 48 | Sending command Num {id=0x0012; val= 18} 49 | Got sum 9 35 50 | Sending command Num {id=0x0013; val= 19} 51 | Got product 8 16800 52 | Got product 9 151200 53 | Handling command Num {id=0x000c; val= 12} 54 | Got sum 10 10 55 | Handling command Num {id=0x000d; val= 13} 56 | Sending command Reset {id=0x0014; newSum= 20; newProduct= 200} 57 | Got sum 11 21 58 | Got product 10 100 59 | Got product 11 1100 60 | Handling command Num {id=0x000e; val= 14} 61 | Got sum 12 33 62 | Handling command Reset {id=0x000f; newSum= 15; newProduct= 150} 63 | Got sum 13 46 64 | Got product 12 13200 65 | Got product 13 171600 66 | Handling command Num {id=0x0010; val= 16} 67 | Got sum 14 60 68 | Handling command Num {id=0x0011; val= 17} 69 | Got sum 15 15 70 | Got product 14 2402400 71 | Got product 15 150 72 | Handling command Num {id=0x0012; val= 18} 73 | Got sum 16 31 74 | Handling command Num {id=0x0013; val= 19} 75 | Got sum 17 48 76 | Got product 16 2400 77 | Got product 17 40800 78 | Handling command Reset {id=0x0014; newSum= 20; newProduct= 200} 79 | Got sum 18 66 80 | Got sum 19 85 81 | Got product 18 734400 82 | Got product 19 13953600 83 | Got sum 20 20 84 | Got product 20 200 85 | -------------------------------------------------------------------------------- /testing/bsc.contrib/GenC/GenCMsg/counter_driver.c.keep: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | 6 | #include "counter.h" 7 | 8 | CounterMsgs_state state; 9 | bool initialized = false; 10 | 11 | unsigned j = 0, k = 0; 12 | unsigned responses = 0; 13 | 14 | #define NUM_ITERS 100 15 | 16 | void runHostAction() { 17 | Result_int16 sumResult; 18 | if (dequeue_CounterMsgs_sums(&state, &sumResult)) { 19 | printf("==== Sum %hu: %hd ====\n", sumResult.id, sumResult.val); 20 | responses++; 21 | } 22 | Result_int32 productResult; 23 | if (dequeue_CounterMsgs_products(&state, &productResult)) { 24 | printf("==== Product %hu: %hd ====\n", productResult.id, productResult.val); 25 | responses++; 26 | } 27 | 28 | for (unsigned i = 0; i < random() % 10; i++) { 29 | if (k >= NUM_ITERS) break; 30 | 31 | uint16_t id = j + k * 6; 32 | 33 | // Send 5 sequential Val commands, followed by a Reset 34 | Command command = {Command_Num, {.Num = {id, j + 1}}}; 35 | if (j == 5) { 36 | command.tag = Command_Reset; 37 | command.contents.Reset = k + 2; 38 | } 39 | if (enqueue_CounterMsgs_commands(&state, command)) { 40 | printf("Enqueued command %hu\n", id); 41 | j++; 42 | if (j > 5) { 43 | j = 0; 44 | k++; 45 | } 46 | } else break; 47 | } 48 | 49 | // Halt after the expected number of responses have been received 50 | static bool sent_halt = false; 51 | if (responses >= NUM_ITERS * 10 && !sent_halt) { 52 | printf("Enqueued halt\n"); 53 | enqueue_CounterMsgs_commands(&state, (Command){Command_Halt}); 54 | sent_halt = true; 55 | } 56 | } 57 | 58 | uint8_t out_buf[size_tx_CounterMsgs] = {0}; 59 | bool avail = false; 60 | 61 | unsigned char messageAvailable() { 62 | if (!initialized) { 63 | init_CounterMsgs(&state); 64 | initialized = true; 65 | } 66 | 67 | // Run a step of the "host app" whenever availability is polled, emulating an 68 | // independent process on the host machine. 69 | // In reality this would be run from the same top-level event loop that is 70 | // listening on a serial port, or in a seperate thread of the host process. 71 | runHostAction(); 72 | 73 | if (!avail) { 74 | size_t size = encode_CounterMsgs(&state, out_buf); 75 | avail = size > 0; 76 | } 77 | return avail; 78 | } 79 | 80 | unsigned long long getMessage() { 81 | if (!initialized) { 82 | init_CounterMsgs(&state); 83 | initialized = true; 84 | } 85 | 86 | if (!avail) { 87 | size_t size = encode_CounterMsgs(&state, out_buf); 88 | avail = size > 0; 89 | } 90 | 91 | //printf("C sending message %hhx %hhx %hhx %hhx %hhx %hhx %hhx\n", out_buf[0], out_buf[1], out_buf[2], out_buf[3], out_buf[4], out_buf[5], out_buf[6]); 92 | 93 | unsigned long long out = 0; 94 | for (int i = 0; i < size_tx_CounterMsgs; i++) { 95 | out <<= 8; 96 | out |= out_buf[i]; 97 | } 98 | memset(out_buf, 0, sizeof(out_buf)); 99 | avail = false; 100 | 101 | return out; 102 | } 103 | 104 | unsigned char putMessage(unsigned long long in) { 105 | if (!initialized) { 106 | init_CounterMsgs(&state); 107 | initialized = true; 108 | } 109 | 110 | uint8_t in_buf[size_rx_CounterMsgs]; 111 | for (int i = size_rx_CounterMsgs - 1; i >= 0; i--) { 112 | in_buf[i] = in & 0xFF; 113 | in >>= 8; 114 | } 115 | 116 | //printf("C received message %hhx %hhx %hhx %hhx %hhx %hhx %hhx\n", in_buf[0], in_buf[1], in_buf[2], in_buf[3], in_buf[4], in_buf[5], in_buf[6]); 117 | 118 | _Bool result = decode_CounterMsgs(&state, in_buf); 119 | return result; 120 | } 121 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLM2Reduce.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLM2Reduce; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import SpecialFIFOs::*; 12 | import FIFO::*; 13 | import GetPut::*; 14 | import TLM2Defines::*; 15 | 16 | `include "TLM.defines" 17 | 18 | //////////////////////////////////////////////////////////////////////////////// 19 | /// Convert a stream of (arbitrary) TLM ops into a stream with only single 20 | /// reads and single writes. 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | module mkTLMReducer (TLMTransformIFC#(req_t, resp_t)) 24 | provisos(TLMRequestTC#(req_t, `TLM_PRM), 25 | TLMResponseTC#(resp_t, `TLM_PRM), 26 | Bits#(req_t, s0), 27 | Bits#(resp_t, s1), 28 | Bits#(RequestDescriptor#(`TLM_PRM), s2)); 29 | 30 | Reg#(RequestDescriptor#(`TLM_PRM)) desc_reg <- mkReg(?); 31 | Reg#(TLMUInt#(`TLM_PRM)) count <- mkReg(0); 32 | 33 | FIFO#(resp_t) fifo_in_tx <- mkBypassFIFO; 34 | FIFO#(req_t) fifo_in_rx <- mkBypassFIFO; 35 | FIFO#(req_t) fifo_out_tx <- mkBypassFIFO; 36 | FIFO#(resp_t) fifo_out_rx <- mkBypassFIFO; 37 | 38 | let rx_in = toTLMRequest(fifo_in_rx.first); 39 | 40 | rule read_op_first (rx_in matches tagged Descriptor .d 41 | &&& d.command matches READ 42 | &&& (count == 0)); 43 | let desc_current = d; 44 | desc_current.burst_length = 1; 45 | fifo_out_tx.enq(fromTLMRequest(tagged Descriptor desc_current)); 46 | desc_reg <= incrTLMAddr(d); 47 | 48 | let remaining = d.burst_length - 1; 49 | count <= remaining; 50 | if (remaining == 0) fifo_in_rx.deq; 51 | endrule 52 | 53 | rule read_op_rest (rx_in matches tagged Descriptor .d 54 | &&& d.command matches READ 55 | &&& (count > 0)); 56 | let desc_current = desc_reg; 57 | desc_current.burst_length = 1; 58 | fifo_out_tx.enq(fromTLMRequest(tagged Descriptor desc_current)); 59 | desc_reg <= incrTLMAddr(desc_reg); 60 | 61 | let remaining = count - 1; 62 | count <= remaining; 63 | if (remaining == 0) fifo_in_rx.deq; 64 | endrule 65 | 66 | rule write_op_first (rx_in matches tagged Descriptor .d 67 | &&& d.command matches WRITE); 68 | let desc_current = d; 69 | desc_current.burst_length = 1; 70 | fifo_out_tx.enq(fromTLMRequest(tagged Descriptor desc_current)); 71 | desc_reg <= incrTLMAddr(d); 72 | 73 | fifo_in_rx.deq; 74 | endrule 75 | 76 | rule write_op_rest (rx_in matches tagged Data .d); 77 | let desc_current = desc_reg; 78 | desc_current.burst_length = 1; 79 | desc_current.data = d.data; 80 | fifo_out_tx.enq(fromTLMRequest(tagged Descriptor desc_current)); 81 | desc_reg <= incrTLMAddr(desc_reg); 82 | 83 | fifo_in_rx.deq; 84 | endrule 85 | 86 | // for now just pass on responses 87 | rule pass_on_responses; 88 | let response = fifo_out_rx.first; 89 | fifo_in_tx.enq(response); 90 | fifo_out_rx.deq; 91 | endrule 92 | 93 | interface TLMRecvIFC in; 94 | interface Get tx = toGet(fifo_in_tx); 95 | interface Put rx = toPut(fifo_in_rx); 96 | endinterface 97 | 98 | interface TLMSendIFC out; 99 | interface Get tx = toGet(fifo_out_tx); 100 | interface Put rx = toPut(fifo_out_rx); 101 | endinterface 102 | 103 | endmodule 104 | 105 | 106 | endpackage 107 | -------------------------------------------------------------------------------- /testing/bsc.contrib/AzureIP/DMADefines.bsv: -------------------------------------------------------------------------------- 1 | package DMADefines; 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | /// 5 | //////////////////////////////////////////////////////////////////////////////// 6 | 7 | import CBus::*; 8 | import Randomizable::*; 9 | import TLM::*; 10 | 11 | `include "TLM.defines" 12 | 13 | //////////////////////////////////////////////////////////////////////////////// 14 | /// 15 | //////////////////////////////////////////////////////////////////////////////// 16 | 17 | typedef 1 NumChannels; 18 | 19 | //////////////////////////////////////////////////////////////////////////////// 20 | /// 21 | //////////////////////////////////////////////////////////////////////////////// 22 | 23 | // Values currently selected so Transfer descriptor will fit in 32 bits. 24 | typedef TransferDescriptor#(`TLM_STD_TYPES) TransferDescriptorStd; 25 | typedef Bit#(11) DescAddr; 26 | typedef Bit#(6) DescLen; 27 | 28 | typedef struct {DescAddr source; 29 | DescAddr dest; 30 | DescLen length; 31 | } TransferDescriptor#(`TLM_TYPE_PRMS) deriving (Eq, Bits, Bounded); 32 | 33 | 34 | instance Randomizable#(TransferDescriptor#(`TLM_TYPES)); 35 | 36 | module mkRandomizer (Randomize#(TransferDescriptor#(`TLM_TYPES))); 37 | 38 | Randomize#(DescLen) length_gen <- mkGenericRandomizer; 39 | Randomize#(Bit#(9)) dest_gen <- mkGenericRandomizer; 40 | Randomize#(Bit#(9)) source_gen <- mkGenericRandomizer; 41 | 42 | interface Control cntrl; 43 | method Action init(); 44 | source_gen.cntrl.init(); 45 | dest_gen.cntrl.init(); 46 | length_gen.cntrl.init(); 47 | endmethod 48 | endinterface 49 | 50 | method ActionValue#(TransferDescriptor#(`TLM_TYPES)) next (); 51 | 52 | let descriptor = unpack(0); 53 | 54 | let source <- source_gen.next; 55 | let dest <- dest_gen.next; 56 | let length <- length_gen.next; 57 | 58 | descriptor.source = {source, 0}; 59 | descriptor.dest = {dest, 0}; 60 | descriptor.length = length; 61 | 62 | return descriptor; 63 | endmethod 64 | 65 | endmodule 66 | 67 | endinstance 68 | 69 | //////////////////////////////////////////////////////////////////////////////// 70 | /// Configuration Register Types 71 | //////////////////////////////////////////////////////////////////////////////// 72 | 73 | typedef 12 DCBusAddrWidth; 74 | typedef 32 DCBusDataWidth; 75 | 76 | typedef CBus#(DCBusAddrWidth, 32) DCBus; 77 | typedef ModWithCBus#(DCBusAddrWidth, 32, i) DModWithCBus#(type i); 78 | 79 | typedef CRAddr#(DCBusAddrWidth,DCBusDataWidth) DCAddr; 80 | 81 | //////////////////////////////////////////////////////////////////////////////// 82 | /// Configuration Register Locations 83 | //////////////////////////////////////////////////////////////////////////////// 84 | 85 | DCAddr statusAddr = DCAddr {a: 12'h000, o: 0}; 86 | 87 | //////////////////////////////////////////////////////////////////////////////// 88 | /// Configuration Register Locations For Each Channel 89 | //////////////////////////////////////////////////////////////////////////////// 90 | 91 | DCAddr descriptorAddrBase = DCAddr {a: 12'h100, o: 0}; 92 | DCAddr activeAddrBase = DCAddr {a: 12'h104, o: 0}; 93 | 94 | function DCAddr calculateDCAddrForChannel(DCAddr base, Bit#(12) channel); 95 | let delta = DCAddr { a: (channel * 12'h020), o: 0}; 96 | let addr = base + delta; 97 | return addr; 98 | endfunction 99 | 100 | //////////////////////////////////////////////////////////////////////////////// 101 | /// 102 | //////////////////////////////////////////////////////////////////////////////// 103 | 104 | 105 | endpackage 106 | -------------------------------------------------------------------------------- /Libraries/FPGA/DDR2/DDR2Types.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | import Clocks::*; 6 | import Connectable::*; 7 | import GetPut::*; 8 | 9 | typedef Bit#(32) DDR2Address; 10 | typedef Bit#(64) DDR2Data; 11 | 12 | // DDR2ReqCmd 13 | // A request command. 14 | // You specify read or write and a memory address. 15 | // For write requests, the data to be written is supplied separately. 16 | typedef struct { 17 | Bool rnw; 18 | DDR2Address addr; 19 | } DDR2ReqCmd deriving(Bits, Eq); 20 | 21 | // Write request data. 22 | // The data to write to memory when you've sent a write request command. 23 | // be - byte enable, it specifies which bytes to in the data should be 24 | // written. 25 | // data - The data to write. 26 | typedef struct { 27 | Bit#(8) be; 28 | DDR2Data data; 29 | } DDR2ReqData deriving(Bits, Eq); 30 | 31 | 32 | // DDR2Client interface. 33 | // For reads the server will take the request command and put the data read 34 | // some number of cycles later. 35 | // For writes the server will take the request command and the request data. 36 | // No response is given to writes. 37 | interface DDR2RequestClient; 38 | interface Get#(DDR2ReqCmd) command; 39 | interface Get#(DDR2ReqData) data; 40 | endinterface 41 | 42 | interface DDR2Client; 43 | interface DDR2RequestClient request; 44 | interface Put#(DDR2Data) response; 45 | endinterface 46 | 47 | interface DDR2RequestServer; 48 | interface Put#(DDR2ReqCmd) command; 49 | interface Put#(DDR2ReqData) data; 50 | endinterface 51 | 52 | interface DDR2Server; 53 | interface DDR2RequestServer request; 54 | interface Get#(DDR2Data) response; 55 | endinterface 56 | 57 | instance Connectable#(DDR2RequestClient, DDR2RequestServer); 58 | module mkConnection#(DDR2RequestClient client, DDR2RequestServer server)(Empty); 59 | mkConnection(client.command, server.command); 60 | mkConnection(client.data, server.data); 61 | endmodule 62 | endinstance 63 | 64 | instance Connectable#(DDR2RequestServer, DDR2RequestClient); 65 | module mkConnection#(DDR2RequestServer server, DDR2RequestClient client)(Empty); 66 | mkConnection(client, server); 67 | endmodule 68 | endinstance 69 | 70 | instance Connectable#(DDR2Client, DDR2Server); 71 | module mkConnection#(DDR2Client client, DDR2Server server)(Empty); 72 | mkConnection(client.request, server.request); 73 | mkConnection(client.response, server.response); 74 | endmodule 75 | endinstance 76 | 77 | instance Connectable#(DDR2Server, DDR2Client); 78 | module mkConnection#(DDR2Server server, DDR2Client client)(Empty); 79 | mkConnection(client, server); 80 | endmodule 81 | endinstance 82 | 83 | // Brings a DDR2Client from one clock domain to another. 84 | module mkDDR2ClientSync#(DDR2Client ddr2, 85 | Clock sclk, Reset srst, Clock dclk, Reset drst 86 | ) (DDR2Client); 87 | 88 | SyncFIFOIfc#(DDR2ReqCmd) cmds <- mkSyncFIFO(2, sclk, srst, dclk); 89 | SyncFIFOIfc#(DDR2ReqData) wdata <- mkSyncFIFO(2, sclk, srst, dclk); 90 | SyncFIFOIfc#(DDR2Data) rdata <- mkSyncFIFO(2, dclk, drst, sclk); 91 | 92 | mkConnection(toPut(cmds), toGet(ddr2.request.command)); 93 | mkConnection(toPut(wdata), toGet(ddr2.request.data)); 94 | mkConnection(toGet(rdata), toPut(ddr2.response)); 95 | 96 | interface DDR2RequestClient request; 97 | interface Get command = toGet(cmds); 98 | interface Get data = toGet(wdata); 99 | endinterface 100 | 101 | interface Put response = toPut(rdata); 102 | endmodule 103 | 104 | 105 | interface SimpleMemory; 106 | method Action request ( Bool write, UInt#(31) addr, Bit#(256) data, Bit#(32) be); 107 | interface Get#(Bit#(256)) readData; 108 | endinterface 109 | 110 | 111 | 112 | 113 | -------------------------------------------------------------------------------- /testing/bsc.contrib/VerilogRepr/chess.svh.expected: -------------------------------------------------------------------------------- 1 | package chess; 2 | 3 | 4 | localparam MAX_SCORE = 9'd500; 5 | localparam MAX_WEIGHT = 3'd4; 6 | localparam MAX_DEPTH = 5'd16; 7 | localparam COLOR_TAG_WIDTH = 1'd1; 8 | localparam NUM_COLOR = 2'd2; 9 | typedef enum logic [0:0] { 10 | COLOR_WHITE = 1'd0, 11 | COLOR_BLACK = 1'd1 12 | } color_tag_t; 13 | 14 | // Color 15 | typedef color_tag_t color_t; 16 | 17 | localparam PIECE_KIND_TAG_WIDTH = 2'd3; 18 | localparam NUM_PIECE_KIND = 3'd6; 19 | typedef enum logic [2:0] { 20 | PIECE_KIND_PAWN = 3'd0, 21 | PIECE_KIND_KNIGHT = 3'd1, 22 | PIECE_KIND_BISHOP = 3'd2, 23 | PIECE_KIND_ROOK = 3'd3, 24 | PIECE_KIND_QUEEN = 3'd4, 25 | PIECE_KIND_KING = 3'd5 26 | } piece_kind_tag_t; 27 | 28 | // PieceKind 29 | typedef piece_kind_tag_t piece_kind_t; 30 | 31 | // Piece 32 | typedef struct packed { 33 | color_t color; 34 | piece_kind_t kind; 35 | } piece_t; 36 | 37 | // Maybe Piece 38 | typedef struct packed { 39 | logic has_value; 40 | piece_t value; 41 | } option_piece_t; 42 | 43 | // PlayerHistory 44 | typedef struct packed { 45 | logic has_pawn_moved2; 46 | logic [2:0] pawn_moved2; 47 | logic king_moved; 48 | logic k_rook_moved; 49 | logic q_rook_moved; 50 | logic castled; 51 | } player_history_t; 52 | 53 | // State 54 | typedef struct packed { 55 | color_t turn; 56 | option_piece_t [7:0][7:0] board; 57 | player_history_t white_hist; 58 | player_history_t black_hist; 59 | logic [5:0] last_progress_move; 60 | } state_t; 61 | 62 | // Int 9 63 | typedef logic signed [8:0] int9_t; 64 | 65 | // Config (UInt 2) 66 | typedef struct packed { 67 | logic [1:0] material_value; 68 | logic [1:0] center_control_value; 69 | logic [1:0] extended_center_control_value; 70 | logic [1:0] castle_value; 71 | logic [1:0] pawn_structure_value; 72 | } config_uint2_t; 73 | 74 | // SearchQuery (Config (UInt 2)) 500 16 75 | typedef struct packed { 76 | logic [7:0] rid; 77 | state_t state; 78 | logic [3:0] depth; 79 | logic get_moves; 80 | logic has_alpha; 81 | int9_t alpha; 82 | logic has_beta; 83 | int9_t beta; 84 | config_uint2_t conf; 85 | } search_query_config_uint2_500_16_t; 86 | 87 | localparam OUTCOME_TAG_WIDTH = 2'd2; 88 | localparam NUM_OUTCOME = 3'd4; 89 | typedef enum logic [1:0] { 90 | OUTCOME_NO_OUTCOME = 2'd0, 91 | OUTCOME_CHECK = 2'd1, 92 | OUTCOME_CHECK_MATE = 2'd2, 93 | OUTCOME_DRAW = 2'd3 94 | } outcome_tag_t; 95 | 96 | // Outcome 97 | typedef outcome_tag_t outcome_t; 98 | 99 | localparam MOVE_TAG_WIDTH = 2'd2; 100 | localparam NUM_MOVE = 3'd4; 101 | typedef enum logic [1:0] { 102 | MOVE_MOVE = 2'd0, 103 | MOVE_EN_PASSANT = 2'd1, 104 | MOVE_PROMOTE = 2'd2, 105 | MOVE_CASTLE = 2'd3 106 | } move_tag_t; 107 | 108 | // Position 109 | typedef struct packed { 110 | logic [2:0] rank; 111 | logic [2:0] file; 112 | } position_t; 113 | 114 | typedef struct packed { 115 | logic [2:0] pad; 116 | position_t from; 117 | position_t to; 118 | } move_move_t; 119 | 120 | typedef struct packed { 121 | logic [2:0] pad; 122 | position_t from; 123 | position_t to; 124 | } move_en_passant_t; 125 | 126 | typedef struct packed { 127 | piece_kind_t kind; 128 | position_t from; 129 | position_t to; 130 | } move_promote_t; 131 | 132 | typedef struct packed { 133 | logic [13:0] pad; 134 | logic king_side; 135 | } move_castle_t; 136 | 137 | typedef union packed { 138 | move_move_t move; 139 | move_en_passant_t en_passant; 140 | move_promote_t promote; 141 | move_castle_t castle; 142 | } move_content_t; 143 | 144 | // Move 145 | typedef struct packed { 146 | move_tag_t tag; 147 | move_content_t content; 148 | } move_t; 149 | 150 | // SearchResult 500 16 151 | typedef struct packed { 152 | logic [7:0] rid; 153 | outcome_t outcome; 154 | logic has_best_move; 155 | move_t best_move; 156 | logic forced_outcome; 157 | int9_t score; 158 | logic [3:0] depth; 159 | } search_result_500_16_t; 160 | 161 | endpackage 162 | -------------------------------------------------------------------------------- /Libraries/FPGA/DDR2/ML507_mig_33_wrapper.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | // DDR2 Wires 6 | (* always_ready, always_enabled *) 7 | interface DDR2Wires; 8 | interface Inout#(Bit#(64)) dq; 9 | method Bit#(13) a; 10 | method Bit#(2) ba; 11 | method Bit#(1) ras_n; 12 | method Bit#(1) cas_n; 13 | method Bit#(1) we_n; 14 | method Bit#(1) cs_n; 15 | method Bit#(1) odt; 16 | method Bit#(1) cke; 17 | method Bit#(8) dm; 18 | interface Inout#(Bit#(8)) dqs; 19 | interface Inout#(Bit#(8)) dqs_n; 20 | method Bit#(2) ck; 21 | method Bit#(2) ck_n; 22 | endinterface 23 | 24 | // Mig33 application interface. 25 | interface Mig33App; 26 | // Request a read or write. 27 | // cmd: 3'b000 - write 28 | // 3'b001 - read 29 | // addr: - Address 30 | method Action af(Bit#(3) cmd, Bit#(31) addr); 31 | 32 | // Data to use for writes. 33 | // Takes two 64 bit words and 2 8 bit masks which select which bytes to 34 | // update. 35 | method Action wdf(Bit#(128) data, Bit#(16) mask); 36 | 37 | // Read data. 38 | // This is not buffered, so if there is data ready, you better grab it 39 | // that cycle, otherwise the data will be lost. 40 | method Bit#(128) data(); 41 | endinterface 42 | 43 | interface Mig33; 44 | interface Clock clk0_tb; 45 | interface Reset rst0_tb; 46 | interface DDR2Wires ddr2; 47 | interface Mig33App app; 48 | endinterface 49 | 50 | import "BVI" mig_33_wrapper = 51 | module mkMig33Wrapper#( 52 | Clock clk0, 53 | Clock clk90, 54 | Clock clkdiv0, 55 | Clock clk200, 56 | Reset sys_rst_n, 57 | Bool locked 58 | ) (Mig33); 59 | 60 | default_clock no_clock; 61 | default_reset no_reset; 62 | 63 | input_clock (clk0, (*inhigh*)g1) = clk0; 64 | input_clock (clk90, (*inhigh*)g1) = clk90; 65 | input_clock (clkdiv0, (*inhigh*)g1) = clkdiv0; 66 | input_clock (clk200, (*inhigh*)g1) = clk200; 67 | input_reset sys_rst_n(sys_rst_n) = sys_rst_n; 68 | 69 | port locked = locked; 70 | 71 | output_clock clk0_tb(clk0_tb); 72 | output_reset rst0_tb(rst0_tb_n) clocked_by (clk0_tb); 73 | 74 | interface DDR2Wires ddr2; 75 | ifc_inout dq(ddr2_dq); 76 | method ddr2_a a; 77 | method ddr2_ba ba; 78 | method ddr2_ras_n ras_n; 79 | method ddr2_cas_n cas_n; 80 | method ddr2_we_n we_n; 81 | method ddr2_cs_n cs_n; 82 | method ddr2_odt odt; 83 | method ddr2_cke cke; 84 | method ddr2_dm dm; 85 | ifc_inout dqs(ddr2_dqs); 86 | ifc_inout dqs_n(ddr2_dqs_n); 87 | method ddr2_ck ck; 88 | method ddr2_ck_n ck_n; 89 | endinterface 90 | 91 | interface Mig33App app; 92 | method af(app_af_cmd, app_af_addr) 93 | enable(app_af_enable) 94 | ready(app_af_ready) 95 | clocked_by(clk0_tb) 96 | reset_by(rst0_tb); 97 | 98 | method wdf(app_wdf_data, app_wdf_mask_data) 99 | enable(app_wdf_enable) 100 | ready(app_wdf_ready) 101 | clocked_by(clk0_tb) 102 | reset_by(rst0_tb); 103 | 104 | method rd_data_out data 105 | ready(rd_data_ready) 106 | clocked_by(clk0_tb) 107 | reset_by(rst0_tb); 108 | 109 | endinterface 110 | 111 | // TODO: is this the right schedule? I'm worried... 112 | // Specifically: shouldn't af, and wdf be Conflicting with 113 | // themselves? 114 | schedule 115 | ( 116 | ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_cs_n, 117 | ddr2_odt, ddr2_cke, ddr2_dm, ddr2_ck, 118 | ddr2_ck_n, app_af, app_wdf, app_data 119 | ) 120 | CF 121 | ( 122 | ddr2_a, ddr2_ba, ddr2_ras_n, ddr2_cas_n, ddr2_we_n, ddr2_cs_n, 123 | ddr2_odt, ddr2_cke, ddr2_dm, ddr2_ck, 124 | ddr2_ck_n, app_af, app_wdf, app_data 125 | ); 126 | 127 | 128 | endmodule 129 | 130 | -------------------------------------------------------------------------------- /Libraries/VerilogRepr/Json.bs: -------------------------------------------------------------------------------- 1 | -- Author: Lucas Kramer (https://github.com/krame505) 2 | -- Copyright (c) 2024 MatX, Inc. 3 | package Json where 4 | 5 | import List 6 | import BuildList 7 | 8 | -- This is a generic library for encoding elaboration-time information as JSON. 9 | -- The schema is defined as types; values of these types can be converted to 10 | -- Json values as interpreted by the `JsonSchema` typeclass. 11 | -- See VerilogRepr.bs for an example of how this is used. 12 | 13 | -- Abstract syntax representation of JSON values 14 | data Json 15 | = JsonObject (List (String, Json)) 16 | | JsonArray (List Json) 17 | | JsonString String 18 | | JsonNumber Integer 19 | | JsonBool Bool 20 | | JsonNull 21 | 22 | showJson :: Json -> String 23 | showJson = 24 | let showJson' :: Integer -> Json -> String 25 | showJson' nest (JsonObject fields) = "{" +++ 26 | -- TODO: escape keys 27 | showItems nest 28 | (map (\ (key, value) -> 29 | "\"" +++ key +++ "\": " +++ showJson' (nest + 1) value) 30 | fields) +++ 31 | "}" 32 | showJson' nest (JsonArray elems) = "[" +++ 33 | showItems nest (map (showJson' (nest + 1)) elems) +++ 34 | "]" 35 | showJson' _ (JsonString str) = "\"" +++ str +++ "\"" -- TODO: escape 36 | showJson' _ (JsonNumber n) = integerToString n 37 | showJson' _ (JsonBool b) = if b then "true" else "false" 38 | showJson' _ JsonNull = "null" 39 | 40 | showItems :: Integer -> List String -> String 41 | showItems _ Nil = "" 42 | showItems nest lines = 43 | "\n" +++ makeIndent (nest + 1) +++ 44 | foldr1 (\ line res -> line +++ ",\n" +++ makeIndent (nest + 1) +++ res) 45 | lines +++ 46 | "\n" +++ makeIndent nest 47 | 48 | makeIndent :: Integer -> String 49 | makeIndent nest = foldr strConcat "" $ replicate nest " " 50 | in showJson' 0 51 | 52 | -- Convert a value of some schema type to a JSON value 53 | class JsonSchema a where 54 | toJson :: a -> Json 55 | 56 | instance JsonSchema Integer where 57 | toJson n = JsonNumber n 58 | 59 | instance JsonSchema String where 60 | toJson str = JsonString str 61 | 62 | instance JsonSchema Bool where 63 | toJson b = JsonBool b 64 | 65 | instance (JsonSchema a) => JsonSchema (List (String, a)) where 66 | toJson pairs = JsonObject $ map (\ (key, value) -> (key, toJson value)) pairs 67 | 68 | instance (JsonSchema a) => JsonSchema (List a) where 69 | toJson lst = JsonArray $ map toJson lst 70 | 71 | instance (Generic a r, JsonSchema' r) => JsonSchema a where 72 | toJson = toJson' ∘ from 73 | 74 | class JsonSchema' r where 75 | toJson' :: r -> Json 76 | 77 | instance (ToJsonObject r) => 78 | JsonSchema' (Meta (MetaData name pkg args 1) r) where 79 | toJson' (Meta x) = JsonObject $ toJsonObject x 80 | 81 | instance (ToJsonTag r) => JsonSchema' (Meta (MetaData name pkg args n) r) where 82 | toJson' (Meta x) = JsonString $ toJsonTag x 83 | 84 | class ToJsonObject r where 85 | toJsonObject :: r -> List (String, Json) 86 | 87 | instance ToJsonObject () where 88 | toJsonObject () = nil 89 | 90 | instance (ToJsonObject a, ToJsonObject b) => ToJsonObject (a, b) where 91 | toJsonObject (a, b) = toJsonObject a `append` toJsonObject b 92 | 93 | instance (ToJsonObject a) => ToJsonObject (Meta m a) where 94 | toJsonObject (Meta x) = toJsonObject x 95 | 96 | instance (JsonSchema a) => ToJsonObject (Meta (MetaField n i) (Conc a)) where 97 | toJsonObject (Meta (Conc x)) = lst (stringOf n, toJson x) 98 | 99 | instance (JsonSchema a) => 100 | ToJsonObject (Meta (MetaField n i) (Conc (Maybe a))) where 101 | toJsonObject (Meta (Conc (Just x))) = lst (stringOf n, toJson x) 102 | toJsonObject (Meta (Conc Nothing)) = nil 103 | 104 | class ToJsonTag r where 105 | toJsonTag :: r -> String 106 | 107 | instance (ToJsonTag a, ToJsonTag b) => ToJsonTag (Either a b) where 108 | toJsonTag (Left x) = toJsonTag x 109 | toJsonTag (Right x) = toJsonTag x 110 | 111 | instance ToJsonTag (Meta (MetaConsAnon name i nf) ()) where 112 | toJsonTag _ = stringOf name 113 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM3/TLM3/TLM.defines: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | `define TLM_PRM_DCL numeric type id_size, \ 6 | numeric type addr_size, \ 7 | numeric type data_size, \ 8 | numeric type length_size, \ 9 | numeric type user_size 10 | 11 | `define TLM_PRM id_size, \ 12 | addr_size, \ 13 | data_size, \ 14 | length_size, \ 15 | user_size 16 | 17 | `define TLM_PRM_STD 4, \ 18 | 32, \ 19 | 32, \ 20 | 8, \ 21 | 0 22 | 23 | //////////////////////////////////////////////////////////////////////////////// 24 | /// 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | `define TLM_RR_DCL type req_t, \ 28 | type resp_t 29 | 30 | `define TLM_RR req_t, \ 31 | resp_t 32 | 33 | `define TLM_RR_NSTD TLMRequest#(`TLM_PRM), \ 34 | TLMResponse#(`TLM_PRM) \ 35 | 36 | `define TLM_RR_STD TLMRequest#(`TLM_PRM_STD), \ 37 | TLMResponse#(`TLM_PRM_STD) \ 38 | 39 | //////////////////////////////////////////////////////////////////////////////// 40 | /// 41 | //////////////////////////////////////////////////////////////////////////////// 42 | 43 | `define TLM_XTR_DCL `TLM_RR_DCL, `TLM_PRM_DCL 44 | `define TLM_XTR `TLM_RR, `TLM_PRM 45 | `define TLM_XTR_STD `TLM_RR_STD, `TLM_PRM_STD 46 | 47 | //////////////////////////////////////////////////////////////////////////////// 48 | /// 49 | //////////////////////////////////////////////////////////////////////////////// 50 | 51 | `define TLM_TYPE_PRMS `TLM_PRM_DCL 52 | `define TLM_TYPES `TLM_PRM 53 | `define TLM_STD_TYPES `TLM_PRM_STD 54 | 55 | //////////////////////////////////////////////////////////////////////////////// 56 | /// 57 | //////////////////////////////////////////////////////////////////////////////// 58 | 59 | `define dv deriving(Bits,Eq) 60 | 61 | `define TLM_PRM_ID_EXT id_size_ext, \ 62 | addr_size, \ 63 | data_size, \ 64 | length_size, \ 65 | user_size 66 | 67 | `define TLM_PRM_L_EXT id_size, \ 68 | addr_size, \ 69 | data_size, \ 70 | length_size_ext, \ 71 | user_size 72 | 73 | `define TLM_PRM_REST addr_size, \ 74 | data_size, \ 75 | length_size, \ 76 | user_size 77 | 78 | //////////////////////////////////////////////////////////////////////////////// 79 | /// Add defines for stream transfers 80 | //////////////////////////////////////////////////////////////////////////////// 81 | 82 | `define TLM_T_DCL type trans_t 83 | `define TLM_T trans_t 84 | 85 | `define TLM_XT_DCL `TLM_T_DCL, `TLM_PRM_DCL 86 | `define TLM_XT `TLM_T, `TLM_PRM 87 | 88 | //////////////////////////////////////////////////////////////////////////////// 89 | /// Add versions with a parametrized suffix. 90 | //////////////////////////////////////////////////////////////////////////////// 91 | 92 | `define T_PRM_(sfx) id_size_`` sfx, \ 93 | addr_size_`` sfx, \ 94 | data_size_`` sfx, \ 95 | length_size_`` sfx, \ 96 | user_size_`` sfx 97 | 98 | `define T_PRM_DCL_(sfx) numeric type id_size_`` sfx, \ 99 | numeric type addr_size_`` sfx, \ 100 | numeric type data_size_`` sfx, \ 101 | numeric type length_size_`` sfx, \ 102 | numeric type user_size_`` sfx 103 | 104 | `define T_REQ_(sfx) req_t_`` sfx 105 | `define T_RSP_(sfx) resp_t_`` sfx 106 | 107 | `define T_RR_DCL_(sfx) type req_t_`` sfx, \ 108 | type resp_t_`` sfx 109 | 110 | `define T_RR_(sfx) req_t_`` sfx, \ 111 | resp_t_`` sfx 112 | 113 | `define T_XTR_DCL_(sfx) `T_RR_DCL_(sfx), `T_PRM_DCL_(sfx) 114 | `define T_XTR_(sfx) `T_RR_(sfx) , `T_PRM_(sfx) 115 | 116 | `define T_T_DCL_(sfx) type trans_t_`` sfx 117 | `define T_T_(sfx) trans_t_`` sfx 118 | 119 | `define T_XT_DCL_(sfx) `T_T_DCL_(sfx), `T_PRM_DCL_(sfx) 120 | `define T_XT_(sfx) `T_T_(sfx) , `T_PRM_(sfx) 121 | 122 | 123 | 124 | -------------------------------------------------------------------------------- /Libraries/GenC/GenCMsg/msgclient.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import threading 4 | import select 5 | import eventfd 6 | import time 7 | from cobs import cobs 8 | 9 | class Client: 10 | def __init__(self, name, ffi, lib, serial): 11 | self.name = name 12 | self.ffi = ffi 13 | self.lib = lib 14 | self.channelTypes = { 15 | fieldName[:-4]: field.type.item 16 | for fieldName, field in self.ffi.typeof(name + "_state").fields 17 | if fieldName.endswith('_buf') 18 | } 19 | self.serial = serial 20 | self._state = self.ffi.new(name + "_state *") 21 | getattr(self.lib, "init_" + name)(self._state) 22 | self._stateMutex = threading.Lock() 23 | self._txReady = eventfd.EventFD() 24 | self._txDone = eventfd.EventFD() 25 | 26 | def _run(self): 27 | rxData = [] 28 | self._stateMutex.acquire() 29 | while True: 30 | gotData = False 31 | for byte in self.serial.read(self.serial.in_waiting): 32 | if byte == 0: 33 | #print("Rx raw", bytes(rxData)) 34 | #print("Rx", cobs.decode(bytes(rxData))) 35 | gotData |= getattr(self.lib, "decode_" + self.name)(self._state, cobs.decode(bytes(rxData))) 36 | rxData.clear() 37 | else: 38 | rxData.append(byte) 39 | if gotData: 40 | self._stateMutex.release() 41 | self.notify() 42 | self._stateMutex.acquire() 43 | 44 | txArray = self.ffi.new("uint8_t[]", getattr(self.lib, "size_tx_" + self.name)) 45 | txSize = getattr(self.lib, "encode_" + self.name)(self._state, txArray) 46 | if txSize: 47 | while txSize: 48 | txData = bytes(txArray)[0:txSize] 49 | #print("Tx", txSize, txData) 50 | #print("Tx raw", cobs.encode(txData) + b'\0') 51 | self.serial.write(cobs.encode(txData) + b'\0') 52 | self._txDone.set() 53 | txSize = getattr(self.lib, "encode_" + self.name)(self._state, txArray) 54 | else: 55 | self._stateMutex.release() 56 | select.select([self.serial, self._txReady], [], []) 57 | self._stateMutex.acquire() 58 | self._txReady.clear() 59 | 60 | def start(self): 61 | """Start listening for and sending messages""" 62 | threading.Thread(target=self._run, daemon=True).start() 63 | 64 | def notify(self): 65 | """Method to be called when a message is received""" 66 | pass 67 | 68 | def put(self, channel, data): 69 | """Enqueue a message into a channel, blocks until there is space available""" 70 | if channel not in self.channelTypes: 71 | raise KeyError("{} does not have message channel {}".format(self.name, channel)) 72 | self._stateMutex.acquire() 73 | while not getattr(self.lib, "enqueue_{}_{}".format(self.name, channel))(self._state, data): 74 | self._stateMutex.release() 75 | self._txDone.wait() 76 | self._stateMutex.acquire() 77 | self._txDone.clear() 78 | 79 | self._txReady.set() 80 | self._stateMutex.release() 81 | 82 | def avail(self, channel): 83 | """Return the number of available messages in a channel""" 84 | if channel not in self.channelTypes: 85 | raise KeyError("{} does not have message channel {}".format(self.name, channel)) 86 | return getattr(self._state, channel + "_size") 87 | 88 | def get(self, channel): 89 | """Dequeues a message from a channel, or returns None if no message is available""" 90 | if channel not in self.channelTypes: 91 | raise KeyError("{} does not have message channel {}".format(self.name, channel)) 92 | res = self.ffi.new(self.channelTypes[channel].cname + " *") 93 | self._stateMutex.acquire() 94 | hasRes = getattr(self.lib, "dequeue_{}_{}".format(self.name, channel))(self._state, res) 95 | self._txReady.set() 96 | self._stateMutex.release() 97 | if hasRes: 98 | return res[0] 99 | -------------------------------------------------------------------------------- /Libraries/AMBA_TLM2/TLM/TLMReadWriteRam.bsv: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2020 Bluespec, Inc. All rights reserved. 2 | // 3 | // SPDX-License-Identifier: BSD-3-Clause 4 | 5 | package TLMReadWriteRam; 6 | 7 | //////////////////////////////////////////////////////////////////////////////// 8 | /// 9 | //////////////////////////////////////////////////////////////////////////////// 10 | 11 | import FShow::*; 12 | import GetPut::*; 13 | import Probe::*; 14 | import RegFile::*; 15 | import TLMDefines::*; 16 | import TLMUtils::*; 17 | import BUtils::*; 18 | 19 | `include "TLM.defines" 20 | 21 | //////////////////////////////////////////////////////////////////////////////// 22 | /// 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module mkTLMReadWriteRam#(parameter Bit#(4) id, Bool verbose) (TLMReadWriteRecvIFC#(`TLM_TYPES)) 26 | provisos(Bits#(TLMRequest#(`TLM_TYPES), s0), 27 | Bits#(TLMResponse#(`TLM_TYPES), s1), 28 | FShow#(TLMRequest#(`TLM_TYPES)), 29 | FShow#(TLMResponse#(`TLM_TYPES))); 30 | 31 | Wire#(TLMRequest#(`TLM_TYPES)) read_in_wire <- mkWire; 32 | Wire#(TLMResponse#(`TLM_TYPES)) read_out_wire <- mkWire; 33 | Wire#(TLMRequest#(`TLM_TYPES)) write_in_wire <- mkWire; 34 | Wire#(TLMResponse#(`TLM_TYPES)) write_out_wire <- mkWire; 35 | 36 | RegFile#(Bit#(8), Bit#(data_size)) ram <- mkRegFileLoad("ram_init.text", 0, 255); 37 | 38 | rule read_op (read_in_wire matches tagged Descriptor .d 39 | &&& d.command == READ 40 | &&& d.burst_length == 1); 41 | 42 | TLMResponse#(`TLM_TYPES) response = createBasicTLMResponse(); 43 | Bit#(10) addr = zExtend(d.addr); 44 | Bit#(8) mem_addr = grab_left(addr); 45 | TLMData#(`TLM_TYPES) data = ram.sub(mem_addr); 46 | response.data = maskTLMData(d.byte_enable, data); 47 | response.status = SUCCESS; 48 | response.transaction_id = d.transaction_id; 49 | response.command = READ; 50 | 51 | read_out_wire <= response; 52 | 53 | if (verbose) $display("(%0d) TM (%0d) %0d Read Op %h %h", $time, id, d.transaction_id, d.addr, response.data); 54 | 55 | endrule 56 | 57 | rule write_op (write_in_wire matches tagged Descriptor .d 58 | &&& d.command == WRITE 59 | &&& d.burst_length == 1); 60 | 61 | Bit#(10) addr = zExtend(d.addr); 62 | Bit#(8) mem_addr = grab_left(addr); 63 | TLMData#(`TLM_TYPES) data_orig = ram.sub(mem_addr); 64 | TLMData#(`TLM_TYPES) data_new = overwriteTLMData(d.byte_enable, data_orig, d.data); 65 | ram.upd(mem_addr, data_new); 66 | 67 | TLMResponse#(`TLM_TYPES) response = createBasicTLMResponse(); 68 | response.status = SUCCESS; 69 | response.transaction_id = d.transaction_id; 70 | response.command = WRITE; 71 | 72 | write_out_wire <= response; 73 | 74 | if (verbose) $display("(%0d) TM (%0d) %0d Write Op %h %h", $time, id, d.transaction_id, d.addr, d.data); 75 | 76 | endrule 77 | 78 | rule read_error_op (read_in_wire matches tagged Descriptor .d 79 | &&& (d.burst_length > 1)); 80 | $display("(%0d) ERROR: TLMReadWriteRAM (%0d) (cannot handle ops with burst length > 1).", $time, id); 81 | endrule 82 | 83 | rule write_error_op (write_in_wire matches tagged Descriptor .d 84 | &&& (d.burst_length > 1)); 85 | $display("(%0d) ERROR: TLMReadWriteRAM (%0d) (cannot handle ops with burst length > 1).", $time, id); 86 | endrule 87 | 88 | interface TLMRecvIFC read; 89 | interface Get tx; 90 | method get; 91 | actionvalue 92 | return read_out_wire; 93 | endactionvalue 94 | endmethod 95 | endinterface 96 | interface Put rx; 97 | method Action put (x); 98 | read_in_wire <= x; 99 | endmethod 100 | endinterface 101 | endinterface 102 | 103 | interface TLMRecvIFC write; 104 | interface Get tx; 105 | method get; 106 | actionvalue 107 | return write_out_wire; 108 | endactionvalue 109 | endmethod 110 | endinterface 111 | interface Put rx; 112 | method Action put (x); 113 | write_in_wire <= x; 114 | endmethod 115 | endinterface 116 | endinterface 117 | 118 | 119 | endmodule 120 | 121 | endpackage 122 | --------------------------------------------------------------------------------