├── 01_四路视频拼接+视频移动 ├── 01_four_channel_viideo_splicer │ ├── td_project │ │ ├── al_ip │ │ │ ├── ddr_ip.adc │ │ │ ├── ddr_ip.ipc │ │ │ ├── ddr_ip.mif │ │ │ ├── ddr_ip.sdc │ │ │ ├── ddr_ip.v │ │ │ ├── ddr_ip_1.mif │ │ │ ├── ddr_ip_1.txt │ │ │ ├── ddr_ip_dbg.mif │ │ │ ├── pll.ipc │ │ │ ├── pll.v │ │ │ └── pll.vhd │ │ ├── fpga_prj.al │ │ └── fpga_prj_Runs │ │ │ └── best_result │ │ │ ├── fpga_prj.bit │ │ │ ├── fpga_prj_inst.bid │ │ │ └── readMe.txt │ └── user_source │ │ ├── constraints_source │ │ ├── ap106_ddr_pin.adc │ │ ├── pin.adc │ │ └── timing.sdc │ │ └── hdl_source │ │ ├── design_top_wrapper.v │ │ ├── down_samping │ │ └── down_samping_2x2.v │ │ ├── four_channel_video_splicer.v │ │ ├── ph1a_hdmi_tx_lvds │ │ ├── hdmi_edid_receiver_wrapper.v │ │ ├── hdmi_phy_wrapper.v │ │ ├── hdmi_tx.v │ │ └── hdmi_tx_controller_wrapper.v │ │ ├── tpg │ │ ├── uitpg_0.v │ │ ├── uitpg_1.v │ │ ├── uitpg_2.v │ │ └── uitpg_3.v │ │ ├── uibuf_interconnect │ │ └── uidbufw_interconnect.v │ │ ├── uifdma │ │ ├── uiFDMA.v │ │ └── uifdma_axi_ddr.v │ │ ├── uifdmadbuf │ │ ├── fs_cap.v │ │ ├── rfifo │ │ │ ├── rfifo.ipc │ │ │ ├── rfifo.tcl │ │ │ └── rfifo.v │ │ ├── uidbuf.v │ │ ├── uidbuf_only_w.v │ │ └── wfifo │ │ │ ├── wfifo.ipc │ │ │ ├── wfifo.tcl │ │ │ └── wfifo.v │ │ ├── uisetvbuf │ │ └── uisetvbuf.v │ │ ├── vtc │ │ └── uivtc.v │ │ └── width_conversion │ │ ├── rd_width_convert.v │ │ └── wr_width_convert.v ├── 02_four_channel_viideo_splicer_move │ ├── td_project │ │ ├── al_ip │ │ │ ├── ddr_ip.adc │ │ │ ├── ddr_ip.ipc │ │ │ ├── ddr_ip.mif │ │ │ ├── ddr_ip.sdc │ │ │ ├── ddr_ip.v │ │ │ ├── ddr_ip_1.mif │ │ │ ├── ddr_ip_1.txt │ │ │ ├── ddr_ip_dbg.mif │ │ │ ├── pll.ipc │ │ │ ├── pll.v │ │ │ └── pll.vhd │ │ ├── fpga_prj.al │ │ └── fpga_prj_Runs │ │ │ └── best_result │ │ │ ├── fpga_prj.bit │ │ │ ├── fpga_prj_inst.bid │ │ │ └── readMe.txt │ └── user_source │ │ ├── constraints_source │ │ ├── ap106_ddr_pin.adc │ │ ├── pin.adc │ │ └── timing.sdc │ │ └── hdl_source │ │ ├── design_top_wrapper.v │ │ ├── down_samping │ │ └── down_samping_2x2.v │ │ ├── four_channel_video_splicer_move.v │ │ ├── ph1a_hdmi_tx_lvds │ │ ├── hdmi_edid_receiver_wrapper.v │ │ ├── hdmi_phy_wrapper.v │ │ ├── hdmi_tx.v │ │ └── hdmi_tx_controller_wrapper.v │ │ ├── tpg │ │ ├── uitpg_0.v │ │ ├── uitpg_1.v │ │ ├── uitpg_2.v │ │ └── uitpg_3.v │ │ ├── uart │ │ ├── command_parsing.v │ │ ├── uart_trans.v │ │ ├── uiuart_rx.v │ │ └── uiuart_tx.v │ │ ├── uibuf_interconnect │ │ ├── uidbufr_interconnect.v │ │ └── uidbufw_interconnect.v │ │ ├── uifdma │ │ ├── uiFDMA.v │ │ └── uifdma_axi_ddr.v │ │ ├── uifdmadbuf │ │ ├── fs_cap.v │ │ ├── rfifo │ │ │ ├── rfifo.ipc │ │ │ ├── rfifo.tcl │ │ │ └── rfifo.v │ │ ├── uidbuf.v │ │ └── wfifo │ │ │ ├── wfifo.ipc │ │ │ ├── wfifo.tcl │ │ │ └── wfifo.v │ │ ├── uisetvbuf │ │ └── uisetvbuf.v │ │ ├── vtc │ │ ├── uivtc.v │ │ └── uivtc_video_move.v │ │ └── width_conversion │ │ ├── rd_width_convert.v │ │ └── wr_width_convert.v └── README.md ├── 02_四分屏显示与全屏自由切换 └── 03_split_screen_full_screen_switch │ ├── README.md │ ├── td_project │ ├── al_ip │ │ ├── ddr_ip.adc │ │ ├── ddr_ip.ipc │ │ ├── ddr_ip.mif │ │ ├── ddr_ip.sdc │ │ ├── ddr_ip.v │ │ ├── ddr_ip_1.mif │ │ ├── ddr_ip_1.txt │ │ ├── ddr_ip_dbg.mif │ │ ├── pll.ipc │ │ ├── pll.v │ │ └── pll.vhd │ ├── fpga_prj.al │ └── fpga_prj_Runs │ │ └── best_result │ │ ├── fpga_prj.bit │ │ ├── fpga_prj_inst.bid │ │ └── readMe.txt │ └── user_source │ ├── constraints_source │ ├── ap106_ddr_pin.adc │ ├── pin.adc │ └── timing.sdc │ └── hdl_source │ ├── design_top_wrapper.v │ ├── down_samping │ └── down_samping_2x2.v │ ├── four_channel_video_splicer_move.v │ ├── full_screen_switch.v │ ├── ph1a_hdmi_tx_lvds │ ├── hdmi_edid_receiver_wrapper.v │ ├── hdmi_phy_wrapper.v │ ├── hdmi_tx.v │ └── hdmi_tx_controller_wrapper.v │ ├── tpg │ ├── uitpg_0.v │ ├── uitpg_1.v │ ├── uitpg_2.v │ └── uitpg_3.v │ ├── uart │ ├── command_parsing.v │ ├── uart_trans.v │ ├── uiuart_rx.v │ └── uiuart_tx.v │ ├── uibuf_interconnect │ ├── uidbufr_interconnect.v │ └── uidbufw_interconnect.v │ ├── uifdma │ ├── uiFDMA.v │ └── uifdma_axi_ddr.v │ ├── uifdmadbuf │ ├── fs_cap.v │ ├── rfifo │ │ ├── rfifo.ipc │ │ ├── rfifo.tcl │ │ └── rfifo.v │ ├── uidbuf.v │ ├── uidbuf_only_w.v │ ├── uidbuf_r_baseaddr_switch.v │ └── wfifo │ │ ├── wfifo.ipc │ │ ├── wfifo.tcl │ │ └── wfifo.v │ ├── uisetvbuf │ └── uisetvbuf.v │ ├── vtc │ ├── uivtc.v │ └── uivtc_video_move.v │ └── width_conversion │ ├── rd_width_convert.v │ └── wr_width_convert.v ├── 03_任意角度视频旋转 ├── 04_video_rotate_180 │ ├── td_project │ │ ├── al_ip │ │ │ ├── ddr_ip.adc │ │ │ ├── ddr_ip.ipc │ │ │ ├── ddr_ip.mif │ │ │ ├── ddr_ip.sdc │ │ │ ├── ddr_ip.v │ │ │ ├── ddr_ip_1.mif │ │ │ ├── ddr_ip_1.txt │ │ │ ├── ddr_ip_dbg.mif │ │ │ ├── hdmi_pll.ipc │ │ │ ├── hdmi_pll.v │ │ │ ├── hdmi_pll.vhd │ │ │ ├── ila │ │ │ │ ├── .m_params_ila.txt │ │ │ │ ├── .params_ila.txt │ │ │ │ ├── .ports_ila.txt │ │ │ │ ├── ChipWatcher_e89d8dc9dd72.sv │ │ │ │ ├── Design.xml │ │ │ │ ├── DesignConfiguration.xml │ │ │ │ ├── ila.sv │ │ │ │ └── ila.xml │ │ │ ├── pll.ipc │ │ │ ├── pll.v │ │ │ └── pll.vhd │ │ ├── chip_debugger │ │ │ └── user.cwc │ │ ├── fpga_prj.al │ │ └── fpga_prj_Runs │ │ │ └── best_result │ │ │ ├── fpga_prj.bit │ │ │ ├── fpga_prj_compress.bit │ │ │ ├── fpga_prj_inst.bid │ │ │ └── readMe.txt │ └── user_source │ │ ├── constraints_source │ │ ├── ap106_ddr_pin.adc │ │ ├── pin.adc │ │ └── timing.sdc │ │ └── hdl_source │ │ ├── design_top_wrapper.v │ │ ├── down_samping │ │ └── down_samping_2x2.v │ │ ├── hdmi_in │ │ ├── dram_10bit.v │ │ ├── edid_1280720.mif │ │ ├── hdmi_1_4b_receiver_core_wrapper.enc.v │ │ ├── hdmi_rx_phy_wrapper.v │ │ └── lane_lvds_1_10.v │ │ ├── ph1a_hdmi_tx_lvds │ │ ├── hdmi_edid_receiver_wrapper.v │ │ ├── hdmi_phy_wrapper.v │ │ ├── hdmi_tx.v │ │ └── hdmi_tx_controller_wrapper.v │ │ ├── uibuf_interconnect │ │ └── uidbufr_interconnect.v │ │ ├── uifdma │ │ ├── uiFDMA.v │ │ └── uifdma_axi_ddr.v │ │ ├── uifdmadbuf │ │ ├── fs_cap.v │ │ ├── ram_rd_buf │ │ │ ├── ram_rd_buf.ipc │ │ │ ├── ram_rd_buf.v │ │ │ └── ram_rd_buf.vhd │ │ ├── rfifo │ │ │ ├── rfifo.ipc │ │ │ ├── rfifo.tcl │ │ │ └── rfifo.v │ │ ├── uidbuf.v │ │ ├── uidbuf_only_r_rotate_180.v │ │ └── wfifo │ │ │ ├── wfifo.ipc │ │ │ ├── wfifo.tcl │ │ │ └── wfifo.v │ │ ├── uisetvbuf │ │ └── uisetvbuf.v │ │ ├── video_rotate_180_process.v │ │ ├── vtc │ │ └── uivtc_video_rotate_180.v │ │ └── width_conversion │ │ ├── rd_width_convert.v │ │ └── wr_width_convert.v └── README.md └── README.md /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/ddr_ip.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 18 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 19 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 20 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 21 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 24 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 25 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 34 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 35 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 36 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 37 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 38 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 39 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 40 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 41 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 46 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 47 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 49 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_hard_controller_0} {LOCATION = X65Y40Z0} 50 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_1$ph1_ddr_4lanes} {LOCATION = X81Y40Z0} 51 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_2$ph1_ddr_4lanes} {LOCATION = X81Y0Z0} 52 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll0/pll_inst} { LOCATION = X81Y39Z0} 53 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll1/pll_inst} { LOCATION = X81Y0Z0} 54 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/ddr_ip.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PH1_LOGIC_DDR_SDRAM 5 | 3.0 6 | PH1A90SBG484 7 | false 8 | ddr_ip 9 | DDR3 10 | MC and Standard PHY 11 | 1 12 | 2-1 13 | ENABLE 14 | ENABLE 15 | 4 16 | 533.000000 17 | MHz 18 | 25.000000 19 | MHz 20 | Bank31 21 | false 22 | 4:1 23 | false 24 | false 25 | false 26 | false 27 | 100.000000 28 | 100.000000 29 | 100.000000 30 | 100.000000 31 | MHz 32 | MHz 33 | MHz 34 | MHz 35 | 100.000000 36 | 100.000000 37 | 100.000000 38 | 100.000000 39 | MT41J128M16JT-125 40 | 1.5V 41 | 16 42 | false 43 | true 44 | Row_Column_Bank 45 | Normal 46 | Sequential 47 | RZQ/6 48 | RZQ/4 49 | Enable 50 | DISABLE 51 | DISABLE 52 | DISABLE 53 | ENABLE 54 | DISABLE 55 | ENABLE 56 | Pin 57 | L1,M3,K1,N2,K2,N3,K3,L3,R2,P1,U1,R3,T1,P2,R4,R1,M1,M2,N4,M5,L5,P4,Y9,W9,R7,AB6,U8,U6,W11,AA5,AA6,AB7,V9,V8,W6,AA11,U7,Y11,AA8,U12,AB8,AB10,AA10,V10,U10,Y6,AB11,T8 58 | None 59 | 60 | 61 | ddr_ip.adc 62 | ddr_ip.v 63 | ddr_ip.sdc 64 | 65 | 66 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/ddr_ip_1.txt: -------------------------------------------------------------------------------- 1 | 00000042 2 | 00000000 3 | 8000042a 4 | 00000010 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | ff55f0ff 12 | ffffff54 13 | ffff89ab 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | 05_08_0d_09 18 | 0a_06_04_07 19 | 00_01_00_02 20 | 0c_0b_01_00 21 | 00_00_00_00 22 | 02_07_08_0d 23 | 09_05_0a_06 24 | 00_01_00_04 25 | 0c_0b_01_00 26 | 00_00_00_00 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000830 66 | 00000004 67 | 00000008 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 06140704 75 | 281b0004 76 | 0003005b 77 | 82000000 78 | 00560504 79 | 001b0704 80 | 00000000 81 | 030b0200 82 | bb5d9999 83 | 030b0200 84 | bb5d9999 85 | 030b0200 86 | bb5d9999 87 | 030b0200 88 | bb5d9999 89 | 030b0200 90 | bb5d9999 91 | 030b0200 92 | bb5d9999 93 | 030b0200 94 | bb5d9999 95 | 030b0200 96 | bb5d9999 97 | 030b0200 98 | bb5d9999 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | 00000000 130 | 00000000 131 | 00000000 132 | 00000000 133 | 00000000 134 | 00000000 135 | 00000000 136 | 00000000 137 | 00000000 138 | 00000000 139 | 00000000 140 | 00000000 141 | 00000000 142 | 00000000 143 | 00000000 144 | 00000000 145 | 00000000 146 | 00000000 147 | 00000000 148 | 00000000 149 | 00000000 150 | 00000000 151 | 00000000 152 | 00000000 153 | 00000000 154 | 00000000 155 | 00000000 156 | 00000000 157 | 00000000 158 | 00000000 159 | 00000000 160 | 00000000 161 | 00000000 162 | 00000000 163 | 00000000 164 | 00000000 165 | 00000000 166 | 00000000 167 | 00000000 168 | 00000000 169 | 00000000 170 | 00000000 171 | 00000000 172 | 00000000 173 | 00000000 174 | 00000000 175 | 00000000 176 | 00000000 177 | 00000000 178 | 00000000 179 | 00000000 180 | 00000000 181 | 00000000 182 | 00000000 183 | 00000000 184 | 00000000 185 | 00000000 186 | 00000000 187 | 00000000 188 | 00000000 189 | 00000000 190 | 00000000 191 | 00000000 192 | 00000000 193 | 00000000 194 | 00000000 195 | 00000000 196 | 00000000 197 | 00000000 198 | 00000000 199 | 00000000 200 | 00000000 201 | 00000000 202 | 00000000 203 | 00000000 204 | 00000000 205 | 00000000 206 | 00000000 207 | 00000000 208 | 00000000 209 | 00000000 210 | 00000000 211 | 00000000 212 | 00000000 213 | 00000000 214 | 00000000 215 | 00000000 216 | 00000000 217 | 00000000 218 | 00000000 219 | 00000000 220 | 00000000 221 | 00000000 222 | 00000000 223 | 00000000 224 | 00000000 225 | 00000000 226 | 00000000 227 | 00000000 228 | 00000000 229 | 00000000 230 | 00000000 231 | 00000000 232 | 00000000 233 | 00000000 234 | 00000000 235 | 00000000 236 | 00000000 237 | 00000000 238 | 00000000 239 | 00000000 240 | 00000000 241 | 00000000 242 | 00000000 243 | 00000000 244 | 00000000 245 | 00000000 246 | 00000000 247 | 00000000 248 | 00000000 249 | 00000000 250 | 00000000 251 | 00000000 252 | 00000000 253 | 00000000 254 | 00000000 255 | 00000000 256 | 00000000 257 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | PH1A90SBG484 6 | true 7 | 8 | 9 | Any 10 | 25.0000000000000000MHz 11 | Normal 12 | CLKC0 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | DISABLE 17 | DISABLE 18 | DISABLE 19 | ENABLE 20 | ENABLE 21 | 22 | 23 | Medium 24 | 25 | 26 | frequncy_setting 27 | 3 28 | 1 29 | 30 | 31 | 0 32 | 15 33 | 75.0000000000000000MHz 34 | 0.0000000000000000deg 35 | 0.5 36 | false 37 | false 38 | BUFG 39 | 40 | 41 | 1 42 | 3 43 | 375.0000000000000000MHz 44 | 0.0000000000000000deg 45 | 0.5 46 | false 47 | false 48 | NONE 49 | 50 | 51 | 52 | 53 | pll.vhd 54 | pll.v 55 | 56 | 57 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2024 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.v 8 | ** Date : 2024 12 07 9 | ** TD version : 6.0.117864 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 25.000000MHz 14 | // Clock multiplication factor: 3 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 75.000000 MHZ | 0.0000 DEG 19 | // C1 | 375.000000MHZ | 0.0000 DEG 20 | /////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1 ns / 100 fs 22 | 23 | module pll ( 24 | refclk, 25 | reset, 26 | lock, 27 | clk0_out, 28 | clk1_out 29 | ); 30 | 31 | input refclk; 32 | input reset; 33 | output lock; 34 | output clk0_out; 35 | output clk1_out; 36 | 37 | wire clk0_buf; 38 | 39 | PH1_LOGIC_BUFG bufg_feedback ( 40 | .i(clk0_buf), 41 | .o(clk0_out) 42 | ); 43 | 44 | PH1_PHY_PLL #( 45 | .DYN_PHASE_PATH_SEL("DISABLE"), 46 | .DYN_FPHASE_EN("DISABLE"), 47 | .MPHASE_ENABLE("DISABLE"), 48 | .FIN("25.000000"), 49 | .FEEDBK_MODE("NORMAL"), 50 | .FBKCLK("CLKC0_EXT"), 51 | .PLL_FEED_TYPE("EXTERNAL"), 52 | .PLL_USR_RST("ENABLE"), 53 | .GMC_GAIN(1), 54 | .ICP_CUR(11), 55 | .LPF_CAP(2), 56 | .LPF_RES(3), 57 | .REFCLK_DIV(1), 58 | .FBCLK_DIV(3), 59 | .CLKC0_ENABLE("ENABLE"), 60 | .CLKC0_DIV(15), 61 | .CLKC0_CPHASE(14), 62 | .CLKC0_FPHASE(0), 63 | .CLKC0_FPHASE_RSTSEL(0), 64 | .CLKC0_DUTY_INT(8), 65 | .CLKC0_DUTY50("ENABLE"), 66 | .CLKC1_ENABLE("ENABLE"), 67 | .CLKC1_DIV(3), 68 | .CLKC1_CPHASE(2), 69 | .CLKC1_FPHASE(0), 70 | .CLKC1_FPHASE_RSTSEL(0), 71 | .CLKC1_DUTY_INT(2), 72 | .CLKC1_DUTY50("ENABLE"), 73 | .INTPI(1), 74 | .HIGH_SPEED_EN("DISABLE"), 75 | .SSC_ENABLE("DISABLE"), 76 | .SSC_MODE("CENTER"), 77 | .SSC_AMP(0.0000), 78 | .SSC_FREQ_DIV(0), 79 | .SSC_RNGE(0), 80 | .FRAC_ENABLE("DISABLE"), 81 | .DITHER_ENABLE("DISABLE"), 82 | .SDM_FRAC(0) 83 | ) pll_inst ( 84 | .refclk(refclk), 85 | .pllreset(reset), 86 | .lock(lock), 87 | .pllpd(1'b0), 88 | .refclk_rst(1'b0), 89 | .wakeup(1'b0), 90 | .psclk(1'b0), 91 | .psdown(1'b0), 92 | .psstep(1'b0), 93 | .psclksel(3'b000), 94 | .psdone(pll_open0), 95 | .cps_step(2'b00), 96 | .drp_clk(1'b0), 97 | .drp_rstn(1'b1), 98 | .drp_sel(1'b0), 99 | .drp_rd(1'b0), 100 | .drp_wr(1'b0), 101 | .drp_addr(8'b00000000), 102 | .drp_wdata(8'b00000000), 103 | .drp_err(pll_open1), 104 | .drp_rdy(pll_open2), 105 | .drp_rdata({pll_open10, pll_open9, pll_open8, pll_open7, pll_open6, pll_open5, pll_open4, pll_open3}), 106 | .fbclk(clk0_out), 107 | .clkc({pll_open23, pll_open21, pll_open19, pll_open17, pll_open15, pll_open13, clk1_out, clk0_buf}), 108 | .clkcb({pll_open24, pll_open22, pll_open20, pll_open18, pll_open16, pll_open14, pll_open12, pll_open11}), 109 | .clkc_en({8'b00000011}), 110 | .clkc_rst(2'b00), 111 | .ext_freq_mod_clk(1'b0), 112 | .ext_freq_mod_en(1'b0), 113 | .ext_freq_mod_val(17'b00000000000000000), 114 | .ssc_en(1'b0) 115 | ); 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/al_ip/pll.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2024 Anlogic Inc. -- All Right Reserved. 3 | -------------------------------------------------------------- 4 | -- Log : This file is generated by Anlogic IP Generator. 5 | -- File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.vhd 6 | -- Date : 2024 12 07 7 | -- TD version : 6.0.117864 8 | -------------------------------------------------------------- 9 | 10 | ------------------------------------------------------------------------------- 11 | -- Input frequency: 25.000000MHz 12 | -- Clock multiplication factor: 3 13 | -- Clock division factor: 1 14 | -- Clock information: 15 | -- Clock name | Frequency | Phase shift 16 | -- C0 | 75.000000 MHZ | 0.0000 DEG 17 | -- C1 | 375.000000MHZ | 0.0000 DEG 18 | ------------------------------------------------------------------------------- 19 | 20 | LIBRARY ieee; 21 | USE ieee.std_logic_1164.ALL; 22 | USE ieee.numeric_std.ALL; 23 | USE ieee.std_logic_unsigned.ALL; 24 | USE ieee.std_logic_arith.ALL; 25 | LIBRARY ph1_macro; 26 | USE ph1_macro.PH1_COMPONENTS.ALL; 27 | 28 | ENTITY pll IS 29 | PORT ( 30 | refclk : IN STD_LOGIC; 31 | reset : IN STD_LOGIC; 32 | lock : OUT STD_LOGIC; 33 | clk0_out : OUT STD_LOGIC; 34 | clk1_out : OUT STD_LOGIC 35 | ); 36 | END pll; 37 | 38 | ARCHITECTURE rtl OF pll IS 39 | SIGNAL clk0_buf : STD_LOGIC; 40 | SIGNAL fbk_wire : STD_LOGIC; 41 | SIGNAL clkc_en_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 42 | SIGNAL clkc_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 43 | SIGNAL clkcb_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 44 | BEGIN 45 | bufg_feedback : PH1_LOGIC_BUFG 46 | PORT MAP ( 47 | i => clk0_buf, 48 | o => fbk_wire 49 | ); 50 | 51 | pll_inst : PH1_PHY_PLL 52 | GENERIC MAP ( 53 | DYN_PHASE_PATH_SEL => "DISABLE", 54 | DYN_FPHASE_EN => "DISABLE", 55 | MPHASE_ENABLE => "DISABLE", 56 | FIN => "25.000000", 57 | FEEDBK_MODE => "NORMAL", 58 | FBKCLK => "CLKC0_EXT", 59 | PLL_FEED_TYPE => "EXTERNAL", 60 | PLL_USR_RST => "ENABLE", 61 | GMC_GAIN => 1, 62 | ICP_CUR => 11, 63 | LPF_CAP => 2, 64 | LPF_RES => 3, 65 | REFCLK_DIV => 1, 66 | FBCLK_DIV => 3, 67 | CLKC0_ENABLE => "ENABLE", 68 | CLKC0_DIV => 15, 69 | CLKC0_CPHASE => 14, 70 | CLKC0_FPHASE => 0, 71 | CLKC0_FPHASE_RSTSEL => 0, 72 | CLKC0_DUTY_INT => 8, 73 | CLKC0_DUTY50 => "ENABLE", 74 | CLKC1_ENABLE => "ENABLE", 75 | CLKC1_DIV => 3, 76 | CLKC1_CPHASE => 2, 77 | CLKC1_FPHASE => 0, 78 | CLKC1_FPHASE_RSTSEL => 0, 79 | CLKC1_DUTY_INT => 2, 80 | CLKC1_DUTY50 => "ENABLE", 81 | INTPI => 1, 82 | HIGH_SPEED_EN => "DISABLE", 83 | SSC_ENABLE => "DISABLE", 84 | SSC_MODE => "CENTER", 85 | SSC_AMP => 0.0000, 86 | SSC_FREQ_DIV => 0, 87 | SSC_RNGE => 0, 88 | FRAC_ENABLE => "DISABLE", 89 | DITHER_ENABLE => "DISABLE", 90 | SDM_FRAC => 0 91 | ) 92 | PORT MAP ( 93 | refclk => refclk, 94 | pllreset => reset, 95 | lock => lock, 96 | pllpd => '0', 97 | refclk_rst => '0', 98 | wakeup => '0', 99 | psclk => '0', 100 | psdown => '0', 101 | psstep => '0', 102 | psclksel => b"000", 103 | cps_step => b"00", 104 | drp_clk => '0', 105 | drp_rstn => '1', 106 | drp_sel => '0', 107 | drp_rd => '0', 108 | drp_wr => '0', 109 | drp_addr => b"00000000", 110 | drp_wdata => b"00000000", 111 | fbclk => fbk_wire, 112 | clkc => clkc_wire, 113 | clkcb => clkcb_wire, 114 | clkc_en => clkc_en_wire, 115 | clkc_rst => b"00", 116 | ext_freq_mod_clk => '0', 117 | ext_freq_mod_en => '0', 118 | ext_freq_mod_val => b"00000000000000000", 119 | ssc_en => '0' 120 | ); 121 | 122 | clk0_out <= fbk_wire; 123 | clkc_en_wire <= b"00000011"; 124 | clk1_out <= clkc_wire(1); 125 | clk0_buf <= clkc_wire(0); 126 | 127 | END rtl; 128 | 129 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/fpga_prj_Runs/best_result/fpga_prj.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/fpga_prj_Runs/best_result/fpga_prj.bit -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/td_project/fpga_prj_Runs/best_result/readMe.txt: -------------------------------------------------------------------------------- 1 | The implemented result of phy_1 is saved as best result. 2 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/constraints_source/ap106_ddr_pin.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dq[16] } {LOCATION = U3; IOSTANDARD = SSTL15; } 18 | set_ippin_assignment { ddr_dq[17] } {LOCATION = W2; IOSTANDARD = SSTL15; } 19 | set_ippin_assignment { ddr_dq[18] } {LOCATION = T4; IOSTANDARD = SSTL15; } 20 | set_ippin_assignment { ddr_dq[19] } {LOCATION = W4; IOSTANDARD = SSTL15; } 21 | set_ippin_assignment { ddr_dq[20] } {LOCATION = V4; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dq[21] } {LOCATION = U5; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_dq[22] } {LOCATION = V3; IOSTANDARD = SSTL15; } 24 | set_ippin_assignment { ddr_dq[23] } {LOCATION = T5; IOSTANDARD = SSTL15; } 25 | set_ippin_assignment { ddr_dq[24] } {LOCATION = AA3; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_dq[25] } {LOCATION = W1; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_dq[26] } {LOCATION = AB3; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_dq[27] } {LOCATION = AB2; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_dq[28] } {LOCATION = W5; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_dq[29] } {LOCATION = AB1; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_dq[30] } {LOCATION = AA1; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_dq[31] } {LOCATION = Y1; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 34 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 35 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 36 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 37 | set_ippin_assignment { ddr_dqs_n[2] } {LOCATION = V2; IOSTANDARD = DIFF_SSTL15; } 38 | set_ippin_assignment { ddr_dqs_p[2] } {LOCATION = U2; IOSTANDARD = DIFF_SSTL15; } 39 | set_ippin_assignment { ddr_dqs_n[3] } {LOCATION = Y2; IOSTANDARD = DIFF_SSTL15; } 40 | set_ippin_assignment { ddr_dqs_p[3] } {LOCATION = Y3; IOSTANDARD = DIFF_SSTL15; } 41 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_dm[2] } {LOCATION = N5; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_dm[3] } {LOCATION = AA4; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 46 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 47 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 49 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 50 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 51 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 52 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 53 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 54 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 55 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 56 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 57 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 58 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 59 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 60 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 61 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 62 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 63 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 64 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 65 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 66 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 67 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 68 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 69 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 70 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 71 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/constraints_source/pin.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment { I_rst_n } { LOCATION = K4; IOSTANDARD = LVCMOS15; PULLTYPE = PULLUP; } 2 | set_pin_assignment { I_sys_clk } { LOCATION = N18; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; } 3 | 4 | set_pin_assignment { O_uart_txd } { LOCATION = R22 ; IOSTANDARD = LVCMOS33;} 5 | set_pin_assignment { I_uart_rxd } { LOCATION = M16 ; IOSTANDARD = LVCMOS33; } 6 | 7 | set_pin_assignment { O_hdmi_tx_p[0] } { LOCATION = V13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 8 | set_pin_assignment { O_hdmi_tx_p[1] } { LOCATION = Y12; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 9 | set_pin_assignment { O_hdmi_tx_p[2] } { LOCATION = T13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 10 | set_pin_assignment { O_hdmi_clk_p } { LOCATION = V17; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 11 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/constraints_source/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name {sys_clk_25m} -period 40.000 -waveform {0.000 20.000} [get_ports {I_sys_clk}] 2 | derive_pll_clocks -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/down_samping/down_samping_2x2.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:33:13 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:33:33 6 | */ 7 | 8 | 9 | module down_samping_2x2#( 10 | parameter [13:0] H_SIZE = 1920, 11 | parameter [13:0] V_SIZE = 1080 12 | ) 13 | ( 14 | input wire I_clk, 15 | input wire I_rst_n, 16 | 17 | input wire I_rgb_vs, 18 | input wire I_rgb_de, 19 | input wire [31:0] I_rgb_data, 20 | 21 | output reg O_rgb_vs, 22 | output reg O_rgb_de, 23 | output reg [31:0] O_rgb_data 24 | 25 | ); 26 | 27 | reg [11:0] col_count, row_count; 28 | 29 | 30 | wire vs_up_edge; 31 | 32 | assign vs_up_edge = I_rgb_vs &(~O_rgb_vs) ; 33 | 34 | always @(posedge I_clk or negedge I_rst_n) begin 35 | if (!I_rst_n) begin 36 | col_count <= 0; 37 | end else if (vs_up_edge) begin 38 | col_count <= 0; 39 | end else if (I_rgb_de) begin 40 | if (col_count == (H_SIZE- 1)) begin 41 | col_count <= 0; 42 | end else begin 43 | col_count <= col_count + 1; 44 | end 45 | end else begin 46 | col_count<=col_count; 47 | end 48 | end 49 | 50 | always @(posedge I_clk or negedge I_rst_n) begin 51 | if (!I_rst_n) begin 52 | row_count <= 0; 53 | end else if (vs_up_edge) begin 54 | row_count <= 0; 55 | end else if (I_rgb_de) begin 56 | if (row_count == (V_SIZE - 1) && col_count == (H_SIZE - 1)) begin 57 | row_count <= 0; 58 | end else if (col_count == (H_SIZE- 1)) begin 59 | row_count <= row_count + 1; 60 | end 61 | end else begin 62 | row_count<=row_count; 63 | end 64 | end 65 | 66 | 67 | reg sample_select; 68 | // wire sample_select; 69 | 70 | // assign sample_select = (col_count % 2 == 0) && (row_count % 2 == 0); 71 | 72 | always @(*) begin 73 | if(!I_rst_n) begin 74 | sample_select<=1'b0; 75 | end else begin 76 | sample_select <= (col_count % 2 == 0) && (row_count % 2 == 0); 77 | end 78 | end 79 | 80 | always @(posedge I_clk or negedge I_rst_n) begin 81 | if (!I_rst_n) begin 82 | O_rgb_vs <= 0; 83 | end else begin 84 | O_rgb_vs<=I_rgb_vs; 85 | end 86 | end 87 | 88 | always @(posedge I_clk or negedge I_rst_n) begin 89 | if (!I_rst_n) begin 90 | O_rgb_de <= 0; 91 | end else if(I_rgb_de) begin 92 | O_rgb_de<=sample_select; 93 | end else begin 94 | O_rgb_de<=0; 95 | end 96 | end 97 | 98 | always @(posedge I_clk or negedge I_rst_n) begin 99 | if (!I_rst_n) begin 100 | O_rgb_data <= 'd0; 101 | end else if(sample_select) begin 102 | O_rgb_data<=I_rgb_data; 103 | end 104 | end 105 | 106 | 107 | 108 | 109 | 110 | endmodule //video_samping 111 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_0.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_1.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_2.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/tpg/uitpg_3.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdma/uiFDMA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdma/uiFDMA.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdma/uifdma_axi_ddr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdma/uifdma_axi_ddr.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/fs_cap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop: https://milianke.taobao.com 9 | *Create Date: 2022/09/25 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 3.1 20 | *Signal description 21 | *1) _i input 22 | *2) _o output 23 | *3) _n activ low 24 | *4) _dg debug signal 25 | *5) _r delay or register 26 | *6) _s state mechine 27 | *********************************************************************/ 28 | 29 | 30 | module fs_cap#( 31 | parameter integer VIDEO_ENABLE = 1 32 | ) 33 | ( 34 | input I_clk, 35 | input I_rstn, 36 | input I_vs, 37 | output reg O_fs_cap 38 | ); 39 | 40 | //----CH0_CNT_FS�źŵ�ƽ���� ʵ�ʾ��Dz���VS�ź�---------------- 41 | reg[4:0]CNT_FS = 6'b0; 42 | reg[4:0]CNT_FS_n = 6'b0; 43 | reg FS = 1'b0; 44 | (* ASYNC_REG = "TRUE" *) reg vs_i_r1; 45 | (* ASYNC_REG = "TRUE" *) reg vs_i_r2; 46 | (* ASYNC_REG = "TRUE" *) reg vs_i_r3; 47 | (* ASYNC_REG = "TRUE" *) reg vs_i_r4; 48 | //----ͬ�����ε�·��֮ǰ����û�����ε�·�������Dzɼ�vs����----- 49 | always@(posedge I_clk) begin 50 | vs_i_r1 <= I_vs; 51 | vs_i_r2 <= vs_i_r1; 52 | vs_i_r3 <= vs_i_r2; 53 | vs_i_r4 <= vs_i_r3; 54 | end 55 | 56 | always@(posedge I_clk) begin 57 | if(!I_rstn)begin 58 | O_fs_cap <= 1'd0; 59 | end 60 | else if(VIDEO_ENABLE == 1)begin 61 | if({vs_i_r4,vs_i_r3} == 2'b01)begin 62 | O_fs_cap <= 1'b1; 63 | end 64 | else begin 65 | O_fs_cap <= 1'b0; 66 | end 67 | end 68 | else begin 69 | O_fs_cap <= vs_i_r4; 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 253 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 2048 11 | 32 12 | Enable 13 | 256 14 | 256 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | rfifo 22 | 23 | 24 | rfifo.v 25 | rfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/uidbuf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/uidbuf.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/uidbuf_only_w.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/uidbuf_only_w.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 2045 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 256 11 | 256 12 | Enable 13 | 2048 14 | 32 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | wfifo 22 | 23 | 24 | wfifo.v 25 | wfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/uisetvbuf/uisetvbuf.v: -------------------------------------------------------------------------------- 1 | 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop1: https://milianke.taobao.com 9 | *Create Date: 2023/03/23 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 1.1 20 | *Signal description 21 | *1) I_ input 22 | *2) O_ output 23 | *3) IO_ input output 24 | *3) S_ system internal signal 25 | *3) _n activ low 26 | *4) _dg debug signal 27 | *5) _r delay or register 28 | *6) _s state mechine 29 | *********************************************************************/ 30 | `timescale 1ns / 1ps 31 | 32 | module uisetvbuf#( 33 | parameter integer BUF_DELAY = 1, 34 | parameter integer BUF_LENTH = 3 35 | ) 36 | ( 37 | 38 | input [7 :0] I_bufn, 39 | output [7 :0] O_bufn 40 | ); 41 | 42 | 43 | 44 | assign O_bufn = I_bufn < BUF_DELAY? (BUF_LENTH - BUF_DELAY + I_bufn) : (I_bufn - BUF_DELAY) ; 45 | 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/vtc/uivtc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/vtc/uivtc.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/width_conversion/rd_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:20 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:20 6 | */ 7 | 8 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 9 | module rd_width_convert( 10 | input wire [15:0] I_rd_data, 11 | 12 | output wire [31:0] O_rd_data 13 | ); 14 | 15 | 16 | assign O_rd_data ={8'd0,I_rd_data[15:11], 3'd0, I_rd_data[10:5], 2'd0,I_rd_data[4:0], 3'd0} ; 17 | 18 | 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/01_four_channel_viideo_splicer/user_source/hdl_source/width_conversion/wr_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:27 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:27 6 | */ 7 | 8 | 9 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 10 | module wr_width_convert( 11 | input wire [31:0] I_wr_data, 12 | 13 | output wire [15:0] O_wr_data 14 | ); 15 | 16 | assign O_wr_data = {I_wr_data[23:19],I_wr_data[15:10],I_wr_data[7:3]}; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/ddr_ip.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 18 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 19 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 20 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 21 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 24 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 25 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 34 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 35 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 36 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 37 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 38 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 39 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 40 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 41 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 46 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 47 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 49 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_hard_controller_0} {LOCATION = X65Y40Z0} 50 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_1$ph1_ddr_4lanes} {LOCATION = X81Y40Z0} 51 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_2$ph1_ddr_4lanes} {LOCATION = X81Y0Z0} 52 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll0/pll_inst} { LOCATION = X81Y39Z0} 53 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll1/pll_inst} { LOCATION = X81Y0Z0} 54 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/ddr_ip.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PH1_LOGIC_DDR_SDRAM 5 | 3.0 6 | PH1A90SBG484 7 | false 8 | ddr_ip 9 | DDR3 10 | MC and Standard PHY 11 | 1 12 | 2-1 13 | ENABLE 14 | ENABLE 15 | 4 16 | 533.000000 17 | MHz 18 | 25.000000 19 | MHz 20 | Bank31 21 | false 22 | 4:1 23 | false 24 | false 25 | false 26 | false 27 | 100.000000 28 | 100.000000 29 | 100.000000 30 | 100.000000 31 | MHz 32 | MHz 33 | MHz 34 | MHz 35 | 100.000000 36 | 100.000000 37 | 100.000000 38 | 100.000000 39 | MT41J128M16JT-125 40 | 1.5V 41 | 16 42 | false 43 | true 44 | Row_Column_Bank 45 | Normal 46 | Sequential 47 | RZQ/6 48 | RZQ/4 49 | Enable 50 | DISABLE 51 | DISABLE 52 | DISABLE 53 | ENABLE 54 | DISABLE 55 | ENABLE 56 | Pin 57 | L1,M3,K1,N2,K2,N3,K3,L3,R2,P1,U1,R3,T1,P2,R4,R1,M1,M2,N4,M5,L5,P4,Y9,W9,R7,AB6,U8,U6,W11,AA5,AA6,AB7,V9,V8,W6,AA11,U7,Y11,AA8,U12,AB8,AB10,AA10,V10,U10,Y6,AB11,T8 58 | None 59 | 60 | 61 | ddr_ip.adc 62 | ddr_ip.v 63 | ddr_ip.sdc 64 | 65 | 66 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/ddr_ip_1.txt: -------------------------------------------------------------------------------- 1 | 00000042 2 | 00000000 3 | 8000042a 4 | 00000010 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | ff55f0ff 12 | ffffff54 13 | ffff89ab 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | 05_08_0d_09 18 | 0a_06_04_07 19 | 00_01_00_02 20 | 0c_0b_01_00 21 | 00_00_00_00 22 | 02_07_08_0d 23 | 09_05_0a_06 24 | 00_01_00_04 25 | 0c_0b_01_00 26 | 00_00_00_00 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000830 66 | 00000004 67 | 00000008 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 06140704 75 | 281b0004 76 | 0003005b 77 | 82000000 78 | 00560504 79 | 001b0704 80 | 00000000 81 | 030b0200 82 | bb5d9999 83 | 030b0200 84 | bb5d9999 85 | 030b0200 86 | bb5d9999 87 | 030b0200 88 | bb5d9999 89 | 030b0200 90 | bb5d9999 91 | 030b0200 92 | bb5d9999 93 | 030b0200 94 | bb5d9999 95 | 030b0200 96 | bb5d9999 97 | 030b0200 98 | bb5d9999 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | 00000000 130 | 00000000 131 | 00000000 132 | 00000000 133 | 00000000 134 | 00000000 135 | 00000000 136 | 00000000 137 | 00000000 138 | 00000000 139 | 00000000 140 | 00000000 141 | 00000000 142 | 00000000 143 | 00000000 144 | 00000000 145 | 00000000 146 | 00000000 147 | 00000000 148 | 00000000 149 | 00000000 150 | 00000000 151 | 00000000 152 | 00000000 153 | 00000000 154 | 00000000 155 | 00000000 156 | 00000000 157 | 00000000 158 | 00000000 159 | 00000000 160 | 00000000 161 | 00000000 162 | 00000000 163 | 00000000 164 | 00000000 165 | 00000000 166 | 00000000 167 | 00000000 168 | 00000000 169 | 00000000 170 | 00000000 171 | 00000000 172 | 00000000 173 | 00000000 174 | 00000000 175 | 00000000 176 | 00000000 177 | 00000000 178 | 00000000 179 | 00000000 180 | 00000000 181 | 00000000 182 | 00000000 183 | 00000000 184 | 00000000 185 | 00000000 186 | 00000000 187 | 00000000 188 | 00000000 189 | 00000000 190 | 00000000 191 | 00000000 192 | 00000000 193 | 00000000 194 | 00000000 195 | 00000000 196 | 00000000 197 | 00000000 198 | 00000000 199 | 00000000 200 | 00000000 201 | 00000000 202 | 00000000 203 | 00000000 204 | 00000000 205 | 00000000 206 | 00000000 207 | 00000000 208 | 00000000 209 | 00000000 210 | 00000000 211 | 00000000 212 | 00000000 213 | 00000000 214 | 00000000 215 | 00000000 216 | 00000000 217 | 00000000 218 | 00000000 219 | 00000000 220 | 00000000 221 | 00000000 222 | 00000000 223 | 00000000 224 | 00000000 225 | 00000000 226 | 00000000 227 | 00000000 228 | 00000000 229 | 00000000 230 | 00000000 231 | 00000000 232 | 00000000 233 | 00000000 234 | 00000000 235 | 00000000 236 | 00000000 237 | 00000000 238 | 00000000 239 | 00000000 240 | 00000000 241 | 00000000 242 | 00000000 243 | 00000000 244 | 00000000 245 | 00000000 246 | 00000000 247 | 00000000 248 | 00000000 249 | 00000000 250 | 00000000 251 | 00000000 252 | 00000000 253 | 00000000 254 | 00000000 255 | 00000000 256 | 00000000 257 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | PH1A90SBG484 6 | true 7 | 8 | 9 | Any 10 | 25.0000000000000000MHz 11 | Normal 12 | CLKC0 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | DISABLE 17 | DISABLE 18 | DISABLE 19 | ENABLE 20 | ENABLE 21 | 22 | 23 | Medium 24 | 25 | 26 | frequncy_setting 27 | 3 28 | 1 29 | 30 | 31 | 0 32 | 15 33 | 75.0000000000000000MHz 34 | 0.0000000000000000deg 35 | 0.5 36 | false 37 | false 38 | BUFG 39 | 40 | 41 | 1 42 | 3 43 | 375.0000000000000000MHz 44 | 0.0000000000000000deg 45 | 0.5 46 | false 47 | false 48 | NONE 49 | 50 | 51 | 52 | 53 | pll.vhd 54 | pll.v 55 | 56 | 57 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2024 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.v 8 | ** Date : 2024 12 07 9 | ** TD version : 6.0.117864 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 25.000000MHz 14 | // Clock multiplication factor: 3 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 75.000000 MHZ | 0.0000 DEG 19 | // C1 | 375.000000MHZ | 0.0000 DEG 20 | /////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1 ns / 100 fs 22 | 23 | module pll ( 24 | refclk, 25 | reset, 26 | lock, 27 | clk0_out, 28 | clk1_out 29 | ); 30 | 31 | input refclk; 32 | input reset; 33 | output lock; 34 | output clk0_out; 35 | output clk1_out; 36 | 37 | wire clk0_buf; 38 | 39 | PH1_LOGIC_BUFG bufg_feedback ( 40 | .i(clk0_buf), 41 | .o(clk0_out) 42 | ); 43 | 44 | PH1_PHY_PLL #( 45 | .DYN_PHASE_PATH_SEL("DISABLE"), 46 | .DYN_FPHASE_EN("DISABLE"), 47 | .MPHASE_ENABLE("DISABLE"), 48 | .FIN("25.000000"), 49 | .FEEDBK_MODE("NORMAL"), 50 | .FBKCLK("CLKC0_EXT"), 51 | .PLL_FEED_TYPE("EXTERNAL"), 52 | .PLL_USR_RST("ENABLE"), 53 | .GMC_GAIN(1), 54 | .ICP_CUR(11), 55 | .LPF_CAP(2), 56 | .LPF_RES(3), 57 | .REFCLK_DIV(1), 58 | .FBCLK_DIV(3), 59 | .CLKC0_ENABLE("ENABLE"), 60 | .CLKC0_DIV(15), 61 | .CLKC0_CPHASE(14), 62 | .CLKC0_FPHASE(0), 63 | .CLKC0_FPHASE_RSTSEL(0), 64 | .CLKC0_DUTY_INT(8), 65 | .CLKC0_DUTY50("ENABLE"), 66 | .CLKC1_ENABLE("ENABLE"), 67 | .CLKC1_DIV(3), 68 | .CLKC1_CPHASE(2), 69 | .CLKC1_FPHASE(0), 70 | .CLKC1_FPHASE_RSTSEL(0), 71 | .CLKC1_DUTY_INT(2), 72 | .CLKC1_DUTY50("ENABLE"), 73 | .INTPI(1), 74 | .HIGH_SPEED_EN("DISABLE"), 75 | .SSC_ENABLE("DISABLE"), 76 | .SSC_MODE("CENTER"), 77 | .SSC_AMP(0.0000), 78 | .SSC_FREQ_DIV(0), 79 | .SSC_RNGE(0), 80 | .FRAC_ENABLE("DISABLE"), 81 | .DITHER_ENABLE("DISABLE"), 82 | .SDM_FRAC(0) 83 | ) pll_inst ( 84 | .refclk(refclk), 85 | .pllreset(reset), 86 | .lock(lock), 87 | .pllpd(1'b0), 88 | .refclk_rst(1'b0), 89 | .wakeup(1'b0), 90 | .psclk(1'b0), 91 | .psdown(1'b0), 92 | .psstep(1'b0), 93 | .psclksel(3'b000), 94 | .psdone(pll_open0), 95 | .cps_step(2'b00), 96 | .drp_clk(1'b0), 97 | .drp_rstn(1'b1), 98 | .drp_sel(1'b0), 99 | .drp_rd(1'b0), 100 | .drp_wr(1'b0), 101 | .drp_addr(8'b00000000), 102 | .drp_wdata(8'b00000000), 103 | .drp_err(pll_open1), 104 | .drp_rdy(pll_open2), 105 | .drp_rdata({pll_open10, pll_open9, pll_open8, pll_open7, pll_open6, pll_open5, pll_open4, pll_open3}), 106 | .fbclk(clk0_out), 107 | .clkc({pll_open23, pll_open21, pll_open19, pll_open17, pll_open15, pll_open13, clk1_out, clk0_buf}), 108 | .clkcb({pll_open24, pll_open22, pll_open20, pll_open18, pll_open16, pll_open14, pll_open12, pll_open11}), 109 | .clkc_en({8'b00000011}), 110 | .clkc_rst(2'b00), 111 | .ext_freq_mod_clk(1'b0), 112 | .ext_freq_mod_en(1'b0), 113 | .ext_freq_mod_val(17'b00000000000000000), 114 | .ssc_en(1'b0) 115 | ); 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/al_ip/pll.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2024 Anlogic Inc. -- All Right Reserved. 3 | -------------------------------------------------------------- 4 | -- Log : This file is generated by Anlogic IP Generator. 5 | -- File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.vhd 6 | -- Date : 2024 12 07 7 | -- TD version : 6.0.117864 8 | -------------------------------------------------------------- 9 | 10 | ------------------------------------------------------------------------------- 11 | -- Input frequency: 25.000000MHz 12 | -- Clock multiplication factor: 3 13 | -- Clock division factor: 1 14 | -- Clock information: 15 | -- Clock name | Frequency | Phase shift 16 | -- C0 | 75.000000 MHZ | 0.0000 DEG 17 | -- C1 | 375.000000MHZ | 0.0000 DEG 18 | ------------------------------------------------------------------------------- 19 | 20 | LIBRARY ieee; 21 | USE ieee.std_logic_1164.ALL; 22 | USE ieee.numeric_std.ALL; 23 | USE ieee.std_logic_unsigned.ALL; 24 | USE ieee.std_logic_arith.ALL; 25 | LIBRARY ph1_macro; 26 | USE ph1_macro.PH1_COMPONENTS.ALL; 27 | 28 | ENTITY pll IS 29 | PORT ( 30 | refclk : IN STD_LOGIC; 31 | reset : IN STD_LOGIC; 32 | lock : OUT STD_LOGIC; 33 | clk0_out : OUT STD_LOGIC; 34 | clk1_out : OUT STD_LOGIC 35 | ); 36 | END pll; 37 | 38 | ARCHITECTURE rtl OF pll IS 39 | SIGNAL clk0_buf : STD_LOGIC; 40 | SIGNAL fbk_wire : STD_LOGIC; 41 | SIGNAL clkc_en_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 42 | SIGNAL clkc_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 43 | SIGNAL clkcb_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 44 | BEGIN 45 | bufg_feedback : PH1_LOGIC_BUFG 46 | PORT MAP ( 47 | i => clk0_buf, 48 | o => fbk_wire 49 | ); 50 | 51 | pll_inst : PH1_PHY_PLL 52 | GENERIC MAP ( 53 | DYN_PHASE_PATH_SEL => "DISABLE", 54 | DYN_FPHASE_EN => "DISABLE", 55 | MPHASE_ENABLE => "DISABLE", 56 | FIN => "25.000000", 57 | FEEDBK_MODE => "NORMAL", 58 | FBKCLK => "CLKC0_EXT", 59 | PLL_FEED_TYPE => "EXTERNAL", 60 | PLL_USR_RST => "ENABLE", 61 | GMC_GAIN => 1, 62 | ICP_CUR => 11, 63 | LPF_CAP => 2, 64 | LPF_RES => 3, 65 | REFCLK_DIV => 1, 66 | FBCLK_DIV => 3, 67 | CLKC0_ENABLE => "ENABLE", 68 | CLKC0_DIV => 15, 69 | CLKC0_CPHASE => 14, 70 | CLKC0_FPHASE => 0, 71 | CLKC0_FPHASE_RSTSEL => 0, 72 | CLKC0_DUTY_INT => 8, 73 | CLKC0_DUTY50 => "ENABLE", 74 | CLKC1_ENABLE => "ENABLE", 75 | CLKC1_DIV => 3, 76 | CLKC1_CPHASE => 2, 77 | CLKC1_FPHASE => 0, 78 | CLKC1_FPHASE_RSTSEL => 0, 79 | CLKC1_DUTY_INT => 2, 80 | CLKC1_DUTY50 => "ENABLE", 81 | INTPI => 1, 82 | HIGH_SPEED_EN => "DISABLE", 83 | SSC_ENABLE => "DISABLE", 84 | SSC_MODE => "CENTER", 85 | SSC_AMP => 0.0000, 86 | SSC_FREQ_DIV => 0, 87 | SSC_RNGE => 0, 88 | FRAC_ENABLE => "DISABLE", 89 | DITHER_ENABLE => "DISABLE", 90 | SDM_FRAC => 0 91 | ) 92 | PORT MAP ( 93 | refclk => refclk, 94 | pllreset => reset, 95 | lock => lock, 96 | pllpd => '0', 97 | refclk_rst => '0', 98 | wakeup => '0', 99 | psclk => '0', 100 | psdown => '0', 101 | psstep => '0', 102 | psclksel => b"000", 103 | cps_step => b"00", 104 | drp_clk => '0', 105 | drp_rstn => '1', 106 | drp_sel => '0', 107 | drp_rd => '0', 108 | drp_wr => '0', 109 | drp_addr => b"00000000", 110 | drp_wdata => b"00000000", 111 | fbclk => fbk_wire, 112 | clkc => clkc_wire, 113 | clkcb => clkcb_wire, 114 | clkc_en => clkc_en_wire, 115 | clkc_rst => b"00", 116 | ext_freq_mod_clk => '0', 117 | ext_freq_mod_en => '0', 118 | ext_freq_mod_val => b"00000000000000000", 119 | ssc_en => '0' 120 | ); 121 | 122 | clk0_out <= fbk_wire; 123 | clkc_en_wire <= b"00000011"; 124 | clk1_out <= clkc_wire(1); 125 | clk0_buf <= clkc_wire(0); 126 | 127 | END rtl; 128 | 129 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/fpga_prj_Runs/best_result/fpga_prj.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/fpga_prj_Runs/best_result/fpga_prj.bit -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/td_project/fpga_prj_Runs/best_result/readMe.txt: -------------------------------------------------------------------------------- 1 | The implemented result of phy_1 is saved as best result. 2 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/constraints_source/ap106_ddr_pin.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dq[16] } {LOCATION = U3; IOSTANDARD = SSTL15; } 18 | set_ippin_assignment { ddr_dq[17] } {LOCATION = W2; IOSTANDARD = SSTL15; } 19 | set_ippin_assignment { ddr_dq[18] } {LOCATION = T4; IOSTANDARD = SSTL15; } 20 | set_ippin_assignment { ddr_dq[19] } {LOCATION = W4; IOSTANDARD = SSTL15; } 21 | set_ippin_assignment { ddr_dq[20] } {LOCATION = V4; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dq[21] } {LOCATION = U5; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_dq[22] } {LOCATION = V3; IOSTANDARD = SSTL15; } 24 | set_ippin_assignment { ddr_dq[23] } {LOCATION = T5; IOSTANDARD = SSTL15; } 25 | set_ippin_assignment { ddr_dq[24] } {LOCATION = AA3; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_dq[25] } {LOCATION = W1; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_dq[26] } {LOCATION = AB3; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_dq[27] } {LOCATION = AB2; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_dq[28] } {LOCATION = W5; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_dq[29] } {LOCATION = AB1; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_dq[30] } {LOCATION = AA1; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_dq[31] } {LOCATION = Y1; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 34 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 35 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 36 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 37 | set_ippin_assignment { ddr_dqs_n[2] } {LOCATION = V2; IOSTANDARD = DIFF_SSTL15; } 38 | set_ippin_assignment { ddr_dqs_p[2] } {LOCATION = U2; IOSTANDARD = DIFF_SSTL15; } 39 | set_ippin_assignment { ddr_dqs_n[3] } {LOCATION = Y2; IOSTANDARD = DIFF_SSTL15; } 40 | set_ippin_assignment { ddr_dqs_p[3] } {LOCATION = Y3; IOSTANDARD = DIFF_SSTL15; } 41 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_dm[2] } {LOCATION = N5; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_dm[3] } {LOCATION = AA4; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 46 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 47 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 49 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 50 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 51 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 52 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 53 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 54 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 55 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 56 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 57 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 58 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 59 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 60 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 61 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 62 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 63 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 64 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 65 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 66 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 67 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 68 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 69 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 70 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 71 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/constraints_source/pin.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment { I_rst_n } { LOCATION = K4; IOSTANDARD = LVCMOS15; PULLTYPE = PULLUP; } 2 | set_pin_assignment { I_sys_clk } { LOCATION = N18; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; } 3 | 4 | set_pin_assignment { O_uart_txd } { LOCATION = R22 ; IOSTANDARD = LVCMOS33;} 5 | set_pin_assignment { I_uart_rxd } { LOCATION = M16 ; IOSTANDARD = LVCMOS33; } 6 | 7 | set_pin_assignment { O_hdmi_tx_p[0] } { LOCATION = V13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 8 | set_pin_assignment { O_hdmi_tx_p[1] } { LOCATION = Y12; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 9 | set_pin_assignment { O_hdmi_tx_p[2] } { LOCATION = T13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 10 | set_pin_assignment { O_hdmi_clk_p } { LOCATION = V17; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 11 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/constraints_source/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name {sys_clk_25m} -period 40.000 -waveform {0.000 20.000} [get_ports {I_sys_clk}] 2 | derive_clocks 3 | set_clock_groups -asynchronous -group [get_clocks {sys_clk_25m}] -group [get_clocks {u_pll/pll_inst.clkc[0]}] -group [get_clocks {u_uifdma_axi_ddr/u_ddr_phy/dfi_clk}] -group [get_clocks {u_pll/pll_inst.clkc[1]}] 4 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/down_samping/down_samping_2x2.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:33:13 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:33:33 6 | */ 7 | 8 | 9 | module down_samping_2x2#( 10 | parameter [13:0] H_SIZE = 1920, 11 | parameter [13:0] V_SIZE = 1080 12 | ) 13 | ( 14 | input wire I_clk, 15 | input wire I_rst_n, 16 | 17 | input wire I_rgb_vs, 18 | input wire I_rgb_de, 19 | input wire [31:0] I_rgb_data, 20 | 21 | output reg O_rgb_vs, 22 | output reg O_rgb_de, 23 | output reg [31:0] O_rgb_data 24 | 25 | ); 26 | 27 | reg [11:0] col_count, row_count; 28 | 29 | 30 | wire vs_up_edge; 31 | 32 | assign vs_up_edge = I_rgb_vs &(~O_rgb_vs) ; 33 | 34 | always @(posedge I_clk or negedge I_rst_n) begin 35 | if (!I_rst_n) begin 36 | col_count <= 0; 37 | end else if (vs_up_edge) begin 38 | col_count <= 0; 39 | end else if (I_rgb_de) begin 40 | if (col_count == (H_SIZE- 1)) begin 41 | col_count <= 0; 42 | end else begin 43 | col_count <= col_count + 1; 44 | end 45 | end else begin 46 | col_count<=col_count; 47 | end 48 | end 49 | 50 | always @(posedge I_clk or negedge I_rst_n) begin 51 | if (!I_rst_n) begin 52 | row_count <= 0; 53 | end else if (vs_up_edge) begin 54 | row_count <= 0; 55 | end else if (I_rgb_de) begin 56 | if (row_count == (V_SIZE - 1) && col_count == (H_SIZE - 1)) begin 57 | row_count <= 0; 58 | end else if (col_count == (H_SIZE- 1)) begin 59 | row_count <= row_count + 1; 60 | end 61 | end else begin 62 | row_count<=row_count; 63 | end 64 | end 65 | 66 | 67 | reg sample_select; 68 | // wire sample_select; 69 | 70 | // assign sample_select = (col_count % 2 == 0) && (row_count % 2 == 0); 71 | 72 | always @(*) begin 73 | if(!I_rst_n) begin 74 | sample_select<=1'b0; 75 | end else begin 76 | sample_select <= (col_count % 2 == 0) && (row_count % 2 == 0); 77 | end 78 | end 79 | 80 | always @(posedge I_clk or negedge I_rst_n) begin 81 | if (!I_rst_n) begin 82 | O_rgb_vs <= 0; 83 | end else begin 84 | O_rgb_vs<=I_rgb_vs; 85 | end 86 | end 87 | 88 | always @(posedge I_clk or negedge I_rst_n) begin 89 | if (!I_rst_n) begin 90 | O_rgb_de <= 0; 91 | end else if(I_rgb_de) begin 92 | O_rgb_de<=sample_select; 93 | end else begin 94 | O_rgb_de<=0; 95 | end 96 | end 97 | 98 | always @(posedge I_clk or negedge I_rst_n) begin 99 | if (!I_rst_n) begin 100 | O_rgb_data <= 'd0; 101 | end else if(sample_select) begin 102 | O_rgb_data<=I_rgb_data; 103 | end 104 | end 105 | 106 | 107 | 108 | 109 | 110 | endmodule //video_samping 111 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_0.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_1.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_2.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/tpg/uitpg_3.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/command_parsing.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-12 19:11:31 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-12 19:11:31 6 | */ 7 | 8 | module command_parsing( 9 | input wire clk, 10 | input wire rst_n, 11 | input wire I_command_flag, 12 | input wire [3:0] I_ctrl_command , 13 | input wire [3:0] I_value_command, 14 | 15 | output reg O_video_move_en 16 | ); 17 | 18 | 19 | always @(posedge clk or negedge rst_n) begin 20 | if(!rst_n) begin 21 | O_video_move_en <= 'd0; 22 | end 23 | else if((I_ctrl_command == 4'b0000) && (I_command_flag == 1'b1)) begin //视频移动命令： 00 复位，回到初始位置 01 移动使能 24 | O_video_move_en <= I_value_command[0]; 25 | end 26 | end 27 | 28 | 29 | 30 | 31 | endmodule //command_parsing 32 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/uart_trans.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-12 19:09:02 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-12 19:11:11 6 | */ 7 | 8 | module uart_trans( 9 | input I_sysclk,//系统时钟输入 10 | input I_uart_rx,//uart rx接收信号 11 | output O_uart_tx, //uart tx发送信号 12 | output wire O_video_move_en 13 | ); 14 | 15 | 16 | localparam SYSCLKHZ = 25_000_000; //系统输入时钟 17 | 18 | reg [11:0] rstn_cnt = 0;//上电后延迟复位 19 | wire uart_rstn_i;//内部复位信号 20 | wire uart_wreq,uart_rvalid; 21 | wire [7:0]uart_wdata,uart_rdata; 22 | 23 | assign uart_wreq = uart_rvalid;//用uart rx接收数据有效的uart_rvalid信号，控制uart发送模块的发送请求 24 | assign uart_wdata = uart_rdata; //接收的数据给发送模块发送 25 | assign uart_rstn_i = rstn_cnt[11];//延迟复位设计，用计数器的高bit控制复位 26 | 27 | //同步计数器实现复位 28 | always @(posedge I_sysclk)begin 29 | if(rstn_cnt[11] == 1'b0) 30 | rstn_cnt <= rstn_cnt + 1'b1; 31 | else 32 | rstn_cnt <= rstn_cnt; 33 | end 34 | 35 | 36 | 37 | reg [3:0] reg_ctrl_command; 38 | reg [3:0] reg_value_command; 39 | 40 | reg command_out_flag; 41 | 42 | // 延迟一个周期 43 | always @(posedge I_sysclk or negedge uart_rstn_i) begin 44 | if(!uart_rstn_i) begin 45 | command_out_flag <= 'b0; 46 | end 47 | else begin 48 | command_out_flag <= uart_rvalid; 49 | end 50 | end 51 | 52 | // 控制信号只有效一个时钟周期 53 | always @(posedge I_sysclk or negedge uart_rstn_i) begin 54 | if(!uart_rstn_i) begin 55 | reg_ctrl_command <= 'b0; 56 | reg_value_command <= 'b0; 57 | end 58 | else if(uart_rvalid) begin 59 | reg_ctrl_command <= uart_rdata[7:4]; 60 | reg_value_command <= uart_rdata[3:0]; 61 | end 62 | else begin 63 | reg_ctrl_command <= reg_ctrl_command; 64 | reg_value_command <= reg_value_command; 65 | end 66 | end 67 | 68 | 69 | command_parsing u_command_parsing( 70 | .clk ( I_sysclk ), 71 | .rst_n ( uart_rstn_i ), 72 | .I_command_flag ( command_out_flag ), 73 | .I_ctrl_command ( reg_ctrl_command ), 74 | .I_value_command ( reg_value_command ), 75 | .O_video_move_en ( O_video_move_en ) 76 | ); 77 | 78 | 79 | //例化uart 发送模块 80 | uiuart_tx# 81 | ( 82 | .BAUD_DIV(SYSCLKHZ/115200-1) 83 | ) 84 | uart_tx_u 85 | ( 86 | .I_clk(I_sysclk),//系统时钟输入 87 | .I_uart_rstn(uart_rstn_i), //系统复位 88 | .I_uart_wreq(uart_wreq), //uart发送驱动的写请求信号，高电平有效 89 | .I_uart_wdata(uart_wdata), //uart发送驱动的写数据 90 | .O_uart_wbusy(),//uart 发送驱动的忙标志 91 | .O_uart_tx(O_uart_tx)//uart 串行数据发送 92 | ); 93 | 94 | //例化uart 接收 95 | uiuart_rx# 96 | ( 97 | .BAUD_DIV(SYSCLKHZ/115200-1) 98 | ) 99 | uiuart_rx_u 100 | ( 101 | .I_clk(I_sysclk), //系统时钟输入 102 | .I_uart_rstn(uart_rstn_i),//系统复位 103 | .I_uart_rx(I_uart_rx), //uart 串行数据接收 104 | .O_uart_rdata(uart_rdata), //uart 接收数据 105 | .O_uart_rvalid(uart_rvalid)//uart 接收数据有效，当O_uart_rvalid =1'b1 O_uart_rdata输出的数据有效 106 | ); 107 | 108 | endmodule -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/uiuart_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/uiuart_rx.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/uiuart_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uart/uiuart_tx.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdma/uiFDMA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdma/uiFDMA.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdma/uifdma_axi_ddr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdma/uifdma_axi_ddr.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/fs_cap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop: https://milianke.taobao.com 9 | *Create Date: 2022/09/25 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 3.1 20 | *Signal description 21 | *1) _i input 22 | *2) _o output 23 | *3) _n activ low 24 | *4) _dg debug signal 25 | *5) _r delay or register 26 | *6) _s state mechine 27 | *********************************************************************/ 28 | 29 | 30 | module fs_cap#( 31 | parameter integer VIDEO_ENABLE = 1 32 | ) 33 | ( 34 | input I_clk, 35 | input I_rstn, 36 | input I_vs, 37 | output reg O_fs_cap 38 | ); 39 | 40 | //----CH0_CNT_FS�źŵ�ƽ���� ʵ�ʾ��Dz���VS�ź�---------------- 41 | reg[4:0]CNT_FS = 6'b0; 42 | reg[4:0]CNT_FS_n = 6'b0; 43 | reg FS = 1'b0; 44 | (* ASYNC_REG = "TRUE" *) reg vs_i_r1; 45 | (* ASYNC_REG = "TRUE" *) reg vs_i_r2; 46 | (* ASYNC_REG = "TRUE" *) reg vs_i_r3; 47 | (* ASYNC_REG = "TRUE" *) reg vs_i_r4; 48 | //----ͬ�����ε�·��֮ǰ����û�����ε�·�������Dzɼ�vs����----- 49 | always@(posedge I_clk) begin 50 | vs_i_r1 <= I_vs; 51 | vs_i_r2 <= vs_i_r1; 52 | vs_i_r3 <= vs_i_r2; 53 | vs_i_r4 <= vs_i_r3; 54 | end 55 | 56 | always@(posedge I_clk) begin 57 | if(!I_rstn)begin 58 | O_fs_cap <= 1'd0; 59 | end 60 | else if(VIDEO_ENABLE == 1)begin 61 | if({vs_i_r4,vs_i_r3} == 2'b01)begin 62 | O_fs_cap <= 1'b1; 63 | end 64 | else begin 65 | O_fs_cap <= 1'b0; 66 | end 67 | end 68 | else begin 69 | O_fs_cap <= vs_i_r4; 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 253 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 2048 11 | 32 12 | Enable 13 | 256 14 | 256 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | rfifo 22 | 23 | 24 | rfifo.v 25 | rfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/uidbuf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/uidbuf.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 2045 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 256 11 | 256 12 | Enable 13 | 2048 14 | 32 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | wfifo 22 | 23 | 24 | wfifo.v 25 | wfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/uisetvbuf/uisetvbuf.v: -------------------------------------------------------------------------------- 1 | 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop1: https://milianke.taobao.com 9 | *Create Date: 2023/03/23 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 1.1 20 | *Signal description 21 | *1) I_ input 22 | *2) O_ output 23 | *3) IO_ input output 24 | *3) S_ system internal signal 25 | *3) _n activ low 26 | *4) _dg debug signal 27 | *5) _r delay or register 28 | *6) _s state mechine 29 | *********************************************************************/ 30 | `timescale 1ns / 1ps 31 | 32 | module uisetvbuf#( 33 | parameter integer BUF_DELAY = 1, 34 | parameter integer BUF_LENTH = 3 35 | ) 36 | ( 37 | 38 | input [7 :0] I_bufn, 39 | output [7 :0] O_bufn 40 | ); 41 | 42 | 43 | 44 | assign O_bufn = I_bufn < BUF_DELAY? (BUF_LENTH - BUF_DELAY + I_bufn) : (I_bufn - BUF_DELAY) ; 45 | 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/vtc/uivtc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/vtc/uivtc.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/vtc/uivtc_video_move.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/vtc/uivtc_video_move.v -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/width_conversion/rd_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:20 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:20 6 | */ 7 | 8 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 9 | module rd_width_convert( 10 | input wire [15:0] I_rd_data, 11 | 12 | output wire [31:0] O_rd_data 13 | ); 14 | 15 | 16 | assign O_rd_data ={8'd0,I_rd_data[15:11], 3'd0, I_rd_data[10:5], 2'd0,I_rd_data[4:0], 3'd0} ; 17 | 18 | 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/02_four_channel_viideo_splicer_move/user_source/hdl_source/width_conversion/wr_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:27 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:27 6 | */ 7 | 8 | 9 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 10 | module wr_width_convert( 11 | input wire [31:0] I_wr_data, 12 | 13 | output wire [15:0] O_wr_data 14 | ); 15 | 16 | assign O_wr_data = {I_wr_data[23:19],I_wr_data[15:10],I_wr_data[7:3]}; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /01_四路视频拼接+视频移动/README.md: -------------------------------------------------------------------------------- 1 | 四分屏显示+分屏时视频自动移动可以分成两个部分 2 | 3 | 四路视频源的拼接工程文件见01_four_channel_viideo_splicer文件夹 4 | 5 | 四路视频拼接+视频移动见02_four_channel_viideo_splicer_move文件夹 6 | 7 | 移植注意事项 8 | 9 | 1、 在本工程中，为了减少ERAM资源的使用，我们将图像像素点在DDR3中的存储和读取格式设置为RGB565格式，其中每个像素点占用16bit，并将DDR3的数据位宽设置为16bit。由于DDR3的突发传输长度固定为8，每次突发传输8次16bit数据，即总共传输128bit。因此，在进行DDR3存取时，FIFO的读写位宽可以设置为16bit和128bit。与此不同，若将图像像素点的存储格式设置为RGB888格式，每个像素点将占用24bit，并将DDR3的数据位宽设置为32bit。在这种情况下，进行存取时，FIFO的读写位宽将为32bit和256bit，这样会导致ERAM资源消耗的加倍。 10 | 11 | 2、本工程把四路视频源拼接模块输入的视频分辨率为1280×720，如果要改为1920×1080，需要更改 12 | down_samping_2x2、uidbuf、uivtc模块的参数。 13 | 14 | 3、使用串口命令发送16进制 00 视频不移动，发送16进制01 视频开始移动。波特率为115200。 15 | 16 | 关于四路视频源拼接方案实现讲解，博客地址如下：[FPGA实现四分屏显示+分屏时视频自动移动（一）](https://blog.csdn.net/weixin_53015183/article/details/144307736?spm=1001.2014.3001.5502) 17 | 18 | 关于四路视频拼接+视频移动实现讲解，博客地址如下：[国产安路FPGA实现多路视频拼接，四分屏显示+分屏时视频自动移动（二）](https://blog.csdn.net/weixin_53015183/article/details/144431849?spm=1001.2014.3001.5501) 19 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/README.md: -------------------------------------------------------------------------------- 1 | 移植注意事项 2 | 3 | 1、 在本工程中，为了减少ERAM资源的使用，我们将图像像素点在DDR3中的存储和读取格式设置为RGB565格式，其中每个像素点占用16bit，并将DDR3的数据位宽设置为16bit。由于DDR3的突发传输长度固定为8，每次突发传输8次16bit数据，即总共传输128bit。因此，在进行DDR3存取时，FIFO的读写位宽可以设置为16bit和128bit。与此不同，若将图像像素点的存储格式设置为RGB888格式，每个像素点将占用24bit，并将DDR3的数据位宽设置为32bit。在这种情况下，进行存取时，FIFO的读写位宽将为32bit和256bit，这样会导致ERAM资源消耗的加倍。 4 | 5 | 2、本工程四路视频源输入的视频分辨率为1280×720 6 | 7 | **3、使用串口命令发送16进制 00 视频不移动，发送16进制01 视频开始移动。10 分屏显示 11 Video0全屏 12 video1全屏 13 video2全屏 14 video3全屏，波特率为115200。** 8 | 9 | 10 | 关于四分屏显示与全屏自由切换实现讲解，博客地址如下：[FPGA实现四分屏显示与全屏自由切换](https://blog.csdn.net/weixin_53015183/article/details/144698331?spm=1001.2014.3001.5501) 11 | 12 | 13 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/ddr_ip.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 18 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 19 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 20 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 21 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 24 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 25 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 34 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 35 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 36 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 37 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 38 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 39 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 40 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 41 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 46 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 47 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 49 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_hard_controller_0} {LOCATION = X65Y40Z0} 50 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_1$ph1_ddr_4lanes} {LOCATION = X81Y40Z0} 51 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_2$ph1_ddr_4lanes} {LOCATION = X81Y0Z0} 52 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll0/pll_inst} { LOCATION = X81Y39Z0} 53 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll1/pll_inst} { LOCATION = X81Y0Z0} 54 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/ddr_ip.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PH1_LOGIC_DDR_SDRAM 5 | 3.0 6 | PH1A90SBG484 7 | false 8 | ddr_ip 9 | DDR3 10 | MC and Standard PHY 11 | 1 12 | 2-1 13 | ENABLE 14 | ENABLE 15 | 4 16 | 533.000000 17 | MHz 18 | 25.000000 19 | MHz 20 | Bank31 21 | false 22 | 4:1 23 | false 24 | false 25 | false 26 | false 27 | 100.000000 28 | 100.000000 29 | 100.000000 30 | 100.000000 31 | MHz 32 | MHz 33 | MHz 34 | MHz 35 | 100.000000 36 | 100.000000 37 | 100.000000 38 | 100.000000 39 | MT41J128M16JT-125 40 | 1.5V 41 | 16 42 | false 43 | true 44 | Row_Column_Bank 45 | Normal 46 | Sequential 47 | RZQ/6 48 | RZQ/4 49 | Enable 50 | DISABLE 51 | DISABLE 52 | DISABLE 53 | ENABLE 54 | DISABLE 55 | ENABLE 56 | Pin 57 | L1,M3,K1,N2,K2,N3,K3,L3,R2,P1,U1,R3,T1,P2,R4,R1,M1,M2,N4,M5,L5,P4,Y9,W9,R7,AB6,U8,U6,W11,AA5,AA6,AB7,V9,V8,W6,AA11,U7,Y11,AA8,U12,AB8,AB10,AA10,V10,U10,Y6,AB11,T8 58 | None 59 | 60 | 61 | ddr_ip.adc 62 | ddr_ip.v 63 | ddr_ip.sdc 64 | 65 | 66 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/ddr_ip_1.txt: -------------------------------------------------------------------------------- 1 | 00000042 2 | 00000000 3 | 8000042a 4 | 00000010 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | ff55f0ff 12 | ffffff54 13 | ffff89ab 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | 05_08_0d_09 18 | 0a_06_04_07 19 | 00_01_00_02 20 | 0c_0b_01_00 21 | 00_00_00_00 22 | 02_07_08_0d 23 | 09_05_0a_06 24 | 00_01_00_04 25 | 0c_0b_01_00 26 | 00_00_00_00 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000830 66 | 00000004 67 | 00000008 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 06140704 75 | 281b0004 76 | 0003005b 77 | 82000000 78 | 00560504 79 | 001b0704 80 | 00000000 81 | 030b0200 82 | bb5d9999 83 | 030b0200 84 | bb5d9999 85 | 030b0200 86 | bb5d9999 87 | 030b0200 88 | bb5d9999 89 | 030b0200 90 | bb5d9999 91 | 030b0200 92 | bb5d9999 93 | 030b0200 94 | bb5d9999 95 | 030b0200 96 | bb5d9999 97 | 030b0200 98 | bb5d9999 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | 00000000 130 | 00000000 131 | 00000000 132 | 00000000 133 | 00000000 134 | 00000000 135 | 00000000 136 | 00000000 137 | 00000000 138 | 00000000 139 | 00000000 140 | 00000000 141 | 00000000 142 | 00000000 143 | 00000000 144 | 00000000 145 | 00000000 146 | 00000000 147 | 00000000 148 | 00000000 149 | 00000000 150 | 00000000 151 | 00000000 152 | 00000000 153 | 00000000 154 | 00000000 155 | 00000000 156 | 00000000 157 | 00000000 158 | 00000000 159 | 00000000 160 | 00000000 161 | 00000000 162 | 00000000 163 | 00000000 164 | 00000000 165 | 00000000 166 | 00000000 167 | 00000000 168 | 00000000 169 | 00000000 170 | 00000000 171 | 00000000 172 | 00000000 173 | 00000000 174 | 00000000 175 | 00000000 176 | 00000000 177 | 00000000 178 | 00000000 179 | 00000000 180 | 00000000 181 | 00000000 182 | 00000000 183 | 00000000 184 | 00000000 185 | 00000000 186 | 00000000 187 | 00000000 188 | 00000000 189 | 00000000 190 | 00000000 191 | 00000000 192 | 00000000 193 | 00000000 194 | 00000000 195 | 00000000 196 | 00000000 197 | 00000000 198 | 00000000 199 | 00000000 200 | 00000000 201 | 00000000 202 | 00000000 203 | 00000000 204 | 00000000 205 | 00000000 206 | 00000000 207 | 00000000 208 | 00000000 209 | 00000000 210 | 00000000 211 | 00000000 212 | 00000000 213 | 00000000 214 | 00000000 215 | 00000000 216 | 00000000 217 | 00000000 218 | 00000000 219 | 00000000 220 | 00000000 221 | 00000000 222 | 00000000 223 | 00000000 224 | 00000000 225 | 00000000 226 | 00000000 227 | 00000000 228 | 00000000 229 | 00000000 230 | 00000000 231 | 00000000 232 | 00000000 233 | 00000000 234 | 00000000 235 | 00000000 236 | 00000000 237 | 00000000 238 | 00000000 239 | 00000000 240 | 00000000 241 | 00000000 242 | 00000000 243 | 00000000 244 | 00000000 245 | 00000000 246 | 00000000 247 | 00000000 248 | 00000000 249 | 00000000 250 | 00000000 251 | 00000000 252 | 00000000 253 | 00000000 254 | 00000000 255 | 00000000 256 | 00000000 257 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | PH1A90SBG484 6 | true 7 | 8 | 9 | Any 10 | 25.0000000000000000MHz 11 | Normal 12 | CLKC0 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | DISABLE 17 | DISABLE 18 | DISABLE 19 | ENABLE 20 | ENABLE 21 | 22 | 23 | Medium 24 | 25 | 26 | frequncy_setting 27 | 3 28 | 1 29 | 30 | 31 | 0 32 | 15 33 | 75.0000000000000000MHz 34 | 0.0000000000000000deg 35 | 0.5 36 | false 37 | false 38 | BUFG 39 | 40 | 41 | 1 42 | 3 43 | 375.0000000000000000MHz 44 | 0.0000000000000000deg 45 | 0.5 46 | false 47 | false 48 | NONE 49 | 50 | 51 | 52 | 53 | pll.vhd 54 | pll.v 55 | 56 | 57 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2024 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.v 8 | ** Date : 2024 12 07 9 | ** TD version : 6.0.117864 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 25.000000MHz 14 | // Clock multiplication factor: 3 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 75.000000 MHZ | 0.0000 DEG 19 | // C1 | 375.000000MHZ | 0.0000 DEG 20 | /////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1 ns / 100 fs 22 | 23 | module pll ( 24 | refclk, 25 | reset, 26 | lock, 27 | clk0_out, 28 | clk1_out 29 | ); 30 | 31 | input refclk; 32 | input reset; 33 | output lock; 34 | output clk0_out; 35 | output clk1_out; 36 | 37 | wire clk0_buf; 38 | 39 | PH1_LOGIC_BUFG bufg_feedback ( 40 | .i(clk0_buf), 41 | .o(clk0_out) 42 | ); 43 | 44 | PH1_PHY_PLL #( 45 | .DYN_PHASE_PATH_SEL("DISABLE"), 46 | .DYN_FPHASE_EN("DISABLE"), 47 | .MPHASE_ENABLE("DISABLE"), 48 | .FIN("25.000000"), 49 | .FEEDBK_MODE("NORMAL"), 50 | .FBKCLK("CLKC0_EXT"), 51 | .PLL_FEED_TYPE("EXTERNAL"), 52 | .PLL_USR_RST("ENABLE"), 53 | .GMC_GAIN(1), 54 | .ICP_CUR(11), 55 | .LPF_CAP(2), 56 | .LPF_RES(3), 57 | .REFCLK_DIV(1), 58 | .FBCLK_DIV(3), 59 | .CLKC0_ENABLE("ENABLE"), 60 | .CLKC0_DIV(15), 61 | .CLKC0_CPHASE(14), 62 | .CLKC0_FPHASE(0), 63 | .CLKC0_FPHASE_RSTSEL(0), 64 | .CLKC0_DUTY_INT(8), 65 | .CLKC0_DUTY50("ENABLE"), 66 | .CLKC1_ENABLE("ENABLE"), 67 | .CLKC1_DIV(3), 68 | .CLKC1_CPHASE(2), 69 | .CLKC1_FPHASE(0), 70 | .CLKC1_FPHASE_RSTSEL(0), 71 | .CLKC1_DUTY_INT(2), 72 | .CLKC1_DUTY50("ENABLE"), 73 | .INTPI(1), 74 | .HIGH_SPEED_EN("DISABLE"), 75 | .SSC_ENABLE("DISABLE"), 76 | .SSC_MODE("CENTER"), 77 | .SSC_AMP(0.0000), 78 | .SSC_FREQ_DIV(0), 79 | .SSC_RNGE(0), 80 | .FRAC_ENABLE("DISABLE"), 81 | .DITHER_ENABLE("DISABLE"), 82 | .SDM_FRAC(0) 83 | ) pll_inst ( 84 | .refclk(refclk), 85 | .pllreset(reset), 86 | .lock(lock), 87 | .pllpd(1'b0), 88 | .refclk_rst(1'b0), 89 | .wakeup(1'b0), 90 | .psclk(1'b0), 91 | .psdown(1'b0), 92 | .psstep(1'b0), 93 | .psclksel(3'b000), 94 | .psdone(pll_open0), 95 | .cps_step(2'b00), 96 | .drp_clk(1'b0), 97 | .drp_rstn(1'b1), 98 | .drp_sel(1'b0), 99 | .drp_rd(1'b0), 100 | .drp_wr(1'b0), 101 | .drp_addr(8'b00000000), 102 | .drp_wdata(8'b00000000), 103 | .drp_err(pll_open1), 104 | .drp_rdy(pll_open2), 105 | .drp_rdata({pll_open10, pll_open9, pll_open8, pll_open7, pll_open6, pll_open5, pll_open4, pll_open3}), 106 | .fbclk(clk0_out), 107 | .clkc({pll_open23, pll_open21, pll_open19, pll_open17, pll_open15, pll_open13, clk1_out, clk0_buf}), 108 | .clkcb({pll_open24, pll_open22, pll_open20, pll_open18, pll_open16, pll_open14, pll_open12, pll_open11}), 109 | .clkc_en({8'b00000011}), 110 | .clkc_rst(2'b00), 111 | .ext_freq_mod_clk(1'b0), 112 | .ext_freq_mod_en(1'b0), 113 | .ext_freq_mod_val(17'b00000000000000000), 114 | .ssc_en(1'b0) 115 | ); 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/al_ip/pll.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2024 Anlogic Inc. -- All Right Reserved. 3 | -------------------------------------------------------------- 4 | -- Log : This file is generated by Anlogic IP Generator. 5 | -- File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.vhd 6 | -- Date : 2024 12 07 7 | -- TD version : 6.0.117864 8 | -------------------------------------------------------------- 9 | 10 | ------------------------------------------------------------------------------- 11 | -- Input frequency: 25.000000MHz 12 | -- Clock multiplication factor: 3 13 | -- Clock division factor: 1 14 | -- Clock information: 15 | -- Clock name | Frequency | Phase shift 16 | -- C0 | 75.000000 MHZ | 0.0000 DEG 17 | -- C1 | 375.000000MHZ | 0.0000 DEG 18 | ------------------------------------------------------------------------------- 19 | 20 | LIBRARY ieee; 21 | USE ieee.std_logic_1164.ALL; 22 | USE ieee.numeric_std.ALL; 23 | USE ieee.std_logic_unsigned.ALL; 24 | USE ieee.std_logic_arith.ALL; 25 | LIBRARY ph1_macro; 26 | USE ph1_macro.PH1_COMPONENTS.ALL; 27 | 28 | ENTITY pll IS 29 | PORT ( 30 | refclk : IN STD_LOGIC; 31 | reset : IN STD_LOGIC; 32 | lock : OUT STD_LOGIC; 33 | clk0_out : OUT STD_LOGIC; 34 | clk1_out : OUT STD_LOGIC 35 | ); 36 | END pll; 37 | 38 | ARCHITECTURE rtl OF pll IS 39 | SIGNAL clk0_buf : STD_LOGIC; 40 | SIGNAL fbk_wire : STD_LOGIC; 41 | SIGNAL clkc_en_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 42 | SIGNAL clkc_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 43 | SIGNAL clkcb_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 44 | BEGIN 45 | bufg_feedback : PH1_LOGIC_BUFG 46 | PORT MAP ( 47 | i => clk0_buf, 48 | o => fbk_wire 49 | ); 50 | 51 | pll_inst : PH1_PHY_PLL 52 | GENERIC MAP ( 53 | DYN_PHASE_PATH_SEL => "DISABLE", 54 | DYN_FPHASE_EN => "DISABLE", 55 | MPHASE_ENABLE => "DISABLE", 56 | FIN => "25.000000", 57 | FEEDBK_MODE => "NORMAL", 58 | FBKCLK => "CLKC0_EXT", 59 | PLL_FEED_TYPE => "EXTERNAL", 60 | PLL_USR_RST => "ENABLE", 61 | GMC_GAIN => 1, 62 | ICP_CUR => 11, 63 | LPF_CAP => 2, 64 | LPF_RES => 3, 65 | REFCLK_DIV => 1, 66 | FBCLK_DIV => 3, 67 | CLKC0_ENABLE => "ENABLE", 68 | CLKC0_DIV => 15, 69 | CLKC0_CPHASE => 14, 70 | CLKC0_FPHASE => 0, 71 | CLKC0_FPHASE_RSTSEL => 0, 72 | CLKC0_DUTY_INT => 8, 73 | CLKC0_DUTY50 => "ENABLE", 74 | CLKC1_ENABLE => "ENABLE", 75 | CLKC1_DIV => 3, 76 | CLKC1_CPHASE => 2, 77 | CLKC1_FPHASE => 0, 78 | CLKC1_FPHASE_RSTSEL => 0, 79 | CLKC1_DUTY_INT => 2, 80 | CLKC1_DUTY50 => "ENABLE", 81 | INTPI => 1, 82 | HIGH_SPEED_EN => "DISABLE", 83 | SSC_ENABLE => "DISABLE", 84 | SSC_MODE => "CENTER", 85 | SSC_AMP => 0.0000, 86 | SSC_FREQ_DIV => 0, 87 | SSC_RNGE => 0, 88 | FRAC_ENABLE => "DISABLE", 89 | DITHER_ENABLE => "DISABLE", 90 | SDM_FRAC => 0 91 | ) 92 | PORT MAP ( 93 | refclk => refclk, 94 | pllreset => reset, 95 | lock => lock, 96 | pllpd => '0', 97 | refclk_rst => '0', 98 | wakeup => '0', 99 | psclk => '0', 100 | psdown => '0', 101 | psstep => '0', 102 | psclksel => b"000", 103 | cps_step => b"00", 104 | drp_clk => '0', 105 | drp_rstn => '1', 106 | drp_sel => '0', 107 | drp_rd => '0', 108 | drp_wr => '0', 109 | drp_addr => b"00000000", 110 | drp_wdata => b"00000000", 111 | fbclk => fbk_wire, 112 | clkc => clkc_wire, 113 | clkcb => clkcb_wire, 114 | clkc_en => clkc_en_wire, 115 | clkc_rst => b"00", 116 | ext_freq_mod_clk => '0', 117 | ext_freq_mod_en => '0', 118 | ext_freq_mod_val => b"00000000000000000", 119 | ssc_en => '0' 120 | ); 121 | 122 | clk0_out <= fbk_wire; 123 | clkc_en_wire <= b"00000011"; 124 | clk1_out <= clkc_wire(1); 125 | clk0_buf <= clkc_wire(0); 126 | 127 | END rtl; 128 | 129 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/fpga_prj_Runs/best_result/fpga_prj.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/fpga_prj_Runs/best_result/fpga_prj.bit -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/td_project/fpga_prj_Runs/best_result/readMe.txt: -------------------------------------------------------------------------------- 1 | The implemented result of phy_1 is saved as best result. 2 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/constraints_source/pin.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment { I_rst_n } { LOCATION = K4; IOSTANDARD = LVCMOS15; PULLTYPE = PULLUP; } 2 | set_pin_assignment { I_sys_clk } { LOCATION = N18; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; } 3 | 4 | set_pin_assignment { O_uart_txd } { LOCATION = R22 ; IOSTANDARD = LVCMOS33;} 5 | set_pin_assignment { I_uart_rxd } { LOCATION = M16 ; IOSTANDARD = LVCMOS33; } 6 | 7 | set_pin_assignment { O_hdmi_tx_p[0] } { LOCATION = V13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 8 | set_pin_assignment { O_hdmi_tx_p[1] } { LOCATION = Y12; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 9 | set_pin_assignment { O_hdmi_tx_p[2] } { LOCATION = T13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 10 | set_pin_assignment { O_hdmi_clk_p } { LOCATION = V17; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 11 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/constraints_source/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name {sys_clk_25m} -period 40.000 -waveform {0.000 20.000} [get_ports {I_sys_clk}] 2 | derive_pll_clocks 3 | set_clock_groups -asynchronous -group [get_clocks {sys_clk_25m}] -group [get_clocks {u_pll/pll_inst.clkc[0]}] -group [get_clocks {u_pll/pll_inst.clkc[1]}] 4 | set_clock_groups -asynchronous -group [get_clocks {sys_clk_25m}] -group [get_clocks {u_uifdma_axi_ddr/u_ddr_phy/dfi_clk}] 5 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/down_samping/down_samping_2x2.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:33:13 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:33:33 6 | */ 7 | 8 | 9 | module down_samping_2x2#( 10 | parameter [13:0] H_SIZE = 1920, 11 | parameter [13:0] V_SIZE = 1080 12 | ) 13 | ( 14 | input wire I_clk, 15 | input wire I_rst_n, 16 | 17 | input wire I_rgb_vs, 18 | input wire I_rgb_de, 19 | input wire [31:0] I_rgb_data, 20 | 21 | output reg O_rgb_vs, 22 | output reg O_rgb_de, 23 | output reg [31:0] O_rgb_data 24 | 25 | ); 26 | 27 | reg [11:0] col_count, row_count; 28 | 29 | 30 | wire vs_up_edge; 31 | 32 | assign vs_up_edge = I_rgb_vs &(~O_rgb_vs) ; 33 | 34 | always @(posedge I_clk or negedge I_rst_n) begin 35 | if (!I_rst_n) begin 36 | col_count <= 0; 37 | end else if (vs_up_edge) begin 38 | col_count <= 0; 39 | end else if (I_rgb_de) begin 40 | if (col_count == (H_SIZE- 1)) begin 41 | col_count <= 0; 42 | end else begin 43 | col_count <= col_count + 1; 44 | end 45 | end else begin 46 | col_count<=col_count; 47 | end 48 | end 49 | 50 | always @(posedge I_clk or negedge I_rst_n) begin 51 | if (!I_rst_n) begin 52 | row_count <= 0; 53 | end else if (vs_up_edge) begin 54 | row_count <= 0; 55 | end else if (I_rgb_de) begin 56 | if (row_count == (V_SIZE - 1) && col_count == (H_SIZE - 1)) begin 57 | row_count <= 0; 58 | end else if (col_count == (H_SIZE- 1)) begin 59 | row_count <= row_count + 1; 60 | end 61 | end else begin 62 | row_count<=row_count; 63 | end 64 | end 65 | 66 | 67 | reg sample_select; 68 | // wire sample_select; 69 | 70 | // assign sample_select = (col_count % 2 == 0) && (row_count % 2 == 0); 71 | 72 | always @(*) begin 73 | if(!I_rst_n) begin 74 | sample_select<=1'b0; 75 | end else begin 76 | sample_select <= (col_count % 2 == 0) && (row_count % 2 == 0); 77 | end 78 | end 79 | 80 | always @(posedge I_clk or negedge I_rst_n) begin 81 | if (!I_rst_n) begin 82 | O_rgb_vs <= 0; 83 | end else begin 84 | O_rgb_vs<=I_rgb_vs; 85 | end 86 | end 87 | 88 | always @(posedge I_clk or negedge I_rst_n) begin 89 | if (!I_rst_n) begin 90 | O_rgb_de <= 0; 91 | end else if(I_rgb_de) begin 92 | O_rgb_de<=sample_select; 93 | end else begin 94 | O_rgb_de<=0; 95 | end 96 | end 97 | 98 | always @(posedge I_clk or negedge I_rst_n) begin 99 | if (!I_rst_n) begin 100 | O_rgb_data <= 'd0; 101 | end else if(sample_select) begin 102 | O_rgb_data<=I_rgb_data; 103 | end 104 | end 105 | 106 | 107 | 108 | 109 | 110 | endmodule //video_samping 111 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_0.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_0.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_1.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_2.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_2.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/tpg/uitpg_3.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/command_parsing.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-12 19:11:31 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-12 19:11:31 6 | */ 7 | 8 | module command_parsing( 9 | input wire clk, 10 | input wire rst_n, 11 | input wire I_command_flag, 12 | input wire [3:0] I_ctrl_command , 13 | input wire [3:0] I_value_command, 14 | 15 | output reg O_video_move_en, 16 | output reg O_split_full_flag,//0 分屏 1 全屏 17 | output reg [3:0] O_screen_switch 18 | ); 19 | 20 | 21 | always @(posedge clk or negedge rst_n) begin 22 | if(!rst_n) begin 23 | O_video_move_en <= 'd0; 24 | O_split_full_flag <= 'd0; 25 | O_screen_switch <= 'd0; 26 | end 27 | else if((I_ctrl_command == 4'b0000) && (I_command_flag == 1'b1)) begin //视频移动命令： 00 复位，回到初始位置 01 移动使能 28 | O_video_move_en <= I_value_command[0]; 29 | end else if((I_ctrl_command == 4'b0001) && (I_command_flag == 1'b1)) begin //控制分屏/全屏切换: 10 分屏显示 11 Video0全屏 12 video1全屏 13 video2全屏 14 video3全屏 30 | if (I_value_command == 4'd0) begin 31 | O_split_full_flag <= 0; 32 | end else if (I_value_command == 4'd1) begin 33 | O_split_full_flag <= 1; 34 | O_screen_switch <= 4'b0001; 35 | end else if (I_value_command == 4'd2) begin 36 | O_split_full_flag <= 1; 37 | O_screen_switch <= 4'b0010; 38 | end else if (I_value_command == 4'd3) begin 39 | O_split_full_flag <= 1; 40 | O_screen_switch <= 4'b0100; 41 | end else if (I_value_command == 4'd4) begin 42 | O_split_full_flag <= 1; 43 | O_screen_switch <= 4'b1000; 44 | end 45 | end 46 | end 47 | 48 | 49 | 50 | 51 | endmodule //command_parsing 52 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/uart_trans.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-12 19:09:02 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-12 19:11:11 6 | */ 7 | 8 | module uart_trans( 9 | input I_sysclk,//系统时钟输入 10 | input I_uart_rx,//uart rx接收信号 11 | output O_uart_tx, //uart tx发送信号 12 | 13 | output wire O_video_move_en, 14 | output wire O_split_full_flag,//0 分屏 1 全屏 15 | output wire [3:0] O_screen_switch 16 | ); 17 | 18 | 19 | localparam SYSCLKHZ = 25_000_000; //系统输入时钟 20 | 21 | reg [11:0] rstn_cnt = 0;//上电后延迟复位 22 | wire uart_rstn_i;//内部复位信号 23 | wire uart_wreq,uart_rvalid; 24 | wire [7:0]uart_wdata,uart_rdata; 25 | 26 | assign uart_wreq = uart_rvalid;//用uart rx接收数据有效的uart_rvalid信号，控制uart发送模块的发送请求 27 | assign uart_wdata = uart_rdata; //接收的数据给发送模块发送 28 | assign uart_rstn_i = rstn_cnt[11];//延迟复位设计，用计数器的高bit控制复位 29 | 30 | //同步计数器实现复位 31 | always @(posedge I_sysclk)begin 32 | if(rstn_cnt[11] == 1'b0) 33 | rstn_cnt <= rstn_cnt + 1'b1; 34 | else 35 | rstn_cnt <= rstn_cnt; 36 | end 37 | 38 | 39 | 40 | reg [3:0] reg_ctrl_command; 41 | reg [3:0] reg_value_command; 42 | 43 | reg command_out_flag; 44 | 45 | // 延迟一个周期 46 | always @(posedge I_sysclk or negedge uart_rstn_i) begin 47 | if(!uart_rstn_i) begin 48 | command_out_flag <= 'b0; 49 | end 50 | else begin 51 | command_out_flag <= uart_rvalid; 52 | end 53 | end 54 | 55 | // 控制信号只有效一个时钟周期 56 | always @(posedge I_sysclk or negedge uart_rstn_i) begin 57 | if(!uart_rstn_i) begin 58 | reg_ctrl_command <= 'b0; 59 | reg_value_command <= 'b0; 60 | end 61 | else if(uart_rvalid) begin 62 | reg_ctrl_command <= uart_rdata[7:4]; 63 | reg_value_command <= uart_rdata[3:0]; 64 | end 65 | else begin 66 | reg_ctrl_command <= reg_ctrl_command; 67 | reg_value_command <= reg_value_command; 68 | end 69 | end 70 | 71 | 72 | command_parsing u_command_parsing( 73 | .clk ( I_sysclk ), 74 | .rst_n ( uart_rstn_i ), 75 | .I_command_flag ( command_out_flag ), 76 | .I_ctrl_command ( reg_ctrl_command ), 77 | .I_value_command ( reg_value_command ), 78 | .O_video_move_en ( O_video_move_en ), 79 | .O_split_full_flag ( O_split_full_flag ), 80 | .O_screen_switch ( O_screen_switch ) 81 | ); 82 | 83 | 84 | //例化uart 发送模块 85 | uiuart_tx# 86 | ( 87 | .BAUD_DIV(SYSCLKHZ/115200-1) 88 | ) 89 | uart_tx_u 90 | ( 91 | .I_clk(I_sysclk),//系统时钟输入 92 | .I_uart_rstn(uart_rstn_i), //系统复位 93 | .I_uart_wreq(uart_wreq), //uart发送驱动的写请求信号，高电平有效 94 | .I_uart_wdata(uart_wdata), //uart发送驱动的写数据 95 | .O_uart_wbusy(),//uart 发送驱动的忙标志 96 | .O_uart_tx(O_uart_tx)//uart 串行数据发送 97 | ); 98 | 99 | //例化uart 接收 100 | uiuart_rx# 101 | ( 102 | .BAUD_DIV(SYSCLKHZ/115200-1) 103 | ) 104 | uiuart_rx_u 105 | ( 106 | .I_clk(I_sysclk), //系统时钟输入 107 | .I_uart_rstn(uart_rstn_i),//系统复位 108 | .I_uart_rx(I_uart_rx), //uart 串行数据接收 109 | .O_uart_rdata(uart_rdata), //uart 接收数据 110 | .O_uart_rvalid(uart_rvalid)//uart 接收数据有效，当O_uart_rvalid =1'b1 O_uart_rdata输出的数据有效 111 | ); 112 | 113 | endmodule -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/uiuart_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/uiuart_rx.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/uiuart_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uart/uiuart_tx.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdma/uiFDMA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdma/uiFDMA.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdma/uifdma_axi_ddr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdma/uifdma_axi_ddr.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/fs_cap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop: https://milianke.taobao.com 9 | *Create Date: 2022/09/25 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 3.1 20 | *Signal description 21 | *1) _i input 22 | *2) _o output 23 | *3) _n activ low 24 | *4) _dg debug signal 25 | *5) _r delay or register 26 | *6) _s state mechine 27 | *********************************************************************/ 28 | 29 | 30 | module fs_cap#( 31 | parameter integer VIDEO_ENABLE = 1 32 | ) 33 | ( 34 | input I_clk, 35 | input I_rstn, 36 | input I_vs, 37 | output reg O_fs_cap 38 | ); 39 | 40 | //----CH0_CNT_FS�źŵ�ƽ���� ʵ�ʾ��Dz���VS�ź�---------------- 41 | reg[4:0]CNT_FS = 6'b0; 42 | reg[4:0]CNT_FS_n = 6'b0; 43 | reg FS = 1'b0; 44 | (* ASYNC_REG = "TRUE" *) reg vs_i_r1; 45 | (* ASYNC_REG = "TRUE" *) reg vs_i_r2; 46 | (* ASYNC_REG = "TRUE" *) reg vs_i_r3; 47 | (* ASYNC_REG = "TRUE" *) reg vs_i_r4; 48 | //----ͬ�����ε�·��֮ǰ����û�����ε�·�������Dzɼ�vs����----- 49 | always@(posedge I_clk) begin 50 | vs_i_r1 <= I_vs; 51 | vs_i_r2 <= vs_i_r1; 52 | vs_i_r3 <= vs_i_r2; 53 | vs_i_r4 <= vs_i_r3; 54 | end 55 | 56 | always@(posedge I_clk) begin 57 | if(!I_rstn)begin 58 | O_fs_cap <= 1'd0; 59 | end 60 | else if(VIDEO_ENABLE == 1)begin 61 | if({vs_i_r4,vs_i_r3} == 2'b01)begin 62 | O_fs_cap <= 1'b1; 63 | end 64 | else begin 65 | O_fs_cap <= 1'b0; 66 | end 67 | end 68 | else begin 69 | O_fs_cap <= vs_i_r4; 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 253 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 2048 11 | 32 12 | Enable 13 | 256 14 | 256 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | rfifo 22 | 23 | 24 | rfifo.v 25 | rfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf_only_w.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf_only_w.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf_r_baseaddr_switch.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/uidbuf_r_baseaddr_switch.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 2045 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 256 11 | 256 12 | Enable 13 | 2048 14 | 32 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | wfifo 22 | 23 | 24 | wfifo.v 25 | wfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/uisetvbuf/uisetvbuf.v: -------------------------------------------------------------------------------- 1 | 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop1: https://milianke.taobao.com 9 | *Create Date: 2023/03/23 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 1.1 20 | *Signal description 21 | *1) I_ input 22 | *2) O_ output 23 | *3) IO_ input output 24 | *3) S_ system internal signal 25 | *3) _n activ low 26 | *4) _dg debug signal 27 | *5) _r delay or register 28 | *6) _s state mechine 29 | *********************************************************************/ 30 | `timescale 1ns / 1ps 31 | 32 | module uisetvbuf#( 33 | parameter integer BUF_DELAY = 1, 34 | parameter integer BUF_LENTH = 3 35 | ) 36 | ( 37 | 38 | input [7 :0] I_bufn, 39 | output [7 :0] O_bufn 40 | ); 41 | 42 | 43 | 44 | assign O_bufn = I_bufn < BUF_DELAY? (BUF_LENTH - BUF_DELAY + I_bufn) : (I_bufn - BUF_DELAY) ; 45 | 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/vtc/uivtc.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/vtc/uivtc.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/vtc/uivtc_video_move.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/vtc/uivtc_video_move.v -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/width_conversion/rd_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:20 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:20 6 | */ 7 | 8 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 9 | module rd_width_convert( 10 | input wire [15:0] I_rd_data, 11 | 12 | output wire [31:0] O_rd_data 13 | ); 14 | 15 | 16 | assign O_rd_data ={8'd0,I_rd_data[15:11], 3'd0, I_rd_data[10:5], 2'd0,I_rd_data[4:0], 3'd0} ; 17 | 18 | 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /02_四分屏显示与全屏自由切换/03_split_screen_full_screen_switch/user_source/hdl_source/width_conversion/wr_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:27 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:27 6 | */ 7 | 8 | 9 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 10 | module wr_width_convert( 11 | input wire [31:0] I_wr_data, 12 | 13 | output wire [15:0] O_wr_data 14 | ); 15 | 16 | assign O_wr_data = {I_wr_data[23:19],I_wr_data[15:10],I_wr_data[7:3]}; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ddr_ip.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 18 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 19 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 20 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 21 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 24 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 25 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 34 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 35 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 36 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 37 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 38 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 39 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 40 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 41 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 46 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 47 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 49 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_hard_controller_0} {LOCATION = X65Y40Z0} 50 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_1$ph1_ddr_4lanes} {LOCATION = X81Y40Z0} 51 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_ddrphy_standard/u_ddrphy/ddr_phy_4lanes_2$ph1_ddr_4lanes} {LOCATION = X81Y0Z0} 52 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll0/pll_inst} { LOCATION = X81Y39Z0} 53 | set_ipinst_assignment {u_ph1_logic_standard_phy/u_clk/u_pll1/pll_inst} { LOCATION = X81Y0Z0} 54 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ddr_ip.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PH1_LOGIC_DDR_SDRAM 5 | 3.0 6 | PH1A90SBG484 7 | false 8 | ddr_ip 9 | DDR3 10 | MC and Standard PHY 11 | 1 12 | 2-1 13 | ENABLE 14 | ENABLE 15 | 4 16 | 533.000000 17 | MHz 18 | 25.000000 19 | MHz 20 | Bank31 21 | false 22 | 4:1 23 | false 24 | false 25 | false 26 | false 27 | 100.000000 28 | 100.000000 29 | 100.000000 30 | 100.000000 31 | MHz 32 | MHz 33 | MHz 34 | MHz 35 | 100.000000 36 | 100.000000 37 | 100.000000 38 | 100.000000 39 | MT41J128M16JT-125 40 | 1.5V 41 | 16 42 | false 43 | true 44 | Row_Column_Bank 45 | Normal 46 | Sequential 47 | RZQ/6 48 | RZQ/4 49 | Enable 50 | DISABLE 51 | DISABLE 52 | DISABLE 53 | ENABLE 54 | DISABLE 55 | ENABLE 56 | Pin 57 | L1,M3,K1,N2,K2,N3,K3,L3,R2,P1,U1,R3,T1,P2,R4,R1,M1,M2,N4,M5,L5,P4,Y9,W9,R7,AB6,U8,U6,W11,AA5,AA6,AB7,V9,V8,W6,AA11,U7,Y11,AA8,U12,AB8,AB10,AA10,V10,U10,Y6,AB11,T8 58 | None 59 | 60 | 61 | ddr_ip.adc 62 | ddr_ip.v 63 | ddr_ip.sdc 64 | 65 | 66 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ddr_ip_1.txt: -------------------------------------------------------------------------------- 1 | 00000042 2 | 00000000 3 | 8000042a 4 | 00000010 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | ff55f0ff 12 | ffffff54 13 | ffff89ab 14 | ffffffff 15 | ffffffff 16 | ffffffff 17 | 05_08_0d_09 18 | 0a_06_04_07 19 | 00_01_00_02 20 | 0c_0b_01_00 21 | 00_00_00_00 22 | 02_07_08_0d 23 | 09_05_0a_06 24 | 00_01_00_04 25 | 0c_0b_01_00 26 | 00_00_00_00 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 00000000 34 | 00000000 35 | 00000000 36 | 00000000 37 | 00000000 38 | 00000000 39 | 00000000 40 | 00000000 41 | 00000000 42 | 00000000 43 | 00000000 44 | 00000000 45 | 00000000 46 | 00000000 47 | 00000000 48 | 00000000 49 | 00000000 50 | 00000000 51 | 00000000 52 | 00000000 53 | 00000000 54 | 00000000 55 | 00000000 56 | 00000000 57 | 00000000 58 | 00000000 59 | 00000000 60 | 00000000 61 | 00000000 62 | 00000000 63 | 00000000 64 | 00000000 65 | 00000830 66 | 00000004 67 | 00000008 68 | 00000000 69 | 00000000 70 | 00000000 71 | 00000000 72 | 00000000 73 | 00000000 74 | 06140704 75 | 281b0004 76 | 0003005b 77 | 82000000 78 | 00560504 79 | 001b0704 80 | 00000000 81 | 030b0200 82 | bb5d9999 83 | 030b0200 84 | bb5d9999 85 | 030b0200 86 | bb5d9999 87 | 030b0200 88 | bb5d9999 89 | 030b0200 90 | bb5d9999 91 | 030b0200 92 | bb5d9999 93 | 030b0200 94 | bb5d9999 95 | 030b0200 96 | bb5d9999 97 | 030b0200 98 | bb5d9999 99 | 00000000 100 | 00000000 101 | 00000000 102 | 00000000 103 | 00000000 104 | 00000000 105 | 00000000 106 | 00000000 107 | 00000000 108 | 00000000 109 | 00000000 110 | 00000000 111 | 00000000 112 | 00000000 113 | 00000000 114 | 00000000 115 | 00000000 116 | 00000000 117 | 00000000 118 | 00000000 119 | 00000000 120 | 00000000 121 | 00000000 122 | 00000000 123 | 00000000 124 | 00000000 125 | 00000000 126 | 00000000 127 | 00000000 128 | 00000000 129 | 00000000 130 | 00000000 131 | 00000000 132 | 00000000 133 | 00000000 134 | 00000000 135 | 00000000 136 | 00000000 137 | 00000000 138 | 00000000 139 | 00000000 140 | 00000000 141 | 00000000 142 | 00000000 143 | 00000000 144 | 00000000 145 | 00000000 146 | 00000000 147 | 00000000 148 | 00000000 149 | 00000000 150 | 00000000 151 | 00000000 152 | 00000000 153 | 00000000 154 | 00000000 155 | 00000000 156 | 00000000 157 | 00000000 158 | 00000000 159 | 00000000 160 | 00000000 161 | 00000000 162 | 00000000 163 | 00000000 164 | 00000000 165 | 00000000 166 | 00000000 167 | 00000000 168 | 00000000 169 | 00000000 170 | 00000000 171 | 00000000 172 | 00000000 173 | 00000000 174 | 00000000 175 | 00000000 176 | 00000000 177 | 00000000 178 | 00000000 179 | 00000000 180 | 00000000 181 | 00000000 182 | 00000000 183 | 00000000 184 | 00000000 185 | 00000000 186 | 00000000 187 | 00000000 188 | 00000000 189 | 00000000 190 | 00000000 191 | 00000000 192 | 00000000 193 | 00000000 194 | 00000000 195 | 00000000 196 | 00000000 197 | 00000000 198 | 00000000 199 | 00000000 200 | 00000000 201 | 00000000 202 | 00000000 203 | 00000000 204 | 00000000 205 | 00000000 206 | 00000000 207 | 00000000 208 | 00000000 209 | 00000000 210 | 00000000 211 | 00000000 212 | 00000000 213 | 00000000 214 | 00000000 215 | 00000000 216 | 00000000 217 | 00000000 218 | 00000000 219 | 00000000 220 | 00000000 221 | 00000000 222 | 00000000 223 | 00000000 224 | 00000000 225 | 00000000 226 | 00000000 227 | 00000000 228 | 00000000 229 | 00000000 230 | 00000000 231 | 00000000 232 | 00000000 233 | 00000000 234 | 00000000 235 | 00000000 236 | 00000000 237 | 00000000 238 | 00000000 239 | 00000000 240 | 00000000 241 | 00000000 242 | 00000000 243 | 00000000 244 | 00000000 245 | 00000000 246 | 00000000 247 | 00000000 248 | 00000000 249 | 00000000 250 | 00000000 251 | 00000000 252 | 00000000 253 | 00000000 254 | 00000000 255 | 00000000 256 | 00000000 257 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/hdmi_pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | PH1A90SBG484 6 | true 7 | 8 | 9 | Any 10 | 75.0000000000000000MHz 11 | Normal 12 | CLKC0 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | DISABLE 17 | DISABLE 18 | DISABLE 19 | ENABLE 20 | ENABLE 21 | 22 | 23 | Medium 24 | 25 | 26 | frequncy_setting 27 | 1 28 | 1 29 | 30 | 31 | 0 32 | 15 33 | 75.0000000000000000MHz 34 | 0.0000000000000000deg 35 | 0.5 36 | false 37 | false 38 | BUFG 39 | 40 | 41 | 1 42 | 6 43 | 187.5000000000000000MHz 44 | 0.0000000000000000deg 45 | 0.5 46 | false 47 | false 48 | NONE 49 | 50 | 51 | 2 52 | 3 53 | 375.0000000000000000MHz 54 | 90.0000000000000000deg 55 | 0.5 56 | false 57 | false 58 | NONE 59 | 60 | 61 | 3 62 | 15 63 | 75.0000000000000000MHz 64 | 0.0000000000000000deg 65 | 0.5 66 | false 67 | false 68 | NONE 69 | 70 | 71 | 72 | 73 | hdmi_pll.v 74 | hdmi_pll.vhd 75 | 76 | 77 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/hdmi_pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2023 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/FPGA_compete/prj/cascade/second_card_rotate/user_source/ip_source/hdmi_pll.v 8 | ** Date : 2024 11 17 9 | ** TD version : 5.6.88061 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 75.000000MHz 14 | // Clock multiplication factor: 1 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 75.000000 MHZ | 0.0000 DEG 19 | // C1 | 187.500000MHZ | 0.0000 DEG 20 | // C2 | 375.000000MHZ | 90.0000 DEG 21 | // C3 | 75.000000 MHZ | 0.0000 DEG 22 | /////////////////////////////////////////////////////////////////////////////// 23 | `timescale 1 ns / 100 fs 24 | 25 | module hdmi_pll ( 26 | refclk, 27 | reset, 28 | lock, 29 | clk0_out, 30 | clk1_out, 31 | clk2_out, 32 | clk3_out 33 | ); 34 | 35 | input refclk; 36 | input reset; 37 | output lock; 38 | output clk0_out; 39 | output clk1_out; 40 | output clk2_out; 41 | output clk3_out; 42 | 43 | wire clk0_buf; 44 | 45 | PH1_LOGIC_BUFG bufg_feedback ( 46 | .i(clk0_buf), 47 | .o(clk0_out) 48 | ); 49 | 50 | PH1_PHY_PLL #( 51 | .DYN_PHASE_PATH_SEL("DISABLE"), 52 | .DYN_FPHASE_EN("DISABLE"), 53 | .MPHASE_ENABLE("ENABLE"), 54 | .FIN("75.000000"), 55 | .FEEDBK_MODE("NORMAL"), 56 | .FBKCLK("CLKC0_EXT"), 57 | .PLL_FEED_TYPE("EXTERNAL"), 58 | .PLL_USR_RST("ENABLE"), 59 | .GMC_GAIN(2), 60 | .ICP_CUR(12), 61 | .LPF_CAP(2), 62 | .LPF_RES(2), 63 | .REFCLK_DIV(1), 64 | .FBCLK_DIV(1), 65 | .CLKC0_ENABLE("ENABLE"), 66 | .CLKC0_DIV(15), 67 | .CLKC0_CPHASE(14), 68 | .CLKC0_FPHASE(0), 69 | .CLKC0_FPHASE_RSTSEL(0), 70 | .CLKC0_DUTY_INT(8), 71 | .CLKC0_DUTY50("ENABLE"), 72 | .CLKC1_ENABLE("ENABLE"), 73 | .CLKC1_DIV(6), 74 | .CLKC1_CPHASE(5), 75 | .CLKC1_FPHASE(0), 76 | .CLKC1_FPHASE_RSTSEL(0), 77 | .CLKC1_DUTY_INT(3), 78 | .CLKC1_DUTY50("ENABLE"), 79 | .CLKC2_ENABLE("ENABLE"), 80 | .CLKC2_DIV(3), 81 | .CLKC2_CPHASE(2), 82 | .CLKC2_FPHASE(6), 83 | .CLKC2_FPHASE_RSTSEL(1), 84 | .CLKC2_DUTY_INT(2), 85 | .CLKC2_DUTY50("ENABLE"), 86 | .CLKC3_ENABLE("ENABLE"), 87 | .CLKC3_DIV(15), 88 | .CLKC3_CPHASE(14), 89 | .CLKC3_FPHASE(0), 90 | .CLKC3_FPHASE_RSTSEL(0), 91 | .CLKC3_DUTY_INT(8), 92 | .CLKC3_DUTY50("ENABLE"), 93 | .INTPI(1), 94 | .HIGH_SPEED_EN("DISABLE"), 95 | .SSC_ENABLE("DISABLE"), 96 | .SSC_MODE("CENTER"), 97 | .SSC_AMP(0.0000), 98 | .SSC_FREQ_DIV(0), 99 | .SSC_RNGE(0), 100 | .FRAC_ENABLE("DISABLE"), 101 | .DITHER_ENABLE("DISABLE"), 102 | .SDM_FRAC(0) 103 | ) pll_inst ( 104 | .refclk(refclk), 105 | .pllreset(reset), 106 | .lock(lock), 107 | .pllpd(1'b0), 108 | .refclk_rst(1'b0), 109 | .wakeup(1'b0), 110 | .psclk(1'b0), 111 | .psdown(1'b0), 112 | .psstep(1'b0), 113 | .psclksel(3'b000), 114 | .psdone(open), 115 | .cps_step(2'b00), 116 | .drp_clk(1'b0), 117 | .drp_rstn(1'b1), 118 | .drp_sel(1'b0), 119 | .drp_rd(1'b0), 120 | .drp_wr(1'b0), 121 | .drp_addr(8'b00000000), 122 | .drp_wdata(8'b00000000), 123 | .drp_err(open), 124 | .drp_rdy(open), 125 | .drp_rdata({open, open, open, open, open, open, open, open}), 126 | .fbclk(clk0_out), 127 | .clkc({open, open, open, open, clk3_out, clk2_out, clk1_out, clk0_buf}), 128 | .clkcb({open, open, open, open, open, open, open, open}), 129 | .clkc_en({8'b00001111}), 130 | .clkc_rst(2'b00), 131 | .ext_freq_mod_clk(1'b0), 132 | .ext_freq_mod_en(1'b0), 133 | .ext_freq_mod_val(17'b00000000000000000), 134 | .ssc_en(1'b0) 135 | ); 136 | 137 | endmodule 138 | 139 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/hdmi_pll.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2023 Anlogic Inc. 3 | -- All Right Reserved. 4 | -------------------------------------------------------------- 5 | -- Log : This file is generated by Anlogic IP Generator. 6 | -- File : C:/HIT/personal_learn/FPGA_compete/prj/cascade/second_card_rotate/user_source/ip_source/hdmi_pll.vhd 7 | -- Date : 2024 11 17 8 | -- TD version : 5.6.88061 9 | -------------------------------------------------------------- 10 | 11 | ------------------------------------------------------------------------------- 12 | -- Input frequency: 75.000000MHz 13 | -- Clock multiplication factor: 1 14 | -- Clock division factor: 1 15 | -- Clock information: 16 | -- Clock name | Frequency | Phase shift 17 | -- C0 | 75.000000 MHZ | 0.0000 DEG 18 | -- C1 | 187.500000MHZ | 0.0000 DEG 19 | -- C2 | 375.000000MHZ | 90.0000 DEG 20 | -- C3 | 75.000000 MHZ | 0.0000 DEG 21 | ------------------------------------------------------------------------------- 22 | 23 | LIBRARY ieee; 24 | USE ieee.std_logic_1164.ALL; 25 | USE ieee.numeric_std.ALL; 26 | USE ieee.std_logic_unsigned.ALL; 27 | USE ieee.std_logic_arith.ALL; 28 | LIBRARY ph1_macro; 29 | USE ph1_macro.PH1_COMPONENTS.ALL; 30 | 31 | ENTITY hdmi_pll IS 32 | PORT ( 33 | refclk : IN STD_LOGIC; 34 | reset : IN STD_LOGIC; 35 | lock : OUT STD_LOGIC; 36 | clk0_out : OUT STD_LOGIC; 37 | clk1_out : OUT STD_LOGIC; 38 | clk2_out : OUT STD_LOGIC; 39 | clk3_out : OUT STD_LOGIC 40 | ); 41 | END hdmi_pll; 42 | 43 | ARCHITECTURE rtl OF hdmi_pll IS 44 | SIGNAL clk0_buf : STD_LOGIC; 45 | SIGNAL fbk_wire : STD_LOGIC; 46 | SIGNAL clkc_en_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 47 | SIGNAL clkc_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 48 | SIGNAL clkcb_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 49 | BEGIN 50 | bufg_feedback : PH1_LOGIC_BUFG 51 | PORT MAP ( 52 | i => clk0_buf, 53 | o => fbk_wire 54 | ); 55 | 56 | pll_inst : PH1_PHY_PLL 57 | GENERIC MAP ( 58 | DYN_PHASE_PATH_SEL => "DISABLE", 59 | DYN_FPHASE_EN => "DISABLE", 60 | MPHASE_ENABLE => "ENABLE", 61 | FIN => "75.000000", 62 | FEEDBK_MODE => "NORMAL", 63 | FBKCLK => "CLKC0_EXT", 64 | PLL_FEED_TYPE => "EXTERNAL", 65 | PLL_USR_RST => "ENABLE", 66 | GMC_GAIN => 2, 67 | ICP_CUR => 12, 68 | LPF_CAP => 2, 69 | LPF_RES => 2, 70 | REFCLK_DIV => 1, 71 | FBCLK_DIV => 1, 72 | CLKC0_ENABLE => "ENABLE", 73 | CLKC0_DIV => 15, 74 | CLKC0_CPHASE => 14, 75 | CLKC0_FPHASE => 0, 76 | CLKC0_FPHASE_RSTSEL => 0, 77 | CLKC0_DUTY_INT => 8, 78 | CLKC0_DUTY50 => "ENABLE", 79 | CLKC1_ENABLE => "ENABLE", 80 | CLKC1_DIV => 6, 81 | CLKC1_CPHASE => 5, 82 | CLKC1_FPHASE => 0, 83 | CLKC1_FPHASE_RSTSEL => 0, 84 | CLKC1_DUTY_INT => 3, 85 | CLKC1_DUTY50 => "ENABLE", 86 | CLKC2_ENABLE => "ENABLE", 87 | CLKC2_DIV => 3, 88 | CLKC2_CPHASE => 2, 89 | CLKC2_FPHASE => 6, 90 | CLKC2_FPHASE_RSTSEL => 1, 91 | CLKC2_DUTY_INT => 2, 92 | CLKC2_DUTY50 => "ENABLE", 93 | CLKC3_ENABLE => "ENABLE", 94 | CLKC3_DIV => 15, 95 | CLKC3_CPHASE => 14, 96 | CLKC3_FPHASE => 0, 97 | CLKC3_FPHASE_RSTSEL => 0, 98 | CLKC3_DUTY_INT => 8, 99 | CLKC3_DUTY50 => "ENABLE", 100 | INTPI => 1, 101 | HIGH_SPEED_EN => "DISABLE", 102 | SSC_ENABLE => "DISABLE", 103 | SSC_MODE => "CENTER", 104 | SSC_AMP => 0.0000, 105 | SSC_FREQ_DIV => 0, 106 | SSC_RNGE => 0, 107 | FRAC_ENABLE => "DISABLE", 108 | DITHER_ENABLE => "DISABLE", 109 | SDM_FRAC => 0 110 | ) 111 | PORT MAP ( 112 | refclk => refclk, 113 | pllreset => reset, 114 | lock => lock, 115 | pllpd => '0', 116 | refclk_rst => '0', 117 | wakeup => '0', 118 | psclk => '0', 119 | psdown => '0', 120 | psstep => '0', 121 | psclksel => b"000", 122 | cps_step => b"00", 123 | drp_clk => '0', 124 | drp_rstn => '1', 125 | drp_sel => '0', 126 | drp_rd => '0', 127 | drp_wr => '0', 128 | drp_addr => b"00000000", 129 | drp_wdata => b"00000000", 130 | fbclk => fbk_wire, 131 | clkc => clkc_wire, 132 | clkcb => clkcb_wire, 133 | clkc_en => clkc_en_wire, 134 | clkc_rst => b"00", 135 | ext_freq_mod_clk => '0', 136 | ext_freq_mod_en => '0', 137 | ext_freq_mod_val => b"00000000000000000", 138 | ssc_en => '0' 139 | ); 140 | 141 | clk0_out <= fbk_wire; 142 | clkc_en_wire <= b"00001111"; 143 | clk3_out <= clkc_wire(3); 144 | clk2_out <= clkc_wire(2); 145 | clk1_out <= clkc_wire(1); 146 | clk0_buf <= clkc_wire(0); 147 | 148 | END rtl; 149 | 150 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/.m_params_ila.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/.m_params_ila.txt -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/.ports_ila.txt: -------------------------------------------------------------------------------- 1 | probe0; 1 2 | probe1; 1 3 | probe2; 1 4 | probe3; 1 5 | probe4; 1 6 | probe5; 1 7 | probe6; 0 8 | probe7; 0 9 | probe8; 0 10 | probe9; 0 11 | probe10; 0 12 | probe11; 0 13 | probe12; 0 14 | probe13; 0 15 | probe14; 0 16 | probe15; 0 17 | probe16; 0 18 | probe17; 0 19 | probe18; 0 20 | probe19; 0 21 | probe20; 0 22 | probe21; 0 23 | probe22; 0 24 | probe23; 0 25 | probe24; 0 26 | probe25; 0 27 | probe26; 0 28 | probe27; 0 29 | probe28; 0 30 | probe29; 0 31 | probe30; 0 32 | probe31; 0 33 | probe32; 0 34 | probe33; 0 35 | probe34; 0 36 | probe35; 0 37 | probe36; 0 38 | probe37; 0 39 | probe38; 0 40 | probe39; 0 41 | probe40; 0 42 | probe41; 0 43 | probe42; 0 44 | probe43; 0 45 | probe44; 0 46 | probe45; 0 47 | probe46; 0 48 | probe47; 0 49 | probe48; 0 50 | probe49; 0 51 | probe50; 0 52 | probe51; 0 53 | probe52; 0 54 | probe53; 0 55 | probe54; 0 56 | probe55; 0 57 | probe56; 0 58 | probe57; 0 59 | probe58; 0 60 | probe59; 0 61 | probe60; 0 62 | probe61; 0 63 | probe62; 0 64 | probe63; 0 65 | clk; 1 -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/ChipWatcher_e89d8dc9dd72.sv: -------------------------------------------------------------------------------- 1 | 2 | module ChipWatcher_e89d8dc9dd72 ( 3 | input [9:0] probe0, 4 | input [0:0] probe1, 5 | input [14:0] probe2, 6 | input [9:0] probe3, 7 | input [0:0] probe4, 8 | input [14:0] probe5, 9 | input clk 10 | ); 11 | localparam CWC_BUS_NUM = 6; 12 | localparam CWC_BUS_DIN_NUM = 52; 13 | localparam INPUT_PIPE_NUM = 0; 14 | localparam OUTPUT_PIPE_NUM = 0; 15 | localparam RAM_LEN = 52; 16 | localparam RAM_DATA_DEPTH = 4096; 17 | 18 | 19 | localparam integer CWC_BUS_WIDTH[0:CWC_BUS_NUM-1] = {15,1,10,15,1,10}; 20 | localparam integer CWC_BUS_DIN_POS[0:CWC_BUS_NUM-1] = {0,15,16,26,41,42}; 21 | localparam integer CWC_BUS_CTRL_POS[0:CWC_BUS_NUM-1] = {0,34,40,64,98,104}; 22 | 23 | parameter STAT_REG_LEN = 24; 24 | parameter BUS_CTRL_NUM = CWC_BUS_NUM*4 + CWC_BUS_DIN_NUM*2 + 36; 25 | 26 | wire cwc_rst; 27 | wire [BUS_CTRL_NUM-1:0] cwc_control; 28 | wire [STAT_REG_LEN-1:0] cwc_status; 29 | 30 | top_cwc_hub #( 31 | .CWC_BUS_NUM(CWC_BUS_NUM), 32 | .CWC_BUS_DIN_NUM(CWC_BUS_DIN_NUM), 33 | .CWC_BUS_WIDTH(CWC_BUS_WIDTH), 34 | .CWC_BUS_DIN_POS(CWC_BUS_DIN_POS), 35 | .CWC_BUS_CTRL_POS(CWC_BUS_CTRL_POS), 36 | .RAM_DATA_DEPTH(RAM_DATA_DEPTH), 37 | .RAM_LEN(RAM_LEN), 38 | .INPUT_PIPE_NUM(INPUT_PIPE_NUM), 39 | .OUTPUT_PIPE_NUM(OUTPUT_PIPE_NUM) 40 | ) 41 | 42 | wrapper_cwc_top( 43 | .cwc_trig_clk(clk), 44 | .cwc_control(cwc_control), 45 | .cwc_status(cwc_status), 46 | .cwc_rst(cwc_rst), 47 | .cwc_bus_din({probe0,probe1,probe2,probe3,probe4,probe5}), 48 | .ram_data_din({probe0,probe1,probe2,probe3,probe4,probe5}) 49 | ); 50 | 51 | AL_LOGIC_DEBUGHUB #( 52 | .CTRL_LEN(BUS_CTRL_NUM), 53 | .STAT_LEN(STAT_REG_LEN) 54 | ) wrapper_debughub( 55 | .clk(clk), 56 | .control(cwc_control), 57 | .status(cwc_status), 58 | .rst(cwc_rst) 59 | ); 60 | 61 | endmodule 62 | 63 | 64 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/DesignConfiguration.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | anlogic.com 4 | customized 5 | designConfig_ila 6 | 1.0 7 | 8 | ChipWatcher_e89d8dc9dd72_Inst 9 | 10 | 11 | 12 | Chip Watcher 13 | 1.0 14 | 15 | 16 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/ila/ila.sv: -------------------------------------------------------------------------------- 1 | module ila 2 | ( 3 | input [9:0] probe0, 4 | input [0:0] probe1, 5 | input [14:0] probe2, 6 | input [9:0] probe3, 7 | input [0:0] probe4, 8 | input [14:0] probe5, 9 | input clk 10 | ); 11 | 12 | ChipWatcher_e89d8dc9dd72 ChipWatcher_e89d8dc9dd72_Inst 13 | ( 14 | .probe0(probe0), 15 | .probe1(probe1), 16 | .probe2(probe2), 17 | .probe3(probe3), 18 | .probe4(probe4), 19 | .probe5(probe5), 20 | .clk(clk) 21 | ); 22 | endmodule 23 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/pll.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | PLL 5 | PH1A90SBG484 6 | true 7 | 8 | 9 | Any 10 | 25.0000000000000000MHz 11 | Normal 12 | CLKC0 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | DISABLE 17 | DISABLE 18 | DISABLE 19 | ENABLE 20 | ENABLE 21 | 22 | 23 | Medium 24 | 25 | 26 | frequncy_setting 27 | 3 28 | 1 29 | 30 | 31 | 0 32 | 15 33 | 75.0000000000000000MHz 34 | 0.0000000000000000deg 35 | 0.5 36 | false 37 | false 38 | BUFG 39 | 40 | 41 | 1 42 | 3 43 | 375.0000000000000000MHz 44 | 0.0000000000000000deg 45 | 0.5 46 | false 47 | false 48 | NONE 49 | 50 | 51 | 52 | 53 | pll.vhd 54 | pll.v 55 | 56 | 57 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/pll.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2024 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.v 8 | ** Date : 2024 12 07 9 | ** TD version : 6.0.117864 10 | \************************************************************/ 11 | 12 | /////////////////////////////////////////////////////////////////////////////// 13 | // Input frequency: 25.000000MHz 14 | // Clock multiplication factor: 3 15 | // Clock division factor: 1 16 | // Clock information: 17 | // Clock name | Frequency | Phase shift 18 | // C0 | 75.000000 MHZ | 0.0000 DEG 19 | // C1 | 375.000000MHZ | 0.0000 DEG 20 | /////////////////////////////////////////////////////////////////////////////// 21 | `timescale 1 ns / 100 fs 22 | 23 | module pll ( 24 | refclk, 25 | reset, 26 | lock, 27 | clk0_out, 28 | clk1_out 29 | ); 30 | 31 | input refclk; 32 | input reset; 33 | output lock; 34 | output clk0_out; 35 | output clk1_out; 36 | 37 | wire clk0_buf; 38 | 39 | PH1_LOGIC_BUFG bufg_feedback ( 40 | .i(clk0_buf), 41 | .o(clk0_out) 42 | ); 43 | 44 | PH1_PHY_PLL #( 45 | .DYN_PHASE_PATH_SEL("DISABLE"), 46 | .DYN_FPHASE_EN("DISABLE"), 47 | .MPHASE_ENABLE("DISABLE"), 48 | .FIN("25.000000"), 49 | .FEEDBK_MODE("NORMAL"), 50 | .FBKCLK("CLKC0_EXT"), 51 | .PLL_FEED_TYPE("EXTERNAL"), 52 | .PLL_USR_RST("ENABLE"), 53 | .GMC_GAIN(1), 54 | .ICP_CUR(11), 55 | .LPF_CAP(2), 56 | .LPF_RES(3), 57 | .REFCLK_DIV(1), 58 | .FBCLK_DIV(3), 59 | .CLKC0_ENABLE("ENABLE"), 60 | .CLKC0_DIV(15), 61 | .CLKC0_CPHASE(14), 62 | .CLKC0_FPHASE(0), 63 | .CLKC0_FPHASE_RSTSEL(0), 64 | .CLKC0_DUTY_INT(8), 65 | .CLKC0_DUTY50("ENABLE"), 66 | .CLKC1_ENABLE("ENABLE"), 67 | .CLKC1_DIV(3), 68 | .CLKC1_CPHASE(2), 69 | .CLKC1_FPHASE(0), 70 | .CLKC1_FPHASE_RSTSEL(0), 71 | .CLKC1_DUTY_INT(2), 72 | .CLKC1_DUTY50("ENABLE"), 73 | .INTPI(1), 74 | .HIGH_SPEED_EN("DISABLE"), 75 | .SSC_ENABLE("DISABLE"), 76 | .SSC_MODE("CENTER"), 77 | .SSC_AMP(0.0000), 78 | .SSC_FREQ_DIV(0), 79 | .SSC_RNGE(0), 80 | .FRAC_ENABLE("DISABLE"), 81 | .DITHER_ENABLE("DISABLE"), 82 | .SDM_FRAC(0) 83 | ) pll_inst ( 84 | .refclk(refclk), 85 | .pllreset(reset), 86 | .lock(lock), 87 | .pllpd(1'b0), 88 | .refclk_rst(1'b0), 89 | .wakeup(1'b0), 90 | .psclk(1'b0), 91 | .psdown(1'b0), 92 | .psstep(1'b0), 93 | .psclksel(3'b000), 94 | .psdone(pll_open0), 95 | .cps_step(2'b00), 96 | .drp_clk(1'b0), 97 | .drp_rstn(1'b1), 98 | .drp_sel(1'b0), 99 | .drp_rd(1'b0), 100 | .drp_wr(1'b0), 101 | .drp_addr(8'b00000000), 102 | .drp_wdata(8'b00000000), 103 | .drp_err(pll_open1), 104 | .drp_rdy(pll_open2), 105 | .drp_rdata({pll_open10, pll_open9, pll_open8, pll_open7, pll_open6, pll_open5, pll_open4, pll_open3}), 106 | .fbclk(clk0_out), 107 | .clkc({pll_open23, pll_open21, pll_open19, pll_open17, pll_open15, pll_open13, clk1_out, clk0_buf}), 108 | .clkcb({pll_open24, pll_open22, pll_open20, pll_open18, pll_open16, pll_open14, pll_open12, pll_open11}), 109 | .clkc_en({8'b00000011}), 110 | .clkc_rst(2'b00), 111 | .ext_freq_mod_clk(1'b0), 112 | .ext_freq_mod_en(1'b0), 113 | .ext_freq_mod_val(17'b00000000000000000), 114 | .ssc_en(1'b0) 115 | ); 116 | 117 | endmodule 118 | 119 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/al_ip/pll.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2024 Anlogic Inc. -- All Right Reserved. 3 | -------------------------------------------------------------- 4 | -- Log : This file is generated by Anlogic IP Generator. 5 | -- File : C:/HIT/personal_learn/open_source/01_four_channel_viideo_splicer/td_project/al_ip/pll.vhd 6 | -- Date : 2024 12 07 7 | -- TD version : 6.0.117864 8 | -------------------------------------------------------------- 9 | 10 | ------------------------------------------------------------------------------- 11 | -- Input frequency: 25.000000MHz 12 | -- Clock multiplication factor: 3 13 | -- Clock division factor: 1 14 | -- Clock information: 15 | -- Clock name | Frequency | Phase shift 16 | -- C0 | 75.000000 MHZ | 0.0000 DEG 17 | -- C1 | 375.000000MHZ | 0.0000 DEG 18 | ------------------------------------------------------------------------------- 19 | 20 | LIBRARY ieee; 21 | USE ieee.std_logic_1164.ALL; 22 | USE ieee.numeric_std.ALL; 23 | USE ieee.std_logic_unsigned.ALL; 24 | USE ieee.std_logic_arith.ALL; 25 | LIBRARY ph1_macro; 26 | USE ph1_macro.PH1_COMPONENTS.ALL; 27 | 28 | ENTITY pll IS 29 | PORT ( 30 | refclk : IN STD_LOGIC; 31 | reset : IN STD_LOGIC; 32 | lock : OUT STD_LOGIC; 33 | clk0_out : OUT STD_LOGIC; 34 | clk1_out : OUT STD_LOGIC 35 | ); 36 | END pll; 37 | 38 | ARCHITECTURE rtl OF pll IS 39 | SIGNAL clk0_buf : STD_LOGIC; 40 | SIGNAL fbk_wire : STD_LOGIC; 41 | SIGNAL clkc_en_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 42 | SIGNAL clkc_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 43 | SIGNAL clkcb_wire : STD_LOGIC_VECTOR (7 DOWNTO 0); 44 | BEGIN 45 | bufg_feedback : PH1_LOGIC_BUFG 46 | PORT MAP ( 47 | i => clk0_buf, 48 | o => fbk_wire 49 | ); 50 | 51 | pll_inst : PH1_PHY_PLL 52 | GENERIC MAP ( 53 | DYN_PHASE_PATH_SEL => "DISABLE", 54 | DYN_FPHASE_EN => "DISABLE", 55 | MPHASE_ENABLE => "DISABLE", 56 | FIN => "25.000000", 57 | FEEDBK_MODE => "NORMAL", 58 | FBKCLK => "CLKC0_EXT", 59 | PLL_FEED_TYPE => "EXTERNAL", 60 | PLL_USR_RST => "ENABLE", 61 | GMC_GAIN => 1, 62 | ICP_CUR => 11, 63 | LPF_CAP => 2, 64 | LPF_RES => 3, 65 | REFCLK_DIV => 1, 66 | FBCLK_DIV => 3, 67 | CLKC0_ENABLE => "ENABLE", 68 | CLKC0_DIV => 15, 69 | CLKC0_CPHASE => 14, 70 | CLKC0_FPHASE => 0, 71 | CLKC0_FPHASE_RSTSEL => 0, 72 | CLKC0_DUTY_INT => 8, 73 | CLKC0_DUTY50 => "ENABLE", 74 | CLKC1_ENABLE => "ENABLE", 75 | CLKC1_DIV => 3, 76 | CLKC1_CPHASE => 2, 77 | CLKC1_FPHASE => 0, 78 | CLKC1_FPHASE_RSTSEL => 0, 79 | CLKC1_DUTY_INT => 2, 80 | CLKC1_DUTY50 => "ENABLE", 81 | INTPI => 1, 82 | HIGH_SPEED_EN => "DISABLE", 83 | SSC_ENABLE => "DISABLE", 84 | SSC_MODE => "CENTER", 85 | SSC_AMP => 0.0000, 86 | SSC_FREQ_DIV => 0, 87 | SSC_RNGE => 0, 88 | FRAC_ENABLE => "DISABLE", 89 | DITHER_ENABLE => "DISABLE", 90 | SDM_FRAC => 0 91 | ) 92 | PORT MAP ( 93 | refclk => refclk, 94 | pllreset => reset, 95 | lock => lock, 96 | pllpd => '0', 97 | refclk_rst => '0', 98 | wakeup => '0', 99 | psclk => '0', 100 | psdown => '0', 101 | psstep => '0', 102 | psclksel => b"000", 103 | cps_step => b"00", 104 | drp_clk => '0', 105 | drp_rstn => '1', 106 | drp_sel => '0', 107 | drp_rd => '0', 108 | drp_wr => '0', 109 | drp_addr => b"00000000", 110 | drp_wdata => b"00000000", 111 | fbclk => fbk_wire, 112 | clkc => clkc_wire, 113 | clkcb => clkcb_wire, 114 | clkc_en => clkc_en_wire, 115 | clkc_rst => b"00", 116 | ext_freq_mod_clk => '0', 117 | ext_freq_mod_en => '0', 118 | ext_freq_mod_val => b"00000000000000000", 119 | ssc_en => '0' 120 | ); 121 | 122 | clk0_out <= fbk_wire; 123 | clkc_en_wire <= b"00000011"; 124 | clk1_out <= clkc_wire(1); 125 | clk0_buf <= clkc_wire(0); 126 | 127 | END rtl; 128 | 129 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/fpga_prj_Runs/best_result/fpga_prj.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/td_project/fpga_prj_Runs/best_result/fpga_prj.bit -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/fpga_prj_Runs/best_result/fpga_prj_compress.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/td_project/fpga_prj_Runs/best_result/fpga_prj_compress.bit -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/td_project/fpga_prj_Runs/best_result/readMe.txt: -------------------------------------------------------------------------------- 1 | The implemented result of phy_1 is saved as best result. 2 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/constraints_source/ap106_ddr_pin.adc: -------------------------------------------------------------------------------- 1 | set_ippin_assignment { ddr_dq[0] } {LOCATION = L1; IOSTANDARD = SSTL15; } 2 | set_ippin_assignment { ddr_dq[1] } {LOCATION = M3; IOSTANDARD = SSTL15; } 3 | set_ippin_assignment { ddr_dq[2] } {LOCATION = K1; IOSTANDARD = SSTL15; } 4 | set_ippin_assignment { ddr_dq[3] } {LOCATION = N2; IOSTANDARD = SSTL15; } 5 | set_ippin_assignment { ddr_dq[4] } {LOCATION = K2; IOSTANDARD = SSTL15; } 6 | set_ippin_assignment { ddr_dq[5] } {LOCATION = N3; IOSTANDARD = SSTL15; } 7 | set_ippin_assignment { ddr_dq[6] } {LOCATION = K3; IOSTANDARD = SSTL15; } 8 | set_ippin_assignment { ddr_dq[7] } {LOCATION = L3; IOSTANDARD = SSTL15; } 9 | set_ippin_assignment { ddr_dq[8] } {LOCATION = R2; IOSTANDARD = SSTL15; } 10 | set_ippin_assignment { ddr_dq[9] } {LOCATION = P1; IOSTANDARD = SSTL15; } 11 | set_ippin_assignment { ddr_dq[10] } {LOCATION = U1; IOSTANDARD = SSTL15; } 12 | set_ippin_assignment { ddr_dq[11] } {LOCATION = R3; IOSTANDARD = SSTL15; } 13 | set_ippin_assignment { ddr_dq[12] } {LOCATION = T1; IOSTANDARD = SSTL15; } 14 | set_ippin_assignment { ddr_dq[13] } {LOCATION = P2; IOSTANDARD = SSTL15; } 15 | set_ippin_assignment { ddr_dq[14] } {LOCATION = R4; IOSTANDARD = SSTL15; } 16 | set_ippin_assignment { ddr_dq[15] } {LOCATION = R1; IOSTANDARD = SSTL15; } 17 | set_ippin_assignment { ddr_dq[16] } {LOCATION = U3; IOSTANDARD = SSTL15; } 18 | set_ippin_assignment { ddr_dq[17] } {LOCATION = W2; IOSTANDARD = SSTL15; } 19 | set_ippin_assignment { ddr_dq[18] } {LOCATION = T4; IOSTANDARD = SSTL15; } 20 | set_ippin_assignment { ddr_dq[19] } {LOCATION = W4; IOSTANDARD = SSTL15; } 21 | set_ippin_assignment { ddr_dq[20] } {LOCATION = V4; IOSTANDARD = SSTL15; } 22 | set_ippin_assignment { ddr_dq[21] } {LOCATION = U5; IOSTANDARD = SSTL15; } 23 | set_ippin_assignment { ddr_dq[22] } {LOCATION = V3; IOSTANDARD = SSTL15; } 24 | set_ippin_assignment { ddr_dq[23] } {LOCATION = T5; IOSTANDARD = SSTL15; } 25 | set_ippin_assignment { ddr_dq[24] } {LOCATION = AA3; IOSTANDARD = SSTL15; } 26 | set_ippin_assignment { ddr_dq[25] } {LOCATION = W1; IOSTANDARD = SSTL15; } 27 | set_ippin_assignment { ddr_dq[26] } {LOCATION = AB3; IOSTANDARD = SSTL15; } 28 | set_ippin_assignment { ddr_dq[27] } {LOCATION = AB2; IOSTANDARD = SSTL15; } 29 | set_ippin_assignment { ddr_dq[28] } {LOCATION = W5; IOSTANDARD = SSTL15; } 30 | set_ippin_assignment { ddr_dq[29] } {LOCATION = AB1; IOSTANDARD = SSTL15; } 31 | set_ippin_assignment { ddr_dq[30] } {LOCATION = AA1; IOSTANDARD = SSTL15; } 32 | set_ippin_assignment { ddr_dq[31] } {LOCATION = Y1; IOSTANDARD = SSTL15; } 33 | set_ippin_assignment { ddr_dqs_n[0] } {LOCATION = M1; IOSTANDARD = DIFF_SSTL15; } 34 | set_ippin_assignment { ddr_dqs_p[0] } {LOCATION = M2; IOSTANDARD = DIFF_SSTL15; } 35 | set_ippin_assignment { ddr_dqs_n[1] } {LOCATION = N4; IOSTANDARD = DIFF_SSTL15; } 36 | set_ippin_assignment { ddr_dqs_p[1] } {LOCATION = M5; IOSTANDARD = DIFF_SSTL15; } 37 | set_ippin_assignment { ddr_dqs_n[2] } {LOCATION = V2; IOSTANDARD = DIFF_SSTL15; } 38 | set_ippin_assignment { ddr_dqs_p[2] } {LOCATION = U2; IOSTANDARD = DIFF_SSTL15; } 39 | set_ippin_assignment { ddr_dqs_n[3] } {LOCATION = Y2; IOSTANDARD = DIFF_SSTL15; } 40 | set_ippin_assignment { ddr_dqs_p[3] } {LOCATION = Y3; IOSTANDARD = DIFF_SSTL15; } 41 | set_ippin_assignment { ddr_dm[0] } {LOCATION = L5; IOSTANDARD = SSTL15; } 42 | set_ippin_assignment { ddr_dm[1] } {LOCATION = P4; IOSTANDARD = SSTL15; } 43 | set_ippin_assignment { ddr_dm[2] } {LOCATION = N5; IOSTANDARD = SSTL15; } 44 | set_ippin_assignment { ddr_dm[3] } {LOCATION = AA4; IOSTANDARD = SSTL15; } 45 | set_ippin_assignment { ddr_ck_n[0] } {LOCATION = Y9; IOSTANDARD = DIFF_SSTL15; } 46 | set_ippin_assignment { ddr_ck_p[0] } {LOCATION = W9; IOSTANDARD = DIFF_SSTL15; } 47 | set_ippin_assignment { ddr_ras_n } {LOCATION = R7; IOSTANDARD = SSTL15; } 48 | set_ippin_assignment { ddr_cas_n } {LOCATION = AB6; IOSTANDARD = SSTL15; } 49 | set_ippin_assignment { ddr_we_n } {LOCATION = U8; IOSTANDARD = SSTL15; } 50 | set_ippin_assignment { ddr_reset_n } {LOCATION = U6; IOSTANDARD = SSTL15; } 51 | set_ippin_assignment { ddr_cke[0] } {LOCATION = W11; IOSTANDARD = SSTL15; } 52 | set_ippin_assignment { ddr_cs_n[0] } {LOCATION = AA5; IOSTANDARD = SSTL15; } 53 | set_ippin_assignment { ddr_odt[0] } {LOCATION = AA6; IOSTANDARD = SSTL15; } 54 | set_ippin_assignment { ddr_addr[0] } {LOCATION = AB7; IOSTANDARD = SSTL15; } 55 | set_ippin_assignment { ddr_addr[1] } {LOCATION = V9; IOSTANDARD = SSTL15; } 56 | set_ippin_assignment { ddr_addr[2] } {LOCATION = V8; IOSTANDARD = SSTL15; } 57 | set_ippin_assignment { ddr_addr[3] } {LOCATION = W6; IOSTANDARD = SSTL15; } 58 | set_ippin_assignment { ddr_addr[4] } {LOCATION = AA11; IOSTANDARD = SSTL15; } 59 | set_ippin_assignment { ddr_addr[5] } {LOCATION = U7; IOSTANDARD = SSTL15; } 60 | set_ippin_assignment { ddr_addr[6] } {LOCATION = Y11; IOSTANDARD = SSTL15; } 61 | set_ippin_assignment { ddr_addr[7] } {LOCATION = AA8; IOSTANDARD = SSTL15; } 62 | set_ippin_assignment { ddr_addr[8] } {LOCATION = U12; IOSTANDARD = SSTL15; } 63 | set_ippin_assignment { ddr_addr[9] } {LOCATION = AB8; IOSTANDARD = SSTL15; } 64 | set_ippin_assignment { ddr_addr[10] } {LOCATION = AB10; IOSTANDARD = SSTL15; } 65 | set_ippin_assignment { ddr_addr[11] } {LOCATION = AA10; IOSTANDARD = SSTL15; } 66 | set_ippin_assignment { ddr_addr[12] } {LOCATION = V10; IOSTANDARD = SSTL15; } 67 | set_ippin_assignment { ddr_addr[13] } {LOCATION = U10; IOSTANDARD = SSTL15; } 68 | set_ippin_assignment { ddr_ba[0] } {LOCATION = Y6; IOSTANDARD = SSTL15; } 69 | set_ippin_assignment { ddr_ba[1] } {LOCATION = AB11; IOSTANDARD = SSTL15; } 70 | set_ippin_assignment { ddr_ba[2] } {LOCATION = T8; IOSTANDARD = SSTL15; } 71 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/constraints_source/pin.adc: -------------------------------------------------------------------------------- 1 | set_pin_assignment { I_rst_n } { LOCATION = K4; IOSTANDARD = LVCMOS15; PULLTYPE = PULLUP; } 2 | set_pin_assignment { I_sys_clk } { LOCATION = N18; IOSTANDARD = LVCMOS33; PULLTYPE = PULLUP; } 3 | 4 | set_pin_assignment { O_uart_txd } { LOCATION = R22 ; IOSTANDARD = LVCMOS33;} 5 | set_pin_assignment { I_uart_rxd } { LOCATION = M16 ; IOSTANDARD = LVCMOS33; } 6 | 7 | set_pin_assignment { O_hdmi_tx_p[0] } { LOCATION = V13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 8 | set_pin_assignment { O_hdmi_tx_p[1] } { LOCATION = Y12; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 9 | set_pin_assignment { O_hdmi_tx_p[2] } { LOCATION = T13; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 10 | set_pin_assignment { O_hdmi_clk_p } { LOCATION = V17; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 11 | 12 | set_pin_assignment { I_hdmi_rx_ch0_p } { LOCATION = U22; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 13 | set_pin_assignment { I_hdmi_rx_ch1_p } { LOCATION = T20; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 14 | set_pin_assignment { I_hdmi_rx_ch2_p } { LOCATION = U21; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 15 | set_pin_assignment { I_hdmi_rx_clk_p } { LOCATION = V20; IOSTANDARD = LVDS25; PULLTYPE = NONE; } 16 | set_pin_assignment { I_hdmi_rx_ddc_scl } { LOCATION = T19; IOSTANDARD = LVCMOS25; PULLTYPE = PULLUP; } 17 | set_pin_assignment { IO_hdmi_rx_ddc_sda } { LOCATION = U20; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = PULLUP; } 18 | set_pin_assignment { O_hdmi_rx_hpd } { LOCATION = W19; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = PULLUP; } 19 | set_pin_assignment { O_hdmi_tx_ddc_scl } { LOCATION = W14; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = PULLUP; } 20 | set_pin_assignment { IO_hdmi_tx_ddc_sda } { LOCATION = W15; IOSTANDARD = LVCMOS25; DRIVESTRENGTH = 8; PULLTYPE = PULLUP; } -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/constraints_source/timing.sdc: -------------------------------------------------------------------------------- 1 | create_clock -name {sys_clk_25m} -period 40.000 -waveform {0.000 20.000} [get_ports {I_sys_clk}] 2 | create_clock -name {hdmi_rx_ck_lane_p} -period 13.468 -waveform {0.000 6.734} [get_ports {I_hdmi_rx_clk_p}] 3 | 4 | derive_pll_clocks 5 | set_clock_groups -asynchronous -group [get_clocks {sys_clk_25m}] -group [get_clocks {u_pll/pll_inst.clkc[0]}] -group [get_clocks {u_pll/pll_inst.clkc[1]}] -group [get_clocks {hdmi_rx_ck_lane_p}] -group [get_clocks {u_hdmi_pll/pll_inst.clkc[3]}] -group [get_clocks {u_hdmi_pll/pll_inst.clkc[2]}] 6 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/down_samping/down_samping_2x2.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:33:13 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:33:33 6 | */ 7 | 8 | 9 | module down_samping_2x2#( 10 | parameter [13:0] H_SIZE = 1920, 11 | parameter [13:0] V_SIZE = 1080 12 | ) 13 | ( 14 | input wire I_clk, 15 | input wire I_rst_n, 16 | 17 | input wire I_rgb_vs, 18 | input wire I_rgb_de, 19 | input wire [31:0] I_rgb_data, 20 | 21 | output reg O_rgb_vs, 22 | output reg O_rgb_de, 23 | output reg [31:0] O_rgb_data 24 | 25 | ); 26 | 27 | reg [11:0] col_count, row_count; 28 | 29 | 30 | wire vs_up_edge; 31 | 32 | assign vs_up_edge = I_rgb_vs &(~O_rgb_vs) ; 33 | 34 | always @(posedge I_clk or negedge I_rst_n) begin 35 | if (!I_rst_n) begin 36 | col_count <= 0; 37 | end else if (vs_up_edge) begin 38 | col_count <= 0; 39 | end else if (I_rgb_de) begin 40 | if (col_count == (H_SIZE- 1)) begin 41 | col_count <= 0; 42 | end else begin 43 | col_count <= col_count + 1; 44 | end 45 | end else begin 46 | col_count<=col_count; 47 | end 48 | end 49 | 50 | always @(posedge I_clk or negedge I_rst_n) begin 51 | if (!I_rst_n) begin 52 | row_count <= 0; 53 | end else if (vs_up_edge) begin 54 | row_count <= 0; 55 | end else if (I_rgb_de) begin 56 | if (row_count == (V_SIZE - 1) && col_count == (H_SIZE - 1)) begin 57 | row_count <= 0; 58 | end else if (col_count == (H_SIZE- 1)) begin 59 | row_count <= row_count + 1; 60 | end 61 | end else begin 62 | row_count<=row_count; 63 | end 64 | end 65 | 66 | 67 | reg sample_select; 68 | // wire sample_select; 69 | 70 | // assign sample_select = (col_count % 2 == 0) && (row_count % 2 == 0); 71 | 72 | always @(*) begin 73 | if(!I_rst_n) begin 74 | sample_select<=1'b0; 75 | end else begin 76 | sample_select <= (col_count % 2 == 0) && (row_count % 2 == 0); 77 | end 78 | end 79 | 80 | always @(posedge I_clk or negedge I_rst_n) begin 81 | if (!I_rst_n) begin 82 | O_rgb_vs <= 0; 83 | end else begin 84 | O_rgb_vs<=I_rgb_vs; 85 | end 86 | end 87 | 88 | always @(posedge I_clk or negedge I_rst_n) begin 89 | if (!I_rst_n) begin 90 | O_rgb_de <= 0; 91 | end else if(I_rgb_de) begin 92 | O_rgb_de<=sample_select; 93 | end else begin 94 | O_rgb_de<=0; 95 | end 96 | end 97 | 98 | always @(posedge I_clk or negedge I_rst_n) begin 99 | if (!I_rst_n) begin 100 | O_rgb_data <= 'd0; 101 | end else if(sample_select) begin 102 | O_rgb_data<=I_rgb_data; 103 | end 104 | end 105 | 106 | 107 | 108 | 109 | 110 | endmodule //video_samping 111 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/hdmi_in/edid_1280720.mif: -------------------------------------------------------------------------------- 1 | 2 | WIDTH=8; 3 | DEPTH=256; 4 | 5 | ADDRESS_RADIX=DEC; 6 | DATA_RADIX=HEX; 7 | 8 | CONTENT BEGIN 9 | 10 | 0 : 00 ; 11 | 1 : FF ; 12 | 2 : FF ; 13 | 3 : FF ; 14 | 4 : FF ; 15 | 5 : FF ; 16 | 6 : FF ; 17 | 7 : 00 ; 18 | 8 : 36 ; 19 | 9 : 74 ; 20 | 10 : 30 ; 21 | 11 : 00 ; 22 | 12 : 01 ; 23 | 13 : 00 ; 24 | 14 : 00 ; 25 | 15 : 00 ; 26 | 16 : 18 ; 27 | 17 : 0F ; 28 | 18 : 01 ; 29 | 19 : 03 ; 30 | 20 : 80 ; 31 | 21 : 73 ; 32 | 22 : 41 ; 33 | 23 : 78 ; 34 | 24 : 0A ; 35 | 25 : CF ; 36 | 26 : 74 ; 37 | 27 : A3 ; 38 | 28 : 57 ; 39 | 29 : 4C ; 40 | 30 : B0 ; 41 | 31 : 23 ; 42 | 32 : 09 ; 43 | 33 : 48 ; 44 | 34 : 4C ; 45 | 35 : 00 ; 46 | 36 : 00 ; 47 | 37 : 00 ; 48 | 38 : 01 ; 49 | 39 : 01 ; 50 | 40 : 01 ; 51 | 41 : FF ; 52 | 42 : 01 ; 53 | 43 : FF ; 54 | 44 : FF ; 55 | 45 : 01 ; 56 | 46 : 01 ; 57 | 47 : 01 ; 58 | 48 : 01 ; 59 | 49 : 01 ; 60 | 50 : 01 ; 61 | 51 : 01 ; 62 | 52 : 01 ; 63 | 53 : 20 ; 64 | 54 : 01 ; 65 | 55 : 1D ; 66 | 56 : 00 ; 67 | 57 : 72 ; 68 | 58 : 51 ; 69 | 59 : D0 ; 70 | 60 : 1E ; 71 | 61 : 20 ; 72 | 62 : 6E ; 73 | 63 : 28 ; 74 | 64 : 55 ; 75 | 65 : 00 ; 76 | 66 : C4 ; 77 | 67 : 8E ; 78 | 68 : 21 ; 79 | 69 : 00 ; 80 | 70 : 00 ; 81 | 71 : 1E ; 82 | 72 : 01 ; 83 | 73 : 1D ; 84 | 74 : 80 ; 85 | 75 : 18 ; 86 | 76 : 71 ; 87 | 77 : 1C ; 88 | 78 : 16 ; 89 | 79 : 20 ; 90 | 80 : 58 ; 91 | 81 : 2C ; 92 | 82 : 25 ; 93 | 83 : 00 ; 94 | 84 : C4 ; 95 | 85 : 8E ; 96 | 86 : 21 ; 97 | 87 : 00 ; 98 | 88 : 00 ; 99 | 89 : 9E ; 100 | 90 : 00 ; 101 | 91 : 00 ; 102 | 92 : 00 ; 103 | 93 : FC ; 104 | 94 : 00 ; 105 | 95 : 4D ; 106 | 96 : 53 ; 107 | 97 : 74 ; 108 | 98 : 61 ; 109 | 99 : 72 ; 110 | 100 : 20 ; 111 | 101 : 44 ; 112 | 102 : 65 ; 113 | 103 : 6D ; 114 | 104 : 6F ; 115 | 105 : 0A ; 116 | 106 : 20 ; 117 | 107 : 20 ; 118 | 108 : 00 ; 119 | 109 : 00 ; 120 | 110 : 00 ; 121 | 111 : FC ; 122 | 112 : 00 ; 123 | 113 : 3B ; 124 | 114 : 3C ; 125 | 115 : 1F ; 126 | 116 : 2D ; 127 | 117 : 08 ; 128 | 118 : 00 ; 129 | 119 : 0A ; 130 | 120 : 20 ; 131 | 121 : 20 ; 132 | 122 : 20 ; 133 | 123 : 20 ; 134 | 124 : 20 ; 135 | 125 : 20 ; 136 | 126 : 00 ; 137 | 127 : 27 ; 138 | 128 : 00 ; 139 | 129 : 00 ; 140 | 130 : 00 ; 141 | 131 : 00 ; 142 | 132 : 00 ; 143 | 133 : 00 ; 144 | 134 : 00 ; 145 | 135 : 00 ; 146 | 136 : 00 ; 147 | 137 : 00 ; 148 | 138 : 00 ; 149 | 139 : 00 ; 150 | 140 : 00 ; 151 | 141 : 00 ; 152 | 142 : 00 ; 153 | 143 : 00 ; 154 | 144 : 00 ; 155 | 145 : 00 ; 156 | 146 : 00 ; 157 | 147 : 00 ; 158 | 148 : 00 ; 159 | 149 : 00 ; 160 | 150 : 00 ; 161 | 151 : 00 ; 162 | 152 : 00 ; 163 | 153 : 00 ; 164 | 154 : 00 ; 165 | 155 : 00 ; 166 | 156 : 00 ; 167 | 157 : 00 ; 168 | 158 : 00 ; 169 | 159 : 00 ; 170 | 160 : 00 ; 171 | 161 : 00 ; 172 | 162 : 00 ; 173 | 163 : 00 ; 174 | 164 : 00 ; 175 | 165 : 00 ; 176 | 166 : 00 ; 177 | 167 : 00 ; 178 | 168 : 00 ; 179 | 169 : 00 ; 180 | 170 : 00 ; 181 | 171 : 00 ; 182 | 172 : 00 ; 183 | 173 : 00 ; 184 | 174 : 00 ; 185 | 175 : 00 ; 186 | 176 : 00 ; 187 | 177 : 00 ; 188 | 178 : 00 ; 189 | 179 : 00 ; 190 | 180 : 00 ; 191 | 181 : 00 ; 192 | 182 : 00 ; 193 | 183 : 00 ; 194 | 184 : 00 ; 195 | 185 : 00 ; 196 | 186 : 00 ; 197 | 187 : 00 ; 198 | 188 : 00 ; 199 | 189 : 00 ; 200 | 190 : 00 ; 201 | 191 : 00 ; 202 | 192 : 00 ; 203 | 193 : 00 ; 204 | 194 : 00 ; 205 | 195 : 00 ; 206 | 196 : 00 ; 207 | 197 : 00 ; 208 | 198 : 00 ; 209 | 199 : 00 ; 210 | 200 : 00 ; 211 | 201 : 00 ; 212 | 202 : 00 ; 213 | 203 : 00 ; 214 | 204 : 00 ; 215 | 205 : 00 ; 216 | 206 : 00 ; 217 | 207 : 00 ; 218 | 208 : 00 ; 219 | 209 : 00 ; 220 | 210 : 00 ; 221 | 211 : 00 ; 222 | 212 : 00 ; 223 | 213 : 00 ; 224 | 214 : 00 ; 225 | 215 : 00 ; 226 | 216 : 00 ; 227 | 217 : 00 ; 228 | 218 : 00 ; 229 | 219 : 00 ; 230 | 220 : 00 ; 231 | 221 : 00 ; 232 | 222 : 00 ; 233 | 223 : 00 ; 234 | 224 : 00 ; 235 | 225 : 00 ; 236 | 226 : 00 ; 237 | 227 : 00 ; 238 | 228 : 00 ; 239 | 229 : 00 ; 240 | 230 : 00 ; 241 | 231 : 00 ; 242 | 232 : 00 ; 243 | 232 : 00 ; 244 | 233 : 00 ; 245 | 234 : 00 ; 246 | 235 : 00 ; 247 | 236 : 00 ; 248 | 237 : 00 ; 249 | 238 : 00 ; 250 | 239 : 00 ; 251 | 240 : 00 ; 252 | 241 : 00 ; 253 | 242 : 00 ; 254 | 243 : 00 ; 255 | 244 : 00 ; 256 | 245 : 00 ; 257 | 246 : 00 ; 258 | 247 : 00 ; 259 | 248 : 00 ; 260 | 249 : 00 ; 261 | 250 : 00 ; 262 | 251 : 00 ; 263 | 252 : 00 ; 264 | 253 : 00 ; 265 | 254 : 00 ; 266 | 255 : 00 ; 267 | 268 | END; -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/hdmi_in/hdmi_rx_phy_wrapper.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module hdmi_rx_phy_wrapper#( 4 | parameter DEVICE = "PH1A" //"EF2","EF3","EF4","SF1","EG","PH1A","PH1P","DR1" 5 | )( 6 | input wire I_parallel_clk, 7 | input wire I_parallel_2p5x_clk, 8 | input wire I_parallel_5x_clk, 9 | input wire I_rst, 10 | 11 | input wire I_hdmi_rx_ch0_p, 12 | input wire I_hdmi_rx_ch1_p, 13 | input wire I_hdmi_rx_ch2_p, 14 | 15 | output wire[9:0] O_ch0_raw_data, 16 | output wire[9:0] O_ch1_raw_data, 17 | output wire[9:0] O_ch2_raw_data 18 | ); 19 | 20 | lane_lvds_1_10 #( 21 | .DEVICE ( DEVICE ) 22 | )u0_lane_lvds_1_10( 23 | .I_parallel_clk ( I_parallel_clk ), 24 | .I_parallel_2p5x_clk ( I_parallel_2p5x_clk ), 25 | .I_parallel_5x_clk ( I_parallel_5x_clk ), 26 | 27 | .I_rst ( I_rst ), 28 | 29 | .I_lvds_serial_in ( I_hdmi_rx_ch0_p ), 30 | 31 | .O_data ( O_ch0_raw_data ) 32 | ); 33 | 34 | 35 | lane_lvds_1_10 #( 36 | .DEVICE ( DEVICE ) 37 | )u1_lane_lvds_1_10( 38 | .I_parallel_clk ( I_parallel_clk ), 39 | .I_parallel_2p5x_clk ( I_parallel_2p5x_clk ), 40 | .I_parallel_5x_clk ( I_parallel_5x_clk ), 41 | 42 | .I_rst ( I_rst ), 43 | 44 | .I_lvds_serial_in ( I_hdmi_rx_ch1_p ), 45 | 46 | .O_data ( O_ch1_raw_data ) 47 | ); 48 | 49 | lane_lvds_1_10 #( 50 | .DEVICE ( DEVICE ) 51 | )u2_lane_lvds_1_10( 52 | .I_parallel_clk ( I_parallel_clk ), 53 | .I_parallel_2p5x_clk ( I_parallel_2p5x_clk ), 54 | .I_parallel_5x_clk ( I_parallel_5x_clk ), 55 | 56 | .I_rst ( I_rst ), 57 | 58 | .I_lvds_serial_in ( I_hdmi_rx_ch2_p ), 59 | 60 | .O_data ( O_ch2_raw_data ) 61 | ); 62 | endmodule -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/ph1a_hdmi_tx_lvds/hdmi_tx.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdma/uiFDMA.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdma/uiFDMA.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdma/uifdma_axi_ddr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdma/uifdma_axi_ddr.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/fs_cap.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop: https://milianke.taobao.com 9 | *Create Date: 2022/09/25 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 3.1 20 | *Signal description 21 | *1) _i input 22 | *2) _o output 23 | *3) _n activ low 24 | *4) _dg debug signal 25 | *5) _r delay or register 26 | *6) _s state mechine 27 | *********************************************************************/ 28 | 29 | 30 | module fs_cap#( 31 | parameter integer VIDEO_ENABLE = 1 32 | ) 33 | ( 34 | input I_clk, 35 | input I_rstn, 36 | input I_vs, 37 | output reg O_fs_cap 38 | ); 39 | 40 | //----CH0_CNT_FS�źŵ�ƽ���� ʵ�ʾ��Dz���VS�ź�---------------- 41 | reg[4:0]CNT_FS = 6'b0; 42 | reg[4:0]CNT_FS_n = 6'b0; 43 | reg FS = 1'b0; 44 | (* ASYNC_REG = "TRUE" *) reg vs_i_r1; 45 | (* ASYNC_REG = "TRUE" *) reg vs_i_r2; 46 | (* ASYNC_REG = "TRUE" *) reg vs_i_r3; 47 | (* ASYNC_REG = "TRUE" *) reg vs_i_r4; 48 | //----ͬ�����ε�·��֮ǰ����û�����ε�·�������Dzɼ�vs����----- 49 | always@(posedge I_clk) begin 50 | vs_i_r1 <= I_vs; 51 | vs_i_r2 <= vs_i_r1; 52 | vs_i_r3 <= vs_i_r2; 53 | vs_i_r4 <= vs_i_r3; 54 | end 55 | 56 | always@(posedge I_clk) begin 57 | if(!I_rstn)begin 58 | O_fs_cap <= 1'd0; 59 | end 60 | else if(VIDEO_ENABLE == 1)begin 61 | if({vs_i_r4,vs_i_r3} == 2'b01)begin 62 | O_fs_cap <= 1'b1; 63 | end 64 | else begin 65 | O_fs_cap <= 1'b0; 66 | end 67 | end 68 | else begin 69 | O_fs_cap <= vs_i_r4; 70 | end 71 | end 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/ram_rd_buf/ram_rd_buf.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | SYNC 5 | SET 6 | ASYNC 7 | SYNC 8 | SET 9 | ASYNC 10 | ASYNC 11 | DISABLE 12 | DISABLE 13 | DISABLE 14 | DISABLE 15 | DISABLE 16 | 17 | 18 | NONE 19 | 20 | 21 | PH1A90SBG484 22 | PH1_LOGIC_ERAM 23 | true 24 | ram_rd_buf 25 | 26 | 27 | none 28 | NO 29 | NO 30 | 31 | 32 | 20K 33 | 34 | 35 | PDPW 36 | 37 | 38 | 1024 39 | disable 40 | enable 41 | NORMAL 42 | None 43 | 16 44 | 45 | 46 | 1024 47 | disable 48 | NORMAL 49 | None 50 | 16 51 | 52 | 53 | ram_rd_buf.vhd 54 | ram_rd_buf.v 55 | 56 | 57 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/ram_rd_buf/ram_rd_buf.v: -------------------------------------------------------------------------------- 1 | /************************************************************\ 2 | ** Copyright (c) 2012-2024 Anlogic Inc. 3 | ** All Right Reserved.\ 4 | \************************************************************/ 5 | /************************************************************\ 6 | ** Log : This file is generated by Anlogic IP Generator. 7 | ** File : C:/HIT/personal_learn/open_source/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/ram_rd_buf/ram_rd_buf.v 8 | ** Date : 2025 01 15 9 | ** TD version : 6.0.117864 10 | \************************************************************/ 11 | 12 | `timescale 1ns / 1ps 13 | 14 | module ram_rd_buf ( 15 | dia, addra, clka, wea, 16 | dob, addrb, clkb 17 | ); 18 | 19 | 20 | parameter DATA_WIDTH_A = 16; 21 | parameter ADDR_WIDTH_A = 10; 22 | parameter DATA_DEPTH_A = 1024; 23 | parameter DATA_WIDTH_B = 16; 24 | parameter ADDR_WIDTH_B = 10; 25 | parameter DATA_DEPTH_B = 1024; 26 | parameter REGMODE_A = "NOREG"; 27 | parameter REGMODE_B = "NOREG"; 28 | parameter WRITEMODE_A = "NORMAL"; 29 | parameter WRITEMODE_B = "NORMAL"; 30 | parameter RESETMODE_A = "ASYNC"; 31 | parameter RESETMODE_B = "ASYNC"; 32 | 33 | output [DATA_WIDTH_B-1:0] dob; 34 | 35 | 36 | input [DATA_WIDTH_A-1:0] dia; 37 | input [ADDR_WIDTH_A-1:0] addra; 38 | input [ADDR_WIDTH_B-1:0] addrb; 39 | input wea; 40 | input clka; 41 | input clkb; 42 | 43 | 44 | 45 | PH1_LOGIC_ERAM #( .DATA_WIDTH_A(DATA_WIDTH_A), 46 | .DATA_WIDTH_B(DATA_WIDTH_B), 47 | .ADDR_WIDTH_A(ADDR_WIDTH_A), 48 | .ADDR_WIDTH_B(ADDR_WIDTH_B), 49 | .DATA_DEPTH_A(DATA_DEPTH_A), 50 | .DATA_DEPTH_B(DATA_DEPTH_B), 51 | .MODE("PDPW"), 52 | .REGMODE_A(REGMODE_A), 53 | .REGMODE_B(REGMODE_B), 54 | .WRITEMODE_A(WRITEMODE_A), 55 | .WRITEMODE_B(WRITEMODE_B), 56 | .IMPLEMENT("20K"), 57 | .ECC_ENCODE("DISABLE"), 58 | .ECC_DECODE("DISABLE"), 59 | .CLKMODE("ASYNC"), 60 | .SSROVERCE("DISABLE"), 61 | .OREGSET_A("SET"), 62 | .OREGSET_B("SET"), 63 | .RESETMODE_A(RESETMODE_A), 64 | .RESETMODE_B(RESETMODE_B), 65 | .ASYNC_RESET_RELEASE_A("SYNC"), 66 | .ASYNC_RESET_RELEASE_B("SYNC"), 67 | .INIT_FILE("NONE"), 68 | .FILL_ALL("NONE")) 69 | inst( 70 | .dia(dia), 71 | .dib({16{1'b0}}), 72 | .addra(addra), 73 | .addrb(addrb), 74 | .cea(1'b1), 75 | .ceb(1'b1), 76 | .ocea(1'b0), 77 | .oceb(1'b0), 78 | .clka(clka), 79 | .clkb(clkb), 80 | .wea(wea), 81 | .web(1'b0), 82 | .bea(1'b0), 83 | .beb(1'b0), 84 | .rsta(1'b0), 85 | .rstb(1'b0), 86 | .ecc_sbiterr(), 87 | .ecc_dbiterr(), 88 | .ecc_sbiterrinj('d0), 89 | .ecc_dbiterrinj('d0), 90 | .doa(), 91 | .dob(dob)); 92 | 93 | 94 | endmodule -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/ram_rd_buf/ram_rd_buf.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------- 2 | -- Copyright (c) 2012-2024 Anlogic Inc. -- All Right Reserved. 3 | -------------------------------------------------------------- 4 | -- Log : This file is generated by Anlogic IP Generator. 5 | -- File : C:/HIT/personal_learn/open_source/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/ram_rd_buf/ram_rd_buf.vhd 6 | -- Date : 2025 01 15 7 | -- TD version : 6.0.117864 8 | -------------------------------------------------------------- 9 | 10 | LIBRARY ieee; 11 | USE work.ALL; 12 | USE ieee.std_logic_1164.all; 13 | LIBRARY ph1_macro; 14 | USE ph1_macro.PH1_COMPONENTS.all; 15 | 16 | ENTITY ram_rd_buf IS 17 | PORT ( 18 | dob : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); 19 | 20 | dia : IN STD_LOGIC_VECTOR(15 DOWNTO 0); 21 | addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 22 | wea : IN STD_LOGIC; 23 | clka : IN STD_LOGIC; 24 | addrb : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 25 | clkb : IN STD_LOGIC 26 | ); 27 | END ram_rd_buf; 28 | 29 | ARCHITECTURE struct OF ram_rd_buf IS 30 | 31 | BEGIN 32 | inst : PH1_LOGIC_ERAM 33 | GENERIC MAP ( 34 | DATA_WIDTH_A => 16, 35 | DATA_WIDTH_B => 16, 36 | ADDR_WIDTH_A => 10, 37 | ADDR_WIDTH_B => 10, 38 | DATA_DEPTH_A => 1024, 39 | DATA_DEPTH_B => 1024, 40 | MODE => "PDPW", 41 | REGMODE_A => "NOREG", 42 | REGMODE_B => "NOREG", 43 | WRITEMODE_A => "NORMAL", 44 | WRITEMODE_B => "NORMAL", 45 | IMPLEMENT => "20K", 46 | CLKMODE => "ASYNC", 47 | ECC_ENCODE => "DISABLE", 48 | ECC_DECODE => "DISABLE", 49 | SSROVERCE => "DISABLE", 50 | OREGSET_A => "SET", 51 | OREGSET_B => "SET", 52 | RESETMODE_A => "ASYNC", 53 | RESETMODE_B => "ASYNC", 54 | ASYNC_RESET_RELEASE_A => "SYNC", 55 | ASYNC_RESET_RELEASE_B => "SYNC", 56 | INIT_FILE => "NONE", 57 | FILL_ALL => "NONE" 58 | ) 59 | PORT MAP ( 60 | dia => dia, 61 | dib => (others=>'0'), 62 | addra => addra, 63 | addrb => addrb, 64 | cea => '1', 65 | ceb => '1', 66 | clka => clka, 67 | clkb => clkb, 68 | wea => wea, 69 | web => '0', 70 | bea => (others=>'0'), 71 | beb => (others=>'0'), 72 | ocea => '0', 73 | oceb => '0', 74 | rsta => '0', 75 | rstb => '0', 76 | ecc_sbiterr => OPEN, 77 | ecc_dbiterr => OPEN, 78 | ecc_sbiterrinj => OPEN, 79 | ecc_dbiterrinj => OPEN, 80 | doa => OPEN, 81 | dob => dob 82 | ); 83 | 84 | END struct; 85 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 253 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 2048 11 | 32 12 | Enable 13 | 256 14 | 256 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | rfifo 22 | 23 | 24 | rfifo.v 25 | rfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/rfifo/rfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/uidbuf.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/uidbuf.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/uidbuf_only_r_rotate_180.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/uidbuf_only_r_rotate_180.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.ipc: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2 5 | 2045 6 | ASYNC 7 | EMB20K(Area Opt) 8 | Disable 9 | ERAM 10 | 256 11 | 256 12 | Enable 13 | 2048 14 | 32 15 | 16 | 17 | PH1A90SBG484 18 | PH1_Soft_FIFO 19 | 1.1 20 | false 21 | wfifo 22 | 23 | 24 | wfifo.v 25 | wfifo.tcl 26 | 27 | 28 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uifdmadbuf/wfifo/wfifo.tcl: -------------------------------------------------------------------------------- 1 | set clkw [get_clocks -nowarn -of [get_ports {clkw}]] 2 | set clkr [get_clocks -nowarn -of [get_ports {clkr}]] 3 | 4 | set wr_clk_period [get_property -nowarn -max PERIOD $clkw] 5 | set rd_clk_period [get_property -nowarn -max PERIOD $clkr] 6 | 7 | set dly_sly_slack 0.3 8 | 9 | if { $clkw =="" } { 10 | set wr_clk_period 1000 11 | } 12 | 13 | if { $clkr =="" } { 14 | set rd_clk_period 1001 15 | } 16 | 17 | set_max_delay -from [get_regs {rd_to_wr_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {rd_to_wr_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only 18 | set_max_delay -from [get_regs {wr_to_rd_cross_inst/primary_addr_gray_reg[*]}] -to [get_regs {wr_to_rd_cross_inst/sync_r1[*]}] [expr min($wr_clk_period,$rd_clk_period) - $dly_sly_slack] -datapath_only -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/uisetvbuf/uisetvbuf.v: -------------------------------------------------------------------------------- 1 | 2 | /*******************************MILIANKE******************************* 3 | *Company : MiLianKe Electronic Technology Co., Ltd. 4 | *WebSite:https://www.milianke.com 5 | *TechWeb:https://www.uisrc.com 6 | *tmall-shop:https://milianke.tmall.com 7 | *jd-shop:https://milianke.jd.com 8 | *taobao-shop1: https://milianke.taobao.com 9 | *Create Date: 2023/03/23 10 | *Module Name: 11 | *File Name: 12 | *Description: 13 | *The reference demo provided by Milianke is only used for learning. 14 | *We cannot ensure that the demo itself is free of bugs, so users 15 | *should be responsible for the technical problems and consequences 16 | *caused by the use of their own products. 17 | *Copyright: Copyright (c) MiLianKe 18 | *All rights reserved. 19 | *Revision: 1.1 20 | *Signal description 21 | *1) I_ input 22 | *2) O_ output 23 | *3) IO_ input output 24 | *3) S_ system internal signal 25 | *3) _n activ low 26 | *4) _dg debug signal 27 | *5) _r delay or register 28 | *6) _s state mechine 29 | *********************************************************************/ 30 | `timescale 1ns / 1ps 31 | 32 | module uisetvbuf#( 33 | parameter integer BUF_DELAY = 1, 34 | parameter integer BUF_LENTH = 3 35 | ) 36 | ( 37 | 38 | input [7 :0] I_bufn, 39 | output [7 :0] O_bufn 40 | ); 41 | 42 | 43 | 44 | assign O_bufn = I_bufn < BUF_DELAY? (BUF_LENTH - BUF_DELAY + I_bufn) : (I_bufn - BUF_DELAY) ; 45 | 46 | 47 | endmodule 48 | 49 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/vtc/uivtc_video_rotate_180.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BIT-stream-lab/Multifunctional-video-processing-platform/b01bcea79822adce747f9ced7f50d7e213b2ad94/03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/vtc/uivtc_video_rotate_180.v -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/width_conversion/rd_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:20 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:20 6 | */ 7 | 8 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 9 | module rd_width_convert( 10 | input wire [15:0] I_rd_data, 11 | 12 | output wire [31:0] O_rd_data 13 | ); 14 | 15 | 16 | assign O_rd_data ={8'd0,I_rd_data[15:11], 3'd0, I_rd_data[10:5], 2'd0,I_rd_data[4:0], 3'd0} ; 17 | 18 | 19 | 20 | endmodule 21 | 22 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/04_video_rotate_180/user_source/hdl_source/width_conversion/wr_width_convert.v: -------------------------------------------------------------------------------- 1 | /* 2 | * @Author: bit_stream 3 | * @Date: 2024-12-07 16:30:27 4 | * @Last Modified by: bit_stream 5 | * @Last Modified time: 2024-12-07 16:30:27 6 | */ 7 | 8 | 9 | //此模块的作用是把RGB88格式的数据转换为两个RGB565格式的数据 10 | module wr_width_convert( 11 | input wire [31:0] I_wr_data, 12 | 13 | output wire [15:0] O_wr_data 14 | ); 15 | 16 | assign O_wr_data = {I_wr_data[23:19],I_wr_data[15:10],I_wr_data[7:3]}; 17 | 18 | endmodule 19 | 20 | -------------------------------------------------------------------------------- /03_任意角度视频旋转/README.md: -------------------------------------------------------------------------------- 1 | 任意角度视频旋转分为三个部分：180度视频实时旋转，90/270度视频实时旋转，任意角度视频实时旋转。 2 | 3 | 180度视频实时旋转工程文件见04_video_rotate_180文件夹 4 | 5 | 6 | 7 | 移植注意事项 8 | 9 | 1、 在本工程中，为了减少ERAM资源的使用，我们将图像像素点在DDR3中的存储和读取格式设置为RGB565格式，其中每个像素点占用16bit，并将DDR3的数据位宽设置为16bit。由于DDR3的突发传输长度固定为8，每次突发传输8次16bit数据，即总共传输128bit。因此，在进行DDR3存取时，FIFO的读写位宽可以设置为16bit和128bit。与此不同，若将图像像素点的存储格式设置为RGB888格式，每个像素点将占用24bit，并将DDR3的数据位宽设置为32bit。在这种情况下，进行存取时，FIFO的读写位宽将为32bit和256bit，这样会导致ERAM资源消耗的加倍。 10 | 11 | 2、本工程把四路视频源拼接模块输入的视频分辨率为1280×720 12 | 13 | 14 | 关于180度视频实时旋转方案实现讲解，博客地址如下：[FPGA实现视频180度实时旋转](https://blog.csdn.net/weixin_53015183/article/details/145122071?spm=1001.2014.3001.5502) 15 | 16 | 关于90/270度视频旋转方案实现讲解，博客地址如下：[FPGA实现视频90/270度旋转](https://blog.csdn.net/weixin_53015183/article/details/145321324?spm=1001.2014.3001.5502) -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Multifunctional-video-processing-platform 2 | 该作品为2024年FPGA创新设计大赛（上海安路科技赛道）国一作品 （希望大家给点点右上角的 star 呀） 3 | ### （持续更新中...） 4 | 5 | 初赛演示视频：[2024年FPGA创新设计竞赛国一作品，该视频为安路科技赛道初赛视频]( https://www.bilibili.com/video/BV1K8zdYuEAu/?share_source=copy_web&vd_source=d38841530cd28bd68603ca38364bd8a1) 6 | 7 | 该作品由三张板卡级联组成，板卡一和板卡二之间使用HDMI级联，板卡一和板卡三之间使用SFP级联 8 | 板卡一实现了五路数据源的输入（双目摄像头、SD卡、HDMI IN、以太网），3路视频源的输出（HDMI OUT0、HDMI OUT1,SFP） 9 | 板卡二实现了1路视频源的输入（HDMI IN），2路视频源的输出（HDMI OUT、以太网 ） 10 | 板卡三实现了3路视频源的输入（SFP、HDMI IN、MIPI摄像头），1路视频源的输出（HDMI OUT） 11 | 12 | 整个系统实现了任意角度视频旋转（三种实现方案）、任意比例视频缩放、任意分辨率JPG图片解码等24种图像处理算法，以及SD卡SDIO模式读取等模块。 13 | 14 | 由于整个系统的功能较多、数据通路较为复杂，我会把每一个比较重要的功能都独立的对应一个工程文件，并且会在博客中给出每个重要的功能的设计思路。 15 | 博客地址：[2024年FPGA大赛（上海安路科技赛道）国一作品分享](https://blog.csdn.net/weixin_53015183/category_12849637.html?spm=1001.2014.3001.5482) 16 | 17 | 更新顺序如下： 18 | 1、四分屏+分屏时视频移动方案实现 （已更新） 19 | 2、分屏/全屏切换实现 （已更新） 20 | 3、视频任意角度旋转方案实现 （已更新180度旋转、90/270旋转） 21 | 22 | 4、视频任意比例缩放方案实现 23 | 5、任意分辨率JPG图片解码实现 24 | 6、以太网传输字符显示实现 25 | 7、SD卡SDIO模式读取实现 26 | .........(未完待续) 27 | 28 | 29 | 30 | 31 | 32 | 33 | --------------------------------------------------------------------------------