├── DbgCfg_Debugger.jpg ├── DbgCfg_Main.jpg ├── DbgCfg_Startup.jpg ├── GDB_RSP └── GDB_RSP_Debug.vhd ├── Interconnect.vhd ├── LICENSE ├── Memory └── Memory.vhd ├── Peripherals ├── GPIO.vhd └── Timer.vhd ├── README.md ├── ScaleClock.vhd ├── Synth_Basys3 ├── Synth_Basys3.xpr └── VexRiscvWB_TOP.bit ├── System.jpg ├── Test_Program ├── Boot.S ├── Linker.ld ├── Make_all.bat ├── Make_clean.bat ├── Makefile ├── Readelf.bat ├── gdb_riscv32_serial.bat └── riscv_csr_encoding.h ├── Test_WS ├── Eclipse.bat └── First │ ├── .cproject │ ├── .project │ ├── .settings │ ├── language.settings.xml │ └── org.eclipse.cdt.core.prefs │ ├── gdb_riscv32_serial.bat │ ├── postbuild.bat │ └── src │ ├── Boot.S │ ├── Linker.ld │ ├── interrupts.c │ ├── interrupts.h │ ├── main.c │ ├── premain.c │ └── riscv_csr_encoding.h ├── UART_Sender_nur_Simulation.vhd ├── VexRiscvWB_System.vhd ├── VexRiscvWB_TOP.vhd ├── VexRiscvWB_TOP.xdc ├── VexRiscvWB_TOP_TB.do ├── VexRiscvWB_TOP_TB.vhd ├── VexRiscvWB_small.scala ├── VexRiscvWB_small.vhd └── string_stream_pack.vhd /DbgCfg_Debugger.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/DbgCfg_Debugger.jpg -------------------------------------------------------------------------------- /DbgCfg_Main.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/DbgCfg_Main.jpg -------------------------------------------------------------------------------- /DbgCfg_Startup.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/DbgCfg_Startup.jpg -------------------------------------------------------------------------------- /Interconnect.vhd: -------------------------------------------------------------------------------- 1 | --------------------------------------------------------------------------------- 2 | -- based on https://github.com/olofk/serv/blob/main/serving/serving_arbiter.v 3 | -- B.Lang, HS-Osnabrueck 4 | --------------------------------------------------------------------------------- 5 | 6 | library IEEE; 7 | use IEEE.std_logic_1164.all; 8 | use IEEE.numeric_std.all; 9 | 10 | entity ibus_dbus_mux is 11 | port ( 12 | -- 13 | dBusWishbone_STB : in std_logic; 14 | dBusWishbone_ACK : out std_logic; 15 | dBusWishbone_WE : in std_logic; 16 | dBusWishbone_ADR : in unsigned(29 downto 0); 17 | dBusWishbone_DAT_MISO : out std_logic_vector(31 downto 0); 18 | dBusWishbone_DAT_MOSI : in std_logic_vector(31 downto 0); 19 | dBusWishbone_SEL : in std_logic_vector(3 downto 0); 20 | -- 21 | iBusWishbone_STB : in std_logic; 22 | iBusWishbone_ACK : out std_logic; 23 | iBusWishbone_ADR : in unsigned(29 downto 0); 24 | iBusWishbone_DAT_MISO : out std_logic_vector(31 downto 0); 25 | -- 26 | Wishbone_STB : out std_logic; 27 | Wishbone_ACK : in std_logic; 28 | Wishbone_WE : out std_logic; 29 | Wishbone_ADR : out unsigned(29 downto 0); 30 | Wishbone_DAT_MISO : in std_logic_vector(31 downto 0); 31 | Wishbone_DAT_MOSI : out std_logic_vector(31 downto 0); 32 | Wishbone_SEL : out std_logic_vector(3 downto 0) 33 | ); 34 | end ibus_dbus_mux; 35 | 36 | architecture arch of ibus_dbus_mux is 37 | begin 38 | -- 39 | dBusWishbone_DAT_MISO <= Wishbone_DAT_MISO; 40 | dBusWishbone_ACK <= '1' when Wishbone_ACK='1' and iBusWishbone_STB='0' else '0'; 41 | -- 42 | iBusWishbone_DAT_MISO <= Wishbone_DAT_MISO; 43 | iBusWishbone_ACK <= Wishbone_ACK and iBusWishbone_STB; 44 | -- 45 | Wishbone_ADR <= iBusWishbone_ADR when iBusWishbone_STB='1' else 46 | dBusWishbone_ADR when dBusWishbone_STB='1' else 47 | (others=>'-'); 48 | Wishbone_DAT_MOSI <= dBusWishbone_DAT_MOSI; 49 | Wishbone_SEL <= dBusWishbone_SEL; 50 | Wishbone_WE <= dBusWishbone_WE when iBusWishbone_STB='0' else '0'; 51 | Wishbone_STB <= iBusWishbone_STB or dBusWishbone_STB; 52 | -- 53 | end arch; 54 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. 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If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. 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Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /Memory/Memory.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- (c) Bernhard Lang, Hochschule Osnabrueck 3 | ---------------------------------------------------------------------------------------- 4 | library ieee; 5 | use ieee.std_logic_1164.all; 6 | entity Memory is 7 | generic ( 8 | ADR_I_WIDTH : natural := 14; 9 | BASE_ADDR : natural := 16#10000# 10 | ); 11 | port ( 12 | CLK_I : in std_logic; 13 | RST_I : in std_logic; 14 | STB_I : in std_logic; 15 | WE_I : in std_logic; 16 | SEL_I : in std_logic_vector(3 downto 0); 17 | ADR_I : in std_logic_vector(ADR_I_WIDTH - 1 downto 0); 18 | DAT_I : in std_logic_vector(31 downto 0); 19 | DAT_O : out std_logic_vector(31 downto 0); 20 | ACK_O : out std_logic 21 | ); 22 | end entity; 23 | 24 | library ieee; 25 | use ieee.numeric_std.all; 26 | 27 | architecture rtl of Memory is 28 | type mem_type is array (natural range<>) of std_logic_vector(31 downto 0); 29 | signal mem : mem_type(0 to 2**(ADR_I_WIDTH-2)- 1) := (others => x"00000013"); -- Memory filled with NOPs 30 | signal read_ack : std_logic; 31 | signal write_ack : std_logic; 32 | begin 33 | 34 | write_ack <= STB_I and WE_I; 35 | 36 | ACK_O <= read_ack or write_ack; 37 | 38 | process(CLK_I) 39 | begin 40 | if rising_edge(CLK_I) then 41 | if WE_I='1' and STB_I='1' then 42 | for i in 0 to 3 loop 43 | if SEL_I(i) = '1' then 44 | mem(to_integer(unsigned(ADR_I(ADR_I'length-1 downto 2))))(i*8+7 downto i*8) <= DAT_I(i*8+7 downto i*8); 45 | end if; 46 | end loop; 47 | end if; 48 | if RST_I = '1' then DAT_O <= x"00000000"; 49 | else DAT_O <= mem(to_integer(unsigned(ADR_I(ADR_I'length-1 downto 2)))); 50 | end if; 51 | end if; 52 | end process; 53 | 54 | gen_read_ack: process(CLK_I) 55 | begin 56 | if rising_edge(CLK_I) then 57 | if WE_I='0' and read_ack='0' and STB_I='1' and RST_I='0' then read_ack <= '1'; 58 | else read_ack <= '0'; 59 | end if; 60 | end if; 61 | end process; 62 | 63 | end architecture; 64 | -------------------------------------------------------------------------------- /Peripherals/GPIO.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Dateiname: GPIO.vhd 3 | -- 4 | -- GPIO Komponente 5 | -- 6 | -- Erstellt: 19.03.2014, Rainer Hoeckmann 7 | -- 8 | -- Aenderungen: 9 | -------------------------------------------------------------------------------- 10 | ---------------------------------------------------------------------------------------- 11 | -- (c) Bernhard Lang, Rainer Hoeckmann, Hochschule Osnabrueck 12 | ---------------------------------------------------------------------------------------- 13 | 14 | library ieee; 15 | use ieee.std_logic_1164.all; 16 | use ieee.numeric_std.all; 17 | 18 | entity GPIO is 19 | generic( 20 | NUM_PORTS: positive 21 | ); 22 | port( 23 | clk_i : in std_logic; 24 | rst_i : in std_logic; 25 | stb_i : in std_logic; 26 | we_i : in std_logic; 27 | adr_i : in std_logic_vector(7 downto 0); 28 | dat_i : in std_logic_vector(31 downto 0); 29 | ack_o : out std_logic; 30 | dat_o : out std_logic_vector(31 downto 0); 31 | pins : inout std_logic_vector(NUM_PORTS - 1 downto 0) 32 | ); 33 | end entity; 34 | 35 | architecture rtl of GPIO is 36 | -- direction register 37 | signal dir_r: std_logic_vector(NUM_PORTS - 1 downto 0) := (others=>'0'); 38 | -- data register 39 | signal data_r: std_logic_vector(NUM_PORTS - 1 downto 0) := (others=>'0'); 40 | -- synchronized input pins 41 | signal pins_sync: std_logic_vector(pins'range) := (others=>'0'); 42 | begin 43 | -- generate ack_o each time this component is accessed 44 | ack_o <= stb_i; 45 | 46 | -- dat_o multiplexer for read accesses 47 | rd_mux: process(adr_i, dir_r, data_r, pins_sync) 48 | begin 49 | dat_o <= (others=>'0'); 50 | case adr_i is 51 | when x"00" => dat_o(dir_r'range) <= dir_r; 52 | when x"10" => dat_o(data_r'range) <= data_r; 53 | when x"20" => dat_o(pins_sync'range) <= pins_sync; 54 | when others => null; 55 | end case; 56 | end process; 57 | 58 | -- instantiate needed number of iobufs 59 | generate_iobuf: for i in 0 to NUM_PORTS - 1 generate 60 | pins(i) <= 61 | data_r(i) when dir_r(i) = '1' else 62 | 'Z' when dir_r(i) = '0' else 63 | '-'; 64 | end generate; 65 | 66 | 67 | reg_proc: process 68 | begin 69 | wait until rising_edge(clk_i); 70 | -- synchronize pin inputs 71 | pins_sync <= pins; 72 | -- dir- and data-registers 73 | if rst_i='1' then 74 | dir_r <= (others=>'0'); 75 | data_r <= (others=>'0'); 76 | else 77 | -- register write accesses 78 | if stb_i = '1' and we_i = '1' then 79 | case adr_i is 80 | when x"00" => dir_r <= dat_i(dir_r'range); -- DIR 81 | when x"04" => dir_r <= dir_r or dat_i(dir_r'range); -- DIR_SET 82 | when x"08" => dir_r <= dir_r and (not dat_i(dir_r'range)); -- DIR_DELETE 83 | when x"0C" => dir_r <= dir_r xor dat_i(dir_r'range); -- DIR_TOGGLE 84 | when x"10" => data_r <= dat_i(data_r'range); -- DATA 85 | when x"14" => data_r <= data_r or dat_i(data_r'range); -- DATA_SET 86 | when x"18" => data_r <= data_r and (not dat_i(data_r'range)); -- DATA_DELETE 87 | when x"1C" => data_r <= data_r xor dat_i(data_r'range); -- DATA_TOGGLE 88 | when others => null; 89 | end case; 90 | end if; 91 | end if; 92 | end process; 93 | end architecture; 94 | -------------------------------------------------------------------------------- /Peripherals/Timer.vhd: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- 2 | -- Dateiname: Timer.vhd 3 | -- 4 | -- Timer Komponente 5 | -- 6 | -- Erstellt: 12.05.2014, Rainer Hoeckmann 7 | -- 8 | -- Aenderungen: 9 | -- 2020-04-29 cyc_i entfernt, zu std_logic geaendert 10 | -- 2020-05-28 Aufteilung in Prozesse geaendert 11 | -------------------------------------------------------------------------------- 12 | -- Registers: 13 | -- 0x0: Timer_Value (RW) 14 | -- 0x4: Timer_Start (RW) 15 | -- 0x8: Timer_Status (R) 16 | -- [31:1]: unused 17 | -- [0]: Timer_IRQ (Reset on Read) 18 | -------------------------------------------------------------------------------- 19 | ---------------------------------------------------------------------------------------- 20 | -- (c) Bernhard Lang, Rainer Hoeckmann, Hochschule Osnabrueck 21 | ---------------------------------------------------------------------------------------- 22 | 23 | library ieee; 24 | use ieee.std_logic_1164.all; 25 | use ieee.numeric_std.all; 26 | 27 | entity Timer is 28 | port( 29 | CLK_I : in std_logic; 30 | RST_I : in std_logic; 31 | STB_I : in std_logic; 32 | WE_I : in std_logic; 33 | ADR_I : in std_logic_vector(3 downto 0); 34 | DAT_I : in std_logic_vector(31 downto 0); 35 | ACK_O : out std_logic; 36 | DAT_O : out std_logic_vector(31 downto 0); 37 | Timer_IRQ : out std_logic 38 | ); 39 | end entity; 40 | 41 | architecture rtl of Timer is 42 | 43 | -- Typ fuer den Lesedatenmultiplexer 44 | type RD_Mux_Type is (RD_SEL_Nichts, RD_SEL_Start, RD_SEL_Value, RD_SEL_Status); 45 | 46 | -- Interne Version des Ausgangssignals 47 | signal Timer_IRQ_i : std_logic := '0'; 48 | 49 | -- Register 50 | signal Timer_Value : unsigned(31 downto 0) := (others=>'0'); 51 | signal Timer_Start : unsigned(31 downto 0) := (others=>'0'); 52 | signal Timer_Status : std_logic_vector(31 downto 0) := (others=>'0'); 53 | signal TC : std_logic := '1'; 54 | 55 | -- Kombinatorische Signale 56 | signal RD_Sel : RD_Mux_Type; 57 | signal Lese_Status : std_logic; 58 | signal Schreibe_Start : std_logic; 59 | signal Schreibe_Value : std_logic; 60 | 61 | begin 62 | -- Interne Version des Ausgangsignals nach aussen fuehren 63 | Timer_IRQ <= Timer_IRQ_i; 64 | 65 | -- Timer_Status mit Statussignal verbinden 66 | Timer_Status(0) <= Timer_IRQ_i; 67 | 68 | -- Kombinatorischer Prozess zur Dekodierung der Bussignale 69 | Decoding: process(STB_I, WE_I, ADR_I) is 70 | begin 71 | 72 | -- Default-Zuweisungen 73 | ACK_O <= '0'; 74 | Lese_Status <= '0'; 75 | Schreibe_Start <= '0'; 76 | Schreibe_Value <= '0'; 77 | RD_Sel <= RD_SEL_Nichts; 78 | 79 | -- TODO: Dekodierung der Bussignale beschreiben 80 | -- BEGIN SOLUTION 81 | if STB_I = '1' then 82 | 83 | ACK_O <= '1'; 84 | 85 | case ADR_I is 86 | when x"0" => 87 | if WE_I = '0' then 88 | RD_Sel <= RD_SEL_Value; 89 | elsif WE_I = '1' then 90 | Schreibe_Value <= '1'; 91 | end if; 92 | 93 | when x"4" => 94 | if WE_I = '0' then 95 | RD_Sel <= RD_SEL_Start; 96 | elsif WE_I = '1' then 97 | Schreibe_Start <= '1'; 98 | end if; 99 | 100 | when x"8" => 101 | if WE_I = '0' then 102 | RD_Sel <= RD_SEL_Status; 103 | Lese_Status <= '1'; 104 | end if; 105 | 106 | when others => 107 | null; 108 | end case; 109 | end if; 110 | -- END SOLUTION 111 | end process; 112 | 113 | -- Kombinatorischer Prozess fuer den Lesedatenmultiplexer 114 | Mux_Lesedaten: process(RD_Sel, Timer_Start, Timer_Value, Timer_Status) is 115 | begin 116 | -- TODO: Zuweisung an DAT_O beschreiben 117 | -- BEGIN SOLUTION 118 | case RD_Sel is 119 | when RD_SEL_Start => DAT_O <= std_logic_vector(Timer_Start); 120 | when RD_SEL_Value => DAT_O <= std_logic_vector(Timer_Value); 121 | when RD_SEL_Status => DAT_O <= Timer_Status; 122 | when RD_SEL_Nichts => DAT_O <= (others=>'0'); 123 | end case; 124 | -- END SOLUTION 125 | end process; 126 | 127 | -- Synchroner Prozess fuer das Register Timer_Start 128 | Reg_Timer_Start: process(CLK_I) is 129 | begin 130 | if rising_edge(CLK_I) then 131 | -- TODO: Zuweisung an Timer_Start beschreiben 132 | -- BEGIN SOLUTION 133 | if RST_I = '1' then 134 | Timer_Start <= (others=>'0'); 135 | else 136 | if Schreibe_Start = '1' then 137 | Timer_Start <= unsigned(DAT_I); 138 | end if; 139 | end if; 140 | -- END SOLUTION 141 | end if; 142 | end process; 143 | 144 | -- Synchroner Prozess fuer das Register Timer_Value, 145 | -- (umfasst auch den Multiplexer fuer die Schreibdaten sowie das Oder-Gatter) 146 | Reg_Timer_Value: process(CLK_I) is 147 | variable Timer_Value_var : unsigned(Timer_Value'range); 148 | begin 149 | if rising_edge(CLK_I) then 150 | 151 | -- alten Zahlerstand vom Signal lesen 152 | Timer_Value_var := Timer_Value; 153 | 154 | -- Default-Zuweisung 155 | TC <= '0'; 156 | 157 | -- TODO: Verhalten des Zaehlers beschreiben 158 | -- BEGIN SOLUTION 159 | if RST_I = '1' then 160 | Timer_Value_var := (others=>'0'); 161 | else 162 | if Schreibe_Value = '1' then 163 | Timer_Value_var := unsigned(DAT_I); 164 | elsif Schreibe_Value = '0' and TC = '1' then 165 | Timer_Value_var := Timer_Start; 166 | elsif Schreibe_Value = '0' and TC = '0' then 167 | Timer_Value_var := Timer_Value_var - 1; 168 | end if; 169 | end if; 170 | 171 | if Timer_Value_var = 0 then TC <= '1'; end if; 172 | -- END SOLUTION 173 | 174 | -- neuen Zahlerstand dem Signal zuweisen 175 | Timer_Value <= Timer_Value_var; 176 | end if; 177 | end process; 178 | 179 | -- Synchroner Prozess fuer das Register Timer_IRQ_i 180 | Reg_Timer_IRQ_i: process(CLK_I) is 181 | begin 182 | if rising_edge(CLK_I) then 183 | -- TODO: Register Timer_IRQ_i beschreiben 184 | -- BEGIN SOLUTION 185 | if RST_I = '1' then 186 | Timer_IRQ_i <= '0'; 187 | else 188 | if Lese_Status = '1' then 189 | Timer_IRQ_i <= '0'; 190 | end if; 191 | 192 | if TC = '1' then 193 | Timer_IRQ_i <= '1'; 194 | end if; 195 | end if; 196 | -- END SOLUTION 197 | end if; 198 | end process; 199 | end architecture; -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## VexRiscv System with Hardware GDB-Server for Basys3 2 | This project contains an example system with VexRiscv and a GDB-Server in hardware. It can directly connected with `gdb` via serial port without any Software-GDB-Server. 3 | The project can be simulated and synthesized. 4 | 5 | The system runs on [Basys3 from Digilent](https://digilent.com/reference/programmable-logic/basys-3/start). The VexRiscv is configured with Wishbone bus, jump table and external interrupts. See `VexRiscvWB_small.scala` for details. 6 | The system contains: 7 | 8 | - RAM memory of size 16k at address `0x00000000` 9 | - simulated ROM of size 16k at address `0x00010000` 10 | - GPIO 0 at address `0x00008000` connected to the Basys2 LEDs (Bits 15..0) and switches (Bits 31..16) 11 | - GPIO 1 at address `0x00008100` connected to the Basys2 7-Seg Display: Segment (Bits 6..0), DP (Bit 7), and anodes (Bits 11..8) 12 | - Timer 0 at address `0x00008200` connected to VexRiscv Timer Interrupt 13 | - Timer 1 at address `0x00008300`connected to VexRiscv Loacal Interrupt 0 14 | 15 | All these values can be changed, see `VexRiscvWB_System.vhd`.
16 | 17 | ![System](System.jpg) 18 | 19 | The system can be simulated with the testbench `VexRiscvWB_TOP_TB.vhd`. During simulation the system executes a program that can be found in directory `Test_Program`. The program is loaded by the testbench into the system via RSP-commands and then executed.
20 | For simulation with ModelSim the script file `VexRiscvWB_TOP_TB.do` is supplied. The simulation requires the `unisim`-library from Xilinx.
21 | Simulation with Vivado is also possible. 22 | 23 | In directory `Synth_Basys3` a Xilinx project file for Vivado 2020.1 is given which allows to synthesize the system.
24 | Further an already generated bitfile `VexRiscvWB_TOP.bit` is supplied that can directly be loaded into `Basys3` without synthesizing. 25 | 26 | Directory `Test_WS` contains an Eclipse-project `First`. It demonstrates how to use the GPIO and how to handle the timer interrupts. It connects the 16 switches to the 16 LEDs. Further it controls the 7Sement display and shows a hexadecimal counter value that increments each second.
27 | Setup your Eclipse workspace with the Risc-V toolchain and import the project `First` into your workspace.
28 | 29 | To connect GDB via the correct serial port of the `Basys3`-Board to the Hardware-GDB_Server (named `Debug_IF` in the above image) check the windows device manager. In the current settings COM6 is used. Adapt your debug configuration to the choosen serial port number of your computer.
30 | Below the settings for the debug configuration is shown. Consider that the remote connection is not setup in the Debugger Tab but in the Startup Tab. 31 | 32 | ![Debug Configuration Main Tab](DbgCfg_Main.jpg) 33 | 34 | ![Debug Configuration Debugger Tab](DbgCfg_Debugger.jpg) 35 | 36 | ![Debug Configuration Startup Tab](DbgCfg_Startup.jpg) 37 | 38 | If you want to use the hardware breakpoints of the VexRiscV you should use the following Commands in the Eclipse Startup Tab: 39 | 40 | file Debug/First.elf 41 | set serial baud 115200 42 | target extended-remote \\.\com6 43 | monitor r 44 | load Debug/First.elf 45 | mem 0x10000 0x1ffff ro 46 | mem 0x0000 0xffff rw 47 | 48 | **Have fun** 49 | -------------------------------------------------------------------------------- /ScaleClock.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- (c) Bernhard Lang, Hochschule Osnabrueck 3 | ---------------------------------------------------------------------------------------- 4 | library IEEE; 5 | use IEEE.STD_LOGIC_1164.ALL; 6 | library UNISIM; 7 | use UNISIM.VComponents.all; 8 | entity ScaleClock is 9 | Generic ( 10 | ExtFreq : real := 12.0; -- External frequency in MHz 11 | Mult : real := 60.000; -- Multiply value (2.000-64.000) 12 | Divide : real := 12.0 -- Divide value (1.000-128.000) 13 | ); 14 | Port ( 15 | ExtClk : in std_logic; 16 | ExtReset : in std_logic; 17 | SysClk : out std_logic; 18 | SysReset : out std_logic 19 | ); 20 | end ScaleClock; 21 | 22 | architecture arch of ScaleClock is 23 | -- signal ExtClk_buffered : std_logic := '0'; 24 | signal clkfb : std_logic := '0'; 25 | signal SysClk_i : std_logic; 26 | signal locked : std_logic := '0'; 27 | begin 28 | 29 | -- MMCME2_BASE: Base Mixed Mode Clock Manager, 7 Series 30 | MMCME2_BASE_inst : MMCME2_BASE 31 | generic map ( 32 | BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) 33 | CLKFBOUT_MULT_F => Mult, -- Multiply value for all CLKOUT (2.000-64.000). 34 | CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of CLKFB (-360.000-360.000). 35 | CLKIN1_PERIOD => 1000.0/ExtFreq, -- Input clock period in ns to ps resolution (i.e. 83.333 is 12 MHz). 36 | -- CLKOUT0_DIVIDE: Divide amount for CLKOUT0 (1.000-128.000). 37 | CLKOUT0_DIVIDE_F => Divide, -- 18.0, 38 | -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) 39 | CLKOUT1_DIVIDE => 100, 40 | CLKOUT2_DIVIDE => 100, 41 | CLKOUT3_DIVIDE => 100, 42 | CLKOUT4_DIVIDE => 100, 43 | CLKOUT5_DIVIDE => 100, 44 | CLKOUT6_DIVIDE => 100, 45 | -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). 46 | CLKOUT0_DUTY_CYCLE => 0.5, 47 | CLKOUT1_DUTY_CYCLE => 0.5, 48 | CLKOUT2_DUTY_CYCLE => 0.5, 49 | CLKOUT3_DUTY_CYCLE => 0.5, 50 | CLKOUT4_DUTY_CYCLE => 0.5, 51 | CLKOUT5_DUTY_CYCLE => 0.5, 52 | CLKOUT6_DUTY_CYCLE => 0.5, 53 | -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). 54 | CLKOUT0_PHASE => 0.0, 55 | CLKOUT1_PHASE => 0.0, 56 | CLKOUT2_PHASE => 0.0, 57 | CLKOUT3_PHASE => 0.0, 58 | CLKOUT4_PHASE => 0.0, 59 | CLKOUT5_PHASE => 0.0, 60 | CLKOUT6_PHASE => 0.0, 61 | CLKOUT4_CASCADE => FALSE, -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) 62 | DIVCLK_DIVIDE => 1, -- Master division value (1-106) 63 | REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999). 64 | STARTUP_WAIT => FALSE -- Delays DONE until MMCM is locked (FALSE, TRUE) 65 | ) 66 | port map ( 67 | -- Clock Outputs: 1-bit (each) output: User configurable clock outputs 68 | CLKOUT0 => SysClk_i, 69 | CLKOUT0B => open, 70 | CLKOUT1 => open, 71 | CLKOUT1B => open, 72 | CLKOUT2 => open, 73 | CLKOUT2B => open, 74 | CLKOUT3 => open, 75 | CLKOUT3B => open, 76 | CLKOUT4 => open, 77 | CLKOUT5 => open, 78 | CLKOUT6 => open, 79 | -- Feedback Clocks: 1-bit (each) output: Clock feedback ports 80 | CLKFBOUT => clkfb, 81 | CLKFBOUTB => open, 82 | -- Status Ports: 1-bit (each) output: MMCM status ports 83 | LOCKED => locked, 84 | -- Clock Inputs: 1-bit (each) input: Clock input 85 | CLKIN1 => ExtClk, -- ExtClk_buffered, 86 | -- Control Ports: 1-bit (each) input: MMCM control ports 87 | PWRDWN => '0', 88 | RST => ExtReset, 89 | -- Feedback Clocks: 1-bit (each) input: Clock feedback ports 90 | CLKFBIN => clkfb 91 | ); 92 | 93 | SysClk <= SysClk_i; 94 | 95 | process(SysClk_i) 96 | begin 97 | if rising_edge(SysClk_i) then 98 | SysReset <= not locked; 99 | end if; 100 | end process; 101 | 102 | end arch; -------------------------------------------------------------------------------- /Synth_Basys3/Synth_Basys3.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 175 | 176 | 177 | 178 | 179 | 181 | 182 | 183 | 184 | 185 | 188 | 189 | 191 | 192 | 194 | 195 | 197 | 198 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | default_dashboard 257 | 258 | 259 | 260 | -------------------------------------------------------------------------------- /Synth_Basys3/VexRiscvWB_TOP.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/Synth_Basys3/VexRiscvWB_TOP.bit -------------------------------------------------------------------------------- /System.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/System.jpg -------------------------------------------------------------------------------- /Test_Program/Boot.S: -------------------------------------------------------------------------------- 1 | #include "riscv_csr_encoding.h" 2 | 3 | /* -------------------------------------------------------------- 4 | * Initial jump and vector table entries. 5 | ---------------------------------------------------------------- */ 6 | 7 | .section .vector_table,"ax",%progbits 8 | 9 | .global entrypoint 10 | .type entrypoint,@function 11 | entrypoint: 12 | j startup_code 13 | 14 | .org entrypoint+16 15 | // vector table 16 | .global vtable 17 | .type vtable, %object 18 | vtable: 19 | j exception_handler // vtable+0x00000000 20 | j supervisor_software_irhandler // vtable+0x00000004 21 | j default_handler // vtable+0x00000008 22 | j machine_software_irhandler // vtable+0x0000000c 23 | j user_timer_irhandler // vtable+0x00000010 24 | j supervisor_timer_irhandler // vtable+0x00000014 25 | j default_handler // vtable+0x00000018 26 | j machine_timer_irhandler // vtable+0x0000001c 27 | j user_external_irhandler // vtable+0x00000010 28 | j supervisor_external_irhandler // vtable+0x00000014 29 | j default_handler // vtable+0x00000018 30 | j machine_external_irhandler // vtable+0x0000001c 31 | j default_handler // vtable+0x00000020 32 | j default_handler // vtable+0x00000024 33 | j default_handler // vtable+0x00000028 34 | j default_handler // vtable+0x0000002c 35 | j LocalInt0_handler // vtable+0x00000030 36 | j LocalInt1_handler // vtable+0x00000034 37 | j LocalInt2_handler // vtable+0x00000038 38 | j LocalInt3_handler // vtable+0x0000003C 39 | j LocalInt4_handler // vtable+0x00000040 40 | j LocalInt5_handler // vtable+0x00000044 41 | j LocalInt6_handler // vtable+0x00000048 42 | j LocalInt7_handler // vtable+0x0000004C 43 | j LocalInt8_handler // vtable+0x00000050 44 | j LocalInt9_handler // vtable+0x00000054 45 | j LocalIntA_handler // vtable+0x00000058 46 | j LocalIntB_handler // vtable+0x0000005C 47 | j LocalIntC_handler // vtable+0x00000060 48 | j LocalIntD_handler // vtable+0x00000064 49 | j LocalIntE_handler // vtable+0x00000068 50 | j LocalIntF_handler // vtable+0x0000006C 51 | 52 | /* -------------------------------------------------------------- 53 | * Weak aliases to point each exception handler to the 54 | * 'default_interrupt_handler', unless the application defines 55 | * a function with the same name to override the reference. 56 | ---------------------------------------------------------------- */ 57 | .global exception_handler 58 | .weak exception_handler 59 | .set exception_handler,default_handler 60 | 61 | .global supervisor_software_irhandler 62 | .weak supervisor_software_irhandler 63 | .set supervisor_software_irhandler,default_handler 64 | .global machine_software_irhandler 65 | .weak machine_software_irhandler 66 | .set machine_software_irhandler,default_handler 67 | 68 | .global user_timer_irhandler 69 | .weak user_timer_irhandler 70 | .set user_timer_irhandler,default_handler 71 | .global supervisor_timer_irhandler 72 | .weak supervisor_timer_irhandler 73 | .set supervisor_timer_irhandler,default_handler 74 | .global machine_timer_irhandler 75 | .weak machine_timer_irhandler 76 | .set machine_timer_irhandler,default_handler 77 | 78 | .global user_external_irhandler 79 | .weak user_external_irhandler 80 | .set user_external_irhandler,default_handler 81 | .global supervisor_external_irhandler 82 | .weak supervisor_external_irhandler 83 | .set supervisor_external_irhandler,default_handler 84 | .global machine_external_irhandler 85 | .weak machine_external_irhandler 86 | .set machine_external_irhandler,default_handler 87 | 88 | .global LocalInt0_handler 89 | .weak LocalInt0_handler 90 | .set LocalInt0_handler,default_handler 91 | .global LocalInt1_handler 92 | .weak LocalInt1_handler 93 | .set LocalInt1_handler,default_handler 94 | .global LocalInt2_handler 95 | .weak LocalInt2_handler 96 | .set LocalInt2_handler,default_handler 97 | .global LocalInt3_handler 98 | .weak LocalInt3_handler 99 | .set LocalInt3_handler,default_handler 100 | .global LocalInt4_handler 101 | .weak LocalInt4_handler 102 | .set LocalInt4_handler,default_handler 103 | .global LocalInt5_handler 104 | .weak LocalInt5_handler 105 | .set LocalInt5_handler,default_handler 106 | .global LocalInt6_handler 107 | .weak LocalInt6_handler 108 | .set LocalInt6_handler,default_handler 109 | .global LocalInt7_handler 110 | .weak LocalInt7_handler 111 | .set LocalInt7_handler,default_handler 112 | .global LocalInt8_handler 113 | .weak LocalInt8_handler 114 | .set LocalInt8_handler,default_handler 115 | .global LocalInt9_handler 116 | .weak LocalInt9_handler 117 | .set LocalInt9_handler,default_handler 118 | .global LocalIntA_handler 119 | .weak LocalIntA_handler 120 | .set LocalIntA_handler,default_handler 121 | .global LocalIntB_handler 122 | .weak LocalIntB_handler 123 | .set LocalIntB_handler,default_handler 124 | .global LocalIntC_handler 125 | .weak LocalIntC_handler 126 | .set LocalIntC_handler,default_handler 127 | .global LocalIntD_handler 128 | .weak LocalIntD_handler 129 | .set LocalIntD_handler,default_handler 130 | .global LocalIntE_handler 131 | .weak LocalIntE_handler 132 | .set LocalIntE_handler,default_handler 133 | .global LocalIntF_handler 134 | .weak LocalIntF_handler 135 | .set LocalIntF_handler,default_handler 136 | 137 | .section .text,"ax",%progbits 138 | 139 | /* -------------------------------------------------------------- 140 | * Assembly 'reset handler' function to initialize core CPU registers. 141 | ---------------------------------------------------------------- */ 142 | startup_code: 143 | 144 | // Disable interrupts until they are needed. 145 | csrc mstatus, (MSTATUS_MIE | MSTATUS_SIE | MSTATUS_UIE) 146 | 147 | // Load the initial stack pointer value. 148 | la sp, _sp 149 | 150 | // ---------------------------------------------- 151 | test_begin: 152 | addi x3, x0, 0 // 0 153 | addi x3, x3, 1 // 1 154 | .option rvc 155 | c.addi x3, 2 // 3 156 | .option norvc 157 | addi x3, x3, 3 // 6 158 | addi x3, x3, 4 // 10 159 | addi x3, x3, 5 // 15 160 | .option rvc 161 | addi x3, x3, 6 // 21 162 | addi x3, x3, 7 // 28 163 | .option norvc 164 | addi x3, x3, 8 // 36 165 | addi x3, x3, 9 // 45 166 | addi x3, x3, 10 // 55 167 | j test_begin 168 | // ---------------------------------------------- 169 | 170 | // default handler 171 | default_handler: 172 | j default_handler 173 | -------------------------------------------------------------------------------- /Test_Program/Linker.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY( entrypoint ) 3 | 4 | MEMORY { 5 | FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 16K 6 | RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 4K 7 | } 8 | 9 | SECTIONS { 10 | __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; 11 | .vector_table : { 12 | KEEP (*(SORT_NONE(.vector_table))) 13 | } >FLASH 14 | 15 | .text : { 16 | *(.text .text.*) 17 | *(.text*) 18 | *(.rodata .rodata.*) 19 | *(.srodata .srodata.*) 20 | } >FLASH 21 | . = ALIGN(4); 22 | PROVIDE (__etext = .); 23 | PROVIDE (_etext = .); 24 | PROVIDE (etext = .); 25 | 26 | _sidata = .; 27 | .data : AT( _sidata ) { 28 | _sdata = .; 29 | *(.rdata) 30 | *(.data .data.*) 31 | *(.data*) 32 | *(.sdata .sdata.*) 33 | . = ALIGN(4); 34 | _edata = .; 35 | } >RAM 36 | PROVIDE( _edata = . ); 37 | PROVIDE( edata = . ); 38 | 39 | PROVIDE( _fbss = . ); 40 | PROVIDE( __bss_start = . ); 41 | .bss : { 42 | _sbss = .; 43 | *(.sbss*) 44 | *(.bss .bss.*) 45 | *(COMMON) 46 | . = ALIGN(4); 47 | _ebss = .; 48 | } >RAM 49 | . = ALIGN(8); 50 | PROVIDE( _end = . ); 51 | PROVIDE( end = . ); 52 | 53 | /* 54 | .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { 55 | PROVIDE( _heap_end = . ); 56 | . = __stack_size; 57 | PROVIDE( _sp = . ); 58 | } >RAM 59 | */ 60 | PROVIDE(_sp = ORIGIN(RAM) + LENGTH(RAM)); 61 | } -------------------------------------------------------------------------------- /Test_Program/Make_all.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-windows-build-tools-4.2.1-2\bin;%path% 2 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin;%path% 3 | 4 | make 5 | 6 | pause 7 | -------------------------------------------------------------------------------- /Test_Program/Make_clean.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-windows-build-tools-4.2.1-2\bin;%path% 2 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin;%path% 3 | 4 | make clean 5 | 6 | pause 7 | -------------------------------------------------------------------------------- /Test_Program/Makefile: -------------------------------------------------------------------------------- 1 | # GCC toolchain programs. 2 | CC = riscv-none-embed-gcc 3 | OC = riscv-none-embed-objcopy 4 | OD = riscv-none-embed-objdump 5 | OS = riscv-none-embed-size 6 | ARCH=rv32i 7 | 8 | # Assembly directives. 9 | ASFLAGS += -c 10 | ASFLAGS += -O0 11 | ASFLAGS += -g 12 | ASFLAGS += -Wall 13 | ASFLAGS += -fmessage-length=0 14 | ASFLAGS += -mno-div 15 | ASFLAGS += -march=$(ARCH) # -march=rv32ic 16 | ASFLAGS += -mabi=ilp32 17 | ASFLAGS += -mcmodel=medlow 18 | 19 | # C compilation directives 20 | CFLAGS += -c 21 | CFLAGS += -Wall 22 | CFLAGS += -O0 23 | CFLAGS += -g 24 | CFLAGS += -fmessage-length=0 25 | CFLAGS += --specs=nosys.specs 26 | CFLAGS += -mno-div 27 | CFLAGS += -march=$(ARCH) # -march=rv32ic 28 | CFLAGS += -mabi=ilp32 29 | CFLAGS += -mcmodel=medlow 30 | 31 | # Linker directives. 32 | LFLAGS += -Wall 33 | LFLAGS += -Wl,--no-relax 34 | LFLAGS += -Wl,--gc-sections 35 | LFLAGS += -nostdlib 36 | LFLAGS += -nostartfiles 37 | LFLAGS += -lc 38 | LFLAGS += -lgcc 39 | LFLAGS += --specs=nosys.specs 40 | LFLAGS += -mno-div 41 | LFLAGS += -march=$(ARCH) # -march=rv32ic 42 | LFLAGS += -mabi=ilp32 43 | LFLAGS += -mcmodel=medlow # Generate code for the medium-low code model 44 | LFLAGS += -TLinker.ld 45 | 46 | # Source files. 47 | AS_SRC = Boot.S 48 | C_SRC = 49 | 50 | # Header file directories. 51 | #INCLUDE = -I./../common/device_headers 52 | 53 | # Object files to build. 54 | OBJS = $(AS_SRC:.S=.o) 55 | OBJS += $(C_SRC:.c=.o) 56 | 57 | # Default rule to build the whole project. 58 | .PHONY: all 59 | all: main.bin main_diss.txt main.hex 60 | 61 | # Rule to build assembly files. 62 | %.o: %.S 63 | $(CC) -x assembler-with-cpp $(ASFLAGS) $(INCLUDE) $< -o $@ 64 | 65 | # Rule to compile C files. 66 | %.o: %.c 67 | $(CC) $(CFLAGS) $(INCLUDE) $< -o $@ 68 | 69 | # Rule to create an ELF file from the compiled object files. 70 | main.elf: $(OBJS) 71 | $(CC) $^ $(LFLAGS) -o $@ 72 | 73 | # Rule to create a raw binary file from an ELF file. 74 | main.bin: main.elf 75 | $(OC) -S -O binary $< $@ 76 | $(OS) $< 77 | 78 | # disassemble for information purpose 79 | main_diss.txt: main.elf 80 | 81 | # $(OD) -h -t -j.vectors -j.text -j.data -j.bss -S $< > $@ 82 | $(OD) -D -S $< > $@ 83 | 84 | # Generate HEX-FIle for memory initialization 85 | main.hex: main.elf 86 | $(OC) -O ihex $< $@ 87 | 88 | # Rule to clear out generated build files. 89 | .PHONY: clean 90 | clean: 91 | rm -f $(OBJS) 92 | rm -f main.elf 93 | rm -f main.bin 94 | rm -f main.hex 95 | rm -f main_diss.txt 96 | -------------------------------------------------------------------------------- /Test_Program/Readelf.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin;%path% 2 | 3 | riscv-none-embed-readelf -h -l -s -t -s main.elf 4 | 5 | pause -------------------------------------------------------------------------------- /Test_Program/gdb_riscv32_serial.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin;%path% 2 | 3 | del gdb.x 4 | echo set serial baud 115200 >gdb.x 5 | echo set debug remote 1 >>gdb.x 6 | echo file main.elf >>gdb.x 7 | echo target remote \\.\com6 >>gdb.x 8 | 9 | riscv-none-embed-gdb -x gdb.x 10 | 11 | pause -------------------------------------------------------------------------------- /Test_Program/riscv_csr_encoding.h: -------------------------------------------------------------------------------- 1 | // Original file: "encoding.h" from repository https://github.com/SpinalHDL/VexRiscv 2 | // See LICENSE for license details. 3 | 4 | #ifndef RISCV_CSR_ENCODING_H 5 | #define RISCV_CSR_ENCODING_H 6 | 7 | #define MSTATUS_UIE 0x00000001 8 | #define MSTATUS_SIE 0x00000002 9 | #define MSTATUS_HIE 0x00000004 10 | #define MSTATUS_MIE 0x00000008 11 | #define MSTATUS_UPIE 0x00000010 12 | #define MSTATUS_SPIE 0x00000020 13 | #define MSTATUS_HPIE 0x00000040 14 | #define MSTATUS_MPIE 0x00000080 15 | #define MSTATUS_SPP 0x00000100 16 | #define MSTATUS_HPP 0x00000600 17 | #define MSTATUS_MPP 0x00001800 18 | #define MSTATUS_FS 0x00006000 19 | #define MSTATUS_XS 0x00018000 20 | #define MSTATUS_MPRV 0x00020000 21 | #define MSTATUS_SUM 0x00040000 22 | #define MSTATUS_MXR 0x00080000 23 | #define MSTATUS_TVM 0x00100000 24 | #define MSTATUS_TW 0x00200000 25 | #define MSTATUS_TSR 0x00400000 26 | #define MSTATUS32_SD 0x80000000 27 | #define MSTATUS_UXL 0x0000000300000000 28 | #define MSTATUS_SXL 0x0000000C00000000 29 | #define MSTATUS64_SD 0x8000000000000000 30 | 31 | #define SSTATUS_UIE 0x00000001 32 | #define SSTATUS_SIE 0x00000002 33 | #define SSTATUS_UPIE 0x00000010 34 | #define SSTATUS_SPIE 0x00000020 35 | #define SSTATUS_SPP 0x00000100 36 | #define SSTATUS_FS 0x00006000 37 | #define SSTATUS_XS 0x00018000 38 | #define SSTATUS_SUM 0x00040000 39 | #define SSTATUS_MXR 0x00080000 40 | #define SSTATUS32_SD 0x80000000 41 | #define SSTATUS_UXL 0x0000000300000000 42 | #define SSTATUS64_SD 0x8000000000000000 43 | 44 | #define DCSR_XDEBUGVER (3U<<30) 45 | #define DCSR_NDRESET (1<<29) 46 | #define DCSR_FULLRESET (1<<28) 47 | #define DCSR_EBREAKM (1<<15) 48 | #define DCSR_EBREAKH (1<<14) 49 | #define DCSR_EBREAKS (1<<13) 50 | #define DCSR_EBREAKU (1<<12) 51 | #define DCSR_STOPCYCLE (1<<10) 52 | #define DCSR_STOPTIME (1<<9) 53 | #define DCSR_CAUSE (7<<6) 54 | #define DCSR_DEBUGINT (1<<5) 55 | #define DCSR_HALT (1<<3) 56 | #define DCSR_STEP (1<<2) 57 | #define DCSR_PRV (3<<0) 58 | 59 | #define DCSR_CAUSE_NONE 0 60 | #define DCSR_CAUSE_SWBP 1 61 | #define DCSR_CAUSE_HWBP 2 62 | #define DCSR_CAUSE_DEBUGINT 3 63 | #define DCSR_CAUSE_STEP 4 64 | #define DCSR_CAUSE_HALT 5 65 | 66 | #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4)) 67 | #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5)) 68 | #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11)) 69 | 70 | #define MCONTROL_SELECT (1<<19) 71 | #define MCONTROL_TIMING (1<<18) 72 | #define MCONTROL_ACTION (0x3f<<12) 73 | #define MCONTROL_CHAIN (1<<11) 74 | #define MCONTROL_MATCH (0xf<<7) 75 | #define MCONTROL_M (1<<6) 76 | #define MCONTROL_H (1<<5) 77 | #define MCONTROL_S (1<<4) 78 | #define MCONTROL_U (1<<3) 79 | #define MCONTROL_EXECUTE (1<<2) 80 | #define MCONTROL_STORE (1<<1) 81 | #define MCONTROL_LOAD (1<<0) 82 | 83 | #define MCONTROL_TYPE_NONE 0 84 | #define MCONTROL_TYPE_MATCH 2 85 | 86 | #define MCONTROL_ACTION_DEBUG_EXCEPTION 0 87 | #define MCONTROL_ACTION_DEBUG_MODE 1 88 | #define MCONTROL_ACTION_TRACE_START 2 89 | #define MCONTROL_ACTION_TRACE_STOP 3 90 | #define MCONTROL_ACTION_TRACE_EMIT 4 91 | 92 | #define MCONTROL_MATCH_EQUAL 0 93 | #define MCONTROL_MATCH_NAPOT 1 94 | #define MCONTROL_MATCH_GE 2 95 | #define MCONTROL_MATCH_LT 3 96 | #define MCONTROL_MATCH_MASK_LOW 4 97 | #define MCONTROL_MATCH_MASK_HIGH 5 98 | 99 | #define MIP_SSIP (1 << IRQ_S_SOFT) 100 | #define MIP_HSIP (1 << IRQ_H_SOFT) 101 | #define MIP_MSIP (1 << IRQ_M_SOFT) 102 | #define MIP_STIP (1 << IRQ_S_TIMER) 103 | #define MIP_HTIP (1 << IRQ_H_TIMER) 104 | #define MIP_MTIP (1 << IRQ_M_TIMER) 105 | #define MIP_SEIP (1 << IRQ_S_EXT) 106 | #define MIP_HEIP (1 << IRQ_H_EXT) 107 | #define MIP_MEIP (1 << IRQ_M_EXT) 108 | 109 | #define SIP_SSIP MIP_SSIP 110 | #define SIP_STIP MIP_STIP 111 | 112 | #define PRV_U 0 113 | #define PRV_S 1 114 | #define PRV_H 2 115 | #define PRV_M 3 116 | 117 | #define SATP32_MODE 0x80000000 118 | #define SATP32_ASID 0x7FC00000 119 | #define SATP32_PPN 0x003FFFFF 120 | #define SATP64_MODE 0xF000000000000000 121 | #define SATP64_ASID 0x0FFFF00000000000 122 | #define SATP64_PPN 0x00000FFFFFFFFFFF 123 | 124 | #define SATP_MODE_OFF 0 125 | #define SATP_MODE_SV32 1 126 | #define SATP_MODE_SV39 8 127 | #define SATP_MODE_SV48 9 128 | #define SATP_MODE_SV57 10 129 | #define SATP_MODE_SV64 11 130 | 131 | #define PMP_R 0x01 132 | #define PMP_W 0x02 133 | #define PMP_X 0x04 134 | #define PMP_A 0x18 135 | #define PMP_L 0x80 136 | #define PMP_SHIFT 2 137 | 138 | #define PMP_TOR 0x08 139 | #define PMP_NA4 0x10 140 | #define PMP_NAPOT 0x18 141 | 142 | #define IRQ_S_SOFT 1 143 | #define IRQ_H_SOFT 2 144 | #define IRQ_M_SOFT 3 145 | #define IRQ_S_TIMER 5 146 | #define IRQ_H_TIMER 6 147 | #define IRQ_M_TIMER 7 148 | #define IRQ_S_EXT 9 149 | #define IRQ_H_EXT 10 150 | #define IRQ_M_EXT 11 151 | #define IRQ_COP 12 152 | #define IRQ_HOST 13 153 | 154 | #define DEFAULT_RSTVEC 0x00001000 155 | #define CLINT_BASE 0x02000000 156 | #define CLINT_SIZE 0x000c0000 157 | #define EXT_IO_BASE 0x40000000 158 | #define DRAM_BASE 0x80000000 159 | 160 | // page table entry (PTE) fields 161 | #define PTE_V 0x001 // Valid 162 | #define PTE_R 0x002 // Read 163 | #define PTE_W 0x004 // Write 164 | #define PTE_X 0x008 // Execute 165 | #define PTE_U 0x010 // User 166 | #define PTE_G 0x020 // Global 167 | #define PTE_A 0x040 // Accessed 168 | #define PTE_D 0x080 // Dirty 169 | #define PTE_SOFT 0x300 // Reserved for Software 170 | 171 | #define PTE_PPN_SHIFT 10 172 | 173 | #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) 174 | 175 | #ifdef __riscv 176 | 177 | #if __riscv_xlen == 64 178 | # define MSTATUS_SD MSTATUS64_SD 179 | # define SSTATUS_SD SSTATUS64_SD 180 | # define RISCV_PGLEVEL_BITS 9 181 | # define SATP_MODE SATP64_MODE 182 | #else 183 | # define MSTATUS_SD MSTATUS32_SD 184 | # define SSTATUS_SD SSTATUS32_SD 185 | # define RISCV_PGLEVEL_BITS 10 186 | # define SATP_MODE SATP32_MODE 187 | #endif 188 | #define RISCV_PGSHIFT 12 189 | #define RISCV_PGSIZE (1 << RISCV_PGSHIFT) 190 | 191 | #ifndef __ASSEMBLER__ 192 | 193 | #ifdef __GNUC__ 194 | 195 | #define read_csr(reg) ({ unsigned long __tmp; \ 196 | asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ 197 | __tmp; }) 198 | 199 | #define write_csr(reg, val) ({ \ 200 | asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) 201 | 202 | #define swap_csr(reg, val) ({ unsigned long __tmp; \ 203 | asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ 204 | __tmp; }) 205 | 206 | #define set_csr(reg, bit) ({ unsigned long __tmp; \ 207 | asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 208 | __tmp; }) 209 | 210 | #define clear_csr(reg, bit) ({ unsigned long __tmp; \ 211 | asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ 212 | __tmp; }) 213 | 214 | #define rdtime() read_csr(time) 215 | #define rdcycle() read_csr(cycle) 216 | #define rdinstret() read_csr(instret) 217 | 218 | #endif 219 | 220 | #endif 221 | 222 | #endif 223 | 224 | #endif 225 | /* Automatically generated by parse-opcodes. */ 226 | #ifndef RISCV_ENCODING_H 227 | #define RISCV_ENCODING_H 228 | #define MATCH_BEQ 0x63 229 | #define MASK_BEQ 0x707f 230 | #define MATCH_BNE 0x1063 231 | #define MASK_BNE 0x707f 232 | #define MATCH_BLT 0x4063 233 | #define MASK_BLT 0x707f 234 | #define MATCH_BGE 0x5063 235 | #define MASK_BGE 0x707f 236 | #define MATCH_BLTU 0x6063 237 | #define MASK_BLTU 0x707f 238 | #define MATCH_BGEU 0x7063 239 | #define MASK_BGEU 0x707f 240 | #define MATCH_JALR 0x67 241 | #define MASK_JALR 0x707f 242 | #define MATCH_JAL 0x6f 243 | #define MASK_JAL 0x7f 244 | #define MATCH_LUI 0x37 245 | #define MASK_LUI 0x7f 246 | #define MATCH_AUIPC 0x17 247 | #define MASK_AUIPC 0x7f 248 | #define MATCH_ADDI 0x13 249 | #define MASK_ADDI 0x707f 250 | #define MATCH_SLLI 0x1013 251 | #define MASK_SLLI 0xfc00707f 252 | #define MATCH_SLTI 0x2013 253 | #define MASK_SLTI 0x707f 254 | #define MATCH_SLTIU 0x3013 255 | #define MASK_SLTIU 0x707f 256 | #define MATCH_XORI 0x4013 257 | #define MASK_XORI 0x707f 258 | #define MATCH_SRLI 0x5013 259 | #define MASK_SRLI 0xfc00707f 260 | #define MATCH_SRAI 0x40005013 261 | #define MASK_SRAI 0xfc00707f 262 | #define MATCH_ORI 0x6013 263 | #define MASK_ORI 0x707f 264 | #define MATCH_ANDI 0x7013 265 | #define MASK_ANDI 0x707f 266 | #define MATCH_ADD 0x33 267 | #define MASK_ADD 0xfe00707f 268 | #define MATCH_SUB 0x40000033 269 | #define MASK_SUB 0xfe00707f 270 | #define MATCH_SLL 0x1033 271 | #define MASK_SLL 0xfe00707f 272 | #define MATCH_SLT 0x2033 273 | #define MASK_SLT 0xfe00707f 274 | #define MATCH_SLTU 0x3033 275 | #define MASK_SLTU 0xfe00707f 276 | #define MATCH_XOR 0x4033 277 | #define MASK_XOR 0xfe00707f 278 | #define MATCH_SRL 0x5033 279 | #define MASK_SRL 0xfe00707f 280 | #define MATCH_SRA 0x40005033 281 | #define MASK_SRA 0xfe00707f 282 | #define MATCH_OR 0x6033 283 | #define MASK_OR 0xfe00707f 284 | #define MATCH_AND 0x7033 285 | #define MASK_AND 0xfe00707f 286 | #define MATCH_ADDIW 0x1b 287 | #define MASK_ADDIW 0x707f 288 | #define MATCH_SLLIW 0x101b 289 | #define MASK_SLLIW 0xfe00707f 290 | #define MATCH_SRLIW 0x501b 291 | #define MASK_SRLIW 0xfe00707f 292 | #define MATCH_SRAIW 0x4000501b 293 | #define MASK_SRAIW 0xfe00707f 294 | #define MATCH_ADDW 0x3b 295 | #define MASK_ADDW 0xfe00707f 296 | #define MATCH_SUBW 0x4000003b 297 | #define MASK_SUBW 0xfe00707f 298 | #define MATCH_SLLW 0x103b 299 | #define MASK_SLLW 0xfe00707f 300 | #define MATCH_SRLW 0x503b 301 | #define MASK_SRLW 0xfe00707f 302 | #define MATCH_SRAW 0x4000503b 303 | #define MASK_SRAW 0xfe00707f 304 | #define MATCH_LB 0x3 305 | #define MASK_LB 0x707f 306 | #define MATCH_LH 0x1003 307 | #define MASK_LH 0x707f 308 | #define MATCH_LW 0x2003 309 | #define MASK_LW 0x707f 310 | #define MATCH_LD 0x3003 311 | #define MASK_LD 0x707f 312 | #define MATCH_LBU 0x4003 313 | #define MASK_LBU 0x707f 314 | #define MATCH_LHU 0x5003 315 | #define MASK_LHU 0x707f 316 | #define MATCH_LWU 0x6003 317 | #define MASK_LWU 0x707f 318 | #define MATCH_SB 0x23 319 | #define MASK_SB 0x707f 320 | #define MATCH_SH 0x1023 321 | #define MASK_SH 0x707f 322 | #define MATCH_SW 0x2023 323 | #define MASK_SW 0x707f 324 | #define MATCH_SD 0x3023 325 | #define MASK_SD 0x707f 326 | #define MATCH_FENCE 0xf 327 | #define MASK_FENCE 0x707f 328 | #define MATCH_FENCE_I 0x100f 329 | #define MASK_FENCE_I 0x707f 330 | #define MATCH_MUL 0x2000033 331 | #define MASK_MUL 0xfe00707f 332 | #define MATCH_MULH 0x2001033 333 | #define MASK_MULH 0xfe00707f 334 | #define MATCH_MULHSU 0x2002033 335 | #define MASK_MULHSU 0xfe00707f 336 | #define MATCH_MULHU 0x2003033 337 | #define MASK_MULHU 0xfe00707f 338 | #define MATCH_DIV 0x2004033 339 | #define MASK_DIV 0xfe00707f 340 | #define MATCH_DIVU 0x2005033 341 | #define MASK_DIVU 0xfe00707f 342 | #define MATCH_REM 0x2006033 343 | #define MASK_REM 0xfe00707f 344 | #define MATCH_REMU 0x2007033 345 | #define MASK_REMU 0xfe00707f 346 | #define MATCH_MULW 0x200003b 347 | #define MASK_MULW 0xfe00707f 348 | #define MATCH_DIVW 0x200403b 349 | #define MASK_DIVW 0xfe00707f 350 | #define MATCH_DIVUW 0x200503b 351 | #define MASK_DIVUW 0xfe00707f 352 | #define MATCH_REMW 0x200603b 353 | #define MASK_REMW 0xfe00707f 354 | #define MATCH_REMUW 0x200703b 355 | #define MASK_REMUW 0xfe00707f 356 | #define MATCH_AMOADD_W 0x202f 357 | #define MASK_AMOADD_W 0xf800707f 358 | #define MATCH_AMOXOR_W 0x2000202f 359 | #define MASK_AMOXOR_W 0xf800707f 360 | #define MATCH_AMOOR_W 0x4000202f 361 | #define MASK_AMOOR_W 0xf800707f 362 | #define MATCH_AMOAND_W 0x6000202f 363 | #define MASK_AMOAND_W 0xf800707f 364 | #define MATCH_AMOMIN_W 0x8000202f 365 | #define MASK_AMOMIN_W 0xf800707f 366 | #define MATCH_AMOMAX_W 0xa000202f 367 | #define MASK_AMOMAX_W 0xf800707f 368 | #define MATCH_AMOMINU_W 0xc000202f 369 | #define MASK_AMOMINU_W 0xf800707f 370 | #define MATCH_AMOMAXU_W 0xe000202f 371 | #define MASK_AMOMAXU_W 0xf800707f 372 | #define MATCH_AMOSWAP_W 0x800202f 373 | #define MASK_AMOSWAP_W 0xf800707f 374 | #define MATCH_LR_W 0x1000202f 375 | #define MASK_LR_W 0xf9f0707f 376 | #define MATCH_SC_W 0x1800202f 377 | #define MASK_SC_W 0xf800707f 378 | #define MATCH_AMOADD_D 0x302f 379 | #define MASK_AMOADD_D 0xf800707f 380 | #define MATCH_AMOXOR_D 0x2000302f 381 | #define MASK_AMOXOR_D 0xf800707f 382 | #define MATCH_AMOOR_D 0x4000302f 383 | #define MASK_AMOOR_D 0xf800707f 384 | #define MATCH_AMOAND_D 0x6000302f 385 | #define MASK_AMOAND_D 0xf800707f 386 | #define MATCH_AMOMIN_D 0x8000302f 387 | #define MASK_AMOMIN_D 0xf800707f 388 | #define MATCH_AMOMAX_D 0xa000302f 389 | #define MASK_AMOMAX_D 0xf800707f 390 | #define MATCH_AMOMINU_D 0xc000302f 391 | #define MASK_AMOMINU_D 0xf800707f 392 | #define MATCH_AMOMAXU_D 0xe000302f 393 | #define MASK_AMOMAXU_D 0xf800707f 394 | #define MATCH_AMOSWAP_D 0x800302f 395 | #define MASK_AMOSWAP_D 0xf800707f 396 | #define MATCH_LR_D 0x1000302f 397 | #define MASK_LR_D 0xf9f0707f 398 | #define MATCH_SC_D 0x1800302f 399 | #define MASK_SC_D 0xf800707f 400 | #define MATCH_ECALL 0x73 401 | #define MASK_ECALL 0xffffffff 402 | #define MATCH_EBREAK 0x100073 403 | #define MASK_EBREAK 0xffffffff 404 | #define MATCH_URET 0x200073 405 | #define MASK_URET 0xffffffff 406 | #define MATCH_SRET 0x10200073 407 | #define MASK_SRET 0xffffffff 408 | #define MATCH_MRET 0x30200073 409 | #define MASK_MRET 0xffffffff 410 | #define MATCH_DRET 0x7b200073 411 | #define MASK_DRET 0xffffffff 412 | #define MATCH_SFENCE_VMA 0x12000073 413 | #define MASK_SFENCE_VMA 0xfe007fff 414 | #define MATCH_WFI 0x10500073 415 | #define MASK_WFI 0xffffffff 416 | #define MATCH_CSRRW 0x1073 417 | #define MASK_CSRRW 0x707f 418 | #define MATCH_CSRRS 0x2073 419 | #define MASK_CSRRS 0x707f 420 | #define MATCH_CSRRC 0x3073 421 | #define MASK_CSRRC 0x707f 422 | #define MATCH_CSRRWI 0x5073 423 | #define MASK_CSRRWI 0x707f 424 | #define MATCH_CSRRSI 0x6073 425 | #define MASK_CSRRSI 0x707f 426 | #define MATCH_CSRRCI 0x7073 427 | #define MASK_CSRRCI 0x707f 428 | #define MATCH_FADD_S 0x53 429 | #define MASK_FADD_S 0xfe00007f 430 | #define MATCH_FSUB_S 0x8000053 431 | #define MASK_FSUB_S 0xfe00007f 432 | #define MATCH_FMUL_S 0x10000053 433 | #define MASK_FMUL_S 0xfe00007f 434 | #define MATCH_FDIV_S 0x18000053 435 | #define MASK_FDIV_S 0xfe00007f 436 | #define MATCH_FSGNJ_S 0x20000053 437 | #define MASK_FSGNJ_S 0xfe00707f 438 | #define MATCH_FSGNJN_S 0x20001053 439 | #define MASK_FSGNJN_S 0xfe00707f 440 | #define MATCH_FSGNJX_S 0x20002053 441 | #define MASK_FSGNJX_S 0xfe00707f 442 | #define MATCH_FMIN_S 0x28000053 443 | #define MASK_FMIN_S 0xfe00707f 444 | #define MATCH_FMAX_S 0x28001053 445 | #define MASK_FMAX_S 0xfe00707f 446 | #define MATCH_FSQRT_S 0x58000053 447 | #define MASK_FSQRT_S 0xfff0007f 448 | #define MATCH_FADD_D 0x2000053 449 | #define MASK_FADD_D 0xfe00007f 450 | #define MATCH_FSUB_D 0xa000053 451 | #define MASK_FSUB_D 0xfe00007f 452 | #define MATCH_FMUL_D 0x12000053 453 | #define MASK_FMUL_D 0xfe00007f 454 | #define MATCH_FDIV_D 0x1a000053 455 | #define MASK_FDIV_D 0xfe00007f 456 | #define MATCH_FSGNJ_D 0x22000053 457 | #define MASK_FSGNJ_D 0xfe00707f 458 | #define MATCH_FSGNJN_D 0x22001053 459 | #define MASK_FSGNJN_D 0xfe00707f 460 | #define MATCH_FSGNJX_D 0x22002053 461 | #define MASK_FSGNJX_D 0xfe00707f 462 | #define MATCH_FMIN_D 0x2a000053 463 | #define MASK_FMIN_D 0xfe00707f 464 | #define MATCH_FMAX_D 0x2a001053 465 | #define MASK_FMAX_D 0xfe00707f 466 | #define MATCH_FCVT_S_D 0x40100053 467 | #define MASK_FCVT_S_D 0xfff0007f 468 | #define MATCH_FCVT_D_S 0x42000053 469 | #define MASK_FCVT_D_S 0xfff0007f 470 | #define MATCH_FSQRT_D 0x5a000053 471 | #define MASK_FSQRT_D 0xfff0007f 472 | #define MATCH_FADD_Q 0x6000053 473 | #define MASK_FADD_Q 0xfe00007f 474 | #define MATCH_FSUB_Q 0xe000053 475 | #define MASK_FSUB_Q 0xfe00007f 476 | #define MATCH_FMUL_Q 0x16000053 477 | #define MASK_FMUL_Q 0xfe00007f 478 | #define MATCH_FDIV_Q 0x1e000053 479 | #define MASK_FDIV_Q 0xfe00007f 480 | #define MATCH_FSGNJ_Q 0x26000053 481 | #define MASK_FSGNJ_Q 0xfe00707f 482 | #define MATCH_FSGNJN_Q 0x26001053 483 | #define MASK_FSGNJN_Q 0xfe00707f 484 | #define MATCH_FSGNJX_Q 0x26002053 485 | #define MASK_FSGNJX_Q 0xfe00707f 486 | #define MATCH_FMIN_Q 0x2e000053 487 | #define MASK_FMIN_Q 0xfe00707f 488 | #define MATCH_FMAX_Q 0x2e001053 489 | #define MASK_FMAX_Q 0xfe00707f 490 | #define MATCH_FCVT_S_Q 0x40300053 491 | #define MASK_FCVT_S_Q 0xfff0007f 492 | #define MATCH_FCVT_Q_S 0x46000053 493 | #define MASK_FCVT_Q_S 0xfff0007f 494 | #define MATCH_FCVT_D_Q 0x42300053 495 | #define MASK_FCVT_D_Q 0xfff0007f 496 | #define MATCH_FCVT_Q_D 0x46100053 497 | #define MASK_FCVT_Q_D 0xfff0007f 498 | #define MATCH_FSQRT_Q 0x5e000053 499 | #define MASK_FSQRT_Q 0xfff0007f 500 | #define MATCH_FLE_S 0xa0000053 501 | #define MASK_FLE_S 0xfe00707f 502 | #define MATCH_FLT_S 0xa0001053 503 | #define MASK_FLT_S 0xfe00707f 504 | #define MATCH_FEQ_S 0xa0002053 505 | #define MASK_FEQ_S 0xfe00707f 506 | #define MATCH_FLE_D 0xa2000053 507 | #define MASK_FLE_D 0xfe00707f 508 | #define MATCH_FLT_D 0xa2001053 509 | #define MASK_FLT_D 0xfe00707f 510 | #define MATCH_FEQ_D 0xa2002053 511 | #define MASK_FEQ_D 0xfe00707f 512 | #define MATCH_FLE_Q 0xa6000053 513 | #define MASK_FLE_Q 0xfe00707f 514 | #define MATCH_FLT_Q 0xa6001053 515 | #define MASK_FLT_Q 0xfe00707f 516 | #define MATCH_FEQ_Q 0xa6002053 517 | #define MASK_FEQ_Q 0xfe00707f 518 | #define MATCH_FCVT_W_S 0xc0000053 519 | #define MASK_FCVT_W_S 0xfff0007f 520 | #define MATCH_FCVT_WU_S 0xc0100053 521 | #define MASK_FCVT_WU_S 0xfff0007f 522 | #define MATCH_FCVT_L_S 0xc0200053 523 | #define MASK_FCVT_L_S 0xfff0007f 524 | #define MATCH_FCVT_LU_S 0xc0300053 525 | #define MASK_FCVT_LU_S 0xfff0007f 526 | #define MATCH_FMV_X_W 0xe0000053 527 | #define MASK_FMV_X_W 0xfff0707f 528 | #define MATCH_FCLASS_S 0xe0001053 529 | #define MASK_FCLASS_S 0xfff0707f 530 | #define MATCH_FCVT_W_D 0xc2000053 531 | #define MASK_FCVT_W_D 0xfff0007f 532 | #define MATCH_FCVT_WU_D 0xc2100053 533 | #define MASK_FCVT_WU_D 0xfff0007f 534 | #define MATCH_FCVT_L_D 0xc2200053 535 | #define MASK_FCVT_L_D 0xfff0007f 536 | #define MATCH_FCVT_LU_D 0xc2300053 537 | #define MASK_FCVT_LU_D 0xfff0007f 538 | #define MATCH_FMV_X_D 0xe2000053 539 | #define MASK_FMV_X_D 0xfff0707f 540 | #define MATCH_FCLASS_D 0xe2001053 541 | #define MASK_FCLASS_D 0xfff0707f 542 | #define MATCH_FCVT_W_Q 0xc6000053 543 | #define MASK_FCVT_W_Q 0xfff0007f 544 | #define MATCH_FCVT_WU_Q 0xc6100053 545 | #define MASK_FCVT_WU_Q 0xfff0007f 546 | #define MATCH_FCVT_L_Q 0xc6200053 547 | #define MASK_FCVT_L_Q 0xfff0007f 548 | #define MATCH_FCVT_LU_Q 0xc6300053 549 | #define MASK_FCVT_LU_Q 0xfff0007f 550 | #define MATCH_FMV_X_Q 0xe6000053 551 | #define MASK_FMV_X_Q 0xfff0707f 552 | #define MATCH_FCLASS_Q 0xe6001053 553 | #define MASK_FCLASS_Q 0xfff0707f 554 | #define MATCH_FCVT_S_W 0xd0000053 555 | #define MASK_FCVT_S_W 0xfff0007f 556 | #define MATCH_FCVT_S_WU 0xd0100053 557 | #define MASK_FCVT_S_WU 0xfff0007f 558 | #define MATCH_FCVT_S_L 0xd0200053 559 | #define MASK_FCVT_S_L 0xfff0007f 560 | #define MATCH_FCVT_S_LU 0xd0300053 561 | #define MASK_FCVT_S_LU 0xfff0007f 562 | #define MATCH_FMV_W_X 0xf0000053 563 | #define MASK_FMV_W_X 0xfff0707f 564 | #define MATCH_FCVT_D_W 0xd2000053 565 | #define MASK_FCVT_D_W 0xfff0007f 566 | #define MATCH_FCVT_D_WU 0xd2100053 567 | #define MASK_FCVT_D_WU 0xfff0007f 568 | #define MATCH_FCVT_D_L 0xd2200053 569 | #define MASK_FCVT_D_L 0xfff0007f 570 | #define MATCH_FCVT_D_LU 0xd2300053 571 | #define MASK_FCVT_D_LU 0xfff0007f 572 | #define MATCH_FMV_D_X 0xf2000053 573 | #define MASK_FMV_D_X 0xfff0707f 574 | #define MATCH_FCVT_Q_W 0xd6000053 575 | #define MASK_FCVT_Q_W 0xfff0007f 576 | #define MATCH_FCVT_Q_WU 0xd6100053 577 | #define MASK_FCVT_Q_WU 0xfff0007f 578 | #define MATCH_FCVT_Q_L 0xd6200053 579 | #define MASK_FCVT_Q_L 0xfff0007f 580 | #define MATCH_FCVT_Q_LU 0xd6300053 581 | #define MASK_FCVT_Q_LU 0xfff0007f 582 | #define MATCH_FMV_Q_X 0xf6000053 583 | #define MASK_FMV_Q_X 0xfff0707f 584 | #define MATCH_FLW 0x2007 585 | #define MASK_FLW 0x707f 586 | #define MATCH_FLD 0x3007 587 | #define MASK_FLD 0x707f 588 | #define MATCH_FLQ 0x4007 589 | #define MASK_FLQ 0x707f 590 | #define MATCH_FSW 0x2027 591 | #define MASK_FSW 0x707f 592 | #define MATCH_FSD 0x3027 593 | #define MASK_FSD 0x707f 594 | #define MATCH_FSQ 0x4027 595 | #define MASK_FSQ 0x707f 596 | #define MATCH_FMADD_S 0x43 597 | #define MASK_FMADD_S 0x600007f 598 | #define MATCH_FMSUB_S 0x47 599 | #define MASK_FMSUB_S 0x600007f 600 | #define MATCH_FNMSUB_S 0x4b 601 | #define MASK_FNMSUB_S 0x600007f 602 | #define MATCH_FNMADD_S 0x4f 603 | #define MASK_FNMADD_S 0x600007f 604 | #define MATCH_FMADD_D 0x2000043 605 | #define MASK_FMADD_D 0x600007f 606 | #define MATCH_FMSUB_D 0x2000047 607 | #define MASK_FMSUB_D 0x600007f 608 | #define MATCH_FNMSUB_D 0x200004b 609 | #define MASK_FNMSUB_D 0x600007f 610 | #define MATCH_FNMADD_D 0x200004f 611 | #define MASK_FNMADD_D 0x600007f 612 | #define MATCH_FMADD_Q 0x6000043 613 | #define MASK_FMADD_Q 0x600007f 614 | #define MATCH_FMSUB_Q 0x6000047 615 | #define MASK_FMSUB_Q 0x600007f 616 | #define MATCH_FNMSUB_Q 0x600004b 617 | #define MASK_FNMSUB_Q 0x600007f 618 | #define MATCH_FNMADD_Q 0x600004f 619 | #define MASK_FNMADD_Q 0x600007f 620 | #define MATCH_C_NOP 0x1 621 | #define MASK_C_NOP 0xffff 622 | #define MATCH_C_ADDI16SP 0x6101 623 | #define MASK_C_ADDI16SP 0xef83 624 | #define MATCH_C_JR 0x8002 625 | #define MASK_C_JR 0xf07f 626 | #define MATCH_C_JALR 0x9002 627 | #define MASK_C_JALR 0xf07f 628 | #define MATCH_C_EBREAK 0x9002 629 | #define MASK_C_EBREAK 0xffff 630 | #define MATCH_C_LD 0x6000 631 | #define MASK_C_LD 0xe003 632 | #define MATCH_C_SD 0xe000 633 | #define MASK_C_SD 0xe003 634 | #define MATCH_C_ADDIW 0x2001 635 | #define MASK_C_ADDIW 0xe003 636 | #define MATCH_C_LDSP 0x6002 637 | #define MASK_C_LDSP 0xe003 638 | #define MATCH_C_SDSP 0xe002 639 | #define MASK_C_SDSP 0xe003 640 | #define MATCH_C_ADDI4SPN 0x0 641 | #define MASK_C_ADDI4SPN 0xe003 642 | #define MATCH_C_FLD 0x2000 643 | #define MASK_C_FLD 0xe003 644 | #define MATCH_C_LW 0x4000 645 | #define MASK_C_LW 0xe003 646 | #define MATCH_C_FLW 0x6000 647 | #define MASK_C_FLW 0xe003 648 | #define MATCH_C_FSD 0xa000 649 | #define MASK_C_FSD 0xe003 650 | #define MATCH_C_SW 0xc000 651 | #define MASK_C_SW 0xe003 652 | #define MATCH_C_FSW 0xe000 653 | #define MASK_C_FSW 0xe003 654 | #define MATCH_C_ADDI 0x1 655 | #define MASK_C_ADDI 0xe003 656 | #define MATCH_C_JAL 0x2001 657 | #define MASK_C_JAL 0xe003 658 | #define MATCH_C_LI 0x4001 659 | #define MASK_C_LI 0xe003 660 | #define MATCH_C_LUI 0x6001 661 | #define MASK_C_LUI 0xe003 662 | #define MATCH_C_SRLI 0x8001 663 | #define MASK_C_SRLI 0xec03 664 | #define MATCH_C_SRAI 0x8401 665 | #define MASK_C_SRAI 0xec03 666 | #define MATCH_C_ANDI 0x8801 667 | #define MASK_C_ANDI 0xec03 668 | #define MATCH_C_SUB 0x8c01 669 | #define MASK_C_SUB 0xfc63 670 | #define MATCH_C_XOR 0x8c21 671 | #define MASK_C_XOR 0xfc63 672 | #define MATCH_C_OR 0x8c41 673 | #define MASK_C_OR 0xfc63 674 | #define MATCH_C_AND 0x8c61 675 | #define MASK_C_AND 0xfc63 676 | #define MATCH_C_SUBW 0x9c01 677 | #define MASK_C_SUBW 0xfc63 678 | #define MATCH_C_ADDW 0x9c21 679 | #define MASK_C_ADDW 0xfc63 680 | #define MATCH_C_J 0xa001 681 | #define MASK_C_J 0xe003 682 | #define MATCH_C_BEQZ 0xc001 683 | #define MASK_C_BEQZ 0xe003 684 | #define MATCH_C_BNEZ 0xe001 685 | #define MASK_C_BNEZ 0xe003 686 | #define MATCH_C_SLLI 0x2 687 | #define MASK_C_SLLI 0xe003 688 | #define MATCH_C_FLDSP 0x2002 689 | #define MASK_C_FLDSP 0xe003 690 | #define MATCH_C_LWSP 0x4002 691 | #define MASK_C_LWSP 0xe003 692 | #define MATCH_C_FLWSP 0x6002 693 | #define MASK_C_FLWSP 0xe003 694 | #define MATCH_C_MV 0x8002 695 | #define MASK_C_MV 0xf003 696 | #define MATCH_C_ADD 0x9002 697 | #define MASK_C_ADD 0xf003 698 | #define MATCH_C_FSDSP 0xa002 699 | #define MASK_C_FSDSP 0xe003 700 | #define MATCH_C_SWSP 0xc002 701 | #define MASK_C_SWSP 0xe003 702 | #define MATCH_C_FSWSP 0xe002 703 | #define MASK_C_FSWSP 0xe003 704 | #define MATCH_CUSTOM0 0xb 705 | #define MASK_CUSTOM0 0x707f 706 | #define MATCH_CUSTOM0_RS1 0x200b 707 | #define MASK_CUSTOM0_RS1 0x707f 708 | #define MATCH_CUSTOM0_RS1_RS2 0x300b 709 | #define MASK_CUSTOM0_RS1_RS2 0x707f 710 | #define MATCH_CUSTOM0_RD 0x400b 711 | #define MASK_CUSTOM0_RD 0x707f 712 | #define MATCH_CUSTOM0_RD_RS1 0x600b 713 | #define MASK_CUSTOM0_RD_RS1 0x707f 714 | #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b 715 | #define MASK_CUSTOM0_RD_RS1_RS2 0x707f 716 | #define MATCH_CUSTOM1 0x2b 717 | #define MASK_CUSTOM1 0x707f 718 | #define MATCH_CUSTOM1_RS1 0x202b 719 | #define MASK_CUSTOM1_RS1 0x707f 720 | #define MATCH_CUSTOM1_RS1_RS2 0x302b 721 | #define MASK_CUSTOM1_RS1_RS2 0x707f 722 | #define MATCH_CUSTOM1_RD 0x402b 723 | #define MASK_CUSTOM1_RD 0x707f 724 | #define MATCH_CUSTOM1_RD_RS1 0x602b 725 | #define MASK_CUSTOM1_RD_RS1 0x707f 726 | #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b 727 | #define MASK_CUSTOM1_RD_RS1_RS2 0x707f 728 | #define MATCH_CUSTOM2 0x5b 729 | #define MASK_CUSTOM2 0x707f 730 | #define MATCH_CUSTOM2_RS1 0x205b 731 | #define MASK_CUSTOM2_RS1 0x707f 732 | #define MATCH_CUSTOM2_RS1_RS2 0x305b 733 | #define MASK_CUSTOM2_RS1_RS2 0x707f 734 | #define MATCH_CUSTOM2_RD 0x405b 735 | #define MASK_CUSTOM2_RD 0x707f 736 | #define MATCH_CUSTOM2_RD_RS1 0x605b 737 | #define MASK_CUSTOM2_RD_RS1 0x707f 738 | #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b 739 | #define MASK_CUSTOM2_RD_RS1_RS2 0x707f 740 | #define MATCH_CUSTOM3 0x7b 741 | #define MASK_CUSTOM3 0x707f 742 | #define MATCH_CUSTOM3_RS1 0x207b 743 | #define MASK_CUSTOM3_RS1 0x707f 744 | #define MATCH_CUSTOM3_RS1_RS2 0x307b 745 | #define MASK_CUSTOM3_RS1_RS2 0x707f 746 | #define MATCH_CUSTOM3_RD 0x407b 747 | #define MASK_CUSTOM3_RD 0x707f 748 | #define MATCH_CUSTOM3_RD_RS1 0x607b 749 | #define MASK_CUSTOM3_RD_RS1 0x707f 750 | #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b 751 | #define MASK_CUSTOM3_RD_RS1_RS2 0x707f 752 | #define CSR_FFLAGS 0x1 753 | #define CSR_FRM 0x2 754 | #define CSR_FCSR 0x3 755 | #define CSR_CYCLE 0xc00 756 | #define CSR_TIME 0xc01 757 | #define CSR_INSTRET 0xc02 758 | #define CSR_HPMCOUNTER3 0xc03 759 | #define CSR_HPMCOUNTER4 0xc04 760 | #define CSR_HPMCOUNTER5 0xc05 761 | #define CSR_HPMCOUNTER6 0xc06 762 | #define CSR_HPMCOUNTER7 0xc07 763 | #define CSR_HPMCOUNTER8 0xc08 764 | #define CSR_HPMCOUNTER9 0xc09 765 | #define CSR_HPMCOUNTER10 0xc0a 766 | #define CSR_HPMCOUNTER11 0xc0b 767 | #define CSR_HPMCOUNTER12 0xc0c 768 | #define CSR_HPMCOUNTER13 0xc0d 769 | #define CSR_HPMCOUNTER14 0xc0e 770 | #define CSR_HPMCOUNTER15 0xc0f 771 | #define CSR_HPMCOUNTER16 0xc10 772 | #define CSR_HPMCOUNTER17 0xc11 773 | #define CSR_HPMCOUNTER18 0xc12 774 | #define CSR_HPMCOUNTER19 0xc13 775 | #define CSR_HPMCOUNTER20 0xc14 776 | #define CSR_HPMCOUNTER21 0xc15 777 | #define CSR_HPMCOUNTER22 0xc16 778 | #define CSR_HPMCOUNTER23 0xc17 779 | #define CSR_HPMCOUNTER24 0xc18 780 | #define CSR_HPMCOUNTER25 0xc19 781 | #define CSR_HPMCOUNTER26 0xc1a 782 | #define CSR_HPMCOUNTER27 0xc1b 783 | #define CSR_HPMCOUNTER28 0xc1c 784 | #define CSR_HPMCOUNTER29 0xc1d 785 | #define CSR_HPMCOUNTER30 0xc1e 786 | #define CSR_HPMCOUNTER31 0xc1f 787 | #define CSR_SSTATUS 0x100 788 | #define CSR_SIE 0x104 789 | #define CSR_STVEC 0x105 790 | #define CSR_SCOUNTEREN 0x106 791 | #define CSR_SSCRATCH 0x140 792 | #define CSR_SEPC 0x141 793 | #define CSR_SCAUSE 0x142 794 | #define CSR_STVAL 0x143 795 | #define CSR_SIP 0x144 796 | #define CSR_SATP 0x180 797 | #define CSR_MSTATUS 0x300 798 | #define CSR_MISA 0x301 799 | #define CSR_MEDELEG 0x302 800 | #define CSR_MIDELEG 0x303 801 | #define CSR_MIE 0x304 802 | #define CSR_MTVEC 0x305 803 | #define CSR_MCOUNTEREN 0x306 804 | #define CSR_MSCRATCH 0x340 805 | #define CSR_MEPC 0x341 806 | #define CSR_MCAUSE 0x342 807 | #define CSR_MTVAL 0x343 808 | #define CSR_MIP 0x344 809 | #define CSR_PMPCFG0 0x3a0 810 | #define CSR_PMPCFG1 0x3a1 811 | #define CSR_PMPCFG2 0x3a2 812 | #define CSR_PMPCFG3 0x3a3 813 | #define CSR_PMPADDR0 0x3b0 814 | #define CSR_PMPADDR1 0x3b1 815 | #define CSR_PMPADDR2 0x3b2 816 | #define CSR_PMPADDR3 0x3b3 817 | #define CSR_PMPADDR4 0x3b4 818 | #define CSR_PMPADDR5 0x3b5 819 | #define CSR_PMPADDR6 0x3b6 820 | #define CSR_PMPADDR7 0x3b7 821 | #define CSR_PMPADDR8 0x3b8 822 | #define CSR_PMPADDR9 0x3b9 823 | #define CSR_PMPADDR10 0x3ba 824 | #define CSR_PMPADDR11 0x3bb 825 | #define CSR_PMPADDR12 0x3bc 826 | #define CSR_PMPADDR13 0x3bd 827 | #define CSR_PMPADDR14 0x3be 828 | #define CSR_PMPADDR15 0x3bf 829 | #define CSR_TSELECT 0x7a0 830 | #define CSR_TDATA1 0x7a1 831 | #define CSR_TDATA2 0x7a2 832 | #define CSR_TDATA3 0x7a3 833 | #define CSR_DCSR 0x7b0 834 | #define CSR_DPC 0x7b1 835 | #define CSR_DSCRATCH 0x7b2 836 | #define CSR_MCYCLE 0xb00 837 | #define CSR_MINSTRET 0xb02 838 | #define CSR_MHPMCOUNTER3 0xb03 839 | #define CSR_MHPMCOUNTER4 0xb04 840 | #define CSR_MHPMCOUNTER5 0xb05 841 | #define CSR_MHPMCOUNTER6 0xb06 842 | #define CSR_MHPMCOUNTER7 0xb07 843 | #define CSR_MHPMCOUNTER8 0xb08 844 | #define CSR_MHPMCOUNTER9 0xb09 845 | #define CSR_MHPMCOUNTER10 0xb0a 846 | #define CSR_MHPMCOUNTER11 0xb0b 847 | #define CSR_MHPMCOUNTER12 0xb0c 848 | #define CSR_MHPMCOUNTER13 0xb0d 849 | #define CSR_MHPMCOUNTER14 0xb0e 850 | #define CSR_MHPMCOUNTER15 0xb0f 851 | #define CSR_MHPMCOUNTER16 0xb10 852 | #define CSR_MHPMCOUNTER17 0xb11 853 | #define CSR_MHPMCOUNTER18 0xb12 854 | #define CSR_MHPMCOUNTER19 0xb13 855 | #define CSR_MHPMCOUNTER20 0xb14 856 | #define CSR_MHPMCOUNTER21 0xb15 857 | #define CSR_MHPMCOUNTER22 0xb16 858 | #define CSR_MHPMCOUNTER23 0xb17 859 | #define CSR_MHPMCOUNTER24 0xb18 860 | #define CSR_MHPMCOUNTER25 0xb19 861 | #define CSR_MHPMCOUNTER26 0xb1a 862 | #define CSR_MHPMCOUNTER27 0xb1b 863 | #define CSR_MHPMCOUNTER28 0xb1c 864 | #define CSR_MHPMCOUNTER29 0xb1d 865 | #define CSR_MHPMCOUNTER30 0xb1e 866 | #define CSR_MHPMCOUNTER31 0xb1f 867 | #define CSR_MHPMEVENT3 0x323 868 | #define CSR_MHPMEVENT4 0x324 869 | #define CSR_MHPMEVENT5 0x325 870 | #define CSR_MHPMEVENT6 0x326 871 | #define CSR_MHPMEVENT7 0x327 872 | #define CSR_MHPMEVENT8 0x328 873 | #define CSR_MHPMEVENT9 0x329 874 | #define CSR_MHPMEVENT10 0x32a 875 | #define CSR_MHPMEVENT11 0x32b 876 | #define CSR_MHPMEVENT12 0x32c 877 | #define CSR_MHPMEVENT13 0x32d 878 | #define CSR_MHPMEVENT14 0x32e 879 | #define CSR_MHPMEVENT15 0x32f 880 | #define CSR_MHPMEVENT16 0x330 881 | #define CSR_MHPMEVENT17 0x331 882 | #define CSR_MHPMEVENT18 0x332 883 | #define CSR_MHPMEVENT19 0x333 884 | #define CSR_MHPMEVENT20 0x334 885 | #define CSR_MHPMEVENT21 0x335 886 | #define CSR_MHPMEVENT22 0x336 887 | #define CSR_MHPMEVENT23 0x337 888 | #define CSR_MHPMEVENT24 0x338 889 | #define CSR_MHPMEVENT25 0x339 890 | #define CSR_MHPMEVENT26 0x33a 891 | #define CSR_MHPMEVENT27 0x33b 892 | #define CSR_MHPMEVENT28 0x33c 893 | #define CSR_MHPMEVENT29 0x33d 894 | #define CSR_MHPMEVENT30 0x33e 895 | #define CSR_MHPMEVENT31 0x33f 896 | #define CSR_MVENDORID 0xf11 897 | #define CSR_MARCHID 0xf12 898 | #define CSR_MIMPID 0xf13 899 | #define CSR_MHARTID 0xf14 900 | #define CSR_CYCLEH 0xc80 901 | #define CSR_TIMEH 0xc81 902 | #define CSR_INSTRETH 0xc82 903 | #define CSR_HPMCOUNTER3H 0xc83 904 | #define CSR_HPMCOUNTER4H 0xc84 905 | #define CSR_HPMCOUNTER5H 0xc85 906 | #define CSR_HPMCOUNTER6H 0xc86 907 | #define CSR_HPMCOUNTER7H 0xc87 908 | #define CSR_HPMCOUNTER8H 0xc88 909 | #define CSR_HPMCOUNTER9H 0xc89 910 | #define CSR_HPMCOUNTER10H 0xc8a 911 | #define CSR_HPMCOUNTER11H 0xc8b 912 | #define CSR_HPMCOUNTER12H 0xc8c 913 | #define CSR_HPMCOUNTER13H 0xc8d 914 | #define CSR_HPMCOUNTER14H 0xc8e 915 | #define CSR_HPMCOUNTER15H 0xc8f 916 | #define CSR_HPMCOUNTER16H 0xc90 917 | #define CSR_HPMCOUNTER17H 0xc91 918 | #define CSR_HPMCOUNTER18H 0xc92 919 | #define CSR_HPMCOUNTER19H 0xc93 920 | #define CSR_HPMCOUNTER20H 0xc94 921 | #define CSR_HPMCOUNTER21H 0xc95 922 | #define CSR_HPMCOUNTER22H 0xc96 923 | #define CSR_HPMCOUNTER23H 0xc97 924 | #define CSR_HPMCOUNTER24H 0xc98 925 | #define CSR_HPMCOUNTER25H 0xc99 926 | #define CSR_HPMCOUNTER26H 0xc9a 927 | #define CSR_HPMCOUNTER27H 0xc9b 928 | #define CSR_HPMCOUNTER28H 0xc9c 929 | #define CSR_HPMCOUNTER29H 0xc9d 930 | #define CSR_HPMCOUNTER30H 0xc9e 931 | #define CSR_HPMCOUNTER31H 0xc9f 932 | #define CSR_MCYCLEH 0xb80 933 | #define CSR_MINSTRETH 0xb82 934 | #define CSR_MHPMCOUNTER3H 0xb83 935 | #define CSR_MHPMCOUNTER4H 0xb84 936 | #define CSR_MHPMCOUNTER5H 0xb85 937 | #define CSR_MHPMCOUNTER6H 0xb86 938 | #define CSR_MHPMCOUNTER7H 0xb87 939 | #define CSR_MHPMCOUNTER8H 0xb88 940 | #define CSR_MHPMCOUNTER9H 0xb89 941 | #define CSR_MHPMCOUNTER10H 0xb8a 942 | #define CSR_MHPMCOUNTER11H 0xb8b 943 | #define CSR_MHPMCOUNTER12H 0xb8c 944 | #define CSR_MHPMCOUNTER13H 0xb8d 945 | #define CSR_MHPMCOUNTER14H 0xb8e 946 | #define CSR_MHPMCOUNTER15H 0xb8f 947 | #define CSR_MHPMCOUNTER16H 0xb90 948 | #define CSR_MHPMCOUNTER17H 0xb91 949 | #define CSR_MHPMCOUNTER18H 0xb92 950 | #define CSR_MHPMCOUNTER19H 0xb93 951 | #define CSR_MHPMCOUNTER20H 0xb94 952 | #define CSR_MHPMCOUNTER21H 0xb95 953 | #define CSR_MHPMCOUNTER22H 0xb96 954 | #define CSR_MHPMCOUNTER23H 0xb97 955 | #define CSR_MHPMCOUNTER24H 0xb98 956 | #define CSR_MHPMCOUNTER25H 0xb99 957 | #define CSR_MHPMCOUNTER26H 0xb9a 958 | #define CSR_MHPMCOUNTER27H 0xb9b 959 | #define CSR_MHPMCOUNTER28H 0xb9c 960 | #define CSR_MHPMCOUNTER29H 0xb9d 961 | #define CSR_MHPMCOUNTER30H 0xb9e 962 | #define CSR_MHPMCOUNTER31H 0xb9f 963 | #define CAUSE_MISALIGNED_FETCH 0x0 964 | #define CAUSE_FETCH_ACCESS 0x1 965 | #define CAUSE_ILLEGAL_INSTRUCTION 0x2 966 | #define CAUSE_BREAKPOINT 0x3 967 | #define CAUSE_MISALIGNED_LOAD 0x4 968 | #define CAUSE_LOAD_ACCESS 0x5 969 | #define CAUSE_MISALIGNED_STORE 0x6 970 | #define CAUSE_STORE_ACCESS 0x7 971 | #define CAUSE_USER_ECALL 0x8 972 | #define CAUSE_SUPERVISOR_ECALL 0x9 973 | #define CAUSE_HYPERVISOR_ECALL 0xa 974 | #define CAUSE_MACHINE_ECALL 0xb 975 | #define CAUSE_FETCH_PAGE_FAULT 0xc 976 | #define CAUSE_LOAD_PAGE_FAULT 0xd 977 | #define CAUSE_STORE_PAGE_FAULT 0xf 978 | #endif 979 | #ifdef DECLARE_INSN 980 | DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) 981 | DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) 982 | DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) 983 | DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) 984 | DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) 985 | DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) 986 | DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) 987 | DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) 988 | DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) 989 | DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) 990 | DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) 991 | DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) 992 | DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) 993 | DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) 994 | DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) 995 | DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) 996 | DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) 997 | DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) 998 | DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) 999 | DECLARE_INSN(add, MATCH_ADD, MASK_ADD) 1000 | DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) 1001 | DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) 1002 | DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) 1003 | DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) 1004 | DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) 1005 | DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) 1006 | DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) 1007 | DECLARE_INSN(or, MATCH_OR, MASK_OR) 1008 | DECLARE_INSN(and, MATCH_AND, MASK_AND) 1009 | DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) 1010 | DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) 1011 | DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) 1012 | DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) 1013 | DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) 1014 | DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) 1015 | DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) 1016 | DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) 1017 | DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) 1018 | DECLARE_INSN(lb, MATCH_LB, MASK_LB) 1019 | DECLARE_INSN(lh, MATCH_LH, MASK_LH) 1020 | DECLARE_INSN(lw, MATCH_LW, MASK_LW) 1021 | DECLARE_INSN(ld, MATCH_LD, MASK_LD) 1022 | DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) 1023 | DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) 1024 | DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) 1025 | DECLARE_INSN(sb, MATCH_SB, MASK_SB) 1026 | DECLARE_INSN(sh, MATCH_SH, MASK_SH) 1027 | DECLARE_INSN(sw, MATCH_SW, MASK_SW) 1028 | DECLARE_INSN(sd, MATCH_SD, MASK_SD) 1029 | DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) 1030 | DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) 1031 | DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) 1032 | DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) 1033 | DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) 1034 | DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) 1035 | DECLARE_INSN(div, MATCH_DIV, MASK_DIV) 1036 | DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) 1037 | DECLARE_INSN(rem, MATCH_REM, MASK_REM) 1038 | DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) 1039 | DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) 1040 | DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) 1041 | DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) 1042 | DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) 1043 | DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) 1044 | DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) 1045 | DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) 1046 | DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) 1047 | DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) 1048 | DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) 1049 | DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) 1050 | DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) 1051 | DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) 1052 | DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) 1053 | DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) 1054 | DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) 1055 | DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) 1056 | DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) 1057 | DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) 1058 | DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) 1059 | DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) 1060 | DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) 1061 | DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) 1062 | DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) 1063 | DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) 1064 | DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) 1065 | DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) 1066 | DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) 1067 | DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) 1068 | DECLARE_INSN(uret, MATCH_URET, MASK_URET) 1069 | DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) 1070 | DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) 1071 | DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) 1072 | DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA) 1073 | DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) 1074 | DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) 1075 | DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) 1076 | DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) 1077 | DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) 1078 | DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) 1079 | DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) 1080 | DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) 1081 | DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) 1082 | DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) 1083 | DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) 1084 | DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) 1085 | DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) 1086 | DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) 1087 | DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) 1088 | DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) 1089 | DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) 1090 | DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) 1091 | DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) 1092 | DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) 1093 | DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) 1094 | DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) 1095 | DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) 1096 | DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) 1097 | DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) 1098 | DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) 1099 | DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) 1100 | DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) 1101 | DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) 1102 | DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q) 1103 | DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q) 1104 | DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q) 1105 | DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q) 1106 | DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q) 1107 | DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q) 1108 | DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q) 1109 | DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q) 1110 | DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q) 1111 | DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q) 1112 | DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S) 1113 | DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q) 1114 | DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D) 1115 | DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q) 1116 | DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) 1117 | DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) 1118 | DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) 1119 | DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) 1120 | DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) 1121 | DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) 1122 | DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q) 1123 | DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q) 1124 | DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q) 1125 | DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) 1126 | DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) 1127 | DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) 1128 | DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) 1129 | DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W) 1130 | DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) 1131 | DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) 1132 | DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) 1133 | DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) 1134 | DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) 1135 | DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) 1136 | DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) 1137 | DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q) 1138 | DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q) 1139 | DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q) 1140 | DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q) 1141 | DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q) 1142 | DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q) 1143 | DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) 1144 | DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) 1145 | DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) 1146 | DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) 1147 | DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X) 1148 | DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) 1149 | DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) 1150 | DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) 1151 | DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) 1152 | DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) 1153 | DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W) 1154 | DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU) 1155 | DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L) 1156 | DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU) 1157 | DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X) 1158 | DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) 1159 | DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) 1160 | DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ) 1161 | DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) 1162 | DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) 1163 | DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ) 1164 | DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) 1165 | DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) 1166 | DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) 1167 | DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) 1168 | DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) 1169 | DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) 1170 | DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) 1171 | DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) 1172 | DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q) 1173 | DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q) 1174 | DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q) 1175 | DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q) 1176 | DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) 1177 | DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) 1178 | DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) 1179 | DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) 1180 | DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) 1181 | DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) 1182 | DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) 1183 | DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) 1184 | DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) 1185 | DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) 1186 | DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) 1187 | DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) 1188 | DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) 1189 | DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) 1190 | DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) 1191 | DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) 1192 | DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) 1193 | DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) 1194 | DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) 1195 | DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) 1196 | DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) 1197 | DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) 1198 | DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) 1199 | DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) 1200 | DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) 1201 | DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) 1202 | DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) 1203 | DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) 1204 | DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) 1205 | DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) 1206 | DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) 1207 | DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) 1208 | DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) 1209 | DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) 1210 | DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) 1211 | DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) 1212 | DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) 1213 | DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) 1214 | DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) 1215 | DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) 1216 | DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) 1217 | DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) 1218 | DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) 1219 | DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) 1220 | DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) 1221 | DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) 1222 | DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) 1223 | DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2) 1224 | DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) 1225 | DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) 1226 | DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) 1227 | DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) 1228 | DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) 1229 | DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2) 1230 | DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) 1231 | DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) 1232 | DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) 1233 | DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) 1234 | DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) 1235 | DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2) 1236 | DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) 1237 | DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) 1238 | DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) 1239 | DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) 1240 | DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) 1241 | DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) 1242 | #endif 1243 | #ifdef DECLARE_CSR 1244 | DECLARE_CSR(fflags, CSR_FFLAGS) 1245 | DECLARE_CSR(frm, CSR_FRM) 1246 | DECLARE_CSR(fcsr, CSR_FCSR) 1247 | DECLARE_CSR(cycle, CSR_CYCLE) 1248 | DECLARE_CSR(time, CSR_TIME) 1249 | DECLARE_CSR(instret, CSR_INSTRET) 1250 | DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) 1251 | DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) 1252 | DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) 1253 | DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) 1254 | DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) 1255 | DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) 1256 | DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) 1257 | DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) 1258 | DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) 1259 | DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) 1260 | DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) 1261 | DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) 1262 | DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) 1263 | DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) 1264 | DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) 1265 | DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) 1266 | DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) 1267 | DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) 1268 | DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) 1269 | DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) 1270 | DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) 1271 | DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) 1272 | DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) 1273 | DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) 1274 | DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) 1275 | DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) 1276 | DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) 1277 | DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) 1278 | DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) 1279 | DECLARE_CSR(sstatus, CSR_SSTATUS) 1280 | DECLARE_CSR(sie, CSR_SIE) 1281 | DECLARE_CSR(stvec, CSR_STVEC) 1282 | DECLARE_CSR(scounteren, CSR_SCOUNTEREN) 1283 | DECLARE_CSR(sscratch, CSR_SSCRATCH) 1284 | DECLARE_CSR(sepc, CSR_SEPC) 1285 | DECLARE_CSR(scause, CSR_SCAUSE) 1286 | DECLARE_CSR(stval, CSR_STVAL) 1287 | DECLARE_CSR(sip, CSR_SIP) 1288 | DECLARE_CSR(satp, CSR_SATP) 1289 | DECLARE_CSR(mstatus, CSR_MSTATUS) 1290 | DECLARE_CSR(misa, CSR_MISA) 1291 | DECLARE_CSR(medeleg, CSR_MEDELEG) 1292 | DECLARE_CSR(mideleg, CSR_MIDELEG) 1293 | DECLARE_CSR(mie, CSR_MIE) 1294 | DECLARE_CSR(mtvec, CSR_MTVEC) 1295 | DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) 1296 | DECLARE_CSR(mscratch, CSR_MSCRATCH) 1297 | DECLARE_CSR(mepc, CSR_MEPC) 1298 | DECLARE_CSR(mcause, CSR_MCAUSE) 1299 | DECLARE_CSR(mtval, CSR_MTVAL) 1300 | DECLARE_CSR(mip, CSR_MIP) 1301 | DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) 1302 | DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) 1303 | DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) 1304 | DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) 1305 | DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) 1306 | DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) 1307 | DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) 1308 | DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) 1309 | DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) 1310 | DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) 1311 | DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) 1312 | DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) 1313 | DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) 1314 | DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) 1315 | DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) 1316 | DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) 1317 | DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) 1318 | DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) 1319 | DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) 1320 | DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) 1321 | DECLARE_CSR(tselect, CSR_TSELECT) 1322 | DECLARE_CSR(tdata1, CSR_TDATA1) 1323 | DECLARE_CSR(tdata2, CSR_TDATA2) 1324 | DECLARE_CSR(tdata3, CSR_TDATA3) 1325 | DECLARE_CSR(dcsr, CSR_DCSR) 1326 | DECLARE_CSR(dpc, CSR_DPC) 1327 | DECLARE_CSR(dscratch, CSR_DSCRATCH) 1328 | DECLARE_CSR(mcycle, CSR_MCYCLE) 1329 | DECLARE_CSR(minstret, CSR_MINSTRET) 1330 | DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) 1331 | DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) 1332 | DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) 1333 | DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) 1334 | DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) 1335 | DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) 1336 | DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) 1337 | DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) 1338 | DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) 1339 | DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) 1340 | DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) 1341 | DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) 1342 | DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) 1343 | DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) 1344 | DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) 1345 | DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) 1346 | DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) 1347 | DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) 1348 | DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) 1349 | DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) 1350 | DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) 1351 | DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) 1352 | DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) 1353 | DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) 1354 | DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) 1355 | DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) 1356 | DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) 1357 | DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) 1358 | DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) 1359 | DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) 1360 | DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) 1361 | DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) 1362 | DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) 1363 | DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) 1364 | DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) 1365 | DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) 1366 | DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) 1367 | DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) 1368 | DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) 1369 | DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) 1370 | DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) 1371 | DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) 1372 | DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) 1373 | DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) 1374 | DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) 1375 | DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) 1376 | DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) 1377 | DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) 1378 | DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) 1379 | DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) 1380 | DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) 1381 | DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) 1382 | DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) 1383 | DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) 1384 | DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) 1385 | DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) 1386 | DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) 1387 | DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) 1388 | DECLARE_CSR(mvendorid, CSR_MVENDORID) 1389 | DECLARE_CSR(marchid, CSR_MARCHID) 1390 | DECLARE_CSR(mimpid, CSR_MIMPID) 1391 | DECLARE_CSR(mhartid, CSR_MHARTID) 1392 | DECLARE_CSR(cycleh, CSR_CYCLEH) 1393 | DECLARE_CSR(timeh, CSR_TIMEH) 1394 | DECLARE_CSR(instreth, CSR_INSTRETH) 1395 | DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) 1396 | DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) 1397 | DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) 1398 | DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) 1399 | DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) 1400 | DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) 1401 | DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) 1402 | DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) 1403 | DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) 1404 | DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) 1405 | DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) 1406 | DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) 1407 | DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) 1408 | DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) 1409 | DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) 1410 | DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) 1411 | DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) 1412 | DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) 1413 | DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) 1414 | DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) 1415 | DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) 1416 | DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) 1417 | DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) 1418 | DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) 1419 | DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) 1420 | DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) 1421 | DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) 1422 | DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) 1423 | DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) 1424 | DECLARE_CSR(mcycleh, CSR_MCYCLEH) 1425 | DECLARE_CSR(minstreth, CSR_MINSTRETH) 1426 | DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) 1427 | DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) 1428 | DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) 1429 | DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) 1430 | DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) 1431 | DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) 1432 | DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) 1433 | DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) 1434 | DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) 1435 | DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) 1436 | DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) 1437 | DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) 1438 | DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) 1439 | DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) 1440 | DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) 1441 | DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) 1442 | DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) 1443 | DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) 1444 | DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) 1445 | DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) 1446 | DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) 1447 | DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) 1448 | DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) 1449 | DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) 1450 | DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) 1451 | DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) 1452 | DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) 1453 | DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) 1454 | DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) 1455 | #endif 1456 | #ifdef DECLARE_CAUSE 1457 | DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) 1458 | DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS) 1459 | DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) 1460 | DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) 1461 | DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) 1462 | DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS) 1463 | DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) 1464 | DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS) 1465 | DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) 1466 | DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) 1467 | DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) 1468 | DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) 1469 | DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT) 1470 | DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT) 1471 | DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT) 1472 | #endif 1473 | -------------------------------------------------------------------------------- /Test_WS/Eclipse.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | 3 | rem Pfad auf "Windows Build Tools" bekannt machen 4 | PATH L:\tools\xpack-windows-build-tools-4.2.1-2\bin;%PATH% 5 | rem Pfad zum Eclipse executable und zum gewuenschten Workspace setzen 6 | set ECLIPSE_PATH=L:\tools\eclipse-cpp-2020-09-R-win32-x86_64\eclipse 7 | set WORKSPACE=.\ 8 | %ECLIPSE_PATH%\eclipse.exe -data %WORKSPACE% 9 | -------------------------------------------------------------------------------- /Test_WS/First/.cproject: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | -------------------------------------------------------------------------------- /Test_WS/First/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | First 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | 11 | 12 | 13 | 14 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 15 | full,incremental, 16 | 17 | 18 | 19 | 20 | 21 | org.eclipse.cdt.core.cnature 22 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 23 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 24 | 25 | 26 | -------------------------------------------------------------------------------- /Test_WS/First/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | -------------------------------------------------------------------------------- /Test_WS/First/.settings/org.eclipse.cdt.core.prefs: -------------------------------------------------------------------------------- 1 | doxygen/doxygen_new_line_after_brief=true 2 | doxygen/doxygen_use_brief_tag=false 3 | doxygen/doxygen_use_javadoc_tags=true 4 | doxygen/doxygen_use_pre_tag=false 5 | doxygen/doxygen_use_structural_commands=false 6 | eclipse.preferences.version=1 7 | -------------------------------------------------------------------------------- /Test_WS/First/gdb_riscv32_serial.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin;%path% 2 | 3 | echo set debug remote 1 >gdb.x 4 | echo file Debug/First.elf >>gdb.x 5 | echo target extended-remote \\.\com6 >>gdb.x 6 | echo set serial baud 115200 >>gdb.x 7 | 8 | riscv-none-embed-gdb -x gdb.x 9 | del gdb.x 10 | pause -------------------------------------------------------------------------------- /Test_WS/First/postbuild.bat: -------------------------------------------------------------------------------- 1 | path L:\tools\xpack-riscv-none-embed-gcc-10.1.0-1.1\bin 2 | riscv-none-embed-objdump.exe -h -j.text -j.data -j.bss %1.elf 3 | riscv-none-embed-objdump.exe -h -t -j.text -j.data -j.bss -S %1.elf > %1_diss.txt 4 | riscv-none-embed-objcopy.exe -O ihex %1.elf %1.hex 5 | -------------------------------------------------------------------------------- /Test_WS/First/src/Boot.S: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------------------------------------------- 2 | // (c) Bernhard Lang, Hochschule Osnabrueck 3 | // ------------------------------------------------------------------------------------------- 4 | #include "riscv_csr_encoding.h" 5 | 6 | /* -------------------------------------------------------------- 7 | * Initial jump and vector table entries. 8 | ---------------------------------------------------------------- */ 9 | 10 | .section .vector_table,"ax",%progbits 11 | 12 | // entry point at startup with jump to startup code 13 | .global entrypoint 14 | .type entrypoint,@function 15 | entrypoint: 16 | j startup_code 17 | 18 | .org entrypoint+16 19 | // vector table 20 | .global vtable 21 | .type vtable, %object 22 | vtable: 23 | j exception_handler // vtable+0x00000000 24 | j supervisor_software_irhandler // vtable+0x00000004 25 | j default_handler // vtable+0x00000008 26 | j machine_software_irhandler // vtable+0x0000000c 27 | j user_timer_irhandler // vtable+0x00000010 28 | j supervisor_timer_irhandler // vtable+0x00000014 29 | j default_handler // vtable+0x00000018 30 | j machine_timer_irhandler // vtable+0x0000001c 31 | j user_external_irhandler // vtable+0x00000020 32 | j supervisor_external_irhandler // vtable+0x00000024 33 | j default_handler // vtable+0x00000028 34 | j machine_external_irhandler // vtable+0x0000002c 35 | j default_handler // vtable+0x00000030 36 | j default_handler // vtable+0x00000034 37 | j default_handler // vtable+0x00000038 38 | j default_handler // vtable+0x0000003c 39 | j LocalInt0_handler // vtable+0x00000040 40 | j LocalInt1_handler // vtable+0x00000044 41 | j LocalInt2_handler // vtable+0x00000048 42 | j LocalInt3_handler // vtable+0x0000004C 43 | j LocalInt4_handler // vtable+0x00000050 44 | j LocalInt5_handler // vtable+0x00000054 45 | j LocalInt6_handler // vtable+0x00000058 46 | j LocalInt7_handler // vtable+0x0000005C 47 | j LocalInt8_handler // vtable+0x00000060 48 | j LocalInt9_handler // vtable+0x00000064 49 | j LocalIntA_handler // vtable+0x00000068 50 | j LocalIntB_handler // vtable+0x0000006C 51 | j LocalIntC_handler // vtable+0x00000070 52 | j LocalIntD_handler // vtable+0x00000074 53 | j LocalIntE_handler // vtable+0x00000078 54 | j LocalIntF_handler // vtable+0x0000007C 55 | 56 | 57 | .section .text,"ax",%progbits 58 | 59 | /* -------------------------------------------------------------- 60 | * Assembly 'reset handler' function to initialize core CPU registers. 61 | ---------------------------------------------------------------- */ 62 | startup_code: 63 | 64 | // Disable interrupts until they are needed. 65 | csrc mstatus, (MSTATUS_MIE | MSTATUS_SIE | MSTATUS_UIE) 66 | // Activate vector table for interrupts. 67 | // csrs mtvec, 1 68 | // Load the initial stack pointer value. 69 | la sp, _sp 70 | // Call 'premain()' 71 | call premain 72 | // All other settings are done there 73 | // .data/.bss sections initialized there 74 | // At the end main is called 75 | 76 | // endless loop after unexpected premain return 77 | the_end: 78 | j the_end 79 | 80 | -------------------------------------------------------------------------------- /Test_WS/First/src/Linker.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_ARCH( "riscv" ) 2 | ENTRY( entrypoint ) 3 | 4 | MEMORY { 5 | FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 16K 6 | RAM (rwx) : ORIGIN = 0x00000000, LENGTH = 4K 7 | } 8 | 9 | SECTIONS { 10 | __stack_size = DEFINED(__stack_size) ? __stack_size : 1K; 11 | .vector_table : { 12 | KEEP (*(SORT_NONE(.vector_table))) 13 | } >FLASH 14 | 15 | .text : { 16 | *(.text .text.*) 17 | *(.text*) 18 | *(.rodata .rodata.*) 19 | *(.srodata .srodata.*) 20 | } >FLASH 21 | . = ALIGN(4); 22 | PROVIDE (__etext = .); 23 | PROVIDE (_etext = .); 24 | PROVIDE (etext = .); 25 | 26 | _sidata = .; 27 | .data : AT( _sidata ) { 28 | _sdata = .; 29 | *(.rdata) 30 | *(.data .data.*) 31 | *(.data*) 32 | *(.sdata .sdata.*) 33 | . = ALIGN(4); 34 | _edata = .; 35 | } >RAM 36 | PROVIDE( _edata = . ); 37 | PROVIDE( edata = . ); 38 | 39 | PROVIDE( _fbss = . ); 40 | PROVIDE( __bss_start = . ); 41 | .bss : { 42 | _sbss = .; 43 | *(.sbss*) 44 | *(.bss .bss.*) 45 | *(COMMON) 46 | . = ALIGN(4); 47 | _ebss = .; 48 | } >RAM 49 | . = ALIGN(8); 50 | PROVIDE( _end = . ); 51 | PROVIDE( end = . ); 52 | 53 | .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { 54 | PROVIDE( _heap_end = . ); 55 | . = __stack_size; 56 | PROVIDE( _sp = . ); 57 | } >RAM 58 | 59 | } -------------------------------------------------------------------------------- /Test_WS/First/src/interrupts.c: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------------------------------------------- 2 | // (c) Bernhard Lang, Hochschule Osnabrueck 3 | // ------------------------------------------------------------------------------------------- 4 | 5 | #include 6 | 7 | #include "interrupts.h" 8 | #include "riscv_csr_encoding.h" 9 | 10 | asm("\t.weak exception_handler\n \t.set exception_handler ,default_handler\n"); 11 | asm("\t.weak supervisor_software_irhandler\n\t.set supervisor_software_irhandler ,default_handler\n"); 12 | asm("\t.weak machine_software_irhandler\n \t.set machine_software_irhandler ,default_handler\n"); 13 | asm("\t.weak user_timer_irhandler\n \t.set user_timer_irhandler ,default_handler\n"); 14 | asm("\t.weak supervisor_timer_irhandler\n \t.set supervisor_timer_irhandler ,default_handler\n"); 15 | asm("\t.weak machine_timer_irhandler\n \t.set machine_timer_irhandler ,default_handler\n"); 16 | asm("\t.weak user_external_irhandler\n \t.set user_external_irhandler ,default_handler\n"); 17 | asm("\t.weak supervisor_external_irhandler\n\t.set supervisor_external_irhandler ,default_handler\n"); 18 | asm("\t.weak machine_external_irhandler\n \t.set machine_external_irhandler ,default_handler\n"); 19 | asm("\t.weak LocalInt0_handler\n \t.set LocalInt0_handler ,default_handler\n"); 20 | asm("\t.weak LocalInt1_handler\n \t.set LocalInt1_handler ,default_handler\n"); 21 | asm("\t.weak LocalInt2_handler\n \t.set LocalInt2_handler ,default_handler\n"); 22 | asm("\t.weak LocalInt3_handler\n \t.set LocalInt3_handler ,default_handler\n"); 23 | asm("\t.weak LocalInt4_handler\n \t.set LocalInt4_handler ,default_handler\n"); 24 | asm("\t.weak LocalInt5_handler\n \t.set LocalInt5_handler ,default_handler\n"); 25 | asm("\t.weak LocalInt6_handler\n \t.set LocalInt6_handler ,default_handler\n"); 26 | asm("\t.weak LocalInt7_handler\n \t.set LocalInt7_handler ,default_handler\n"); 27 | asm("\t.weak LocalInt8_handler\n \t.set LocalInt8_handler ,default_handler\n"); 28 | asm("\t.weak LocalInt9_handler\n \t.set LocalInt9_handler ,default_handler\n"); 29 | asm("\t.weak LocalIntA_handler\n \t.set LocalIntA_handler ,default_handler\n"); 30 | asm("\t.weak LocalIntB_handler\n \t.set LocalIntB_handler ,default_handler\n"); 31 | asm("\t.weak LocalIntC_handler\n \t.set LocalIntC_handler ,default_handler\n"); 32 | asm("\t.weak LocalIntD_handler\n \t.set LocalIntD_handler ,default_handler\n"); 33 | asm("\t.weak LocalIntE_handler\n \t.set LocalIntE_handler ,default_handler\n"); 34 | asm("\t.weak LocalIntF_handler\n \t.set LocalIntF_handler ,default_handler\n"); 35 | 36 | void __attribute__ ( (interrupt) ) default_handler (void) { 37 | uint32_t the_cause; 38 | the_cause = read_csr(mcause); 39 | while (1) {} 40 | } 41 | 42 | void __attribute__ ( (interrupt) ) exception_handler (void) { 43 | // handler code 44 | uint32_t the_cause; 45 | the_cause = read_csr(mcause); 46 | switch(the_cause) { 47 | case 0x0: break; // Instruction address misaligned 48 | case 0x1: break; // Instruction access fault 49 | case 0x2: break; // Illegal instruction 50 | case 0x3: break; // Breakpoint 51 | case 0x4: break; // Load address misaligned 52 | case 0x5: break; // Load access fault 53 | case 0x6: break; // Store/AMO address misaligned 54 | case 0x7: break; // Store/AMO access fault 55 | case 0x8: break; // Environment call from U-mode 56 | case 0x9: break; // Environment call from S-mode 57 | case 0xb: break; // Environment call from M-mode 58 | case 0xc: break; // Instruction page fault 59 | case 0xd: break; // Load page fault 60 | case 0xe: break; // Reserved for future standard use 61 | case 0xf: break; // Store/AMO page fault 62 | default: break; 63 | } 64 | } 65 | -------------------------------------------------------------------------------- /Test_WS/First/src/interrupts.h: -------------------------------------------------------------------------------- 1 | #ifndef interrupts_h 2 | #define interrupts_h 3 | 4 | void __attribute__ ( (interrupt) ) default_handler (void); 5 | void __attribute__ ( (interrupt) ) exception_handler (void); 6 | void __attribute__ ( (interrupt) ) supervisor_software_irhandler (void); 7 | void __attribute__ ( (interrupt) ) machine_software_irhandler (void); 8 | void __attribute__ ( (interrupt) ) user_timer_irhandler (void); 9 | void __attribute__ ( (interrupt) ) supervisor_timer_irhandler (void); 10 | void __attribute__ ( (interrupt) ) machine_timer_irhandler (void); 11 | void __attribute__ ( (interrupt) ) user_external_irhandler (void); 12 | void __attribute__ ( (interrupt) ) supervisor_external_irhandler (void); 13 | void __attribute__ ( (interrupt) ) machine_external_irhandler (void); 14 | 15 | void __attribute__ ( (interrupt) ) LocalInt0_handler (void); 16 | void __attribute__ ( (interrupt) ) LocalInt1_handler (void); 17 | void __attribute__ ( (interrupt) ) LocalInt2_handler (void); 18 | void __attribute__ ( (interrupt) ) LocalInt3_handler (void); 19 | void __attribute__ ( (interrupt) ) LocalInt4_handler (void); 20 | void __attribute__ ( (interrupt) ) LocalInt5_handler (void); 21 | void __attribute__ ( (interrupt) ) LocalInt6_handler (void); 22 | void __attribute__ ( (interrupt) ) LocalInt7_handler (void); 23 | void __attribute__ ( (interrupt) ) LocalInt8_handler (void); 24 | void __attribute__ ( (interrupt) ) LocalInt9_handler (void); 25 | void __attribute__ ( (interrupt) ) LocalIntA_handler (void); 26 | void __attribute__ ( (interrupt) ) LocalIntB_handler (void); 27 | void __attribute__ ( (interrupt) ) LocalIntC_handler (void); 28 | void __attribute__ ( (interrupt) ) LocalIntD_handler (void); 29 | void __attribute__ ( (interrupt) ) LocalIntE_handler (void); 30 | void __attribute__ ( (interrupt) ) LocalIntF_handler (void); 31 | 32 | #define IRQ_LOCAL_0 0x10 33 | #define IRQ_LOCAL_1 0x11 34 | #define IRQ_LOCAL_2 0x12 35 | #define IRQ_LOCAL_3 0x13 36 | #define IRQ_LOCAL_4 0x14 37 | #define IRQ_LOCAL_5 0x15 38 | #define IRQ_LOCAL_6 0x16 39 | #define IRQ_LOCAL_7 0x17 40 | #define IRQ_LOCAL_8 0x18 41 | #define IRQ_LOCAL_9 0x19 42 | #define IRQ_LOCAL_A 0x1A 43 | #define IRQ_LOCAL_B 0x1B 44 | #define IRQ_LOCAL_C 0x1C 45 | #define IRQ_LOCAL_D 0x1D 46 | #define IRQ_LOCAL_E 0x1E 47 | #define IRQ_LOCAL_F 0x1F 48 | 49 | #endif 50 | -------------------------------------------------------------------------------- /Test_WS/First/src/main.c: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------------------------------------------- 2 | // (c) Bernhard Lang, Hochschule Osnabrueck 3 | // ------------------------------------------------------------------------------------------- 4 | #include 5 | #include 6 | 7 | #include "riscv_csr_encoding.h" 8 | #include "interrupts.h" 9 | 10 | 11 | #define Read_Word(Address) (*(volatile uint32_t*)(Address)) 12 | #define Write_Word(Address,Value) {*((volatile uint32_t*)(Address))=Value;} 13 | 14 | #define GPIO0_BASE 0x8000 15 | #define GPIO1_BASE 0x8100 16 | #define GPIO_Dir 0x00 17 | #define GPIO_Dir_Set 0x04 18 | #define GPIO_Dir_Delete 0x08 19 | #define GPIO_Dir_Toggle 0x0c 20 | #define GPIO_Data 0x10 21 | #define GPIO_Data_Set 0x14 22 | #define GPIO_Data_Delete 0x18 23 | #define GPIO_Data_Toggle 0x1c 24 | #define GPIO_PIN 0x20 25 | 26 | #define TIMER0_BASE 0x8200 27 | #define TIMER1_BASE 0x8300 28 | #define TIMER_VALUE 0x00 29 | #define TIMER_START 0x04 30 | #define TIMER_STATUS 0x08 31 | 32 | volatile uint32_t timer_irs=0; 33 | volatile uint32_t timer_status; 34 | volatile uint32_t timer_value; 35 | 36 | void __attribute__ ( (interrupt) ) machine_timer_irhandler (void) { 37 | timer_status = Read_Word(TIMER0_BASE+TIMER_STATUS); // clear interrupt by reading timer status 38 | timer_irs++; 39 | } 40 | 41 | volatile uint32_t segments[4]; 42 | volatile uint32_t segment_counter; 43 | 44 | void __attribute__ ( (interrupt) ) LocalInt0_handler (void) { 45 | timer_status = Read_Word(TIMER1_BASE+TIMER_STATUS); // clear interrupt by reading timer status 46 | if (++segment_counter>3) { segment_counter=0; } 47 | Write_Word(GPIO1_BASE+GPIO_Data,segments[segment_counter]); 48 | } 49 | 50 | void set_digit(uint32_t value, uint32_t dp, uint32_t segment) { 51 | static uint32_t decode_tab[16] = {0x40,0x79,0x24,0x30,0x19,0x12,0x02,0x78,0x00,0x10,0x08,0x03,0x27,0x21,0x06,0x0e}; 52 | uint32_t sseg; 53 | if (value<16) { sseg = decode_tab[value]; } 54 | else { sseg = 0x7f; } 55 | if (segment<4) { segments[segment] = ((~(1<>4; 62 | dps = dps>>1; 63 | } 64 | } 65 | 66 | void write_LEDs(uint32_t value) { 67 | Write_Word(GPIO0_BASE+GPIO_Data,value); 68 | } 69 | 70 | uint32_t read_SWs() { 71 | return (Read_Word(GPIO0_BASE+GPIO_PIN)>>16) & 0xffff; 72 | } 73 | 74 | 75 | int main( void ) { 76 | volatile uint32_t counter =0; // Variable for endlessly increment 77 | 78 | // enable all machine interrupts in mstatus-register 79 | set_csr(mstatus,MSTATUS_MIE); // MSTATUS_SIE MSTATUS_UIE 80 | 81 | // Initialize GPIO0: lower 16 Bits are the LED outputs, upper 16 Bits are the switch inputs 82 | Write_Word(GPIO0_BASE+GPIO_Dir,0xffff); 83 | 84 | // Initialize GPIO1: lower 7 Bits are the Segment outputs, bit 7 is the dp output and Bits 8 to 11 are the anode outputs 85 | Write_Word(GPIO1_BASE+GPIO_Dir,0xfff); 86 | 87 | // Initialize Timer0 and enable timer interrupt 88 | Write_Word(TIMER0_BASE+TIMER_START,50000000-1); // At 50MHz generate interrupt each second 89 | set_csr(mie,(1 << IRQ_M_TIMER)); 90 | 91 | // Initialize Timer1 and enable timer interrupt 92 | Write_Word(TIMER1_BASE+TIMER_START,50000-1); // At 50MHz generate interrupt each millisecond 93 | set_csr(mie,(1 << IRQ_LOCAL_0)); 94 | //set_csr(mie,(1 << 16)); 95 | 96 | while ( 1 ) { 97 | timer_value = Read_Word(TIMER0_BASE+TIMER_VALUE); // only for debugging, value not used 98 | timer_value = Read_Word(TIMER1_BASE+TIMER_VALUE); // only for debugging, value not used 99 | counter++; // only for debugging, value not used 100 | 101 | set_display(timer_irs,(1<<0)); // set to SevenSeg display 102 | write_LEDs(read_SWs()); // read switches and write them to the LEDs 103 | } 104 | return 0; 105 | } 106 | -------------------------------------------------------------------------------- /Test_WS/First/src/premain.c: -------------------------------------------------------------------------------- 1 | // ------------------------------------------------------------------------------------------- 2 | // (c) Bernhard Lang, Hochschule Osnabrueck 3 | // ------------------------------------------------------------------------------------------- 4 | #include 5 | #include 6 | 7 | #include "riscv_csr_encoding.h" 8 | 9 | int main(); 10 | 11 | // Pre-defined memory locations for program initialization. 12 | extern uint32_t _sidata, _sdata, _edata, _sbss, _ebss; 13 | 14 | void premain() { 15 | uint8_t *src, *dst; 16 | size_t len; 17 | 18 | // Copy initialized data from .sidata (Flash) to .data (RAM) 19 | src = (uint8_t *)&_sidata; 20 | dst = (uint8_t *)&_sdata; 21 | while (dst < (uint8_t *)&_edata) 22 | *dst++ = *src++; 23 | 24 | // Clear the .bss RAM section. 25 | dst = (uint8_t *)&_sbss; 26 | while (dst < (uint8_t *)&_ebss) 27 | *dst++ = 0; 28 | 29 | main(); 30 | 31 | while(1) {} 32 | } 33 | -------------------------------------------------------------------------------- /UART_Sender_nur_Simulation.vhd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BLangOS/VexRiscV_with_HW-GDB_Server/0ad14e2525dee91ff13d483cc7ca1641e01bc7b2/UART_Sender_nur_Simulation.vhd -------------------------------------------------------------------------------- /VexRiscvWB_System.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- GDB_RSP_Debug for VexRiscV Project 3 | -- (c) Bernhard Lang, Hochschule Osnabrueck 4 | ---------------------------------------------------------------------------------------- 5 | library ieee; 6 | use ieee.std_logic_1164.all; 7 | use ieee.numeric_std.all; 8 | 9 | entity VexRiscvWB_System is 10 | port ( 11 | clk : in std_logic; 12 | reset : in std_logic; 13 | -- VexRiscV Debug Interface 14 | dbgbus_cmd_valid : in std_logic; 15 | dbgbus_cmd_payload_wr : in std_logic; 16 | dbgbus_cmd_payload_address : in unsigned(7 downto 0); 17 | dbgbus_cmd_payload_data : in std_logic_vector(31 downto 0); 18 | dbgbus_cmd_ready : out std_logic; 19 | dbgbus_rsp_data : out std_logic_vector(31 downto 0); 20 | CPU_Halted : in std_logic; 21 | -- GPIO 22 | GPIO0 : inout std_logic_vector(31 downto 0); 23 | GPIO1 : inout std_logic_vector(11 downto 0) 24 | ); 25 | end VexRiscvWB_System; 26 | 27 | architecture arch of VexRiscvWB_System is 28 | signal dBusWishbone_STB : std_logic; 29 | signal dBusWishbone_ACK : std_logic; 30 | signal dBusWishbone_WE : std_logic; 31 | signal dBusWishbone_ADR : unsigned(29 downto 0); 32 | signal dBusWishbone_DAT_MISO : std_logic_vector(31 downto 0); 33 | signal dBusWishbone_DAT_MOSI : std_logic_vector(31 downto 0); 34 | signal dBusWishbone_SEL : std_logic_vector(3 downto 0); 35 | -- 36 | signal iBusWishbone_STB : std_logic; 37 | signal iBusWishbone_ACK : std_logic; 38 | signal iBusWishbone_ADR : unsigned(29 downto 0); 39 | signal iBusWishbone_DAT_MISO : std_logic_vector(31 downto 0); 40 | -- 41 | signal SYS_STB : std_logic; 42 | signal SYS_ACK : std_logic; 43 | signal SYS_WE : std_logic; 44 | signal SYS_ADR_unsigned : unsigned(29 downto 0); 45 | signal SYS_ADR : std_logic_vector(31 downto 0); 46 | signal SYS_DAT_I : std_logic_vector(31 downto 0); 47 | signal SYS_DAT_O : std_logic_vector(31 downto 0); 48 | signal SYS_SEL : std_logic_vector(3 downto 0); 49 | -- 50 | signal SYS_RESET : std_logic; 51 | signal DBG_RESET : std_logic; 52 | -- Interrupt Lines 53 | signal Timer0_Interrupt : std_logic; 54 | signal Timer1_Interrupt : std_logic; 55 | begin 56 | -- 57 | SYS_RESET <= '1' when reset='1' else 58 | '1' when DBG_RESET='1' else 59 | '0'; 60 | CPU: entity work.VexRiscv 61 | port map ( 62 | clk => clk, -- : in std_logic; 63 | reset => SYS_RESET, -- : in std_logic; 64 | debugReset => reset, -- : in std_logic 65 | debug_resetOut => DBG_RESET, -- : out std_logic; 66 | -- 67 | LocalInt0 => Timer1_Interrupt, -- : in std_logic; 68 | LocalInt1 => '0', -- : in std_logic; 69 | LocalInt2 => '0', -- : in std_logic; 70 | LocalInt3 => '0', -- : in std_logic; 71 | timerInterrupt => Timer0_Interrupt, -- : in std_logic; 72 | externalInterrupt => '0', -- : in std_logic; 73 | softwareInterrupt => '0', -- : in std_logic; 74 | -- 75 | debug_bus_cmd_valid => dbgbus_cmd_valid, -- : in std_logic; 76 | debug_bus_cmd_ready => dbgbus_cmd_ready, -- : out std_logic; 77 | debug_bus_cmd_payload_wr => dbgbus_cmd_payload_wr, -- : in std_logic; 78 | debug_bus_cmd_payload_address => dbgbus_cmd_payload_address, -- : in unsigned(7 downto 0); 79 | debug_bus_cmd_payload_data => dbgbus_cmd_payload_data, -- : in std_logic_vector(31 downto 0); 80 | debug_bus_rsp_data => dbgbus_rsp_data, -- : out std_logic_vector(31 downto 0); 81 | -- 82 | iBusWishbone_CYC => open, -- : out std_logic; 83 | iBusWishbone_STB => iBusWishbone_STB, -- : out std_logic; 84 | iBusWishbone_ACK => iBusWishbone_ACK, -- : in std_logic; 85 | iBusWishbone_WE => open, -- : out std_logic; 86 | iBusWishbone_ADR => iBusWishbone_ADR, -- : out unsigned(29 downto 0); 87 | iBusWishbone_DAT_MISO => iBusWishbone_DAT_MISO, -- : in std_logic_vector(31 downto 0); 88 | iBusWishbone_DAT_MOSI => open, -- : out std_logic_vector(31 downto 0); 89 | iBusWishbone_SEL => open, -- : out std_logic_vector(3 downto 0); 90 | iBusWishbone_ERR => '0', -- : in std_logic; 91 | iBusWishbone_CTI => open, -- : out std_logic_vector(2 downto 0); 92 | iBusWishbone_BTE => open, -- : out std_logic_vector(1 downto 0); 93 | -- 94 | dBusWishbone_CYC => open, -- : out std_logic; 95 | dBusWishbone_STB => dBusWishbone_STB, -- : out std_logic; 96 | dBusWishbone_ACK => dBusWishbone_ACK, -- : in std_logic; 97 | dBusWishbone_WE => dBusWishbone_WE, -- : out std_logic; 98 | dBusWishbone_ADR => dBusWishbone_ADR, -- : out unsigned(29 downto 0); 99 | dBusWishbone_DAT_MISO => dBusWishbone_DAT_MISO, -- : in std_logic_vector(31 downto 0); 100 | dBusWishbone_DAT_MOSI => dBusWishbone_DAT_MOSI, -- : out std_logic_vector(31 downto 0); 101 | dBusWishbone_SEL => dBusWishbone_SEL, -- : out std_logic_vector(3 downto 0); 102 | dBusWishbone_ERR => '0', -- : in std_logic; 103 | dBusWishbone_CTI => open, -- : out std_logic_vector(2 downto 0); 104 | dBusWishbone_BTE => open -- : out std_logic_vector(1 downto 0); 105 | ); 106 | -- 107 | BUS_MUX: entity work.ibus_dbus_mux 108 | port map ( 109 | -- 110 | dBusWishbone_STB => dBusWishbone_STB, 111 | dBusWishbone_ACK => dBusWishbone_ACK, 112 | dBusWishbone_WE => dBusWishbone_WE, 113 | dBusWishbone_ADR => dBusWishbone_ADR, 114 | dBusWishbone_DAT_MISO => dBusWishbone_DAT_MISO, 115 | dBusWishbone_DAT_MOSI => dBusWishbone_DAT_MOSI, 116 | dBusWishbone_SEL => dBusWishbone_SEL, 117 | -- 118 | iBusWishbone_STB => iBusWishbone_STB, 119 | iBusWishbone_ACK => iBusWishbone_ACK, 120 | iBusWishbone_ADR => iBusWishbone_ADR, 121 | iBusWishbone_DAT_MISO => iBusWishbone_DAT_MISO, 122 | -- 123 | Wishbone_STB => SYS_STB, 124 | Wishbone_ACK => SYS_ACK, 125 | Wishbone_WE => SYS_WE, 126 | Wishbone_ADR => SYS_ADR_unsigned, 127 | Wishbone_DAT_MISO => SYS_DAT_I, 128 | Wishbone_DAT_MOSI => SYS_DAT_O, 129 | Wishbone_SEL => SYS_SEL 130 | ); 131 | SYS_ADR <= std_logic_vector(SYS_ADR_unsigned)&"00"; 132 | ------------------------------------------------------------ 133 | -- Wishbone Interconnect 134 | ------------------------------------------------------------ 135 | intercon_block: block is 136 | signal ROM_STB : std_logic; 137 | signal ROM_WE : std_logic; 138 | signal ROM_ACK : std_logic; 139 | signal ROM_DAT_O : std_logic_vector(31 downto 0); 140 | 141 | signal RAM_STB : std_logic; 142 | signal RAM_ACK : std_logic; 143 | signal RAM_DAT_O : std_logic_vector(31 downto 0); 144 | 145 | signal GPIO0_STB : std_logic; 146 | signal GPIO0_ACK : std_logic; 147 | signal GPIO0_DAT_O : std_logic_vector(31 downto 0); 148 | 149 | signal GPIO1_STB : std_logic; 150 | signal GPIO1_ACK : std_logic; 151 | signal GPIO1_DAT_O : std_logic_vector(31 downto 0); 152 | 153 | signal Timer0_STB : std_logic; 154 | signal Timer0_ACK : std_logic; 155 | signal Timer0_DAT_O : std_logic_vector(31 downto 0); 156 | 157 | signal Timer1_STB : std_logic; 158 | signal Timer1_ACK : std_logic; 159 | signal Timer1_DAT_O : std_logic_vector(31 downto 0); 160 | begin 161 | ------------------------------------------------------------ 162 | -- Bus Decoding 163 | ------------------------------------------------------------ 164 | -- Address Decoder 165 | ROM_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00010000# and unsigned(SYS_ADR) <= 16#00013FFF# else '0'; 166 | RAM_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00000000# and unsigned(SYS_ADR) <= 16#00003FFF# else '0'; 167 | GPIO0_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00008000# and unsigned(SYS_ADR) <= 16#00008023# else '0'; 168 | GPIO1_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00008100# and unsigned(SYS_ADR) <= 16#00008123# else '0'; 169 | Timer0_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00008200# and unsigned(SYS_ADR) <= 16#0000820F# else '0'; 170 | Timer1_STB <= SYS_STB when unsigned(SYS_ADR) >= 16#00008300# and unsigned(SYS_ADR) <= 16#0000830F# else '0'; 171 | -- Read Data MUX 172 | SYS_DAT_I <= ROM_DAT_O when ROM_STB = '1' else 173 | RAM_DAT_O when RAM_STB = '1' else 174 | GPIO0_DAT_O when GPIO0_STB = '1' else 175 | GPIO1_DAT_O when GPIO1_STB = '1' else 176 | Timer0_DAT_O when Timer0_STB = '1' else 177 | Timer1_DAT_O when Timer1_STB = '1' else 178 | (others=>'1'); 179 | -- Acknowledge MUX 180 | SYS_ACK <= ROM_ACK when ROM_STB = '1' else 181 | RAM_ACK when RAM_STB = '1' else 182 | GPIO0_ACK when GPIO0_STB = '1' else 183 | GPIO1_ACK when GPIO1_STB = '1' else 184 | Timer0_ACK when Timer0_STB = '1' else 185 | Timer1_ACK when Timer1_STB = '1' else 186 | '1'; 187 | 188 | ------------------------------------------------------------ 189 | -- ROM 190 | ------------------------------------------------------------ 191 | ROM_WE <= '1' when SYS_WE='1' and CPU_Halted='1' else '0'; 192 | ROM_Inst: entity work.Memory 193 | generic map ( 194 | ADR_I_WIDTH => 14, 195 | BASE_ADDR => 16#00010000# 196 | ) 197 | port map( 198 | CLK_I => CLK, 199 | RST_I => SYS_RESET, 200 | STB_I => ROM_STB, 201 | WE_I => ROM_WE, 202 | SEL_I => SYS_SEL, 203 | ADR_I => SYS_ADR(13 downto 0), 204 | DAT_I => SYS_DAT_O, 205 | DAT_O => ROM_DAT_O, 206 | ACK_O => ROM_ACK 207 | ); 208 | 209 | ------------------------------------------------------------ 210 | -- RAM 211 | ------------------------------------------------------------ 212 | RAM_Inst: entity work.Memory 213 | generic map ( 214 | ADR_I_WIDTH => 14, 215 | BASE_ADDR => 16#00000000# 216 | ) 217 | port map( 218 | CLK_I => CLK, 219 | RST_I => SYS_RESET, 220 | STB_I => RAM_STB, 221 | WE_I => SYS_WE, 222 | SEL_I => SYS_SEL, 223 | ADR_I => SYS_ADR(13 downto 0), 224 | DAT_I => SYS_DAT_O, 225 | DAT_O => RAM_DAT_O, 226 | ACK_O => RAM_ACK 227 | ); 228 | 229 | ------------------------------------------------------------ 230 | -- GPIO0 231 | ------------------------------------------------------------ 232 | GPIO0_Inst: entity work.GPIO 233 | generic map ( 234 | NUM_PORTS => GPIO0'length 235 | ) port map ( 236 | CLK_I => CLK, 237 | RST_I => SYS_RESET, 238 | STB_I => GPIO0_STB, 239 | WE_I => SYS_WE, 240 | ADR_I => SYS_ADR(7 downto 0), 241 | DAT_I => SYS_DAT_O, 242 | DAT_O => GPIO0_DAT_O, 243 | ACK_O => GPIO0_ACK, 244 | Pins => GPIO0 245 | ); 246 | 247 | ------------------------------------------------------------ 248 | -- GPIO1 249 | ------------------------------------------------------------ 250 | GPIO1_Inst: entity work.GPIO 251 | generic map ( 252 | NUM_PORTS => GPIO1'length 253 | ) port map ( 254 | CLK_I => CLK, 255 | RST_I => SYS_RESET, 256 | STB_I => GPIO1_STB, 257 | WE_I => SYS_WE, 258 | ADR_I => SYS_ADR(7 downto 0), 259 | DAT_I => SYS_DAT_O, 260 | DAT_O => GPIO1_DAT_O, 261 | ACK_O => GPIO1_ACK, 262 | Pins => GPIO1 263 | ); 264 | 265 | ------------------------------------------------------------ 266 | -- Timer0 267 | ------------------------------------------------------------ 268 | Timer0_Inst: entity work.Timer 269 | port map( 270 | CLK_I => CLK, 271 | RST_I => SYS_RESET, 272 | STB_I => Timer0_STB, 273 | WE_I => SYS_WE, 274 | ADR_I => SYS_ADR(3 downto 0), 275 | DAT_I => SYS_DAT_O, 276 | ACK_O => Timer0_ACK, 277 | DAT_O => Timer0_DAT_O, 278 | Timer_IRQ => Timer0_Interrupt 279 | ); 280 | 281 | ------------------------------------------------------------ 282 | -- Timer1 283 | ------------------------------------------------------------ 284 | Timer1_Inst: entity work.Timer 285 | port map( 286 | CLK_I => CLK, 287 | RST_I => SYS_RESET, 288 | STB_I => Timer1_STB, 289 | WE_I => SYS_WE, 290 | ADR_I => SYS_ADR(3 downto 0), 291 | DAT_I => SYS_DAT_O, 292 | ACK_O => Timer1_ACK, 293 | DAT_O => Timer1_DAT_O, 294 | Timer_IRQ => Timer1_Interrupt 295 | ); 296 | 297 | end block; 298 | 299 | end arch; -------------------------------------------------------------------------------- /VexRiscvWB_TOP.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- GDB_RSP_Debug for VexRiscV Project 3 | -- (c) Bernhard Lang, Hochschule Osnabrueck 4 | ---------------------------------------------------------------------------------------- 5 | library ieee; 6 | use ieee.math_real.all; 7 | use IEEE.std_logic_1164.all; 8 | use IEEE.numeric_std.all; 9 | 10 | entity VexRiscvWB_TOP is 11 | -- Generic Values are for Synthesizing. Testbench may override these values to speed up simulation 12 | generic ( 13 | DBG_BW : integer := 434; 14 | ExtFreq : real := 100_000_000.0; -- External frequency in MHz 15 | Mult : real := 8.000; -- Multiply value (2.000-64.000), VCO Frequency must be in range 600-1200 MHz 16 | Divide : real := 16.000; -- Divide value (1.000-128.000) 17 | DBG_Baud : integer := 115200 -- Baudrate for GDB serial line debug port 18 | ); 19 | port ( 20 | ExtClk : in std_logic; 21 | -- GDB serial line debug port 22 | DBG_RXD : in std_logic; 23 | DBG_TXD : out std_logic; 24 | -- GPIO 25 | LED : inout std_logic_vector(15 downto 0); 26 | sw : inout std_logic_vector(15 downto 0); 27 | -- SevenSeg Display 28 | seg : inout std_logic_vector( 6 downto 0); 29 | dp : inout std_logic; 30 | an : inout std_logic_vector( 3 downto 0) 31 | ); 32 | -- Specify PLL Parameters (BASYS3) 33 | constant SysFreq : real := (ExtFreq*Mult)/Divide; 34 | end VexRiscvWB_TOP; 35 | 36 | architecture arch of VexRiscvWB_TOP is 37 | signal RESET : std_logic; 38 | -- 39 | signal SysClk : std_logic; 40 | signal SysReset : std_logic; 41 | -- signal SysResetn : std_logic; 42 | -- VexRiscV Debug Interface 43 | signal dbgbus_cmd_valid : std_logic; 44 | signal dbgbus_cmd_payload_wr : std_logic; 45 | signal dbgbus_cmd_payload_address : unsigned(7 downto 0); 46 | signal dbgbus_cmd_payload_data : std_logic_vector(31 downto 0); 47 | signal dbgbus_cmd_ready : std_logic; 48 | signal dbgbus_rsp_data : std_logic_vector(31 downto 0); 49 | signal CPU_Halted : std_logic; 50 | begin 51 | 52 | -- Power on Reset Signal 53 | PowerOn_Reset: process(ExtClk) is 54 | variable cnt : unsigned(4 downto 0) := (others=>'1'); 55 | begin 56 | if rising_edge(ExtClk) then 57 | RESET <= '1'; -- assert Reset 58 | if cnt>0 then cnt:=cnt-1; 59 | else RESET <= '0'; 60 | end if; 61 | end if; 62 | end process; 63 | 64 | -- Generate system clock from external clock input ExtClk 65 | clkgen: entity work.ScaleClock 66 | Generic map ( 67 | ExtFreq => ExtFreq/1_000_000.0, 68 | Mult => Mult, 69 | Divide => Divide 70 | ) 71 | Port map ( 72 | ExtClk => ExtClk, 73 | ExtReset => RESET, 74 | SysClk => SysClk, 75 | SysReset => SysReset 76 | ); 77 | --SysReset<='0'; 78 | -- SysResetn <= not SysReset; 79 | 80 | -- The VexRicV Wishbone system 81 | MCU: entity work.VexRiscvWB_System 82 | port map ( 83 | clk => SysClk, 84 | reset => SysReset, 85 | -- VexRiscV Debug Interface 86 | dbgbus_cmd_valid => dbgbus_cmd_valid, 87 | dbgbus_cmd_payload_wr => dbgbus_cmd_payload_wr, 88 | dbgbus_cmd_payload_address => dbgbus_cmd_payload_address, 89 | dbgbus_cmd_payload_data => dbgbus_cmd_payload_data, 90 | dbgbus_cmd_ready => dbgbus_cmd_ready, 91 | dbgbus_rsp_data => dbgbus_rsp_data, 92 | CPU_Halted => CPU_Halted, 93 | -- GPIO for switches and LEDs 94 | GPIO0(15 downto 0) => LED, 95 | GPIO0(31 downto 16) => sw, 96 | -- GPIO for SevenSegment display 97 | GPIO1( 6 downto 0) => seg, 98 | GPIO1(7) => dp, 99 | GPIO1(11 downto 8) => an 100 | ); 101 | -- 102 | Debug_IF: entity work.GDB_RSP_Debug 103 | generic map ( 104 | DBG_BW => DBG_BW 105 | ) 106 | port map ( 107 | Clk => SysClk, 108 | DebugReset => SysReset, 109 | CPU_Halted => CPU_Halted, 110 | -- GDB serial line debug port 111 | DBG_RXD => DBG_RXD, 112 | DBG_TXD => DBG_TXD, 113 | -- VexRiscV Debug Interface 114 | dbgbus_cmd_valid => dbgbus_cmd_valid, 115 | dbgbus_cmd_payload_wr => dbgbus_cmd_payload_wr, 116 | dbgbus_cmd_payload_address => dbgbus_cmd_payload_address, 117 | dbgbus_cmd_payload_data => dbgbus_cmd_payload_data, 118 | dbgbus_cmd_ready => dbgbus_cmd_ready, 119 | dbgbus_rsp_data => dbgbus_rsp_data 120 | ); 121 | 122 | end arch; -------------------------------------------------------------------------------- /VexRiscvWB_TOP.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the Basys3 rev B board 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | # Clock signal 7 | set_property PACKAGE_PIN W5 [get_ports ExtClk] 8 | set_property IOSTANDARD LVCMOS33 [get_ports ExtClk] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports ExtClk] 10 | 11 | # Switches 12 | set_property PACKAGE_PIN V17 [get_ports {sw[0]}] 13 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] 14 | set_property PACKAGE_PIN V16 [get_ports {sw[1]}] 15 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] 16 | set_property PACKAGE_PIN W16 [get_ports {sw[2]}] 17 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] 18 | set_property PACKAGE_PIN W17 [get_ports {sw[3]}] 19 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] 20 | set_property PACKAGE_PIN W15 [get_ports {sw[4]}] 21 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] 22 | set_property PACKAGE_PIN V15 [get_ports {sw[5]}] 23 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] 24 | set_property PACKAGE_PIN W14 [get_ports {sw[6]}] 25 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] 26 | set_property PACKAGE_PIN W13 [get_ports {sw[7]}] 27 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] 28 | set_property PACKAGE_PIN V2 [get_ports {sw[8]}] 29 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] 30 | set_property PACKAGE_PIN T3 [get_ports {sw[9]}] 31 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] 32 | set_property PACKAGE_PIN T2 [get_ports {sw[10]}] 33 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] 34 | set_property PACKAGE_PIN R3 [get_ports {sw[11]}] 35 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] 36 | set_property PACKAGE_PIN W2 [get_ports {sw[12]}] 37 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] 38 | set_property PACKAGE_PIN U1 [get_ports {sw[13]}] 39 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] 40 | set_property PACKAGE_PIN T1 [get_ports {sw[14]}] 41 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] 42 | set_property PACKAGE_PIN R2 [get_ports {sw[15]}] 43 | set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] 44 | 45 | # LEDs 46 | set_property PACKAGE_PIN U16 [get_ports {LED[0]}] 47 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}] 48 | set_property PACKAGE_PIN E19 [get_ports {LED[1]}] 49 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[1]}] 50 | set_property PACKAGE_PIN U19 [get_ports {LED[2]}] 51 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[2]}] 52 | set_property PACKAGE_PIN V19 [get_ports {LED[3]}] 53 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[3]}] 54 | set_property PACKAGE_PIN W18 [get_ports {LED[4]}] 55 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[4]}] 56 | set_property PACKAGE_PIN U15 [get_ports {LED[5]}] 57 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[5]}] 58 | set_property PACKAGE_PIN U14 [get_ports {LED[6]}] 59 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[6]}] 60 | set_property PACKAGE_PIN V14 [get_ports {LED[7]}] 61 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[7]}] 62 | set_property PACKAGE_PIN V13 [get_ports {LED[8]}] 63 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[8]}] 64 | set_property PACKAGE_PIN V3 [get_ports {LED[9]}] 65 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[9]}] 66 | set_property PACKAGE_PIN W3 [get_ports {LED[10]}] 67 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[10]}] 68 | set_property PACKAGE_PIN U3 [get_ports {LED[11]}] 69 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[11]}] 70 | set_property PACKAGE_PIN P3 [get_ports {LED[12]}] 71 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[12]}] 72 | set_property PACKAGE_PIN N3 [get_ports {LED[13]}] 73 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[13]}] 74 | set_property PACKAGE_PIN P1 [get_ports {LED[14]}] 75 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[14]}] 76 | set_property PACKAGE_PIN L1 [get_ports {LED[15]}] 77 | set_property IOSTANDARD LVCMOS33 [get_ports {LED[15]}] 78 | 79 | #7 segment display 80 | set_property PACKAGE_PIN W7 [get_ports {seg[0]}] 81 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] 82 | set_property PACKAGE_PIN W6 [get_ports {seg[1]}] 83 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] 84 | set_property PACKAGE_PIN U8 [get_ports {seg[2]}] 85 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] 86 | set_property PACKAGE_PIN V8 [get_ports {seg[3]}] 87 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] 88 | set_property PACKAGE_PIN U5 [get_ports {seg[4]}] 89 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] 90 | set_property PACKAGE_PIN V5 [get_ports {seg[5]}] 91 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] 92 | set_property PACKAGE_PIN U7 [get_ports {seg[6]}] 93 | set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] 94 | 95 | set_property PACKAGE_PIN V7 [get_ports dp] 96 | set_property IOSTANDARD LVCMOS33 [get_ports dp] 97 | 98 | set_property PACKAGE_PIN U2 [get_ports {an[0]}] 99 | set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] 100 | set_property PACKAGE_PIN U4 [get_ports {an[1]}] 101 | set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] 102 | set_property PACKAGE_PIN V4 [get_ports {an[2]}] 103 | set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] 104 | set_property PACKAGE_PIN W4 [get_ports {an[3]}] 105 | set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] 106 | 107 | ##Buttons 108 | # set_property PACKAGE_PIN U18 [get_ports btnC] 109 | # set_property IOSTANDARD LVCMOS33 [get_ports btnC] 110 | # set_property PACKAGE_PIN T18 [get_ports btnU] 111 | # set_property IOSTANDARD LVCMOS33 [get_ports btnU] 112 | # set_property PACKAGE_PIN W19 [get_ports btnL] 113 | # set_property IOSTANDARD LVCMOS33 [get_ports btnL] 114 | # set_property PACKAGE_PIN T17 [get_ports btnR] 115 | # set_property IOSTANDARD LVCMOS33 [get_ports btnR] 116 | # set_property PACKAGE_PIN U17 [get_ports btnD] 117 | # set_property IOSTANDARD LVCMOS33 [get_ports btnD] 118 | 119 | #Pmod Header JA 120 | # #Sch name = JA1 121 | # set_property PACKAGE_PIN J1 [get_ports {JA[0]}] 122 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] 123 | # #Sch name = JA2 124 | # set_property PACKAGE_PIN L2 [get_ports {JA[1]}] 125 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] 126 | # #Sch name = JA3 127 | # set_property PACKAGE_PIN J2 [get_ports {JA[2]}] 128 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] 129 | # #Sch name = JA4 130 | # set_property PACKAGE_PIN G2 [get_ports {JA[3]}] 131 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] 132 | # #Sch name = JA7 133 | # set_property PACKAGE_PIN H1 [get_ports {JA[4]}] 134 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] 135 | # #Sch name = JA8 136 | # set_property PACKAGE_PIN K2 [get_ports {JA[5]}] 137 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] 138 | # #Sch name = JA9 139 | # set_property PACKAGE_PIN H2 [get_ports {JA[6]}] 140 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] 141 | # #Sch name = JA10 142 | # set_property PACKAGE_PIN G3 [get_ports {JA[7]}] 143 | # set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] 144 | 145 | 146 | #USB-RS232 Interface 147 | set_property PACKAGE_PIN B18 [get_ports DBG_RXD] 148 | set_property IOSTANDARD LVCMOS33 [get_ports DBG_RXD] 149 | set_property PACKAGE_PIN A18 [get_ports DBG_TXD] 150 | set_property IOSTANDARD LVCMOS33 [get_ports DBG_TXD] 151 | -------------------------------------------------------------------------------- /VexRiscvWB_TOP_TB.do: -------------------------------------------------------------------------------- 1 | #---------------------------------------------------------------------------------- 2 | # (c) Bernhard Lang, Hochschule Osnabrueck 3 | #---------------------------------------------------------------------------------- 4 | vcom -work work ScaleClock.vhd 5 | 6 | vcom -work work VexRiscvWB_small.vhd 7 | vcom -work work GDB_RSP/GDB_RSP_Debug.vhd 8 | 9 | vcom -work work Memory/Memory.vhd 10 | 11 | vcom -work work Peripherals/GPIO.vhd 12 | 13 | vcom -work work Peripherals/Timer.vhd 14 | 15 | vcom -work work Interconnect.vhd 16 | vcom -work work VexRiscvWB_System.vhd 17 | 18 | vcom -work work VexRiscvWB_TOP.vhd 19 | 20 | vcom -work work string_stream_pack.vhd 21 | vcom -work work UART_Sender_nur_Simulation.vhd 22 | vcom -work work VexRiscvWB_TOP_TB.vhd 23 | 24 | vsim -novopt -t ps -noglitch work.vexriscvwb_top_tb 25 | 26 | set NumericStdNoWarnings 1 27 | 28 | config wave -signalnamewidth 1 29 | 30 | if (1) { add wave /vexriscvwb_top_tb/ExtClk } 31 | if (1) { add wave /vexriscvwb_top_tb/DUT/Reset } 32 | if (1) { add wave /vexriscvwb_top_tb/DUT/SysClk } 33 | if (1) { add wave /vexriscvwb_top_tb/DUT/SysReset } 34 | if (1) { add wave /vexriscvwb_top_tb/DUT/clkgen/locked } 35 | 36 | if (1) { 37 | add wave -divider "== DBG_TXD, DBG_RXD ==" 38 | add wave /vexriscvwb_top_tb/s_valid 39 | add wave /vexriscvwb_top_tb/s_last 40 | add wave -ASCII /vexriscvwb_top_tb/s_data 41 | add wave /vexriscvwb_top_tb/s_ready 42 | add wave /vexriscvwb_top_tb/DBG_Sender/marker 43 | add wave /vexriscvwb_top_tb/DBG_RXD 44 | add wave /vexriscvwb_top_tb/Stimulate/message 45 | add wave /vexriscvwb_top_tb/DBG_TXD 46 | add wave -ASCII /vexriscvwb_top_tb/response 47 | } 48 | 49 | add wave -divider "== VexRiscV ==" 50 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/execute_PC 51 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/execute_INSTRUCTION 52 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/execute_arbitration_isValid 53 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/RegFilePlugin_regFile(1) 54 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/RegFilePlugin_regFile(2) 55 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/RegFilePlugin_regFile(3) 56 | 57 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/DebugPlugin_resetIt 58 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/DebugPlugin_haltIt 59 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/DebugPlugin_stepIt 60 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/DebugPlugin_godmode 61 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/DebugPlugin_haltedByBreak 62 | add wave -divider "===================" 63 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/debug_bus_cmd_valid 64 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/debug_bus_cmd_payload_wr 65 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/debug_bus_cmd_payload_address 66 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/MCU/CPU/debug_bus_rsp_data 67 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU/debug_bus_cmd_ready 68 | 69 | if (1) { 70 | add wave -divider "== VexRiscV dbgbus ==" 71 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_cmd_valid 72 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_cmd_payload_wr 73 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_cmd_payload_address 74 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_cmd_payload_data 75 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_cmd_ready 76 | add wave -hexadecimal /vexriscvwb_top_tb/DUT/Debug_IF/dbgbus_rsp_data 77 | add wave /vexriscvwb_top_tb/DUT/MCU/CPU_Halted 78 | } 79 | 80 | if (0) { 81 | add wave -divider "== RXD TXD ==" 82 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/in_valid 83 | add wave -ASCII /vexriscvwb_top_tb/DUT/Debug_IF/in_data 84 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/in_ready 85 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRRF_valid 86 | 87 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRRF_last 88 | add wave -ASCII /vexriscvwb_top_tb/DUT/Debug_IF/GRRF_data 89 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRRF_ready 90 | 91 | 92 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspC_valid 93 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspC_last 94 | add wave -ASCII /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspC_data 95 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspC_ready 96 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspR_valid 97 | add wave -ASCII /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspR_data 98 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/rspR_ready 99 | 100 | add wave /vexriscvwb_top_tb/DUT/Debug_IF/GRI/control_path/state 101 | } 102 | 103 | run 700 us 104 | 105 | wave zoom full 106 | 107 | 108 | 109 | -------------------------------------------------------------------------------- /VexRiscvWB_TOP_TB.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- GDB_RSP_Debug for VexRiscV Project 3 | -- (c) Bernhard Lang, Hochschule Osnabrueck 4 | ---------------------------------------------------------------------------------------- 5 | 6 | entity VexRiscvWB_TOP_TB is 7 | constant ExtFreq : real := 100_000_000.0; 8 | constant ExtResetTime : time := 50 ns; 9 | end VexRiscvWB_TOP_TB; 10 | 11 | library ieee; 12 | use IEEE.std_logic_1164.all; 13 | use IEEE.numeric_std.all; 14 | 15 | use work.string_stream.all; 16 | 17 | architecture test of VexRiscvWB_TOP_TB is 18 | signal ExtClk : std_logic := '0'; 19 | signal ExtRESET : std_logic := '0'; 20 | -- 21 | signal s_valid : std_logic; 22 | signal s_last : std_logic:='0'; 23 | signal s_data : std_logic_vector(7 downto 0); 24 | signal s_ready : std_logic; 25 | -- 26 | signal DBG_RXD : std_logic := '1'; 27 | signal DBG_TXD : std_logic := '1'; 28 | -- 29 | signal response : character; 30 | begin 31 | 32 | ExtClk <= not ExtClk after 0.5 sec / ExtFreq; 33 | ExtRESET <= '1' after 0 ns, '0' after ExtResetTime; 34 | 35 | DUT: entity work.VexRiscvWB_TOP 36 | generic map ( 37 | DBG_BW => 3 38 | ) 39 | port map ( 40 | ExtClk => ExtClk, 41 | -- GDB serial link debug port 42 | DBG_RXD => DBG_RXD, 43 | DBG_TXD => DBG_TXD, 44 | -- GPIO 45 | LED => open, 46 | sw => open, 47 | -- SevenSeg Display 48 | seg => open, 49 | dp => open, 50 | an => open 51 | ); 52 | 53 | DBG_Sender: entity work.UART_Sender_Simulation 54 | generic map ( 55 | Baudrate => real(12500000), 56 | Bitanzahl => 8 57 | ) 58 | port map ( 59 | Takt => ExtClk, 60 | Reset => ExtRESET, 61 | -- Eingang 62 | s_valid => s_valid, 63 | s_data => s_data, 64 | s_ready => s_ready, 65 | -- Ausgang 66 | TxD => DBG_RXD 67 | ); 68 | 69 | DBG_Receiver: process 70 | constant Bitbreite : time := 1 sec / real(12500000); 71 | variable rec_val : std_logic_vector(7 downto 0); 72 | begin 73 | wait until falling_edge(DBG_TXD) and DBG_TXD='0'; 74 | wait for Bitbreite*1.5; 75 | response <= ' '; 76 | for i in 0 to 7 loop 77 | rec_val(i) := DBG_TXD; 78 | wait for Bitbreite; 79 | end loop; 80 | response <= character'val(to_integer(unsigned(rec_val))); 81 | wait for Bitbreite; 82 | end process; 83 | 84 | Stimulate: process 85 | variable message : string(1 to MsgLen); 86 | begin 87 | s_valid <= '0'; 88 | wait for 2 us; -- PLL must be locked, check simultion wave 89 | wait until rising_edge(ExtClk); 90 | -- 91 | -- extended remote 92 | Send_String("$!#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 0.4 us; 93 | wait until rising_edge(ExtClk) and response='#'; 94 | -- monitor r 95 | Send_String("$qRcmd,72#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 96 | wait until rising_edge(ExtClk) and response='#'; 97 | -- 98 | --Send_String("$g#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 99 | --wait until rising_edge(ExtClk) and response='#'; 100 | -- 101 | -- Load test program 102 | Send_String("$M10000,10:6F000009000000000000000000000000#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 103 | wait until rising_edge(ExtClk) and response='#'; 104 | Send_String("$M10010,10:6F00600B6F00200B6F00E00A6F00A00A#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 105 | wait until rising_edge(ExtClk) and response='#'; 106 | Send_String("$M10020,10:6F00600A6F00200A6F00E0096F00A009#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 107 | wait until rising_edge(ExtClk) and response='#'; 108 | Send_String("$M10030,10:6F0060096F0020096F00E0086F00A008#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 109 | wait until rising_edge(ExtClk) and response='#'; 110 | Send_String("$M10040,10:6F0060086F0020086F00E0076F00A007#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 111 | wait until rising_edge(ExtClk) and response='#'; 112 | Send_String("$M10050,10:6F0060076F0020076F00E0066F00A006#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 113 | wait until rising_edge(ExtClk) and response='#'; 114 | Send_String("$M10060,10:6F0060066F0020066F00E0056F00A005#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 115 | wait until rising_edge(ExtClk) and response='#'; 116 | Send_String("$M10070,10:6F0060056F0020056F00E0046F00A004#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 117 | wait until rising_edge(ExtClk) and response='#'; 118 | Send_String("$M10080,10:6F0060046F0020046F00E0036F00A003#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 119 | wait until rising_edge(ExtClk) and response='#'; 120 | Send_String("$M10090,10:73F005301711FFFF1301C1F693010000#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 121 | wait until rising_edge(ExtClk) and response='#'; 122 | Send_String("$M100A0,10:93811100890193813100938141009381#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 123 | wait until rising_edge(ExtClk) and response='#'; 124 | Send_String("$M100B0,10:510099019D0193818100938191009381#00",Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 125 | wait until rising_edge(ExtClk) and response='#'; 126 | Send_String("$M100C0,0C:A1006FF0BFFD6F0000000000#00" ,Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 127 | -- resume 128 | wait until rising_edge(ExtClk) and response='#'; 129 | Send_String("$c#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 2 us; 130 | wait until rising_edge(ExtClk) and response='+'; 131 | -- ctrl-C 132 | Send_String(""&ETX, Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 1 us; 133 | wait until rising_edge(ExtClk) and response='#'; 134 | -- Step 135 | Send_String("$s#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 2 us; 136 | wait until rising_edge(ExtClk) and response='#'; 137 | -- Step 138 | Send_String("$s#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 2 us; 139 | wait until rising_edge(ExtClk) and response='#'; 140 | -- resume 141 | Send_String("$c#00", Message, ExtClk, s_valid, s_last, s_data, s_ready); wait for 2 us; 142 | wait until rising_edge(ExtClk) and response='+'; 143 | 144 | report "Fertig" severity note; 145 | wait; 146 | end process; 147 | 148 | 149 | end test; -------------------------------------------------------------------------------- /VexRiscvWB_small.scala: -------------------------------------------------------------------------------- 1 | package vexriscv.demo 2 | 3 | import vexriscv.plugin._ 4 | import vexriscv.{VexRiscv, VexRiscvConfig, plugin} 5 | import spinal.core._ 6 | import spinal.lib._ 7 | 8 | object VexRiscvWB_small{ 9 | def main(args: Array[String]) { 10 | //val report = SpinalConfig(mode = Verilog).generate{ 11 | val report = SpinalConfig(mode = VHDL).generate{ 12 | 13 | //CPU configuration 14 | val cpuConfig = VexRiscvConfig( 15 | plugins = List( 16 | new IBusSimplePlugin( 17 | resetVector = 0x00010000l, 18 | cmdForkOnSecondStage = false, 19 | cmdForkPersistence = false, 20 | prediction = NONE, 21 | catchAccessFault = false, 22 | compressedGen = true 23 | ), 24 | new DBusSimplePlugin( 25 | catchAddressMisaligned = true, 26 | catchAccessFault = false 27 | ), 28 | new CsrPlugin( 29 | CsrPluginConfig( 30 | catchIllegalAccess = false, 31 | mvendorid = null, 32 | marchid = null, 33 | mimpid = null, 34 | mhartid = null, 35 | misaExtensionsInit = 66, 36 | misaAccess = CsrAccess.NONE, 37 | mtvecAccess = CsrAccess.READ_WRITE, // required for xtvecModeGen 38 | mtvecInit = 0x00010011l, 39 | mepcAccess = CsrAccess.READ_WRITE, // required to access EPC from software 40 | mscratchGen = false, 41 | mcauseAccess = CsrAccess.READ_ONLY, 42 | mbadaddrAccess = CsrAccess.NONE, 43 | mcycleAccess = CsrAccess.NONE, 44 | minstretAccess = CsrAccess.NONE, 45 | ecallGen = true, // enable 46 | wfiGenAsWait = false, 47 | ucycleAccess = CsrAccess.NONE, 48 | uinstretAccess = CsrAccess.NONE, 49 | xtvecModeGen = true 50 | ) 51 | ), 52 | new DecoderSimplePlugin( 53 | catchIllegalInstruction = true 54 | ), 55 | new RegFilePlugin( 56 | regFileReadyKind = plugin.SYNC, 57 | zeroBoot = false 58 | ), 59 | new IntAluPlugin, 60 | new MulPlugin, 61 | new DivPlugin, 62 | new SrcPlugin( 63 | separatedAddSub = false, 64 | executeInsertion = false 65 | ), 66 | //new LightShifterPlugin, 67 | new FullBarrelShifterPlugin, 68 | new HazardSimplePlugin( 69 | bypassExecute = true, 70 | bypassMemory = true, 71 | bypassWriteBack = true, 72 | bypassWriteBackBuffer = true, 73 | pessimisticUseSrc = false, 74 | pessimisticWriteRegFile = false, 75 | pessimisticAddressMatch = false 76 | ), 77 | new DebugPlugin( 78 | debugClockDomain = ClockDomain.current.clone(reset = Bool().setName("debugReset")), 79 | hardwareBreakpointCount = 16 80 | ), 81 | new BranchPlugin( 82 | earlyBranch = false, 83 | catchAddressMisaligned = true 84 | ), 85 | new UserInterruptPlugin( 86 | interruptName = "LocalInt0", 87 | code = 16 88 | ), 89 | new UserInterruptPlugin( 90 | interruptName = "LocalInt1", 91 | code = 17 92 | ), 93 | new UserInterruptPlugin( 94 | interruptName = "LocalInt2", 95 | code = 18 96 | ), 97 | new UserInterruptPlugin( 98 | interruptName = "LocalInt3", 99 | code = 19 100 | ), 101 | new YamlPlugin("cpu0.yaml") 102 | ) 103 | ) 104 | 105 | //CPU instanciation 106 | val cpu = new VexRiscv(cpuConfig) 107 | 108 | //CPU modifications to be an AhbLite3 one 109 | cpu.rework { 110 | for (plugin <- cpuConfig.plugins) plugin match { 111 | case plugin: IBusSimplePlugin => { 112 | plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus 113 | master(plugin.iBus.toWishbone()).setName("iBusWishbone") 114 | } 115 | case plugin: DBusSimplePlugin => { 116 | plugin.dBus.setAsDirectionLess() 117 | master(plugin.dBus.toWishbone()).setName("dBusWishbone") 118 | } 119 | case _ => 120 | } 121 | } 122 | cpu 123 | } 124 | } 125 | } 126 | 127 | -------------------------------------------------------------------------------- /string_stream_pack.vhd: -------------------------------------------------------------------------------- 1 | ---------------------------------------------------------------------------------------- 2 | -- GDB_RSP_Debug for VexRiscV Project 3 | -- (c) Bernhard Lang, Hochschule Osnabrueck 4 | ---------------------------------------------------------------------------------------- 5 | library ieee; 6 | use ieee.std_logic_1164.all; 7 | package string_stream is 8 | constant MsgLen: integer := 300; 9 | function SetMessage(constant message: string) return string; 10 | procedure Send_String( 11 | constant command : in string; 12 | variable message : inout string; 13 | signal Clk : in std_logic; 14 | signal out_valid : out std_logic; 15 | signal out_last : out std_logic; 16 | signal out_data : out std_logic_vector(7 downto 0); 17 | signal out_ready : in std_logic 18 | ); 19 | procedure Receive_String( 20 | variable response : out string; 21 | signal Clk : in std_logic; 22 | signal in_valid : in std_logic; 23 | signal in_last : in std_logic; 24 | signal in_data : in std_logic_vector(7 downto 0); 25 | signal in_ready : out std_logic 26 | ); 27 | end package; 28 | 29 | library ieee; 30 | use ieee.numeric_std.all; 31 | package body string_stream is 32 | ---------------------------------------------------------------------------- 33 | function SetMessage(constant message: string) return string is 34 | variable m: string(1 to MsgLen) := (others=>' '); 35 | begin 36 | m(message'range) := message; 37 | return m; 38 | end; 39 | ---------------------------------------------------------------------------- 40 | procedure Send_String( 41 | constant command : in string; 42 | variable message : inout string; 43 | signal Clk : in std_logic; 44 | signal out_valid : out std_logic; 45 | signal out_last : out std_logic; 46 | signal out_data : out std_logic_vector(7 downto 0); 47 | signal out_ready : in std_logic 48 | ) is 49 | begin 50 | message := (message'range =>' '); 51 | out_valid <= '0'; 52 | out_last <= '0'; 53 | out_data <= x"00"; 54 | wait until rising_edge(Clk); 55 | for i in command'range loop 56 | out_valid <= '1'; 57 | if i=command'right then out_last<='1'; else out_last<='0'; end if; 58 | out_data <= std_logic_vector(to_unsigned(character'pos(command(i)),8)); 59 | wait until rising_edge(Clk) and out_ready='1'; 60 | end loop; 61 | message := SetMessage(command); 62 | out_valid <= '0'; 63 | out_last <= '0'; 64 | out_data <= x"00"; 65 | wait until rising_edge(Clk); 66 | message := (message'range =>' '); 67 | end procedure; 68 | ---------------------------------------------------------------------------- 69 | procedure Receive_String( 70 | variable response : out string; 71 | signal Clk : in std_logic; 72 | signal in_valid : in std_logic; 73 | signal in_last : in std_logic; 74 | signal in_data : in std_logic_vector(7 downto 0); 75 | signal in_ready : out std_logic 76 | ) is 77 | variable index: integer; 78 | variable char: character; 79 | variable resp: string(response'range); 80 | begin 81 | response := (response'range =>' '); 82 | index := 1; 83 | in_ready <= '1'; 84 | loop 85 | wait until rising_edge(Clk) and in_valid='1'; 86 | char := character'val(to_integer(unsigned(in_data))); 87 | resp(index) := char; 88 | exit when in_last='1'; 89 | if index' '); 97 | end procedure; 98 | ---------------------------------------------------------------------------- 99 | end package body; 100 | 101 | --------------------------------------------------------------------------------