├── LICENSE └── README.md /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2024 CI Lab 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Literature on SRAM-based Compute-In-Memory 2 | This repository serves as a comprehensive resource for the rapidly advancing field of SRAM-based Compute-In-Memory (CIM), particularly in the context of AI acceleration. It compiles a wide range of materials, including research papers, tools, and surveys, curated by our [team of Maintainers](#maintainers). We welcome and encourage contributions from the community. 3 | 4 | The content is systematically categorized to provide a clear and structured overview: 5 | - [Macro Level](#macro-level): Research on CIM macro designs. 6 | - [Architecture Level](#architecture-level): Designs and optimizations of CIM accelerators. 7 | - [Simulation Tools](#simulation-tools): Evaluation tools for CIM. 8 | - [Software Stack](#software-stack): Software integration with CIM hardware. 9 | - [Surveys and Analysis](#surveys-and-analysis): In-depth reviews and meta-studies in CIM research. 10 | 11 | This curated collection aims to offer valuable insights into the integration of CIM technologies for AI, showcasing the latest advancements and methodologies in the field. 12 | 13 | --- 14 | ## Macro Level 15 | * [**JSSC 2025**] A 22-nm 109.3-to-249.5-TFLOPS/W Outlier-Aware Floating-Point SRAM Compute-in-Memory Macro for Large Language Models. 16 | >*Siqi He, Haozhe Zhu, Hongyi Zhang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2025.3571315) 17 | * [**JSSC 2025**] A 22-nm Delta–Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing. 18 | >*Peiyu Chen, Wentao Zhao, Meng Wu, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2025.3539736) 19 | * [**CICC 2025**] A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization. 20 | >*Xiaofeng Hu, HanGyeol Mun, Jian Meng, et al.* [[Paper]](https://doi.org/10.1109/CICC63670.2025.10982878) 21 | * [**MEJ 2025**] A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits. 22 | >*Chenghu Dai, Jianhao Zhang, Ruixuan Wang, et al.* [[Paper]](https://doi.org/10.1016/j.mejo.2025.106703) 23 | * [**LSSC 2025**] A Segmented Precision Configurable Computing-in-Memory Macro With Dual-Edge Time-Domain Structure. 24 | >*Chang Xue, Youming Yang, Siyuan He, et al.* [[Paper]](https://doi.org/10.1109/LSSC.2025.3558928) 25 | * [**ISSCC 2025**] 14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <2-30 Loss for Compound AI. 26 | >*Zhiheng Yue, Xujiang Xiang, Yang Wang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC49661.2025.10904702) 27 | * [**ISSCC 2025**] 14.5 A 28nm 192.3TFLOPS/W Accurate/Approximate Dual-Mode-Transpose Digital 6T-SRAM CIM Macro for Floating-Point Edge Training and Inference. 28 | >*Yiyang Yuan, Bingxin Zhang, Yiming Yang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC49661.2025.10904659) 29 | * [**ISSCC 2025**] 14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. 30 | >*Xi Chen, Shaochen Li, Zhican Zhang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC49661.2025.10904646) 31 | * [**ISSCC 2025**] 14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. 32 | >*An Guo, Jingmin Zhang, Xingyu Pu, et al.* [[Paper]](https://doi.org/10.1109/ISSCC49661.2025.10904805) 33 | * [**TVLSI 2025**] A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks. 34 | >*Chunyu Peng, Jiating Guo, Shengyuan Yan, et al.* [[Paper]](https://doi.ieeecomputersociety.org/10.1109/TVLSI.2025.3552641) 35 | * [**TVLSI 2025**] A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs. 36 | >*Zhiting Lin, Runru Yu, Yunhao Li, et al.* [[Paper]](https://doi.org/10.1109/TVLSI.2025.3545635) 37 | * [**TVLSI 2025**] Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing. 38 | >*Zhang Zhang, Zhihao Chen, Jiedong Wang, Guangjun Xie, Gang Liu.* [[Paper]](https://doi.ieeecomputersociety.org/10.1109/TVLSI.2025.3526973) 39 | * [**A-SSCC 2024**] A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications. 40 | >*D.-G. Choi, et al.* [[Paper]](https://doi.org/10.1109/A-SSCC60305.2024.10848920) 41 | * [**DAC 2024**] Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. 42 | >*Anni Lu, Junmo Lee, Yuan-Chun Luo, et al.* [[Paper]](https://doi.org/10.1145/3649329.3655673) 43 | * [**DAC 2024**] Addition is Most You Need: Efficient Floating-Point SRAM Compute-in-Memory by Harnessing Mantissa Addition. 44 | >*Weidong Cao, Jian Gao, Xin Xin, et al.* [[Paper]](https://doi.org/10.1145/3649329.3655930) 45 | * [**DAC 2024**] ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. 46 | >*Jonathan Hao-Cheng Ku, Junyao Zhang, Haoxuan Shan, et al.* [[Paper]](https://doi.org/10.1145/3649329.3656496) 47 | * [**DAC 2024**] Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning. 48 | >*Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, et al.* [[Paper]](https://doi.org/10.1145/3649329.3656514) 49 | * [**DAC 2024**] Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference. 50 | >*Qilin Zheng, Ziru Li, Jonathan Ku, et al.* [[Paper]](https://doi.org/10.1145/3649329.3658472) 51 | * [**CICC 2024**] A 28nm 8928Kb/mm²-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. 52 | >*Guodong Yin, Yiming Chen, Mingyen Lee, et al.* [[Paper]](https://doi.org/10.1109/CICC60959.2024.10528966) 53 | * [**CICC 2024**] STAR-SRAM: 43.06-TFLOPS/W, 1.89-TFLOPS/mm², 400-Kb/mm² Floating-Point SRAM-Based Digital Computing-in-Memory Macro in 28-nm CMOS. 54 | >*Chuan-Tung Lin, Jonghyun Oh, Kevin Lee, Mingoo Seok* [[Paper]](https://doi.org/10.1109/CICC60959.2024.10529048) 55 | * [**CICC 2024**] A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. 56 | >*Zhaoyang Zhang, Zhichao Liu, Feiran Liu, et al.* [[Paper]](https://doi.org/10.1109/CICC60959.2024.10529053) 57 | * [**JSSC 2023**] MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks. 58 | >*Bo Zhang, Jyotishman Saikia, Jian Meng, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2023.3332017) 59 | * [**CICC 2023**] A 65 nm 1.4-6.7 TOPS/W Adaptive-SNR Sparsity-Aware CIM Core with Load Balancing Support for DL workloads. 60 | >*Mustafa Fayez Ali, Indranil Chakraborty, Sakshi Choudhary, et al.* [[Paper]](https://doi.org/10.1109/CICC57935.2023.10121243) 61 | * [**CICC 2023**] A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. 62 | >*Yuanzhe Zhao, Minglei Zhang, Pengyu He, et al.* [[Paper]](https://doi.org/10.1109/CICC57935.2023.10121308) 63 | * [**CICC 2023**] iMCU: A 102-μJ, 61-ms Digital In-Memory Computing-based Microcontroller Unit for Edge TinyML. 64 | >*Chuan-Tung Lin, Paul Xuanyuanliang Huang, Jonghyun Oh, et al.* [[Paper]](https://doi.org/10.1109/CICC57935.2023.10121221) 65 | * [**ISSCC 7.1 2023**] A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. 66 | >*Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067527) 67 | * [**ISSCC 7.2 2023**] A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs. 68 | >*An Guo, Xin Si, Xi Chen, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067260) 69 | * [**ISSCC 7.3 2023**] A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. 70 | >*Yifan He, Haikang Diao, Chen Tang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067305) 71 | * [**ISSCC 7.4 2023**] A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. 72 | >*Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067555) 73 | * [**ISSCC 7.5 2023**] A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. 74 | >*Bo Wang, Chen Xue, Zhongyuan Feng, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067526) 75 | * [**ISSCC 7.6 2023**] A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation. 76 | >*Sung-En Hsieh, Chun-Hao Wei, Cheng-Xin Xue, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067335) 77 | * [**ISSCC 7.7 2023**] CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. 78 | >*Zhiheng Yue, Yang Wang, Huizheng Wang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067720) 79 | * [**ISSCC 7.8 2023**] A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. 80 | >*Peiyu Chen, Meng Wu, Wentao Zhao, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067289) 81 | * [**VLSI 2023**] A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. 82 | >*Jinshan Yue, Mingtao Zhan, Zi Wang, et al.* [[Paper]](https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185315) 83 | * [**JSSC 2023**] A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference. 84 | >*Hechen Wang, Renzhi Liu, Richard Dorrance, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3232601) 85 | * [**JSSC 2023**] In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. 86 | >*Zhiting Lin, Zhongzhen Tong, Fangming Wang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3206318) 87 | * [**CICC 2022**] An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. 88 | >*Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, et al.* [[Paper]](https://doi.org/10.1109/CICC53496.2022.9772789) 89 | * [**CICC 2022**] 5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. 90 | >*R. Mathur, M. Kumar, Vivek Asthana, et al.* [[Paper]](https://doi.org/10.1109/CICC53496.2022.9772840) 91 | * [**DAC 2022**] CP-SRAM: Charge-Pulsation SRAM Marco for Ultra-High Energy-Efficiency Computing-in-Memory. 92 | >*He Zhang, Linjun Jiang, Jianxin Wu, et al.* [[Paper]](https://doi.org/10.1145/3489517.3530398) 93 | * [**DAC 2022**] TAIM: ternary activation in-memory computing hardware with 6T SRAM array. 94 | >*Nameun Kang, Hyungjun Kim, Hyunmyung Oh, et al.* [[Paper]](https://doi.org/10.1145/3489517.3530574) 95 | * [**ISSCC 11.6 2022**] A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. 96 | >*Hidehiro Fujiwara, Haruki Mori, Wei-Chang Zhao, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731754) 97 | * [**ISSCC 11.7 2022**] A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-In-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. 98 | >*Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731545) 99 | * [**ISSCC 11.8 2022**] A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. 100 | >*Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731681) 101 | * [**JSSC 2022**] Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. 102 | >*Jian-Wei Su, Xin Si, Yen-Chi Chou, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3108344) 103 | * [**VLSI 2022**] A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. 104 | >*Hechen Wang, Renzhi Liu, Richard Dorrance, et al.* [[Paper]](https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830322) 105 | * [**VLSI C02-5 2022**] A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. 106 | >*Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, et al.* [[Paper]](https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830438) 107 | * [**VLSI C04-2 2022**] Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron Firing. 108 | >*Sangyeob Kim, Sangjin Kim, Soyeon Um, et al.* [[Paper]](https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830276) 109 | * [**CICC 2021**] A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. 110 | >*Rezwan A. Rasul, Mike Shuo-Wei Chen* [[Paper]](https://doi.org/10.1109/CICC51472.2021.9431485) 111 | * [**CICC 2021**] An In-Memory-Computing Charge-Domain Ternary CNN Classifier. 112 | >*Xiangxing Yang, Keren Zhu, Xiyuan Tang, et al.* [[Paper]](https://doi.org/10.1109/CICC51472.2021.9431398) 113 | * [**DAC 2021**] A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration. 114 | >*Kyeongho Lee, Sungsoo Cheon, Joongho Jo, et al.* [[Paper]](https://doi.org/10.1109/DAC18074.2021.9586103) 115 | * [**ISSCC 16.3 2021**] A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b of Precision for AI Edge Chips. 116 | >*Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42613.2021.9365984) 117 | * [**ISSCC 16.4 2021**] An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro 118 | in 22nm for Machine-Learning Edge Applications. 119 | >*Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42613.2021.9365766) 120 | * [**ISSCC, 16.1 2021**] DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware. 121 | >*Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731659) 122 | * [**JSSC 2021**] Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. 123 | >*Zhiting Lin, Zhiyong Zhu, Honglan Zhan, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3061260) 124 | * [**JSSC 2021**] A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. 125 | >*Xin Si, Yung-Ning Tu, Wei-Hsing Huang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3073254) 126 | * [**JSSC 2021**] A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. 127 | >*Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.3031290) 128 | * [**JSSC 2021**] Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks. 129 | >*Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3061508) 130 | * [**JSSC 2021**] Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. 131 | >*Zhiting Lin, Honglan Zhan, Zhongwei Chen, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3063719) 132 | * [**JSSC 2021**] ±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing. 133 | >*Saurabh Jain, Longyang Lin, and Massimo Alioto* [[Paper]](https://doi.org/10.1109/JSSC.2021.3092759) 134 | * [**JSSC 2021**] CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference. 135 | >*Zhiyu Chen, Zhanghao Yu, Qing Jin, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3056447) 136 | * [**VLSI JFS2-5 2021**] HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing. 137 | >*Riduan Khaddam-Aljameh, Milos Stanisavljevic, Jordi Fornt Mas, et al.* [[Paper]](https://doi.org/10.23919/VLSICircuits52068.2021.9492362) 138 | * [**VLSI JFS2-6 2021**] A 20x28 Spins Hybrid In-Memory Annealing Computer Featuring Voltage-Mode Analog Spin Operator for Solving Combinatorial Optimization Problems. 139 | >*Junjie Mu, Yuqi Su, Bongjin Kim* [[Paper]](https://doi.org/10.23919/VLSICircuits52068.2021.9492453) 140 | * [**CICC 2020**] A 16K Current-Based 8T SRAM Compute-In-Memory Macro with Decoupled Read/Write and 1-5bit Column ADC. 141 | >*Chengshuo Yu, Taegeun Yoo, Tony Tae-Hyoung Kim, et al.* [[Paper]](https://doi.org/10.1109/CICC48029.2020.9075883) 142 | * [**DAC 2020**] Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. 143 | >*Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, et al.* [[Paper]](https://doi.org/10.1109/DAC18072.2020.9218567) 144 | * [**DAC 2020**] A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. 145 | >*Hongwu Jiang, Shanshi Huang, Xiaochen Peng, et al.* [[Paper]](https://doi.org/10.1109/DAC18072.2020.9218524) 146 | * [**DATE 2020**] Robust and High-Performance 12-T Interlocked SRAM for In-Memory Computing. 147 | >*Neelam Surana, Mili Lavania, Abhishek Barma and Joycee Mekie* [[Paper]](https://doi.org/10.23919/DATE48585.2020.9116361) 148 | * [**ICCAD 2020**] XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption. 149 | >*Shanshi Huang, Hongwu Jiang, Xiaochen Peng, et al.* [[Paper]](https://doi.org/10.1145/3400302.3415678) 150 | * [**ICCAD 2020**] Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. 151 | >*Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim* [[Paper]](https://doi.org/10.1145/3400302.3415641) 152 | * [**ISSCC 15.2 2020**] A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. 153 | >*Jian-Wei Su, Xin Si, Yen-Chi Chou, et al.* [[Paper]](https://doi.org/10.1109/ISSCC19947.2020.9062949) 154 | * [**ISSCC 15.3 2020**] A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning 155 | Applications. 156 | >*Qing Dong, Mahmut E. Sinangil, Burak Erbagci, et al.* [[Paper]](https://doi.org/10.1109/ISSCC19947.2020.9062985) 157 | * [**ISSCC 15.5 2020**] A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. 158 | >*Xin Si, Yung-Ning Tu, Wei-Hsing Huang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC19947.2020.9062995) 159 | * [**ISSCC 31.2 2020**] CIM-Spin: A 0.5-to-1.2V Scalable Annealing Processor Using Digital Compute-In-Memory Spin Operators and Register-Based Spins for Combinatorial Optimization Problems. 160 | >*Yuqi Su, Hyunjoon Kim, Bongjin Kim* [[Paper]](https://doi.org/10.1109/ISSCC19947.2020.9062938) 161 | * [**JSSC 2020**] A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. 162 | >*Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.3005754) 163 | * [**JSSC 2020**] C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism. 164 | >*Zhewei Jiang, Shihui Yin, Jae-Sun Seo, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.2992886) 165 | * [**JSSC 2020**] A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. 166 | >*Xin Si, Jia-Jing Chen, Yung-Ning Tu, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2019.2952773) 167 | * [**JSSC 2020**] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. 168 | >*Jingcheng Wang, Xiaowei Wang, Charles Eckert, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2019.2939682) 169 | * [**JSSC 2020**] XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks. 170 | >*Shihui Yin, Zhewei Jiang, Jae-Sun Seo, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2019.2963616) 171 | * [**VLSI 2020**] Z-PIM: An Energy-Efficient Sparsity-Aware Processing-In-Memory Architecture with Fully-Variable Weight Precision. 172 | >*Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, et al.* [[Paper]](https://doi.org/10.1109/VLSICircuits18222.2020.9163015) 173 | * [**JSSC 2019**] CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks. 174 | >*Avishek Biswas, and Anantha P. Chandrakasan* [[Paper]](https://doi.org/10.1109/JSSC.2018.2880918) 175 | 176 | --- 177 | ## Architecture Level 178 | * [**DAC 2025**] Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-Memory. 179 | >*Yi Li, Zijian Ye, Xiangqu Fu, et al.* [[Paper]](https://doi.org/10.1109/DAC63849.2025.11132426) 180 | * [**DAC 2025**] HH-PIM: Dynamic Optimization of Power and Performance with Heterogeneous-Hybrid PIM for Edge AI Devices. 181 | >*Sangmin Jeon, Kangju Lee, Kyeongwon Lee, Woojoo Lee* [[Paper]](https://doi.org/10.1109/DAC63849.2025.11132829) 182 | * [**TCAS-I 2025**] SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. 183 | >*Xiangqu Fu, Jinshan Yue, Muhammad Faizan, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2025.3561245) 184 | * [**TCAS-I 2025**] A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference. 185 | >*Jinkai Wang, Youxiang Chen, Zekun Wang, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2025.3543104) 186 | * [**TCAS-I 2025**] FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration. 187 | >*Vishal Sharma, Xin Zhang, Narendra Singh Dhakad, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2025.3547853) 188 | * [**JSSC 2025**] Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models. 189 | >*Guodong Yin, Yiming Chen, Mingyen Lee, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2025.3556008) 190 | * [**arXiv 2025**] Accelerating LLM Inference with Flexible N: M Sparsity via A Fully Digital Compute-in-Memory Accelerator. 191 | >*Akshat Ramachandran, Souvik Kundu, Arnab Raha, et al.* [[Paper]](https://arxiv.org/abs/2504.14365) 192 | * [**Nature 2025**] A mixed-precision memristor and SRAM compute-in-memory AI processor. 193 | >*W.S. Khwa, T.H. Wen, H.H. Hsu, et al.* [[Paper]](https://doi.org/10.1038/s41586-025-08639-2) 194 | * [**DATE 2025**] SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memory Architecture. 195 | >*Yanfeng Yang, Yi Zou, Zhibiao Xue, et al.* [[Paper]](https://doi.org/10.23919/DATE64628.2025.10993209) 196 | * [**ASPDAC 2025**] A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies. 197 | >*Yitong Zhou, Wente Yi, Sifan Sun, et al.* [[Paper]](https://doi.org/10.1145/3658617.3697580) 198 | * [**ASPDAC 2025**] A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs. 199 | >*Haoxiang Zhou, Zikun Wei, Dingbang Liu, et al.* [[Paper]](https://doi.org/10.1145/3658617.3697682) 200 | * [**TACO 2025**] Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication. 201 | >*Gaoyang Zhao, Qiuran Li, Rongzhen Lin, et al.* [[Paper]](https://doi.org/10.1145/3719654) 202 | * [**TVLSI 2025**] SysCIM: A Heterogeneous Chip Architecture for High-Efficiency CNN Training at Edge. 203 | >*Shuai Wang, Ziwei Li, Yuang Ma, Yi Kang.* [[Paper]](https://doi.org/10.1109/TVLSI.2025.3526363) 204 | * [**HPCA 2025**] ER-DCIM: Error-Resilient Digital CIM Architecture with Run-Time MAC-Cell Error Correction. 205 | >*Zhen He, Yiqi Wang, Zihan Wu, et al.* [[Paper]](https://doi.org/10.1109/HPCA61900.2025.00046) 206 | * [**HPCA 2025**] Multi-Dimensional Vector ISA Extension for Mobile In-Cache Computing. 207 | >*Alireza Khadem, Daichi Fujiki, Hilbert Chen, et al.* [[Paper]](https://ieeexplore.ieee.org/document/10946805/) 208 | * [**DAC 2024**] CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. 209 | >*Zhiheng Yue, Shaojun Wei, Yang Hu, et al.* [[Paper]](https://doi.org/10.1145/3649329.3655689) 210 | * [**DAC 2024**] Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. 211 | >*Xujiang Xiang, Zhiheng Yue, Yuxuan Li, et al.* [[Paper]](https://doi.org/10.1145/3649329.3655690) 212 | * [**DAC 2024**] FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. 213 | >*Bo Liu, Qingwen Wei, Yang Zhang, et al.* [[Paper]](https://doi.org/10.1145/3649329.3656253) 214 | * [**DAC 2024**] AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. 215 | >*Yiqi Jing, Meng Wu, Jiaqi Zhou, et al.* [[Paper]](https://doi.org/10.1145/3649329.3657373) 216 | * [**DAC 2024**] Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. 217 | >*Duan, Cenlin, Jianlei Yang, Yiou Wang, et al.* [[Paper]](https://arxiv.org/abs/2404.09497) 218 | * [**DAC 2024**] Hyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM/SRAM Memory. 219 | >*Fan Zhang, Li Yang, Deliang Fan* [[Paper]](https://doi.org/10.1145/3649329.3657389) 220 | * [**DAC 2024**] Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning. 221 | >*Fan Zhang, Amitesh Sridharan, Wilman Tsai, et al.* [[Paper]](https://doi.org/10.1145/3649329.3657390) 222 | * [**DAC 2024**] An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. 223 | >*Zhiyuan Chen, Yufei Ma, Keyi Li, et al.* [[Paper]](https://doi.org/10.1145/3649329.3658244) 224 | * [**DAC 2024**] HEIRS: Hybrid Three-Dimension RRAM- and SRAM-CIM Architecture for Multi-task Transformer Acceleration. 225 | >*Liukai Xu, Shuai Yuan, Dengfeng Wang, et al.* [[Paper]](https://doi.org/10.1145/3649329.3657327) 226 | * [**DATE 2024**] CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks. 227 | >*Kavitha S, Binsu J Kailath, B. S. Reniwal* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546864) 228 | * [**DATE 2024**] H3DFact: Heterogeneous 3D Integrated CIM for Factorization with Holographic Perceptual Representations. 229 | >*Zishen Wan, Che-Kai Liu, Mohamed Ibrahim, et al.* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546582) 230 | * [**DATE 2024**] AdaP-CIM: Compute-in-Memory Based Neural Network Accelerator Using Adaptive Posit. 231 | >*Jingyu He, Fengbin Tu, Kwang-Ting Cheng, et al.* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546569) 232 | * [**DATE 2024**] DAISM: Digital Approximate In-SRAM Multiplier-Based Accelerator for DNN Training and Inference. 233 | >*L. Sonnino, S. Shresthamali, Y. He, et al.* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546578) 234 | * [**TCAS-I 2024**] DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. 235 | >*Ma, Yufei, Yikan Qiu, Wentao Zhao, et al.* [[Paper]](https://ieeexplore.ieee.org/abstract/document/10500021) 236 | * [**DAC 2023**] BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication. 237 | >*Jingyao Zhang, Mohsen Imani, Elaheh Sadredini* [[Paper]](https://doi.org/10.48550/arXiv.2303.00173) 238 | * [**DAC 2023**] Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture. 239 | >*Yun-Chen Lo, Ren-Shuo Liu* [[Paper]](https://doi.org/10.1109/DAC56929.2023.10247750) 240 | * [**DATE 2023**] Process Variation Resilient Current-Domain Analog In Memory Computing. 241 | >*Kailash Prasad, Sai Shubham, Aditya Biswas, et al.* [[Paper]](https://doi.org/10.23919/DATE56975.2023.10137088) 242 | * [**DATE 2023**] PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM. 243 | >*Kailash Prasad, Aditya Biswas, Arpita Kabra, et al.* [[Paper]](https://doi.org/10.23919/DATE56975.2023.10137338) 244 | * [**HPCA 2023**] EVE: Ephemeral Vector Engines. 245 | >*Khalid Al-Hawaj, Tuan Ta, Nick Cebry, et al.* [[Paper]](https://doi.org/10.1109/HPCA56546.2023.10071074) 246 | * [**HPCA 2023**] Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications. 247 | >*Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, et al.* [[Paper]](https://doi.org/10.1109/HPCA56546.2023.10071089) 248 | * [**ISSCC 16.1 2023**] MuITCIM: A 28nm $2.24 \mu\mathrm{J}$/Token Attention-Token-Bit Hybrid Sparse Digital CIM-Based Accelerator for Multimodal Transformers. 249 | >*Fengbin Tu, Zihan Wu, Yiqi Wang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067842) 250 | * [**ISSCC 16.2 2023**] A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. 251 | >*Shiwei Liu, Peizhe Li, Jinshan Zhang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067360) 252 | * [**ISSCC 16.3 2023**] A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. 253 | >*Jinshan Yue, Chaojie He, Zi Wang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067779) 254 | * [**ISSCC 16.4 2023**] TensorCIM: A 28nm 3.7nJ/Gather and 8.3TFLOPS/W FP32 Digital-CIM Tensor Processor for MCM-CIM-Based Beyond-NN Acceleration. 255 | >*Fengbin Tu, Yiqi Wang, Zihan Wu, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067285) 256 | * [**ISSCC 16.7 2023**] A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications. 257 | >*Giuseppe Desoli, Nitin Chawla, Thomas Boesch, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42615.2023.10067422) 258 | * [**JSSC 2023**] ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration. 259 | >*Fengbin Tu, Yiqi Wang, Zihan Wu, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3222059) 260 | * [**JSSC 2023**] TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. 261 | >*Guo, Ruiqi and Yue, Zhiheng and Si, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3198413) 262 | * [**JSSC 2023**] PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference. 263 | >*Bo Zhang, Shihui Yin, Minkyu Kim, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3211290) 264 | * [**JSSC 2023**] An In-Memory-Computing Charge-Domain Ternary CNN Classifier. 265 | >*Xiangxing Yang, Keren Zhu, Xiyuan Tang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2023.3238725) 266 | * [**JSSC 2023**] TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes. 267 | >*Fengbin Tu, Zihan Wu, Yiqi Wang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2022.3213542) 268 | * [**JSSC 2023**] IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm2 CIM-SRAM With Multi-Bit Analog Batch-Normalization. 269 | >*Adrian Kneip, Martin Lefebvre, Julien Verecken, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2023.3269098) 270 | * [**MICRO 2023**] MVC: Enabling Fully Coherent Multi-Data-Views through the 271 | Memory Hierarchy with Processing in Memory. 272 | >*Daichi Fujiki* [[Paper]](https://doi.org/10.1145/3613424.3623784) 273 | * [**MICRO 2023**] MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference. 274 | >*Renhao Fan, Yikai Cui, Qilin Chen, et al.* [[Paper]](https://doi.org/10.1145/3613424.3614268) 275 | * [**TC 2023**] Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks. 276 | >*Charles Eckert, Arun Subramaniyan, Xiaowei Wang, et al.* [[Paper]](https://doi.org/10.1109/TC.2022.3214151) 277 | * [**TC 2023**] An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array. 278 | >*Sunrui Zhang, Xiaole Cui, Feng Wei, et al.* [[Paper]](https://doi.org/10.1109/TC.2023.3301156) 279 | * [**TCAD 2023**] SDP: Co-Designing Algorithm, Dataflow, and Architecture for in-SRAM Sparse NN Acceleration. 280 | >*Fengbin Tu, Yiqi Wang, Ling Liang, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2022.3172600) 281 | * [**TCAD 2023**] Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units. 282 | >*Kevin Mambu, Henri-Pierre Charles, and Maha Kooli* [[Paper]](https://doi.org/10.1109/TCAD.2023.3258346) 283 | * [**TCAS-I 2023**] SPCIM: Sparsity-Balanced Practical CIM Accelerator With Optimized Spatial-Temporal Multi-Macro Utilization. 284 | >*Yiqi Wang, Fengbin Tu, Leibo Liu, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2022.3216735) 285 | * [**TCAS-I 2023**] ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication 286 | and Parasitic-Capacitance Charge Sharing for AI Edge Application. 287 | >*Chenyang Zhao, Jinbei Fang, Jingwen Jiang, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2022.3215535) 288 | * [**TCAS-I 2023**] MC-CIM: Compute-in-Memory With Monte-Carlo Dropouts for Bayesian Edge Intelligence. 289 | >*Priyesh Shukla, Shamma Nasrin, Nastaran Darabi, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2022.3224703) 290 | * [**TCAS-I 2023**] An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-µs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. 291 | >*Ying Liu, Yufei Ma, Wei He, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2023.3275387) 292 | * [**TCAS-I 2023**] TDPRO: Time-Domain-Based Computing-in Memory Engine for Ultra-Low Power ECG Processor. 293 | >*Liang Chang, Siqi Yang, Zhiyuan Chang, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2023.3294181) 294 | * [**TCAS-I 2023**] WDVR-RAM: A 0.25–1.2 V, 2.6–76 POPS/W Charge-Domain In-Memory-Computing Binarized 295 | CNN Accelerator for Dynamic AIoT Workloads. 296 | >*Hongtu Zhang, Yuhao Shu, Qi Deng, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2023.3294296) 297 | * [**CICC 2022**] T-PIM: A 2.21-to-161.08TOPS/W Processing-In-Memory Accelerator for End-to-End On-Device Training. 298 | >*Jaehoon Heo, Junsoo Kim, Wontak Han, et al.* [[Paper]](https://doi.org/10.1109/CICC53496.2022.9772808) 299 | * [**DAC 2022**] CREAM: Computing in ReRAM-assisted Energy and Area efficient SRAM for Neural Network Acceleration. 300 | >*Liukai Xu, Songyuan Liu, Zhi Li, et al.* [[Paper]](https://doi.org/10.1145/3489517.3530399) 301 | * [**DAC 2022**] Processing-in-SRAM Acceleration for Ultra-Low Power Visual 3D Perception. 302 | >*Yuquan He, Songyun Qu, Gangliang Lin, et al.* [[Paper]](https://doi.org/10.1145/3489517.3530446) 303 | * [**DAC 2022**] MC-CIM: A Reconfigurable Computation-In-Memory For Efficient Stereo Matching Cost Computation. 304 | >*Zhiheng Yue, Yabing Wang, Leibo Liu, et al.* [[Paper]](https://doi.org/10.1145/3489517.3530477) 305 | * [**DATE 2022**] HyperX: A Hybrid RRAM-SRAM partitioned system for error recovery in memristive Xbars. 306 | >*Adarsh Kosta, Efstathia Soufleri, Indranil Chakraborty, et al.* [[Paper]](https://doi.org/10.23919/DATE54114.2022.9774549) 307 | * [**DATE 2022**] AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator. 308 | >*Saeed Seyedfaraji, Baset Mesgari, Semeen Rehman * [[Paper]](https://doi.org/10.23919/DATE54114.2022.9774748) 309 | * [**ISCA 2022**] Gearbox: a case for supporting accumulation dispatching and hybrid partitioning in PIM-based accelerators. 310 | >*Marzieh Lenjani, Alif Ahmed, Mircea Stan, et al.* [[Paper]](https://doi.org/10.1145/3470496.3527402) 311 | * [**ISSCC 15.4 2022**] A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. 312 | >*Muya Chang, Samuel D. Spetalnick, Brian Crafton, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731679) 313 | * [**ISSCC 15.3 2022**] COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. 314 | >*Haozhe Zhu, Bo Jiao, Jinshan Zhang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731657) 315 | * [**ISSCC 15.5 2022**] A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 Reconfigurable Digital CIM Processor with Unified FP/INT Pipeline and Bitwise In-Memory Booth Multiplication for Cloud Deep Learning Acceleration. 316 | >*Fengbin Tu, Yiqi Wang, Zihan Wu, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731762) 317 | * [**ISSCC 29.3 2022**] A 28nm 15.59μJ/Token Full-Digital Bitline-Transpose CIM-Based Sparse Transformer Accelerator with 318 | Pipeline/Parallel Reconfigurable Modes. 319 | >*Fengbin Tu, Zihan Wu, Yiqi Wang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731645) 320 | * [**ISSCC 2022**] DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. 321 | >*Kodai Ueyoshi, Ioannis A. Papistas, Pouya Houshmand, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42614.2022.9731716) 322 | * [**JETC 2022**] Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution. 323 | >*Maha Kooli, Antoine Heraud, Henri-Pierre Charles, et al.* [[Paper]](https://doi.org/10.1145/3485823) 324 | * [**JSSC 2022**] Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing. 325 | >*Hongyang Jia, Murat Ozatay, Yinqi Tang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2021.3119018) 326 | * [**TCAD 2022**] MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks. 327 | >*Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2021.3082107) 328 | * [**TCAS-I 2022**] BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. 329 | >*Zhiheng Yue, Yabing Wang, Yubin Qin, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2022.3185135) 330 | * [**DATE 2021**] Compute-in-Memory Upside Down: A Learning Operator Co-Design Perspective for Scalability. 331 | >*Shamma Nasrin, Priyesh Shukla, Shruthi Jaisimha, et al.* [[Paper]](https://doi.org/10.23919/DATE51398.2021.9474119) 332 | * [**DATE 2021**] Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing. 333 | >*Marco Rios, Flavio Ponzina, Giovanni Ansaloni, et al.* [[Paper]](https://doi.org/10.23919/DATE51398.2021.9474233) 334 | * [**ISSCC 15.1 2021**] A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing. 335 | >*Hongyang Jia, Murat Ozatay, Yinqi Tang, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42613.2021.9365788) 336 | * [**ISSCC 15.2 2021**] A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. 337 | >*Jinshan Yue, Xiaoyu Feng, Yifan He, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42613.2021.9365958) 338 | * [**ISSCC 15.4 2021**] A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-SparsityBased Optimization and Variable-Precision Quantization. 339 | >*Ruiqi Guo, Zhiheng Yue, Xin Si, et al.* [[Paper]](https://doi.org/10.1109/ISSCC42613.2021.9365989) 340 | * [**JSSC 2021**] A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting. 341 | >*Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.3029586) 342 | * [**JSSC 2021**] Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks. 343 | >*Ji-Hoon Kim, Juhyoung Lee, Jinsu Lee, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.3039206) 344 | * [**VLSI JFS2-3 2021**] A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation. 345 | >*Ruiqi Guo, Hao Li, Ruhui Liu, et al.* [[Paper]](https://doi.org/10.23919/VLSICircuits52068.2021.9492492) 346 | * [**CICC 2020**] KeyRAM: A 0.34 uJ/decision 18 k decisions/s Recurrent Attention In-memory Processor for Keyword Spotting. 347 | >*Hassan Dbouk, Sujan K. Gonugondla, Charbel Sakr, et al.* [[Paper]](https://doi.org/10.1109/CICC48029.2020.9075923) 348 | * [**DAC 2020**] Q-PIM: A Genetic Algorithm based Flexible DNN Quantization Method and Application to Processing-In-Memory Platform. 349 | >*Yun Long, Edward Lee, Daehyun Kim, et al.* [[Paper]](https://doi.org/10.1109/DAC18072.2020.9218737) 350 | * [**DATE 2020**] A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning Applications. 351 | >*Dayane Reis, Ann Franchesca Laguna, Michael Niemier, et al.* [[Paper]](https://doi.org/10.23919/DATE48585.2020.9116292) 352 | * [**ISSCC 14.3 2020**] A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse. 353 | >*Jinshan Yue, Zhe Yuan, Xiaoyu Feng, et al.* [[Paper]](https://doi.org/10.1109/ISSCC19947.2020.9062958) 354 | * [**JSSC 2020**] A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing. 355 | >*Hongyang Jia, Hossein Valavi, Yinqi Tang, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2020.2987714) 356 | * [**JSSC 2020**] A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. 357 | >*Takashi Takemoto, Member, IEEE, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2019.2949230) 358 | * [**JSSC 2020**] A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations forProgrammable In-Memory Vector Computing. 359 | >*Jingcheng Wang, Xiaowei Wang, Charles Eckert, et al.* [[Paper]](https://doi.org/10.1109/JSSC.2019.2939682) 360 | * [**MICRO 2020**] CATCAM: Constant-time Alteration Ternary CAM with Scalable In-Memory Architecture. 361 | >*Dibei Chen, Zhaoshi Li, Tianzhu Xiong, et al.* [[Paper]](https://doi.org/10.1109/MICRO50266.2020.00038) 362 | * [**TC 2020**] CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays. 363 | >*Hongwu Jiang, Xiaochen Peng, Shanshi Huang, et al.* [[Paper]](https://doi.org/10.1109/TC.2020.2980533) 364 | * [**DAC 2018**] SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory. 365 | >*Peiqi Wang, Yu Ji, Chi Hong, et al.* [[Paper]](https://doi.org/10.1145/3195970.3196116) 366 | 367 | --- 368 | ## Simulation Tools 369 | * [**DATE 2025**] DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. 370 | >*Chuyu Wang, Ke Hu, Fan Yang, et al.* [[Paper]](https://doi.org/10.23919/DATE64628.2025.10992711) 371 | * [**DATE 2024**] X-PIM: Fast Modeling and Validation Framework for Mixed-Signal Processing-in-Memory Using Compressed Equivalent Model in System Verilog. 372 | >*I. Jeong, J. -E. Park* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546655) 373 | * [**TCAS-I 2024**] NeuroSim V1. 4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node. 374 | >*Lee, Junmo, Anni Lu, Wantong Li, et al.* [[Paper]](https://www.x-mol.com/paper/1761279482257969152) 375 | * [**TCAD 2023**] MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. 376 | >*Zhenhua Zhu, Hanbo Sun, Tongxin Xie, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2023.3251696) [[GitHub]](https://github.com/thu-nics/MNSIM-2.0) 377 | * [**ASPDAC 2021**] DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures. 378 | >*Minxuan Zhou, Mohsen Imani, Yeseong Kim* [[Paper]](https://doi.org/10.1145/3394885.3431525) 379 | * [**FAI 2021**] NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark. 380 | >*Anni Lu, Xiaochen Peng, Wantong Li, et al.* [[Paper]](https://doi.org/10.3389/frai.2021.659060) [[GitHub]](https://github.com/neurosim) 381 | * [**TCAD 2021**] DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training. 382 | >*Xiaochen Peng, Shanshi Huang, Hongwu Jiang, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2020.3043731) [[GitHub]](https://github.com/neurosim/DNN_NeuroSim_V2.1) 383 | * [**TCAD 2020**] Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures. 384 | >*Di Gao, Dayane Reis, Xiaobo Sharon Hu, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2020.2966484) [[GitHub]](https://github.com/skycrapers/Eva-CiM) 385 | 386 | --- 387 | ## Software Stack 388 | * [**DAC 2025**] CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. 389 | >*Yingjie Qi, Jianlei Yang, Yiou Wang, et al.* [[Paper]](https://doi.org/10.1109/DAC63849.2025.11133270) [[GitHub]]((https://github.com/BUAA-CI-LAB/CIMFlow)) 390 | * [**DATE 2025**] SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. 391 | >*Haikang Diao, Haoyi Zhang, Jiahao Song, et al.* [[Paper]](https://doi.org/10.23919/DATE64628.2025.10993192) 392 | * [**TCAD 2025**] Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization. 393 | >*Yongkun Wu, Xiaomeng Wang, Jia Chen, et al.* [[Paper]](https://doi.org/10.1109/TCAD.2025.3565487) 394 | * [**TCAS-I 2025**] A Design Framework of Heterogeneous Approximate DCIM-Based Accelerator for Energy-Efficient NN Processing. 395 | >*Kyeongho Lee, Hyeyeong Lee, Jongsun Park.* [[Paper]](https://doi.org/10.1109/TCSI.2025.3530637) 396 | * [**DAC 2024**] EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. 397 | >*Haoyi Zhang, Jiahao Song, Xiaohan Gao, et al.* [[Paper]](https://doi.org/10.1145/3649329.3656229) 398 | * [**DATE 2024**] A Novel March Test Algorithm for Testing 8T SRAM-Based IMC Architectures. 399 | >*L. Ammoura, M. -L. Flottes, P. Girard, et al.* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546583) 400 | * [**DATE 2024**] PIMLC: Logic Compiler for Bit-Serial Based PIM. 401 | >*C. Tang, C. Nie, W. Qian, et al.* [[Paper]](https://doi.org/10.23919/DATE58400.2024.10546754) 402 | * [**ASPLOS 2024**] CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators. 403 | >*Songyun Qu, Shixin Zhao, Bing Li, et al.* [[Paper]](https://ar5iv.org/abs/2401.12428) 404 | * [**ASPLOS 2023**] Infinity Stream: Portable and Programmer-Friendly In-/Near-Memory Fusion. 405 | >*Zhengrong Wang, Christopher Liu, Aman Arora, et al.* [[Paper]](https://polyarch.cs.ucla.edu/papers/asplos2023-infinity-stream.pdf) 406 | * [**DAC 2023**] AutoDCIM: An Automated Digital CIM Compiler. 407 | >*Jia Chen, Fengbin Tu, Kunming Shao, et al.* [[Paper]](https://doi.org/10.1109/DAC56929.2023.10247976) 408 | * [**DAC 2023**] PIM-HLS: An Automatic Hardware Generation Tool for Heterogeneous 409 | Processing-In-Memory-based Neural Network Accelerators. 410 | >*Yu Zhu, Zhenhua Zhu, Guohao Dai, et al.* [[Paper]](https://doi.org/10.1109/DAC56929.2023.10247755) 411 | * [**ASPDAC 2022**] Optimal Data Allocation for Graph Processing in Processing-in-Memory Systems. 412 | >*Zerun Li, Xiaoming Chen, Yinhe Han* [[Paper]](https://doi.org/10.1109/ASP-DAC52403.2022.9712587) 413 | * [**MICRO 2022**] Multi-Layer In-Memory Processing. 414 | >*Daichi Fujiki, Alireza Khadem, S. Mahlke, et al.* [[Paper]](https://doi.org/10.1109/MICRO56248.2022.00068) 415 | * [**TCAS-I 2022**] Neural Network Training on In-Memory-Computing Hardware With Radix-4 Gradients. 416 | >*Christopher Grimm, and Naveen Verma* [[Paper]](https://doi.org/10.1109/TCSI.2022.3185556) 417 | * [**ASPDAC 2021**] Providing Plug N’ Play for Processing-in-Memory Accelerators. 418 | >*Paulo C. Santos, Bruno E. Forlin, Luigi Carro* [[Paper]](https://doi.org/10.1145/3394885.3431527) 419 | * [**DAC 2021**] Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks. 420 | >*Sai Kiran Cherupally, Adnan Siraj Rakin, Shihui Yin, et al.* [[Paper]](https://doi.org/10.1109/DAC18074.2021.9586233) 421 | * [**DAC 2021**] Invited: Accelerating Fully Homomorphic Encryption with Processing in Memory. 422 | >*Saransh Gupta, Tajana Simunic Rosing* [[Paper]](https://doi.org/10.1109/DAC18074.2021.9586285) 423 | 424 | --- 425 | ## Surveys and Analysis 426 | * [**DAC 2023**] Unified Agile Accuracy Assessment in Computing-in-Memory Neural Accelerators by Layerwise Dynamical Isometry. 427 | >*Xuan-Jun Chen, Cynthia Kuan, Chia-Lin Yang* [[Paper]](https://doi.org/10.1109/DAC56929.2023.10247782) 428 | * [**DAC 2023**] Advances and Trends on On-Chip Compute-in-Memory Macros and Accelerators. 429 | >*Jae-sun Seo* [[Paper]](https://doi.org/10.1109/DAC56929.2023.10248014) 430 | * [**TCAS-I 2022**] A Practical Design-Space Analysis of Compute-in-Memory With SRAM. 431 | >*Samuel Spetalnick, and Arijit Raychowdhury* [[Paper]](https://doi.org/10.1109/TCSI.2021.3138057) 432 | * [**DATE 2021**] Perspectives on Emerging Computation-in-Memory Paradigms. 433 | >*Shubham Rai, Mengyun Liu, Anteneh Gebregiorgis, et al.* [[Paper]](https://doi.org/10.23919/DATE51398.2021.9473976) 434 | * [**DATE 2021**] Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design. 435 | >*Jyotishman Saikia, Shihui Yin, Sai Kiran Cherupally, et al.* [[Paper]](https://doi.org/10.23919/DATE51398.2021.9473973) 436 | * [**TCAS-I 2021**] Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices. 437 | >*Chuan-Jia Jhang, Cheng-Xin Xue, Je-Min Hung, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2021.3064189) 438 | * [**TCAS-I 2021**] Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing. 439 | >*Adrian Kneip, and David Bol* [[Paper]](https://doi.org/10.1109/TCSI.2021.3058510) 440 | * [**TCAS-I 2021**] Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM. 441 | >*Jian Chen, Wenfeng Zhao, Yuqi Wang, et al.* [[Paper]](https://doi.org/10.1109/TCSI.2021.3054972) 442 | * [**ICCAD 2020**] Fundamental Limits on the Precision of In-memory Architectures. 443 | >*Sujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, et al.* [[Paper]](https://doi.org/10.1145/3400302.3416344) 444 | 445 | --- 446 | ## Maintainers 447 | - Yingjie Qi, Beihang University. [[GitHub]](https://github.com/Kevin7Qi) 448 | - Cenlin Duan, Beihang University. [[GitHub]](https://github.com/AuroraSky111) 449 | - Xiaolin He, Beihang University. [[GitHub]](https://github.com/iboxl) 450 | --------------------------------------------------------------------------------