├── P0 ├── CRC校验(P0.Q1).circ ├── P0.md ├── fsm.circ ├── ftoi.circ ├── grf.circ ├── logisim导航(P0.Q3).circ ├── navigation.circ ├── navigation.md ├── 实现GRF(P0.Q2).circ ├── 正则表达式匹配.md └── 状态机.circ ├── P1 ├── P1.Q1.v ├── P1.Q2.v ├── P1.Q3.v ├── P1.Q4.v ├── P1.Q5-string.v └── P1.md ├── P2 ├── Mars4_5.jar ├── P2.md ├── maze.asm ├── 全排列生成.asm ├── 判断回文.asm ├── 判断质数.asm ├── 卷积.asm ├── 矩阵乘法.asm ├── 约瑟夫串.asm └── 迷宫.cpp ├── P3 ├── P3.circ ├── P3_doc_byfzc.pdf └── P3test.circ ├── P4 ├── ALU.v ├── DM.v ├── EXT.v ├── IFU.v ├── IM.v ├── MUX.v ├── P4.md ├── P4_doc_byfzc.pdf ├── PC.v ├── ctroller.v ├── grf.v ├── mips.v ├── mips_tb.v ├── pcCalc.v ├── spliter.v └── 测试脚本文件.zip ├── P5 ├── ALU.v ├── CMP.v ├── D2E.v ├── DM.v ├── E2M.v ├── EXT.v ├── F2D.v ├── GRF.v ├── IM.v ├── M2W.v ├── MIPS_CPU_P5_tb.v ├── MUX.v ├── P5.md ├── P5_doc_fzc.pdf ├── PC.v ├── autotest_P5.zip ├── constants.v ├── controller.v ├── for_MUX.v ├── hazard_Unit.v ├── instr_class.v ├── mips.v ├── pcCalc.v └── 冒险单元.xlsx ├── P6 ├── ALU.v ├── CMP.v ├── D2E.v ├── DM.v ├── E2M.v ├── EXT.v ├── F2D.v ├── GRF.v ├── IM.v ├── M2W.v ├── MIPS_CPU_P5_t6.v ├── MULT_DIV.v ├── MUX.v ├── P6.md ├── P6_doc_fzc.pdf ├── P6指令分类.md ├── PC.v ├── constants.v ├── controller.v ├── data_ext.v ├── for_MUX.v ├── hazard_Unit.v ├── instr_class.v ├── mips.v ├── mipsAutoTest.v ├── p6_fzc2.zip ├── pcCalc.v ├── store_judge.v ├── tb_div_mult.v ├── test.v └── 冒险单元.xlsx ├── P7 ├── ALU.v ├── Bridge.v ├── CMP.v ├── CP0.v ├── D2E.v ├── DM.v ├── E2M.v ├── EXT.v ├── F2D.v ├── GRF.v ├── IM.v ├── L13-MIPS系统结构-V1.pdf ├── L15-支持IO.pdf ├── M2W.v ├── MULT_DIV.v ├── MUX.v ├── Mars.jar ├── P7.md ├── P7_doc_fzc.pdf ├── PC.v ├── Timer.v ├── constants.v ├── controller.v ├── cpu.v ├── data_ext.v ├── for_MUX.v ├── hazard_Unit.v ├── instr_class.v ├── mips.v ├── mips_tb.v ├── pcCalc.v ├── store_judge.v ├── test.v └── test_file.zip ├── Pre ├── 2^n_mod5.circ ├── ALU.v ├── ALU1.v ├── Pre.md ├── alwaysALU.v ├── assignALU.v ├── counting-2.v ├── counting.v ├── counting1.v ├── counting2.v ├── cpu_checker.v ├── cpu_checker_challenge.v ├── febnacci.asm ├── febnacci.circ ├── febonacci_fast.circ ├── gate.circ ├── hamilton.asm ├── hamilton_hacker.asm ├── id_fsm.v ├── jiecheng.asm ├── mips1.asm ├── mips2.asm ├── ram.circ ├── sort.asm ├── swap_byfzc.circ ├── swap_circuit_byfzc.circ ├── toupiaobiaojue.v ├── 八选一选择器完成函数.circ ├── 哈密顿通路.cpp ├── 四进制半加器.v ├── 字符自动机.v ├── 排序电路.circ ├── 斐波那契.circ ├── 时序电路.circ ├── 组合电路.circ └── 组合逻辑作业T6.v ├── README.md └── TestData ├── AutoSpecialJudge1.c ├── AutoSpecialJudge2.c ├── AutoTest.c ├── Mars.jar ├── My_test ├── 1.md ├── 1.txt ├── 2.txt ├── Mars.jar ├── alu.txt ├── ans.txt ├── code.txt ├── instr.asm ├── jump.txt ├── log.txt ├── my.txt ├── run.py ├── test.py ├── test.zip ├── test1.txt ├── test_1 │ ├── testpoint1.asm │ ├── testpoint2.asm │ └── testpoint3.asm ├── test_2 │ ├── testpoint1.asm │ ├── testpoint10.asm │ ├── testpoint11.asm │ ├── testpoint12.asm │ ├── testpoint13.asm │ ├── testpoint14.asm │ ├── testpoint15.asm │ ├── testpoint16.asm │ ├── testpoint17.asm │ ├── testpoint18.asm │ ├── testpoint19.asm │ ├── testpoint2.asm │ ├── testpoint20.asm │ ├── testpoint21.asm │ ├── testpoint22.asm │ ├── testpoint23.asm │ ├── testpoint24.asm │ ├── testpoint25.asm │ ├── testpoint26.asm │ ├── testpoint27.asm │ ├── testpoint28.asm │ ├── testpoint29.asm │ ├── testpoint3.asm │ ├── testpoint4.asm │ ├── testpoint5.asm │ ├── testpoint6.asm │ ├── testpoint7.asm │ ├── testpoint8.asm │ └── testpoint9.asm ├── test_asm.rar ├── test_asm │ ├── 1 │ │ ├── 16LZHtest-AC │ │ │ ├── testpoint1.asm │ │ │ ├── testpoint10.asm │ │ │ ├── testpoint11.asm │ │ │ ├── testpoint12.asm │ │ │ ├── testpoint13.asm │ │ │ ├── testpoint14.asm │ │ │ ├── testpoint15.asm │ │ │ ├── testpoint2.asm │ │ │ ├── testpoint3.asm │ │ │ ├── testpoint4.asm │ │ │ ├── testpoint5.asm │ │ │ ├── testpoint6.asm │ │ │ ├── testpoint7.asm │ │ │ ├── testpoint8.asm │ │ │ └── testpoint9.asm │ │ ├── Forward_rs.asm │ │ ├── Stall-AC │ │ │ ├── stall1.asm │ │ │ ├── stall2.asm │ │ │ ├── stall3.asm │ │ │ ├── stall4.asm │ │ │ ├── stall5.asm │ │ │ └── stall6.asm │ │ ├── bgezal.txt │ │ ├── bgezal2.txt │ │ ├── bgezal2答案.txt │ │ ├── bgezal_2jinzhi.txt │ │ ├── movz.txt │ │ ├── swl&swr&lwl&lwr.asm │ │ ├── 说明.txt │ │ ├── 超强侧movz2jinzhi.txt │ │ ├── 超强测movz1036.asm │ │ └── 超强测movz答案.txt │ ├── MondayCha │ │ ├── testpoint1.asm │ │ ├── testpoint2.asm │ │ ├── testpoint3.asm │ │ ├── testpoint4.asm │ │ ├── testpoint5.asm │ │ ├── testpoint6.asm │ │ └── testpoint7.asm │ ├── aptx-AC │ │ ├── testpoint1.asm │ │ ├── testpoint2.asm │ │ ├── testpoint3.asm │ │ ├── testpoint4.asm │ │ └── testpoint5.asm │ ├── cjb │ │ ├── testpoint1.asm │ │ ├── testpoint2.asm │ │ ├── testpoint3.asm │ │ ├── testpoint4.asm │ │ ├── testpoint5.asm │ │ ├── testpoint6.asm │ │ └── testpoint7.asm │ └── other │ │ ├── testpoint1.asm │ │ ├── testpoint10.asm │ │ ├── testpoint11.asm │ │ ├── testpoint12.asm │ │ ├── testpoint13.asm │ │ ├── testpoint14.asm │ │ ├── testpoint15.asm │ │ ├── testpoint16.asm │ │ ├── testpoint17.asm │ │ ├── testpoint18.asm │ │ ├── testpoint19.asm │ │ ├── testpoint2.asm │ │ ├── testpoint3.asm │ │ ├── testpoint4.asm │ │ ├── testpoint5.asm │ │ ├── testpoint6.asm │ │ ├── testpoint7.asm │ │ ├── testpoint8.asm │ │ └── testpoint9.asm ├── test_info.txt ├── test_succeed │ ├── Forward_rs.asm │ ├── code.asm │ ├── jump.asm │ ├── mips1.asm │ ├── mips3.asm │ ├── strong.asm │ ├── test.asm │ ├── test14.asm │ └── 强测.asm ├── testcode_fullp5 │ ├── testpoint1.asm │ ├── testpoint10.asm │ ├── testpoint11.asm │ ├── testpoint12.asm │ ├── testpoint13.asm │ ├── testpoint14.asm │ ├── testpoint15.asm │ ├── testpoint16.asm │ ├── testpoint17.asm │ ├── testpoint18.asm │ ├── testpoint19.asm │ ├── testpoint2.asm │ ├── testpoint20.asm │ ├── testpoint21.asm │ ├── testpoint22.asm │ ├── testpoint23.asm │ ├── testpoint24.asm │ ├── testpoint25.asm │ ├── testpoint26.asm │ ├── testpoint27.asm │ ├── testpoint28.asm │ ├── testpoint29.asm │ ├── testpoint3.asm │ ├── testpoint30.asm │ ├── testpoint31.asm │ ├── testpoint32.asm │ ├── testpoint33.asm │ ├── testpoint34.asm │ ├── testpoint35.asm │ ├── testpoint36.asm │ ├── testpoint37.asm │ ├── testpoint38.asm │ ├── testpoint39.asm │ ├── testpoint4.asm │ ├── testpoint40.asm │ ├── testpoint41.asm │ ├── testpoint42.asm │ ├── testpoint43.asm │ ├── testpoint44.asm │ ├── testpoint45.asm │ ├── testpoint46.asm │ ├── testpoint47.asm │ ├── testpoint48.asm │ ├── testpoint49.asm │ ├── testpoint5.asm │ ├── testpoint50.asm │ ├── testpoint6.asm │ ├── testpoint7.asm │ ├── testpoint8.asm │ └── testpoint9.asm ├── testpoint1.asm ├── testpoint15.asm ├── testpoint16.asm ├── testpoint2.asm ├── testpoint23.asm ├── testpoint28.asm ├── testpoint29.asm ├── testpoint3.asm ├── testpoint4.asm ├── testpoint5.asm ├── testpoint6.asm └── 综合测试.asm ├── SpecialJudge.c ├── ch_test.zip ├── p7_test.zip ├── test ├── t1.asm ├── t2.asm └── t3.asm └── testcode_fullp5 ├── testpoint1.asm ├── testpoint10.asm ├── testpoint11.asm ├── testpoint12.asm ├── testpoint13.asm ├── testpoint14.asm ├── testpoint15.asm ├── testpoint16.asm ├── testpoint17.asm ├── testpoint18.asm ├── testpoint19.asm ├── testpoint2.asm ├── testpoint20.asm ├── testpoint21.asm ├── testpoint22.asm ├── testpoint23.asm ├── testpoint24.asm ├── testpoint25.asm ├── testpoint26.asm ├── testpoint27.asm ├── testpoint28.asm ├── testpoint29.asm ├── testpoint3.asm ├── testpoint30.asm ├── testpoint31.asm ├── testpoint32.asm ├── testpoint33.asm ├── testpoint34.asm ├── testpoint35.asm ├── testpoint36.asm ├── testpoint37.asm ├── testpoint38.asm ├── testpoint39.asm ├── testpoint4.asm ├── testpoint40.asm ├── testpoint41.asm ├── testpoint42.asm ├── testpoint43.asm ├── testpoint44.asm ├── testpoint45.asm ├── testpoint46.asm ├── testpoint47.asm ├── testpoint48.asm ├── testpoint49.asm ├── testpoint5.asm ├── testpoint50.asm ├── testpoint6.asm ├── testpoint7.asm ├── testpoint8.asm └── testpoint9.asm /P0/P0.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P0/navigation.md: -------------------------------------------------------------------------------- 1 | x B 2 | 3 | x x 4 | 5 | A 6 | 7 | 3 4 8 | 9 | 1 2 10 | 11 | 0 12 | 13 | 00 north 01 east 10 south 11 west 14 | 15 | | dir[0] | dir[1] | state | state' | arrive | hit | 16 | | :----: | :----: | :---: | :----: | :----: | :--: | 17 | | 0 | 0 | 0 | 1 | 0 | 0 | 18 | | 0 | 1 | 0 | 0 | 0 | 1 | 19 | | 1 | 0 | 0 | 0 | 0 | 1 | 20 | | 1 | 1 | 0 | 0 | 0 | 1 | 21 | | 0 | 0 | 1 | 3 | 0 | 0 | 22 | | 0 | 1 | 1 | 2 | 0 | 0 | 23 | | 1 | 0 | 1 | 0 | 0 | 0 | 24 | | 1 | 1 | 1 | 1 | 0 | 1 | 25 | | 0 | 0 | 2 | 4 | 1 | 0 | 26 | | 0 | 1 | 2 | 2 | 0 | 1 | 27 | | 1 | 0 | 2 | 2 | 0 | 1 | 28 | | 1 | 1 | 2 | 1 | 0 | 0 | 29 | | 0 | 0 | 3 | 3 | 0 | 1 | 30 | | 0 | 1 | 3 | 4 | 1 | 0 | 31 | | 1 | 0 | 3 | 1 | 0 | 0 | 32 | | 1 | 1 | 3 | 3 | 0 | 1 | 33 | | | | 4 | 0 | 1 | 0 | 34 | | | | | | | | 35 | | | | | | | | 36 | | | | | | | | 37 | 38 | -------------------------------------------------------------------------------- /P0/正则表达式匹配.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | | s \| c out | 00 | 01 | 10 | 11 | z | 4 | | :----------: | :--: | :--: | :--: | :--: | :--: | 5 | | 0 | 0 | 1 | 0 | 0 | 0 | 6 | | 1 | 2 | 1 | 2 | 0 | 0 | 7 | | 2 | 3 | 0 | 3 | 0 | 0 | 8 | | 3 | 0 | 1 | 0 | 0 | 1 | 9 | 10 | -------------------------------------------------------------------------------- /P1/P1.Q1.v: -------------------------------------------------------------------------------- 1 | module splitter( 2 | input [31:0] A, 3 | output [7:0] O1, 4 | output [7:0] O2, 5 | output [7:0] O3, 6 | output [7:0] O4 7 | ); 8 | assign O1=A[31:24]; 9 | assign O2=A[23:16]; 10 | assign O3=A[15:8]; 11 | assign O4=A[7:0]; 12 | endmodule -------------------------------------------------------------------------------- /P1/P1.Q2.v: -------------------------------------------------------------------------------- 1 | module alu( 2 | input [31:0] A, 3 | input [31:0] B, 4 | input [2:0] ALUOp, 5 | output reg [31:0] C 6 | ); 7 | 8 | 9 | always@(*) begin 10 | case(ALUOp) 11 | 0: begin 12 | C=A+B; 13 | end 14 | 1: begin 15 | C=A-B; 16 | end 17 | 2: begin 18 | C=A&B; 19 | end 20 | 3: begin 21 | C=A|B; 22 | end 23 | 4: begin 24 | C=A>>B; 25 | end 26 | 5: begin 27 | C=($signed(A))>>>B; 28 | end 29 | default: begin 30 | C=C; 31 | end 32 | endcase 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /P1/P1.Q3.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ext( 3 | input [15:0] imm, 4 | input [1:0] EOp, 5 | output reg [31:0] ext 6 | ); 7 | reg [31:0] t; 8 | always@(*) begin 9 | case(EOp) 10 | 0:begin 11 | ext={{16{imm[15]}},imm}; 12 | end 13 | 1:begin 14 | ext={{16{0}},imm}; 15 | end 16 | 2:begin 17 | ext={imm,{16{0}}}; 18 | end 19 | 3:begin 20 | t={{16{imm[15]}},imm}; 21 | ext=t<<2; 22 | end 23 | endcase 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /P1/P1.Q4.v: -------------------------------------------------------------------------------- 1 | `define s0 3'b000 2 | `define s1 3'b001 3 | `define s2 3'b011 4 | `define s3 3'b010 5 | `define s4 3'b110 6 | `define s5 3'b111 7 | `define s6 3'b101 8 | `define s7 3'b100 9 | 10 | module gray( 11 | input Clk, 12 | input Reset, 13 | input En, 14 | output reg [2:0] Output=0, 15 | output reg Overflow=0 16 | ); 17 | 18 | always@(posedge Clk) begin 19 | if(Reset) begin 20 | Output<=0; 21 | Overflow<=0; 22 | end 23 | else if(En) begin 24 | case(Output) 25 | `s0:begin 26 | Output<=`s1; 27 | end 28 | `s1:begin 29 | Output<=`s2; 30 | end 31 | `s2:begin 32 | Output<=`s3; 33 | end 34 | `s3:begin 35 | Output<=`s4; 36 | end 37 | `s4:begin 38 | Output<=`s5; 39 | end 40 | `s5:begin 41 | Output<=`s6; 42 | end 43 | `s6:begin 44 | Output<=`s7; 45 | end 46 | `s7:begin 47 | Output<=`s0; 48 | if(Overflow==0) Overflow<=1; 49 | end 50 | endcase 51 | end 52 | end 53 | 54 | endmodule 55 | -------------------------------------------------------------------------------- /P1/P1.Q5-string.v: -------------------------------------------------------------------------------- 1 | module string( 2 | input clk, 3 | input clr, 4 | input [7:0] in, 5 | output out 6 | ); 7 | reg st=0;//是否是第一个字符 8 | reg [7:0] lastc; 9 | reg o; 10 | reg[3:0] s; 11 | function isnum(); 12 | input [7:0] c; 13 | isnum=((c>="0")&&(c<="9")); 14 | endfunction; 15 | function isop(); 16 | input [7:0] c; 17 | isop=((c=="+")||(c=="*")); 18 | endfunction 19 | function[1:0] is(); 20 | input [7:0] c; 21 | begin 22 | if(isnum(c)) is=1; 23 | else if(isop(c)) is=2; 24 | else is=0; 25 | end 26 | endfunction 27 | assign out=o; 28 | always @(posedge clk,posedge clr) begin 29 | if(clr) begin 30 | st=0; 31 | lastc=0; 32 | o=0; 33 | s=0; 34 | end 35 | else if(st==0)begin 36 | st=1; 37 | if(isnum(in))begin 38 | s=1; 39 | end 40 | else begin 41 | s=2; 42 | end 43 | end 44 | else begin 45 | if(s!=2) begin 46 | if((is(in)==is(lastc))||(!is(in))) begin 47 | s=2; 48 | end 49 | else if(isop(in)) begin 50 | s=3; 51 | end 52 | else begin 53 | s=1; 54 | end 55 | end 56 | end 57 | lastc=in; 58 | o=(s==1)?1:0; 59 | end 60 | endmodule 61 | -------------------------------------------------------------------------------- /P1/P1.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P2/Mars4_5.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P2/Mars4_5.jar -------------------------------------------------------------------------------- /P2/P2.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P2/maze.asm: -------------------------------------------------------------------------------- 1 | .data 2 | a: .word 100 3 | 4 | .text 5 | .macro getindex(%data,%i,%j,%rank) 6 | mult %i %rank 7 | mflo %data 8 | add %data %data %j 9 | sll %data %data 2 10 | .end_macro 11 | 12 | li $v0 5 13 | syscall 14 | move $s0 $v0 #-->n 15 | li $v0 5 16 | syscall 17 | move $s1 $v0 #-->m 18 | 19 | li $t0 1 #t0-->i 20 | li $t1 1 #t1-->j 21 | li $s7 0 #s7-->cnt 22 | 23 | for_i_1: 24 | bgt $t0 $s0 for_i_1end 25 | for_j_1: 26 | bgt $t1 $s1 for_j_1end 27 | getindex($t2,$t0,$t1,$s1) 28 | li $v0 5 29 | syscall 30 | sw $v0 a($t2) 31 | addi $t1 $t1 1 32 | j for_j_1 33 | for_j_1end: 34 | li $t1 1 35 | addi $t0 $t0 1 36 | j for_i_1 37 | for_i_1end: 38 | 39 | li $v0 5 40 | syscall 41 | move $s2 $v0 #beginx 42 | li $v0 5 43 | syscall 44 | move $s3 $v0 #beginy 45 | li $v0 5 46 | syscall 47 | move $s4 $v0 #endx 48 | li $v0 5 49 | syscall 50 | move $s5 $v0 #endy 51 | move $a0 $s2 52 | move $a1 $s3 53 | move $a2 $s4 54 | move $a3 $s5 55 | jal way 56 | move $a0 $s7 57 | li $v0 1 58 | syscall 59 | li $v0 10 60 | syscall 61 | 62 | way: 63 | if_i_end: 64 | bne $a0 $a2 else 65 | bne $a1 $a3 else 66 | addi $s7 $s7 1 67 | jr $ra 68 | else: 69 | li $t1 1 70 | getindex($t2,$a0,$a1,$s1) 71 | sw $t1 a($t2) 72 | sll $t1 $t1 2 73 | li $t0 0 #t0-->i 74 | for_i_2: 75 | beq $t0 $t1 for_i_2end 76 | li $t2 1 77 | li $t3 2 78 | move $t8 $a0 #sti 79 | move $t9 $a1 #stj 80 | case0: 81 | bnez $t0 case1 82 | addi $t9 $a1 1 83 | j pro 84 | case1: 85 | bne $t0 $t2 case2 86 | addi $t8 $a0 1 87 | j pro 88 | case2: 89 | bne $t0 $t3 case3 90 | subi $t9 $a1 1 91 | j pro 92 | case3: 93 | subi $t8 $a0 1 94 | j pro 95 | 96 | pro: 97 | blt $t8 $t2 next 98 | bgt $t8 $s0 next 99 | blt $t9 $t2 next 100 | bgt $t9 $s1 next 101 | getindex($t3,$t8,$t9,$s1) 102 | lw $t2 a($t3) 103 | bnez $t2 next 104 | li $t2 1 105 | sw $t2 a($t3) 106 | 107 | sw $a0 0($sp) 108 | subi $sp $sp 4 109 | sw $a1 0($sp) 110 | subi $sp $sp 4 111 | sw $t3 0($sp) 112 | subi $sp $sp 4 113 | sw $ra 0($sp) 114 | subi $sp $sp 4 115 | sw $t0 0($sp) 116 | subi $sp $sp 4 117 | 118 | move $a0 $t8 119 | move $a1 $t9 120 | 121 | jal way 122 | 123 | addi $sp $sp 4 124 | lw $t0 0($sp) 125 | addi $sp $sp 4 126 | lw $ra 0($sp) 127 | addi $sp $sp 4 128 | lw $t3 0($sp) 129 | addi $sp $sp 4 130 | lw $a1 0($sp) 131 | addi $sp $sp 4 132 | lw $a0 0($sp) 133 | 134 | sw $0 a($t3) 135 | next: 136 | addi $t0 $t0 1 137 | j for_i_2 138 | for_i_2end: 139 | jr $ra 140 | 141 | 142 | 143 | -------------------------------------------------------------------------------- /P2/全排列生成.asm: -------------------------------------------------------------------------------- 1 | .data 2 | symbol:.space 28 3 | a:.space 28 4 | space: .asciiz " " 5 | ln: .asciiz"\n" 6 | 7 | .text 8 | 9 | main: 10 | li $v0 5 11 | syscall 12 | move $s0 $v0 #s0-->n 13 | move $a0 $0 14 | jal fullarray 15 | li $v0 10 16 | syscall 17 | 18 | fullarray: 19 | li $t0 0 #t0--i 20 | move $s1 $a0 21 | blt $a0 $s0 for_i_begin 22 | for_i_1: 23 | beq $t0 $s0 for_i_1end 24 | li $t1 4 25 | mult $t0 $t1 26 | mflo $t1 27 | lw $a0 a($t1) 28 | li $v0 1 29 | syscall 30 | la $a0 space 31 | li $v0 4 32 | syscall 33 | addi $t0 $t0 1 34 | j for_i_1 35 | for_i_1end: 36 | la $a0 ln 37 | li $v0 4 38 | syscall 39 | move $a0 $s1 40 | jr $ra 41 | 42 | for_i_begin: 43 | li $t0 0 44 | for_i: 45 | beq $t0 $s0 for_i_end 46 | 47 | li $t1 4 48 | mult $t0 $t1 49 | mflo $t3 #t3=4*i 50 | li $t1 1 51 | lw $t1 symbol($t3) 52 | bnez $t1 next 53 | 54 | li $t1 4 55 | multu $a0 $t1 56 | mflo $t1 #t1=4*index 57 | addi $t2 $t0 1 58 | sw $t2 a($t1) 59 | li $t2 1 60 | sw $t2 symbol($t3) 61 | 62 | sw $ra 0($sp) 63 | subi $sp $sp 4 64 | sw $a0 0($sp) 65 | subi $sp $sp 4 66 | sw $t0 0($sp) 67 | subi $sp $sp 4 68 | sw $t3 0($sp) 69 | subi $sp $sp 4 70 | 71 | addi $a0 $a0 1 72 | jal fullarray 73 | 74 | addi $sp $sp 4 75 | lw $t3 0($sp) 76 | addi $sp $sp 4 77 | lw $t0 0($sp) 78 | addi $sp $sp 4 79 | lw $a0 0($sp) 80 | addi $sp $sp 4 81 | lw $ra 0($sp) 82 | 83 | sw $0 symbol($t3) 84 | 85 | next: 86 | addi $t0 $t0 1 87 | j for_i 88 | for_i_end: 89 | jr $ra 90 | 91 | 92 | -------------------------------------------------------------------------------- /P2/判断回文.asm: -------------------------------------------------------------------------------- 1 | .data 2 | str:.byte 20 3 | ln:.asciiz "\n" 4 | 5 | .text 6 | li $v0 5 7 | syscall 8 | move $s0 $v0 #s0-->n 9 | 10 | li $t0 0 #t0-->i 11 | for_i_1: 12 | beq $t0 $s0 for_i_1end 13 | li $v0 12 14 | syscall 15 | sb $v0 str($t0) 16 | addi $t0 $t0 1 17 | j for_i_1 18 | for_i_1end: 19 | 20 | 21 | li $t0 0 #t0-->i 22 | div $s1 $s0 2 23 | subi $s2 $s0 1 24 | for_i_2: 25 | beq $t0 $s1 for_i_2end 26 | lb $t1 str($t0) 27 | sub $t2 $s2 $t0 28 | lb $t2 str($t2) 29 | bne $t2 $t1 end0 30 | addi $t0 $t0 1 31 | j for_i_2 32 | for_i_2end: 33 | j end1 34 | 35 | end0: 36 | li $a0 0 37 | j end 38 | end1: 39 | li $a0 1 40 | j end 41 | 42 | end: 43 | li $v0 1 44 | syscall 45 | 46 | li $v0 10 47 | syscall 48 | 49 | 50 | 51 | 52 | -------------------------------------------------------------------------------- /P2/判断质数.asm: -------------------------------------------------------------------------------- 1 | .text 2 | li $v0 5 3 | syscall 4 | move $s0 $v0 5 | blt $s0 2 print0 6 | li $t0 2 #t0-->i 7 | for_i_1: 8 | beq $t0 $s0 for_i_1end 9 | div $s0 $t0 10 | mfhi $t1 11 | beqz $t1 print0 12 | addi $t0 $t0 1 13 | j for_i_1 14 | for_i_1end: 15 | 16 | print1: 17 | li $a0 1 18 | li $v0 1 19 | syscall 20 | j end 21 | 22 | print0: 23 | li $a0 0 24 | li $v0 1 25 | syscall 26 | j end 27 | 28 | end: 29 | li $v0 10 30 | syscall 31 | 32 | 33 | -------------------------------------------------------------------------------- /P2/卷积.asm: -------------------------------------------------------------------------------- 1 | .data 2 | a:.space 400 3 | conv:.space 400 4 | space:.asciiz" " 5 | ln:.asciiz"\n" 6 | .text 7 | .macro getad(%ad,%i,%j,%rank,%ele,%tmp) 8 | multu %i %rank 9 | mflo %ad 10 | multu %j %ele 11 | mflo %tmp 12 | add %ad %ad %tmp 13 | .end_macro 14 | input_m1n1m2n2: #m1-s0 n1-s1 m2-s2 n2-s3 15 | li $v0 5 16 | syscall 17 | move $s0 $v0 18 | li $v0 5 19 | syscall 20 | move $s1 $v0 21 | li $v0 5 22 | syscall 23 | move $s2 $v0 24 | li $v0 5 25 | syscall 26 | move $s3 $v0 27 | 28 | li $s4 4 #ele 29 | mult $s1 $s4 30 | mflo $s5 #4*n1 31 | mult $s3 $s4 32 | mflo $s6 #4*n2 33 | 34 | input_a_conv: 35 | li $t0 0 36 | li $t1 0 #t0-i t1-j t2-address 37 | for_i_1: 38 | beq $t0 $s0 for_i_1end 39 | for_j_1: 40 | beq $t1 $s1 for_j_1end 41 | li $v0 5 42 | syscall 43 | getad($t2,$t0,$t1,$s5,$s4,$s7) 44 | sw $v0 a($t2) 45 | addiu $t1 $t1 1 46 | j for_j_1 47 | for_j_1end:li $t1 0 48 | addiu $t0 $t0 1 49 | j for_i_1 50 | for_i_1end: 51 | 52 | li $t0 0 53 | li $t1 0 #t0-i t1-j t2-address 54 | for_i_2: 55 | beq $t0 $s2 for_i_2end 56 | for_j_2: 57 | beq $t1 $s3 for_j_2end 58 | li $v0 5 59 | syscall 60 | #subi $t3 $s2 1 61 | #subi $t4 $s3 1 62 | #sub $t3 $t3 $t0 63 | #sub $t4 $t4 $t1 64 | getad($t2,$t0,$t1,$s6,$s4,$s7) 65 | sw $v0 conv($t2) 66 | addiu $t1 $t1 1 67 | j for_j_2 68 | for_j_2end:li $t1 0 69 | addiu $t0 $t0 1 70 | j for_i_2 71 | for_i_2end: 72 | 73 | calculate_output: 74 | sub $t6 $s0 $s2 #t6--m1-m2+1 75 | addi $t6 $t6 1 76 | sub $t7 $s1 $s3 #t7--n1-n2+1 77 | addi $t7 $t7 1 78 | li $t0 0 79 | li $t1 0 #t0-i t1-j t2-k t3-l 80 | li $t2 0 81 | li $t3 0 82 | li $a2 0 83 | for_i_3: 84 | beq $t0 $t6 for_i_3end 85 | for_j_3: 86 | beq $t1 $t7 for_j_3end 87 | for_k: 88 | beq $t2 $s2 for_k_end 89 | for_l: 90 | beq $t3 $s3 for_l_end 91 | getad($t4,$t2,$t3,$s6,$s4,$s7) 92 | add $t8 $t0 $t2 93 | add $t9 $t1 $t3 94 | getad($t5,$t8,$t9,$s5,$s4,$s7) 95 | lw $t8 a($t5) 96 | lw $t9 conv($t4) 97 | multu $t8 $t9 98 | mflo $t8 #t8=a[k+i][l+j]*conv[k][l] 99 | add $a2 $a2 $t8 100 | addi $t3 $t3 1 101 | j for_l 102 | for_l_end: li $t3 0 103 | addi $t2 $t2 1 104 | j for_k 105 | for_k_end: li $t2 0 106 | move $a0 $a2 107 | li $v0 1 108 | syscall 109 | la $a0 space 110 | li $v0 4 111 | syscall 112 | li $a2 0 113 | addiu $t1 $t1 1 114 | j for_j_3 115 | for_j_3end:li $t1 0 116 | la $a0 ln 117 | li $v0 4 118 | syscall 119 | addiu $t0 $t0 1 120 | j for_i_3 121 | for_i_3end: 122 | 123 | li $v0 10 124 | syscall 125 | -------------------------------------------------------------------------------- /P2/矩阵乘法.asm: -------------------------------------------------------------------------------- 1 | .data 2 | a:.space 64 3 | b1:.space 64 4 | c:.space 256 5 | space: .asciiz " " 6 | ln: .asciiz "\n" 7 | .text 8 | .macro calc_addr(%dst,%row,%column,%rank) 9 | multu %row %rank 10 | mflo %dst 11 | addu %dst %dst %column 12 | .end_macro 13 | 14 | li $v0 5 15 | syscall 16 | move $t0 $v0 #v0-->n 17 | li $t1 0 #t1-->i 18 | li $t2 0 #t2-->j t3-->address t4-->data 19 | for_i: 20 | beq $t1 $t0 for_i_end 21 | for_j: 22 | beq $t2 $t0 for_j_end 23 | 24 | calc_addr($t3,$t1,$t2,$t0) 25 | li $v0 5 26 | syscall 27 | move $t4 $v0 28 | sb $t4 a($t3) #input a[i][j] 29 | 30 | addi $t2 $t2 1 #j++ 31 | j for_j 32 | for_j_end: 33 | addi $t1 $t1 1#i++ 34 | li $t2 0 35 | j for_i 36 | for_i_end: 37 | 38 | 39 | li $t1 0 #t1-->i 40 | li $t2 0 #t2-->j t3-->address t4-->data 41 | for_i_1: 42 | beq $t1 $t0 for_i_1_end 43 | for_j_1: 44 | beq $t2 $t0 for_j_1_end 45 | 46 | calc_addr($t3,$t1,$t2,$t0) 47 | li $v0 5 48 | syscall 49 | move $t4 $v0 50 | sb $t4 b1($t3) #input a[i][j] 51 | 52 | addi $t2 $t2 1 #j++ 53 | j for_j_1 54 | for_j_1_end: 55 | addi $t1 $t1 1#i++ 56 | li $t2 0 57 | j for_i_1 58 | for_i_1_end: 59 | 60 | 61 | li $t1 0 #t1-->i 62 | li $t2 0 #t2-->j t3-->k t4-->c[i][j] 63 | li $s1 4 #s1--> size of an element of c 64 | multu $s1 $t0 65 | mflo $s0 #s0-->n*4 66 | 67 | for_i_2: 68 | beq $t1 $t0 for_i_2_end 69 | for_j_2: 70 | beq $t2 $t0 for_j_2_end 71 | li $t3 0 72 | li $t4 0 73 | for_k: 74 | beq $t3 $t0 for_k_end 75 | calc_addr($t5,$t1,$t3,$t0) 76 | calc_addr($t6,$t3,$t2,$t0) 77 | lb $s1 a($t5) 78 | lb $s2 b1($t6) 79 | multu $s1 $s2 80 | mflo $s3 81 | add $t4 $t4 $s3 82 | addiu $t3 $t3 1 83 | j for_k 84 | for_k_end: 85 | #multu $t1 $s0 86 | #mflo $t5 87 | #multu $t2 $s1 88 | #mflo $t6 89 | #addu $t5 $t5 $t6 90 | move $a0 $t4 91 | li $v0 1 92 | syscall 93 | la $a0 space 94 | li $v0 4 95 | syscall 96 | addi $t2 $t2 1 #j++ 97 | li $t3 0 98 | j for_j_2 99 | for_j_2_end: 100 | la $a0 ln 101 | li $v0 4 102 | syscall 103 | addi $t1 $t1 1#i++ 104 | li $t2 0 105 | j for_i_2 106 | for_i_2_end: 107 | 108 | 109 | 110 | li $v0,10 111 | syscall 112 | 113 | 114 | 115 | 116 | -------------------------------------------------------------------------------- /P2/约瑟夫串.asm: -------------------------------------------------------------------------------- 1 | .data 2 | a: .word 100 3 | 4 | .text 5 | li $v0 5 6 | syscall 7 | move $s0 $v0 #s0-->n 8 | li $v0 5 9 | syscall 10 | move $s1 $v0 #s1-->m 11 | 12 | li $t0 0 13 | li $t1 1 14 | li $t2 0 15 | li $t5 1 16 | for_i: 17 | beq $t0 $s0 for_iend 18 | for_j: 19 | beq $t2 $s1 for_jend 20 | beqz $t2 while 21 | blt $t1 $s0 add2 22 | li $t1 1 23 | j while 24 | add2:addi $t1 $t1 1 25 | while: 26 | sll $t4 $t1 2 27 | lw $t3 a($t4) 28 | beqz $t3 whileend 29 | blt $t1 $s0 add1 30 | li $t1 1 31 | j next 32 | add1:addi $t1 $t1 1 33 | next:j while 34 | whileend: 35 | addi $t2 $t2 1 36 | j for_j 37 | for_jend: 38 | sll $t4 $t1 2 39 | li $t5 1 40 | sw $t5 a($t4) 41 | move $a0 $t1 42 | li $v0 1 43 | syscall 44 | addi $t0 $t0 1 45 | li $t2 0 46 | j for_i 47 | for_iend: 48 | 49 | li $v0 10 50 | syscall 51 | 52 | -------------------------------------------------------------------------------- /P2/迷宫.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | using namespace std; 4 | int a[8][8]; 5 | int cnt=0; 6 | int n,m; 7 | int to[4][2]={ 8 | {0,1}, 9 | {1,0}, 10 | {0,-1}, 11 | {-1,0} 12 | }; 13 | void way(int sti,int stj,int edi,int edj){ 14 | if(sti==edi&&stj==edj){ 15 | cnt++; 16 | return; 17 | } 18 | else { 19 | a[sti][stj]=1; 20 | for(int i=0;i<4;i++){ 21 | int nexti=sti+to[i][0]; 22 | int nextj=stj+to[i][1]; 23 | if(nexti>=1&&nexti<=n&&nextj>=1&&nextj<=m&&a[nexti][nextj]==0){ 24 | a[nexti][nextj]=1; 25 | way(nexti,nextj,edi,edj); 26 | a[nexti][nextj]=0; 27 | } 28 | } 29 | } 30 | return; 31 | } 32 | int main() 33 | { 34 | cin>>n>>m; 35 | for(int i=1;i<=n;i++){ 36 | for(int j=1;j<=m;j++){ 37 | cin>>a[i][j]; 38 | } 39 | } 40 | int beginx,beginy,endx,endy; 41 | cin>>beginx>>beginy>>endx>>endy; 42 | way(beginx,beginy,endx,endy); 43 | printf("%d",cnt); 44 | 45 | return 0; 46 | } 47 | -------------------------------------------------------------------------------- /P3/P3_doc_byfzc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P3/P3_doc_byfzc.pdf -------------------------------------------------------------------------------- /P4/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:21:45 11/14/2020 7 | // Design Name: 8 | // Module Name: ALU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module ALU( 22 | input [31:0] dataA, 23 | input [31:0] dataB, 24 | input [2:0] aluCtrl, 25 | output reg [31:0] result, 26 | output reg zero 27 | ); 28 | always@(*)begin 29 | case(aluCtrl) 30 | 3'b000:begin //& 31 | result = dataA&dataB; 32 | end 33 | 3'b001:begin //| 34 | result = dataA|dataB; 35 | end 36 | 3'b010:begin //+ 37 | result = dataA+dataB; 38 | end 39 | 3'b011:begin //- 40 | result = dataA-dataB; 41 | end 42 | default:begin 43 | result = result; 44 | end 45 | endcase 46 | zero=(dataA==dataB); 47 | end 48 | endmodule 49 | -------------------------------------------------------------------------------- /P4/DM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:59:13 11/14/2020 7 | // Design Name: 8 | // Module Name: DM 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module DM( 22 | input [31:0] A, 23 | input [31:0] WD, 24 | output [31:0] RD, 25 | input RE, 26 | input WE, 27 | input clk, 28 | input reset, 29 | input [31:0] pc 30 | ); 31 | reg [31:0] dm [0:1023]; 32 | wire [11:2] addr; 33 | assign addr=A[11:2]; 34 | integer i=0; 35 | assign RD=RE?dm[addr]:RD; 36 | always@(posedge clk)begin 37 | if(reset)begin 38 | for(i=0;i<=10'h3ff;i=i+1)begin 39 | dm[i]<=0; 40 | end 41 | end 42 | else begin 43 | if(WE)begin 44 | dm[addr]<=WD; 45 | end 46 | else begin 47 | dm[addr]<=dm[addr]; 48 | end 49 | end 50 | end 51 | 52 | always@(posedge clk)begin 53 | if(WE & ~reset)begin 54 | $display("@%h: *%h <= %h", pc, A, WD); 55 | end 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /P4/EXT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:34:39 11/14/2020 7 | // Design Name: 8 | // Module Name: EXT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module EXT( 22 | input [15:0] in, 23 | input extOp, 24 | output reg [31:0] out 25 | ); 26 | always@(*)begin 27 | case(extOp) 28 | 0:begin 29 | out={{16{in[15]}},in}; 30 | end 31 | 1:begin 32 | out={{16{1'b0}},in}; 33 | end 34 | default:out=out; 35 | endcase 36 | end 37 | endmodule 38 | -------------------------------------------------------------------------------- /P4/IFU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:44:13 11/14/2020 7 | // Design Name: 8 | // Module Name: IFU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module IFU( 22 | input clk, 23 | input reset, 24 | input zero, 25 | input branch, 26 | output reg [31:0] instr, 27 | input [31:0] imm, 28 | output reg [31:0] pcPlus4, 29 | input jump 30 | ); 31 | reg [31:0] pc=32'h00003000; 32 | reg [9:0] address; 33 | IM imOfIfu ( 34 | .addr(address), 35 | .instr(instr) 36 | ); 37 | always@(posedge clk)begin 38 | if(reset)begin 39 | pc<=32'h00003000; 40 | end 41 | else begin 42 | address<=pc[11:2]; 43 | pcPlus4<=pc+4; 44 | if( branch&zero | jump )begin 45 | pc <= pc+4+imm; 46 | end 47 | else begin 48 | pc <= pc+4; 49 | end 50 | end 51 | end 52 | endmodule 53 | -------------------------------------------------------------------------------- /P4/IM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:33:02 11/14/2020 7 | // Design Name: 8 | // Module Name: im 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module im( 22 | input [31:0] pc, 23 | output reg [31:0] instr 24 | ); 25 | reg [31:0] instruction [0:1023]; 26 | reg [9:0] addr; 27 | initial begin 28 | $readmemh("code.txt",instruction); 29 | end 30 | always@(*)begin 31 | addr=pc[11:2]; 32 | instr=instruction[addr]; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /P4/MUX.v: -------------------------------------------------------------------------------- 1 | module writeASel( 2 | input [4:0] rt, 3 | input [4:0] rd, 4 | input [1:0] regDst, 5 | output reg [4:0] WA 6 | ); 7 | always@(*)begin 8 | case(regDst) 9 | 0:begin 10 | WA=rt; 11 | end 12 | 1:begin 13 | WA=rd; 14 | end 15 | 2:begin 16 | WA=5'b11111; 17 | end 18 | default:begin 19 | WA=WA; 20 | end 21 | endcase 22 | end 23 | endmodule 24 | 25 | module aluDSel( 26 | input [31:0] rtData, 27 | input [31:0] imm32, 28 | input aluSrc, 29 | output [31:0] aluDataB 30 | ); 31 | assign aluDataB=(aluSrc)?imm32:rtData; 32 | endmodule 33 | 34 | module writeDSel( 35 | input [31:0] aluOut, 36 | input [31:0] dmRd, 37 | input [15:0] imm16, 38 | input [31:0] pcPlus4, 39 | input [1:0] memToReg, 40 | output reg [31:0] writeD 41 | ); 42 | always@(*)begin 43 | case(memToReg) 44 | 2'b00:begin 45 | writeD=aluOut; 46 | end 47 | 2'b01:begin 48 | writeD=dmRd; 49 | end 50 | 2'b10:begin 51 | writeD={imm16,{16{1'b0}}}; 52 | end 53 | 2'b11:begin 54 | writeD=pcPlus4; 55 | end 56 | default:begin 57 | writeD=0; 58 | end 59 | endcase 60 | end 61 | endmodule 62 | -------------------------------------------------------------------------------- /P4/P4.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P4/P4_doc_byfzc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P4/P4_doc_byfzc.pdf -------------------------------------------------------------------------------- /P4/PC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:32:27 11/14/2020 7 | // Design Name: 8 | // Module Name: PC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PC( 22 | input clk, 23 | input reset, 24 | input [31:0] next_pc, 25 | output reg [31:0] pc 26 | ); 27 | always@(posedge clk)begin 28 | if(reset)begin 29 | pc<=32'h00003000; 30 | end 31 | else begin 32 | pc<=next_pc; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /P4/grf.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:40:23 11/14/2020 7 | // Design Name: 8 | // Module Name: grf 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module GRF( 22 | input [4:0] RA1, 23 | input [4:0] RA2, 24 | output [31:0] RD1, 25 | output [31:0] RD2, 26 | input [4:0] WA, 27 | input [31:0] WD, 28 | input WE, 29 | input reset, 30 | input clk, 31 | input [31:0] pc 32 | ); 33 | reg [31:0] gpr [31:0]; 34 | assign RD1=gpr[RA1]; 35 | assign RD2=gpr[RA2]; 36 | integer i=0; 37 | always@(posedge clk)begin 38 | if(reset)begin 39 | for(i=0;i<32;i=i+1)begin 40 | gpr[i]<=32'b0; 41 | end 42 | end 43 | else begin 44 | if(WE)begin 45 | if(WA)gpr[WA]<=WD; 46 | else gpr[WA]<=0; 47 | end 48 | end 49 | end 50 | 51 | always@(posedge clk)begin 52 | if(WE & ~reset)begin 53 | $display("@%h: $%d <= %h", pc, WA, WD); 54 | end 55 | end 56 | endmodule 57 | -------------------------------------------------------------------------------- /P4/mips_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 11:43:54 11/15/2020 8 | // Design Name: mips 9 | // Module Name: E:/computer/verilog_ISE/CO/P4_byfzc/mips_tb.v 10 | // Project Name: P4_byfzc 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: mips 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module mips_tb; 26 | 27 | // Inputs 28 | reg clk; 29 | reg reset; 30 | 31 | // Instantiate the Unit Under Test (UUT) 32 | mips uut ( 33 | .clk(clk), 34 | .reset(reset) 35 | ); 36 | 37 | initial begin 38 | // Initialize Inputs 39 | clk = 0; 40 | reset = 1; 41 | // Wait 100 ns for global reset to finish 42 | #30 reset=0; 43 | 44 | // Add stimulus here 45 | 46 | end 47 | always #5 clk=~clk; 48 | endmodule 49 | 50 | -------------------------------------------------------------------------------- /P4/pcCalc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:54:46 11/14/2020 7 | // Design Name: 8 | // Module Name: pcCalc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module pcCalc( 22 | input [31:0] pc, 23 | input [31:0] imm, 24 | input [31:0] rsData, 25 | output reg [31:0] npc, 26 | output reg [31:0] pcPlus4, 27 | input branch, 28 | input jump, 29 | input zero, 30 | input pcSrc, 31 | input [25:0] imm26 32 | ); 33 | always@(*)begin 34 | pcPlus4=pc+4; 35 | case(pcSrc) 36 | 0:begin 37 | if( zero&branch)begin 38 | npc=pc+4+(imm<<2); 39 | end 40 | else if(jump)begin 41 | npc={pc[31:28],imm26,{2{1'b0}}}; 42 | end 43 | else begin 44 | npc=pc+4; 45 | end 46 | end 47 | 1:begin 48 | npc=rsData; 49 | end 50 | endcase 51 | end 52 | endmodule 53 | -------------------------------------------------------------------------------- /P4/spliter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:34:04 11/14/2020 7 | // Design Name: 8 | // Module Name: spliter 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module spliter( 22 | input [31:0] instr, 23 | output [4:0] rs, 24 | output [4:0] rt, 25 | output [4:0] rd, 26 | output [15:0] imm16, 27 | output [5:0] opcode, 28 | output [5:0] funcode, 29 | output [25:0] imm26 30 | ); 31 | assign rs=instr[25:21]; 32 | assign rt=instr[20:16]; 33 | assign rd=instr[15:11]; 34 | assign imm16=instr[15:0]; 35 | assign imm26=instr[25:0]; 36 | assign opcode=instr[31:26]; 37 | assign funcode=instr[5:0]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /P4/测试脚本文件.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P4/测试脚本文件.zip -------------------------------------------------------------------------------- /P5/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU( 3 | input [31:0] dataA, 4 | input [31:0] dataB, 5 | input [2:0] aluCtrl, 6 | output reg [31:0] result, 7 | output reg zero 8 | ); 9 | always@(*)begin 10 | case(aluCtrl) 11 | 3'b000:begin //& 12 | result = dataA&dataB; 13 | zero = result==0; 14 | end 15 | 3'b001:begin //| 16 | result = dataA|dataB; 17 | zero = result==0; 18 | end 19 | 3'b010:begin //+ 20 | result = dataA+dataB; 21 | zero = result==0; 22 | end 23 | 3'b011:begin //- 24 | result = dataA-dataB; 25 | zero = result==0; 26 | end 27 | default:begin 28 | result = result; 29 | zero = 0; 30 | end 31 | endcase 32 | end 33 | endmodule -------------------------------------------------------------------------------- /P5/CMP.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:52:46 11/23/2020 7 | // Design Name: 8 | // Module Name: CMP 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module CMP( 22 | input [31:0] d1, 23 | input [31:0] d2, 24 | output equal 25 | ); 26 | assign equal=(d1==d2); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /P5/D2E.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:02:12 11/23/2020 7 | // Design Name: 8 | // Module Name: D2E 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module D2E( 22 | input [31:0] instr_D, 23 | input [31:0] pc_D, 24 | input [31:0] pc_D4, 25 | input [31:0] pc_D8, 26 | output reg [31:0] pc_E, 27 | output reg [31:0] pc_E4, 28 | output reg [31:0] pc_E8, 29 | input [31:0] grf_RD1, 30 | input [31:0] grf_RD2, 31 | input [31:0] ext_D, 32 | output reg [31:0] ext_E, 33 | output reg [31:0] instr_E, 34 | output reg [31:0] rs_E, 35 | output reg [31:0] rt_E, 36 | input clk, 37 | input reset 38 | ); 39 | always@(posedge clk)begin 40 | if(reset)begin 41 | pc_E<=32'h00003000; 42 | pc_E4<=32'h00003000; 43 | pc_E8<=32'h00003000; 44 | ext_E<=0; 45 | instr_E<=0; 46 | rs_E<=0; 47 | rt_E<=0; 48 | end 49 | else begin 50 | pc_E<=pc_D; 51 | pc_E4<=pc_D4; 52 | pc_E8<=pc_D8; 53 | ext_E<=ext_D; 54 | instr_E<=instr_D; 55 | rs_E<=grf_RD1; 56 | rt_E<=grf_RD2; 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /P5/DM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DM( 3 | input [31:0] A, 4 | input [31:0] WD, 5 | output [31:0] RD, 6 | input RE, 7 | input WE, 8 | input clk, 9 | input reset, 10 | input [31:0] pc, 11 | input stall_D 12 | ); 13 | reg [31:0] dm [0:1023]; 14 | wire [11:2] addr; 15 | assign addr=A[11:2]; 16 | integer i=0; 17 | assign RD=RE?dm[addr]:0; 18 | 19 | always@(posedge clk)begin 20 | if(reset)begin 21 | for(i=0;i<=10'h3ff;i=i+1)begin 22 | dm[i]<=0; 23 | end 24 | end 25 | else begin 26 | if(WE)begin 27 | dm[addr]<=WD; 28 | end 29 | else begin 30 | dm[addr]<=dm[addr]; 31 | end 32 | end 33 | end 34 | 35 | always@(posedge clk)begin 36 | if(/*stall_D &*/WE & ~reset)begin 37 | $display("%d@%h: *%h <= %h",$time, pc, A, WD); 38 | //$display("@%h: *%h <= %h", pc, A, WD); 39 | end 40 | end 41 | endmodule -------------------------------------------------------------------------------- /P5/E2M.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:25:41 11/23/2020 7 | // Design Name: 8 | // Module Name: E2M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module E2M( 22 | input [31:0] instr_E, 23 | input [31:0] pc_E, 24 | input [31:0] pc_E4, 25 | input [31:0] pc_E8, 26 | input [31:0] rt_E, 27 | input [31:0] aluRet_E, 28 | input [31:0] ext_E, 29 | output reg [31:0] ext_M, 30 | output reg [31:0] pc_M, 31 | output reg [31:0] pc_M4, 32 | output reg [31:0] pc_M8, 33 | output reg [31:0] aluRet_M, 34 | output reg [31:0] instr_M, 35 | output reg [31:0] rt_M, 36 | 37 | input clk, 38 | input reset 39 | ); 40 | always@(posedge clk)begin 41 | if(reset)begin 42 | pc_M<=32'h00003000; 43 | pc_M4<=32'h00003000; 44 | pc_M8<=32'h00003000; 45 | aluRet_M<=0; 46 | instr_M<=0; 47 | rt_M<=0; 48 | ext_M<=0; 49 | end 50 | else begin 51 | pc_M<=pc_E; 52 | pc_M4<=pc_E4; 53 | pc_M8<=pc_E8; 54 | aluRet_M<=aluRet_E; 55 | instr_M<=instr_E; 56 | rt_M<=rt_E; 57 | ext_M<=ext_E; 58 | end 59 | end 60 | 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /P5/EXT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:54:09 11/23/2020 7 | // Design Name: 8 | // Module Name: EXT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module EXT( 22 | input [15:0] imm16, 23 | input [1:0] extOp, 24 | output reg [31:0] ext_D 25 | ); 26 | always@(*)begin 27 | case(extOp) 28 | 0:begin 29 | ext_D={{16{imm16[15]}},imm16}; 30 | end 31 | 1:begin 32 | ext_D={{16{1'b0}},imm16}; 33 | end 34 | 2:begin 35 | ext_D={imm16,{16{1'b0}}}; 36 | end 37 | default:begin 38 | ext_D=0; 39 | end 40 | endcase 41 | end 42 | endmodule 43 | -------------------------------------------------------------------------------- /P5/F2D.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:48:07 11/23/2020 7 | // Design Name: 8 | // Module Name: F2D 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module F2D( 22 | input clk, 23 | input reset, 24 | input en, 25 | input [31:0] instr_F, 26 | input [31:0] pc_F, 27 | input [31:0] npc, 28 | output reg [31:0] pc_D, 29 | output reg [31:0] pc_D4, 30 | output reg [31:0] pc_D8, 31 | output reg [31:0] instr_D 32 | ); 33 | always@(posedge clk)begin 34 | if(reset)begin 35 | pc_D<=32'h00003000; 36 | pc_D4<=32'h00003000; 37 | pc_D8<=32'h00003000; 38 | instr_D<=0; 39 | end 40 | else if(en) begin 41 | pc_D<=pc_F; 42 | pc_D4<=pc_F+4; 43 | pc_D8<=pc_F+8; 44 | instr_D<=instr_F; 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /P5/GRF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module GRF( 3 | input [4:0] RA1, 4 | input [4:0] RA2, 5 | output [31:0] RD1, 6 | output [31:0] RD2, 7 | input [4:0] WA, 8 | input [31:0] WD, 9 | input WE, 10 | input reset, 11 | input clk, 12 | input [31:0] pc_W, 13 | input stall_D 14 | ); 15 | reg [31:0] gpr [31:0]; 16 | assign RD1=(WA==RA1&&WA&&WE)?WD:gpr[RA1]; 17 | assign RD2=(WA==RA2&&WA&&WE)?WD:gpr[RA2]; 18 | integer i=0; 19 | 20 | always@(posedge clk)begin 21 | if(reset)begin 22 | for(i=0;i<32;i=i+1)begin 23 | gpr[i]<=32'b0; 24 | end 25 | end 26 | else begin 27 | if(WE)begin 28 | if(WA)gpr[WA]<=WD; 29 | else gpr[WA]<=0; 30 | end 31 | end 32 | end 33 | 34 | always@(posedge clk)begin 35 | if(/*stall_D &*/ WE & ~reset)begin 36 | $display("%d@%h: $%d <= %h", $time, pc_W, WA, WD); 37 | //$display("@%h: $%d <= %h", pc_W, WA, WD); 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /P5/IM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module IM( 3 | input [31:0] pc, 4 | output reg [31:0] instr 5 | ); 6 | reg [31:0] instruction [0:1023]; 7 | reg [9:0] addr; 8 | 9 | integer file_wr; 10 | initial begin 11 | $readmemh("code.txt",instruction); 12 | end 13 | 14 | always@(*)begin 15 | addr=pc[11:2]; 16 | instr=instruction[addr]; 17 | end 18 | endmodule -------------------------------------------------------------------------------- /P5/M2W.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:33:58 11/23/2020 7 | // Design Name: 8 | // Module Name: M2W 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module M2W( 22 | input [31:0] instr_M, 23 | input [31:0] pc_M, 24 | input [31:0] pc_M4, 25 | input [31:0] pc_M8, 26 | input [31:0] rt_M, 27 | input [31:0] aluRet_M, 28 | input [31:0] RD_M, 29 | input [31:0] ext_M, 30 | output reg [31:0] ext_W, 31 | output reg [31:0] pc_W, 32 | output reg [31:0] pc_W4, 33 | output reg [31:0] pc_W8, 34 | output reg [31:0] aluRet_W, 35 | output reg [31:0] instr_W, 36 | output reg [31:0] rt_W, 37 | output reg [31:0] RD_W, 38 | input clk, 39 | input reset 40 | ); 41 | 42 | always@(posedge clk)begin 43 | if(reset)begin 44 | pc_W<=32'h00003000; 45 | pc_W4<=32'h00003000; 46 | pc_W8<=32'h00003000; 47 | aluRet_W<=0; 48 | instr_W<=0; 49 | rt_W<=0; 50 | RD_W<=0; 51 | ext_W<=0; 52 | end 53 | else begin 54 | pc_W<=pc_M; 55 | pc_W4<=pc_M4; 56 | pc_W8<=pc_M8; 57 | aluRet_W<=aluRet_M; 58 | instr_W<=instr_M; 59 | rt_W<=rt_M; 60 | RD_W<=RD_M; 61 | ext_W<=ext_M; 62 | end 63 | end 64 | 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /P5/MIPS_CPU_P5_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 00:12:36 11/26/2020 8 | // Design Name: mips 9 | // Module Name: E:/computer/verilog_ISE/CO/P5/MIPS_CPU_P5_tb.v 10 | // Project Name: P5 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: mips 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module MIPS_CPU_P5_tb; 26 | 27 | // Inputs 28 | reg reset; 29 | reg clk; 30 | 31 | // Instantiate the Unit Under Test (UUT) 32 | mips uut ( 33 | .reset(reset), 34 | .clk(clk) 35 | ); 36 | 37 | initial begin 38 | // Initialize Inputs 39 | reset = 1; 40 | clk = 0; 41 | #10 42 | reset=0; 43 | 44 | // Add stimulus here 45 | 46 | end 47 | 48 | always #5 clk=~clk; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /P5/MUX.v: -------------------------------------------------------------------------------- 1 | module writeASel( 2 | input [4:0] rt, 3 | input [4:0] rd, 4 | input [1:0] regDst, 5 | output reg [4:0] WA 6 | ); 7 | always@(*)begin 8 | case(regDst) 9 | 0:begin 10 | WA=rt; 11 | end 12 | 1:begin 13 | WA=rd; 14 | end 15 | 2:begin 16 | WA=5'b11111; 17 | end 18 | default:begin 19 | WA=WA; 20 | end 21 | endcase 22 | end 23 | endmodule 24 | 25 | module aluDSel( 26 | input [31:0] rtData, 27 | input [31:0] imm32, 28 | input aluSrc, 29 | output [31:0] aluDataB 30 | ); 31 | assign aluDataB=(aluSrc)?imm32:rtData; 32 | endmodule 33 | 34 | module writeDSel( 35 | input [31:0] aluOut, 36 | input [31:0] dmRd, 37 | input [31:0] lui_ext, 38 | input [31:0] pcPlus8, 39 | input [1:0] memToReg, 40 | output reg [31:0] writeD 41 | ); 42 | always@(*)begin 43 | case(memToReg) 44 | 2'b00:begin 45 | writeD=aluOut; 46 | end 47 | 2'b01:begin 48 | writeD=dmRd; 49 | end 50 | 2'b10:begin 51 | writeD=lui_ext; 52 | end 53 | 2'b11:begin 54 | writeD=pcPlus8; 55 | end 56 | default:begin 57 | writeD=0; 58 | end 59 | endcase 60 | end 61 | endmodule 62 | 63 | 64 | module aluRetSel( 65 | input lui, 66 | input [31:0] ext_E, 67 | input [31:0] aluRet_E, 68 | output reg [31:0] aluRet_M 69 | ); 70 | always@(*) begin 71 | case(lui) 72 | 0:aluRet_M=aluRet_E; 73 | 1:aluRet_M=ext_E; 74 | default:aluRet_M=aluRet_E; 75 | endcase 76 | end 77 | endmodule 78 | -------------------------------------------------------------------------------- /P5/P5.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P5/P5_doc_fzc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P5/P5_doc_fzc.pdf -------------------------------------------------------------------------------- /P5/PC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:35:46 11/23/2020 7 | // Design Name: 8 | // Module Name: PC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PC( 22 | input clk, 23 | input reset, 24 | input [31:0] next_pc, 25 | output reg [31:0] pc, 26 | input en 27 | ); 28 | always@(posedge clk)begin 29 | if(reset)begin 30 | pc<=32'h00003000; 31 | end 32 | else if(en)begin 33 | pc<=next_pc; 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /P5/autotest_P5.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P5/autotest_P5.zip -------------------------------------------------------------------------------- /P5/constants.v: -------------------------------------------------------------------------------- 1 | //R 2 | 3 | //opcode 4 | `define R 6'b000000 5 | //funcode 6 | `define addu 6'b100001 7 | `define subu 6'b100011 8 | `define jr 6'b001000 9 | 10 | //I 11 | //opcode 12 | `define lw 6'b100011 13 | `define sw 6'b101011 14 | `define beq 6'b000100 15 | `define lui 6'b001111 16 | `define ori 6'b001101 17 | 18 | //J 19 | //opcode 20 | `define jal 6'b000011 21 | `define j 6'b000010 22 | 23 | 24 | 25 | //wire select of instr 26 | `define fun 5:0 27 | `define op 31:26 28 | `define rs 25:21 29 | `define rt 20:16 30 | `define rd 15:11 31 | `define imm26 25:0 32 | `define imm16 15:0 33 | -------------------------------------------------------------------------------- /P5/controller.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "constants.v" 3 | module controller( 4 | input [5:0] op, 5 | input [5:0] func, 6 | output [1:0] regDst, 7 | output aluSrc, 8 | output regWrite, 9 | output memRead, 10 | output memWrite, 11 | output [1:0] memToReg, 12 | output [1:0] extOp, 13 | output branch, 14 | output jump, 15 | output [2:0] aluCtrl, 16 | output pcSrc 17 | ); 18 | reg addu=0,subu=0,jr=0; 19 | reg beq=0,lui=0,ori=0,lw=0,sw=0; 20 | reg jal=0,j=0; 21 | reg nop=0; 22 | always@(*)begin 23 | addu=0;subu=0;jr=0; 24 | beq=0;lui=0;ori=0;lw=0;sw=0; 25 | jal=0;j=0; 26 | nop=0; 27 | case(op) 28 | `R:begin 29 | case(func) 30 | `addu:addu=1; 31 | `subu:subu=1; 32 | `jr:jr=1; 33 | default:nop=1; 34 | endcase 35 | end 36 | `beq:beq=1; 37 | `lui:lui=1; 38 | `ori:ori=1; 39 | `lw:lw=1; 40 | `sw:sw=1; 41 | `j:j=1; 42 | `jal:jal=1; 43 | default:nop=1; 44 | endcase 45 | end 46 | assign regDst = (addu|subu|jr)?2'b01: 47 | (jal)?2'b10:2'b00; 48 | assign aluSrc = lw|sw|ori; 49 | assign regWrite = addu|subu|lw|lui|ori|jal; 50 | assign memRead = lw; 51 | assign memWrite = sw; 52 | assign memToReg = (jal)?2'b11: 53 | (lw)?2'b01: 54 | (lui)?2'b10: 55 | 2'b00; 56 | assign extOp = (ori)?2'b01: 57 | (lui)?2'b10: 58 | 2'b00; 59 | assign branch = beq; 60 | assign aluCtrl = (ori)?3'b001: 61 | (addu|lw|sw)?3'b010: 62 | (subu|beq)?3'b011: 63 | 3'b000; 64 | assign jump = (jal|j); 65 | assign pcSrc = (jr|jal|j); 66 | endmodule 67 | -------------------------------------------------------------------------------- /P5/for_MUX.v: -------------------------------------------------------------------------------- 1 | module forRsD( 2 | input [2:0] selRsD, 3 | input [31:0] grf_RD1, 4 | input [31:0] pc_E8, 5 | input [31:0] aluRet_M, 6 | input [31:0] pc_M8, 7 | input [31:0] writeData_W, 8 | input [31:0] pc_W8, 9 | output reg [31:0] for_rs_D 10 | ); 11 | always@(*)begin 12 | case(selRsD) 13 | 0:for_rs_D=grf_RD1; 14 | 1:for_rs_D=pc_E8; 15 | 2:for_rs_D=pc_M8; 16 | 3:for_rs_D=aluRet_M; 17 | 4:for_rs_D=pc_W8; 18 | 5:for_rs_D=writeData_W; 19 | default:for_rs_D=0; 20 | endcase 21 | end 22 | endmodule 23 | 24 | module forRtD( 25 | input [2:0] selRtD, 26 | input [31:0] grf_RD2, 27 | input [31:0] pc_E8, 28 | input [31:0] aluRet_M, 29 | input [31:0] pc_M8, 30 | input [31:0] writeData_W, 31 | input [31:0] pc_W8, 32 | output reg [31:0] for_rt_D 33 | ); 34 | always@(*)begin 35 | case(selRtD) 36 | 0:for_rt_D=grf_RD2; 37 | 1:for_rt_D=pc_E8; 38 | 2:for_rt_D=pc_M8; 39 | 3:for_rt_D=aluRet_M; 40 | 4:for_rt_D=pc_W8; 41 | 5:for_rt_D=writeData_W; 42 | default:for_rt_D=0; 43 | endcase 44 | end 45 | endmodule 46 | 47 | module forRsE( 48 | input [2:0] selRsE, 49 | input [31:0] aluRet_M, 50 | input [31:0] pc_M8, 51 | input [31:0] writeData_W, 52 | input [31:0] pc_W8, 53 | input [31:0] rsD_E, 54 | output reg [31:0] for_rs_E 55 | ); 56 | always@(*)begin 57 | case(selRsE) 58 | 0:for_rs_E=rsD_E; 59 | 1:for_rs_E=pc_M8; 60 | 2:for_rs_E=aluRet_M; 61 | 3:for_rs_E=pc_W8; 62 | 4:for_rs_E=writeData_W; 63 | default:for_rs_E=0; 64 | endcase 65 | end 66 | endmodule 67 | 68 | module forRtE( 69 | input [2:0] selRtE, 70 | input [31:0] aluRet_M, 71 | input [31:0] pc_M8, 72 | input [31:0] writeData_W, 73 | input [31:0] pc_W8, 74 | input [31:0] rtD_E, 75 | output reg [31:0] for_rt_E 76 | ); 77 | always@(*)begin 78 | case(selRtE) 79 | 0:for_rt_E=rtD_E; 80 | 1:for_rt_E=pc_M8; 81 | 2:for_rt_E=aluRet_M; 82 | 3:for_rt_E=pc_W8; 83 | 4:for_rt_E=writeData_W; 84 | default:for_rt_E=0; 85 | endcase 86 | end 87 | endmodule 88 | 89 | module forRtM( 90 | input [2:0] selRtM, 91 | input [31:0] writeData_W, 92 | input [31:0] pc_W8, 93 | input [31:0] rt_M, 94 | output reg [31:0] for_rt_M 95 | ); 96 | always@(*)begin 97 | case(selRtM) 98 | 0:for_rt_M=rt_M; 99 | 1:for_rt_M=pc_W8; 100 | 2:for_rt_M=writeData_W; 101 | default:for_rt_M=0; 102 | endcase 103 | end 104 | endmodule 105 | -------------------------------------------------------------------------------- /P5/instr_class.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 18:48:41 11/25/2020 7 | // Design Name: 8 | // Module Name: instr_class 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `include "constants.v" 22 | module instr_class( 23 | input [31:0] instr, 24 | output jal, 25 | output cal_i, 26 | output cal_r, 27 | output load, 28 | output beq, 29 | output jr, 30 | output store 31 | ); 32 | assign cal_i = (instr[`op]==`ori||instr[`op]==`lui); 33 | assign cal_r = (instr[`op]==`R&&instr[`fun]!=`jr); 34 | assign jal = (instr[`op]==`jal); 35 | assign load = (instr[`op]==`lw); 36 | assign jr = (instr[`op]==`R&&instr[`fun]==`jr); 37 | assign beq = instr[`op]==`beq; 38 | assign store = instr[`op]==`sw; 39 | endmodule 40 | -------------------------------------------------------------------------------- /P5/pcCalc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module pcCalc( 3 | input [31:0] pc, 4 | input [31:0] pc_D4, 5 | input [31:0] imm, 6 | input [31:0] rsData, 7 | output reg [31:0] npc, 8 | input branch, 9 | input jump, 10 | input zero, 11 | input pcSrc, 12 | input [25:0] imm26 13 | ); 14 | always@(*)begin 15 | case(pcSrc) 16 | 0:begin 17 | if( zero&branch )begin 18 | npc=pc_D4+(imm<<2); 19 | end 20 | else begin 21 | npc=pc+4; 22 | end 23 | end 24 | 1:begin 25 | if(jump)begin 26 | npc={pc_D4[31:28],imm26,{2{1'b0}}}; 27 | end 28 | else begin 29 | npc=rsData; 30 | end 31 | end 32 | default:npc=32'h00003000; 33 | endcase 34 | end 35 | endmodule -------------------------------------------------------------------------------- /P5/冒险单元.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P5/冒险单元.xlsx -------------------------------------------------------------------------------- /P6/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU( 3 | input [31:0] dataA, 4 | input [31:0] dataB, 5 | input [3:0] aluCtrl, 6 | output reg [31:0] result, 7 | output reg zero, 8 | input [4:0] shamt 9 | ); 10 | always@(*)begin 11 | case(aluCtrl) 12 | 4'b0000:begin //& 13 | result = dataA&dataB; 14 | zero = result==0; 15 | end 16 | 4'b0001:begin //| 17 | result = dataA|dataB; 18 | zero = result==0; 19 | end 20 | 4'b0010:begin //+ 21 | result = dataA+dataB; 22 | zero = result==0; 23 | end 24 | 4'b0011:begin //- 25 | result = dataA-dataB; 26 | zero = result==0; 27 | end 28 | 4'b0100:begin //nor 29 | result = ~(dataA | dataB); 30 | end 31 | 4'b0101:begin //xor 32 | result = dataA^dataB; 33 | end 34 | 4'b0110:begin //logical left shift 35 | result = dataB<>shamt; 39 | end 40 | 4'b1000:begin //suanshu right logical 41 | result = ($signed(dataB))>>>shamt; 42 | end 43 | 4'b1001:begin //signed A1 slt slti 44 | result = $signed(dataA)<$signed(dataB)?32'b1:32'b0; 45 | end 46 | 4'b1010:begin //unsigned A1 sltu sltiu 47 | result = dataA=0); 36 | assign gtz=(($signed(d1))>0); 37 | assign equal=(eq&&branch==4'b0001)||(~eq&&branch==4'b0010)||(gtz&&branch==4'b0011) 38 | ||(lez&&branch==4'b0100)||(gez&&branch==4'b0101)||(ltz&&branch==4'b0110); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /P6/D2E.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:02:12 11/23/2020 7 | // Design Name: 8 | // Module Name: D2E 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module D2E( 22 | input [31:0] instr_D, 23 | input [31:0] pc_D, 24 | input [31:0] pc_D4, 25 | input [31:0] pc_D8, 26 | output reg [31:0] pc_E, 27 | output reg [31:0] pc_E4, 28 | output reg [31:0] pc_E8, 29 | input [31:0] grf_RD1, 30 | input [31:0] grf_RD2, 31 | input [31:0] ext_D, 32 | output reg [31:0] ext_E, 33 | output reg [31:0] instr_E, 34 | output reg [31:0] rs_E, 35 | output reg [31:0] rt_E, 36 | input clk, 37 | input reset 38 | ); 39 | always@(posedge clk)begin 40 | if(reset)begin 41 | pc_E<=32'h00003000; 42 | pc_E4<=32'h00003000; 43 | pc_E8<=32'h00003000; 44 | ext_E<=0; 45 | instr_E<=0; 46 | rs_E<=0; 47 | rt_E<=0; 48 | end 49 | else begin 50 | pc_E<=pc_D; 51 | pc_E4<=pc_D4; 52 | pc_E8<=pc_D8; 53 | ext_E<=ext_D; 54 | instr_E<=instr_D; 55 | rs_E<=grf_RD1; 56 | rt_E<=grf_RD2; 57 | end 58 | end 59 | 60 | endmodule 61 | -------------------------------------------------------------------------------- /P6/DM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DM( 3 | input [31:0] A, 4 | input [31:0] WD, 5 | output [31:0] RD, 6 | input RE, 7 | input WE, 8 | input clk, 9 | input reset, 10 | input [31:0] pc, 11 | input stall_D, 12 | input [3:0] BE 13 | ); 14 | reg [31:0] dm [0:4095]; 15 | //wire [11:0] addr; 16 | //assign addr=A[13:2]; 17 | integer i=0; 18 | assign RD=dm[A[13:2]]; 19 | 20 | always@(posedge clk)begin 21 | if(reset)begin 22 | for(i=0;i<=12'hfff;i=i+1)begin 23 | dm[i]<=0; 24 | end 25 | end 26 | else begin 27 | if(WE)begin 28 | case(BE) 29 | 4'b1111:begin 30 | dm[A[13:2]]<=WD; 31 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,WD); 32 | //$display("@%h: *%h <= %h",pc,A/4*4,WD); 33 | end 34 | 4'b0011:begin 35 | dm[A[13:2]][15:0]<=WD[15:0]; 36 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:16],WD[15:0]}); 37 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:16],WD[15:0]}); 38 | end 39 | 4'b1100:begin 40 | dm[A[13:2]][31:16]<=WD[15:0]; 41 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{WD[15:0],dm[A[13:2]][15:0]}); 42 | //$display("@%h: *%h <= %h",pc,A/4*4,{WD[15:0],dm[A[13:2]][15:0]}); 43 | end 44 | 4'b0001:begin 45 | dm[A[13:2]][7:0]<=WD[7:0]; 46 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:8],WD[7:0]}); 47 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:8],WD[7:0]}); 48 | end 49 | 4'b0010:begin 50 | dm[A[13:2]][15:8]<=WD[7:0]; 51 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:16],WD[7:0],dm[A[13:2]][7:0]}); 52 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:16],WD[7:0],dm[A[13:2]][7:0]}); 53 | end 54 | 4'b0100:begin 55 | dm[A[13:2]][23:16]<=WD[7:0]; 56 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:24],WD[7:0],dm[A[13:2]][15:0]}); 57 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:24],WD[7:0],dm[A[13:2]][15:0]}); 58 | end 59 | 4'b1000:begin 60 | dm[A[13:2]][31:24]<=WD[7:0]; 61 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{WD[7:0],dm[A[13:2]][23:0]}); 62 | //$display("@%h: *%h <= %h",pc,A/4*4,{WD[7:0],dm[A[13:2]][23:0]}); 63 | end 64 | endcase 65 | end 66 | end 67 | end 68 | 69 | endmodule -------------------------------------------------------------------------------- /P6/E2M.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:25:41 11/23/2020 7 | // Design Name: 8 | // Module Name: E2M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module E2M( 22 | input [31:0] instr_E, 23 | input [31:0] pc_E, 24 | input [31:0] pc_E4, 25 | input [31:0] pc_E8, 26 | input [31:0] rt_E, 27 | input [31:0] aluRet_E, 28 | input [31:0] ext_E, 29 | input [31:0] mdOut_E, 30 | output reg [31:0] ext_M, 31 | output reg [31:0] pc_M, 32 | output reg [31:0] pc_M4, 33 | output reg [31:0] pc_M8, 34 | output reg [31:0] aluRet_M, 35 | output reg [31:0] instr_M, 36 | output reg [31:0] rt_M, 37 | output reg [31:0] mdOut_M, 38 | input clk, 39 | input reset 40 | ); 41 | always@(posedge clk)begin 42 | if(reset)begin 43 | pc_M<=32'h00003000; 44 | pc_M4<=32'h00003000; 45 | pc_M8<=32'h00003000; 46 | aluRet_M<=0; 47 | instr_M<=0; 48 | rt_M<=0; 49 | ext_M<=0; 50 | mdOut_M<=0; 51 | end 52 | else begin 53 | pc_M<=pc_E; 54 | pc_M4<=pc_E4; 55 | pc_M8<=pc_E8; 56 | aluRet_M<=aluRet_E; 57 | instr_M<=instr_E; 58 | rt_M<=rt_E; 59 | ext_M<=ext_E; 60 | mdOut_M<=mdOut_E; 61 | end 62 | end 63 | 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /P6/EXT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:54:09 11/23/2020 7 | // Design Name: 8 | // Module Name: EXT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module EXT( 22 | input [15:0] imm16, 23 | input extOp, 24 | output reg [31:0] ext_D 25 | ); 26 | always@(*)begin 27 | case(extOp) 28 | 0:begin 29 | ext_D={{16{imm16[15]}},imm16}; 30 | end 31 | 1:begin 32 | ext_D={{16{1'b0}},imm16}; 33 | end 34 | default:begin 35 | ext_D=0; 36 | end 37 | endcase 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /P6/F2D.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:48:07 11/23/2020 7 | // Design Name: 8 | // Module Name: F2D 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module F2D( 22 | input clk, 23 | input reset, 24 | input en, 25 | input [31:0] instr_F, 26 | input [31:0] pc_F, 27 | input [31:0] npc, 28 | output reg [31:0] pc_D, 29 | output reg [31:0] pc_D4, 30 | output reg [31:0] pc_D8, 31 | output reg [31:0] instr_D 32 | ); 33 | always@(posedge clk)begin 34 | if(reset)begin 35 | pc_D<=32'h00003000; 36 | pc_D4<=32'h00003000; 37 | pc_D8<=32'h00003000; 38 | instr_D<=0; 39 | end 40 | else if(en) begin 41 | pc_D<=pc_F; 42 | pc_D4<=pc_F+4; 43 | pc_D8<=pc_F+8; 44 | instr_D<=instr_F; 45 | end 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /P6/GRF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module GRF( 3 | input [4:0] RA1, 4 | input [4:0] RA2, 5 | output [31:0] RD1, 6 | output [31:0] RD2, 7 | input [4:0] WA, 8 | input [31:0] WD, 9 | input WE, 10 | input reset, 11 | input clk, 12 | input [31:0] pc_W, 13 | input stall_D 14 | ); 15 | reg [31:0] gpr [31:0]; 16 | assign RD1=(WA==RA1&&WA&&WE)?WD:gpr[RA1]; 17 | assign RD2=(WA==RA2&&WA&&WE)?WD:gpr[RA2]; 18 | integer i=0; 19 | 20 | always@(posedge clk)begin 21 | if(reset)begin 22 | for(i=0;i<32;i=i+1)begin 23 | gpr[i]<=32'b0; 24 | end 25 | end 26 | else begin 27 | if(WE)begin 28 | if(WA)gpr[WA]<=WD; 29 | else gpr[WA]<=0; 30 | end 31 | end 32 | end 33 | 34 | always@(posedge clk)begin 35 | if(/*stall_D &*/ WE & ~reset)begin 36 | $display("%d@%h: $%d <= %h", $time, pc_W, WA, WD); 37 | //$display("@%h: $%d <= %h", pc_W, WA, WD); 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /P6/IM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module IM( 3 | input [31:0] pc, 4 | output reg [31:0] instr 5 | ); 6 | reg [31:0] instruction [0:4095]; 7 | reg [11:0] addr; 8 | 9 | integer file_wr; 10 | initial begin 11 | $readmemh("code.txt",instruction); 12 | end 13 | 14 | always@(*)begin 15 | addr=pc[13:2]-12'hc00; 16 | instr=instruction[addr]; 17 | end 18 | endmodule -------------------------------------------------------------------------------- /P6/M2W.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:33:58 11/23/2020 7 | // Design Name: 8 | // Module Name: M2W 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module M2W( 22 | input [31:0] instr_M, 23 | input [31:0] pc_M, 24 | input [31:0] pc_M4, 25 | input [31:0] pc_M8, 26 | input [31:0] rt_M, 27 | input [31:0] aluRet_M, 28 | input [31:0] RD_M, 29 | input [31:0] ext_M, 30 | input [31:0] mdOut_M, 31 | output reg [31:0] ext_W, 32 | output reg [31:0] pc_W, 33 | output reg [31:0] pc_W4, 34 | output reg [31:0] pc_W8, 35 | output reg [31:0] aluRet_W, 36 | output reg [31:0] instr_W, 37 | output reg [31:0] rt_W, 38 | output reg [31:0] RD_W, 39 | output reg [31:0] mdOut_W, 40 | input clk, 41 | input reset 42 | ); 43 | 44 | always@(posedge clk)begin 45 | if(reset)begin 46 | pc_W<=32'h00003000; 47 | pc_W4<=32'h00003000; 48 | pc_W8<=32'h00003000; 49 | aluRet_W<=0; 50 | instr_W<=0; 51 | rt_W<=0; 52 | RD_W<=0; 53 | ext_W<=0; 54 | mdOut_W<=0; 55 | end 56 | else begin 57 | pc_W<=pc_M; 58 | pc_W4<=pc_M4; 59 | pc_W8<=pc_M8; 60 | aluRet_W<=aluRet_M; 61 | instr_W<=instr_M; 62 | rt_W<=rt_M; 63 | RD_W<=RD_M; 64 | ext_W<=ext_M; 65 | mdOut_W<=mdOut_M; 66 | end 67 | end 68 | 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /P6/MIPS_CPU_P5_t6.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 00:12:36 11/26/2020 8 | // Design Name: mips 9 | // Module Name: E:/computer/verilog_ISE/CO/P5/MIPS_CPU_P5_tb.v 10 | // Project Name: P5 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: mips 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module MIPS_CPU_P5_tb; 26 | 27 | // Inputs 28 | reg reset; 29 | reg clk; 30 | 31 | // Instantiate the Unit Under Test (UUT) 32 | mips uut ( 33 | .reset(reset), 34 | .clk(clk) 35 | ); 36 | 37 | initial begin 38 | // Initialize Inputs 39 | reset = 1; 40 | clk = 0; 41 | #10 42 | reset=0; 43 | 44 | // Add stimulus here 45 | 46 | end 47 | 48 | always #5 clk=~clk; 49 | endmodule 50 | 51 | -------------------------------------------------------------------------------- /P6/MULT_DIV.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:36:05 12/01/2020 7 | // Design Name: 8 | // Module Name: MULT_DIV 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module MULT_DIV( 22 | input reset, 23 | input clk, 24 | input start, 25 | output reg busy, 26 | input [31:0] A, 27 | input [31:0] B, 28 | output reg [31:0] HI, 29 | output reg [31:0] LO, 30 | input sign, 31 | input op, 32 | input WE, 33 | input write_sel 34 | ); 35 | integer cnt=0; 36 | reg [63:0] ret=0; 37 | reg dmop=0; 38 | always@(posedge clk)begin 39 | if(reset)begin 40 | HI<=0; 41 | LO<=0; 42 | cnt<=0; 43 | ret<=0; 44 | busy<=0; 45 | dmop<=0; 46 | end 47 | else begin 48 | if(start&&cnt==0)begin 49 | case(op) 50 | 0:begin 51 | if(sign==0)begin 52 | ret<=A*B; 53 | dmop<=0; 54 | end 55 | else begin 56 | ret<=($signed(A))*($signed(B)); 57 | dmop<=0; 58 | end 59 | end 60 | 1:begin 61 | if(sign==0)begin 62 | ret<={A%B,A/B}; 63 | dmop<=1; 64 | end 65 | else begin 66 | ret<={($signed(A))%($signed(B)),($signed(A))/($signed(B))}; 67 | dmop<=1; 68 | end 69 | end 70 | default:begin 71 | cnt<=0; 72 | ret<=0; 73 | busy<=0; 74 | dmop<=0; 75 | end 76 | endcase 77 | cnt<=1; 78 | busy<=1; 79 | end 80 | else if(cnt==1)begin 81 | HI<=ret[63:32]; 82 | LO<=ret[31:0]; 83 | busy<=1; 84 | cnt<=cnt+1; 85 | end 86 | else if(cnt>1)begin 87 | cnt<=cnt+1; 88 | case(dmop) 89 | 0:begin 90 | if(cnt<=4)begin 91 | busy<=1; 92 | end 93 | else begin 94 | busy<=0; 95 | cnt<=0; 96 | end 97 | end 98 | 1:begin 99 | if(cnt<=9)begin 100 | busy<=1; 101 | end 102 | else begin 103 | busy<=0; 104 | cnt<=0; 105 | end 106 | end 107 | default:begin 108 | cnt<=0; 109 | busy<=0; 110 | end 111 | endcase 112 | end 113 | 114 | if(WE&&~busy)begin 115 | case(write_sel) 116 | 0:HI<=A; 117 | 1:LO<=A; 118 | default:LO<=0; 119 | endcase 120 | end 121 | end 122 | end 123 | 124 | endmodule 125 | -------------------------------------------------------------------------------- /P6/MUX.v: -------------------------------------------------------------------------------- 1 | module writeASel( 2 | input [4:0] rt, 3 | input [4:0] rd, 4 | input [1:0] regDst, 5 | output reg [4:0] WA 6 | ); 7 | always@(*)begin 8 | case(regDst) 9 | 0:begin 10 | WA=rt; 11 | end 12 | 1:begin 13 | WA=rd; 14 | end 15 | 2:begin 16 | WA=5'b11111; 17 | end 18 | default:begin 19 | WA=WA; 20 | end 21 | endcase 22 | end 23 | endmodule 24 | 25 | module aluDSel( 26 | input [31:0] rtData, 27 | input [31:0] imm32, 28 | input aluSrc, 29 | output [31:0] aluDataB 30 | ); 31 | assign aluDataB=(aluSrc)?imm32:rtData; 32 | endmodule 33 | 34 | module writeDSel( 35 | input [31:0] aluOut, 36 | input [31:0] dmRd, 37 | input [31:0] pcPlus8, 38 | input [2:0] memToReg, 39 | input [31:0] mdOut_W, 40 | output reg [31:0] writeD 41 | ); 42 | always@(*)begin 43 | case(memToReg) 44 | 3'b000:begin 45 | writeD=aluOut; 46 | end 47 | 3'b001:begin 48 | writeD=dmRd; 49 | end 50 | 3'b010:begin 51 | writeD=pcPlus8; 52 | end 53 | 3'b011:begin 54 | writeD=mdOut_W; 55 | end 56 | default:begin 57 | writeD=0; 58 | end 59 | endcase 60 | end 61 | endmodule 62 | 63 | module hiloSel( 64 | input [31:0] HI, 65 | input [31:0] LO, 66 | input sel, 67 | output [31:0] mdOut_E 68 | ); 69 | assign mdOut_E=sel==1?LO:HI; 70 | endmodule 71 | 72 | module shrsSel( 73 | input [4:0] shamt, 74 | input [4:0] rs_4_0, 75 | input sel, 76 | output [4:0] shamt_out 77 | ); 78 | assign shamt_out=sel==1?shamt:rs_4_0; 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /P6/P6.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P6/P6_doc_fzc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P6/P6_doc_fzc.pdf -------------------------------------------------------------------------------- /P6/P6指令分类.md: -------------------------------------------------------------------------------- 1 | | 类型 | 指令名字 | 2 | | :----------------------------------------------: | :-----------------------------------------------: | 3 | | 访存指令 | LB、LBU、LH、LHU、LW、SB、SH、SW | 4 | | cal_r | ADD、ADDU、SUB、 SUBU、 AND、OR、XOR、NOR | 5 | | cal_r(需要扩展) | SLLV、SRLV、SRAV、SLL、 SRL、SRA、SLT | 6 | | cal_i(需扩展) | LUI、SLTI、SLTIU、SLTU | 7 | | cal_i | ADDI、ADDIU、ANDI、ORI、XORI | 8 | | beq类 | BEQ、BNE、BLEZ、BGTZ、BLTZ、BGEZ | 9 | | 跳转类 | J、JAL、JALR、JR | 10 | | 乘除寄存（load to gpr[rd] or write from gpr[rs]) | MFHI、MFLO、MTHI、MTLO MULT、 MULTU、 DIV、 DIVU | 11 | 12 | 13 | 14 | | 口名字\输出信号 | addu | subu | jr | lw | sw | beq | lui | ori | jal | j | 15 | | :-------------: | :----: | :----: | :----: | :----: | :----: | :----: | :----: | :----: | :----: | :----: | 16 | | op | 000000 | 000000 | 000000 | 100011 | 101011 | 000100 | 001111 | 001101 | 000011 | 000010 | 17 | | func | 100001 | 100011 | 001000 | xxxxxx | xxxxxx | xxxxxx | xxxxxx | xxxxxx | xxxxxx | xxxxxx | 18 | | regDst[1:0] | 01 | 01 | 01 | 00 | xx | 00 | 00 | 00 | 10 | xx | 19 | | aluSrc | 0 | 0 | 0 | 1 | 1 | 0 | x | 1 | x | x | 20 | | regWrite | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 21 | | memRead | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 22 | | memWrite | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 23 | | memToReg[1:0] | 00 | 00 | 10 | 01 | xx | xx | 00 | 00 | 11 | xx | 24 | | extOp[1:0] | 00 | 00 | 00 | 00 | 00 | 00 | 10 | 01 | 00 | 0 | 25 | | branch | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 26 | | aluCtrl[2:0] | 010 | 011 | xxx | 010 | 010 | 011 | xxx | 001 | xxx | xxx | 27 | | jump | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 28 | | pcSrc | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 29 | 30 | -------------------------------------------------------------------------------- /P6/PC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:35:46 11/23/2020 7 | // Design Name: 8 | // Module Name: PC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PC( 22 | input clk, 23 | input reset, 24 | input [31:0] next_pc, 25 | output reg [31:0] pc, 26 | input en 27 | ); 28 | always@(posedge clk)begin 29 | if(reset)begin 30 | pc<=32'h00003000; 31 | end 32 | else if(en)begin 33 | pc<=next_pc; 34 | end 35 | end 36 | endmodule 37 | -------------------------------------------------------------------------------- /P6/constants.v: -------------------------------------------------------------------------------- 1 | //R 2 | //opcode 3 | `define R 6'b000000 4 | //funcode 5 | //cal_r 6 | `define add 6'b100000 7 | `define addu 6'b100001 8 | `define sub 6'b100010 9 | `define subu 6'b100011 10 | `define AND 6'b100100 11 | `define OR 6'b100101 12 | `define NOR 6'b100111 13 | `define XOR 6'b100110 14 | 15 | `define sll 6'b000000 16 | `define sllv 6'b000100 17 | `define slt 6'b101010 18 | `define sltu 6'b101011 19 | `define sra 6'b000011 20 | `define srav 6'b000111 21 | `define srl 6'b000010 22 | `define srlv 6'b000110 23 | //jump to rs 24 | `define jr 6'b001000 25 | `define jalr 6'b001001 26 | //hi and lo 27 | `define mfhi 6'b010000 28 | `define mflo 6'b010010 29 | `define mthi 6'b010001 30 | `define mtlo 6'b010011 31 | `define mult 6'b011000 32 | `define multu 6'b011001 33 | `define div 6'b011010 34 | `define divu 6'b011011 35 | 36 | //I 37 | //opcode 38 | //store and load 39 | `define lw 6'b100011 40 | `define lb 6'b100000 41 | `define lbu 6'b100100 42 | `define lh 6'b100001 43 | `define lhu 6'b100101 44 | `define sw 6'b101011 45 | `define sb 6'b101000 46 | `define sh 6'b101001 47 | //br 48 | `define beq 6'b000100 49 | `define bne 6'b000101 50 | `define bgtz 6'b000111 51 | `define blez 6'b000110 52 | `define bgeltz 6'b000001 53 | //bgeltz:20:16 to decide the instr 54 | `define bgez 5'b00001 55 | `define bltz 5'b00000 56 | 57 | //cal_i 58 | `define lui 6'b001111 59 | `define ori 6'b001101 60 | `define addi 6'b001000 61 | `define addiu 6'b001001 62 | `define andi 6'b001100 63 | `define xori 6'b001110 64 | `define slti 6'b001010 65 | `define sltiu 6'b001011 66 | 67 | //J 68 | //opcode 69 | `define jal 6'b000011 70 | `define j 6'b000010 71 | 72 | //wire select of instr 73 | `define fun 5:0 74 | `define op 31:26 75 | `define rs 25:21 76 | `define rt 20:16 77 | `define rd 15:11 78 | `define shamt 10:6 79 | `define imm26 25:0 80 | `define imm16 15:0 81 | -------------------------------------------------------------------------------- /P6/data_ext.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:31:17 12/01/2020 7 | // Design Name: 8 | // Module Name: data_ext 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module data_ext( 22 | input [1:0] A, 23 | input [31:0] Din, 24 | input [2:0] op, 25 | output reg [31:0] Dout 26 | ); 27 | always@(*)begin 28 | case(op) 29 | 3'b000:begin 30 | Dout=Din; 31 | end 32 | 3'b001:begin 33 | case(A) 34 | 2'b00:Dout={{24{1'b0}},Din[7:0]}; 35 | 2'b01:Dout={{24{1'b0}},Din[15:8]}; 36 | 2'b10:Dout={{24{1'b0}},Din[23:16]}; 37 | 2'b11:Dout={{24{1'b0}},Din[31:24]}; 38 | default:Dout=0; 39 | endcase 40 | end 41 | 3'b010:begin 42 | case(A) 43 | 2'b00:Dout={{24{Din[7]}},Din[7:0]}; 44 | 2'b01:Dout={{24{Din[15]}},Din[15:8]}; 45 | 2'b10:Dout={{24{Din[23]}},Din[23:16]}; 46 | 2'b11:Dout={{24{Din[31]}},Din[31:24]}; 47 | default:Dout=0; 48 | endcase 49 | end 50 | 3'b011:begin 51 | case(A[1]) 52 | 1'b0:Dout={{16{1'b0}},Din[15:0]}; 53 | 1'b1:Dout={{16{1'b0}},Din[31:16]}; 54 | default:Dout=0; 55 | endcase 56 | end 57 | 3'b100:begin 58 | case(A[1]) 59 | 1'b0:Dout={{16{Din[15]}},Din[15:0]}; 60 | 1'b1:Dout={{16{Din[31]}},Din[31:16]}; 61 | default:Dout=0; 62 | endcase 63 | end 64 | default:Dout=0; 65 | endcase 66 | end 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /P6/mipsAutoTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ns 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 14:32:05 11/03/2020 8 | // Design Name: mips 9 | // Module Name: D:/iseproject/mips/mips_tb.v 10 | // Project Name: mips 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: mips 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module mipsAutoTest; 26 | 27 | // Inputs 28 | reg clk; 29 | reg reset; 30 | 31 | // Output 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | mips uut ( 35 | .clk(clk), 36 | .reset(reset) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | clk = 0; 42 | reset = 1; 43 | 44 | // Wait 100 ns for global reset to finish 45 | #12; 46 | reset = 0; 47 | // Add stimulus here 48 | 49 | end 50 | always#5 clk=~clk; 51 | endmodule 52 | 53 | -------------------------------------------------------------------------------- /P6/p6_fzc2.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P6/p6_fzc2.zip -------------------------------------------------------------------------------- /P6/pcCalc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module pcCalc( 3 | input [31:0] pc, 4 | input [31:0] pc_D4, 5 | input [31:0] imm, 6 | input [31:0] rsData, 7 | output reg [31:0] npc, 8 | input [3:0] branch, 9 | input jump, 10 | input zero, 11 | input pcSrc, 12 | input [25:0] imm26 13 | ); 14 | always@(*)begin 15 | case(pcSrc) 16 | 0:begin 17 | if( zero&&(branch!=0) )begin 18 | npc=pc_D4+(imm<<2); 19 | end 20 | else begin 21 | npc=pc+4; 22 | end 23 | end 24 | 1:begin 25 | if(jump)begin 26 | npc={pc_D4[31:28],imm26,{2{1'b0}}}; 27 | end 28 | else begin 29 | npc=rsData; 30 | end 31 | end 32 | default:npc=32'h00003000; 33 | endcase 34 | end 35 | endmodule -------------------------------------------------------------------------------- /P6/store_judge.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:57:51 12/01/2020 7 | // Design Name: 8 | // Module Name: store_judge 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module store_judge( 22 | input [1:0] op, 23 | output reg [3:0] BE, 24 | input [1:0] A_1_0 25 | ); 26 | always@(*)begin 27 | BE=4'b0000; 28 | case(op) 29 | 2'b00:begin //sw 30 | BE=4'b1111; 31 | end 32 | 2'b01:begin //sh 33 | BE=(A_1_0[1]==1'b1)?4'b1100:4'b0011; 34 | end 35 | 2'b10:begin //sb 36 | BE=(A_1_0==2'b00)?4'b0001: 37 | (A_1_0==2'b01)?4'b0010: 38 | (A_1_0==2'b10)?4'b0100: 39 | (A_1_0==2'b11)?4'b1000: 40 | 4'b0000; 41 | end 42 | default:begin 43 | BE=4'b0000; 44 | end 45 | endcase 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /P6/tb_div_mult.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 21:01:55 12/01/2020 8 | // Design Name: MULT_DIV 9 | // Module Name: E:/computer/verilog_ISE/CO/P6/tb_div_mult.v 10 | // Project Name: P6 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: MULT_DIV 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module tb_div_mult; 26 | 27 | // Inputs 28 | reg reset; 29 | reg clk; 30 | reg start; 31 | reg [31:0] A; 32 | reg [31:0] B; 33 | reg op; 34 | 35 | // Outputs 36 | wire busy; 37 | wire [31:0] HI; 38 | wire [31:0] LO; 39 | 40 | // Instantiate the Unit Under Test (UUT) 41 | MULT_DIV uut ( 42 | .reset(reset), 43 | .clk(clk), 44 | .start(start), 45 | .busy(busy), 46 | .A(A), 47 | .B(B), 48 | .HI(HI), 49 | .LO(LO), 50 | .op(op) 51 | ); 52 | 53 | initial begin 54 | // Initialize Inputs 55 | reset = 1; 56 | clk = 0; 57 | start = 0; 58 | A = 0; 59 | B = 0; 60 | op = 0; 61 | 62 | // Wait 100 ns for global reset to finish 63 | #10; 64 | A=32'h00001234; 65 | B=32'h000012; 66 | op=1; 67 | start=1; 68 | reset=0; 69 | #10 start=0; 70 | op=0; 71 | #200; 72 | A=32'h00001234; 73 | B=32'h00001212; 74 | op=0; 75 | start=1; 76 | #10 start=0; 77 | // Add stimulus here 78 | 79 | end 80 | always #5 clk<=~clk; 81 | endmodule 82 | 83 | -------------------------------------------------------------------------------- /P6/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:24:39 12/01/2020 7 | // Design Name: 8 | // Module Name: test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module test( 22 | ); 23 | reg [31:0] x=32'h0000000f; 24 | always@(*)begin 25 | $display("%h",x/4*4); 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /P6/冒险单元.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P6/冒险单元.xlsx -------------------------------------------------------------------------------- /P7/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU( 3 | input [31:0] dataA, 4 | input [31:0] dataB, 5 | input [3:0] aluCtrl, 6 | output reg [31:0] result, 7 | output reg zero, 8 | input [4:0] shamt, 9 | output of 10 | ); 11 | reg temp; 12 | always@(*)begin 13 | result=0;temp=0; 14 | case(aluCtrl) 15 | 4'b0000:begin //& 16 | result = dataA&dataB; 17 | end 18 | 4'b0001:begin //| 19 | result = dataA|dataB; 20 | end 21 | 4'b0010:begin //+ 22 | {temp,result} = {dataA[31],dataA}+{dataB[31],dataB}; 23 | end 24 | 4'b0011:begin //- 25 | {temp,result} = {dataA[31],dataA}-{dataB[31],dataB}; 26 | end 27 | 4'b0100:begin //nor 28 | result = ~(dataA | dataB); 29 | end 30 | 4'b0101:begin //xor 31 | result = dataA^dataB; 32 | end 33 | 4'b0110:begin //logical left shift 34 | result = dataB<>shamt; 38 | end 39 | 4'b1000:begin //suanshu right logical 40 | result = ($signed(dataB))>>>shamt; 41 | end 42 | 4'b1001:begin //signed A1 slt slti 43 | result = $signed(dataA)<$signed(dataB)?32'b1:32'b0; 44 | end 45 | 4'b1010:begin //unsigned A1 sltu sltiu 46 | result = dataA=0); 36 | assign gtz=(($signed(d1))>0); 37 | assign equal=(eq&&branch==4'b0001)||(~eq&&branch==4'b0010)||(gtz&&branch==4'b0011) 38 | ||(lez&&branch==4'b0100)||(gez&&branch==4'b0101)||(ltz&&branch==4'b0110); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /P7/CP0.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `include "constants.v" 3 | module CP0( 4 | input [4:0] A1, 5 | input [4:0] A2, 6 | input [31:0] Din, 7 | input [31:0] PC, 8 | input [6:2] ExcCode, 9 | input [5:0] HWInt, 10 | input We, 11 | input EXLSet, 12 | input EXLClr, 13 | input clk, 14 | input reset, 15 | output IntReq, 16 | output reg [31:0] EPC, 17 | output [31:0] DOut, 18 | input delayslot, 19 | input syscall 20 | ); 21 | 22 | //grf logic 23 | //SR 24 | reg [15:10] SRIM; 25 | reg EXL,IE; 26 | wire [31:0] SR={16'b0,SRIM,8'b0,EXL,IE}; 27 | //CAUSE 28 | reg BD; 29 | reg [15:10] IP; 30 | reg [6:2] excCode; 31 | wire [31:0] CAUSE={BD,15'b0,IP,3'b0,excCode,2'b0}; 32 | //PRID 33 | reg [31:0] PRID; 34 | 35 | //combinational logic 36 | wire intr,exc; 37 | 38 | assign intr=(|(HWInt & SRIM)) && IE && !EXL ; 39 | assign exc=(ExcCode!=0); 40 | assign IntReq=intr|exc; 41 | assign DOut=(A1==`CP0_SR)?SR: 42 | (A1==`CP0_CAUSE)?CAUSE: 43 | (A1==`CP0_EPC)?EPC: 44 | (A1==`CP0_PRID)?PRID:32'b0; 45 | always@(posedge clk)begin 46 | if(reset)begin 47 | SRIM<=6'b0; 48 | EXL<=1'b0; 49 | IE<=1'b0; 50 | BD<=1'b0; 51 | IP<=6'b0; 52 | excCode<=5'b0; 53 | EPC<=0; 54 | PRID<=32'd19373573; 55 | end 56 | else begin 57 | //IP<=0; 58 | IP<=HWInt; 59 | if(We)begin 60 | case(A2) 61 | `CP0_SR: {SRIM,EXL,IE}<={Din[15:10],Din[1:0]}; 62 | `CP0_EPC: EPC<={Din[31:2],2'b00}; 63 | default: PRID<=32'd19373573; 64 | endcase 65 | end 66 | if(EXLSet)begin 67 | EXL<=1'b1; 68 | end 69 | else if(EXLClr)begin 70 | EXL<=1'b0; 71 | end 72 | if(intr)begin 73 | BD<=delayslot; 74 | excCode<=0; 75 | EPC<=(delayslot)?({PC[31:2],2'b00}-4):({PC[31:2], 2'b00}); 76 | end 77 | else if(ExcCode!=0)begin 78 | BD<=delayslot; 79 | excCode<=ExcCode; 80 | EPC<=(delayslot)?({PC[31:2],2'b00}-4):({PC[31:2], 2'b00}); 81 | end 82 | end 83 | end 84 | endmodule 85 | 86 | 87 | 88 | -------------------------------------------------------------------------------- /P7/D2E.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:02:12 11/23/2020 7 | // Design Name: 8 | // Module Name: D2E 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module D2E( 22 | input [31:0] instr_D, 23 | input [31:0] pc_D, 24 | input [31:0] pc_D4, 25 | input [31:0] pc_D8, 26 | output reg [31:0] pc_E, 27 | output reg [31:0] pc_E4, 28 | output reg [31:0] pc_E8, 29 | input [31:0] grf_RD1, 30 | input [31:0] grf_RD2, 31 | input [31:0] ext_D, 32 | output reg [31:0] ext_E, 33 | output reg [31:0] instr_E, 34 | output reg [31:0] rs_E, 35 | output reg [31:0] rt_E, 36 | input clk, 37 | input reset, 38 | input [4:0] excCode_D, 39 | output reg [4:0] excCode_E, 40 | input BD_D, 41 | output reg BD_E 42 | ); 43 | always@(posedge clk)begin 44 | if(reset)begin 45 | pc_E<=32'h00000000; 46 | pc_E4<=32'h00000000; 47 | pc_E8<=32'h00000000; 48 | ext_E<=0; 49 | instr_E<=0; 50 | rs_E<=0; 51 | rt_E<=0; 52 | excCode_E<=0; 53 | BD_E<=0; 54 | end 55 | else begin 56 | pc_E<=pc_D; 57 | pc_E4<=pc_D4; 58 | pc_E8<=pc_D8; 59 | ext_E<=ext_D; 60 | instr_E<=instr_D; 61 | rs_E<=grf_RD1; 62 | rt_E<=grf_RD2; 63 | excCode_E<=excCode_D; 64 | BD_E<=BD_D; 65 | end 66 | end 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /P7/DM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module DM( 3 | input [31:0] A, 4 | input [31:0] WD, 5 | output [31:0] RD, 6 | input RE, 7 | input WE, 8 | input clk, 9 | input reset, 10 | input [31:0] pc, 11 | input stall_D, 12 | input [3:0] BE 13 | ); 14 | reg [31:0] dm [0:4095]; 15 | //wire [11:0] addr; 16 | //assign addr=A[13:2]; 17 | integer i=0; 18 | assign RD=dm[A[13:2]]; 19 | 20 | always@(posedge clk)begin 21 | if(reset)begin 22 | for(i=0;i<=12'hfff;i=i+1)begin 23 | dm[i]<=0; 24 | end 25 | end 26 | else begin 27 | if(WE&&A<32'h3000)begin 28 | case(BE) 29 | 4'b1111:begin 30 | dm[A[13:2]]<=WD; 31 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,WD); 32 | //$display("@%h: *%h <= %h",pc,A/4*4,WD); 33 | end 34 | 4'b0011:begin 35 | dm[A[13:2]][15:0]<=WD[15:0]; 36 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:16],WD[15:0]}); 37 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:16],WD[15:0]}); 38 | end 39 | 4'b1100:begin 40 | dm[A[13:2]][31:16]<=WD[15:0]; 41 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{WD[15:0],dm[A[13:2]][15:0]}); 42 | //$display("@%h: *%h <= %h",pc,A/4*4,{WD[15:0],dm[A[13:2]][15:0]}); 43 | end 44 | 4'b0001:begin 45 | dm[A[13:2]][7:0]<=WD[7:0]; 46 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:8],WD[7:0]}); 47 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:8],WD[7:0]}); 48 | end 49 | 4'b0010:begin 50 | dm[A[13:2]][15:8]<=WD[7:0]; 51 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:16],WD[7:0],dm[A[13:2]][7:0]}); 52 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:16],WD[7:0],dm[A[13:2]][7:0]}); 53 | end 54 | 4'b0100:begin 55 | dm[A[13:2]][23:16]<=WD[7:0]; 56 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{dm[A[13:2]][31:24],WD[7:0],dm[A[13:2]][15:0]}); 57 | //$display("@%h: *%h <= %h",pc,A/4*4,{dm[A[13:2]][31:24],WD[7:0],dm[A[13:2]][15:0]}); 58 | end 59 | 4'b1000:begin 60 | dm[A[13:2]][31:24]<=WD[7:0]; 61 | $display("%d@%h: *%h <= %h",$time,pc,A/4*4,{WD[7:0],dm[A[13:2]][23:0]}); 62 | //$display("@%h: *%h <= %h",pc,A/4*4,{WD[7:0],dm[A[13:2]][23:0]}); 63 | end 64 | endcase 65 | end 66 | end 67 | end 68 | endmodule -------------------------------------------------------------------------------- /P7/E2M.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:25:41 11/23/2020 7 | // Design Name: 8 | // Module Name: E2M 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module E2M( 22 | input [31:0] instr_E, 23 | input [31:0] pc_E, 24 | input [31:0] pc_E4, 25 | input [31:0] pc_E8, 26 | input [31:0] rt_E, 27 | input [31:0] aluRet_E, 28 | input [31:0] ext_E, 29 | input [31:0] mdOut_E, 30 | output reg [31:0] ext_M, 31 | output reg [31:0] pc_M, 32 | output reg [31:0] pc_M4, 33 | output reg [31:0] pc_M8, 34 | output reg [31:0] aluRet_M, 35 | output reg [31:0] instr_M, 36 | output reg [31:0] rt_M, 37 | output reg [31:0] mdOut_M, 38 | input clk, 39 | input reset, 40 | input [4:0] excCode_E, 41 | output reg [4:0] excCode_M, 42 | input of_E, 43 | output reg of_M, 44 | input BD_E, 45 | output reg BD_M 46 | ); 47 | always@(posedge clk)begin 48 | if(reset)begin 49 | pc_M<=32'h00000000; 50 | pc_M4<=32'h00000000; 51 | pc_M8<=32'h00000000; 52 | aluRet_M<=0; 53 | instr_M<=0; 54 | rt_M<=0; 55 | ext_M<=0; 56 | mdOut_M<=0; 57 | excCode_M<=0; 58 | of_M<=0; 59 | BD_M<=0; 60 | end 61 | else begin 62 | pc_M<=pc_E; 63 | pc_M4<=pc_E4; 64 | pc_M8<=pc_E8; 65 | aluRet_M<=aluRet_E; 66 | instr_M<=instr_E; 67 | rt_M<=rt_E; 68 | ext_M<=ext_E; 69 | mdOut_M<=mdOut_E; 70 | excCode_M<=excCode_E; 71 | of_M<=of_E; 72 | BD_M<=BD_E; 73 | end 74 | end 75 | 76 | 77 | endmodule 78 | -------------------------------------------------------------------------------- /P7/EXT.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:54:09 11/23/2020 7 | // Design Name: 8 | // Module Name: EXT 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module EXT( 22 | input [15:0] imm16, 23 | input extOp, 24 | output reg [31:0] ext_D 25 | ); 26 | always@(*)begin 27 | case(extOp) 28 | 0:begin 29 | ext_D={{16{imm16[15]}},imm16}; 30 | end 31 | 1:begin 32 | ext_D={{16{1'b0}},imm16}; 33 | end 34 | default:begin 35 | ext_D=0; 36 | end 37 | endcase 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /P7/F2D.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:48:07 11/23/2020 7 | // Design Name: 8 | // Module Name: F2D 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module F2D( 22 | input clk, 23 | input reset, 24 | input en, 25 | input [31:0] instr_F, 26 | input [31:0] pc_F, 27 | input [31:0] npc, 28 | input [4:0] excCode_F, 29 | output reg [4:0] excCode_D, 30 | output reg [31:0] pc_D, 31 | output reg [31:0] pc_D4, 32 | output reg [31:0] pc_D8, 33 | output reg [31:0] instr_D, 34 | input BD_F, 35 | output reg BD_D 36 | ); 37 | always@(posedge clk)begin 38 | if(reset)begin 39 | pc_D<=32'h00000000; 40 | pc_D4<=32'h00000000; 41 | pc_D8<=32'h00000000; 42 | instr_D<=0; 43 | excCode_D<=5'b0; 44 | BD_D<=1'b0; 45 | end 46 | else if(en) begin 47 | pc_D<=pc_F; 48 | pc_D4<=pc_F+4; 49 | pc_D8<=pc_F+8; 50 | instr_D<=instr_F; 51 | excCode_D<=excCode_F; 52 | BD_D<=BD_F; 53 | end 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /P7/GRF.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module GRF( 3 | input [4:0] RA1, 4 | input [4:0] RA2, 5 | output [31:0] RD1, 6 | output [31:0] RD2, 7 | input [4:0] WA, 8 | input [31:0] WD, 9 | input WE, 10 | input reset, 11 | input clk, 12 | input [31:0] pc_W, 13 | input stall_D 14 | ); 15 | reg [31:0] gpr [31:0]; 16 | assign RD1=(WA==RA1&&WA&&WE)?WD:gpr[RA1]; 17 | assign RD2=(WA==RA2&&WA&&WE)?WD:gpr[RA2]; 18 | integer i=0; 19 | 20 | always@(posedge clk)begin 21 | if(reset)begin 22 | for(i=0;i<32;i=i+1)begin 23 | gpr[i]<=32'b0; 24 | end 25 | end 26 | else begin 27 | if(WE)begin 28 | if(WA)gpr[WA]<=WD; 29 | else gpr[WA]<=0; 30 | end 31 | end 32 | end 33 | 34 | always@(posedge clk)begin 35 | if(/*stall_D &*/ WE & ~reset)begin 36 | $display("%d@%h: $%d <= %h", $time, pc_W, WA, WD); 37 | //$display("@%h: $%d <= %h", pc_W, WA, WD); 38 | end 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /P7/IM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module IM( 3 | input [31:0] pc, 4 | output reg [31:0] instr 5 | ); 6 | reg [31:0] instruction [0:4095]; 7 | reg [11:0] addr; 8 | 9 | integer file_wr,i; 10 | initial begin 11 | for(i=0;i<4096;i=i+1)begin 12 | instruction[i]=0; 13 | end 14 | $readmemh("code.txt",instruction); 15 | $readmemh("code_handler.txt", instruction, 1120, 2047); 16 | end 17 | 18 | always@(*)begin 19 | addr=pc[13:2]-12'hc00; 20 | instr=instruction[addr]; 21 | end 22 | endmodule -------------------------------------------------------------------------------- /P7/L13-MIPS系统结构-V1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P7/L13-MIPS系统结构-V1.pdf -------------------------------------------------------------------------------- /P7/L15-支持IO.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P7/L15-支持IO.pdf -------------------------------------------------------------------------------- /P7/M2W.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:33:58 11/23/2020 7 | // Design Name: 8 | // Module Name: M2W 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module M2W( 22 | input [31:0] instr_M, 23 | input [31:0] pc_M, 24 | input [31:0] pc_M4, 25 | input [31:0] pc_M8, 26 | input [31:0] rt_M, 27 | input [31:0] aluRet_M, 28 | input [31:0] RD_M, 29 | input [31:0] ext_M, 30 | input [31:0] mdOut_M, 31 | output reg [31:0] ext_W, 32 | output reg [31:0] pc_W, 33 | output reg [31:0] pc_W4, 34 | output reg [31:0] pc_W8, 35 | output reg [31:0] aluRet_W, 36 | output reg [31:0] instr_W, 37 | output reg [31:0] rt_W, 38 | output reg [31:0] RD_W, 39 | output reg [31:0] mdOut_W, 40 | input clk, 41 | input reset, 42 | input [31:0] cp0rd_M, 43 | output reg [31:0] cp0rd_W 44 | ); 45 | 46 | always@(posedge clk)begin 47 | if(reset)begin 48 | pc_W<=32'h00000000; 49 | pc_W4<=32'h00000000; 50 | pc_W8<=32'h00000000; 51 | aluRet_W<=0; 52 | instr_W<=0; 53 | rt_W<=0; 54 | RD_W<=0; 55 | ext_W<=0; 56 | mdOut_W<=0; 57 | cp0rd_W<=0; 58 | end 59 | else begin 60 | pc_W<=pc_M; 61 | pc_W4<=pc_M4; 62 | pc_W8<=pc_M8; 63 | aluRet_W<=aluRet_M; 64 | instr_W<=instr_M; 65 | rt_W<=rt_M; 66 | RD_W<=RD_M; 67 | ext_W<=ext_M; 68 | mdOut_W<=mdOut_M; 69 | cp0rd_W<=cp0rd_M; 70 | end 71 | end 72 | endmodule 73 | -------------------------------------------------------------------------------- /P7/MUX.v: -------------------------------------------------------------------------------- 1 | module writeASel( 2 | input [4:0] rt, 3 | input [4:0] rd, 4 | input [1:0] regDst, 5 | output reg [4:0] WA 6 | ); 7 | always@(*)begin 8 | case(regDst) 9 | 0:begin 10 | WA=rt; 11 | end 12 | 1:begin 13 | WA=rd; 14 | end 15 | 2:begin 16 | WA=5'b11111; 17 | end 18 | default:begin 19 | WA=WA; 20 | end 21 | endcase 22 | end 23 | endmodule 24 | 25 | module aluDSel( 26 | input [31:0] rtData, 27 | input [31:0] imm32, 28 | input aluSrc, 29 | output [31:0] aluDataB 30 | ); 31 | assign aluDataB=(aluSrc)?imm32:rtData; 32 | endmodule 33 | 34 | module writeDSel( 35 | input [31:0] aluOut, 36 | input [31:0] dmRd, 37 | input [31:0] pcPlus8, 38 | input [2:0] memToReg, 39 | input [31:0] mdOut_W, 40 | input [31:0] cp0rd_W, 41 | output reg [31:0] writeD 42 | ); 43 | always@(*)begin 44 | case(memToReg) 45 | 3'b000:begin 46 | writeD=aluOut; 47 | end 48 | 3'b001:begin 49 | writeD=dmRd; 50 | end 51 | 3'b010:begin 52 | writeD=pcPlus8; 53 | end 54 | 3'b011:begin 55 | writeD=mdOut_W; 56 | end 57 | 3'b100:begin 58 | writeD=cp0rd_W; 59 | end 60 | default:begin 61 | writeD=0; 62 | end 63 | endcase 64 | end 65 | endmodule 66 | 67 | module hiloSel( 68 | input [31:0] HI, 69 | input [31:0] LO, 70 | input sel, 71 | output [31:0] mdOut_E 72 | ); 73 | assign mdOut_E=sel==1?LO:HI; 74 | endmodule 75 | 76 | module shrsSel( 77 | input [4:0] shamt, 78 | input [4:0] rs_4_0, 79 | input sel, 80 | output [4:0] shamt_out 81 | ); 82 | assign shamt_out=sel==1?shamt:rs_4_0; 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /P7/Mars.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P7/Mars.jar -------------------------------------------------------------------------------- /P7/P7.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /P7/P7_doc_fzc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P7/P7_doc_fzc.pdf -------------------------------------------------------------------------------- /P7/PC.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:35:46 11/23/2020 7 | // Design Name: 8 | // Module Name: PC 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module PC( 22 | input clk, 23 | input reset, 24 | input [31:0] next_pc, 25 | output reg [31:0] pc, 26 | input en 27 | ); 28 | always@(posedge clk)begin 29 | if(reset)begin 30 | pc<=32'h00003000; 31 | end 32 | else if(en)begin 33 | pc<=next_pc; 34 | end 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /P7/Timer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define IDLE 2'b00 3 | `define LOAD 2'b01 4 | `define CNT 2'b10 5 | `define INT 2'b11 6 | 7 | `define ctrl mem[0] 8 | `define preset mem[1] 9 | `define count mem[2] 10 | module TC( 11 | input clk, 12 | input reset, 13 | input [31:2] Addr, 14 | input WE, 15 | input [31:0] Din, 16 | output [31:0] Dout, 17 | output IRQ 18 | ); 19 | 20 | reg [1:0] state; 21 | reg [31:0] mem [2:0]; 22 | 23 | reg _IRQ; 24 | assign IRQ = `ctrl[3] & _IRQ; 25 | 26 | assign Dout = mem[Addr[3:2]]; 27 | 28 | wire [31:0] load = Addr[3:2] == 0 ? {28'h0, Din[3:0]} : Din; 29 | 30 | integer i; 31 | always @(posedge clk) begin 32 | if(reset) begin 33 | state <= 0; 34 | for(i = 0; i < 3; i = i+1) mem[i] <= 0; 35 | _IRQ <= 0; 36 | end 37 | else if(WE) begin 38 | //$display("%d@: *%h <= %h", $time, {Addr, 2'b00}, load); 39 | mem[Addr[3:2]] <= load; 40 | end 41 | else begin 42 | case(state) 43 | `IDLE : if(`ctrl[0]) begin 44 | state <= `LOAD; 45 | _IRQ <= 1'b0; 46 | end 47 | `LOAD : begin 48 | `count <= `preset; 49 | state <= `CNT; 50 | end 51 | `CNT : 52 | if(`ctrl[0]) begin 53 | if(`count > 1) `count <= `count-1; 54 | else begin 55 | `count <= 0; 56 | state <= `INT; 57 | _IRQ <= 1'b1; 58 | end 59 | end 60 | else state <= `IDLE; 61 | default : begin 62 | if(`ctrl[2:1] == 2'b00) `ctrl[0] <= 1'b0; 63 | else _IRQ <= 1'b0; 64 | state <= `IDLE; 65 | end 66 | endcase 67 | end 68 | end 69 | 70 | endmodule 71 | -------------------------------------------------------------------------------- /P7/constants.v: -------------------------------------------------------------------------------- 1 | //R 2 | //opcode 3 | `define R 6'b000000 4 | //funcode 5 | //cal_r 6 | `define add 6'b100000 7 | `define addu 6'b100001 8 | `define sub 6'b100010 9 | `define subu 6'b100011 10 | `define AND 6'b100100 11 | `define OR 6'b100101 12 | `define NOR 6'b100111 13 | `define XOR 6'b100110 14 | 15 | `define sll 6'b000000 16 | `define sllv 6'b000100 17 | `define slt 6'b101010 18 | `define sltu 6'b101011 19 | `define sra 6'b000011 20 | `define srav 6'b000111 21 | `define srl 6'b000010 22 | `define srlv 6'b000110 23 | //jump to rs 24 | `define jr 6'b001000 25 | `define jalr 6'b001001 26 | //hi and lo 27 | `define mfhi 6'b010000 28 | `define mflo 6'b010010 29 | `define mthi 6'b010001 30 | `define mtlo 6'b010011 31 | `define mult 6'b011000 32 | `define multu 6'b011001 33 | `define div 6'b011010 34 | `define divu 6'b011011 35 | 36 | //I 37 | //opcode 38 | //store and load 39 | `define lw 6'b100011 40 | `define lb 6'b100000 41 | `define lbu 6'b100100 42 | `define lh 6'b100001 43 | `define lhu 6'b100101 44 | `define sw 6'b101011 45 | `define sb 6'b101000 46 | `define sh 6'b101001 47 | //br 48 | `define beq 6'b000100 49 | `define bne 6'b000101 50 | `define bgtz 6'b000111 51 | `define blez 6'b000110 52 | `define bgeltz 6'b000001 53 | //bgeltz:20:16 to decide the instr 54 | `define bgez 5'b00001 55 | `define bltz 5'b00000 56 | 57 | //cal_i 58 | `define lui 6'b001111 59 | `define ori 6'b001101 60 | `define addi 6'b001000 61 | `define addiu 6'b001001 62 | `define andi 6'b001100 63 | `define xori 6'b001110 64 | `define slti 6'b001010 65 | `define sltiu 6'b001011 66 | 67 | //J 68 | //opcode 69 | `define jal 6'b000011 70 | `define j 6'b000010 71 | 72 | //exception and halt 73 | `define COP0 6'b010000 74 | `define eret 6'b011000 75 | `define instr_eret 32'h42000018 76 | `define mtc0rs 5'b00100 77 | `define mfc0rs 5'b00000 78 | `define CP0_SR 5'd12 79 | `define CP0_CAUSE 5'd13 80 | `define CP0_EPC 5'd14 81 | `define CP0_PRID 5'd15 82 | `define spe 6'b110111 83 | `define syscall 6'b001100 84 | 85 | //wire select of instr 86 | `define fun 5:0 87 | `define op 31:26 88 | `define rs 25:21 89 | `define rt 20:16 90 | `define rd 15:11 91 | `define shamt 10:6 92 | `define imm26 25:0 93 | `define imm16 15:0 94 | -------------------------------------------------------------------------------- /P7/data_ext.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:31:17 12/01/2020 7 | // Design Name: 8 | // Module Name: data_ext 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module data_ext( 22 | input [1:0] A, 23 | input [31:0] Din, 24 | input [2:0] op, 25 | output reg [31:0] Dout 26 | ); 27 | always@(*)begin 28 | case(op) 29 | 3'b000:begin 30 | Dout=Din; 31 | end 32 | 3'b001:begin 33 | case(A) 34 | 2'b00:Dout={{24{1'b0}},Din[7:0]}; 35 | 2'b01:Dout={{24{1'b0}},Din[15:8]}; 36 | 2'b10:Dout={{24{1'b0}},Din[23:16]}; 37 | 2'b11:Dout={{24{1'b0}},Din[31:24]}; 38 | default:Dout=0; 39 | endcase 40 | end 41 | 3'b010:begin 42 | case(A) 43 | 2'b00:Dout={{24{Din[7]}},Din[7:0]}; 44 | 2'b01:Dout={{24{Din[15]}},Din[15:8]}; 45 | 2'b10:Dout={{24{Din[23]}},Din[23:16]}; 46 | 2'b11:Dout={{24{Din[31]}},Din[31:24]}; 47 | default:Dout=0; 48 | endcase 49 | end 50 | 3'b011:begin 51 | case(A[1]) 52 | 1'b0:Dout={{16{1'b0}},Din[15:0]}; 53 | 1'b1:Dout={{16{1'b0}},Din[31:16]}; 54 | default:Dout=0; 55 | endcase 56 | end 57 | 3'b100:begin 58 | case(A[1]) 59 | 1'b0:Dout={{16{Din[15]}},Din[15:0]}; 60 | 1'b1:Dout={{16{Din[31]}},Din[31:16]}; 61 | default:Dout=0; 62 | endcase 63 | end 64 | default:Dout=0; 65 | endcase 66 | end 67 | 68 | endmodule 69 | -------------------------------------------------------------------------------- /P7/mips.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 20:44:06 12/16/2020 7 | // Design Name: 8 | // Module Name: mips 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module mips( 22 | input clk, 23 | input reset, 24 | input interrupt, 25 | output [31:0] addr 26 | ); 27 | 28 | wire PrWE_cpu_o,PrWE_bri_o,WeDEV0,WeDEV1,IRQ_tc0,IRQ_tc1; 29 | wire [31:2] PrAddr_cpu_o,PrAddr_bri_o; 30 | wire [31:0] PrWD_cpu_o,PrWD_bri_o,TCRD0,TCRD1,PrRD; 31 | 32 | Bridge Bridge (.PrAddr(PrAddr_cpu_o), .PrWE(PrWE_cpu_o), .PrWD(PrWD_cpu_o), .DEV0_RD(TCRD0), .DEV1_RD(TCRD0), 33 | .PrRD(PrRD), .DEV_Addr(PrAddr_bri_o), .DEV_WD(PrWD_bri_o), .WeDEV0(WeDEV0), .WeDEV1(WeDEV1)); 34 | 35 | TC Timer0(.clk(clk), .reset(reset), .Addr(PrAddr_bri_o), .WE(WeDEV0), .Din(PrWD_bri_o), .Dout(TCRD0), .IRQ(IRQ_tc0)); 36 | TC Timer1(.clk(clk), .reset(reset), .Addr(PrAddr_bri_o), .WE(WeDEV1), .Din(PrWD_bri_o), .Dout(TCRD1), .IRQ(IRQ_tc1)); 37 | 38 | cpu MyCPU (.reset(reset), .clk(clk), .interrupt(interrupt), .PrAddr(PrAddr_cpu_o), .PrWD(PrWD_cpu_o), 39 | .PrRD(PrRD), .PrWE(PrWE_cpu_o), .HWInt({3'b0,interrupt,IRQ_tc0,IRQ_tc1}),.PCAddr(addr)); 40 | endmodule 41 | -------------------------------------------------------------------------------- /P7/mips_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/1ps 2 | 3 | module mips_tb; 4 | 5 | wire [31:0] addr; 6 | reg clk,reset,interrupt; 7 | 8 | mips uut( 9 | .clk(clk),.reset(reset), 10 | .interrupt(interrupt), 11 | .addr(addr) 12 | ); 13 | 14 | initial begin 15 | clk<=0; 16 | reset<=1; 17 | interrupt<=0; 18 | #10; 19 | reset<=0; 20 | end 21 | 22 | always #5 clk<=~clk; 23 | 24 | endmodule -------------------------------------------------------------------------------- /P7/pcCalc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module pcCalc( 3 | input [31:0] pc, 4 | input [31:0] pc_D4, 5 | input [31:0] imm, 6 | input [31:0] rsData, 7 | output reg [31:0] npc, 8 | input [3:0] branch, 9 | input jump, 10 | input zero, 11 | input pcSrc, 12 | input [25:0] imm26 13 | ); 14 | always@(*)begin 15 | case(pcSrc) 16 | 0:begin 17 | if( zero&&(branch!=0) )begin 18 | npc=pc_D4+(imm<<2); 19 | end 20 | else begin 21 | npc=pc+4; 22 | end 23 | end 24 | 1:begin 25 | if(jump)begin 26 | npc={pc_D4[31:28],imm26,{2{1'b0}}}; 27 | end 28 | else begin 29 | npc=rsData; 30 | end 31 | end 32 | default:npc=32'h00003000; 33 | endcase 34 | end 35 | endmodule -------------------------------------------------------------------------------- /P7/store_judge.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 21:57:51 12/01/2020 7 | // Design Name: 8 | // Module Name: store_judge 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module store_judge( 22 | input [1:0] op, 23 | output reg [3:0] BE, 24 | input [1:0] A_1_0 25 | ); 26 | always@(*)begin 27 | BE=4'b0000; 28 | case(op) 29 | 2'b00:begin //sw 30 | BE=4'b1111; 31 | end 32 | 2'b01:begin //sh 33 | BE=(A_1_0[1]==1'b1)?4'b1100:4'b0011; 34 | end 35 | 2'b10:begin //sb 36 | BE=(A_1_0==2'b00)?4'b0001: 37 | (A_1_0==2'b01)?4'b0010: 38 | (A_1_0==2'b10)?4'b0100: 39 | (A_1_0==2'b11)?4'b1000: 40 | 4'b0000; 41 | end 42 | default:begin 43 | BE=4'b0000; 44 | end 45 | endcase 46 | end 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /P7/test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 22:24:39 12/01/2020 7 | // Design Name: 8 | // Module Name: test 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module test( 22 | ); 23 | reg [31:0] x=32'h0000000f; 24 | always@(*)begin 25 | $display("%h",x/4*4); 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /P7/test_file.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/P7/test_file.zip -------------------------------------------------------------------------------- /Pre/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU( 3 | input [3:0] inA, 4 | input [3:0] inB, 5 | input [1:0] op, 6 | output [3:0] ans 7 | ); 8 | 9 | assign ans = (op == 2'b00) ? inA & inB : 10 | (op == 2'b01) ? inA | inB : 11 | (op == 2'b10) ? inA ^ inB : 12 | (op == 2'b11) ? inA + inB : 4'b000 ; //error 13 | 14 | 15 | endmodule -------------------------------------------------------------------------------- /Pre/ALU1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module ALU( 3 | input [3:0] inA, 4 | input [3:0] inB, 5 | input [1:0] inC, 6 | input [1:0] op, 7 | output [3:0] ans 8 | ); 9 | 10 | 11 | assign ans = (op == 2'b00) ? $signed($signed(inA) >>> inC) : 12 | (op == 2'b01) ? inA>>inC : 13 | (op == 2'b10) ? inA-inB : 14 | (op == 2'b11) ? inA+inB : 4'b000 ; //error 15 | endmodule 16 | 17 | -------------------------------------------------------------------------------- /Pre/Pre.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Pre/alwaysALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 00:38:03 07/18/2020 7 | // Design Name: 8 | // Module Name: alwaysALU 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module alwaysALU( 22 | input [3:0] inA, 23 | input [3:0] inB, 24 | input [1:0] op, 25 | output reg [3:0] ans 26 | ); 27 | 28 | always@(*) 29 | begin 30 | case (op) 31 | 2'b00 : begin 32 | ans <= inA + inB; 33 | end 34 | 2'b01 : begin 35 | ans <= inA - inB; 36 | end 37 | 2'b10 : begin 38 | ans <= inA | inB; 39 | end 40 | 2'b11 : begin 41 | ans <= inA & inB; 42 | end 43 | default: begin 44 | ans <= 4'b000; 45 | end 46 | endcase 47 | end 48 | 49 | endmodule 50 | -------------------------------------------------------------------------------- /Pre/assignALU.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/Pre/assignALU.v -------------------------------------------------------------------------------- /Pre/counting-2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 10:41:14 10/01/2020 7 | // Design Name: 8 | // Module Name: code 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module code( 22 | input Clk, 23 | input Reset, 24 | input Slt, 25 | input En, 26 | output [63:0] Output0, 27 | output [63:0] Output1 28 | ); 29 | reg [1:0] cnt; 30 | reg [63:0] o0; 31 | reg [63:0] o1; 32 | initial begin 33 | o0=0; 34 | o1=0; 35 | cnt=0; 36 | end 37 | assign Output0=o0; 38 | assign Output1=o1; 39 | always @(posedge Clk) begin 40 | if(Reset) begin 41 | cnt=0; 42 | o0=0; 43 | o1=0; 44 | end 45 | else if(En) begin 46 | if(Slt==0) begin 47 | o0=o0+1; 48 | end 49 | else begin 50 | cnt=cnt+1; 51 | if(cnt==0) begin 52 | o1=o1+1; 53 | end 54 | end 55 | end 56 | end 57 | 58 | endmodule 59 | -------------------------------------------------------------------------------- /Pre/counting.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05:14:36 07/18/2020 7 | // Design Name: 8 | // Module Name: counting 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define S0 2'b00 22 | `define S1 2'b01 23 | `define S2 2'b10 24 | `define S3 2'b11 25 | module counting( 26 | input [1:0] num, 27 | input clk, 28 | output ans 29 | ); 30 | 31 | reg [1:0] status; 32 | 33 | initial 34 | begin 35 | status <= `S0; 36 | end 37 | 38 | always@(posedge clk) 39 | begin 40 | case(status) 41 | `S0 : begin 42 | if (num == 2'b01) 43 | begin 44 | status <= `S1; 45 | end 46 | else if (num == 2'b10) 47 | begin 48 | status <= `S0; 49 | end 50 | else if (num == 2'b11) 51 | begin 52 | status <= `S0; 53 | end 54 | else 55 | begin 56 | status <= `S0; //����һ�з�����������ص�״̬0 57 | end 58 | end 59 | 60 | `S1 : begin 61 | if (num == 2'b01) 62 | begin 63 | status <= `S1; 64 | end 65 | else if (num == 2'b10) 66 | begin 67 | status <= `S2; 68 | end 69 | else if (num == 2'b11) 70 | begin 71 | status <= `S0; 72 | end 73 | else 74 | begin 75 | status <= `S0; //����һ�з�����������ص�״̬0 76 | end 77 | end 78 | 79 | `S2 : begin 80 | if (num == 2'b01) 81 | begin 82 | status <= `S1; 83 | end 84 | else if (num == 2'b10) 85 | begin 86 | status <= `S0; 87 | end 88 | else if (num == 2'b11) 89 | begin 90 | status <= `S3; 91 | end 92 | else 93 | begin 94 | status <= `S0; //����һ�з�����������ص�״̬0 95 | end 96 | end 97 | 98 | `S3 : begin 99 | if (num == 2'b01) 100 | begin 101 | status <= `S1; 102 | end 103 | else if (num == 2'b10) 104 | begin 105 | status <= `S0; 106 | end 107 | else if (num == 2'b11) 108 | begin 109 | status <= `S0; 110 | end 111 | else 112 | begin 113 | status <= `S0; //����һ�з�����������ص�״̬0 114 | end 115 | end 116 | endcase 117 | end 118 | 119 | assign ans = (status == `S3) ? 1'b1 : 1'b0; 120 | endmodule 121 | -------------------------------------------------------------------------------- /Pre/counting1.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05:14:36 07/18/2020 7 | // Design Name: 8 | // Module Name: counting 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define S0 2'b00 22 | `define S1 2'b01 23 | `define S2 2'b10 24 | `define S3 2'b11 25 | module counting( 26 | input [1:0] num, 27 | input clk, 28 | output ans 29 | ); 30 | 31 | reg [1:0] status; 32 | 33 | initial 34 | begin 35 | status <= `S0; 36 | end 37 | 38 | always@(posedge clk) 39 | begin 40 | case(status) 41 | `S0 : begin 42 | if (num == 2'b01) 43 | begin 44 | status <= `S1; 45 | end 46 | else if (num == 2'b10) 47 | begin 48 | status <= `S0; 49 | end 50 | else if (num == 2'b11) 51 | begin 52 | status <= `S0; 53 | end 54 | else 55 | begin 56 | status <= `S0; 57 | end 58 | end 59 | 60 | `S1 : begin 61 | if (num == 2'b01) 62 | begin 63 | status <= `S1; 64 | end 65 | else if (num == 2'b10) 66 | begin 67 | status <= `S2; 68 | end 69 | else if (num == 2'b11) 70 | begin 71 | status <= `S0; 72 | end 73 | else 74 | begin 75 | status <= `S0; 76 | end 77 | end 78 | 79 | `S2 : begin 80 | if (num == 2'b01) 81 | begin 82 | status <= `S1; 83 | end 84 | else if (num == 2'b10) 85 | begin 86 | status <= `S0; 87 | end 88 | else if (num == 2'b11) 89 | begin 90 | status <= `S3; 91 | end 92 | else 93 | begin 94 | status <= `S0; 95 | end 96 | end 97 | 98 | `S3 : begin 99 | status <= `S3; 100 | end 101 | endcase 102 | end 103 | 104 | assign ans = (status == `S3) ? 1'b1 : 1'b0; 105 | endmodule 106 | -------------------------------------------------------------------------------- /Pre/counting2.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 05:14:36 07/18/2020 7 | // Design Name: 8 | // Module Name: counting 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | `define S0 2'b00 22 | `define S1 2'b01 23 | `define S2 2'b10 24 | `define S3 2'b11 25 | module counting( 26 | input [1:0] num, 27 | input clk, 28 | output ans 29 | ); 30 | 31 | reg [1:0] status; 32 | 33 | initial 34 | begin 35 | status <= `S0; 36 | end 37 | 38 | always@(posedge clk) 39 | begin 40 | case(status) 41 | `S0 : begin 42 | if (num == 2'b01) 43 | begin 44 | status <= `S1; 45 | end 46 | else if (num == 2'b10) 47 | begin 48 | status <= `S0; 49 | end 50 | else if (num == 2'b11) 51 | begin 52 | status <= `S0; 53 | end 54 | else 55 | begin 56 | status <= `S0; 57 | end 58 | end 59 | 60 | `S1 : begin 61 | if (num == 2'b01) 62 | begin 63 | status <= `S1; 64 | end 65 | else if (num == 2'b10) 66 | begin 67 | status <= `S2; 68 | end 69 | else if (num == 2'b11) 70 | begin 71 | status <= `S0; 72 | end 73 | else 74 | begin 75 | status <= `S0; 76 | end 77 | end 78 | 79 | `S2 : begin 80 | if (num == 2'b01) 81 | begin 82 | status <= `S1; 83 | end 84 | else if (num == 2'b10) 85 | begin 86 | status <= `S2; 87 | end 88 | else if (num == 2'b11) 89 | begin 90 | status <= `S3; 91 | end 92 | else 93 | begin 94 | status <= `S0; 95 | end 96 | end 97 | 98 | `S3 : begin 99 | if(num==2'b01) 100 | begin 101 | status<=`S1; 102 | end 103 | else if(num==2'b10) 104 | begin 105 | status<=`S0; 106 | end 107 | else if(num==2'b11) 108 | begin 109 | status<=`S3; 110 | end 111 | else 112 | begin 113 | status<=`S0; 114 | end 115 | end 116 | endcase 117 | end 118 | 119 | assign ans = (status == `S3) ? 1'b1 : 1'b0; 120 | endmodule 121 | -------------------------------------------------------------------------------- /Pre/febnacci.asm: -------------------------------------------------------------------------------- 1 | .data 2 | fibs: .space 48 # "array" of 12 words to contain fib values 3 | size: .word 12 # size of "array" 4 | space:.asciiz " " # space to insert between numbers 5 | head: .asciiz "The Fibonacci numbers are:\n" 6 | .text 7 | la $t0, fibs # load address of array 8 | la $t5, size # load address of size variable -------------------------------------------------------------------------------- /Pre/hamilton_hacker.asm: -------------------------------------------------------------------------------- 1 | .data 2 | bian: .space 260 3 | ap: .space 40 4 | space: .asciiz " " 5 | .text 6 | main: 7 | li $s1 1 8 | li $s7 4 9 | li $s2 0 10 | jal inputInt 11 | move $s4 $v0 12 | jal inputInt 13 | move $s5 $v0 #input n,m s4=n s5=m 14 | li $t0 1 15 | for_i: 16 | bgt $t0 $s5 for_i_end 17 | jal inputInt 18 | move $a0 $v0 19 | jal printInt 20 | 21 | la $a0,space 22 | li $v0,4 23 | syscall 24 | 25 | jal inputInt 26 | move $a0 $v0 27 | jal printInt 28 | 29 | la $a0,space 30 | li $v0,4 31 | syscall 32 | 33 | addi $t0 $t0 1 34 | j for_i 35 | for_i_end: 36 | 37 | la $a0,space 38 | li $v0,4 39 | syscall 40 | la $a0,space 41 | li $v0,4 42 | syscall 43 | la $a0,space 44 | li $v0,4 45 | syscall 46 | 47 | move $a0 $s4 48 | jal printInt 49 | 50 | la $a0,space 51 | li $v0,4 52 | syscall 53 | 54 | move $a0 $s5 55 | jal printInt 56 | 57 | li $v0 10 58 | syscall 59 | 60 | move $a0 $s5 61 | jal printInt 62 | 63 | 64 | 65 | inputInt: 66 | li $v0,5 67 | syscall 68 | jr $ra 69 | printInt: #a0-a3 is the parameter 70 | li $v0 1 71 | syscall 72 | jr $ra 73 | -------------------------------------------------------------------------------- /Pre/id_fsm.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module id_fsm( 3 | input [7:0] char, 4 | input clk, 5 | output out 6 | ); 7 | reg [3:0] s; 8 | reg [1:0] o; 9 | assign out=o; 10 | reg [7:0] ch; 11 | 12 | initial begin 13 | s=0; 14 | o=0; 15 | ch=0; 16 | end 17 | 18 | always @(posedge clk) begin 19 | ch=char; 20 | if(s==0) begin 21 | if((ch>=65&&ch<=90)||(ch>=97&&ch<=122)) begin 22 | s<=1; 23 | o<=0; 24 | end 25 | else begin 26 | o<=0; 27 | end 28 | end 29 | else if (s==1) begin 30 | if((ch>=65&&ch<=90)||(ch>=97&&ch<=122)) begin 31 | s<=1; 32 | o<=0; 33 | end 34 | else if(ch>=48&&ch<=57) begin 35 | s<=2; 36 | o<=1; 37 | end 38 | else begin 39 | s<=0; 40 | o<=0; 41 | end 42 | end 43 | else begin 44 | if(ch>=48&&ch<=57) begin 45 | s<=2; 46 | o<=1; 47 | end 48 | else begin 49 | s<=0; 50 | o<=0; 51 | end 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /Pre/jiecheng.asm: -------------------------------------------------------------------------------- 1 | .data 2 | b:.asciiz "\n" 3 | a: .byte 1004 4 | .text 5 | li $v0 5 6 | syscall 7 | move $s0 $v0 #s0-->n 8 | li $t0 1 9 | sb $t0 a($0) 10 | addi $t0 $t0 1 #t0-->i 11 | li $s1 2 #s1-->len of big number 12 | li $s7 10 13 | 14 | 15 | for_i_2_n: 16 | bgt $t0 $s0 for_1_end 17 | li $t1 0 #t1-->s 18 | li $t2 0 #t2-->c 19 | li $t3 0 #t3-->j 20 | for_j_0_len: 21 | beq $t3 $s1 for_2_end 22 | move $t4 $t3 23 | lb $t5 a($t4) #a[j] 24 | mult $t5 $t0 25 | mflo $t5 26 | add $t1 $t5 $t2 27 | div $t1 $s7 28 | mfhi $t6 29 | sb $t6 a($t4) 30 | mflo $t2 31 | addi $t3 $t3 1 32 | j for_j_0_len 33 | for_2_end: 34 | addi $t0 $t0 1 35 | addi $s1 $s1 2 36 | j for_i_2_n 37 | for_1_end: 38 | 39 | li $s4 0 40 | subi $t0 $s1 1 41 | for_i_len_0: 42 | bltz $t0 for_3_end 43 | move $t4 $t0 44 | lb $t5 a($t4) 45 | beqz $t5 next1 46 | li $s4 1 47 | move $a0 $t5 48 | li $v0 1 49 | syscall 50 | j next 51 | next1: 52 | beqz $s4 next 53 | move $a0 $t5 54 | li $v0 1 55 | syscall 56 | next: 57 | subi $t0 $t0 1 58 | j for_i_len_0 59 | for_3_end: 60 | 61 | la $a0 b 62 | li $v0 4 63 | syscall 64 | 65 | li $v0 10 66 | syscall 67 | 68 | -------------------------------------------------------------------------------- /Pre/mips1.asm: -------------------------------------------------------------------------------- 1 | .data 0x00001000 2 | str: .asciiz "hello world" 3 | num: .byte 1,2,3,4,5,6,7,8 4 | .text 5 | li $a0 0x00001000 6 | lw $t0,12($a0) 7 | -------------------------------------------------------------------------------- /Pre/mips2.asm: -------------------------------------------------------------------------------- 1 | 2 | .text 3 | li $t1, 100 #t1=100 4 | li $t2, 200 #t2=200 5 | 6 | slt $t3, $t1, $t2 #if(t1 2 | #include 3 | #include 4 | using namespace std; 5 | int bian[8][8]; 6 | int n,m; 7 | int ap[8]; 8 | int path[8]; 9 | void print() 10 | { 11 | for(int i=0;i>n>>m; 57 | for(int i=1;i<=m;i++) 58 | { 59 | int a,b; 60 | cin>>a>>b; 61 | bian[b][a]=bian[a][b]=1; 62 | } 63 | cout<<"**********\n"; 64 | cout<="a"&char<="z"|char>="A"&char<="Z")s<=1; 11 | else s<=0; 12 | end 13 | 1:begin 14 | if(char>="a"&char<="z"|char>="A"&char<="Z")s<=1; 15 | else if(char>="0"&char<="9")s<=2; 16 | else s<=0; 17 | end 18 | 2:begin 19 | if(char>="0"&char<="9")s<=2; 20 | else s<=0 21 | end 22 | end 23 | assign out=(s==2); 24 | endmodule -------------------------------------------------------------------------------- /Pre/组合逻辑作业T6.v: -------------------------------------------------------------------------------- 1 | module Seven_segment_digital_tube( 2 | input x3,input x2,input x1,input x0, 3 | output a,output b, output c,output d,output e,output f,output g 4 | ); 5 | assign a=!x2&!x0|!x3&x1|!x3&x2&x0|x2&x1|x3&!x2&!x1|x3&!x0 6 | assign b=!x1&!x0|!x3&x2&!x1|x2&!x0|x3&!x2|x3&x1 7 | assign c=!x2&!x0|x1&!x0|x3&x1|x3&x2 8 | assign d=!x3&!x2&!x0|!x2&x1&x0|x2&!x1&x0|x2&x1&!x0|x3&!x1 9 | assign e=!x3&!x1|!x3&x0|!x1&x0|!x3&x2|x3&!x2 10 | assign f=!x3&!x2|!x3&!x1&!x0|!x2&!x0|!x3&x1&x0|x3&!x1&x0 11 | assign g=!x2&x1|x1&!x0|!x3&x2&!x1|x3&!x2|x3&x0 12 | 13 | endmodule -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # BUAA-CO-2020 2 | 2020年秋季北航计组代码。This is My BUAA Computer Orgnization code project files. 3 | 4 | ## introduction 5 | 由于2020年秋季的北航计组实验由于时间冲突的原因只开课开到P7，P8没有开放，笔者很幸运地通关了，在这里还是放一下本菜鸡的代码，纪念一下那些熬夜奋战的时光 6 | 7 | 北航的计组课程目标是开发支持`MIPS`指令集的CPU，在这个过程中学习数字电路，汇编语言，计算机软硬件组成等基础知识。 8 | 9 | ## about Code 10 | ### Pre 基础知识学习 11 | 主要是`logisim`，`verilog`，`MIPS`以及相关工具（`ISE，Mars`等）的基本使用，为之后的各个Project打基础 12 | 13 | ### P0 logisim搭建基本电路 14 | 利用logisim搭建一些小的元件和状态机，难点主要在状态机搭建，要区分好`Moore`和`Mealy` 15 | 16 | ### P1 verilog搭建基本电路 17 | P1和P0内容差不多，只是工具变了，主要就是用verilog搭建小元件和状态机 18 | 19 | P1课上**初始化**一定要注意！！！笔者就是在课上因为没有对一些变量初始化挂了一次。 20 | 21 | ### P2 MIPS汇编语言 22 | 基本就是用MIPS写一些基本的简单算法题，如果有类似快排，二分查找这样的复杂一些的算法题会给参考的C源代码 23 | 24 | 课上难一些的也就是考**递归**算法翻译题,其他题基本都比较简单 25 | 26 | ### P3 logisim单周期CPU开发(8条指令) 27 | 课下:利用logisim搭建一个支持`{addu, subu, ori, lw, sw, beq, lui, nop}`指令集的单周期CPU 28 | 29 | 课上:扩展给定的指令 30 | 31 | ### P4 Verilog单周期CPU开发(10条指令) 32 | 课下:利用Verilog搭建一个支持`{addu, subu, ori, lw, sw, beq, lui, jr,nop,jal}`指令集的单周期CPU 33 | 34 | 课上:扩展给定的指令 35 | 36 | ### P5 Verilog简单流水线CPU开发(11条指令) 37 | 课下:利用Verilog搭建一个支持`{ addu, subu, ori, lw, sw, beq, lui, j, jal, jr, nop }`指令集的流水线CPU 38 | 39 | 课上:扩展给定的指令 40 | 41 | ### P6 Verilog复杂流水线CPU开发(51条指令) 42 | 课下:利用Verilog搭建一个支持`{LB、LBU、LH、LHU、LW、SB、SH、SW、ADD、ADDU、SUB、 SUBU、 MULT、 MULTU、 DIV、 DIVU、 SLL、 SRL、 SRA、SLLV、SRLV、SRAV、AND、OR、XOR、NOR、ADDI、ADDIU、ANDI、ORI、XORI、LUI、SLT、SLTI、SLTIU、SLTU、BEQ、BNE、BLEZ、BGTZ、BLTZ、BGEZ、J、JAL、JALR、JR、MFHI、MFLO、MTHI、MTLO}`指令集的流水线CPU 43 | 44 | 课上:扩展给定的指令 45 | 46 | ### P7 Verilog处理器系统设计_支持中断异常(54条指令) 47 | 课下:在P6的基础上新增`{eret,mfc0,mtc0}`三条中断/异常相关指令，新增异常处理模块，系统桥模块和定时器模块，和原本的CPU组成一个系统。 48 | 49 | 课上:强测+扩展一条简单的异常中断指令(后者不一定会出现) 50 | 51 | ### TestData 52 | 自己构造，或者从github收集，或者同学提供的测试数据，以及部分测试脚本 53 | 注：数据仅供参考，每年题目都可能会变化 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /TestData/Mars.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/Mars.jar -------------------------------------------------------------------------------- /TestData/My_test/1.txt: -------------------------------------------------------------------------------- 1 | 340a03ff 2 | 340b0001 3 | 0c000c04 4 | 03e06021 5 | 3402007b 6 | 03e00008 7 | -------------------------------------------------------------------------------- /TestData/My_test/2.txt: -------------------------------------------------------------------------------- 1 | 342104d2 2 | 1020000f 3 | 1021000e 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00211021 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 03e00008 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 0c000c07 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 34220000 24 | -------------------------------------------------------------------------------- /TestData/My_test/Mars.jar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/Mars.jar -------------------------------------------------------------------------------- /TestData/My_test/alu.txt: -------------------------------------------------------------------------------- 1 | 34210514 2 | 34420592 3 | 00411821 4 | 3c04007b 5 | 00831023 6 | -------------------------------------------------------------------------------- /TestData/My_test/ans.txt: -------------------------------------------------------------------------------- 1 | @00003000: $ 1 <= 0000007b 2 | Error in G:\P5_test\test_asm\other\testpoint4.asm line 2: Runtime exception at 0x00003004: fetch address not aligned on word boundary 0x0000007b 3 | 4 | Processing terminated due to errors. 5 | 6 | -------------------------------------------------------------------------------- /TestData/My_test/code.txt: -------------------------------------------------------------------------------- 1 | 340a03ff 2 | 340b0001 3 | 0c000c05 4 | 03e06021 5 | 08000c07 6 | 3402007b 7 | 03e00008 8 | 00000000 -------------------------------------------------------------------------------- /TestData/My_test/jump.txt: -------------------------------------------------------------------------------- 1 | 342104d2 2 | 10200002 3 | 10210001 4 | 03e00008 5 | 0c000c03 6 | 34220000 7 | -------------------------------------------------------------------------------- /TestData/My_test/log.txt: -------------------------------------------------------------------------------- 1 | Running: D:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe --nodebug --prj mips.prj -o mips.exe mipsAutoTest 2 | ISim P.20131013 (signature 0x7708f090) 3 | Number of CPUs detected in this system: 8 4 | Turning on mult-threading, number of parallel sub-compilation jobs: 16 5 | Determining compilation order of HDL files 6 | Analyzing Verilog file "G:\P5_test\ALU.v" into library work 7 | Analyzing Verilog file "G:\P5_test\CMP.v" into library work 8 | Analyzing Verilog file "G:\P5_test\constants.v" into library work 9 | Analyzing Verilog file "G:\P5_test\controller.v" into library work 10 | Analyzing Verilog file "G:\P5_test\D2E.v" into library work 11 | Analyzing Verilog file "G:\P5_test\DM.v" into library work 12 | Analyzing Verilog file "G:\P5_test\E2M.v" into library work 13 | Analyzing Verilog file "G:\P5_test\EXT.v" into library work 14 | Analyzing Verilog file "G:\P5_test\F2D.v" into library work 15 | Analyzing Verilog file "G:\P5_test\for_MUX.v" into library work 16 | Analyzing Verilog file "G:\P5_test\GRF.v" into library work 17 | Analyzing Verilog file "G:\P5_test\hazard_Unit.v" into library work 18 | Analyzing Verilog file "G:\P5_test\IM.v" into library work 19 | Analyzing Verilog file "G:\P5_test\instr_class.v" into library work 20 | Analyzing Verilog file "G:\P5_test\M2W.v" into library work 21 | Analyzing Verilog file "G:\P5_test\mips.v" into library work 22 | Analyzing Verilog file "G:\P5_test\mipsAutoTest.v" into library work 23 | Analyzing Verilog file "G:\P5_test\MIPS_CPU_P5_tb.v" into library work 24 | Analyzing Verilog file "G:\P5_test\mips_tb.v" into library work 25 | Analyzing Verilog file "G:\P5_test\MUX.v" into library work 26 | Analyzing Verilog file "G:\P5_test\PC.v" into library work 27 | Analyzing Verilog file "G:\P5_test\pcCalc.v" into library work 28 | Starting static elaboration 29 | Completed static elaboration 30 | Compiling module PC 31 | Compiling module IM 32 | Compiling module F2D 33 | Compiling module controller 34 | Compiling module GRF 35 | Compiling module EXT 36 | Compiling module CMP 37 | Compiling module pcCalc 38 | Compiling module D2E 39 | Compiling module aluDSel 40 | Compiling module ALU 41 | Compiling module aluRetSel 42 | Compiling module E2M 43 | Compiling module DM 44 | Compiling module M2W 45 | Compiling module writeDSel 46 | Compiling module writeASel 47 | Compiling module instr_class 48 | Compiling module hazard_Unit 49 | Compiling module forRsD 50 | Compiling module forRtD 51 | Compiling module forRsE 52 | Compiling module forRtE 53 | Compiling module forRtM 54 | Compiling module mips 55 | Compiling module mipsAutoTest 56 | Time Resolution for simulation is 1ps. 57 | Waiting for 11 sub-compilation(s) to finish... 58 | Compiled 26 Verilog Units 59 | Built simulation executable mips.exe 60 | Fuse Memory Usage: 33460 KB 61 | Fuse CPU Usage: 780 ms 62 | -------------------------------------------------------------------------------- /TestData/My_test/my.txt: -------------------------------------------------------------------------------- 1 | @00003000: $ 1 <= 00000078 2 | @00003004: $ 0 <= 00000000 3 | @00003008: $ 3 <= 00000078 4 | -------------------------------------------------------------------------------- /TestData/My_test/test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test.zip -------------------------------------------------------------------------------- /TestData/My_test/test1.txt: -------------------------------------------------------------------------------- 1 | 340304d2 2 | ac030000 3 | 0c000c08 4 | 00601021 5 | 00801823 6 | ac030008 7 | 8c070008 8 | 08000c0b 9 | 3c040541 10 | ac040010 11 | 03e00008 12 | 34120022 13 | 02447021 14 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint1.asm: -------------------------------------------------------------------------------- 1 | ori $2, 10 2 | ori $3, 5 3 | subu $1, $3, $2 4 | addu $4, $1, $2 5 | subu $4, $3, $2 6 | ori $4, 1 7 | subu $1, $2, $3 8 | lui $1, 10 9 | subu $1, $2, $3 10 | ori $2, 10 11 | sw $1, 0($0) 12 | subu $1, $2, $3 13 | sw $1, 4($0) 14 | subu $1, $2, $3 15 | subu $4, $2, $3 16 | beq $1, $4 QAQ 17 | ori $t0, 10 18 | ori $t1, 10 19 | QAQ: 20 | ori $t2, 10 21 | subu $1, $2, $3 22 | 23 | ori $2, 10 24 | ori $0, 10 25 | subu $1, $0, $2 26 | subu $0, $2, $1 27 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint10.asm: -------------------------------------------------------------------------------- 1 | lui $3, 3 2 | ori $2, 10 3 | addu $1, $2, $3 4 | lui $3, 3 5 | ori $2, 10 6 | subu $1, $3, $2 7 | ori $4, 10 8 | ori $5, 10 9 | beq $4, $5 QAQ 10 | ori $6, 10 11 | ori $7, 100 12 | QAQ: 13 | ori $7, 40 14 | sw $7, 0($7) 15 | lw $7, 0($7) 16 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint11.asm: -------------------------------------------------------------------------------- 1 | ori $1, 10 2 | ori $4, 2 3 | addu $0, $1, $2 4 | sw $1, 0($0) 5 | lw $1, 0($0) 6 | 7 | ori $3, 12 8 | sw $3, 0($3) 9 | lw $3, 0($3) 10 | addu $3, $4, $1 11 | lw $3, 0($3) 12 | addu $0, $1, $2 13 | sw $0, 0($0) 14 | lw $5, 0($0) 15 | lw $0, 0($0) 16 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint12.asm: -------------------------------------------------------------------------------- 1 | ori $t1,$t1,1 2 | ori $t2,$t2,2 3 | addu $t0,$t1,$t2 4 | nop 5 | sw $t0,0($0) -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint13.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint13.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint14.asm: -------------------------------------------------------------------------------- 1 | ori $2, 10 2 | ori $3, 5 3 | subu $1, $3, $2 4 | addu $4, $1, $2 5 | subu $4, $3, $2 6 | ori $4, 1 7 | subu $1, $2, $3 8 | lui $1, 10 9 | subu $1, $2, $3 10 | ori $2, 10 11 | sw $1, 0($0) 12 | subu $1, $2, $3 13 | sw $1, 4($0) 14 | subu $1, $2, $3 15 | subu $4, $2, $3 16 | beq $1, $4 QAQ 17 | ori $t0, 10 18 | ori $t1, 10 19 | QAQ: 20 | ori $t2, 10 21 | subu $1, $2, $3 22 | 23 | ori $2, 10 24 | ori $0, 10 25 | subu $1, $0, $2 26 | subu $0, $2, $1 27 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint15.asm: -------------------------------------------------------------------------------- 1 | lui $5, 233 2 | lui $6, 233 3 | lui $5, 122 4 | addu $6,$5,$5 5 | subu $6,$5,$5 6 | ori $6,123 7 | sw $5, 0($0) 8 | sw $6, 4($0) 9 | lw $7, 0($0) 10 | lw $8, 4($0) 11 | addu $9,$9,$8 12 | addu $10,$9,$8 13 | sw $10, 44($0) 14 | lw $11, 44($0) 15 | add $12,$11,$11 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint16.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint16.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint17.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint17.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint18.asm: -------------------------------------------------------------------------------- 1 | ori $t1,$t1,4 2 | ori $t2,$t2,8 3 | sw $t2,0($t1) 4 | 5 | lw $t2,0($t1) 6 | addu $t1,$t1,$t2 7 | 8 | lw $t2,0($t1) 9 | addu $t1,$t3,$t2 10 | 11 | addu $t3,$t4,$t5 12 | sw $t3,0($t1) 13 | 14 | ori $t3,$t3,12 15 | sw $t3,0($t2) 16 | lw $t4,0($t2) 17 | 18 | subu $1,$1,$1 19 | ori $12,$12,5 20 | ori $1,$1,16 21 | addu $16,$12,$1 22 | addu $18,$16,$1 23 | sw $18,16($1) 24 | 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint19.asm: -------------------------------------------------------------------------------- 1 | ori $1,$1,4 2 | ori $2,$2,10 3 | addu $3,$2,$3 4 | beq $2,$3,next 5 | ori $2,$0,0x3024 6 | jal next 7 | next: 8 | sw $2,0($0) 9 | lw $3,0($0) 10 | jr $2 11 | subu $2,$2,$1 12 | subu $3,$2,$1 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint2.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,123 2 | ori $5, $0, 234 3 | ori $4,$0,123 4 | beq $4,$3,next 5 | addu $30,$30,$5 6 | addu $31,$31,$5 7 | next: 8 | addu $t6,$6,$5 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint20.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,123 2 | ori $4,$3,0 3 | addu $5,$4,$3 4 | addu $6,$5,$4 5 | addu $7,$5,$6 6 | subu $8,$7,$6 7 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint21.asm: -------------------------------------------------------------------------------- 1 | ori $3, $0,12 2 | ori $4,$0,123 3 | sw $4,0($3) 4 | addu $5,$4,$0 5 | sw $5,4($3) -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint22.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint22.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint23.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .macro push(%d) 3 | sw %d,0($s4) 4 | addu $s4,$s4,$s3 5 | .end_macro 6 | 7 | .macro pop(%d) 8 | subu $s4, $s4, $s3 9 | lw %d, 0($s4) 10 | .end_macro 11 | 12 | .text 13 | ori $s0, $0, 0 14 | ori $s1, $0, 1 15 | ori $s2, $0, 2 16 | ori $s3, $0, 4 17 | ori $s4, $0, 0 18 | ori $a0, $0, 7 19 | jal fib 20 | addu $t9, $0, $v0 21 | ori $t0, $0, 0x2333 22 | ori $t1, $0, 0x2333 23 | beq $t0, $t1, end 24 | 25 | fib: 26 | push($ra) 27 | beq $a0, $s0, return 28 | beq $a0, $s1, return 29 | push($a0) 30 | subu $a0, $a0, $s1 31 | jal fib 32 | pop($a0) 33 | addu $t0, $0, $v0 34 | push($t0) 35 | push($a0) 36 | subu $a0, $a0,$s2 37 | jal fib 38 | pop($a0) 39 | pop($t0) 40 | addu $v0, $t0,$v0 41 | pop($ra) 42 | jr $ra 43 | return: 44 | ori $v0, $0, 1 45 | pop($ra) 46 | jr $ra 47 | end: 48 | nop -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint24.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,123 2 | addu $4,$0,$3 3 | beq $4,$3,next1 4 | nop 5 | ori $9,$0,99 6 | next1: 7 | addu $5,$4,$0 8 | ori $6,$0,123 9 | beq $6,$5,next2 10 | nop 11 | ori $9,$0,88 12 | next2: 13 | sw $6,0($0) 14 | lw $7,0($0) 15 | lw $8,0($0) 16 | beq $7,$8,next3 17 | nop 18 | ori $9,$0,77 19 | next3: 20 | ori $9,$0,100 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint25.asm: -------------------------------------------------------------------------------- 1 | ori $8,$0,123 2 | sw $8,0($0) 3 | lw $9,0($0) 4 | addu $10,$9,$9 5 | lw $10,0($0) 6 | ori $11,$10,0 7 | sw $11,1024($0) -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint26.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,12 2 | sw $3,0($0) 3 | lw $4,0($0) 4 | sw $3,0($4) 5 | lw $5,0($0) 6 | lw $6,0($4) -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint27.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,16 2 | sw $3,0($0) 3 | lw $4,0($0) 4 | sw $4,4($0) 5 | lw $6,4($0) 6 | sw $6,8($0) 7 | lw $7,8($0) 8 | sw $7,12($0) 9 | lw $8,12($0) 10 | sw $8,0($8) 11 | lw $9,0($8) 12 | sw $9,4($9) 13 | lw $10,4($9) 14 | addu $11,$10,$10 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint28.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,0x00003010 #16 2 | jr $3 #4 3 | nop#8 4 | ori $4,$0,123 #12 5 | ori $5,$0,0x00003010 #16 6 | ori $6,$0,24#24 7 | addu $7,$5,$6 #24 8 | jr $7 #28 9 | nop 10 | ori $1,$0,123 11 | add $9,$7,$7 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint29.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint29.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint3.asm: -------------------------------------------------------------------------------- 1 | lui $3, 203 2 | lui $4, 203 3 | beq $3,$4 next 4 | ori $5,123 5 | ori $6,123 6 | 7 | next: 8 | jal end 9 | ori $8,$31,0 10 | ori $9,$31,0 11 | end: 12 | ori $10,$31,0 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint4.asm: -------------------------------------------------------------------------------- 1 | ori $2, 10 2 | ori $3, 10 3 | addu $1, $2, $3 4 | subu $4, $1, $2 5 | addu $1, $2, $3 6 | ori $4, 1 7 | addu $1, $2, $3 8 | lui $1, 10 9 | addu $1, $2, $3 10 | ori $2, 10 11 | sw $1, 0($0) 12 | addu $1, $2, $3 13 | sw $1, 4($0) 14 | addu $1, $2, $3 15 | addu $4, $2, $3 16 | beq $1, $4 QAQ 17 | ori $t0, 10 18 | ori $t1, 10 19 | QAQ: 20 | ori $t2, 10 21 | addu $1, $2, $3 22 | 23 | ori $2, 10 24 | ori $0, 10 25 | addu $1, $0, $2 26 | addu $0, $2, $1 27 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint5.asm: -------------------------------------------------------------------------------- 1 | ori $28,$0,123 2 | begin: 3 | ori $21,$0,324 4 | ori $22,$0,643 5 | ori $23,$0,235 6 | j begin 7 | ori $29,$0,134 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint6.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,123 2 | ori $4,$0,123 3 | beq $4,$3,nn 4 | addu $9,$3,$3 5 | addu $10,$5,$5 6 | nn: 7 | jal next 8 | ori $5, $0,345 9 | ori $6,$0,789 10 | next: 11 | ori $4,$0,1234567 -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint7.asm: -------------------------------------------------------------------------------- 1 | .data 2 | arr: .space 32 3 | .text 4 | ori $s0,10 5 | ori $s7,$s0,10 6 | loop: 7 | beq $t0,$s0,loopout 8 | lw $s1,arr($t1) 9 | addu $t1,$t1,4 10 | lw $s2,arr($t1) 11 | addu $s3,$s1,$s7 12 | addu $s2,$s2,$s3 13 | sw $s2,arr($t1) 14 | addu $t0,$t0,1 15 | jal loop 16 | nop 17 | loopout: 18 | -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint8.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_2/testpoint8.asm -------------------------------------------------------------------------------- /TestData/My_test/test_2/testpoint9.asm: -------------------------------------------------------------------------------- 1 | lui $5, 233 2 | lui $6, 233 3 | lui $5, 122 4 | addu $6,$5,$5 5 | subu $6,$5,$5 6 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm.rar: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_asm.rar -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint1.asm: -------------------------------------------------------------------------------- 1 | ori $t0, $t0, 10 2 | lui $t1, 6 3 | addu $t2, $t0, $t1 4 | nop 5 | subu $t3, $t1, $t2 6 | subu $t3, $t1, $t0 7 | 8 | 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint10.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | 4 | .text 5 | ori $t3, $0, 1234 6 | beq $t3, $t3, loop 7 | nop 8 | ori $t0, $0, 1 9 | loop: 10 | ori $t0, $0, 5 11 | ori $t2, $t2, 0123 12 | ori $t4, $t4, 0123 13 | beq $t2, $t4, loop2 14 | nop 15 | ori $t0, $0, 1 16 | loop2: 17 | ori $t0, $0, 6 18 | ori $t1, $t1, 0123 19 | ori $t5, $t5, 0123 20 | beq $t5, $t1, loop3 21 | nop 22 | ori $t0, $0, 1 23 | loop3: 24 | ori $t0, $0, 7 25 | ori $t6, 2333 26 | ori $t7, 2333 27 | nop 28 | beq $t6, $t7, loop4 29 | nop 30 | ori $t0, $0, 1 31 | loop4: 32 | ori $t0, $0, 8 33 | ori $t1, 244 34 | ori $t2, 244 35 | nop 36 | beq $t2, $t1, loop5 37 | nop 38 | ori $t0, $0, 1 39 | loop5: 40 | ori $t0, $0, 9 41 | ori $t3, $0, 255 42 | ori $t4, $0, 255 43 | nop 44 | nop 45 | beq $t3, $t4, loop6 46 | nop 47 | ori $t0, $0, 1 48 | loop6: 49 | ori $t0, $0, 10 50 | ori $t5, $0, 255 51 | ori $t6, $0, 255 52 | nop 53 | nop 54 | beq $t6, $t5, loop7 55 | nop 56 | ori $t0, $0, 1 57 | loop7: 58 | ori $t1, 1000 59 | nop 60 | nop 61 | nop 62 | beq $t1, $t1, end 63 | nop 64 | ori $t0, $0, 1 65 | end: 66 | ori $t0, 11 67 | 68 | 69 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint11.asm: -------------------------------------------------------------------------------- 1 | ori $s0, 4 2 | jal tag 3 | addu $t0, $ra, $ra 4 | ori $t0, $0, 1 5 | tag: 6 | addu $t1, $ra, $s0 7 | addu $t2, $ra, $s0 8 | addu $t3, $ra, $s0 9 | jal tag2 10 | addu $t4, $s0, $ra 11 | ori $t0, $0, 1 12 | tag2: 13 | addu $t4, $s0, $ra 14 | addu $t5, $s0, $ra 15 | addu $t6, $s0, $ra 16 | addu $t7, $s0, $ra 17 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint12.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums:.space 4096 3 | 4 | .text 5 | ori $t0, $0, 4 6 | lui $t1, 15 7 | sw $t1, nums($t0) 8 | lw $t2, nums($t0) 9 | lw $t3, nums($t0) 10 | lw $t4, nums($t0) 11 | lw $t5, nums($t0) 12 | 13 | ori $t0, $0, 4 14 | ori $t1, $0, 8 15 | ori $t2, $0, 12 16 | ori $t3, $0, 16 17 | lui $s1, 17 18 | lui $s2, 18 19 | lui $s3, 19 20 | lui $s4, 20 21 | lui $s5, 21 22 | 23 | sw $s1, nums 24 | lw $s2, nums 25 | sw $s2, nums($t0) 26 | sw $s2, nums($t1) 27 | sw $s2, nums($t2) 28 | sw $s2, nums($t3) 29 | 30 | sw $t0, nums 31 | lw $t1, nums 32 | sw $s1, nums($t1) 33 | 34 | sw $t2, nums 35 | lw $t1, nums 36 | nop 37 | sw $s2, nums($t1) 38 | 39 | sw $t2, nums 40 | lw $t1, nums 41 | nop 42 | nop 43 | sw $s2, nums($t1) 44 | 45 | sw $t3, nums 46 | lw $t1, nums 47 | nop 48 | nop 49 | nop 50 | sw $s2, nums($t1) 51 | 52 | 53 | 54 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint13.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | 4 | .text 5 | ori $t2, $0 15 6 | sw $t2, nums 7 | lw $t1, nums 8 | beq $t2, $t1, tag 9 | nop 10 | ori $t0, $0, 1 11 | tag: 12 | ori $t0, $0, 17 13 | 14 | ori $t5, $0, 19 15 | sw $t5, nums 16 | lw $t6, nums 17 | beq $t6, $t5, tag2 18 | nop 19 | ori $t0, $0, 1 20 | tag2: 21 | ori $t0, $0, 18 22 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint14.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | .text 4 | ori $s1, $s1, 0x3000 5 | ori $s0, $0, 15 6 | sw $s0, nums+0x30 7 | ori $s0, $0, 16 8 | sw $s0, nums+0x40 9 | ori $s0, $0, 17 10 | sw $s0, nums+0x54 11 | jal loop 12 | subu $t1, $ra, $s1 13 | ori $t0, $0, 1 14 | loop: 15 | lw $s3, nums($t1) 16 | jal loop2 17 | subu $t1, $ra, $s1 18 | ori $t0, $0, 1 19 | loop2: 20 | nop 21 | lw $s4, nums($t1) 22 | jal loop3 23 | subu $t1, $ra, $s1 24 | ori $t0, $0, 1 25 | loop3: 26 | nop 27 | nop 28 | lw $s5, nums($t1) 29 | 30 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint15.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | .text 4 | ori $t0, $0, 12 5 | ori $t1, $0, 15 6 | sw $t1, nums($t0) 7 | lw $t2, nums($t0) 8 | beq $t1, $t2, tag 9 | nop 10 | ori $t0, 1 11 | tag: 12 | ori $t0, $0, 16 13 | ori $t1, $0, 19 14 | sw $t1, nums($t0) 15 | lw $t2, nums($t0) 16 | beq $t2, $t1, tag2 17 | nop 18 | ori $t0, 1 19 | tag2: 20 | ori $t0, $0, 20 21 | ori $t1, $0, 21 22 | sw $t1, nums($t0) 23 | lw $t2, nums($t0) 24 | nop 25 | beq $t2, $t1, tag3 26 | nop 27 | ori $t0, 1 28 | tag3: 29 | ori $t0, $0, 24 30 | ori $t1, $0, 22 31 | sw $t1, nums($t0) 32 | lw $t2, nums($t0) 33 | nop 34 | beq $t1, $t2, tag4 35 | nop 36 | ori $t0, 1 37 | tag4: 38 | ori $t0, $0, 28 39 | ori $t1, $0, 23 40 | sw $t1, nums($t0) 41 | lw $t2, nums($t0) 42 | nop 43 | nop 44 | beq $t1, $t2, tag5 45 | nop 46 | ori $t0, 1 47 | tag5: 48 | ori $t0, $0, 28 49 | ori $t1, $0, 23 50 | sw $t1, nums($t0) 51 | lw $t2, nums($t0) 52 | nop 53 | nop 54 | beq $t2, $t1, tag6 55 | nop 56 | ori $t0, 1 57 | tag6: 58 | ori $t0, $0, 28 59 | ori $t1, $0, 23 60 | sw $t1, nums($t0) 61 | lw $t2, nums($t0) 62 | nop 63 | nop 64 | beq $t0, $t0, tag7 65 | nop 66 | ori $t0, 1 67 | tag7: 68 | ori $t0, $0, 2 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint2.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | .text 4 | ori $s3, 0x3000 5 | ori $t3, $0, 16 6 | ori $t2, $0, 12 7 | ori $t1, $0, 8 8 | ori $t0, $0, 4 9 | jal loop 10 | sw $ra, nums($t0) 11 | ori $t0, $0, 1 12 | loop: 13 | jal loop2 14 | nop 15 | loop2: 16 | sw $ra, nums($t1) 17 | jal loop3 18 | nop 19 | loop3: 20 | nop 21 | sw $ra, nums($t2) 22 | jal loop4 23 | nop 24 | loop4: 25 | nop 26 | nop 27 | sw $ra, nums($t3) 28 | jal loop5 29 | subu $t0, $ra, $s3 30 | loop5: 31 | sw $t3, nums($t0) 32 | jal loop6 33 | subu $t0, $ra, $s3 34 | loop6: 35 | nop 36 | sw $t3, nums($t0) 37 | jal loop7 38 | subu $t0, $ra, $s3 39 | loop7: 40 | nop 41 | nop 42 | sw $t3, nums($t0) 43 | 44 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint3.asm: -------------------------------------------------------------------------------- 1 | jal loop 2 | ori $t0, $ra, 0 3 | loop: 4 | beq $t0, $ra, loop2 5 | nop 6 | loop2: 7 | jal loop3 8 | ori $t1, $ra, 0 9 | loop3: 10 | beq $ra, $t1, loop4 11 | nop 12 | loop4: 13 | jal loop5 14 | ori $t2, $ra, 0 15 | loop5: 16 | nop 17 | beq $ra, $t2, loop6 18 | nop 19 | loop6: 20 | jal loop7 21 | ori $t3, $ra, 0 22 | loop7: 23 | nop 24 | beq $t3, $ra, loop8 25 | nop 26 | loop8: 27 | jal loop9 28 | ori $t4, $ra, 0 29 | loop9: 30 | nop 31 | beq $ra, $t4, loop10 32 | nop 33 | loop10: 34 | jal loop11 35 | ori $t5, $ra, 0 36 | loop11: 37 | nop 38 | beq $t5, $ra, loop12 39 | nop 40 | loop12: 41 | jal loop13 42 | ori $t6, $ra, 0 43 | loop13: 44 | nop 45 | nop 46 | beq $t6, $ra, loop14 47 | nop 48 | loop14: 49 | jal loop15 50 | ori $t7, $ra, 0 51 | loop15: 52 | nop 53 | nop 54 | beq $ra, $t7, loop16 55 | nop 56 | loop16: 57 | ori $t0, $0, 12 58 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint4.asm: -------------------------------------------------------------------------------- 1 | ori $t0, $0, 0x00003010 2 | jr $t0 3 | nop 4 | ori $t0, $0, 1 5 | ori $t0, $0, 2 6 | ori $t0, $0, 0x00003028 7 | nop 8 | jr $t0 9 | nop 10 | ori $t0, $0, 1 11 | ori $t0, $0, 3 12 | ori $t0, $0, 0x00003044 13 | nop 14 | nop 15 | jr $t0 16 | nop 17 | ori $t0, $0, 1 18 | ori $t0, $0, 4 19 | ori $t0, $0, 0x00003064 20 | nop 21 | nop 22 | nop 23 | jr $t0 24 | nop 25 | ori $0, $0, 1 26 | ori $t0, $0, 5 27 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint5.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | 4 | .text 5 | ori $t0, $0, 0x3094 6 | ori $t1, $0, 0x30a4 7 | ori $t2, $0, 0x30b4 8 | ori $t3, $0, 0x30c4 9 | ori $t4, $0, 4 10 | ori $t5, $0, 8 11 | ori $t6, $0, 0xc 12 | sw $t0, nums 13 | sw $t1, nums+4 14 | sw $t2, nums+8 15 | sw $t3, nums+12 16 | sw $t3, nums+16 17 | sw $t4, nums+20 18 | 19 | lw $s0, nums 20 | jr $s0 21 | nop 22 | tag: 23 | lw $s1, nums($t4) 24 | nop 25 | jr $s1 26 | nop 27 | tag2: 28 | lw $s2, nums($t5) 29 | nop 30 | nop 31 | jr $s2 32 | nop 33 | tag3: 34 | lw $s3, nums($t6) 35 | nop 36 | nop 37 | nop 38 | jr $s3 39 | nop 40 | 41 | ori $t9, $0, 1 42 | ori $t9, $0, 2 43 | j tag 44 | nop 45 | ori $t9, $0, 1 46 | ori $t9, $0, 3 47 | j tag2 48 | nop 49 | ori $t9, $0, 1 50 | ori $t9, $0, 4 51 | j tag3 52 | nop 53 | ori $t9, $0, 1 54 | ori $t9, $0, 5 55 | end: 56 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint6.asm: -------------------------------------------------------------------------------- 1 | jal loop 2 | nop 3 | jal loop2 4 | nop 5 | jal loop3 6 | nop 7 | jal loop4 8 | nop 9 | ori $t0, $0, 100 10 | loop: 11 | j end 12 | nop 13 | loop2: 14 | nop 15 | jr $ra 16 | nop 17 | loop3: 18 | nop 19 | nop 20 | jr $ra 21 | nop 22 | loop4: 23 | nop 24 | nop 25 | nop 26 | jr $ra 27 | nop 28 | end: 29 | nop 30 | 31 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint7.asm: -------------------------------------------------------------------------------- 1 | ori $t0, $0, 12 2 | ori $t1, $0, 12 3 | bne $t0, $t1, loop 4 | nop 5 | ori $s0, $0, 1 6 | loop: 7 | ori $s0, $0, 2 8 | ori $t2, $0, 11 9 | ori $t3, $0, 11 10 | bne $t3, $t2, loop2 11 | nop 12 | ori $s0, $0, 1 13 | loop2: 14 | ori $s0,$0, 2 15 | ori $t4, $0, 22 16 | ori $t5, $0, 22 17 | nop 18 | bne $t4, $t5, loop3 19 | nop 20 | ori $s0, $0, 1 21 | loop3: 22 | ori $s0, $0, 3 23 | ori $t6, $0, 12 24 | ori $t7, $0, 12 25 | nop 26 | bne $t7, $t6, loop4 27 | nop 28 | ori $s0, $0, 1 29 | loop4: 30 | ori $s0, $0, 4 31 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint8.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums: .space 4096 3 | .text 4 | ori $t0, $t0, 100 5 | sw $t0, nums($t0) 6 | ori $t1, $t1, 12 7 | ori $t3, $t3, 16 8 | sw $t1, nums($t1) 9 | nop 10 | sw $t3, nums($t3) 11 | ori $t4, $t4, 20 12 | nop 13 | nop 14 | sw $t3, nums($t4) 15 | sw $t4, nums($t4) 16 | 17 | 18 | 19 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/16LZHtest-AC/testpoint9.asm: -------------------------------------------------------------------------------- 1 | .data 2 | nums:.space 4096 3 | .text 4 | ori $s0, $s0, 4 5 | ori $s5, 19 6 | sw $s5, nums($s0) 7 | ori $s2, $s2, 8 8 | ori $s5, 17 9 | sw $s5, nums($s2) 10 | ori $s3, $s3, 4092 11 | lui $s5, 13 12 | sw $s5,nums($s3) 13 | ori $s4, $s4, 20 14 | sw $s4,nums($s4) 15 | ori $t0, $t0, 4 16 | lw $t5, nums($t0) 17 | ori $t2, $t2, 8 18 | nop 19 | lw $t6, nums($t2) 20 | ori $t3, $t3, 4092 21 | nop 22 | nop 23 | lw $t7, nums($t3) 24 | ori $t4, $t4, 20 25 | nop 26 | nop 27 | nop 28 | lw $t8, nums($t4) 29 | ori $t6, $0, 24 30 | lw $t9, nums($t6) 31 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Forward_rs.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | lui $t4 0xaf78 4 | tiao: 5 | ori $t2 $0 0x3018 6 | addu $t5 $t1 $t3 7 | beq $t4 $t5 end 8 | lui $t3 0x49bf 9 | j tiao 10 | addu $t4 $t1 $t3 11 | addu $t4 $t4 $t3 12 | end: 13 | subu $t5 $t1 $t2 14 | #addu $t4 $t4 $t3 15 | ori $t3 $0 0x3044 16 | func: 17 | beq $t3 $31 ha #jal + delay + beq 18 | addu $t4 $t4 $t2 19 | ori $t5 $t3 0x6349 20 | jal func 21 | addu $t5 $t2 $t3 22 | subu $t1 $t2 $t5 23 | ha: 24 | subu $t4 $t4 $0 25 | addu $t5 $0 $t4 26 | beq $t4 $t5 end6 #cal + x + beq 27 | subu $t4 $t5 $t3 28 | addu $t6 $t2 $t3 29 | j ha 30 | end6: 31 | ori $t3 $t4 0x26cb 32 | ori $1 $0 48 33 | addu $ra $ra, $1 34 | lui $2 0x41ba 35 | jr $ra #cal + x + jr 36 | addu $1 $0 $t3 37 | subu $t4 $t4 $t1 38 | ori $s0 $0 24 39 | addu $ra $ra $s0 40 | stein:jr $ra 41 | addu $t4 $t5 $t1 42 | subu $t2 $t4 $t3 43 | ori $1 $0 4 44 | jal stein #jal + change$ra + jr 45 | addu $ra $ra $1 46 | lui $s1 0x6249 47 | subu $s1 $s1 $31 48 | jal stein 49 | subu $t0 $t3 $t5 50 | 51 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall1.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | ori $t2 $0 0x3000 4 | lui $t3 0x49bf 5 | addu $t5 $t1 $t3 6 | #rs Tuse=0, Tnew_E=`ALU 7 | addu $t4 $t1 $t3 8 | beq $t4 $t5 end #cal-beq 9 | subu $t6 $t2 $t3 10 | func: 11 | ori $1 $0 4 12 | subu $31 $31 $1 13 | jr $31 #cal-jr 14 | sw $t4 0($0) 15 | jr $31 16 | end: subu $t6 $t3 $t1 17 | jal func 18 | lui $s0 0x462b 19 | ori $s1 $0 0x336c 20 | subu $s2 $s0 $s1 21 | nop -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall2.asm: -------------------------------------------------------------------------------- 1 | ori $t2 $0 0x3000 2 | lui $t3 0x49bf 3 | addu $t5 $t1 $t3 4 | sw $t5 0($0) 5 | ori $t1 $0 0xabfe 6 | lw $t4 0($0) 7 | addu $t1 $t4 $t1 #lw-cal 8 | ori $t0 $0 0x0008 9 | 10 | 11 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall3.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | ori $t2 $0 0x3000 4 | lui $t3 0x49bf 5 | addu $t5 $t1 $t3 6 | addu $t4 $t1 $t3 7 | beq $t5 $t4 end #cal-beq 8 | subu $t6 $t2 $t3 9 | ori $1 $0 4 10 | subu $31 $31 $1 11 | end: subu $t6 $t3 $t1 12 | sw $t6 0($0) 13 | lw $s0 0($0) 14 | end1:lw $s1 0($0) 15 | beq $s0 $s1 end1 16 | ori $s0 $s1 0x619f 17 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall4.asm: -------------------------------------------------------------------------------- 1 | ori $t2 $0 0x3000 2 | lui $t3 0x49bf 3 | addu $t5 $t1 $t3 4 | sw $t5 0($0) 5 | ori $t1 $0 0xabfe 6 | lw $t4 0($0) 7 | addu $t1 $t1 $t4 #lw-cal 8 | ori $t0 $0 0x0008 9 | sw $t0 4($t0) 10 | lw $t0 4($t0) #lw sw 11 | sw $t1 8($t0) 12 | 13 | 14 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall5.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | ori $t2 $0 0x3000 4 | lui $t3 0x49bf 5 | addu $t5 $t1 $t3 6 | sw $t5 0($0) 7 | lw $t4 0($0) 8 | addu $t1 $t1 $t3 9 | beq $t4 $t5 end #lw-cal-beq 10 | func: 11 | sw $31 4($0) 12 | subu $31 $31 4 13 | beq $t4 $t5 end 14 | lui $t4 0x83ba 15 | nop 16 | lw $31 4($0) 17 | addu $t1 $t1 $t2 18 | jr $31 #lw-cal-jr 19 | addu $t4 $t0 $t2 20 | end:subu $t4 $t3 $t1 21 | jal func 22 | addu $t6 $t4 $t5 23 | ori $s0 $0 0xfa6b 24 | addu $s1 $t4 $s0 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/Stall-AC/stall6.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | ori $t2 $0 0x3000 4 | lui $t3 0x49bf 5 | addu $t5 $t1 $t3 6 | sw $t5 0($0) 7 | #rs Tuse=0, Tnew_E=`DM 8 | lw $t4 0($0) #sw-lw 9 | beq $t4 $t5 end #lw-beq 10 | func: 11 | sw $31 4($0) 12 | subu $31 $31 4 13 | beq $t4 $t5 end 14 | lui $t4 0x83ba 15 | nop 16 | lw $31 4($0) #lw-jr 17 | jr $31 18 | addu $t4 $t0 $t2 19 | end:subu $t4 $t3 $t1 20 | jal func 21 | addu $t6 $t4 $t5 22 | ori $s0 $0 0xfa6b 23 | addu $s1 $t4 $s0 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/swl&swr&lwl&lwr.asm: -------------------------------------------------------------------------------- 1 | li $a0, 999997671 2 | sw $a0, 0($0) 3 | addu $t0 $0 0xffffffff 4 | move $t1 $t0 5 | move $t2 $t0 6 | sw $1 4($0) 7 | sw $1 8($0) 8 | sw $1 12($0) 9 | sw $1 16($0) 10 | lwl $t0 0($0) 11 | lwl $t1 1($0) 12 | lwl $t2 2($0) 13 | lwl $t3 3($0) 14 | swl $t3 4($0) 15 | swl $t3 9($0) 16 | swl $t3 14($0) 17 | swl $t3 19($0) 18 | lwr $t4 0($0) 19 | lwr $t5 1($0) 20 | lwr $t6 2($0) 21 | lwr $t7 3($0) 22 | swr $t3 20($0) 23 | swr $t3 25($0) 24 | swr $t3 30($0) 25 | swr $t3 35($0) 26 | nop -------------------------------------------------------------------------------- /TestData/My_test/test_asm/1/说明.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_asm/1/说明.txt -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint1.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | 9 | beq $t0, $s0, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $t1, 0x1234 17 | addu $t2, $t1, $zero 18 | 19 | beq $t1, $t2, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint2.asm: -------------------------------------------------------------------------------- 1 | .data 2 | array: .space 120 # 4 * 30 3 | 4 | .text 5 | j main # jump to main 6 | ori $s0, $zero, 29 # n = 29 7 | 8 | init: 9 | # ori $s0, $zero, 29 # n = 29 10 | li $s1, 0x3badb8 # a = 3911096 11 | sw $s1, array # store a to array[0] 12 | li $s2, 0xaedb5 # b = 716213 13 | sw $s2, array+4 # store b to array[1] 14 | 15 | # ori $t0, $zero, 1 # i = 1 16 | ori $t1, $zero, 1 # constant 1 17 | # ori $t4, $zero, 4 # constant 4 18 | 19 | jr $ra # return to main 20 | ori $t4, $zero, 4 # constant 4 21 | 22 | main: 23 | jal init # jump to init (check $ra cover) 24 | ori $t0, $zero, 1 # i = 1 25 | 26 | for_begin: 27 | beq $t0, $s0, for_end # end for loop if (i == n) 28 | nop 29 | 30 | addu $t2, $t0, $t0 # offset = 2 * i 31 | addu $t2, $t2, $t2 # offset = 4 * i 32 | lw $s2, array($t2) # b = array[i] 33 | 34 | ori $s3, $s1, 0x1234 # c = a | 4660 35 | subu $s3, $s3, $s2 # c = c - b 36 | 37 | addu $t2, $t2, $t4 # offset += 4 38 | sw $s3, array($t2) # store c to array[i + 1] 39 | 40 | move $s1, $s2 # a = b 41 | 42 | # addu $t0, $t0, $t1 # i = i + 1 43 | beq $zero, $zero, for_begin # jump to for_begin 44 | addu $t0, $t0, $t1 # i = i + 1 45 | for_end: 46 | 47 | jal test_reg 48 | nop 49 | 50 | terminate: 51 | beq $zero, $zero, terminate # terminate 52 | nop 53 | 54 | test_reg: 55 | li $a0, 0x12345678 # test $a0 56 | # ori $v0, $zero, 0xcba9 # test $v0 57 | ori $zero, $zero, 0xcdef # test read only 58 | jr $ra 59 | ori $v0, $zero, 0xcba9 # test $v0 60 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint3.asm: -------------------------------------------------------------------------------- 1 | ori $zero, $zero, 1 2 | addu $t1, $zero, $zero 3 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint4.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | ori $s1, $zero, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint5.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | ori $s1, $s0, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint6.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 8 3 | 4 | .text 5 | ori $t4, $zero, 3 6 | sw $t4, 0 7 | ori $t5, $zero, 2 8 | sw $t5, 4 9 | lw $t2, 4 10 | lw $t1, 0 11 | addu $t3, $t1, $t2 12 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/MondayCha/testpoint7.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | 9 | beq $zero, $zero, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $zero, 0x1234 17 | addu $zero, $zero, $zero 18 | 19 | beq $zero, $zero, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/aptx-AC/testpoint1.asm: -------------------------------------------------------------------------------- 1 | addu $a0,$0,$0 2 | ori $t1,$0,1 3 | ori $t2,$0,2 4 | ori $t3,$0,3 5 | addu $t4,$t1,$t2 6 | subu $t5,$t1,$t2 7 | jal out 8 | addu $t3,$t4,$0 9 | 10 | out: 11 | ori $a0,$0,11 12 | beq $a0,$a1,end 13 | lui $a2,111 14 | jr $ra 15 | ori $a1,$0,11 16 | end: 17 | nop -------------------------------------------------------------------------------- /TestData/My_test/test_asm/aptx-AC/testpoint2.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,111 2 | jal end 3 | nop 4 | nop 5 | nop 6 | j out 7 | nop 8 | end: 9 | jr $ra 10 | nop 11 | out: 12 | ori $a1,$0,10 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/aptx-AC/testpoint3.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,1999 2 | ori $a1,$a0,111 3 | lui $a2,12345 4 | lui $a3,0xffff 5 | lui $t0,0xffff 6 | beq $a3,$t0,eee 7 | addu $s7,$0,$a0 8 | nop 9 | ori $a3,$a3,0xffff 10 | addu $s0,$a0,$a1 11 | addu $s1,$a3,$a3 12 | addu $s2,$a3,$s0 13 | beq $s2,$s3,eee 14 | subu $s0,$a0,$s2 15 | subu $s1,$a3,$a3 16 | eee: 17 | subu $s2,$a3,$a0 18 | subu $s3,$s2,$s1 19 | ori $t0,$0,0x0000 20 | sw $a0,0($t0) 21 | nop 22 | sw $a1,4($t0) 23 | sw $s0,8($t0) 24 | sw $s1,12($t0) 25 | sw $s2,16($t0) 26 | sw $s5,20($t0) 27 | lw $t1,20($t0) 28 | lw $t7,0($t0) 29 | lw $t6,20($t0) 30 | sw $t6,24($t0) 31 | lw $t5,12($t0) 32 | jal end 33 | ori $t0,$t0,1 34 | ori $t1,$t1,1 35 | ori $t2,$t2,2 36 | beq $t0,$t2,eee 37 | lui $t3,1111 38 | jal out 39 | end: 40 | addu $t0,$t0,$t7 41 | jr $ra 42 | out: 43 | addu $t0,$t0,$t3 44 | ori $t2,$t0,0 45 | beq $t0,$t2,qqq 46 | lui $v0,10 47 | qqq: 48 | lui $v0,11 49 | j www 50 | nop 51 | www: 52 | lui $ra,100 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/aptx-AC/testpoint4.asm: -------------------------------------------------------------------------------- 1 | ori $a1,$0,111 2 | ori $a2,$0,112 3 | beq $a1,$a2,end 4 | ori $a1,$a1,111 5 | beq $a1,$a1,out 6 | nop 7 | end: 8 | nop 9 | out: 10 | addu $a0,$a0,$a1 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/aptx-AC/testpoint5.asm: -------------------------------------------------------------------------------- 1 | ori $a1,$0,111 2 | ori $a2,$a0,112 3 | addu $0,$a1,$a2 4 | subu $a2,$a1,$0 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint1.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | 9 | beq $t0, $s0, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $t1, 0x1234 17 | addu $t2, $t1, $zero 18 | 19 | beq $t1, $t2, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint2.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | 9 | beq $zero, $zero, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $zero, 0x1234 17 | addu $zero, $zero, $zero 18 | 19 | beq $zero, $zero, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint3.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 8 3 | 4 | .text 5 | ori $t4, $zero, 3 6 | sw $t4, 0 7 | ori $t5, $zero, 2 8 | sw $t5, 4 9 | lw $t2, 4 10 | lw $t1, 0 11 | addu $t3, $t1, $t2 12 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint4.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | ori $s1, $s0, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint5.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | ori $s1, $zero, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint6.asm: -------------------------------------------------------------------------------- 1 | .data 2 | array: .space 120 # 4 * 30 3 | 4 | .text 5 | j main # jump to main 6 | ori $s0, $zero, 29 # n = 29 7 | 8 | init: 9 | # ori $s0, $zero, 29 # n = 29 10 | li $s1, 0x3badb8 # a = 3911096 11 | sw $s1, array # store a to array[0] 12 | li $s2, 0xaedb5 # b = 716213 13 | sw $s2, array+4 # store b to array[1] 14 | 15 | # ori $t0, $zero, 1 # i = 1 16 | ori $t1, $zero, 1 # constant 1 17 | # ori $t4, $zero, 4 # constant 4 18 | 19 | jr $ra # return to main 20 | ori $t4, $zero, 4 # constant 4 21 | 22 | main: 23 | jal init # jump to init (check $ra cover) 24 | ori $t0, $zero, 1 # i = 1 25 | 26 | for_begin: 27 | beq $t0, $s0, for_end # end for loop if (i == n) 28 | nop 29 | 30 | addu $t2, $t0, $t0 # offset = 2 * i 31 | addu $t2, $t2, $t2 # offset = 4 * i 32 | lw $s2, array($t2) # b = array[i] 33 | 34 | ori $s3, $s1, 0x1234 # c = a | 4660 35 | subu $s3, $s3, $s2 # c = c - b 36 | 37 | addu $t2, $t2, $t4 # offset += 4 38 | sw $s3, array($t2) # store c to array[i + 1] 39 | 40 | move $s1, $s2 # a = b 41 | 42 | # addu $t0, $t0, $t1 # i = i + 1 43 | beq $zero, $zero, for_begin # jump to for_begin 44 | addu $t0, $t0, $t1 # i = i + 1 45 | for_end: 46 | 47 | jal test_reg 48 | nop 49 | 50 | terminate: 51 | beq $zero, $zero, terminate # terminate 52 | nop 53 | 54 | test_reg: 55 | li $a0, 0x12345678 # test $a0 56 | # ori $v0, $zero, 0xcba9 # test $v0 57 | ori $zero, $zero, 0xcdef # test read only 58 | jr $ra 59 | ori $v0, $zero, 0xcba9 # test $v0 60 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/cjb/testpoint7.asm: -------------------------------------------------------------------------------- 1 | ori $zero, $zero, 1 2 | addu $t1, $zero, $zero 3 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint1.asm: -------------------------------------------------------------------------------- 1 | ori $gp, $zero, 0 2 | ori $sp, $zero, 0 3 | ori $at, $a3, 0x1010 4 | lw $t2, ($zero) 5 | sw $at, ($zero) 6 | lui $v0, 0x8723 7 | ori $v1, $zero, 0x7856 8 | lui $a0, 0x85ff 9 | ori $a1, $zero, 1 10 | lui $a2, 0xffff 11 | ori $a3, $a3, 0xffff 12 | addu $at, $at, $v0 13 | addu $t1, $at, $v1 14 | subu $t0, $at, $v0 15 | subu $zero, $a3, $zero 16 | nop 17 | nop 18 | nop 19 | nop 20 | nop 21 | #beq $gp, $s1, 0x3060 22 | nop 23 | #j 0x30b0 24 | beq1: 25 | #beq $at, $v0, 0x30b0 26 | nop 27 | ori $v0, $zero, 0xc 28 | nop 29 | nop 30 | nop 31 | #jal 0x3088 32 | sw $at, ($v0) 33 | #j 0x30b0 34 | addu $at, $at, $v0 35 | addu $at, $at, $v0 36 | addu $at, $at, $v0 37 | addu $at, $at, $v0 38 | sw $ra, ($v0) 39 | lw $at, ($v0) 40 | nop 41 | nop 42 | nop 43 | #jr $at 44 | sw $ra, ($v0) 45 | #b 0x30b0 46 | nop 47 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint11.asm: -------------------------------------------------------------------------------- 1 | .data 2 | array: .space 120 # 4 * 30 3 | 4 | .text 5 | j main # jump to main 6 | ori $s0, $zero, 29 # n = 29 7 | 8 | init: 9 | # ori $s0, $zero, 29 # n = 29 10 | li $s1, 0x3badb8 # a = 3911096 11 | sw $s1, array # store a to array[0] 12 | li $s2, 0xaedb5 # b = 716213 13 | sw $s2, array+4 # store b to array[1] 14 | 15 | # ori $t0, $zero, 1 # i = 1 16 | ori $t1, $zero, 1 # constant 1 17 | # ori $t4, $zero, 4 # constant 4 18 | 19 | jr $ra # return to main 20 | ori $t4, $zero, 4 # constant 4 21 | 22 | main: 23 | jal init # jump to init (check $ra cover) 24 | ori $t0, $zero, 1 # i = 1 25 | 26 | for_begin: 27 | beq $t0, $s0, for_end # end for loop if (i == n) 28 | nop 29 | 30 | addu $t2, $t0, $t0 # offset = 2 * i 31 | addu $t2, $t2, $t2 # offset = 4 * i 32 | lw $s2, array($t2) # b = array[i] 33 | 34 | ori $s3, $s1, 0x1234 # c = a | 4660 35 | subu $s3, $s3, $s2 # c = c - b 36 | 37 | addu $t2, $t2, $t4 # offset += 4 38 | sw $s3, array($t2) # store c to array[i + 1] 39 | 40 | move $s1, $s2 # a = b 41 | 42 | # addu $t0, $t0, $t1 # i = i + 1 43 | beq $zero, $zero, for_begin # jump to for_begin 44 | addu $t0, $t0, $t1 # i = i + 1 45 | for_end: 46 | 47 | jal test_reg 48 | nop 49 | 50 | terminate: 51 | beq $zero, $zero, terminate # terminate 52 | nop 53 | 54 | test_reg: 55 | li $a0, 0x12345678 # test $a0 56 | # ori $v0, $zero, 0xcba9 # test $v0 57 | ori $zero, $zero, 0xcdef # test read only 58 | jr $ra 59 | ori $v0, $zero, 0xcba9 # test $v0 60 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint13.asm: -------------------------------------------------------------------------------- 1 | ori $zero, $zero, 1 2 | addu $t1, $zero, $zero 3 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint15.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | ori $s1, $zero, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint16.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | ori $s1, $s0, 0xabcd 9 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint17.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 8 3 | 4 | .text 5 | ori $t4, $zero, 3 6 | sw $t4, 0 7 | ori $t5, $zero, 2 8 | sw $t5, 4 9 | lw $t2, 4 10 | lw $t1, 0 11 | addu $t3, $t1, $t2 12 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint18.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $zero, 0 8 | 9 | beq $zero, $zero, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $zero, 0x1234 17 | addu $zero, $zero, $zero 18 | 19 | beq $zero, $zero, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint19.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_asm/other/testpoint19.asm -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint2.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | lui $t4 0xaf78 4 | tiao: 5 | ori $t2 $0 0x3018 6 | addu $t5 $t1 $t3 7 | beq $t4 $t5 end 8 | lui $t3 0x49bf 9 | j tiao 10 | addu $t4 $t1 $t3 11 | addu $t4 $t4 $t3 12 | end: 13 | subu $t5 $t1 $t2 14 | #addu $t4 $t4 $t3 15 | ori $t3 $0 0x3044 16 | func: 17 | beq $t3 $31 ha #jal + delay + beq 18 | addu $t4 $t4 $t2 19 | ori $t5 $t3 0x6349 20 | jal func 21 | addu $t5 $t2 $t3 22 | subu $t1 $t2 $t5 23 | ha: 24 | subu $t4 $t4 $0 25 | addu $t5 $0 $t4 26 | beq $t4 $t5 end6 #cal + x + beq 27 | subu $t4 $t5 $t3 28 | addu $t6 $t2 $t3 29 | j ha 30 | end6: 31 | ori $t3 $t4 0x26cb 32 | ori $1 $0 48 33 | addu $ra $ra, $1 34 | lui $2 0x41ba 35 | jr $ra #cal + x + jr 36 | addu $1 $0 $t3 37 | subu $t4 $t4 $t1 38 | ori $s0 $0 24 39 | addu $ra $ra $s0 40 | stein:jr $ra 41 | addu $t4 $t5 $t1 42 | subu $t2 $t4 $t3 43 | ori $1 $0 4 44 | jal stein #jal + change$ra + jr 45 | addu $ra $ra $1 46 | lui $s1 0x6249 47 | subu $s1 $s1 $31 48 | jal stein 49 | subu $t0 $t3 $t5 50 | 51 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint3.asm: -------------------------------------------------------------------------------- 1 | ori $10 $0 1023 2 | ori $11 $0 1 3 | jal fun 4 | addu $12 $31 $0 5 | j next 6 | fun:ori $2 $0 123 7 | jr $31 8 | next: 9 | 10 | 11 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint4.asm: -------------------------------------------------------------------------------- 1 | ori $1 $0 120 2 | lw $0 0($1) 3 | addu $3 $1 $0 -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint5.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,1999 2 | ori $a1,$a0,111 3 | lui $a2,12345 4 | lui $a3,0xffff 5 | lui $t0,0xffff 6 | beq $a3,$t0,eee 7 | addu $s7,$0,$a0 8 | nop 9 | ori $a3,$a3,0xffff 10 | addu $s0,$a0,$a1 11 | addu $s1,$a3,$a3 12 | addu $s2,$a3,$s0 13 | beq $s2,$s3,eee 14 | subu $s0,$a0,$s2 15 | subu $s1,$a3,$a3 16 | eee: 17 | subu $s2,$a3,$a0 18 | subu $s3,$s2,$s1 19 | ori $t0,$0,0x0000 20 | sw $a0,0($t0) 21 | nop 22 | sw $a1,4($t0) 23 | sw $s0,8($t0) 24 | sw $s1,12($t0) 25 | sw $s2,16($t0) 26 | sw $s5,20($t0) 27 | lw $t1,20($t0) 28 | lw $t7,0($t0) 29 | lw $t6,20($t0) 30 | sw $t6,24($t0) 31 | lw $t5,12($t0) 32 | jal end 33 | ori $t0,$t0,1 34 | ori $t1,$t1,1 35 | ori $t2,$t2,2 36 | beq $t0,$t2,eee 37 | lui $t3,1111 38 | jal out 39 | end: 40 | addu $t0,$t0,$t7 41 | jr $ra 42 | out: 43 | addu $t0,$t0,$t3 44 | ori $t2,$t0,0 45 | beq $t0,$t2,qqq 46 | lui $v0,10 47 | qqq: 48 | lui $v0,11 49 | j www 50 | nop 51 | www: 52 | lui $ra,100 53 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint8.asm: -------------------------------------------------------------------------------- 1 | jal loop 2 | nop 3 | jal loop2 4 | nop 5 | jal loop3 6 | nop 7 | jal loop4 8 | nop 9 | ori $t0, $0, 100 10 | loop: 11 | jr $ra 12 | nop 13 | loop2: 14 | nop 15 | jr $ra 16 | nop 17 | loop3: 18 | nop 19 | nop 20 | jr $ra 21 | nop 22 | loop4: 23 | nop 24 | nop 25 | nop 26 | jr $ra 27 | nop 28 | 29 | -------------------------------------------------------------------------------- /TestData/My_test/test_asm/other/testpoint9.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .space 4 3 | 4 | .text 5 | li $t0, 0x12345678 6 | sw $t0, 0 7 | lw $s0, 0 8 | 9 | beq $t0, $s0, skiplw 10 | ori $a0, $zero, 1 11 | 12 | ori $v0, $zero, 1 13 | skiplw: 14 | ori $a0, $zero, 2 15 | 16 | lui $t1, 0x1234 17 | addu $t2, $t1, $zero 18 | 19 | beq $t1, $t2, skipr 20 | ori $a1, $zero, 1 21 | 22 | ori $v1, $zero, 1 23 | skipr: 24 | ori $a1, $zero, 2 25 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/Forward_rs.asm: -------------------------------------------------------------------------------- 1 | lui $t0 0xf65b 2 | ori $t1 $0 0xabfe 3 | lui $t4 0xaf78 4 | tiao: 5 | ori $t2 $0 0x3018 6 | addu $t5 $t1 $t3 7 | beq $t4 $t5 end 8 | lui $t3 0x49bf 9 | j tiao 10 | addu $t4 $t1 $t3 11 | addu $t4 $t4 $t3 12 | end: 13 | subu $t5 $t1 $t2 14 | #addu $t4 $t4 $t3 15 | ori $t3 $0 0x3044 16 | func: 17 | beq $t3 $31 ha #jal + delay + beq 18 | addu $t4 $t4 $t2 19 | ori $t5 $t3 0x6349 20 | jal func 21 | addu $t5 $t2 $t3 22 | subu $t1 $t2 $t5 23 | ha: 24 | subu $t4 $t4 $0 25 | addu $t5 $0 $t4 26 | beq $t4 $t5 end6 #cal + x + beq 27 | subu $t4 $t5 $t3 28 | addu $t6 $t2 $t3 29 | j ha 30 | end6: 31 | ori $t3 $t4 0x26cb 32 | ori $1 $0 48 33 | addu $ra $ra, $1 34 | lui $2 0x41ba 35 | jr $ra #cal + x + jr 36 | addu $1 $0 $t3 37 | subu $t4 $t4 $t1 38 | ori $s0 $0 24 39 | addu $ra $ra $s0 40 | stein:jr $ra 41 | addu $t4 $t5 $t1 42 | subu $t2 $t4 $t3 43 | ori $1 $0 4 44 | jal stein #jal + change$ra + jr 45 | addu $ra $ra $1 46 | lui $s1 0x6249 47 | subu $s1 $s1 $31 48 | jal stein 49 | subu $t0 $t3 $t5 50 | 51 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/code.asm: -------------------------------------------------------------------------------- 1 | ori $gp, $zero, 0 2 | ori $sp, $zero, 0 3 | ori $at, $a3, 0x1010 4 | lw $t2, ($zero) 5 | sw $at, ($zero) 6 | lui $v0, 0x8723 7 | ori $v1, $zero, 0x7856 8 | lui $a0, 0x85ff 9 | ori $a1, $zero, 1 10 | lui $a2, 0xffff 11 | ori $a3, $a3, 0xffff 12 | addu $at, $at, $v0 13 | addu $t1, $at, $v1 14 | subu $t0, $at, $v0 15 | subu $zero, $a3, $zero 16 | nop 17 | nop 18 | nop 19 | nop 20 | nop 21 | #beq $gp, $s1, 0x3060 22 | nop 23 | #j 0x30b0 24 | beq1: 25 | #beq $at, $v0, 0x30b0 26 | nop 27 | ori $v0, $zero, 0xc 28 | nop 29 | nop 30 | nop 31 | #jal 0x3088 32 | sw $at, ($v0) 33 | #j 0x30b0 34 | addu $at, $at, $v0 35 | addu $at, $at, $v0 36 | addu $at, $at, $v0 37 | addu $at, $at, $v0 38 | sw $ra, ($v0) 39 | lw $at, ($v0) 40 | nop 41 | nop 42 | nop 43 | #jr $at 44 | sw $ra, ($v0) 45 | #b 0x30b0 46 | nop 47 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/jump.asm: -------------------------------------------------------------------------------- 1 | ori $10 $0 1023 2 | ori $11 $0 1 3 | jal fun 4 | addu $12 $31 $0 5 | j next 6 | fun:ori $2 $0 123 7 | jr $31 8 | next: 9 | 10 | 11 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/mips1.asm: -------------------------------------------------------------------------------- 1 | ori $1 $0 123 2 | lw $0 0($1) 3 | addu $3 $1 $0 -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/mips3.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,1999 2 | ori $a1,$a0,111 3 | lui $a2,12345 4 | lui $a3,0xffff 5 | lui $t0,0xffff 6 | beq $a3,$t0,eee 7 | addu $s7,$0,$a0 8 | nop 9 | ori $a3,$a3,0xffff 10 | addu $s0,$a0,$a1 11 | addu $s1,$a3,$a3 12 | addu $s2,$a3,$s0 13 | beq $s2,$s3,eee 14 | subu $s0,$a0,$s2 15 | subu $s1,$a3,$a3 16 | eee: 17 | subu $s2,$a3,$a0 18 | subu $s3,$s2,$s1 19 | ori $t0,$0,0x0000 20 | sw $a0,0($t0) 21 | nop 22 | sw $a1,4($t0) 23 | sw $s0,8($t0) 24 | sw $s1,12($t0) 25 | sw $s2,16($t0) 26 | sw $s5,20($t0) 27 | lw $t1,20($t0) 28 | lw $t7,0($t0) 29 | lw $t6,20($t0) 30 | sw $t6,24($t0) 31 | lw $t5,12($t0) 32 | jal end 33 | ori $t0,$t0,1 34 | ori $t1,$t1,1 35 | ori $t2,$t2,2 36 | beq $t0,$t2,eee 37 | lui $t3,1111 38 | jal out 39 | end: 40 | addu $t0,$t0,$t7 41 | jr $ra 42 | out: 43 | addu $t0,$t0,$t3 44 | ori $t2,$t0,0 45 | beq $t0,$t2,qqq 46 | lui $v0,10 47 | qqq: 48 | lui $v0,11 49 | j www 50 | nop 51 | www: 52 | lui $ra,100 53 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/test14.asm: -------------------------------------------------------------------------------- 1 | jal loop 2 | nop 3 | jal loop2 4 | nop 5 | jal loop3 6 | nop 7 | jal loop4 8 | nop 9 | ori $t0, $0, 100 10 | loop: 11 | jr $ra 12 | nop 13 | loop2: 14 | nop 15 | jr $ra 16 | nop 17 | loop3: 18 | nop 19 | nop 20 | jr $ra 21 | nop 22 | loop4: 23 | nop 24 | nop 25 | nop 26 | jr $ra 27 | nop 28 | 29 | -------------------------------------------------------------------------------- /TestData/My_test/test_succeed/强测.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/test_succeed/强测.asm -------------------------------------------------------------------------------- /TestData/My_test/testcode_fullp5/testpoint3.asm: -------------------------------------------------------------------------------- 1 | .text 2 | ori $20 $0 4 3 | ori $21 $0 36 4 | ori $22 $0 64 5 | ori $23 $0 80 6 | ori $24 $0 116 7 | ori $25 $0 140 8 | ori $26 $0 172 9 | ori $27 $0 192 10 | ori $28 $0 228 11 | ori $29 $0 228 12 | addu $20 $15 $29 13 | addu $27 $20 $29 14 | addu $21 $1 $8 15 | addu $27 $21 $8 16 | addu $22 $14 $17 17 | addu $29 $22 $17 18 | addu $23 $6 $29 19 | addu $21 $23 $29 20 | addu $24 $1 $28 21 | addu $13 $24 $28 22 | addu $25 $11 $21 23 | addu $28 $25 $21 24 | addu $26 $7 $3 25 | addu $10 $26 $3 26 | addu $27 $17 $29 27 | addu $8 $27 $29 28 | addu $28 $26 $18 29 | addu $7 $28 $18 30 | addu $29 $21 $13 31 | addu $17 $29 $13 32 | ori $21 $0 36 33 | ori $22 $0 64 34 | ori $23 $0 80 35 | ori $24 $0 116 36 | ori $25 $0 140 37 | ori $26 $0 172 38 | ori $27 $0 192 39 | ori $28 $0 228 40 | ori $29 $0 228 41 | ori $30 $0 4 42 | addu $21 $2 $23 43 | addu $28 $21 $23 44 | addu $22 $1 $12 45 | addu $17 $22 $12 46 | addu $23 $23 $16 47 | addu $14 $23 $16 48 | addu $24 $7 $5 49 | addu $3 $24 $5 50 | addu $25 $16 $18 51 | addu $10 $25 $18 52 | addu $26 $14 $0 53 | addu $21 $26 $0 54 | addu $27 $11 $21 55 | addu $24 $27 $21 56 | addu $28 $4 $16 57 | addu $2 $28 $16 58 | addu $29 $14 $14 59 | addu $8 $29 $14 60 | addu $30 $16 $0 61 | addu $13 $30 $0 62 | ori $22 $0 64 63 | ori $23 $0 80 64 | ori $24 $0 116 65 | ori $25 $0 140 66 | ori $26 $0 172 67 | ori $27 $0 192 68 | ori $28 $0 228 69 | ori $29 $0 228 70 | ori $30 $0 4 71 | ori $31 $0 36 72 | addu $22 $18 $26 73 | addu $28 $22 $26 74 | addu $23 $6 $15 75 | addu $8 $23 $15 76 | addu $24 $16 $19 77 | addu $13 $24 $19 78 | addu $25 $19 $1 79 | addu $0 $25 $1 80 | addu $26 $23 $27 81 | addu $3 $26 $27 82 | addu $27 $14 $8 83 | addu $9 $27 $8 84 | addu $28 $9 $22 85 | addu $18 $28 $22 86 | addu $29 $19 $18 87 | addu $4 $29 $18 88 | addu $30 $14 $31 89 | addu $2 $30 $31 90 | addu $31 $13 $10 91 | addu $19 $31 $10 92 | -------------------------------------------------------------------------------- /TestData/My_test/testcode_fullp5/testpoint6.asm: -------------------------------------------------------------------------------- 1 | .text 2 | ori $20 $0 8 3 | ori $21 $0 28 4 | ori $22 $0 52 5 | ori $23 $0 64 6 | ori $24 $0 100 7 | ori $25 $0 116 8 | ori $26 $0 120 9 | ori $27 $0 136 10 | ori $28 $0 136 11 | ori $29 $0 164 12 | addu $20 $25 $26 13 | addu $25 $25 $20 14 | addu $21 $5 $17 15 | addu $15 $5 $21 16 | addu $22 $13 $26 17 | addu $10 $13 $22 18 | addu $23 $6 $15 19 | addu $24 $6 $23 20 | addu $24 $24 $17 21 | addu $22 $24 $24 22 | addu $25 $1 $12 23 | addu $9 $1 $25 24 | addu $26 $27 $23 25 | addu $16 $27 $26 26 | addu $27 $23 $24 27 | addu $25 $23 $27 28 | addu $28 $12 $26 29 | addu $8 $12 $28 30 | addu $29 $17 $25 31 | addu $16 $17 $29 32 | ori $21 $0 28 33 | ori $22 $0 52 34 | ori $23 $0 64 35 | ori $24 $0 100 36 | ori $25 $0 116 37 | ori $26 $0 120 38 | ori $27 $0 136 39 | ori $28 $0 136 40 | ori $29 $0 164 41 | ori $30 $0 8 42 | addu $21 $1 $0 43 | addu $17 $1 $21 44 | addu $22 $27 $26 45 | addu $17 $27 $22 46 | addu $23 $26 $11 47 | addu $29 $26 $23 48 | addu $24 $28 $10 49 | addu $20 $28 $24 50 | addu $25 $8 $2 51 | addu $0 $8 $25 52 | addu $26 $21 $6 53 | addu $27 $21 $26 54 | addu $27 $23 $0 55 | addu $26 $23 $27 56 | addu $28 $15 $1 57 | addu $19 $15 $28 58 | addu $29 $11 $10 59 | addu $12 $11 $29 60 | addu $30 $29 $9 61 | addu $29 $29 $30 62 | ori $22 $0 52 63 | ori $23 $0 64 64 | ori $24 $0 100 65 | ori $25 $0 116 66 | ori $26 $0 120 67 | ori $27 $0 136 68 | ori $28 $0 136 69 | ori $29 $0 164 70 | ori $30 $0 8 71 | ori $31 $0 28 72 | addu $22 $6 $7 73 | addu $9 $6 $22 74 | addu $23 $14 $15 75 | addu $27 $14 $23 76 | addu $24 $30 $23 77 | addu $0 $30 $24 78 | addu $25 $0 $10 79 | addu $23 $0 $25 80 | addu $26 $16 $0 81 | addu $11 $16 $26 82 | addu $27 $2 $28 83 | addu $7 $2 $27 84 | addu $28 $23 $4 85 | addu $24 $23 $28 86 | addu $29 $18 $18 87 | addu $24 $18 $29 88 | addu $30 $26 $19 89 | addu $30 $26 $30 90 | addu $31 $11 $23 91 | addu $29 $11 $31 92 | -------------------------------------------------------------------------------- /TestData/My_test/testpoint1.asm: -------------------------------------------------------------------------------- 1 | addu $a0,$0,$0 2 | ori $t1,$0,1 3 | ori $t2,$0,2 4 | ori $t3,$0,3 5 | addu $t4,$t1,$t2 6 | subu $t5,$t1,$t2 7 | jal out 8 | addu $t3,$t4,$0 9 | 10 | out: 11 | ori $a0,$0,11 12 | beq $a0,$a1,end 13 | lui $a2,111 14 | jr $ra 15 | ori $a1,$0,11 16 | end: 17 | nop -------------------------------------------------------------------------------- /TestData/My_test/testpoint15.asm: -------------------------------------------------------------------------------- 1 | lui $5, 233 2 | lui $6, 233 3 | lui $5, 122 4 | addu $6,$5,$5 5 | subu $6,$5,$5 6 | ori $6,123 7 | sw $5, 0($0) 8 | sw $6, 4($0) 9 | lw $7, 0($0) 10 | lw $8, 4($0) 11 | addu $9,$9,$8 12 | addu $10,$9,$8 13 | sw $10, 44($0) 14 | lw $11, 44($0) 15 | add $12,$11,$11 -------------------------------------------------------------------------------- /TestData/My_test/testpoint16.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/testpoint16.asm -------------------------------------------------------------------------------- /TestData/My_test/testpoint2.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,111 2 | jal end 3 | nop 4 | nop 5 | nop 6 | j out 7 | nop 8 | end: 9 | jr $ra 10 | nop 11 | out: 12 | ori $a1,$0,10 -------------------------------------------------------------------------------- /TestData/My_test/testpoint23.asm: -------------------------------------------------------------------------------- 1 | .data 2 | .macro push(%d) 3 | sw %d,0($s4) 4 | addu $s4,$s4,$s3 5 | .end_macro 6 | 7 | .macro pop(%d) 8 | subu $s4, $s4, $s3 9 | lw %d, 0($s4) 10 | .end_macro 11 | 12 | .text 13 | ori $s0, $0, 0 14 | ori $s1, $0, 1 15 | ori $s2, $0, 2 16 | ori $s3, $0, 4 17 | ori $s4, $0, 0 18 | ori $a0, $0, 7 19 | jal fib 20 | addu $t9, $0, $v0 21 | ori $t0, $0, 0x2333 22 | ori $t1, $0, 0x2333 23 | beq $t0, $t1, end 24 | 25 | fib: 26 | push($ra) 27 | beq $a0, $s0, return 28 | beq $a0, $s1, return 29 | push($a0) 30 | subu $a0, $a0, $s1 31 | jal fib 32 | pop($a0) 33 | addu $t0, $0, $v0 34 | push($t0) 35 | push($a0) 36 | subu $a0, $a0,$s2 37 | jal fib 38 | pop($a0) 39 | pop($t0) 40 | addu $v0, $t0,$v0 41 | pop($ra) 42 | jr $ra 43 | return: 44 | ori $v0, $0, 1 45 | pop($ra) 46 | jr $ra 47 | end: 48 | nop -------------------------------------------------------------------------------- /TestData/My_test/testpoint28.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,0x00003010 #16 2 | jr $3 #4 3 | nop#8 4 | ori $4,$0,123 #12 5 | ori $5,$0,0x00003010 #16 6 | ori $6,$0,24#24 7 | addu $7,$5,$6 #24 8 | jr $7 #28 9 | nop 10 | ori $1,$0,123 11 | add $9,$7,$7 -------------------------------------------------------------------------------- /TestData/My_test/testpoint29.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/My_test/testpoint29.asm -------------------------------------------------------------------------------- /TestData/My_test/testpoint3.asm: -------------------------------------------------------------------------------- 1 | ori $10 $0 1023 2 | ori $11 $0 1 3 | jal fun 4 | addu $12 $31 $0 5 | j next 6 | fun:ori $2 $0 123 7 | jr $31 8 | next: 9 | 10 | 11 | -------------------------------------------------------------------------------- /TestData/My_test/testpoint4.asm: -------------------------------------------------------------------------------- 1 | ori $a1,$0,111 2 | ori $a2,$0,112 3 | beq $a1,$a2,end 4 | ori $a1,$a1,111 5 | beq $a1,$a1,out 6 | nop 7 | end: 8 | nop 9 | out: 10 | addu $a0,$a0,$a1 -------------------------------------------------------------------------------- /TestData/My_test/testpoint5.asm: -------------------------------------------------------------------------------- 1 | ori $a1,$0,111 2 | ori $a2,$a0,112 3 | addu $0,$a1,$a2 4 | subu $a2,$a1,$0 -------------------------------------------------------------------------------- /TestData/My_test/testpoint6.asm: -------------------------------------------------------------------------------- 1 | ori $3,$0,123 2 | ori $4,$0,123 3 | beq $4,$3,nn 4 | addu $9,$3,$3 5 | addu $10,$5,$5 6 | nn: 7 | jal next 8 | ori $5, $0,345 9 | ori $6,$0,789 10 | next: 11 | ori $4,$0,1234567 -------------------------------------------------------------------------------- /TestData/My_test/综合测试.asm: -------------------------------------------------------------------------------- 1 | ori $a0,$0,1999 2 | ori $a1,$a0,111 3 | lui $a2,12345 4 | lui $a3,0xffff 5 | lui $t0,0xffff 6 | beq $a3,$t0,eee 7 | addu $s7,$0,$a0 8 | nop 9 | ori $a3,$a3,0xffff 10 | addu $s0,$a0,$a1 11 | addu $s1,$a3,$a3 12 | addu $s2,$a3,$s0 13 | beq $s2,$s3,eee 14 | subu $s0,$a0,$s2 15 | subu $s1,$a3,$a3 16 | eee: 17 | subu $s2,$a3,$a0 18 | subu $s3,$s2,$s1 19 | ori $t0,$0,0x0000 20 | sw $a0,0($t0) 21 | nop 22 | sw $a1,4($t0) 23 | sw $s0,8($t0) 24 | sw $s1,12($t0) 25 | sw $s2,16($t0) 26 | sw $s5,20($t0) 27 | lw $t1,20($t0) 28 | lw $t7,0($t0) 29 | lw $t6,20($t0) 30 | sw $t6,24($t0) 31 | lw $t5,12($t0) 32 | jal end 33 | ori $t0,$t0,1 34 | ori $t1,$t1,1 35 | ori $t2,$t2,2 36 | beq $t0,$t2,eee 37 | lui $t3,1111 38 | jal out 39 | end: 40 | addu $t0,$t0,$t7 41 | jr $ra 42 | out: 43 | addu $t0,$t0,$t3 44 | ori $t2,$t0,0 45 | beq $t0,$t2,qqq 46 | lui $v0,10 47 | qqq: 48 | lui $v0,11 49 | j www 50 | nop 51 | www: 52 | lui $ra,100 53 | -------------------------------------------------------------------------------- /TestData/SpecialJudge.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | char buffer1[10005],buffer2[10005]; 5 | 6 | int main() 7 | { 8 | FILE *jiXiaoZu,*jiDaZu; 9 | jiXiaoZu=fopen("jiXiaoZu/out.txt","r"); 10 | jiDaZu=fopen("jiDaZu/out.txt","r"); 11 | int index1,index2,cnt=0; char *p; 12 | while ((p=fgets(buffer1,10005,jiXiaoZu))) 13 | { 14 | if (strstr(buffer1,"<=")==NULL) continue; 15 | while ((p=fgets(buffer2,10005,jiDaZu))) 16 | if (strstr(buffer2,"<=")!=NULL) break; cnt++; 17 | if (p==NULL) {puts("jiXiaoZu is more"); fclose(jiXiaoZu),fclose(jiDaZu); return 1;} 18 | for (index1=0;buffer1[index1] && buffer1[index1]!='@';) index1++; 19 | for (index2=0;buffer2[index2] && buffer2[index2]!='@';) index2++; 20 | if (strcmp(buffer1+index1,buffer2+index2)) 21 | { 22 | printf("wrong at line %d\n",cnt); 23 | printf("jiXiaoZu answer is %s\n",buffer1+index1); 24 | printf("jiDaZu answer is %s\n",buffer2+index2); 25 | fclose(jiXiaoZu),fclose(jiDaZu); return 1; 26 | } 27 | } 28 | p=fgets(buffer2,10005,jiDaZu); 29 | if (p!=NULL) {puts("jiDaZu is more"); fclose(jiXiaoZu),fclose(jiDaZu); return 1;} 30 | printf("tot %d that's good oh yeah",cnt); 31 | fclose(jiXiaoZu),fclose(jiDaZu); return 0; 32 | } -------------------------------------------------------------------------------- /TestData/ch_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/ch_test.zip -------------------------------------------------------------------------------- /TestData/p7_test.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/p7_test.zip -------------------------------------------------------------------------------- /TestData/test/t2.asm: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BUAADreamer/BUAA-CO-2020/4e13bc3fe84303570d9d105561fd3ce6fa410574/TestData/test/t2.asm -------------------------------------------------------------------------------- /TestData/testcode_fullp5/testpoint3.asm: -------------------------------------------------------------------------------- 1 | .text 2 | ori $20 $0 4 3 | ori $21 $0 36 4 | ori $22 $0 64 5 | ori $23 $0 80 6 | ori $24 $0 116 7 | ori $25 $0 140 8 | ori $26 $0 172 9 | ori $27 $0 192 10 | ori $28 $0 228 11 | ori $29 $0 228 12 | addu $20 $15 $29 13 | addu $27 $20 $29 14 | addu $21 $1 $8 15 | addu $27 $21 $8 16 | addu $22 $14 $17 17 | addu $29 $22 $17 18 | addu $23 $6 $29 19 | addu $21 $23 $29 20 | addu $24 $1 $28 21 | addu $13 $24 $28 22 | addu $25 $11 $21 23 | addu $28 $25 $21 24 | addu $26 $7 $3 25 | addu $10 $26 $3 26 | addu $27 $17 $29 27 | addu $8 $27 $29 28 | addu $28 $26 $18 29 | addu $7 $28 $18 30 | addu $29 $21 $13 31 | addu $17 $29 $13 32 | ori $21 $0 36 33 | ori $22 $0 64 34 | ori $23 $0 80 35 | ori $24 $0 116 36 | ori $25 $0 140 37 | ori $26 $0 172 38 | ori $27 $0 192 39 | ori $28 $0 228 40 | ori $29 $0 228 41 | ori $30 $0 4 42 | addu $21 $2 $23 43 | addu $28 $21 $23 44 | addu $22 $1 $12 45 | addu $17 $22 $12 46 | addu $23 $23 $16 47 | addu $14 $23 $16 48 | addu $24 $7 $5 49 | addu $3 $24 $5 50 | addu $25 $16 $18 51 | addu $10 $25 $18 52 | addu $26 $14 $0 53 | addu $21 $26 $0 54 | addu $27 $11 $21 55 | addu $24 $27 $21 56 | addu $28 $4 $16 57 | addu $2 $28 $16 58 | addu $29 $14 $14 59 | addu $8 $29 $14 60 | addu $30 $16 $0 61 | addu $13 $30 $0 62 | ori $22 $0 64 63 | ori $23 $0 80 64 | ori $24 $0 116 65 | ori $25 $0 140 66 | ori $26 $0 172 67 | ori $27 $0 192 68 | ori $28 $0 228 69 | ori $29 $0 228 70 | ori $30 $0 4 71 | ori $31 $0 36 72 | addu $22 $18 $26 73 | addu $28 $22 $26 74 | addu $23 $6 $15 75 | addu $8 $23 $15 76 | addu $24 $16 $19 77 | addu $13 $24 $19 78 | addu $25 $19 $1 79 | addu $0 $25 $1 80 | addu $26 $23 $27 81 | addu $3 $26 $27 82 | addu $27 $14 $8 83 | addu $9 $27 $8 84 | addu $28 $9 $22 85 | addu $18 $28 $22 86 | addu $29 $19 $18 87 | addu $4 $29 $18 88 | addu $30 $14 $31 89 | addu $2 $30 $31 90 | addu $31 $13 $10 91 | addu $19 $31 $10 92 | -------------------------------------------------------------------------------- /TestData/testcode_fullp5/testpoint6.asm: -------------------------------------------------------------------------------- 1 | .text 2 | ori $20 $0 8 3 | ori $21 $0 28 4 | ori $22 $0 52 5 | ori $23 $0 64 6 | ori $24 $0 100 7 | ori $25 $0 116 8 | ori $26 $0 120 9 | ori $27 $0 136 10 | ori $28 $0 136 11 | ori $29 $0 164 12 | addu $20 $25 $26 13 | addu $25 $25 $20 14 | addu $21 $5 $17 15 | addu $15 $5 $21 16 | addu $22 $13 $26 17 | addu $10 $13 $22 18 | addu $23 $6 $15 19 | addu $24 $6 $23 20 | addu $24 $24 $17 21 | addu $22 $24 $24 22 | addu $25 $1 $12 23 | addu $9 $1 $25 24 | addu $26 $27 $23 25 | addu $16 $27 $26 26 | addu $27 $23 $24 27 | addu $25 $23 $27 28 | addu $28 $12 $26 29 | addu $8 $12 $28 30 | addu $29 $17 $25 31 | addu $16 $17 $29 32 | ori $21 $0 28 33 | ori $22 $0 52 34 | ori $23 $0 64 35 | ori $24 $0 100 36 | ori $25 $0 116 37 | ori $26 $0 120 38 | ori $27 $0 136 39 | ori $28 $0 136 40 | ori $29 $0 164 41 | ori $30 $0 8 42 | addu $21 $1 $0 43 | addu $17 $1 $21 44 | addu $22 $27 $26 45 | addu $17 $27 $22 46 | addu $23 $26 $11 47 | addu $29 $26 $23 48 | addu $24 $28 $10 49 | addu $20 $28 $24 50 | addu $25 $8 $2 51 | addu $0 $8 $25 52 | addu $26 $21 $6 53 | addu $27 $21 $26 54 | addu $27 $23 $0 55 | addu $26 $23 $27 56 | addu $28 $15 $1 57 | addu $19 $15 $28 58 | addu $29 $11 $10 59 | addu $12 $11 $29 60 | addu $30 $29 $9 61 | addu $29 $29 $30 62 | ori $22 $0 52 63 | ori $23 $0 64 64 | ori $24 $0 100 65 | ori $25 $0 116 66 | ori $26 $0 120 67 | ori $27 $0 136 68 | ori $28 $0 136 69 | ori $29 $0 164 70 | ori $30 $0 8 71 | ori $31 $0 28 72 | addu $22 $6 $7 73 | addu $9 $6 $22 74 | addu $23 $14 $15 75 | addu $27 $14 $23 76 | addu $24 $30 $23 77 | addu $0 $30 $24 78 | addu $25 $0 $10 79 | addu $23 $0 $25 80 | addu $26 $16 $0 81 | addu $11 $16 $26 82 | addu $27 $2 $28 83 | addu $7 $2 $27 84 | addu $28 $23 $4 85 | addu $24 $23 $28 86 | addu $29 $18 $18 87 | addu $24 $18 $29 88 | addu $30 $26 $19 89 | addu $30 $26 $30 90 | addu $31 $11 $23 91 | addu $29 $11 $31 92 | --------------------------------------------------------------------------------