├── .gitignore ├── README.md └── ar9300_eeprom ├── LICENSE ├── Makefile ├── README.md ├── art ├── mr3020_v1.8_2050500194_rev1.1_cz.bin ├── wdr3600_v1.1_2050500231_rev1.0_pl.bin ├── wdr3600_v1.1_2050500272_rev1.3_pl.bin └── wdr4310_v1.0_2050500271_rev1.3_cn.bin ├── bin └── ar9300_eeprom ├── dump ├── mr3020_v1.8_2050500194_rev1.1_cz.txt ├── wdr3600_v1.1_2050500231_rev1.0_pl.txt ├── wdr3600_v1.1_2050500272_rev1.3_pl.txt └── wdr4310_v1.0_2050500271_rev1.3_cn.txt ├── include ├── ar9003_eeprom.h ├── ar9300_eeprom.h ├── eeprom.h ├── types.h └── wdr4300.h └── src ├── ar9300_eeprom.c ├── detect_eeprom.c ├── dump_eeprom.c └── io_eeproms.c /.gitignore: -------------------------------------------------------------------------------- 1 | # Object files 2 | *.o 3 | *.ko 4 | *.obj 5 | *.elf 6 | 7 | # Precompiled Headers 8 | *.gch 9 | *.pch 10 | 11 | # Libraries 12 | *.lib 13 | *.a 14 | *.la 15 | *.lo 16 | 17 | # Shared objects (inc. Windows DLLs) 18 | *.dll 19 | #*.so 20 | *.so.* 21 | *.dylib 22 | 23 | # Executables 24 | *.exe 25 | *.out 26 | *.app 27 | *.i*86 28 | *.x86_64 29 | *.hex 30 | 31 | # Debug files 32 | *.dSYM/ 33 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # ARTool 2 | Tool for Atheros ART partition editing 3 | 4 | # Work In Progress 5 | 6 | ## struct ar9300_eeprom 7 | | Size (byte) | Type | Name | Description | 8 | | :----------: | ---- | ---- | ------- | 9 | | 1 | Unsigned Int | EEPROM Version | Eg: 0x02 | 10 | | 1 | Unsigned Int | Template Version | Eg: 0x02 | 11 | | 6 | Unsigned Int | MAC Address | Eg: 0x00 0x02 0x03 0x04 0x05 0x06 | 12 | | 20 | Unsigned Int | Customer Data | | 13 | | | | | Base EEEPROM Header | 14 | | 2 | Unsigned LE Int | Regulatory Domain 1 | length in bytes | 15 | | 2 | Unsigned LE Int | Regulatory Domain 2 | length in bytes | 16 | | 1 | 4 bit/4 bit | TX RX Mask | First 4 bit TX Mask, last 4 bit RX Mask | 17 | | 1 | Unsigned Int | Operatoin Flags | | 18 | | 1 | Unsigned Int | EEP Misc | | 19 | | 1 | Unsigned Int | RF Silent | | 20 | | 1 | Unsigned Int | BlueTooth Options | | 21 | | 1 | Unsigned Int | Device Capabilities | | 22 | | 1 | Unsigned Int | Device Type | | 23 | | 1 | Signed Int | Power Table Offset | | 24 | | 1 | Unsigned Int | Params for tuning capabilities 1 | | 25 | | 1 | Unsigned Int | Params for tuning capabilities 2 | | 26 | | 1 | Unsigned Int | Feature Enable | bit 0 1 2 3 4 5 | 27 | | 1 | Unsigned Int | Misc Configuratio | | 28 | | 1 | Unsigned Int | EEPROM write enable GPIO | | 29 | | 1 | Unsigned Int | WLAN disable GPIO | | 30 | | 1 | Unsigned Int | WLAN LED GPIO | | 31 | | 1 | Unsigned Int | RX band select GPIO | | 32 | | 1 | Unsigned Int | TX RX gain | | 33 | | 4 | Unsigned LE Int | SW internal Regulator fields | | 34 | | | | | Modal Header 2G | 35 | | 4 | Unsigned LE Int | Antenna control common 1 | | 36 | | 4 | Unsigned LE Int | Antenna control common 2 | | 37 | | 2 | Unsigned LE Int | Antenna control chain 1 | | 38 | | 2 | Unsigned LE Int | Antenna control chain 2 | | 39 | | 2 | Unsigned LE Int | Antenna control chain 3 | | 40 | | 1 | Unsigned Int | X attenuation 1 db 1 | | 41 | | 1 | Unsigned Int | X attenuation 1 db 2 | | 42 | | 1 | Unsigned Int | X attenuation 1 db 3 | | 43 | | 1 | Unsigned Int | X attenuation 1 margin 1 | | 44 | | 1 | Unsigned Int | X attenuation 1 margin 2 | | 45 | | 1 | Unsigned Int | X attenuation 1 margin 3 | | 46 | | 1 | Signed Int | Temp Slope | | 47 | | 1 | Signed Int | Volt Slope | | 48 | | 1 | Unsigned Int | Spur Channel 1 | Spur channels in usual fbin coding format | 49 | | 1 | Unsigned Int | Spur Channel 2 | Spur channels in usual fbin coding format | 50 | | 1 | Unsigned Int | Spur Channel 3 | Spur channels in usual fbin coding format | 51 | | 1 | Unsigned Int | Spur Channel 4 | Spur channels in usual fbin coding format | 52 | | 1 | Unsigned Int | Spur Channel 5 | Spur channels in usual fbin coding format | 53 | | 1 | Unsigned Int | Noise Floor Threshold Chain 1 | Check if the register is per chain | 54 | | 1 | Unsigned Int | Noise Floor Threshold Chain 2 | Check if the register is per chain | 55 | | 1 | Unsigned Int | Noise Floor Threshold Chain 3 | Check if the register is per chain | 56 | | 11 | Unsigned Int | Reserved | | 57 | | 1 | Signed Int | Quick drop | | 58 | | 1 | Unsigned Int | X Pa Bias Level | | 59 | | 1 | Unsigned Int | TX frame to data start | | 60 | | 1 | Unsigned Int | TX frame to Pa on | | 61 | | 1 | Unsigned Int | TX Clip | | 62 | | 1 | Signed Int | Antenna gain | | 63 | | 1 | Unsigned Int | Switch settling | | 64 | | 1 | Signed Int | ADC desired size | | 65 | | 1 | Unsigned Int | TX end to x Pa off | | 66 | | 1 | Unsigned Int | TX end to RX on | | 67 | | 1 | Unsigned Int | Threshold 62 | | 68 | | 4 | Unsigned Int | Papd rate mask High Throughput 20 | | 69 | | 4 | Unsigned Int | Papd rate mask High Throughput 40 | | 70 | | 3 | Unsigned Int | Switch Comspdt | | 71 | | 1 | Unsigned Int | Xlna bias strength | | 72 | | 1 | Unsigned Int | Future Modal 1 | | 73 | | 1 | Unsigned Int | Future Modal 2 | | 74 | | 1 | Unsigned Int | Future Modal 3 | | 75 | | 1 | Unsigned Int | Future Modal 4 | | 76 | | 1 | Unsigned Int | Future Modal 5 | | 77 | | 1 | Unsigned Int | Future Modal 6 | | 78 | | 1 | Unsigned Int | Future Modal 7 | | 79 | | | | | Base Extension 1 | 80 | | | | | | 81 | | 1 | Unsigned Int | Cal Freq Pier 2G 1 | | 82 | | 1 | Unsigned Int | Cal Freq Pier 2G 2 | | 83 | | 1 | Unsigned Int | Cal Freq Pier 2G 3 | | 84 | | | | | Cal data per freq op loop Chain 1 Pier 1 | 85 | | | | | | 86 | | | | | Cal data per freq op loop Chain 1 Pier 2 | 87 | | | | | | 88 | | | | | Cal data per freq op loop Chain 1 Pier 3 | 89 | | | | | | 90 | | | | | Cal data per freq op loop Chain 2 Pier 1 | 91 | | | | | | 92 | | | | | Cal data per freq op loop Chain 2 Pier 2 | 93 | | | | | | 94 | | | | | Cal data per freq op loop Chain 2 Pier 3 | 95 | | | | | | 96 | | | | | Cal data per freq op loop Chain 3 Pier 1 | 97 | | | | | | 98 | | | | | Cal data per freq op loop Chain 3 Pier 2 | 99 | | | | | | 100 | | | | | Cal data per freq op loop Chain 3 Pier 3 | 101 | | | | | | 102 | | 1 | Unsigned Int | Cal Target freq bin CCK 1 | | 103 | | 1 | Unsigned Int | Cal Target freq bin CCK 2 | | 104 | | 1 | Unsigned Int | TX end to RX on | | 105 | | 1 | Unsigned Int | TX end to RX on | | 106 | 107 | -------------------------------------------------------------------------------- /ar9300_eeprom/LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 2, June 1991 3 | 4 | Copyright (C) 1989, 1991 Free Software Foundation, Inc., 5 | 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 6 | Everyone is permitted to copy and distribute verbatim copies 7 | of this license document, but changing it is not allowed. 8 | 9 | Preamble 10 | 11 | The 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It is safest 289 | to attach them to the start of each source file to most effectively 290 | convey the exclusion of warranty; and each file should have at least 291 | the "copyright" line and a pointer to where the full notice is found. 292 | 293 | {description} 294 | Copyright (C) {year} {fullname} 295 | 296 | This program is free software; you can redistribute it and/or modify 297 | it under the terms of the GNU General Public License as published by 298 | the Free Software Foundation; either version 2 of the License, or 299 | (at your option) any later version. 300 | 301 | This program is distributed in the hope that it will be useful, 302 | but WITHOUT ANY WARRANTY; without even the implied warranty of 303 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 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If this is what you want to do, use the GNU Lesser General 339 | Public License instead of this License. 340 | 341 | -------------------------------------------------------------------------------- /ar9300_eeprom/Makefile: -------------------------------------------------------------------------------- 1 | AR9300 := ar9300_eeprom 2 | SRCDIR := src 3 | INC := include 4 | BUILDDIR := build 5 | 6 | BINAR9300 := bin/$(AR9300) 7 | SRCAR9300 := $(shell find $(SRCDIR) -type f -name "*.c") 8 | OBJAR9300 := $(patsubst $(SRCDIR)/%,$(BUILDDIR)/%,$(SRCAR9300:.c=.o)) 9 | 10 | LDFLAGS= 11 | CFLAGS=-c -O2 -I/lib/modules/`uname -r`/build/include 12 | CC=gcc 13 | 14 | all : $(AR9300) 15 | 16 | $(AR9300): $(SRCAR9300) $(BINAR9300) 17 | 18 | $(BINAR9300): $(OBJAR9300) 19 | $(CC) $(LDFLAGS) $(OBJAR9300) -o $@ 20 | 21 | $(BUILDDIR)/%.o: $(SRCDIR)/%.c 22 | @mkdir -p $(BUILDDIR) 23 | $(CC) $(CFLAGS) -I $(INC) $< -o $@ 24 | 25 | clean: 26 | rm -r $(BUILDDIR) $(BINAR9300) 27 | -------------------------------------------------------------------------------- /ar9300_eeprom/README.md: -------------------------------------------------------------------------------- 1 | Tool for Atheros ART partition 2 | ============================== 3 | 4 | Dump, remove regulatory limits and fixes the Atheros ART partition with ar9300 layout, compatible with WDR3600, WDR4300, WDR4310 and more. 5 | 6 | * *I have to thank some (many) people who provided tips and information on forums that saved weeks of hard work.* 7 | 8 | 9 | Development status 10 | ------------------ 11 | 12 | * Dump of the ART partition with ar9300 layout that enables the analysis of settings. 13 | * Have removes the regulatory domain specific (puts all the power in 60dB as suggested by source), leaving it to the drive and configuration apply the appropriate regulatory domain. 14 | * Fix the table 'Calibration 5GHz' that is poorly formatted / incomplete (worked correct only between channels 149 and 165) in WDR4310 v1.0 board 2050500271 r1.3. The values are interpolated, but until I have in hand a WDR4300 ART partition with the same board revision is that I can do. 15 | 16 | 17 | Compiling 18 | --------- 19 | 20 | * Compile for Linux is only run the command 'make' the project root directory. 21 | * The source codes are prepared to be compiled in Visual Studio. 22 | 23 | Take a backup of your ART partition 24 | ----------------------------------- 25 | 26 | ``` 27 | (This command will show you all MTD partitions) 28 | 29 | cat /proc/mtd 30 | 31 | 32 | dev: size erasesize name 33 | mtd0: 00020000 00010000 "u-boot" 34 | mtd1: 000f1808 00010000 "kernel" 35 | mtd2: 006de7f8 00010000 "rootfs" 36 | mtd3: 002e0000 00010000 "rootfs_data" 37 | mtd4: 00010000 00010000 "art" 38 | mtd5: 007d0000 00010000 "firmware" 39 | 40 | 41 | (To backup ART partition in this example, run) 42 | 43 | cat /dev/mtd4 > /tmp/art.bin 44 | ``` 45 | 46 | 47 | How can you contribute to the project 48 | ------------------------------------- 49 | 50 | * Help identify if your router is compatible with the program. The routers WDR3600, WDR4300 and WDR4310 are compatible, they use the AR9344 and AR9580 chips, routers using other Atheros chips can also use ar9300 layout. It is only possible to identify the compatibility taking a backup of ART partition and run the program. Send the result of the dump or compare with [this result](https://github.com/zeptoZB/ar9300_eeprom/blob/master/dump/wdr4310_v1.0_2050500271_rev1.3_cn.txt). Usually the MAC address of the dump is not used but not ownership claim to be true in your router model, suggest that, in doubt, wipe this field for your security before sending the dump. 51 | 52 | * Contributing its ART partition. Help the program to automatically identify your router (model, version, board number e revision). Send your ART partition with the following information: 53 | 54 | * Model and version found in the router label. 55 | 56 |

Router label
source: tp-link.com

57 | 58 | * Board number and revision normally found together in one of the board corners. 59 | 60 |

Board number and revision
source: openwrt.org

61 | 62 | * Where the router was marketed, as for example a router marketed in the European Union usually has a regulatory domain different from marketed in the USA. 63 | 64 | * Report if you know any abnormal behavior of the your wireless router. May be due to the configuration of the ART partition, if so is likely to be fixed. 65 | 66 | * Your contribution as a developer is welcome. The ath9k drive uses other layouts beyond the ar9300, interprets them increases the number of compatible routers. 67 | 68 | * Help improve this documentation, your suggestion is welcome, unfortunately my English is not good and the google translate not do miracles. 69 | 70 | 71 | How everything started 72 | ---------------------- 73 | 74 | I purchased a router WDR4310 (Chinese version of WDR4300) when installed DD-WRT was detected that the 5GHz worked correct only between channels 149 (5745MHz) and 165 (5825MHz). I tried the OpenWrt and problem persisted, with search the web the conclusion was that the ART partition imposed some restriction, but I not found a solution. 75 | 76 | The other day I was looking for how to overclock into WDR4310, I found a [great article](http://aspiregemstone.blogspot.com.br/2014/12/overclocking-tp-link-wdr4300.html) that made everything very simple and yet clarified several points, making it much easier in trying to solve the problem of 5GHz restriction. 77 | 78 | * In WDR4300 the MAC address is not on ART partition but in the upper u-boot partition (64KB U-Boot + 64KB settings). 79 | * The modified U-Boot allows you to update the ART partition easily and safely. 80 | * ART partition has the calibration of the wireless then change the partition WDR4310 by the WDR4300 should remove the restrictions. 81 | * With the [backup of WDR4300](https://github.com/gwlim/Openwrt_Firmware/tree/master/TP-Link_TL-WDR3500-3600-43XX-WM4350R/TL-WDR4300-BackUp_Image_Only) closed everything needed to test. 82 | 83 | The test was successful, the WDR4310 worked properly in 5GHz. But I thought the solution was too simplistic, because the ART partition contain the calibration of the wireless so even though all work good, suspected that the calibration of WDR4310 should be close to WDR4300 but not equal. I decided the one looking in the source code of OpenWrt, everything is there and only find the correct sources, was lucky to find them. 84 | 85 | 86 | Looking the source code of OpenWrt 87 | ---------------------------------- 88 | 89 | The starting point was 'linux-(version)/arch/mips/ath79/mach-tl-wdr4300.c' that is for routers WDR3600, WDR4300 and WDR4310 that has the same hardware (WDR3600 has the same board but the components were suppressed a chain). Analyzing this source has confirmation that the data is in 0x1000 (the offset in ART partition) to 2,4GHz and the data is in 0x5000 to 5GHz and the MAC address that is in u-boot partition. 90 | 91 | The Atheros wireless drive for this router is in 'linux-(version)/drivers/net/wireless/ath/ath9k'. Analyzing the sources, I found that the ART partition data is loaded directly into the struct ar9300_eeprom (definition in the source 'ar9003_eeprom.h'). The starting point for a dump were to ath9k_hw_ar9003_dump_eeprom and ar9003_dump_modal_eeprom functions in source 'ar9003_eeprom.c'. After a long analysis field-by-field, mainly in the source 'ar9003_eeprom.c', have had the first dump version. 92 | 93 | 94 | Analysis, conclusions and speculations 95 | -------------------------------------- 96 | 97 | Based on the limited information obtained so far (ART of one WDR4310 and of two WDR3400) the result for now is: 98 | * Most likely, that the calibration data contained in ART partition are not unique per router, but vary according to the revision of the board. 99 | * The data are loaded directly without any CRC consistency facilitating the changes. 100 | * The MAC address is not on the partition ART allowing test and distribute modified versions without bothering to adjust or be touting the MAC address. 101 | * Various fields presented identical in the three ART images, some are relevant to the correct operation of wireless, others are obsolete or not used by the drive. I did not spend much time with them as it is not the focus. 102 | * The fields 'Caps Tuning' (2.4GHz and 5GHz) are to the accuracy of the crystal clock. Different revisions of board normally will have these different parameters. A good indication that change the ART with another router without looking at the revision of the board may be bad idea. 103 | * The tables 'Calibration' (2.4GHz and 5GHz) are to calibrate / compensate asymmetries between the chains and deviations from expected. Has significant variation between board revisions. Confirming that change the ART with another router without looking at the revision of the board is bad idea. 104 | * The tables 'Target 2.4GHz (11B, 11G, HT20, HT40)', 'Target 5GHz (11A, HT20, HT40)' specify the maximum power due to the speed and fequency of the connection. For the analysis of the sources these tables should (and seem) have only the hardware power limitations, but can be used to impose a regulatory domain specific (I hope they are not used to this). These tables are vital to the health of your router and the wireless vicinity, because they limit the hardware to secure powers for the proper functioning. Change these values or even use a drive that ignores them has consequences. Power up the hardware limit can have a similar effect to a stereo at full volume, a lot of noise, a lot of distortion, it works worse than the more moderate powers, not to mention all that noise interferes in the wireless vicinity operation. Overheating generate thermal erosion deteriorates the power stage, further increasing noise and distortion and over time leads to burning of it. The power may be as high (remembering +3dB that is twice the power) the power stage burning occurs in a short time. Now assume that the hardware has protection from excess power, then none of the above is valid, all table values are merely informative, is useless exceed, are fakes values because the hardware limits the power with supposed to. And last, for much power to the router is a few meters and with little obstacle walls. 105 | * The tables 'Regulatory (2.4GHz and 5GHz)' are to impose regulatory domain specific, limiting the maximum power, vary with where routers are marketed. 106 | 107 | 108 | License 109 | ------- 110 | 111 | This project is Free Software, licensed under version 2 of the **GNU General Public License**. 112 | 113 | 114 | Credits 115 | ------- 116 | 117 | * [pepe2k](https://github.com/pepe2k) contribution with ART partitions. 118 | -------------------------------------------------------------------------------- /ar9300_eeprom/art/mr3020_v1.8_2050500194_rev1.1_cz.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BigNerd95/ARTool/fe91fee249f002f1352a72f4fc6077d113f3cbd7/ar9300_eeprom/art/mr3020_v1.8_2050500194_rev1.1_cz.bin -------------------------------------------------------------------------------- /ar9300_eeprom/art/wdr3600_v1.1_2050500231_rev1.0_pl.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BigNerd95/ARTool/fe91fee249f002f1352a72f4fc6077d113f3cbd7/ar9300_eeprom/art/wdr3600_v1.1_2050500231_rev1.0_pl.bin -------------------------------------------------------------------------------- /ar9300_eeprom/art/wdr3600_v1.1_2050500272_rev1.3_pl.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BigNerd95/ARTool/fe91fee249f002f1352a72f4fc6077d113f3cbd7/ar9300_eeprom/art/wdr3600_v1.1_2050500272_rev1.3_pl.bin -------------------------------------------------------------------------------- /ar9300_eeprom/art/wdr4310_v1.0_2050500271_rev1.3_cn.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BigNerd95/ARTool/fe91fee249f002f1352a72f4fc6077d113f3cbd7/ar9300_eeprom/art/wdr4310_v1.0_2050500271_rev1.3_cn.bin -------------------------------------------------------------------------------- /ar9300_eeprom/bin/ar9300_eeprom: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BigNerd95/ARTool/fe91fee249f002f1352a72f4fc6077d113f3cbd7/ar9300_eeprom/bin/ar9300_eeprom -------------------------------------------------------------------------------- /ar9300_eeprom/dump/mr3020_v1.8_2050500194_rev1.1_cz.txt: -------------------------------------------------------------------------------- 1 | Board not detected. 2 | 3 | EEPROM 0x1000: 4 | ---------------------------------------------------------------------------------------- 5 | EEPROM Version : 2 6 | Template Version : 2 7 | MAC Address : 00 03 7F BE F0 95 8 | Cust Data : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9 | ---------------------------------------------------------------------------------------- 10 | RegDomain1 : 0 11 | RegDomain2 : 31 12 | TX Mask : 0b00000001 13 | RX Mask : 0b00000001 14 | --------------------------------- 15 | Op Flags : 0b00000010 16 | Allow 2.4GHz : 1 17 | Allow 5GHz : 0 18 | Disable 2.4GHz HT20 : 0 19 | Disable 2.4GHz HT40 : 0 20 | --------------------------------- 21 | EEP Misc : 0b00000000 22 | Big Endian : 0 23 | --------------------------------- 24 | RF Silent : 0 25 | BT Option : 0 26 | Device Cap : 0 27 | Device Type : 4 28 | Power Table Offset : 0 29 | Tuning Caps : 96 0 30 | --------------------------------- 31 | Feature Enable : 0b01111101 32 | Enable Tx Temp Comp : 1 33 | Enable Tx Volt Comp : 0 34 | Enable Fast Clock : 1 35 | Enable Doubling : 1 36 | Internal Regulator : 1 37 | Enable PAPRD Scale : 1 38 | Enable Tuning Caps : 1 39 | XPA Timing Ctrl : 0 40 | --------------------------------- 41 | Misc Configuration : 0b00000000 42 | Driver Strength : 0 43 | Thermometer : -1 44 | Chain Mask Reduce : 0 45 | Enable Quick Drop : 0 46 | Temp Slope Extension : 0 47 | Enable Bias Strength : 0 48 | --------------------------------- 49 | Write Enable GPIO : 3 50 | WLAN Disable GPIO : 0 51 | WLAN LED GPIO : 8 52 | Rx Band Select GPIO : 255 53 | Tx Gain : 1 54 | Rx Gain : 1 55 | SW Reg : 0x00000000 56 | ---------------------------------------------------------------------------------------- 57 | Ant Div Control : 9 58 | Future : 00 00 59 | --------------------------------- 60 | Misc Enable : 0b00000000 61 | TX Gain Cap : 0 62 | Uncompress Checksum : 0 63 | MinCCApwr 2.4GHz : 0 64 | ---------------------------------------------------------------------------------------- 65 | Calibration 2.4GHz : Chain0 Chain1 Chain2 66 | 67 | Frequency 0 : 2412[1] 68 | Ref Power 0 : -22 0 0 69 | Volt Meas 0 : 0 0 0 70 | Temp Meas 0 : 137 0 0 71 | RX Noisefloor Cal 0 : 0 0 0 72 | RX Noisefloor Pwr 0 : 0 0 0 73 | RX Temp Meas 0 : 0 0 0 74 | 75 | Frequency 1 : 2437[6] 76 | Ref Power 1 : -22 0 0 77 | Volt Meas 1 : 0 0 0 78 | Temp Meas 1 : 137 0 0 79 | RX Noisefloor Cal 1 : 0 0 0 80 | RX Noisefloor Pwr 1 : 0 0 0 81 | RX Temp Meas 1 : 0 0 0 82 | 83 | Frequency 2 : 2462[11] 84 | Ref Power 2 : -22 0 0 85 | Volt Meas 2 : 0 0 0 86 | Temp Meas 2 : 136 0 0 87 | RX Noisefloor Cal 2 : 0 0 0 88 | RX Noisefloor Pwr 2 : 0 0 0 89 | RX Temp Meas 2 : 0 0 0 90 | ---------------------------------------------------------------------------------------- 91 | Target 2.4GHz 11B : 1L-5L 5S 11L 11S 92 | 93 | Frequency 0 : 2412[1] 94 | Power 0 : 36 36 36 36 95 | 96 | Frequency 1 : 2472[13] 97 | Power 1 : 36 36 36 36 98 | ---------------------------------------------------------------------------------------- 99 | Target 2.4GHz 11G : 6-24 36 48 54 100 | 101 | Frequency 0 : 2412[1] 102 | Power 0 : 36 32 28 26 103 | 104 | Frequency 1 : 2437[6] 105 | Power 1 : 36 32 28 26 106 | 107 | Frequency 2 : 2472[13] 108 | Power 2 : 36 32 28 26 109 | ---------------------------------------------------------------------------------------- 110 | Target 2.4GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 111 | 112 | Frequency 0 : 2412[1] 113 | Power 0 : 36 32 28 26 24 22 26 26 22 20 26 26 22 20 114 | 115 | Frequency 1 : 2437[6] 116 | Power 1 : 36 32 28 26 24 22 26 26 22 20 26 26 22 20 117 | 118 | Frequency 2 : 2472[13] 119 | Power 2 : 36 32 28 26 24 22 26 26 22 20 26 26 22 20 120 | ---------------------------------------------------------------------------------------- 121 | Target 2.4GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 122 | 123 | Frequency 0 : 2412[1] 124 | Power 0 : 32 30 26 24 22 20 26 26 20 18 26 26 20 18 125 | 126 | Frequency 1 : 2437[6] 127 | Power 1 : 32 30 26 24 22 20 26 26 20 18 26 26 20 18 128 | 129 | Frequency 2 : 2472[13] 130 | Power 2 : 32 30 26 24 22 20 26 26 20 18 26 26 20 18 131 | ---------------------------------------------------------------------------------------- 132 | Regulatory 2.4GHz : FCC__11B FCC__11G FCC_HT20 FCC_HT40 MKK__11B MKK__11G MKK_HT20 MKK_HT40 ETSI_11B ETSI_11G ETSIHT20 ETSIHT40 133 | 134 | Frequency 0 : 2412[1] 2412[1] 2412[1] 2422[3] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2422[3] 135 | Power|Edge 0 : 30|1 29|1 29|1 26|1 60|0 60|0 60|0 60|0 36|1 36|1 36|1 36|1 136 | 137 | Frequency 1 : 2417[2] 2417[2] 2417[2] 2427[4] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2427[4] 138 | Power|Edge 1 : 30|1 36|1 36|1 30|1 60|1 60|1 60|1 60|1 36|1 36|1 36|1 36|1 139 | 140 | Frequency 2 : 2422[3] 2422[3] 2422[3] 2432[5] 2472[13] 2472[13] 2472[13] 2472[13] 2447[8] 2447[8] 2447[8] 2432[5] 141 | Power|Edge 2 : 30|1 36|1 36|1 30|1 60|0 60|0 60|0 60|0 36|1 36|1 36|1 36|1 142 | 143 | Frequency 3 : 2462[11] 2462[11] 2462[11] 2452[9] 2484[14] 2484[14] 2484[14] 2484[14] 2472[13] 2472[13] 2472[13] 2462[11] 144 | Power|Edge 3 : 30|0 29|0 29|0 26|0 60|1 60|1 60|1 60|1 36|0 36|0 36|0 36|0 145 | ---------------------------------------------------------------------------------------- 146 | 2.4GHz Modal Header : Chain0 Chain1 Chain2 147 | Ant. Control : 0x0150 0x0150 0x0150 148 | NF Threshold : -1 0 0 149 | xatten1DB : 0 0 0 150 | xatten1Margin : 0 0 0 151 | Temp Slope : 40 152 | Quick Drop : 0 153 | spur Frequency : 2464[11+] 0x00 0x00 0x00 0x00 154 | Ant. Common Control : 0x00000110 155 | Ant. Common Control2 : 0x00022222 156 | Ant. Gain : 0 157 | Switch Settle : 44 158 | Volt Slope : 0 159 | txEndToXpaOff : 0 160 | txEndToRxOn : 2 161 | XPA Bias Level : 0 162 | txFrameToDataStart : 14 163 | txFrameToPaOn : 14 164 | txFrameToXpaOn : 14 165 | txClip : 3 166 | ADC Desired Size : -30 167 | Thresh62 : 28 168 | PAPRD Rate Mask : 5S 11L 11S HT20_12 HT20_13 HT40_1_3_9_11_17_19 SCALE:6 169 | PAPRD Rate Mask HT40 : 6_24 36 48 54 1L_5L 5S 11L 11S HT20_0_8_16 HT20_1_3_9_11_17_19 HT20_4 HT20_5 HT20_6 HT20_7 HT20_12 HT20_13 HT20_14 HT20_15 HT20_20 HT20_21 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HT40_4 170 | switch com spdt : 0 171 | XLNA Bias Strength : 0 172 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 173 | Future Modal : 00 00 00 00 00 00 00 174 | ---------------------------------------------------------------------------------------- 175 | 176 | EEPROM 0x5000: 177 | ---------------------------------------------------------------------------------------- 178 | EEPROM Version : 255 179 | Template Version : 255 180 | MAC Address : FF FF FF FF FF FF 181 | Cust Data : FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 182 | ---------------------------------------------------------------------------------------- 183 | RegDomain1 : 65535 184 | RegDomain2 : 65535 185 | TX Mask : 0b00001111 186 | RX Mask : 0b00001111 187 | --------------------------------- 188 | Op Flags : 0b11111111 189 | Allow 2.4GHz : 1 190 | Allow 5GHz : 1 191 | Disable 2.4GHz HT20 : 1 192 | Disable 2.4GHz HT40 : 1 193 | Disable 5Ghz HT20 : 1 194 | Disable 5Ghz HT40 : 1 195 | --------------------------------- 196 | EEP Misc : 0b11111111 197 | Big Endian : 1 198 | --------------------------------- 199 | RF Silent : 255 200 | BT Option : 255 201 | Device Cap : 255 202 | Device Type : 255 203 | Power Table Offset : -1 204 | Tuning Caps : 255 255 205 | --------------------------------- 206 | Feature Enable : 0b11111111 207 | Enable Tx Temp Comp : 1 208 | Enable Tx Volt Comp : 1 209 | Enable Fast Clock : 1 210 | Enable Doubling : 1 211 | Internal Regulator : 1 212 | Enable PAPRD Scale : 1 213 | Enable Tuning Caps : 1 214 | XPA Timing Ctrl : 1 215 | --------------------------------- 216 | Misc Configuration : 0b11111111 217 | Driver Strength : 1 218 | Thermometer : 2 219 | Chain Mask Reduce : 1 220 | Enable Quick Drop : 1 221 | Temp Slope Extension : 1 222 | Enable Bias Strength : 1 223 | --------------------------------- 224 | Write Enable GPIO : 255 225 | WLAN Disable GPIO : 255 226 | WLAN LED GPIO : 255 227 | Rx Band Select GPIO : 255 228 | Tx Gain : 15 229 | Rx Gain : 15 230 | SW Reg : 0xFFFFFFFF 231 | ---------------------------------------------------------------------------------------- 232 | Ant Div Control : 255 233 | Future : FF FF 234 | --------------------------------- 235 | Misc Enable : 0b11111111 236 | TX Gain Cap : 1 237 | Uncompress Checksum : 1 238 | MinCCApwr 2.4GHz : 1 239 | MinCCApwr 5GHz : 1 240 | --------------------------------- 241 | Temp Slope Extension : -1 -1 -1 -1 -1 -1 -1 -1 242 | ---------------------------------------------------------------------------------------- 243 | Calibration 2.4GHz : Chain0 Chain1 Chain2 244 | 245 | Frequency 0 : 0xFF 246 | Ref Power 0 : -1 -1 -1 247 | Volt Meas 0 : 255 255 255 248 | Temp Meas 0 : 255 255 255 249 | RX Noisefloor Cal 0 : -1 -1 -1 250 | RX Noisefloor Pwr 0 : -1 -1 -1 251 | RX Temp Meas 0 : 255 255 255 252 | 253 | Frequency 1 : 0xFF 254 | Ref Power 1 : -1 -1 -1 255 | Volt Meas 1 : 255 255 255 256 | Temp Meas 1 : 255 255 255 257 | RX Noisefloor Cal 1 : -1 -1 -1 258 | RX Noisefloor Pwr 1 : -1 -1 -1 259 | RX Temp Meas 1 : 255 255 255 260 | 261 | Frequency 2 : 0xFF 262 | Ref Power 2 : -1 -1 -1 263 | Volt Meas 2 : 255 255 255 264 | Temp Meas 2 : 255 255 255 265 | RX Noisefloor Cal 2 : -1 -1 -1 266 | RX Noisefloor Pwr 2 : -1 -1 -1 267 | RX Temp Meas 2 : 255 255 255 268 | ---------------------------------------------------------------------------------------- 269 | Target 2.4GHz 11B : 1L-5L 5S 11L 11S 270 | 271 | Frequency 0 : 0xFF 272 | Power 0 : 255 255 255 255 273 | 274 | Frequency 1 : 0xFF 275 | Power 1 : 255 255 255 255 276 | ---------------------------------------------------------------------------------------- 277 | Target 2.4GHz 11G : 6-24 36 48 54 278 | 279 | Frequency 0 : 0xFF 280 | Power 0 : 255 255 255 255 281 | 282 | Frequency 1 : 0xFF 283 | Power 1 : 255 255 255 255 284 | 285 | Frequency 2 : 0xFF 286 | Power 2 : 255 255 255 255 287 | ---------------------------------------------------------------------------------------- 288 | Target 2.4GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 289 | 290 | Frequency 0 : 0xFF 291 | Power 0 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 292 | 293 | Frequency 1 : 0xFF 294 | Power 1 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 295 | 296 | Frequency 2 : 0xFF 297 | Power 2 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 298 | ---------------------------------------------------------------------------------------- 299 | Target 2.4GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 300 | 301 | Frequency 0 : 0xFF 302 | Power 0 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 303 | 304 | Frequency 1 : 0xFF 305 | Power 1 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 306 | 307 | Frequency 2 : 0xFF 308 | Power 2 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 309 | ---------------------------------------------------------------------------------------- 310 | Regulatory 2.4GHz : ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? 311 | 312 | Frequency 0 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 313 | Power|Edge 0 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 314 | 315 | Frequency 1 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 316 | Power|Edge 1 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 317 | 318 | Frequency 2 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 319 | Power|Edge 2 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 320 | 321 | Frequency 3 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 322 | Power|Edge 3 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 323 | ---------------------------------------------------------------------------------------- 324 | Calibration 5GHz : Chain0 Chain1 Chain2 325 | 326 | Frequency 0 : 0xFF 327 | Ref Power 0 : -1 -1 -1 328 | Volt Meas 0 : 255 255 255 329 | Temp Meas 0 : 255 255 255 330 | RX Noisefloor Cal 0 : -1 -1 -1 331 | RX Noisefloor Pwr 0 : -1 -1 -1 332 | RX Temp Meas 0 : 255 255 255 333 | 334 | Frequency 1 : 0xFF 335 | Ref Power 1 : -1 -1 -1 336 | Volt Meas 1 : 255 255 255 337 | Temp Meas 1 : 255 255 255 338 | RX Noisefloor Cal 1 : -1 -1 -1 339 | RX Noisefloor Pwr 1 : -1 -1 -1 340 | RX Temp Meas 1 : 255 255 255 341 | 342 | Frequency 2 : 0xFF 343 | Ref Power 2 : -1 -1 -1 344 | Volt Meas 2 : 255 255 255 345 | Temp Meas 2 : 255 255 255 346 | RX Noisefloor Cal 2 : -1 -1 -1 347 | RX Noisefloor Pwr 2 : -1 -1 -1 348 | RX Temp Meas 2 : 255 255 255 349 | 350 | Frequency 3 : 0xFF 351 | Ref Power 3 : -1 -1 -1 352 | Volt Meas 3 : 255 255 255 353 | Temp Meas 3 : 255 255 255 354 | RX Noisefloor Cal 3 : -1 -1 -1 355 | RX Noisefloor Pwr 3 : -1 -1 -1 356 | RX Temp Meas 3 : 255 255 255 357 | 358 | Frequency 4 : 0xFF 359 | Ref Power 4 : -1 -1 -1 360 | Volt Meas 4 : 255 255 255 361 | Temp Meas 4 : 255 255 255 362 | RX Noisefloor Cal 4 : -1 -1 -1 363 | RX Noisefloor Pwr 4 : -1 -1 -1 364 | RX Temp Meas 4 : 255 255 255 365 | 366 | Frequency 5 : 0xFF 367 | Ref Power 5 : -1 -1 -1 368 | Volt Meas 5 : 255 255 255 369 | Temp Meas 5 : 255 255 255 370 | RX Noisefloor Cal 5 : -1 -1 -1 371 | RX Noisefloor Pwr 5 : -1 -1 -1 372 | RX Temp Meas 5 : 255 255 255 373 | 374 | Frequency 6 : 0xFF 375 | Ref Power 6 : -1 -1 -1 376 | Volt Meas 6 : 255 255 255 377 | Temp Meas 6 : 255 255 255 378 | RX Noisefloor Cal 6 : -1 -1 -1 379 | RX Noisefloor Pwr 6 : -1 -1 -1 380 | RX Temp Meas 6 : 255 255 255 381 | 382 | Frequency 7 : 0xFF 383 | Ref Power 7 : -1 -1 -1 384 | Volt Meas 7 : 255 255 255 385 | Temp Meas 7 : 255 255 255 386 | RX Noisefloor Cal 7 : -1 -1 -1 387 | RX Noisefloor Pwr 7 : -1 -1 -1 388 | RX Temp Meas 7 : 255 255 255 389 | ---------------------------------------------------------------------------------------- 390 | Target 5GHz 11A : 6-24 36 48 54 391 | 392 | Frequency 0 : 0xFF 393 | Power 0 : 255 255 255 255 394 | 395 | Frequency 1 : 0xFF 396 | Power 1 : 255 255 255 255 397 | 398 | Frequency 2 : 0xFF 399 | Power 2 : 255 255 255 255 400 | 401 | Frequency 3 : 0xFF 402 | Power 3 : 255 255 255 255 403 | 404 | Frequency 4 : 0xFF 405 | Power 4 : 255 255 255 255 406 | 407 | Frequency 5 : 0xFF 408 | Power 5 : 255 255 255 255 409 | 410 | Frequency 6 : 0xFF 411 | Power 6 : 255 255 255 255 412 | 413 | Frequency 7 : 0xFF 414 | Power 7 : 255 255 255 255 415 | ---------------------------------------------------------------------------------------- 416 | Target 5GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 417 | 418 | Frequency 0 : 0xFF 419 | Power 0 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 420 | 421 | Frequency 1 : 0xFF 422 | Power 1 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 423 | 424 | Frequency 2 : 0xFF 425 | Power 2 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 426 | 427 | Frequency 3 : 0xFF 428 | Power 3 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 429 | 430 | Frequency 4 : 0xFF 431 | Power 4 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 432 | 433 | Frequency 5 : 0xFF 434 | Power 5 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 435 | 436 | Frequency 6 : 0xFF 437 | Power 6 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 438 | 439 | Frequency 7 : 0xFF 440 | Power 7 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 441 | ---------------------------------------------------------------------------------------- 442 | Target 5GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 443 | 444 | Frequency 0 : 0xFF 445 | Power 0 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 446 | 447 | Frequency 1 : 0xFF 448 | Power 1 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 449 | 450 | Frequency 2 : 0xFF 451 | Power 2 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 452 | 453 | Frequency 3 : 0xFF 454 | Power 3 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 455 | 456 | Frequency 4 : 0xFF 457 | Power 4 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 458 | 459 | Frequency 5 : 0xFF 460 | Power 5 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 461 | 462 | Frequency 6 : 0xFF 463 | Power 6 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 464 | 465 | Frequency 7 : 0xFF 466 | Power 7 : 255 255 255 255 255 255 255 255 255 255 255 255 255 255 467 | ---------------------------------------------------------------------------------------- 468 | Regulatory 5GHz : ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? ???__??? 469 | 470 | Frequency 0 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 471 | Power|Edge 0 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 472 | 473 | Frequency 1 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 474 | Power|Edge 1 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 475 | 476 | Frequency 2 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 477 | Power|Edge 2 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 478 | 479 | Frequency 3 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 480 | Power|Edge 3 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 481 | 482 | Frequency 4 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 483 | Power|Edge 4 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 484 | 485 | Frequency 5 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 486 | Power|Edge 5 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 487 | 488 | Frequency 6 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 489 | Power|Edge 6 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 490 | 491 | Frequency 7 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 492 | Power|Edge 7 : 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 63|3 493 | ---------------------------------------------------------------------------------------- 494 | 2.4GHz Modal Header : Chain0 Chain1 Chain2 495 | Ant. Control : 0xFFFF 0xFFFF 0xFFFF 496 | NF Threshold : -1 -1 -1 497 | xatten1DB : 255 255 255 498 | xatten1Margin : 255 255 255 499 | Temp Slope : -1 500 | Quick Drop : -1 501 | spur Frequency : 0xFF 0xFF 0xFF 0xFF 0xFF 502 | Ant. Common Control : 0xFFFFFFFF 503 | Ant. Common Control2 : 0xFFFFFFFF 504 | Ant. Gain : -1 505 | Switch Settle : 255 506 | Volt Slope : -1 507 | txEndToXpaOff : 255 508 | txEndToRxOn : 255 509 | XPA Bias Level : 255 510 | txFrameToDataStart : 255 511 | txFrameToPaOn : 255 512 | txFrameToXpaOn : 255 513 | txClip : 255 514 | ADC Desired Size : -1 515 | Thresh62 : 255 516 | PAPRD Rate Mask : 6_24 36 48 54 1L_5L 5S 11L 11S HT20_0_8_16 HT20_1_3_9_11_17_19 HT20_4 HT20_5 HT20_6 HT20_7 HT20_12 HT20_13 HT20_14 HT20_15 HT20_20 HT20_21 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HT40_4 SCALE:7 BIT28 BIT29 BIT30 BIT31 517 | PAPRD Rate Mask HT40 : 6_24 36 48 54 1L_5L 5S 11L 11S HT20_0_8_16 HT20_1_3_9_11_17_19 HT20_4 HT20_5 HT20_6 HT20_7 HT20_12 HT20_13 HT20_14 HT20_15 HT20_20 HT20_21 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HT40_4 BIT25 BIT26 BIT27 BIT28 BIT29 BIT30 BIT31 518 | switch com spdt : 65535 519 | XLNA Bias Strength : 255 520 | Reserved : FF FF FF FF FF FF FF FF FF FF FF 521 | Future Modal : FF FF FF FF FF FF FF 522 | ---------------------------------------------------------------------------------------- 523 | 5GHz Modal Header : Chain0 Chain1 Chain2 524 | Ant. Control : 0xFFFF 0xFFFF 0xFFFF 525 | NF Threshold : -1 -1 -1 526 | Range Chain : Low Mid High Low Mid High Low Mid High 527 | xatten1DB : 255 255 255 255 255 255 255 255 255 528 | xatten1Margin : 255 255 255 255 255 255 255 255 255 529 | Range : Low Mid High 530 | Temp Slope : -1 -1 -1 531 | Quick Drop : -1 -1 -1 532 | spur Frequency : 0xFF 0xFF 0xFF 0xFF 0xFF 533 | Ant. Common Control : 0xFFFFFFFF 534 | Ant. Common Control2 : 0xFFFFFFFF 535 | Ant. Gain : -1 536 | Switch Settle : 255 537 | Volt Slope : -1 538 | txEndToXpaOff : 255 539 | txEndToRxOn : 255 540 | XPA Bias Level : 255 541 | txFrameToDataStart : 255 542 | txFrameToPaOn : 255 543 | txFrameToXpaOn : 255 544 | txClip : 255 545 | ADC Desired Size : -1 546 | Thresh62 : 255 547 | PAPRD Rate Mask : 6_24 36 48 54 1L_5L 5S 11L 11S HT20_0_8_16 HT20_1_3_9_11_17_19 HT20_4 HT20_5 HT20_6 HT20_7 HT20_12 HT20_13 HT20_14 HT20_15 HT20_20 HT20_21 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HT40_4 HIGH_SCALE:7 LOW_SCALE_DIS MID_SCALE_DIS HIGH_SCALE_DIS BIT31 548 | PAPRD Rate Mask HT40 : 6_24 36 48 54 1L_5L 5S 11L 11S HT20_0_8_16 HT20_1_3_9_11_17_19 HT20_4 HT20_5 HT20_6 HT20_7 HT20_12 HT20_13 HT20_14 HT20_15 HT20_20 HT20_21 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HT40_4 LOW_SCALE:7 MID_SCALE:7 BIT31 549 | switch com spdt : 65535 550 | XLNA Bias Strength : 255 551 | Reserved : FF FF FF FF FF FF FF FF FF FF FF 552 | Future Modal : FF FF FF FF FF FF FF 553 | ---------------------------------------------------------------------------------------- 554 | Frequency : Low Mid High 555 | PAPRD Scale : <5400 >=5400 >=5700 556 | Other : 5180 5500 5785 557 | ---------------------------------------------------------------------------------------- 558 | 559 | -------------------------------------------------------------------------------- /ar9300_eeprom/dump/wdr3600_v1.1_2050500231_rev1.0_pl.txt: -------------------------------------------------------------------------------- 1 | Board not detected. 2 | 3 | EEPROM 0x1000: 4 | ---------------------------------------------------------------------------------------- 5 | EEPROM Version : 2 6 | Template Version : 2 7 | MAC Address : 00 02 03 04 05 06 8 | Cust Data : 00 30 3A 30 32 3A 30 33 3A 30 34 3A 30 35 3A 30 36 00 00 00 9 | ---------------------------------------------------------------------------------------- 10 | RegDomain1 : 0 11 | RegDomain2 : 31 12 | TX Mask : 0b00000011 13 | RX Mask : 0b00000011 14 | --------------------------------- 15 | Op Flags : 0b00000010 16 | Allow 2.4GHz : 1 17 | Allow 5GHz : 0 18 | Disable 2.4GHz HT20 : 0 19 | Disable 2.4GHz HT40 : 0 20 | --------------------------------- 21 | EEP Misc : 0b00000000 22 | Big Endian : 0 23 | --------------------------------- 24 | RF Silent : 0 25 | BT Option : 0 26 | Device Cap : 0 27 | Device Type : 4 28 | Power Table Offset : 0 29 | Tuning Caps : 48 0 30 | --------------------------------- 31 | Feature Enable : 0b01001101 32 | Enable Tx Temp Comp : 1 33 | Enable Tx Volt Comp : 0 34 | Enable Fast Clock : 1 35 | Enable Doubling : 1 36 | Internal Regulator : 0 37 | Enable PAPRD Scale : 0 38 | Enable Tuning Caps : 1 39 | XPA Timing Ctrl : 0 40 | --------------------------------- 41 | Misc Configuration : 0b00000010 42 | Driver Strength : 0 43 | Thermometer : 0 44 | Chain Mask Reduce : 0 45 | Enable Quick Drop : 0 46 | Temp Slope Extension : 0 47 | Enable Bias Strength : 0 48 | --------------------------------- 49 | Write Enable GPIO : 3 50 | WLAN Disable GPIO : 0 51 | WLAN LED GPIO : 8 52 | Rx Band Select GPIO : 255 53 | Tx Gain : 6 54 | Rx Gain : 0 55 | SW Reg : 0x00000001 56 | ---------------------------------------------------------------------------------------- 57 | Ant Div Control : 0 58 | Future : 00 00 59 | --------------------------------- 60 | Misc Enable : 0b00000000 61 | TX Gain Cap : 0 62 | Uncompress Checksum : 0 63 | MinCCApwr 2.4GHz : 0 64 | ---------------------------------------------------------------------------------------- 65 | Calibration 2.4GHz : Chain0 Chain1 Chain2 66 | 67 | Frequency 0 : 2412[1] 68 | Ref Power 0 : 9 14 0 69 | Volt Meas 0 : 0 0 0 70 | Temp Meas 0 : 128 132 0 71 | RX Noisefloor Cal 0 : 0 0 0 72 | RX Noisefloor Pwr 0 : 0 0 0 73 | RX Temp Meas 0 : 0 0 0 74 | 75 | Frequency 1 : 2437[6] 76 | Ref Power 1 : 9 14 0 77 | Volt Meas 1 : 0 0 0 78 | Temp Meas 1 : 129 132 0 79 | RX Noisefloor Cal 1 : 0 0 0 80 | RX Noisefloor Pwr 1 : 0 0 0 81 | RX Temp Meas 1 : 0 0 0 82 | 83 | Frequency 2 : 2462[11] 84 | Ref Power 2 : 8 14 0 85 | Volt Meas 2 : 0 0 0 86 | Temp Meas 2 : 129 132 0 87 | RX Noisefloor Cal 2 : 0 0 0 88 | RX Noisefloor Pwr 2 : 0 0 0 89 | RX Temp Meas 2 : 0 0 0 90 | ---------------------------------------------------------------------------------------- 91 | Target 2.4GHz 11B : 1L-5L 5S 11L 11S 92 | 93 | Frequency 0 : 2412[1] 94 | Power 0 : 38 38 38 38 95 | 96 | Frequency 1 : 2472[13] 97 | Power 1 : 38 38 38 38 98 | ---------------------------------------------------------------------------------------- 99 | Target 2.4GHz 11G : 6-24 36 48 54 100 | 101 | Frequency 0 : 2412[1] 102 | Power 0 : 38 38 36 32 103 | 104 | Frequency 1 : 2437[6] 105 | Power 1 : 38 38 36 32 106 | 107 | Frequency 2 : 2472[13] 108 | Power 2 : 38 38 36 32 109 | ---------------------------------------------------------------------------------------- 110 | Target 2.4GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 111 | 112 | Frequency 0 : 2412[1] 113 | Power 0 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 114 | 115 | Frequency 1 : 2437[6] 116 | Power 1 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 117 | 118 | Frequency 2 : 2472[13] 119 | Power 2 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 120 | ---------------------------------------------------------------------------------------- 121 | Target 2.4GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 122 | 123 | Frequency 0 : 2422[3] 124 | Power 0 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 125 | 126 | Frequency 1 : 2447[8] 127 | Power 1 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 128 | 129 | Frequency 2 : 2462[11] 130 | Power 2 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 131 | ---------------------------------------------------------------------------------------- 132 | Regulatory 2.4GHz : FCC__11B FCC__11G FCC_HT20 FCC_HT40 MKK__11B MKK__11G MKK_HT20 MKK_HT40 ETSI_11B ETSI_11G ETSIHT20 ETSIHT40 133 | 134 | Frequency 0 : 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 135 | Power|Edge 0 : 34|0 24|0 24|0 17|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 136 | 137 | Frequency 1 : 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 138 | Power|Edge 1 : 34|1 28|1 28|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 139 | 140 | Frequency 2 : 2462[11] 2462[11] 2462[11] 2462[11] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 141 | Power|Edge 2 : 34|0 26|0 26|0 21|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 142 | 143 | Frequency 3 : 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 144 | Power|Edge 3 : 34|1 26|1 26|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 145 | ---------------------------------------------------------------------------------------- 146 | 2.4GHz Modal Header : Chain0 Chain1 Chain2 147 | Ant. Control : 0x0010 0x0010 0x0010 148 | NF Threshold : -1 0 0 149 | xatten1DB : 26 26 26 150 | xatten1Margin : 17 17 17 151 | Temp Slope : 31 152 | Quick Drop : 0 153 | spur Frequency : 2464[11+] 0x00 0x00 0x00 0x00 154 | Ant. Common Control : 0x00000110 155 | Ant. Common Control2 : 0x000EEEEE 156 | Ant. Gain : 0 157 | Switch Settle : 44 158 | Volt Slope : 0 159 | txEndToXpaOff : 0 160 | txEndToRxOn : 2 161 | XPA Bias Level : 0 162 | txFrameToDataStart : 14 163 | txFrameToPaOn : 14 164 | txFrameToXpaOn : 14 165 | txClip : 3 166 | ADC Desired Size : -30 167 | Thresh62 : 28 168 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 SCALE:6 169 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 170 | switch com spdt : 0 171 | XLNA Bias Strength : 0 172 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 173 | Future Modal : 00 00 00 00 00 00 00 174 | ---------------------------------------------------------------------------------------- 175 | 176 | EEPROM 0x5000: 177 | ---------------------------------------------------------------------------------------- 178 | EEPROM Version : 2 179 | Template Version : 2 180 | MAC Address : 00 02 03 04 05 06 181 | Cust Data : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 182 | ---------------------------------------------------------------------------------------- 183 | RegDomain1 : 0 184 | RegDomain2 : 31 185 | TX Mask : 0b00000011 186 | RX Mask : 0b00000011 187 | --------------------------------- 188 | Op Flags : 0b00000001 189 | Allow 2.4GHz : 0 190 | Allow 5GHz : 1 191 | Disable 5Ghz HT20 : 0 192 | Disable 5Ghz HT40 : 0 193 | --------------------------------- 194 | EEP Misc : 0b00000000 195 | Big Endian : 0 196 | --------------------------------- 197 | RF Silent : 0 198 | BT Option : 0 199 | Device Cap : 0 200 | Device Type : 4 201 | Power Table Offset : 0 202 | Tuning Caps : 72 0 203 | --------------------------------- 204 | Feature Enable : 0b01001101 205 | Enable Tx Temp Comp : 1 206 | Enable Tx Volt Comp : 0 207 | Enable Fast Clock : 1 208 | Enable Doubling : 1 209 | Internal Regulator : 0 210 | Enable PAPRD Scale : 0 211 | Enable Tuning Caps : 1 212 | XPA Timing Ctrl : 0 213 | --------------------------------- 214 | Misc Configuration : 0b00000100 215 | Driver Strength : 0 216 | Thermometer : 1 217 | Chain Mask Reduce : 0 218 | Enable Quick Drop : 0 219 | Temp Slope Extension : 0 220 | Enable Bias Strength : 0 221 | --------------------------------- 222 | Write Enable GPIO : 3 223 | WLAN Disable GPIO : 0 224 | WLAN LED GPIO : 8 225 | Rx Band Select GPIO : 255 226 | Tx Gain : 0 227 | Rx Gain : 0 228 | SW Reg : 0x00000000 229 | ---------------------------------------------------------------------------------------- 230 | Ant Div Control : 0 231 | Future : 00 00 232 | --------------------------------- 233 | Misc Enable : 0b00000000 234 | TX Gain Cap : 0 235 | Uncompress Checksum : 0 236 | MinCCApwr 5GHz : 0 237 | --------------------------------- 238 | Temp Slope Extension : 0 0 0 0 0 0 0 0 239 | ---------------------------------------------------------------------------------------- 240 | Calibration 5GHz : Chain0 Chain1 Chain2 241 | 242 | Frequency 0 : 5180[36] 243 | Ref Power 0 : -12 -23 0 244 | Volt Meas 0 : 0 0 0 245 | Temp Meas 0 : 155 156 0 246 | RX Noisefloor Cal 0 : 0 0 0 247 | RX Noisefloor Pwr 0 : 0 0 0 248 | RX Temp Meas 0 : 0 0 0 249 | 250 | Frequency 1 : 5240[48] 251 | Ref Power 1 : -7 -17 0 252 | Volt Meas 1 : 0 0 0 253 | Temp Meas 1 : 155 155 0 254 | RX Noisefloor Cal 1 : 0 0 0 255 | RX Noisefloor Pwr 1 : 0 0 0 256 | RX Temp Meas 1 : 0 0 0 257 | 258 | Frequency 2 : 5320[64] 259 | Ref Power 2 : -1 -11 0 260 | Volt Meas 2 : 0 0 0 261 | Temp Meas 2 : 154 155 0 262 | RX Noisefloor Cal 2 : 0 0 0 263 | RX Noisefloor Pwr 2 : 0 0 0 264 | RX Temp Meas 2 : 0 0 0 265 | 266 | Frequency 3 : 5500[100] 267 | Ref Power 3 : 3 -5 0 268 | Volt Meas 3 : 0 0 0 269 | Temp Meas 3 : 154 155 0 270 | RX Noisefloor Cal 3 : 0 0 0 271 | RX Noisefloor Pwr 3 : 0 0 0 272 | RX Temp Meas 3 : 0 0 0 273 | 274 | Frequency 4 : 5620[124] 275 | Ref Power 4 : 2 -6 0 276 | Volt Meas 4 : 0 0 0 277 | Temp Meas 4 : 154 155 0 278 | RX Noisefloor Cal 4 : 0 0 0 279 | RX Noisefloor Pwr 4 : 0 0 0 280 | RX Temp Meas 4 : 0 0 0 281 | 282 | Frequency 5 : 5700[140] 283 | Ref Power 5 : -1 -9 0 284 | Volt Meas 5 : 0 0 0 285 | Temp Meas 5 : 154 154 0 286 | RX Noisefloor Cal 5 : 0 0 0 287 | RX Noisefloor Pwr 5 : 0 0 0 288 | RX Temp Meas 5 : 0 0 0 289 | 290 | Frequency 6 : 5745[149] 291 | Ref Power 6 : -4 -11 0 292 | Volt Meas 6 : 0 0 0 293 | Temp Meas 6 : 153 155 0 294 | RX Noisefloor Cal 6 : 0 0 0 295 | RX Noisefloor Pwr 6 : 0 0 0 296 | RX Temp Meas 6 : 0 0 0 297 | 298 | Frequency 7 : 5825[165] 299 | Ref Power 7 : -7 -17 0 300 | Volt Meas 7 : 0 0 0 301 | Temp Meas 7 : 154 155 0 302 | RX Noisefloor Cal 7 : 0 0 0 303 | RX Noisefloor Pwr 7 : 0 0 0 304 | RX Temp Meas 7 : 0 0 0 305 | ---------------------------------------------------------------------------------------- 306 | Target 5GHz 11A : 6-24 36 48 54 307 | 308 | Frequency 0 : 5180[36] 309 | Power 0 : 32 32 30 26 310 | 311 | Frequency 1 : 5240[48] 312 | Power 1 : 32 32 30 26 313 | 314 | Frequency 2 : 5320[64] 315 | Power 2 : 32 32 30 26 316 | 317 | Frequency 3 : 5400[64+] 318 | Power 3 : 32 32 30 26 319 | 320 | Frequency 4 : 5500[100] 321 | Power 4 : 32 32 30 26 322 | 323 | Frequency 5 : 5600[120] 324 | Power 5 : 32 32 30 24 325 | 326 | Frequency 6 : 5700[140] 327 | Power 6 : 32 32 30 24 328 | 329 | Frequency 7 : 5825[165] 330 | Power 7 : 32 32 30 24 331 | ---------------------------------------------------------------------------------------- 332 | Target 5GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 333 | 334 | Frequency 0 : 5180[36] 335 | Power 0 : 32 32 32 30 28 26 32 28 22 22 22 22 22 20 336 | 337 | Frequency 1 : 5220[44] 338 | Power 1 : 32 32 32 30 28 26 32 28 22 22 22 22 22 20 339 | 340 | Frequency 2 : 5320[64] 341 | Power 2 : 32 32 32 30 28 26 32 26 22 22 22 22 22 20 342 | 343 | Frequency 3 : 5500[100] 344 | Power 3 : 32 32 32 30 28 26 32 26 22 22 22 22 22 20 345 | 346 | Frequency 4 : 5600[120] 347 | Power 4 : 32 32 30 28 26 24 32 24 22 22 22 22 20 18 348 | 349 | Frequency 5 : 5700[140] 350 | Power 5 : 32 32 30 28 26 24 32 24 22 22 22 22 20 18 351 | 352 | Frequency 6 : 5745[149] 353 | Power 6 : 32 32 28 26 24 22 32 22 22 22 22 22 18 16 354 | 355 | Frequency 7 : 5825[165] 356 | Power 7 : 32 32 28 26 24 22 32 22 22 22 22 22 18 16 357 | ---------------------------------------------------------------------------------------- 358 | Target 5GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 359 | 360 | Frequency 0 : 5190[38] 361 | Power 0 : 32 32 30 28 28 24 32 28 22 22 24 22 20 18 362 | 363 | Frequency 1 : 5230[46] 364 | Power 1 : 32 32 30 28 28 24 32 28 22 22 24 22 20 18 365 | 366 | Frequency 2 : 5310[60+] 367 | Power 2 : 32 32 30 28 26 24 32 26 22 22 24 22 20 18 368 | 369 | Frequency 3 : 5510[100+] 370 | Power 3 : 32 32 30 28 26 22 32 26 22 22 24 22 18 16 371 | 372 | Frequency 4 : 5550[108+] 373 | Power 4 : 32 32 30 26 24 22 32 24 22 22 24 22 18 16 374 | 375 | Frequency 5 : 5670[132+] 376 | Power 5 : 32 32 30 26 24 22 32 24 22 22 24 22 18 16 377 | 378 | Frequency 6 : 5755[149+] 379 | Power 6 : 32 32 30 24 22 20 32 22 22 20 22 20 18 16 380 | 381 | Frequency 7 : 5795[157+] 382 | Power 7 : 32 32 30 24 22 20 32 22 22 20 22 20 18 16 383 | ---------------------------------------------------------------------------------------- 384 | Regulatory 5GHz : FCC__11A FCC_HT20 FCC_HT40 MKK__11A MKK_HT20 MKK_HT40 ETSI_11A ETSIHT20 ETSIHT40 385 | 386 | Frequency 0 : 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 387 | Power|Edge 0 : 24|0 24|0 18|0 60|0 60|0 60|0 18|0 18|0 18|0 388 | 389 | Frequency 1 : 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 390 | Power|Edge 1 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 391 | 392 | Frequency 2 : 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 393 | Power|Edge 2 : 24|0 24|0 24|0 60|0 60|0 60|0 18|0 18|0 18|0 394 | 395 | Frequency 3 : 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 396 | Power|Edge 3 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 397 | 398 | Frequency 4 : 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 399 | Power|Edge 4 : 24|0 24|0 24|0 60|0 60|0 60|0 32|0 32|0 32|0 400 | 401 | Frequency 5 : 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 402 | Power|Edge 5 : 24|1 24|1 24|1 60|1 60|1 60|1 32|1 32|1 32|1 403 | 404 | Frequency 6 :5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+] 405 | Power|Edge 6 : 30|0 30|0 30|0 60|0 60|0 60|0 32|0 32|0 32|0 406 | 407 | Frequency 7 : 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 408 | Power|Edge 7 : 30|1 30|1 30|1 60|1 60|1 60|1 32|1 32|1 32|1 409 | ---------------------------------------------------------------------------------------- 410 | 5GHz Modal Header : Chain0 Chain1 Chain2 411 | Ant. Control : 0x0010 0x0010 0x0010 412 | NF Threshold : -1 0 0 413 | Range Chain : Low Mid High Low Mid High Low Mid High 414 | xatten1DB : 21 25 28 22 25 27 21 25 24 415 | xatten1Margin : 11 18 11 11 18 11 11 18 11 416 | Range : Low Mid High 417 | Temp Slope : 65 78 86 418 | Quick Drop : 0 0 0 419 | spur Frequency : 5500[100] 0x00 0x00 0x00 0x00 420 | Ant. Common Control : 0x00000110 421 | Ant. Common Control2 : 0x00022222 422 | Ant. Gain : 0 423 | Switch Settle : 45 424 | Volt Slope : 0 425 | txEndToXpaOff : 0 426 | txEndToRxOn : 2 427 | XPA Bias Level : 15 428 | txFrameToDataStart : 14 429 | txFrameToPaOn : 14 430 | txFrameToXpaOn : 14 431 | txClip : 3 432 | ADC Desired Size : -30 433 | Thresh62 : 28 434 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HIGH_SCALE:6 435 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 LOW_SCALE:6 MID_SCALE:6 436 | switch com spdt : 0 437 | XLNA Bias Strength : 0 438 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 439 | Future Modal : 00 00 00 00 00 00 00 440 | ---------------------------------------------------------------------------------------- 441 | Frequency : Low Mid High 442 | PAPRD Scale : <5400 >=5400 >=5700 443 | Other : 5180 5500 5785 444 | ---------------------------------------------------------------------------------------- 445 | 446 | -------------------------------------------------------------------------------- /ar9300_eeprom/dump/wdr3600_v1.1_2050500272_rev1.3_pl.txt: -------------------------------------------------------------------------------- 1 | Board not detected. 2 | 3 | EEPROM 0x1000: 4 | ---------------------------------------------------------------------------------------- 5 | EEPROM Version : 2 6 | Template Version : 2 7 | MAC Address : 00 02 03 04 05 06 8 | Cust Data : 00 30 3A 30 32 3A 30 33 3A 30 34 3A 30 35 3A 30 36 00 00 00 9 | ---------------------------------------------------------------------------------------- 10 | RegDomain1 : 0 11 | RegDomain2 : 31 12 | TX Mask : 0b00000011 13 | RX Mask : 0b00000011 14 | --------------------------------- 15 | Op Flags : 0b00000010 16 | Allow 2.4GHz : 1 17 | Allow 5GHz : 0 18 | Disable 2.4GHz HT20 : 0 19 | Disable 2.4GHz HT40 : 0 20 | --------------------------------- 21 | EEP Misc : 0b00000000 22 | Big Endian : 0 23 | --------------------------------- 24 | RF Silent : 0 25 | BT Option : 0 26 | Device Cap : 0 27 | Device Type : 4 28 | Power Table Offset : 0 29 | Tuning Caps : 40 0 30 | --------------------------------- 31 | Feature Enable : 0b01001101 32 | Enable Tx Temp Comp : 1 33 | Enable Tx Volt Comp : 0 34 | Enable Fast Clock : 1 35 | Enable Doubling : 1 36 | Internal Regulator : 0 37 | Enable PAPRD Scale : 0 38 | Enable Tuning Caps : 1 39 | XPA Timing Ctrl : 0 40 | --------------------------------- 41 | Misc Configuration : 0b00000010 42 | Driver Strength : 0 43 | Thermometer : 0 44 | Chain Mask Reduce : 0 45 | Enable Quick Drop : 0 46 | Temp Slope Extension : 0 47 | Enable Bias Strength : 0 48 | --------------------------------- 49 | Write Enable GPIO : 3 50 | WLAN Disable GPIO : 0 51 | WLAN LED GPIO : 8 52 | Rx Band Select GPIO : 255 53 | Tx Gain : 6 54 | Rx Gain : 0 55 | SW Reg : 0x00000001 56 | ---------------------------------------------------------------------------------------- 57 | Ant Div Control : 0 58 | Future : 00 00 59 | --------------------------------- 60 | Misc Enable : 0b00000000 61 | TX Gain Cap : 0 62 | Uncompress Checksum : 0 63 | MinCCApwr 2.4GHz : 0 64 | ---------------------------------------------------------------------------------------- 65 | Calibration 2.4GHz : Chain0 Chain1 Chain2 66 | 67 | Frequency 0 : 2412[1] 68 | Ref Power 0 : 6 10 0 69 | Volt Meas 0 : 0 0 0 70 | Temp Meas 0 : 144 148 0 71 | RX Noisefloor Cal 0 : 0 0 0 72 | RX Noisefloor Pwr 0 : 0 0 0 73 | RX Temp Meas 0 : 0 0 0 74 | 75 | Frequency 1 : 2437[6] 76 | Ref Power 1 : 5 10 0 77 | Volt Meas 1 : 0 0 0 78 | Temp Meas 1 : 144 149 0 79 | RX Noisefloor Cal 1 : 0 0 0 80 | RX Noisefloor Pwr 1 : 0 0 0 81 | RX Temp Meas 1 : 0 0 0 82 | 83 | Frequency 2 : 2462[11] 84 | Ref Power 2 : 5 9 0 85 | Volt Meas 2 : 0 0 0 86 | Temp Meas 2 : 144 149 0 87 | RX Noisefloor Cal 2 : 0 0 0 88 | RX Noisefloor Pwr 2 : 0 0 0 89 | RX Temp Meas 2 : 0 0 0 90 | ---------------------------------------------------------------------------------------- 91 | Target 2.4GHz 11B : 1L-5L 5S 11L 11S 92 | 93 | Frequency 0 : 2412[1] 94 | Power 0 : 38 38 38 38 95 | 96 | Frequency 1 : 2472[13] 97 | Power 1 : 38 38 38 38 98 | ---------------------------------------------------------------------------------------- 99 | Target 2.4GHz 11G : 6-24 36 48 54 100 | 101 | Frequency 0 : 2412[1] 102 | Power 0 : 38 38 36 32 103 | 104 | Frequency 1 : 2437[6] 105 | Power 1 : 38 38 36 32 106 | 107 | Frequency 2 : 2472[13] 108 | Power 2 : 38 38 36 32 109 | ---------------------------------------------------------------------------------------- 110 | Target 2.4GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 111 | 112 | Frequency 0 : 2412[1] 113 | Power 0 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 114 | 115 | Frequency 1 : 2437[6] 116 | Power 1 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 117 | 118 | Frequency 2 : 2472[13] 119 | Power 2 : 36 36 36 34 32 30 36 33 32 28 32 32 28 20 120 | ---------------------------------------------------------------------------------------- 121 | Target 2.4GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 122 | 123 | Frequency 0 : 2422[3] 124 | Power 0 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 125 | 126 | Frequency 1 : 2447[8] 127 | Power 1 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 128 | 129 | Frequency 2 : 2462[11] 130 | Power 2 : 34 34 34 32 30 28 34 32 30 26 32 32 28 20 131 | ---------------------------------------------------------------------------------------- 132 | Regulatory 2.4GHz : FCC__11B FCC__11G FCC_HT20 FCC_HT40 MKK__11B MKK__11G MKK_HT20 MKK_HT40 ETSI_11B ETSI_11G ETSIHT20 ETSIHT40 133 | 134 | Frequency 0 : 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 135 | Power|Edge 0 : 34|0 24|0 24|0 17|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 136 | 137 | Frequency 1 : 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 138 | Power|Edge 1 : 34|1 28|1 28|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 139 | 140 | Frequency 2 : 2462[11] 2462[11] 2462[11] 2462[11] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 141 | Power|Edge 2 : 34|0 26|0 26|0 21|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 142 | 143 | Frequency 3 : 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 144 | Power|Edge 3 : 34|1 26|1 26|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 145 | ---------------------------------------------------------------------------------------- 146 | 2.4GHz Modal Header : Chain0 Chain1 Chain2 147 | Ant. Control : 0x0010 0x0010 0x0010 148 | NF Threshold : -1 0 0 149 | xatten1DB : 26 26 26 150 | xatten1Margin : 17 17 17 151 | Temp Slope : 31 152 | Quick Drop : 0 153 | spur Frequency : 2464[11+] 0x00 0x00 0x00 0x00 154 | Ant. Common Control : 0x00000110 155 | Ant. Common Control2 : 0x000EEEEE 156 | Ant. Gain : 0 157 | Switch Settle : 44 158 | Volt Slope : 0 159 | txEndToXpaOff : 0 160 | txEndToRxOn : 2 161 | XPA Bias Level : 0 162 | txFrameToDataStart : 14 163 | txFrameToPaOn : 14 164 | txFrameToXpaOn : 14 165 | txClip : 3 166 | ADC Desired Size : -30 167 | Thresh62 : 28 168 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 SCALE:6 169 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 170 | switch com spdt : 0 171 | XLNA Bias Strength : 0 172 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 173 | Future Modal : 00 00 00 00 00 00 00 174 | ---------------------------------------------------------------------------------------- 175 | 176 | EEPROM 0x5000: 177 | ---------------------------------------------------------------------------------------- 178 | EEPROM Version : 2 179 | Template Version : 2 180 | MAC Address : 00 02 03 04 05 06 181 | Cust Data : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 182 | ---------------------------------------------------------------------------------------- 183 | RegDomain1 : 0 184 | RegDomain2 : 31 185 | TX Mask : 0b00000011 186 | RX Mask : 0b00000011 187 | --------------------------------- 188 | Op Flags : 0b00000001 189 | Allow 2.4GHz : 0 190 | Allow 5GHz : 1 191 | Disable 5Ghz HT20 : 0 192 | Disable 5Ghz HT40 : 0 193 | --------------------------------- 194 | EEP Misc : 0b00000000 195 | Big Endian : 0 196 | --------------------------------- 197 | RF Silent : 0 198 | BT Option : 0 199 | Device Cap : 0 200 | Device Type : 4 201 | Power Table Offset : 0 202 | Tuning Caps : 72 0 203 | --------------------------------- 204 | Feature Enable : 0b01001101 205 | Enable Tx Temp Comp : 1 206 | Enable Tx Volt Comp : 0 207 | Enable Fast Clock : 1 208 | Enable Doubling : 1 209 | Internal Regulator : 0 210 | Enable PAPRD Scale : 0 211 | Enable Tuning Caps : 1 212 | XPA Timing Ctrl : 0 213 | --------------------------------- 214 | Misc Configuration : 0b00000100 215 | Driver Strength : 0 216 | Thermometer : 1 217 | Chain Mask Reduce : 0 218 | Enable Quick Drop : 0 219 | Temp Slope Extension : 0 220 | Enable Bias Strength : 0 221 | --------------------------------- 222 | Write Enable GPIO : 3 223 | WLAN Disable GPIO : 0 224 | WLAN LED GPIO : 8 225 | Rx Band Select GPIO : 255 226 | Tx Gain : 0 227 | Rx Gain : 0 228 | SW Reg : 0x00000000 229 | ---------------------------------------------------------------------------------------- 230 | Ant Div Control : 0 231 | Future : 00 00 232 | --------------------------------- 233 | Misc Enable : 0b00000000 234 | TX Gain Cap : 0 235 | Uncompress Checksum : 0 236 | MinCCApwr 5GHz : 0 237 | --------------------------------- 238 | Temp Slope Extension : 0 0 0 0 0 0 0 0 239 | ---------------------------------------------------------------------------------------- 240 | Calibration 5GHz : Chain0 Chain1 Chain2 241 | 242 | Frequency 0 : 5180[36] 243 | Ref Power 0 : -14 -21 0 244 | Volt Meas 0 : 0 0 0 245 | Temp Meas 0 : 146 146 0 246 | RX Noisefloor Cal 0 : 0 0 0 247 | RX Noisefloor Pwr 0 : 0 0 0 248 | RX Temp Meas 0 : 0 0 0 249 | 250 | Frequency 1 : 5240[48] 251 | Ref Power 1 : -10 -14 0 252 | Volt Meas 1 : 0 0 0 253 | Temp Meas 1 : 146 146 0 254 | RX Noisefloor Cal 1 : 0 0 0 255 | RX Noisefloor Pwr 1 : 0 0 0 256 | RX Temp Meas 1 : 0 0 0 257 | 258 | Frequency 2 : 5320[64] 259 | Ref Power 2 : -6 -11 0 260 | Volt Meas 2 : 0 0 0 261 | Temp Meas 2 : 145 146 0 262 | RX Noisefloor Cal 2 : 0 0 0 263 | RX Noisefloor Pwr 2 : 0 0 0 264 | RX Temp Meas 2 : 0 0 0 265 | 266 | Frequency 3 : 5500[100] 267 | Ref Power 3 : -1 -5 0 268 | Volt Meas 3 : 0 0 0 269 | Temp Meas 3 : 146 146 0 270 | RX Noisefloor Cal 3 : 0 0 0 271 | RX Noisefloor Pwr 3 : 0 0 0 272 | RX Temp Meas 3 : 0 0 0 273 | 274 | Frequency 4 : 5620[124] 275 | Ref Power 4 : -2 -5 0 276 | Volt Meas 4 : 0 0 0 277 | Temp Meas 4 : 146 146 0 278 | RX Noisefloor Cal 4 : 0 0 0 279 | RX Noisefloor Pwr 4 : 0 0 0 280 | RX Temp Meas 4 : 0 0 0 281 | 282 | Frequency 5 : 5700[140] 283 | Ref Power 5 : -5 -8 0 284 | Volt Meas 5 : 0 0 0 285 | Temp Meas 5 : 147 147 0 286 | RX Noisefloor Cal 5 : 0 0 0 287 | RX Noisefloor Pwr 5 : 0 0 0 288 | RX Temp Meas 5 : 0 0 0 289 | 290 | Frequency 6 : 5745[149] 291 | Ref Power 6 : -6 -10 0 292 | Volt Meas 6 : 0 0 0 293 | Temp Meas 6 : 146 146 0 294 | RX Noisefloor Cal 6 : 0 0 0 295 | RX Noisefloor Pwr 6 : 0 0 0 296 | RX Temp Meas 6 : 0 0 0 297 | 298 | Frequency 7 : 5825[165] 299 | Ref Power 7 : -10 -14 0 300 | Volt Meas 7 : 0 0 0 301 | Temp Meas 7 : 146 146 0 302 | RX Noisefloor Cal 7 : 0 0 0 303 | RX Noisefloor Pwr 7 : 0 0 0 304 | RX Temp Meas 7 : 0 0 0 305 | ---------------------------------------------------------------------------------------- 306 | Target 5GHz 11A : 6-24 36 48 54 307 | 308 | Frequency 0 : 5180[36] 309 | Power 0 : 32 32 30 26 310 | 311 | Frequency 1 : 5240[48] 312 | Power 1 : 32 32 30 26 313 | 314 | Frequency 2 : 5320[64] 315 | Power 2 : 32 32 30 26 316 | 317 | Frequency 3 : 5400[64+] 318 | Power 3 : 32 32 30 26 319 | 320 | Frequency 4 : 5500[100] 321 | Power 4 : 32 32 30 26 322 | 323 | Frequency 5 : 5600[120] 324 | Power 5 : 32 32 30 24 325 | 326 | Frequency 6 : 5700[140] 327 | Power 6 : 32 32 30 24 328 | 329 | Frequency 7 : 5825[165] 330 | Power 7 : 32 32 30 24 331 | ---------------------------------------------------------------------------------------- 332 | Target 5GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 333 | 334 | Frequency 0 : 5180[36] 335 | Power 0 : 32 32 32 30 28 26 32 28 22 22 22 22 22 20 336 | 337 | Frequency 1 : 5220[44] 338 | Power 1 : 32 32 32 30 28 26 32 28 22 22 22 22 22 20 339 | 340 | Frequency 2 : 5320[64] 341 | Power 2 : 32 32 32 30 28 26 32 26 22 22 22 22 22 20 342 | 343 | Frequency 3 : 5500[100] 344 | Power 3 : 32 32 32 30 28 26 32 26 22 22 22 22 22 20 345 | 346 | Frequency 4 : 5600[120] 347 | Power 4 : 32 32 30 28 26 24 32 24 22 22 22 22 20 18 348 | 349 | Frequency 5 : 5700[140] 350 | Power 5 : 32 32 30 28 26 24 32 24 22 22 22 22 20 18 351 | 352 | Frequency 6 : 5745[149] 353 | Power 6 : 32 32 28 26 24 22 32 22 22 22 22 22 18 16 354 | 355 | Frequency 7 : 5825[165] 356 | Power 7 : 32 32 28 26 24 22 32 22 22 22 22 22 18 16 357 | ---------------------------------------------------------------------------------------- 358 | Target 5GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 359 | 360 | Frequency 0 : 5190[38] 361 | Power 0 : 32 32 30 28 28 24 32 28 22 22 24 22 20 18 362 | 363 | Frequency 1 : 5230[46] 364 | Power 1 : 32 32 30 28 28 24 32 28 22 22 24 22 20 18 365 | 366 | Frequency 2 : 5310[60+] 367 | Power 2 : 32 32 30 28 26 24 32 26 22 22 24 22 20 18 368 | 369 | Frequency 3 : 5510[100+] 370 | Power 3 : 32 32 30 28 26 22 32 26 22 22 24 22 18 16 371 | 372 | Frequency 4 : 5550[108+] 373 | Power 4 : 32 32 30 26 24 22 32 24 22 22 24 22 18 16 374 | 375 | Frequency 5 : 5670[132+] 376 | Power 5 : 32 32 30 26 24 22 32 24 22 22 24 22 18 16 377 | 378 | Frequency 6 : 5755[149+] 379 | Power 6 : 32 32 30 24 22 20 32 22 22 20 22 20 18 16 380 | 381 | Frequency 7 : 5795[157+] 382 | Power 7 : 32 32 30 24 22 20 32 22 22 20 22 20 18 16 383 | ---------------------------------------------------------------------------------------- 384 | Regulatory 5GHz : FCC__11A FCC_HT20 FCC_HT40 MKK__11A MKK_HT20 MKK_HT40 ETSI_11A ETSIHT20 ETSIHT40 385 | 386 | Frequency 0 : 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 387 | Power|Edge 0 : 24|0 24|0 18|0 60|0 60|0 60|0 18|0 18|0 18|0 388 | 389 | Frequency 1 : 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 390 | Power|Edge 1 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 391 | 392 | Frequency 2 : 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 393 | Power|Edge 2 : 24|0 24|0 24|0 60|0 60|0 60|0 18|0 18|0 18|0 394 | 395 | Frequency 3 : 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 396 | Power|Edge 3 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 397 | 398 | Frequency 4 : 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 399 | Power|Edge 4 : 24|0 24|0 24|0 60|0 60|0 60|0 32|0 32|0 32|0 400 | 401 | Frequency 5 : 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 402 | Power|Edge 5 : 24|1 24|1 24|1 60|1 60|1 60|1 32|1 32|1 32|1 403 | 404 | Frequency 6 :5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+] 405 | Power|Edge 6 : 30|0 30|0 30|0 60|0 60|0 60|0 32|0 32|0 32|0 406 | 407 | Frequency 7 : 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 408 | Power|Edge 7 : 30|1 30|1 30|1 60|1 60|1 60|1 32|1 32|1 32|1 409 | ---------------------------------------------------------------------------------------- 410 | 5GHz Modal Header : Chain0 Chain1 Chain2 411 | Ant. Control : 0x0010 0x0010 0x0010 412 | NF Threshold : -1 0 0 413 | Range Chain : Low Mid High Low Mid High Low Mid High 414 | xatten1DB : 21 25 28 22 25 27 21 25 24 415 | xatten1Margin : 11 18 11 11 18 11 11 18 11 416 | Range : Low Mid High 417 | Temp Slope : 65 78 86 418 | Quick Drop : 0 0 0 419 | spur Frequency : 5500[100] 0x00 0x00 0x00 0x00 420 | Ant. Common Control : 0x00000110 421 | Ant. Common Control2 : 0x00022222 422 | Ant. Gain : 0 423 | Switch Settle : 45 424 | Volt Slope : 0 425 | txEndToXpaOff : 0 426 | txEndToRxOn : 2 427 | XPA Bias Level : 15 428 | txFrameToDataStart : 14 429 | txFrameToPaOn : 14 430 | txFrameToXpaOn : 14 431 | txClip : 3 432 | ADC Desired Size : -30 433 | Thresh62 : 28 434 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HIGH_SCALE:6 435 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 LOW_SCALE:6 MID_SCALE:6 436 | switch com spdt : 0 437 | XLNA Bias Strength : 0 438 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 439 | Future Modal : 00 00 00 00 00 00 00 440 | ---------------------------------------------------------------------------------------- 441 | Frequency : Low Mid High 442 | PAPRD Scale : <5400 >=5400 >=5700 443 | Other : 5180 5500 5785 444 | ---------------------------------------------------------------------------------------- 445 | 446 | -------------------------------------------------------------------------------- /ar9300_eeprom/dump/wdr4310_v1.0_2050500271_rev1.3_cn.txt: -------------------------------------------------------------------------------- 1 | Hardware: TL-WDR3600/4300/4310 Model: TL-WDR4310 ver. 1.0 Board: 2050500271 rev. 1.3 2 | 3 | EEPROM 0x1000: 4 | ---------------------------------------------------------------------------------------- 5 | EEPROM Version : 2 6 | Template Version : 2 7 | MAC Address : 00 02 03 04 05 06 8 | Cust Data : 00 30 3A 30 32 3A 30 33 3A 30 34 3A 30 35 3A 30 36 00 00 00 9 | ---------------------------------------------------------------------------------------- 10 | RegDomain1 : 0 11 | RegDomain2 : 31 12 | TX Mask : 0b00000011 13 | RX Mask : 0b00000011 14 | --------------------------------- 15 | Op Flags : 0b00000010 16 | Allow 2.4GHz : 1 17 | Allow 5GHz : 0 18 | Disable 2.4GHz HT20 : 0 19 | Disable 2.4GHz HT40 : 0 20 | --------------------------------- 21 | EEP Misc : 0b00000000 22 | Big Endian : 0 23 | --------------------------------- 24 | RF Silent : 0 25 | BT Option : 0 26 | Device Cap : 0 27 | Device Type : 4 28 | Power Table Offset : 0 29 | Tuning Caps : 48 0 30 | --------------------------------- 31 | Feature Enable : 0b01001101 32 | Enable Tx Temp Comp : 1 33 | Enable Tx Volt Comp : 0 34 | Enable Fast Clock : 1 35 | Enable Doubling : 1 36 | Internal Regulator : 0 37 | Enable PAPRD Scale : 0 38 | Enable Tuning Caps : 1 39 | XPA Timing Ctrl : 0 40 | --------------------------------- 41 | Misc Configuration : 0b00000010 42 | Driver Strength : 0 43 | Thermometer : 0 44 | Chain Mask Reduce : 0 45 | Enable Quick Drop : 0 46 | Temp Slope Extension : 0 47 | Enable Bias Strength : 0 48 | --------------------------------- 49 | Write Enable GPIO : 3 50 | WLAN Disable GPIO : 0 51 | WLAN LED GPIO : 8 52 | Rx Band Select GPIO : 255 53 | Tx Gain : 6 54 | Rx Gain : 0 55 | SW Reg : 0x00000001 56 | ---------------------------------------------------------------------------------------- 57 | Ant Div Control : 0 58 | Future : 00 00 59 | --------------------------------- 60 | Misc Enable : 0b00000000 61 | TX Gain Cap : 0 62 | Uncompress Checksum : 0 63 | MinCCApwr 2.4GHz : 0 64 | ---------------------------------------------------------------------------------------- 65 | Calibration 2.4GHz : Chain0 Chain1 Chain2 66 | 67 | Frequency 0 : 2412[1] 68 | Ref Power 0 : 11 12 0 69 | Volt Meas 0 : 0 0 0 70 | Temp Meas 0 : 157 162 0 71 | RX Noisefloor Cal 0 : 0 0 0 72 | RX Noisefloor Pwr 0 : 0 0 0 73 | RX Temp Meas 0 : 0 0 0 74 | 75 | Frequency 1 : 2437[6] 76 | Ref Power 1 : 11 13 0 77 | Volt Meas 1 : 0 0 0 78 | Temp Meas 1 : 158 162 0 79 | RX Noisefloor Cal 1 : 0 0 0 80 | RX Noisefloor Pwr 1 : 0 0 0 81 | RX Temp Meas 1 : 0 0 0 82 | 83 | Frequency 2 : 2462[11] 84 | Ref Power 2 : 10 13 0 85 | Volt Meas 2 : 0 0 0 86 | Temp Meas 2 : 158 162 0 87 | RX Noisefloor Cal 2 : 0 0 0 88 | RX Noisefloor Pwr 2 : 0 0 0 89 | RX Temp Meas 2 : 0 0 0 90 | ---------------------------------------------------------------------------------------- 91 | Target 2.4GHz 11B : 1L-5L 5S 11L 11S 92 | 93 | Frequency 0 : 2412[1] 94 | Power 0 : 42 42 42 42 95 | 96 | Frequency 1 : 2472[13] 97 | Power 1 : 42 42 42 42 98 | ---------------------------------------------------------------------------------------- 99 | Target 2.4GHz 11G : 6-24 36 48 54 100 | 101 | Frequency 0 : 2412[1] 102 | Power 0 : 42 42 40 36 103 | 104 | Frequency 1 : 2437[6] 105 | Power 1 : 42 42 40 36 106 | 107 | Frequency 2 : 2472[13] 108 | Power 2 : 42 42 40 36 109 | ---------------------------------------------------------------------------------------- 110 | Target 2.4GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 111 | 112 | Frequency 0 : 2412[1] 113 | Power 0 : 40 40 40 38 36 34 40 37 36 32 32 32 28 20 114 | 115 | Frequency 1 : 2437[6] 116 | Power 1 : 40 40 40 38 36 34 40 37 36 32 32 32 28 20 117 | 118 | Frequency 2 : 2472[13] 119 | Power 2 : 40 40 40 38 36 34 40 37 36 32 32 32 28 20 120 | ---------------------------------------------------------------------------------------- 121 | Target 2.4GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 122 | 123 | Frequency 0 : 2422[3] 124 | Power 0 : 38 38 38 36 34 32 38 36 34 30 32 32 28 20 125 | 126 | Frequency 1 : 2447[8] 127 | Power 1 : 38 38 38 36 34 32 38 36 34 30 32 32 28 20 128 | 129 | Frequency 2 : 2462[11] 130 | Power 2 : 38 38 38 36 34 32 38 36 34 30 32 32 28 20 131 | ---------------------------------------------------------------------------------------- 132 | Regulatory 2.4GHz : FCC__11B FCC__11G FCC_HT20 FCC_HT40 MKK__11B MKK__11G MKK_HT20 MKK_HT40 ETSI_11B ETSI_11G ETSIHT20 ETSIHT40 133 | 134 | Frequency 0 : 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 2412[1] 135 | Power|Edge 0 : 34|0 24|0 24|0 17|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 136 | 137 | Frequency 1 : 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 2417[2] 138 | Power|Edge 1 : 34|1 28|1 28|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 139 | 140 | Frequency 2 : 2462[11] 2462[11] 2462[11] 2462[11] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 2472[13] 141 | Power|Edge 2 : 34|0 26|0 26|0 21|0 60|0 60|0 60|0 60|0 29|0 29|0 29|0 29|0 142 | 143 | Frequency 3 : 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 2484[14] 144 | Power|Edge 3 : 34|1 26|1 26|1 21|1 60|1 60|1 60|1 60|1 29|1 29|1 29|1 29|1 145 | ---------------------------------------------------------------------------------------- 146 | 2.4GHz Modal Header : Chain0 Chain1 Chain2 147 | Ant. Control : 0x0010 0x0010 0x0010 148 | NF Threshold : -1 0 0 149 | xatten1DB : 26 26 26 150 | xatten1Margin : 17 17 17 151 | Temp Slope : 31 152 | Quick Drop : 0 153 | spur Frequency : 2464[11+] 0x00 0x00 0x00 0x00 154 | Ant. Common Control : 0x00000110 155 | Ant. Common Control2 : 0x000EEEEE 156 | Ant. Gain : 0 157 | Switch Settle : 44 158 | Volt Slope : 0 159 | txEndToXpaOff : 0 160 | txEndToRxOn : 2 161 | XPA Bias Level : 0 162 | txFrameToDataStart : 14 163 | txFrameToPaOn : 14 164 | txFrameToXpaOn : 14 165 | txClip : 3 166 | ADC Desired Size : -30 167 | Thresh62 : 28 168 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 SCALE:6 169 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 170 | switch com spdt : 0 171 | XLNA Bias Strength : 0 172 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 173 | Future Modal : 00 00 00 00 00 00 00 174 | ---------------------------------------------------------------------------------------- 175 | 176 | EEPROM 0x5000: 177 | ---------------------------------------------------------------------------------------- 178 | EEPROM Version : 2 179 | Template Version : 2 180 | MAC Address : 00 02 03 04 05 06 181 | Cust Data : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 182 | ---------------------------------------------------------------------------------------- 183 | RegDomain1 : 0 184 | RegDomain2 : 31 185 | TX Mask : 0b00000111 186 | RX Mask : 0b00000111 187 | --------------------------------- 188 | Op Flags : 0b00000001 189 | Allow 2.4GHz : 0 190 | Allow 5GHz : 1 191 | Disable 5Ghz HT20 : 0 192 | Disable 5Ghz HT40 : 0 193 | --------------------------------- 194 | EEP Misc : 0b00000000 195 | Big Endian : 0 196 | --------------------------------- 197 | RF Silent : 0 198 | BT Option : 0 199 | Device Cap : 0 200 | Device Type : 4 201 | Power Table Offset : 0 202 | Tuning Caps : 72 0 203 | --------------------------------- 204 | Feature Enable : 0b01001101 205 | Enable Tx Temp Comp : 1 206 | Enable Tx Volt Comp : 0 207 | Enable Fast Clock : 1 208 | Enable Doubling : 1 209 | Internal Regulator : 0 210 | Enable PAPRD Scale : 0 211 | Enable Tuning Caps : 1 212 | XPA Timing Ctrl : 0 213 | --------------------------------- 214 | Misc Configuration : 0b00000100 215 | Driver Strength : 0 216 | Thermometer : 1 217 | Chain Mask Reduce : 0 218 | Enable Quick Drop : 0 219 | Temp Slope Extension : 0 220 | Enable Bias Strength : 0 221 | --------------------------------- 222 | Write Enable GPIO : 3 223 | WLAN Disable GPIO : 0 224 | WLAN LED GPIO : 8 225 | Rx Band Select GPIO : 255 226 | Tx Gain : 0 227 | Rx Gain : 0 228 | SW Reg : 0x00000000 229 | ---------------------------------------------------------------------------------------- 230 | Ant Div Control : 0 231 | Future : 00 00 232 | --------------------------------- 233 | Misc Enable : 0b00000000 234 | TX Gain Cap : 0 235 | Uncompress Checksum : 0 236 | MinCCApwr 5GHz : 0 237 | --------------------------------- 238 | Temp Slope Extension : 0 0 0 0 0 0 0 0 239 | ---------------------------------------------------------------------------------------- 240 | Calibration 5GHz : Chain0 Chain1 Chain2 241 | 242 | Frequency 0 : 5745[149] 243 | Ref Power 0 : -16 -19 -17 244 | Volt Meas 0 : 0 0 0 245 | Temp Meas 0 : 175 176 177 246 | RX Noisefloor Cal 0 : 0 0 0 247 | RX Noisefloor Pwr 0 : 0 0 0 248 | RX Temp Meas 0 : 0 0 0 249 | 250 | Frequency 1 : 5825[165] 251 | Ref Power 1 : -22 -25 -24 252 | Volt Meas 1 : 0 0 0 253 | Temp Meas 1 : 177 177 177 254 | RX Noisefloor Cal 1 : 0 0 0 255 | RX Noisefloor Pwr 1 : 0 0 0 256 | RX Temp Meas 1 : 0 0 0 257 | 258 | Frequency 2 : 5320[64] 259 | Ref Power 2 : 0 0 0 260 | Volt Meas 2 : 0 0 0 261 | Temp Meas 2 : 0 0 0 262 | RX Noisefloor Cal 2 : 0 0 0 263 | RX Noisefloor Pwr 2 : 0 0 0 264 | RX Temp Meas 2 : 0 0 0 265 | 266 | Frequency 3 : 5400[64+] 267 | Ref Power 3 : 0 0 0 268 | Volt Meas 3 : 0 0 0 269 | Temp Meas 3 : 0 0 0 270 | RX Noisefloor Cal 3 : 0 0 0 271 | RX Noisefloor Pwr 3 : 0 0 0 272 | RX Temp Meas 3 : 0 0 0 273 | 274 | Frequency 4 : 5500[100] 275 | Ref Power 4 : 0 0 0 276 | Volt Meas 4 : 0 0 0 277 | Temp Meas 4 : 0 0 0 278 | RX Noisefloor Cal 4 : 0 0 0 279 | RX Noisefloor Pwr 4 : 0 0 0 280 | RX Temp Meas 4 : 0 0 0 281 | 282 | Frequency 5 : 5600[120] 283 | Ref Power 5 : 0 0 0 284 | Volt Meas 5 : 0 0 0 285 | Temp Meas 5 : 0 0 0 286 | RX Noisefloor Cal 5 : 0 0 0 287 | RX Noisefloor Pwr 5 : 0 0 0 288 | RX Temp Meas 5 : 0 0 0 289 | 290 | Frequency 6 : 5725[140+] 291 | Ref Power 6 : 0 0 0 292 | Volt Meas 6 : 0 0 0 293 | Temp Meas 6 : 0 0 0 294 | RX Noisefloor Cal 6 : 0 0 0 295 | RX Noisefloor Pwr 6 : 0 0 0 296 | RX Temp Meas 6 : 0 0 0 297 | 298 | Frequency 7 : 5825[165] 299 | Ref Power 7 : 0 0 0 300 | Volt Meas 7 : 0 0 0 301 | Temp Meas 7 : 0 0 0 302 | RX Noisefloor Cal 7 : 0 0 0 303 | RX Noisefloor Pwr 7 : 0 0 0 304 | RX Temp Meas 7 : 0 0 0 305 | ---------------------------------------------------------------------------------------- 306 | Target 5GHz 11A : 6-24 36 48 54 307 | 308 | Frequency 0 : 5180[36] 309 | Power 0 : 36 36 34 30 310 | 311 | Frequency 1 : 5240[48] 312 | Power 1 : 36 36 34 30 313 | 314 | Frequency 2 : 5320[64] 315 | Power 2 : 36 36 34 30 316 | 317 | Frequency 3 : 5400[64+] 318 | Power 3 : 36 36 34 30 319 | 320 | Frequency 4 : 5500[100] 321 | Power 4 : 36 36 34 30 322 | 323 | Frequency 5 : 5600[120] 324 | Power 5 : 36 36 34 28 325 | 326 | Frequency 6 : 5700[140] 327 | Power 6 : 36 36 34 28 328 | 329 | Frequency 7 : 5825[165] 330 | Power 7 : 36 36 34 28 331 | ---------------------------------------------------------------------------------------- 332 | Target 5GHz HT20 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 333 | 334 | Frequency 0 : 5180[36] 335 | Power 0 : 36 36 36 34 32 30 36 32 28 28 28 28 28 24 336 | 337 | Frequency 1 : 5220[44] 338 | Power 1 : 36 36 36 34 32 30 36 32 28 28 28 28 28 24 339 | 340 | Frequency 2 : 5320[64] 341 | Power 2 : 36 36 36 34 32 30 36 32 28 28 28 28 28 24 342 | 343 | Frequency 3 : 5500[100] 344 | Power 3 : 36 36 36 34 32 30 36 32 28 28 28 28 28 24 345 | 346 | Frequency 4 : 5600[120] 347 | Power 4 : 36 36 34 32 30 28 36 28 28 28 28 28 26 24 348 | 349 | Frequency 5 : 5700[140] 350 | Power 5 : 36 36 34 32 30 28 36 28 28 28 28 28 26 24 351 | 352 | Frequency 6 : 5745[149] 353 | Power 6 : 36 36 32 30 28 26 36 26 26 26 26 26 24 22 354 | 355 | Frequency 7 : 5825[165] 356 | Power 7 : 36 36 32 30 28 26 36 26 26 26 26 26 24 22 357 | ---------------------------------------------------------------------------------------- 358 | Target 5GHz HT40 :0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23 359 | 360 | Frequency 0 : 5190[38] 361 | Power 0 : 36 36 34 32 32 28 36 32 26 26 28 26 24 22 362 | 363 | Frequency 1 : 5230[46] 364 | Power 1 : 36 36 34 32 32 28 36 32 26 26 28 26 24 22 365 | 366 | Frequency 2 : 5310[60+] 367 | Power 2 : 36 36 34 32 32 28 36 32 26 26 28 26 24 22 368 | 369 | Frequency 3 : 5510[100+] 370 | Power 3 : 36 36 34 32 32 28 36 32 26 26 28 26 24 22 371 | 372 | Frequency 4 : 5550[108+] 373 | Power 4 : 36 36 34 30 30 28 36 32 26 26 28 26 22 20 374 | 375 | Frequency 5 : 5670[132+] 376 | Power 5 : 36 36 34 30 30 28 36 32 26 26 28 26 22 20 377 | 378 | Frequency 6 : 5755[149+] 379 | Power 6 : 36 36 34 30 30 28 36 32 26 26 28 26 22 20 380 | 381 | Frequency 7 : 5795[157+] 382 | Power 7 : 36 36 34 30 30 28 36 32 26 26 28 26 22 20 383 | ---------------------------------------------------------------------------------------- 384 | Regulatory 5GHz : FCC__11A FCC_HT20 FCC_HT40 MKK__11A MKK_HT20 MKK_HT40 ETSI_11A ETSIHT20 ETSIHT40 385 | 386 | Frequency 0 : 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 5180[36] 387 | Power|Edge 0 : 24|0 24|0 18|0 60|0 60|0 60|0 18|0 18|0 18|0 388 | 389 | Frequency 1 : 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 5220[44] 390 | Power|Edge 1 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 391 | 392 | Frequency 2 : 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 5320[64] 393 | Power|Edge 2 : 24|0 24|0 24|0 60|0 60|0 60|0 18|0 18|0 18|0 394 | 395 | Frequency 3 : 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 5400[64+] 396 | Power|Edge 3 : 24|1 24|1 24|1 60|1 60|1 60|1 18|1 18|1 18|1 397 | 398 | Frequency 4 : 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 5500[100] 399 | Power|Edge 4 : 24|0 24|0 24|0 60|0 60|0 60|0 32|0 32|0 32|0 400 | 401 | Frequency 5 : 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 5600[120] 402 | Power|Edge 5 : 24|1 24|1 24|1 60|1 60|1 60|1 32|1 32|1 32|1 403 | 404 | Frequency 6 :5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+]5725[140+] 405 | Power|Edge 6 : 30|0 30|0 30|0 60|0 60|0 60|0 32|0 32|0 32|0 406 | 407 | Frequency 7 : 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 5825[165] 408 | Power|Edge 7 : 30|1 30|1 30|1 60|1 60|1 60|1 32|1 32|1 32|1 409 | ---------------------------------------------------------------------------------------- 410 | 5GHz Modal Header : Chain0 Chain1 Chain2 411 | Ant. Control : 0x0010 0x0010 0x0010 412 | NF Threshold : -1 0 0 413 | Range Chain : Low Mid High Low Mid High Low Mid High 414 | xatten1DB : 21 25 28 22 25 27 21 25 24 415 | xatten1Margin : 11 18 11 11 18 11 11 18 11 416 | Range : Low Mid High 417 | Temp Slope : 65 78 86 418 | Quick Drop : 0 0 0 419 | spur Frequency : 5500[100] 0x00 0x00 0x00 0x00 420 | Ant. Common Control : 0x00000110 421 | Ant. Common Control2 : 0x00022222 422 | Ant. Gain : 0 423 | Switch Settle : 45 424 | Volt Slope : 0 425 | txEndToXpaOff : 0 426 | txEndToRxOn : 2 427 | XPA Bias Level : 15 428 | txFrameToDataStart : 14 429 | txFrameToPaOn : 14 430 | txFrameToXpaOn : 14 431 | txClip : 3 432 | ADC Desired Size : -30 433 | Thresh62 : 28 434 | PAPRD Rate Mask : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 HIGH_SCALE:6 435 | PAPRD Rate Mask HT40 : 5S 11L 11S HT20_7 HT20_12 HT20_13 HT20_22 HT20_23 HT40_0_8_16 HT40_1_3_9_11_17_19 LOW_SCALE:6 MID_SCALE:6 436 | switch com spdt : 0 437 | XLNA Bias Strength : 0 438 | Reserved : 00 00 00 00 00 00 00 00 00 00 00 439 | Future Modal : 00 00 00 00 00 00 00 440 | ---------------------------------------------------------------------------------------- 441 | Frequency : Low Mid High 442 | PAPRD Scale : <5400 >=5400 >=5700 443 | Other : 5180 5500 5785 444 | ---------------------------------------------------------------------------------------- 445 | 446 | Fix up calibration incomplete 5GHz, only works between 5745[149] and 5825[165]. Warning: fix up used inaccurate values (interpolated). Version 1. 447 | ---------------------------------------------------------------------------------------- 448 | Allow 2.4GHz : 0 449 | Allow 5GHz : 1 450 | ---------------------------------------------------------------------------------------- 451 | Calibration 5GHz : Chain0 Chain1 Chain2 452 | 453 | Frequency 0 : 5180[36] 454 | Ref Power 0 : -24 -26 -25 455 | Volt Meas 0 : 0 0 0 456 | Temp Meas 0 : 176 176 177 457 | RX Noisefloor Cal 0 : 0 0 0 458 | RX Noisefloor Pwr 0 : 0 0 0 459 | RX Temp Meas 0 : 0 0 0 460 | 461 | Frequency 1 : 5240[48] 462 | Ref Power 1 : -19 -21 -20 463 | Volt Meas 1 : 0 0 0 464 | Temp Meas 1 : 176 177 177 465 | RX Noisefloor Cal 1 : 0 0 0 466 | RX Noisefloor Pwr 1 : 0 0 0 467 | RX Temp Meas 1 : 0 0 0 468 | 469 | Frequency 2 : 5320[64] 470 | Ref Power 2 : -14 -16 -15 471 | Volt Meas 2 : 0 0 0 472 | Temp Meas 2 : 177 177 178 473 | RX Noisefloor Cal 2 : 0 0 0 474 | RX Noisefloor Pwr 2 : 0 0 0 475 | RX Temp Meas 2 : 0 0 0 476 | 477 | Frequency 3 : 5500[100] 478 | Ref Power 3 : -10 -12 -11 479 | Volt Meas 3 : 0 0 0 480 | Temp Meas 3 : 176 177 177 481 | RX Noisefloor Cal 3 : 0 0 0 482 | RX Noisefloor Pwr 3 : 0 0 0 483 | RX Temp Meas 3 : 0 0 0 484 | 485 | Frequency 4 : 5620[124] 486 | Ref Power 4 : -10 -12 -11 487 | Volt Meas 4 : 0 0 0 488 | Temp Meas 4 : 177 176 178 489 | RX Noisefloor Cal 4 : 0 0 0 490 | RX Noisefloor Pwr 4 : 0 0 0 491 | RX Temp Meas 4 : 0 0 0 492 | 493 | Frequency 5 : 5700[140] 494 | Ref Power 5 : -13 -15 -14 495 | Volt Meas 5 : 0 0 0 496 | Temp Meas 5 : 176 177 178 497 | RX Noisefloor Cal 5 : 0 0 0 498 | RX Noisefloor Pwr 5 : 0 0 0 499 | RX Temp Meas 5 : 0 0 0 500 | 501 | Frequency 6 : 5745[149] 502 | Ref Power 6 : -16 -19 -17 503 | Volt Meas 6 : 0 0 0 504 | Temp Meas 6 : 175 176 177 505 | RX Noisefloor Cal 6 : 0 0 0 506 | RX Noisefloor Pwr 6 : 0 0 0 507 | RX Temp Meas 6 : 0 0 0 508 | 509 | Frequency 7 : 5825[165] 510 | Ref Power 7 : -22 -25 -24 511 | Volt Meas 7 : 0 0 0 512 | Temp Meas 7 : 177 177 177 513 | RX Noisefloor Cal 7 : 0 0 0 514 | RX Noisefloor Pwr 7 : 0 0 0 515 | RX Temp Meas 7 : 0 0 0 516 | ---------------------------------------------------------------------------------------- 517 | 518 | -------------------------------------------------------------------------------- /ar9300_eeprom/include/ar9003_eeprom.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2010-2011 Atheros Communications Inc. 3 | * 4 | * Permission to use, copy, modify, and/or distribute this software for any 5 | * purpose with or without fee is hereby granted, provided that the above 6 | * copyright notice and this permission notice appear in all copies. 7 | * 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | */ 16 | 17 | #ifndef AR9003_EEPROM_H 18 | #define AR9003_EEPROM_H 19 | 20 | #ifdef _MSC_VER 21 | #pragma pack(push, 1) 22 | #endif 23 | 24 | #define AR9300_EEP_VER 0xD000 25 | #define AR9300_EEP_VER_MINOR_MASK 0xFFF 26 | #define AR9300_EEP_MINOR_VER_1 0x1 27 | #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1 28 | 29 | /* 16-bit offset location start of calibration struct */ 30 | #define AR9300_EEP_START_LOC 256 31 | #define AR9300_NUM_5G_CAL_PIERS 8 32 | #define AR9300_NUM_2G_CAL_PIERS 3 33 | #define AR9300_NUM_5G_20_TARGET_POWERS 8 34 | #define AR9300_NUM_5G_40_TARGET_POWERS 8 35 | #define AR9300_NUM_2G_CCK_TARGET_POWERS 2 36 | #define AR9300_NUM_2G_20_TARGET_POWERS 3 37 | #define AR9300_NUM_2G_40_TARGET_POWERS 3 38 | /* #define AR9300_NUM_CTLS 21 */ 39 | #define AR9300_NUM_CTLS_5G 9 40 | #define AR9300_NUM_CTLS_2G 12 41 | #define AR9300_NUM_BAND_EDGES_5G 8 42 | #define AR9300_NUM_BAND_EDGES_2G 4 43 | #define AR9300_EEPMISC_BIG_ENDIAN 0x01 44 | #define AR9300_EEPMISC_WOW 0x02 45 | #define AR9300_CUSTOMER_DATA_SIZE 20 46 | 47 | #define AR9300_MAX_CHAINS 3 48 | #define AR9300_ANT_16S 25 49 | #define AR9300_FUTURE_MODAL_SZ 6 50 | 51 | #define AR9300_PAPRD_RATE_MASK 0x01ffffff 52 | #define AR9300_PAPRD_SCALE_1 0x0e000000 53 | #define AR9300_PAPRD_SCALE_1_S 25 54 | #define AR9300_PAPRD_SCALE_2 0x70000000 55 | #define AR9300_PAPRD_SCALE_2_S 28 56 | 57 | #define AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE 0xc9 58 | 59 | /* Delta from which to start power to pdadc table */ 60 | /* This offset is used in both open loop and closed loop power control 61 | * schemes. In open loop power control, it is not really needed, but for 62 | * the "sake of consistency" it was kept. For certain AP designs, this 63 | * value is overwritten by the value in the flag "pwrTableOffset" just 64 | * before writing the pdadc vs pwr into the chip registers. 65 | */ 66 | #define AR9300_PWR_TABLE_OFFSET 0 67 | 68 | /* byte addressable */ 69 | #define AR9300_EEPROM_SIZE (16*1024) 70 | 71 | #define AR9300_BASE_ADDR_4K 0xfff 72 | #define AR9300_BASE_ADDR 0x3ff 73 | #define AR9300_BASE_ADDR_512 0x1ff 74 | 75 | #define AR9300_OTP_BASE \ 76 | ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000) 77 | #define AR9300_OTP_STATUS \ 78 | ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18) 79 | #define AR9300_OTP_STATUS_TYPE 0x7 80 | #define AR9300_OTP_STATUS_VALID 0x4 81 | #define AR9300_OTP_STATUS_ACCESS_BUSY 0x2 82 | #define AR9300_OTP_STATUS_SM_BUSY 0x1 83 | #define AR9300_OTP_READ_DATA \ 84 | ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c) 85 | 86 | enum targetPowerHTRates { 87 | HT_TARGET_RATE_0_8_16, 88 | HT_TARGET_RATE_1_3_9_11_17_19, 89 | HT_TARGET_RATE_4, 90 | HT_TARGET_RATE_5, 91 | HT_TARGET_RATE_6, 92 | HT_TARGET_RATE_7, 93 | HT_TARGET_RATE_12, 94 | HT_TARGET_RATE_13, 95 | HT_TARGET_RATE_14, 96 | HT_TARGET_RATE_15, 97 | HT_TARGET_RATE_20, 98 | HT_TARGET_RATE_21, 99 | HT_TARGET_RATE_22, 100 | HT_TARGET_RATE_23 101 | }; 102 | 103 | enum targetPowerLegacyRates { 104 | LEGACY_TARGET_RATE_6_24, 105 | LEGACY_TARGET_RATE_36, 106 | LEGACY_TARGET_RATE_48, 107 | LEGACY_TARGET_RATE_54 108 | }; 109 | 110 | enum targetPowerCckRates { 111 | LEGACY_TARGET_RATE_1L_5L, 112 | LEGACY_TARGET_RATE_5S, 113 | LEGACY_TARGET_RATE_11L, 114 | LEGACY_TARGET_RATE_11S 115 | }; 116 | 117 | enum ar9300_Rates { 118 | ALL_TARGET_LEGACY_6_24, 119 | ALL_TARGET_LEGACY_36, 120 | ALL_TARGET_LEGACY_48, 121 | ALL_TARGET_LEGACY_54, 122 | ALL_TARGET_LEGACY_1L_5L, 123 | ALL_TARGET_LEGACY_5S, 124 | ALL_TARGET_LEGACY_11L, 125 | ALL_TARGET_LEGACY_11S, 126 | ALL_TARGET_HT20_0_8_16, 127 | ALL_TARGET_HT20_1_3_9_11_17_19, 128 | ALL_TARGET_HT20_4, 129 | ALL_TARGET_HT20_5, 130 | ALL_TARGET_HT20_6, 131 | ALL_TARGET_HT20_7, 132 | ALL_TARGET_HT20_12, 133 | ALL_TARGET_HT20_13, 134 | ALL_TARGET_HT20_14, 135 | ALL_TARGET_HT20_15, 136 | ALL_TARGET_HT20_20, 137 | ALL_TARGET_HT20_21, 138 | ALL_TARGET_HT20_22, 139 | ALL_TARGET_HT20_23, 140 | ALL_TARGET_HT40_0_8_16, 141 | ALL_TARGET_HT40_1_3_9_11_17_19, 142 | ALL_TARGET_HT40_4, 143 | ALL_TARGET_HT40_5, 144 | ALL_TARGET_HT40_6, 145 | ALL_TARGET_HT40_7, 146 | ALL_TARGET_HT40_12, 147 | ALL_TARGET_HT40_13, 148 | ALL_TARGET_HT40_14, 149 | ALL_TARGET_HT40_15, 150 | ALL_TARGET_HT40_20, 151 | ALL_TARGET_HT40_21, 152 | ALL_TARGET_HT40_22, 153 | ALL_TARGET_HT40_23, 154 | ar9300RateSize, 155 | }; 156 | 157 | struct eepFlags { 158 | u8 opFlags; 159 | u8 eepMisc; 160 | } __packed; 161 | 162 | enum CompressAlgorithm { 163 | _CompressNone = 0, 164 | _CompressLzma, 165 | _CompressPairs, 166 | _CompressBlock, 167 | _Compress4, 168 | _Compress5, 169 | _Compress6, 170 | _Compress7, 171 | }; 172 | 173 | struct ar9300_base_eep_hdr { 174 | __le16 regDmn[2]; 175 | /* 4 bits tx and 4 bits rx */ 176 | u8 txrxMask; 177 | struct eepFlags opCapFlags; 178 | u8 rfSilent; 179 | u8 blueToothOptions; 180 | u8 deviceCap; 181 | /* takes lower byte in eeprom location */ 182 | u8 deviceType; 183 | /* offset in dB to be added to beginning 184 | * of pdadc table in calibration 185 | */ 186 | int8_t pwrTableOffset; 187 | u8 params_for_tuning_caps[2]; 188 | /* 189 | * bit0 - enable tx temp comp 190 | * bit1 - enable tx volt comp 191 | * bit2 - enable fastClock - default to 1 192 | * bit3 - enable doubling - default to 1 193 | * bit4 - enable internal regulator - default to 1 194 | */ 195 | u8 featureEnable; 196 | /* misc flags: bit0 - turn down drivestrength */ 197 | u8 miscConfiguration; 198 | u8 eepromWriteEnableGpio; 199 | u8 wlanDisableGpio; 200 | u8 wlanLedGpio; 201 | u8 rxBandSelectGpio; 202 | u8 txrxgain; 203 | /* SW controlled internal regulator fields */ 204 | __le32 swreg; 205 | } __packed; 206 | 207 | struct ar9300_modal_eep_header { 208 | /* 4 idle, t1, t2, b (4 bits per setting) */ 209 | __le32 antCtrlCommon; 210 | /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ 211 | __le32 antCtrlCommon2; 212 | /* 6 idle, t, r, rx1, rx12, b (2 bits each) */ 213 | __le16 antCtrlChain[AR9300_MAX_CHAINS]; 214 | /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ 215 | u8 xatten1DB[AR9300_MAX_CHAINS]; 216 | /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */ 217 | u8 xatten1Margin[AR9300_MAX_CHAINS]; 218 | int8_t tempSlope; 219 | int8_t voltSlope; 220 | /* spur channels in usual fbin coding format */ 221 | u8 spurChans[AR_EEPROM_MODAL_SPURS]; 222 | /* 3 Check if the register is per chain */ 223 | int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; 224 | u8 reserved[11]; 225 | int8_t quick_drop; 226 | u8 xpaBiasLvl; 227 | u8 txFrameToDataStart; 228 | u8 txFrameToPaOn; 229 | u8 txClip; 230 | int8_t antennaGain; 231 | u8 switchSettling; 232 | int8_t adcDesiredSize; 233 | u8 txEndToXpaOff; 234 | u8 txEndToRxOn; 235 | u8 txFrameToXpaOn; 236 | u8 thresh62; 237 | __le32 papdRateMaskHt20; 238 | __le32 papdRateMaskHt40; 239 | __le16 switchcomspdt; 240 | u8 xlna_bias_strength; 241 | u8 futureModal[7]; 242 | } __packed; 243 | 244 | struct ar9300_cal_data_per_freq_op_loop { 245 | int8_t refPower; 246 | /* pdadc voltage at power measurement */ 247 | u8 voltMeas; 248 | /* pcdac used for power measurement */ 249 | u8 tempMeas; 250 | /* range is -60 to -127 create a mapping equation 1db resolution */ 251 | int8_t rxNoisefloorCal; 252 | /*range is same as noisefloor */ 253 | int8_t rxNoisefloorPower; 254 | /* temp measured when noisefloor cal was performed */ 255 | u8 rxTempMeas; 256 | } __packed; 257 | 258 | struct cal_tgt_pow_legacy { 259 | u8 tPow2x[4]; 260 | } __packed; 261 | 262 | struct cal_tgt_pow_ht { 263 | u8 tPow2x[14]; 264 | } __packed; 265 | 266 | struct cal_ctl_data_2g { 267 | u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]; 268 | } __packed; 269 | 270 | struct cal_ctl_data_5g { 271 | u8 ctlEdges[AR9300_NUM_BAND_EDGES_5G]; 272 | } __packed; 273 | 274 | #define MAX_BASE_EXTENSION_FUTURE 2 275 | 276 | struct ar9300_BaseExtension_1 { 277 | u8 ant_div_control; 278 | u8 future[MAX_BASE_EXTENSION_FUTURE]; 279 | /* 280 | * misc_enable: 281 | * 282 | * BIT 0 - TX Gain Cap enable. 283 | * BIT 1 - Uncompressed Checksum enable. 284 | * BIT 2/3 - MinCCApwr enable 2g/5g. 285 | */ 286 | u8 misc_enable; 287 | int8_t tempslopextension[8]; 288 | int8_t quick_drop_low; 289 | int8_t quick_drop_high; 290 | } __packed; 291 | 292 | struct ar9300_BaseExtension_2 { 293 | int8_t tempSlopeLow; 294 | int8_t tempSlopeHigh; 295 | u8 xatten1DBLow[AR9300_MAX_CHAINS]; 296 | u8 xatten1MarginLow[AR9300_MAX_CHAINS]; 297 | u8 xatten1DBHigh[AR9300_MAX_CHAINS]; 298 | u8 xatten1MarginHigh[AR9300_MAX_CHAINS]; 299 | } __packed; 300 | 301 | struct ar9300_eeprom { 302 | u8 eepromVersion; 303 | u8 templateVersion; 304 | u8 macAddr[6]; 305 | u8 custData[AR9300_CUSTOMER_DATA_SIZE]; 306 | 307 | struct ar9300_base_eep_hdr baseEepHeader; 308 | 309 | struct ar9300_modal_eep_header modalHeader2G; 310 | struct ar9300_BaseExtension_1 base_ext1; 311 | u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 312 | struct ar9300_cal_data_per_freq_op_loop 313 | calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 314 | u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]; 315 | u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]; 316 | u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; 317 | u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; 318 | struct cal_tgt_pow_legacy 319 | calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]; 320 | struct cal_tgt_pow_legacy 321 | calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]; 322 | struct cal_tgt_pow_ht 323 | calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; 324 | struct cal_tgt_pow_ht 325 | calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; 326 | u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]; 327 | u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; 328 | struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; 329 | struct ar9300_modal_eep_header modalHeader5G; 330 | struct ar9300_BaseExtension_2 base_ext2; 331 | u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 332 | struct ar9300_cal_data_per_freq_op_loop 333 | calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 334 | u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]; 335 | u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; 336 | u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; 337 | struct cal_tgt_pow_legacy 338 | calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]; 339 | struct cal_tgt_pow_ht 340 | calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; 341 | struct cal_tgt_pow_ht 342 | calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; 343 | u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]; 344 | u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]; 345 | struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]; 346 | } __packed; 347 | 348 | #ifdef _MSC_VER 349 | #pragma pack(pop) 350 | #endif 351 | /* 352 | s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); 353 | s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); 354 | u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz); 355 | u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz); 356 | 357 | u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz); 358 | 359 | unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, 360 | struct ath9k_channel *chan); 361 | 362 | void ar9003_hw_internal_regulator_apply(struct ath_hw *ah); 363 | */ 364 | #endif 365 | -------------------------------------------------------------------------------- /ar9300_eeprom/include/ar9300_eeprom.h: -------------------------------------------------------------------------------- 1 | #ifndef AR9300_EEPROM_H 2 | #define AR9300_EEPROM_H 3 | 4 | #include "eeprom.h" 5 | 6 | struct ar9300_fixup; 7 | struct ar9300_layout; 8 | 9 | u32 dump_eeprom(struct ar9300_eeprom *eep, char *buf, u32 len); 10 | u32 dump_fixup(struct ar9300_fixup *fixup, char *buf, u32 len); 11 | int read_eeproms(struct ar9300_eeprom eeproms[], const struct ar9300_layout *layout, char *filename); 12 | int write_eeproms(struct ar9300_eeprom eeproms[], const struct ar9300_layout *layout, char *filename, char *outname); 13 | bool default_detect(struct ar9300_eeprom eeproms[], const void *data); 14 | 15 | #define AR9300_MAX_EEPROMS 2 16 | 17 | #define AR9300_MAX_CHAINS 3 18 | #define AR9300_NUM_5G_CAL_PIERS 8 19 | #define AR9300_NUM_2G_CAL_PIERS 3 20 | 21 | #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6)) 22 | 23 | #ifdef _MSC_VER 24 | #pragma pack(push, 1) 25 | #endif 26 | 27 | struct ar9300_fixup { 28 | const char *info; 29 | 30 | bool allow2G; 31 | u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 32 | struct ar9300_cal_data_per_freq_op_loop calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 33 | 34 | bool allow5G; 35 | u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 36 | struct ar9300_cal_data_per_freq_op_loop calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 37 | } __packed; 38 | 39 | #ifdef _MSC_VER 40 | #pragma pack(pop) 41 | #endif 42 | 43 | struct ar9300_layout { 44 | const s32 offsets[AR9300_MAX_EEPROMS]; 45 | }; 46 | 47 | struct ar9300_revision { 48 | const char *name; 49 | const char *version; 50 | const char *number; 51 | const char *revision; 52 | const struct ar9300_fixup *fixup; 53 | bool (*detect)(struct ar9300_eeprom eeproms[], const void *data); 54 | const void *data; 55 | }; 56 | 57 | struct ar9300_detect { 58 | const char *name; 59 | struct ar9300_layout layout; 60 | const struct ar9300_revision *revisions[]; 61 | }; 62 | 63 | struct default_detect_data { 64 | u8 params_for_tuning_caps[2]; 65 | 66 | bool allow2G; 67 | u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; 68 | struct ar9300_cal_data_per_freq_op_loop calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; 69 | 70 | bool allow5G; 71 | u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; 72 | struct ar9300_cal_data_per_freq_op_loop calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; 73 | }; 74 | 75 | #endif 76 | -------------------------------------------------------------------------------- /ar9300_eeprom/include/eeprom.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2008-2011 Atheros Communications Inc. 3 | * 4 | * Permission to use, copy, modify, and/or distribute this software for any 5 | * purpose with or without fee is hereby granted, provided that the above 6 | * copyright notice and this permission notice appear in all copies. 7 | * 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 | */ 16 | 17 | #ifndef EEPROM_H 18 | #define EEPROM_H 19 | 20 | #define AR_EEPROM_MODAL_SPURS 5 21 | 22 | //#include "../ath.h" 23 | //#include 24 | #include "types.h" 25 | #include "ar9003_eeprom.h" 26 | 27 | #ifdef _MSC_VER 28 | #pragma pack(push, 1) 29 | #endif 30 | 31 | #ifdef __BIG_ENDIAN 32 | #define AR5416_EEPROM_MAGIC 0x5aa5 33 | #else 34 | #define AR5416_EEPROM_MAGIC 0xa55a 35 | #endif 36 | 37 | #define CTRY_DEBUG 0x1ff 38 | #define CTRY_DEFAULT 0 39 | 40 | #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 41 | #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 42 | #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 43 | #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 44 | #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 45 | #define AR_EEPROM_EEPCAP_MAXQCU_S 4 46 | #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 47 | #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 48 | #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 49 | 50 | #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 51 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 52 | #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 53 | #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 54 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 55 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 56 | 57 | #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 58 | #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 59 | 60 | #define AR5416_EEPROM_MAGIC_OFFSET 0x0 61 | #define AR5416_EEPROM_S 2 62 | #define AR5416_EEPROM_OFFSET 0x2000 63 | #define AR5416_EEPROM_MAX 0xae0 64 | 65 | #define AR5416_EEPROM_START_ADDR \ 66 | (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 67 | 68 | #define SD_NO_CTL 0xE0 69 | #define NO_CTL 0xff 70 | #define CTL_MODE_M 0xf 71 | #define CTL_11A 0 72 | #define CTL_11B 1 73 | #define CTL_11G 2 74 | #define CTL_2GHT20 5 75 | #define CTL_5GHT20 6 76 | #define CTL_2GHT40 7 77 | #define CTL_5GHT40 8 78 | 79 | #define EXT_ADDITIVE (0x8000) 80 | #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 81 | #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 82 | #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 83 | 84 | #define SUB_NUM_CTL_MODES_AT_5G_40 2 85 | #define SUB_NUM_CTL_MODES_AT_2G_40 3 86 | 87 | #define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */ 88 | #define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */ 89 | 90 | /* 91 | * For AR9285 and later chipsets, the following bits are not being programmed 92 | * in EEPROM and so need to be enabled always. 93 | * 94 | * Bit 0: en_fcc_mid 95 | * Bit 1: en_jap_mid 96 | * Bit 2: en_fcc_dfs_ht40 97 | * Bit 3: en_jap_ht40 98 | * Bit 4: en_jap_dfs_ht40 99 | */ 100 | #define AR9285_RDEXT_DEFAULT 0x1F 101 | 102 | #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 103 | #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 104 | #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) 105 | #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 106 | 107 | #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 108 | #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 109 | ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 110 | #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ 111 | ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 112 | 113 | #define EEP_RFSILENT_ENABLED 0x0001 114 | #define EEP_RFSILENT_ENABLED_S 0 115 | #define EEP_RFSILENT_POLARITY 0x0002 116 | #define EEP_RFSILENT_POLARITY_S 1 117 | #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) 118 | #define EEP_RFSILENT_GPIO_SEL_S 2 119 | 120 | #define AR5416_OPFLAGS_11A 0x01 121 | #define AR5416_OPFLAGS_11G 0x02 122 | #define AR5416_OPFLAGS_N_5G_HT40 0x04 123 | #define AR5416_OPFLAGS_N_2G_HT40 0x08 124 | #define AR5416_OPFLAGS_N_5G_HT20 0x10 125 | #define AR5416_OPFLAGS_N_2G_HT20 0x20 126 | 127 | #define AR5416_EEP_NO_BACK_VER 0x1 128 | #define AR5416_EEP_VER 0xE 129 | #define AR5416_EEP_VER_MINOR_MASK 0x0FFF 130 | #define AR5416_EEP_MINOR_VER_2 0x2 131 | #define AR5416_EEP_MINOR_VER_3 0x3 132 | #define AR5416_EEP_MINOR_VER_7 0x7 133 | #define AR5416_EEP_MINOR_VER_9 0x9 134 | #define AR5416_EEP_MINOR_VER_16 0x10 135 | #define AR5416_EEP_MINOR_VER_17 0x11 136 | #define AR5416_EEP_MINOR_VER_19 0x13 137 | #define AR5416_EEP_MINOR_VER_20 0x14 138 | #define AR5416_EEP_MINOR_VER_21 0x15 139 | #define AR5416_EEP_MINOR_VER_22 0x16 140 | 141 | #define AR5416_NUM_5G_CAL_PIERS 8 142 | #define AR5416_NUM_2G_CAL_PIERS 4 143 | #define AR5416_NUM_5G_20_TARGET_POWERS 8 144 | #define AR5416_NUM_5G_40_TARGET_POWERS 8 145 | #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 146 | #define AR5416_NUM_2G_20_TARGET_POWERS 4 147 | #define AR5416_NUM_2G_40_TARGET_POWERS 4 148 | #define AR5416_NUM_CTLS 24 149 | #define AR5416_NUM_BAND_EDGES 8 150 | #define AR5416_NUM_PD_GAINS 4 151 | #define AR5416_PD_GAINS_IN_MASK 4 152 | #define AR5416_PD_GAIN_ICEPTS 5 153 | #define AR5416_NUM_PDADC_VALUES 128 154 | #define AR5416_BCHAN_UNUSED 0xFF 155 | #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 156 | #define AR5416_MAX_CHAINS 3 157 | #define AR9300_MAX_CHAINS 3 158 | #define AR5416_PWR_TABLE_OFFSET_DB -5 159 | 160 | /* Rx gain type values */ 161 | #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 162 | #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 163 | #define AR5416_EEP_RXGAIN_ORIG 2 164 | 165 | /* Tx gain type values */ 166 | #define AR5416_EEP_TXGAIN_ORIGINAL 0 167 | #define AR5416_EEP_TXGAIN_HIGH_POWER 1 168 | 169 | #define AR5416_EEP4K_START_LOC 64 170 | #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 171 | #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 172 | #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 173 | #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 174 | #define AR5416_EEP4K_NUM_CTLS 12 175 | #define AR5416_EEP4K_NUM_BAND_EDGES 4 176 | #define AR5416_EEP4K_NUM_PD_GAINS 2 177 | #define AR5416_EEP4K_MAX_CHAINS 1 178 | 179 | #define AR9280_TX_GAIN_TABLE_SIZE 22 180 | 181 | #define AR9287_EEP_VER 0xE 182 | #define AR9287_EEP_VER_MINOR_MASK 0xFFF 183 | #define AR9287_EEP_MINOR_VER_1 0x1 184 | #define AR9287_EEP_MINOR_VER_2 0x2 185 | #define AR9287_EEP_MINOR_VER_3 0x3 186 | #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 187 | #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 188 | #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 189 | 190 | #define AR9287_EEP_START_LOC 128 191 | #define AR9287_HTC_EEP_START_LOC 256 192 | #define AR9287_NUM_2G_CAL_PIERS 3 193 | #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 194 | #define AR9287_NUM_2G_20_TARGET_POWERS 3 195 | #define AR9287_NUM_2G_40_TARGET_POWERS 3 196 | #define AR9287_NUM_CTLS 12 197 | #define AR9287_NUM_BAND_EDGES 4 198 | #define AR9287_PD_GAIN_ICEPTS 1 199 | #define AR9287_EEPMISC_BIG_ENDIAN 0x01 200 | #define AR9287_EEPMISC_WOW 0x02 201 | #define AR9287_MAX_CHAINS 2 202 | #define AR9287_ANT_16S 32 203 | 204 | #define AR9287_DATA_SZ 32 205 | 206 | #define AR9287_PWR_TABLE_OFFSET_DB -5 207 | 208 | #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 209 | 210 | #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 211 | #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 212 | 213 | #define LNA_CTL_BUF_MODE BIT(0) 214 | #define LNA_CTL_ISEL_LO BIT(1) 215 | #define LNA_CTL_ISEL_HI BIT(2) 216 | #define LNA_CTL_BUF_IN BIT(3) 217 | #define LNA_CTL_FEM_BAND BIT(4) 218 | #define LNA_CTL_LOCAL_BIAS BIT(5) 219 | #define LNA_CTL_FORCE_XPA BIT(6) 220 | #define LNA_CTL_USE_ANT1 BIT(7) 221 | 222 | enum eeprom_param { 223 | EEP_NFTHRESH_5, 224 | EEP_NFTHRESH_2, 225 | EEP_MAC_MSW, 226 | EEP_MAC_MID, 227 | EEP_MAC_LSW, 228 | EEP_REG_0, 229 | EEP_OP_CAP, 230 | EEP_OP_MODE, 231 | EEP_RF_SILENT, 232 | EEP_OB_5, 233 | EEP_DB_5, 234 | EEP_OB_2, 235 | EEP_DB_2, 236 | EEP_MINOR_REV, 237 | EEP_TX_MASK, 238 | EEP_RX_MASK, 239 | EEP_FSTCLK_5G, 240 | EEP_RXGAIN_TYPE, 241 | EEP_OL_PWRCTRL, 242 | EEP_TXGAIN_TYPE, 243 | EEP_RC_CHAIN_MASK, 244 | EEP_DAC_HPWR_5G, 245 | EEP_FRAC_N_5G, 246 | EEP_DEV_TYPE, 247 | EEP_TEMPSENSE_SLOPE, 248 | EEP_TEMPSENSE_SLOPE_PAL_ON, 249 | EEP_PWR_TABLE_OFFSET, 250 | EEP_PAPRD, 251 | EEP_MODAL_VER, 252 | EEP_ANT_DIV_CTL1, 253 | EEP_CHAIN_MASK_REDUCE, 254 | EEP_ANTENNA_GAIN_2G, 255 | EEP_ANTENNA_GAIN_5G, 256 | }; 257 | 258 | enum ar5416_rates { 259 | rate6mb, rate9mb, rate12mb, rate18mb, 260 | rate24mb, rate36mb, rate48mb, rate54mb, 261 | rate1l, rate2l, rate2s, rate5_5l, 262 | rate5_5s, rate11l, rate11s, rateXr, 263 | rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 264 | rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 265 | rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 266 | rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 267 | rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 268 | Ar5416RateSize 269 | }; 270 | 271 | enum ath9k_hal_freq_band { 272 | ATH9K_HAL_FREQ_BAND_5GHZ = 0, 273 | ATH9K_HAL_FREQ_BAND_2GHZ = 1 274 | }; 275 | 276 | struct base_eep_header { 277 | u16 length; 278 | u16 checksum; 279 | u16 version; 280 | u8 opCapFlags; 281 | u8 eepMisc; 282 | u16 regDmn[2]; 283 | u8 macAddr[6]; 284 | u8 rxMask; 285 | u8 txMask; 286 | u16 rfSilent; 287 | u16 blueToothOptions; 288 | u16 deviceCap; 289 | u32 binBuildNumber; 290 | u8 deviceType; 291 | u8 pwdclkind; 292 | u8 fastClk5g; 293 | u8 divChain; 294 | u8 rxGainType; 295 | u8 dacHiPwrMode_5G; 296 | u8 openLoopPwrCntl; 297 | u8 dacLpMode; 298 | u8 txGainType; 299 | u8 rcChainMask; 300 | u8 desiredScaleCCK; 301 | u8 pwr_table_offset; 302 | u8 frac_n_5g; 303 | u8 futureBase_3[21]; 304 | } __packed; 305 | 306 | struct base_eep_header_4k { 307 | u16 length; 308 | u16 checksum; 309 | u16 version; 310 | u8 opCapFlags; 311 | u8 eepMisc; 312 | u16 regDmn[2]; 313 | u8 macAddr[6]; 314 | u8 rxMask; 315 | u8 txMask; 316 | u16 rfSilent; 317 | u16 blueToothOptions; 318 | u16 deviceCap; 319 | u32 binBuildNumber; 320 | u8 deviceType; 321 | u8 txGainType; 322 | } __packed; 323 | 324 | 325 | struct spur_chan { 326 | u16 spurChan; 327 | u8 spurRangeLow; 328 | u8 spurRangeHigh; 329 | } __packed; 330 | 331 | struct modal_eep_header { 332 | u32 antCtrlChain[AR5416_MAX_CHAINS]; 333 | u32 antCtrlCommon; 334 | u8 antennaGainCh[AR5416_MAX_CHAINS]; 335 | u8 switchSettling; 336 | u8 txRxAttenCh[AR5416_MAX_CHAINS]; 337 | u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 338 | u8 adcDesiredSize; 339 | u8 pgaDesiredSize; 340 | u8 xlnaGainCh[AR5416_MAX_CHAINS]; 341 | u8 txEndToXpaOff; 342 | u8 txEndToRxOn; 343 | u8 txFrameToXpaOn; 344 | u8 thresh62; 345 | u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 346 | u8 xpdGain; 347 | u8 xpd; 348 | u8 iqCalICh[AR5416_MAX_CHAINS]; 349 | u8 iqCalQCh[AR5416_MAX_CHAINS]; 350 | u8 pdGainOverlap; 351 | u8 ob; 352 | u8 db; 353 | u8 xpaBiasLvl; 354 | u8 pwrDecreaseFor2Chain; 355 | u8 pwrDecreaseFor3Chain; 356 | u8 txFrameToDataStart; 357 | u8 txFrameToPaOn; 358 | u8 ht40PowerIncForPdadc; 359 | u8 bswAtten[AR5416_MAX_CHAINS]; 360 | u8 bswMargin[AR5416_MAX_CHAINS]; 361 | u8 swSettleHt40; 362 | u8 xatten2Db[AR5416_MAX_CHAINS]; 363 | u8 xatten2Margin[AR5416_MAX_CHAINS]; 364 | u8 ob_ch1; 365 | u8 db_ch1; 366 | u8 lna_ctl; 367 | u8 miscBits; 368 | u16 xpaBiasLvlFreq[3]; 369 | u8 futureModal[6]; 370 | 371 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 372 | } __packed; 373 | 374 | struct calDataPerFreqOpLoop { 375 | u8 pwrPdg[2][5]; 376 | u8 vpdPdg[2][5]; 377 | u8 pcdac[2][5]; 378 | u8 empty[2][5]; 379 | } __packed; 380 | 381 | struct modal_eep_4k_header { 382 | u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 383 | u32 antCtrlCommon; 384 | u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 385 | u8 switchSettling; 386 | u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 387 | u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 388 | u8 adcDesiredSize; 389 | u8 pgaDesiredSize; 390 | u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 391 | u8 txEndToXpaOff; 392 | u8 txEndToRxOn; 393 | u8 txFrameToXpaOn; 394 | u8 thresh62; 395 | u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 396 | u8 xpdGain; 397 | u8 xpd; 398 | u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 399 | u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 400 | u8 pdGainOverlap; 401 | #ifdef __BIG_ENDIAN_BITFIELD 402 | u8 ob_1:4, ob_0:4; 403 | u8 db1_1:4, db1_0:4; 404 | #else 405 | u8 ob_0:4, ob_1:4; 406 | u8 db1_0:4, db1_1:4; 407 | #endif 408 | u8 xpaBiasLvl; 409 | u8 txFrameToDataStart; 410 | u8 txFrameToPaOn; 411 | u8 ht40PowerIncForPdadc; 412 | u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 413 | u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 414 | u8 swSettleHt40; 415 | u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 416 | u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 417 | #ifdef __BIG_ENDIAN_BITFIELD 418 | u8 db2_1:4, db2_0:4; 419 | #else 420 | u8 db2_0:4, db2_1:4; 421 | #endif 422 | u8 version; 423 | #ifdef __BIG_ENDIAN_BITFIELD 424 | u8 ob_3:4, ob_2:4; 425 | u8 antdiv_ctl1:4, ob_4:4; 426 | u8 db1_3:4, db1_2:4; 427 | u8 antdiv_ctl2:4, db1_4:4; 428 | u8 db2_2:4, db2_3:4; 429 | u8 reserved:4, db2_4:4; 430 | #else 431 | u8 ob_2:4, ob_3:4; 432 | u8 ob_4:4, antdiv_ctl1:4; 433 | u8 db1_2:4, db1_3:4; 434 | u8 db1_4:4, antdiv_ctl2:4; 435 | u8 db2_2:4, db2_3:4; 436 | u8 db2_4:4, reserved:4; 437 | #endif 438 | u8 tx_diversity; 439 | u8 flc_pwr_thresh; 440 | u8 bb_scale_smrt_antenna; 441 | #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 442 | u8 futureModal[1]; 443 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 444 | } __packed; 445 | 446 | struct base_eep_ar9287_header { 447 | u16 length; 448 | u16 checksum; 449 | u16 version; 450 | u8 opCapFlags; 451 | u8 eepMisc; 452 | u16 regDmn[2]; 453 | u8 macAddr[6]; 454 | u8 rxMask; 455 | u8 txMask; 456 | u16 rfSilent; 457 | u16 blueToothOptions; 458 | u16 deviceCap; 459 | u32 binBuildNumber; 460 | u8 deviceType; 461 | u8 openLoopPwrCntl; 462 | int8_t pwrTableOffset; 463 | int8_t tempSensSlope; 464 | int8_t tempSensSlopePalOn; 465 | u8 futureBase[29]; 466 | } __packed; 467 | 468 | struct modal_eep_ar9287_header { 469 | u32 antCtrlChain[AR9287_MAX_CHAINS]; 470 | u32 antCtrlCommon; 471 | int8_t antennaGainCh[AR9287_MAX_CHAINS]; 472 | u8 switchSettling; 473 | u8 txRxAttenCh[AR9287_MAX_CHAINS]; 474 | u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 475 | int8_t adcDesiredSize; 476 | u8 txEndToXpaOff; 477 | u8 txEndToRxOn; 478 | u8 txFrameToXpaOn; 479 | u8 thresh62; 480 | int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 481 | u8 xpdGain; 482 | u8 xpd; 483 | int8_t iqCalICh[AR9287_MAX_CHAINS]; 484 | int8_t iqCalQCh[AR9287_MAX_CHAINS]; 485 | u8 pdGainOverlap; 486 | u8 xpaBiasLvl; 487 | u8 txFrameToDataStart; 488 | u8 txFrameToPaOn; 489 | u8 ht40PowerIncForPdadc; 490 | u8 bswAtten[AR9287_MAX_CHAINS]; 491 | u8 bswMargin[AR9287_MAX_CHAINS]; 492 | u8 swSettleHt40; 493 | u8 version; 494 | u8 db1; 495 | u8 db2; 496 | u8 ob_cck; 497 | u8 ob_psk; 498 | u8 ob_qam; 499 | u8 ob_pal_off; 500 | u8 futureModal[30]; 501 | struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 502 | } __packed; 503 | 504 | struct cal_data_per_freq { 505 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 506 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 507 | } __packed; 508 | 509 | struct cal_data_per_freq_4k { 510 | u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 511 | u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 512 | } __packed; 513 | 514 | struct cal_target_power_leg { 515 | u8 bChannel; 516 | u8 tPow2x[4]; 517 | } __packed; 518 | 519 | struct cal_target_power_ht { 520 | u8 bChannel; 521 | u8 tPow2x[8]; 522 | } __packed; 523 | 524 | struct cal_ctl_edges { 525 | u8 bChannel; 526 | u8 ctl; 527 | } __packed; 528 | 529 | struct cal_data_op_loop_ar9287 { 530 | u8 pwrPdg[2][5]; 531 | u8 vpdPdg[2][5]; 532 | u8 pcdac[2][5]; 533 | u8 empty[2][5]; 534 | } __packed; 535 | 536 | struct cal_data_per_freq_ar9287 { 537 | u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 538 | u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 539 | } __packed; 540 | 541 | union cal_data_per_freq_ar9287_u { 542 | struct cal_data_op_loop_ar9287 calDataOpen; 543 | struct cal_data_per_freq_ar9287 calDataClose; 544 | } __packed; 545 | 546 | struct cal_ctl_data_ar9287 { 547 | struct cal_ctl_edges 548 | ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 549 | } __packed; 550 | 551 | struct cal_ctl_data { 552 | struct cal_ctl_edges 553 | ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 554 | } __packed; 555 | 556 | struct cal_ctl_data_4k { 557 | struct cal_ctl_edges 558 | ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 559 | } __packed; 560 | 561 | struct ar5416_eeprom_def { 562 | struct base_eep_header baseEepHeader; 563 | u8 custData[64]; 564 | struct modal_eep_header modalHeader[2]; 565 | u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 566 | u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 567 | struct cal_data_per_freq 568 | calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 569 | struct cal_data_per_freq 570 | calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 571 | struct cal_target_power_leg 572 | calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 573 | struct cal_target_power_ht 574 | calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 575 | struct cal_target_power_ht 576 | calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 577 | struct cal_target_power_leg 578 | calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 579 | struct cal_target_power_leg 580 | calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 581 | struct cal_target_power_ht 582 | calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 583 | struct cal_target_power_ht 584 | calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 585 | u8 ctlIndex[AR5416_NUM_CTLS]; 586 | struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 587 | u8 padding; 588 | } __packed; 589 | 590 | struct ar5416_eeprom_4k { 591 | struct base_eep_header_4k baseEepHeader; 592 | u8 custData[20]; 593 | struct modal_eep_4k_header modalHeader; 594 | u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 595 | struct cal_data_per_freq_4k 596 | calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 597 | struct cal_target_power_leg 598 | calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 599 | struct cal_target_power_leg 600 | calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 601 | struct cal_target_power_ht 602 | calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 603 | struct cal_target_power_ht 604 | calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 605 | u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 606 | struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 607 | u8 padding; 608 | } __packed; 609 | 610 | struct ar9287_eeprom { 611 | struct base_eep_ar9287_header baseEepHeader; 612 | u8 custData[AR9287_DATA_SZ]; 613 | struct modal_eep_ar9287_header modalHeader; 614 | u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 615 | union cal_data_per_freq_ar9287_u 616 | calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 617 | struct cal_target_power_leg 618 | calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 619 | struct cal_target_power_leg 620 | calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 621 | struct cal_target_power_ht 622 | calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 623 | struct cal_target_power_ht 624 | calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 625 | u8 ctlIndex[AR9287_NUM_CTLS]; 626 | struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 627 | u8 padding; 628 | } __packed; 629 | 630 | #ifdef _MSC_VER 631 | #pragma pack(pop) 632 | #endif 633 | 634 | enum reg_ext_bitmap { 635 | REG_EXT_FCC_MIDBAND = 0, 636 | REG_EXT_JAPAN_MIDBAND = 1, 637 | REG_EXT_FCC_DFS_HT40 = 2, 638 | REG_EXT_JAPAN_NONDFS_HT40 = 3, 639 | REG_EXT_JAPAN_DFS_HT40 = 4 640 | }; 641 | 642 | struct ath9k_country_entry { 643 | u16 countryCode; 644 | u16 regDmnEnum; 645 | u16 regDmn5G; 646 | u16 regDmn2G; 647 | u8 isMultidomain; 648 | u8 iso[3]; 649 | }; 650 | /* 651 | struct eeprom_ops { 652 | int (*check_eeprom)(struct ath_hw *hw); 653 | u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 654 | bool (*fill_eeprom)(struct ath_hw *hw); 655 | u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, 656 | u32 len, u32 size); 657 | int (*get_eeprom_ver)(struct ath_hw *hw); 658 | int (*get_eeprom_rev)(struct ath_hw *hw); 659 | void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 660 | void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 661 | void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 662 | u16 cfgCtl, u8 twiceAntennaReduction, 663 | u8 powerLimit, bool test); 664 | u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 665 | }; 666 | 667 | void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 668 | void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 669 | u32 shift, u32 val); 670 | int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 671 | int16_t targetLeft, 672 | int16_t targetRight); 673 | bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 674 | u16 *indexL, u16 *indexR); 675 | bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 676 | void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, 677 | int eep_start_loc, int size); 678 | void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 679 | u8 *pVpdList, u16 numIntercepts, 680 | u8 *pRetVpdList); 681 | void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 682 | struct ath9k_channel *chan, 683 | struct cal_target_power_leg *powInfo, 684 | u16 numChannels, 685 | struct cal_target_power_leg *pNewPower, 686 | u16 numRates, bool isExtTarget); 687 | void ath9k_hw_get_target_powers(struct ath_hw *ah, 688 | struct ath9k_channel *chan, 689 | struct cal_target_power_ht *powInfo, 690 | u16 numChannels, 691 | struct cal_target_power_ht *pNewPower, 692 | u16 numRates, bool isHt40Target); 693 | u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 694 | bool is2GHz, int num_band_edges); 695 | u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, 696 | u8 antenna_reduction); 697 | void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 698 | int ath9k_hw_eeprom_init(struct ath_hw *ah); 699 | 700 | void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 701 | struct ath9k_channel *chan, 702 | void *pRawDataSet, 703 | u8 *bChans, u16 availPiers, 704 | u16 tPdGainOverlap, 705 | u16 *pPdGainBoundaries, 706 | u8 *pPDADCValues, 707 | u16 numXpdGains); 708 | */ 709 | static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 710 | { 711 | if (fbin == AR5416_BCHAN_UNUSED) 712 | return fbin; 713 | 714 | return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 715 | } 716 | 717 | #define ar5416_get_ntxchains(_txchainmask) \ 718 | (((_txchainmask >> 2) & 1) + \ 719 | ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 720 | 721 | extern const struct eeprom_ops eep_def_ops; 722 | extern const struct eeprom_ops eep_4k_ops; 723 | extern const struct eeprom_ops eep_ar9287_ops; 724 | extern const struct eeprom_ops eep_ar9287_ops; 725 | extern const struct eeprom_ops eep_ar9300_ops; 726 | 727 | #endif /* EEPROM_H */ 728 | -------------------------------------------------------------------------------- /ar9300_eeprom/include/types.h: -------------------------------------------------------------------------------- 1 | #ifndef TYPES_H 2 | #define TYPES_H 3 | 4 | typedef signed char s8; 5 | typedef short s16; 6 | typedef int s32; 7 | 8 | typedef unsigned char u8; 9 | typedef unsigned short u16; 10 | typedef unsigned int u32; 11 | 12 | typedef s8 int8_t; 13 | typedef s16 int16_t; 14 | 15 | typedef u16 __le16; 16 | typedef u32 __le32; 17 | 18 | #ifndef __cplusplus 19 | #define true 1 20 | #define false 0 21 | typedef int bool; 22 | #endif 23 | 24 | #ifdef __GNUC__ 25 | #define __packed __attribute__((packed)) 26 | #endif 27 | 28 | #ifdef _MSC_VER 29 | #define __packed 30 | #ifndef __cplusplus 31 | #define inline __inline 32 | #endif 33 | #endif 34 | 35 | #endif //TYPES_H 36 | -------------------------------------------------------------------------------- /ar9300_eeprom/include/wdr4300.h: -------------------------------------------------------------------------------- 1 | #define WDR4300_WMAC_CALDATA_OFFSET 0x1000 2 | #define WDR4300_PCIE_CALDATA_OFFSET 0x5000 3 | 4 | const static struct default_detect_data wdr4310_v1_0_2050500271_rev1_3_data[AR9300_MAX_EEPROMS] = { 5 | { 6 | { 48, 0 }, 7 | 8 | true, 9 | { FREQ2FBIN(2412, 1), FREQ2FBIN(2437, 1), FREQ2FBIN(2462, 1) }, 10 | { 11 | { { 11, 0, 157, 0, 0, 0 }, { 11, 0, 158, 0, 0, 0 }, { 10, 0, 158, 0, 0, 0 } }, 12 | { { 12, 0, 162, 0, 0, 0 }, { 13, 0, 162, 0, 0, 0 }, { 13, 0, 162, 0, 0, 0 } }, 13 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } } 14 | }, 15 | 16 | false, 17 | { 0, 0, 0, 0, 0, 0, 0, 0 }, 18 | { 19 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 20 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 21 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 22 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 23 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 24 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } } 25 | } 26 | }, 27 | 28 | { 29 | { 72, 0 }, 30 | 31 | false, 32 | { 0, 0, 0 }, 33 | { 34 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 35 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 36 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } } 37 | }, 38 | 39 | true, 40 | { 41 | FREQ2FBIN(5745, 0), FREQ2FBIN(5825, 0), FREQ2FBIN(5320, 0), FREQ2FBIN(5400, 0), 42 | FREQ2FBIN(5500, 0), FREQ2FBIN(5600, 0), FREQ2FBIN(5725, 0), FREQ2FBIN(5825, 0) 43 | }, 44 | { 45 | { { -16, 0, 175, 0, 0, 0 }, { -22, 0, 177, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 46 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 47 | { { -19, 0, 176, 0, 0, 0 }, { -25, 0, 177, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 48 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 49 | { { -17, 0, 177, 0, 0, 0 }, { -24, 0, 177, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, 50 | { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } } 51 | } 52 | }, 53 | }; 54 | 55 | const static struct ar9300_fixup wdr4310_v1_0_2050500271_rev1_3_fixup = { 56 | "Fix up calibration incomplete 5GHz, only works between 5745[149] and 5825[165]. Warning: fix up used inaccurate values (interpolated). Version 1.", 57 | 58 | false, 59 | { 0, 0, 0 }, 60 | { 61 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 62 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } }, 63 | { { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 }, { 0, 0, 0, 0, 0, 0 } } 64 | }, 65 | 66 | true, 67 | { 68 | FREQ2FBIN(5180, 0), FREQ2FBIN(5240, 0), FREQ2FBIN(5320, 0), FREQ2FBIN(5500, 0), 69 | FREQ2FBIN(5620, 0), FREQ2FBIN(5700, 0), FREQ2FBIN(5745, 0), FREQ2FBIN(5825, 0) 70 | }, 71 | { 72 | { { -24, 0, 176, 0, 0, 0 }, { -19, 0, 176, 0, 0, 0 }, { -14, 0, 177, 0, 0, 0 }, { -10, 0, 176, 0, 0, 0 }, 73 | { -10, 0, 177, 0, 0, 0 }, { -13, 0, 176, 0, 0, 0 }, { -16, 0, 175, 0, 0, 0 }, { -22, 0, 177, 0, 0, 0 } }, 74 | { { -26, 0, 176, 0, 0, 0 }, { -21, 0, 177, 0, 0, 0 }, { -16, 0, 177, 0, 0, 0 }, { -12, 0, 177, 0, 0, 0 }, 75 | { -12, 0, 176, 0, 0, 0 }, { -15, 0, 177, 0, 0, 0 }, { -19, 0, 176, 0, 0, 0 }, { -25, 0, 177, 0, 0, 0 } }, 76 | { { -25, 0, 177, 0, 0, 0 }, { -20, 0, 177, 0, 0, 0 }, { -15, 0, 178, 0, 0, 0 }, { -11, 0, 177, 0, 0, 0 }, 77 | { -11, 0, 178, 0, 0, 0 }, { -14, 0, 178, 0, 0, 0 }, { -17, 0, 177, 0, 0, 0 }, { -24, 0, 177, 0, 0, 0 } } 78 | } 79 | }; 80 | 81 | const static struct ar9300_revision wdr4310_v1_0_2050500271_rev1_3 = { 82 | "TL-WDR4310", "1.0", "2050500271", "1.3", &wdr4310_v1_0_2050500271_rev1_3_fixup, default_detect, &wdr4310_v1_0_2050500271_rev1_3_data 83 | }; 84 | 85 | const static struct ar9300_detect wdr4300_detect = { 86 | "TL-WDR3600/4300/4310", { { WDR4300_WMAC_CALDATA_OFFSET, WDR4300_PCIE_CALDATA_OFFSET } }, { &wdr4310_v1_0_2050500271_rev1_3, NULL } 87 | }; 88 | -------------------------------------------------------------------------------- /ar9300_eeprom/src/ar9300_eeprom.c: -------------------------------------------------------------------------------- 1 | #ifdef _MSC_VER 2 | #define _CRT_SECURE_NO_WARNINGS 3 | #endif 4 | 5 | #include 6 | #include 7 | 8 | #include "ar9300_eeprom.h" 9 | #include "wdr4300.h" 10 | 11 | const static struct ar9300_detect *ar9300_detects[] = { 12 | &wdr4300_detect, 13 | NULL 14 | }; 15 | 16 | const static struct ar9300_layout layout0 = { 17 | { 0x1000, 0x5000 } 18 | }; 19 | 20 | const static struct ar9300_layout *layouts[] = { 21 | &layout0, 22 | NULL 23 | }; 24 | 25 | static char buffer[64*1024]; 26 | static struct ar9300_eeprom eeproms[AR9300_MAX_EEPROMS]; 27 | 28 | int main(int argc, char *argv[]) 29 | { 30 | int i; 31 | int j; 32 | int l; 33 | int offset; 34 | int len = 0; 35 | int ret = -1; 36 | bool err = false; 37 | bool dump = false; 38 | char *option = ""; 39 | bool found = false; 40 | bool update = false; 41 | int use_layout = -1; 42 | char *outname = NULL; 43 | char *filename = NULL; 44 | const struct ar9300_layout *layout; 45 | const struct ar9300_detect *detect; 46 | const struct ar9300_revision *revision; 47 | 48 | for (i = 1; !err && i < argc; i++) 49 | { 50 | if (argv[i][0] == '-') 51 | { 52 | option = &argv[i][1]; 53 | if (!dump && !strcmp(option, "d")) 54 | { 55 | dump = true; 56 | continue; 57 | } 58 | if (!update && !strcmp(option, "u")) 59 | { 60 | update = true; 61 | continue; 62 | } 63 | if (use_layout < 0 && !strcmp(option, "y0")) 64 | { 65 | use_layout = 0; 66 | continue; 67 | } 68 | err = true; 69 | printf("\nInvalid option: '%s'.\n", argv[i]); 70 | } 71 | else 72 | { 73 | if (outname == NULL && !strcmp(option, "u")) 74 | { 75 | outname = argv[i]; 76 | continue; 77 | } 78 | if (filename == NULL) 79 | { 80 | filename = argv[i]; 81 | continue; 82 | } 83 | err = true; 84 | printf("\nInvalid parameter: '%s'.\n", argv[i]); 85 | } 86 | } 87 | 88 | if (!err && filename == NULL) 89 | { 90 | err = true; 91 | puts("\nBinary image file of 'art' partition not specified."); 92 | } 93 | if (!err && update && outname == NULL) 94 | { 95 | err = true; 96 | puts("\nOutput binary image file 'art' not specified."); 97 | } 98 | if (!err && dump && update) 99 | { 100 | err = true; 101 | puts("\nDump and update can not be specified together."); 102 | } 103 | if (err) 104 | goto print; 105 | 106 | l = (use_layout >= 0) ? use_layout : 0; 107 | while (!found && (layout = layouts[l++]) != NULL) 108 | { 109 | if ((ret = read_eeproms(eeproms, layout, filename)) < 0) 110 | goto print; 111 | 112 | if (ret < AR9300_MAX_EEPROMS) 113 | { 114 | if (use_layout < 0) 115 | continue; 116 | 117 | printf("\nSmall file: '%s'.\n", filename); 118 | goto print; 119 | } 120 | 121 | i = 0; 122 | while (!found && (detect = ar9300_detects[i++]) != NULL) 123 | { 124 | if (memcmp(&detect->layout, layout, sizeof(struct ar9300_layout))) 125 | continue; 126 | 127 | j = 0; 128 | while (!found && (revision = detect->revisions[j++]) != NULL) 129 | found = revision->detect(eeproms, revision->data); 130 | } 131 | 132 | if (use_layout >= 0) 133 | break; 134 | } 135 | 136 | if (!found) 137 | { 138 | if (ret < AR9300_MAX_EEPROMS) 139 | { 140 | printf("\nSmall file: '%s'.\n", filename); 141 | goto print; 142 | } 143 | 144 | puts("Board not detected."); 145 | 146 | if (use_layout < 0) 147 | return 1; 148 | } 149 | else 150 | printf("Hardware: %s Model: %s ver. %s Board: %s rev. %s\n", 151 | detect->name, revision->name, revision->version, revision->number, revision->revision); 152 | 153 | for (i = 0; i < AR9300_MAX_EEPROMS && (offset = layout->offsets[i]) >= 0; i++) 154 | { 155 | struct ar9300_eeprom *eeprom = &eeproms[i]; 156 | if (dump) 157 | { 158 | len += sprintf(buffer + len, "\nEEPROM 0x%4.4X:\n", offset); 159 | len = dump_eeprom(eeprom, buffer, len); 160 | } 161 | if (update) 162 | { 163 | bool allow2G = !!(eeprom->baseEepHeader.opCapFlags.opFlags & AR5416_OPFLAGS_11G); 164 | bool allow5G = !!(eeprom->baseEepHeader.opCapFlags.opFlags & AR5416_OPFLAGS_11A); 165 | printf("\nUpdate EEPROM 0x%4.4X:\n", offset); 166 | if (found && revision->fixup != NULL) 167 | { 168 | const struct ar9300_fixup *fixup = revision->fixup; 169 | if (allow2G && fixup->allow2G) 170 | { 171 | puts("\nFix up 2.4GHz."); 172 | memcpy(eeprom->calFreqPier2G, fixup->calFreqPier2G, sizeof(eeprom->calFreqPier2G)); 173 | memcpy(eeprom->calPierData2G, fixup->calPierData2G, sizeof(eeprom->calPierData2G)); 174 | } 175 | if (allow5G && fixup->allow5G) 176 | { 177 | puts("\nFix up 5GHz."); 178 | memcpy(eeprom->calFreqPier5G, fixup->calFreqPier5G, sizeof(eeprom->calFreqPier5G)); 179 | memcpy(eeprom->calPierData5G, fixup->calPierData5G, sizeof(eeprom->calPierData5G)); 180 | } 181 | } 182 | if (allow2G) 183 | { 184 | int c; 185 | puts("\nUpdate regulatory 2.4GHz."); 186 | for (c = 0; c < AR9300_NUM_CTLS_2G; c++) 187 | { 188 | int e; 189 | for (e = 0; e < AR9300_NUM_BAND_EDGES_2G; e++) 190 | eeprom->ctlPowerData_2G[c].ctlEdges[e] = CTL(60, CTL_EDGE_FLAGS(eeprom->ctlPowerData_2G[c].ctlEdges[e])); 191 | } 192 | } 193 | if (allow5G) 194 | { 195 | int c; 196 | puts("\nUpdate regulatory 5GHz."); 197 | for (c = 0; c < AR9300_NUM_CTLS_5G; c++) 198 | { 199 | int e; 200 | for (e = 0; e < AR9300_NUM_BAND_EDGES_5G; e++) 201 | eeprom->ctlPowerData_5G[c].ctlEdges[e] = CTL(60, CTL_EDGE_FLAGS(eeprom->ctlPowerData_5G[c].ctlEdges[e])); 202 | } 203 | } 204 | 205 | } 206 | } 207 | 208 | if (found && revision->fixup != NULL) 209 | { 210 | if (dump) 211 | { 212 | len += sprintf(buffer + len, "\n%s\n", revision->fixup->info); 213 | len = dump_fixup((struct ar9300_fixup *)revision->fixup, buffer, len); 214 | } 215 | else 216 | printf("\n%s\n", revision->fixup->info); 217 | } 218 | 219 | if (dump) 220 | puts(buffer); 221 | 222 | if (update) 223 | write_eeproms(eeproms, layout, filename, outname); 224 | 225 | return 0; 226 | 227 | print: 228 | puts("\nUsage: ar9300_eeprom [-d|-y0] ART_FILE [-u OUT_FILE]\n\n\t\ 229 | -d: dump eeprom.\n\t\ 230 | -u: update eeprom.\n\t\ 231 | -y0: use layout 0 - eeprom in 0x1000 and eeprom in 0x5000.\n\n\t\ 232 | ART_FILE: 64KB binary image file of 'art' partition.\n\t\ 233 | OUT_FILE: updated binary image file 'art'.\n"); 234 | 235 | return 1; 236 | } 237 | -------------------------------------------------------------------------------- /ar9300_eeprom/src/detect_eeprom.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include "ar9300_eeprom.h" 4 | 5 | bool default_detect(struct ar9300_eeprom eeproms[], const void *data) 6 | { 7 | int i; 8 | 9 | for (i = 0; i < AR9300_MAX_EEPROMS; i++) 10 | { 11 | const struct ar9300_eeprom *eeprom = &eeproms[i]; 12 | const struct default_detect_data *ddd = &((struct default_detect_data *)data)[i]; 13 | if (!ddd->allow2G && !ddd->allow5G) 14 | return true; 15 | 16 | if (!(memcmp(ddd->params_for_tuning_caps, eeprom->baseEepHeader.params_for_tuning_caps, sizeof(ddd->params_for_tuning_caps)) == 0 && 17 | ddd->allow2G == !!(eeprom->baseEepHeader.opCapFlags.opFlags & AR5416_OPFLAGS_11G) && 18 | (!ddd->allow2G || memcmp(ddd->calFreqPier2G, eeprom->calFreqPier2G, sizeof(ddd->calFreqPier2G)) == 0) && 19 | (!ddd->allow2G || memcmp(ddd->calPierData2G, eeprom->calPierData2G, sizeof(ddd->calPierData2G)) == 0) && 20 | ddd->allow5G == !!(eeprom->baseEepHeader.opCapFlags.opFlags & AR5416_OPFLAGS_11A) && 21 | (!ddd->allow5G || memcmp(ddd->calFreqPier5G, eeprom->calFreqPier5G, sizeof(ddd->calFreqPier5G)) == 0) && 22 | (!ddd->allow5G || memcmp(ddd->calPierData5G, eeprom->calPierData5G, sizeof(ddd->calPierData5G)) == 0))) 23 | return false; 24 | } 25 | 26 | return true; 27 | } 28 | -------------------------------------------------------------------------------- /ar9300_eeprom/src/dump_eeprom.c: -------------------------------------------------------------------------------- 1 | #ifdef _MSC_VER 2 | #define _CRT_SECURE_NO_WARNINGS 3 | #endif 4 | 5 | #include 6 | #include 7 | 8 | #include "ar9300_eeprom.h" 9 | 10 | #define BUFSIZE 1024 11 | 12 | #define BIT(nr) (1UL << (nr)) 13 | 14 | #define le16_to_cpu(x) ((u16)(x)) 15 | #define le32_to_cpu(x) ((u32)(x)) 16 | 17 | #define PR_NL() len += sprintf(buf + len, "\n") 18 | #define PR_HDR(_s) len += sprintf(buf + len, "%20s :\n", _s) 19 | #define PR_DSC(_s, _d) len += sprintf(buf + len, "%20s :%s\n", _s, _d) 20 | #define PR_VAL(_s, _val) len += sprintf(buf + len, "%20s : %10d\n", _s, _val) 21 | #define PR_SEP() len += sprintf(buf + len, "----------------------------------------------------------------------------------------\n") 22 | #define PR_SEPVAL() len += sprintf(buf + len, "---------------------------------\n") 23 | 24 | #define PR_BTS(_s, _val) \ 25 | do { \ 26 | bits2str(buf2, _val, 8 * sizeof(_val)); \ 27 | len += sprintf(buf + len, "%20s : 0b%s\n", _s, buf2); \ 28 | } while (0) 29 | 30 | #define PR_HEX(_s, _val) \ 31 | do { \ 32 | switch (sizeof(_val)) \ 33 | { \ 34 | case 1: \ 35 | len += sprintf(buf + len, "%20s : 0x%2.2X\n", _s, _val); \ 36 | break; \ 37 | case 2: \ 38 | len += sprintf(buf + len, "%20s : 0x%4.4X\n", _s, le16_to_cpu(_val)); \ 39 | break; \ 40 | case 4: \ 41 | len += sprintf(buf + len, "%20s : 0x%8.8X\n", _s, le32_to_cpu(_val)); \ 42 | break; \ 43 | default: \ 44 | len += sprintf(buf + len, "%20s : 0x????????\n", _s); \ 45 | break; \ 46 | } \ 47 | } while (0) 48 | 49 | #define PR_HEXS(_s, _val, _step, _start) \ 50 | do { \ 51 | int _i; \ 52 | len += sprintf(buf + len, "%20s :", _s); \ 53 | switch (sizeof(_val[0])) \ 54 | { \ 55 | case 1: \ 56 | for (_i = 0; _i < sizeof(_val); _i++) \ 57 | len += sprintf(buf + len, "%*s0x%2.2X", ((_i == 0) ? _step + _start : _step) - 4, "", _val[_i]); \ 58 | break; \ 59 | case 2: \ 60 | for (_i = 0; _i < sizeof(_val) / 2; _i++) \ 61 | len += sprintf(buf + len, "%*s0x%4.4X", ((_i == 0) ? _step + _start : _step) - 6, "", le16_to_cpu(_val[_i])); \ 62 | break; \ 63 | case 4: \ 64 | for (_i = 0; _i < sizeof(_val) / 4; _i++) \ 65 | len += sprintf(buf + len, "%*s0x%8.8X", ((_i == 0) ? _step + _start : _step) - 10, "", le32_to_cpu(_val[_i])); \ 66 | break; \ 67 | default: \ 68 | len += sprintf(buf + len, "0x????????"); \ 69 | break; \ 70 | } \ 71 | len += sprintf(buf + len, "\n"); \ 72 | } while (0) 73 | 74 | #define PR_VALS(_s, _val, _step, _start) \ 75 | do { \ 76 | int _i; \ 77 | len += sprintf(buf + len, "%20s :", _s); \ 78 | switch (sizeof(_val[0])) \ 79 | { \ 80 | case 1: \ 81 | for (_i = 0; _i < sizeof(_val); _i++) \ 82 | len += sprintf(buf + len, "%*d", (_i == 0) ? _step + _start : _step, _val[_i]); \ 83 | break; \ 84 | case 2: \ 85 | for (_i = 0; _i < sizeof(_val) / 2; _i++) \ 86 | len += sprintf(buf + len, "%*d", (_i == 0) ? _step + _start : _step, le16_to_cpu(_val[_i])); \ 87 | break; \ 88 | case 4: \ 89 | for (_i = 0; _i < sizeof(_val) / 4; _i++) \ 90 | len += sprintf(buf + len, "%*d", (_i == 0) ? _step + _start : _step, le32_to_cpu(_val[_i])); \ 91 | break; \ 92 | default: \ 93 | len += sprintf(buf + len, "????????"); \ 94 | break; \ 95 | } \ 96 | len += sprintf(buf + len, "\n"); \ 97 | } while (0) 98 | 99 | #define PR_LMH(_s, _l, _m, _h, _step) \ 100 | do { \ 101 | switch (sizeof(_l)) \ 102 | { \ 103 | case 1: \ 104 | len += sprintf(buf + len, "%20s :%*d%*d%*d\n", _s, _step, _l, _step, _m, _step, _h); \ 105 | break; \ 106 | case 2: \ 107 | len += sprintf(buf + len, "%20s :%*d%*d%*d\n", _s, _step, le16_to_cpu(_l), _step, le16_to_cpu(_m), _step, le16_to_cpu(_h)); \ 108 | break; \ 109 | case 4: \ 110 | len += sprintf(buf + len, "%20s :%*d%*d%*d\n", _s, _step, le32_to_cpu(_l), _step, le32_to_cpu(_m), _step, le32_to_cpu(_h)); \ 111 | break; \ 112 | default: \ 113 | len += sprintf(buf + len, "%20s :????????\n", _s); \ 114 | break; \ 115 | } \ 116 | } while (0) 117 | 118 | #define PR_LMHs(_s, _l, _m, _h, _step) \ 119 | do { \ 120 | int _i; \ 121 | len += sprintf(buf + len, "%20s :", _s); \ 122 | switch (sizeof(_l[0])) \ 123 | { \ 124 | case 1: \ 125 | for (_i = 0; _i < sizeof(_l); _i++) \ 126 | len += sprintf(buf + len, "%*d%*d%*d", _step, _l[_i], _step, _m[_i], _step, _h[_i]); \ 127 | break; \ 128 | case 2: \ 129 | for (_i = 0; _i < sizeof(_l) / 2; _i++) \ 130 | len += sprintf(buf + len, "%*d%*d%*d", _step, le16_to_cpu(_l[_i]), _step, le16_to_cpu(_m[_i]), _step, le16_to_cpu(_h[_i])); \ 131 | break; \ 132 | case 4: \ 133 | for (_i = 0; _i < sizeof(_l) / 4; _i++) \ 134 | len += sprintf(buf + len, "%*d%*d%*d", _step, le32_to_cpu(_l[_i]), _step, le32_to_cpu(_m[_i]), _step, le32_to_cpu(_h[_i])); \ 135 | break; \ 136 | default: \ 137 | len += sprintf(buf + len, "????????"); \ 138 | break; \ 139 | } \ 140 | len += sprintf(buf + len, "\n"); \ 141 | } while (0) 142 | 143 | #define PR_DMP(_s, _val) \ 144 | do { \ 145 | int _i; \ 146 | len += sprintf(buf + len, "%20s :", _s); \ 147 | for (_i = 0; _i < sizeof(_val); _i++) \ 148 | len += sprintf(buf + len, " %2.2X", ((u8*)(_val))[_i]); \ 149 | len += sprintf(buf + len, "\n"); \ 150 | } while (0) 151 | 152 | #define PR_FREQ(_s, _val, _idx, _is2GHz) \ 153 | do { \ 154 | u32 _v = _val[_idx]; \ 155 | sprintf(buf2, "%s %d", _s, _idx); \ 156 | len += sprintf(buf + len, "%20s :", buf2); \ 157 | if (_v == 0 || _v == 0xff) \ 158 | sprintf(buf2, "0x%2.2X\n", _v); \ 159 | else \ 160 | { \ 161 | u32 _freq = FBIN2FREQ(_v, _is2GHz); \ 162 | int _chn = freq2chn(_freq); \ 163 | if (_chn < 0) \ 164 | sprintf(buf2, "%4.4d[%d+]\n", _freq, -_chn); \ 165 | else \ 166 | sprintf(buf2, "%4.4d[%d]\n", _freq, _chn); \ 167 | } \ 168 | len += sprintf(buf + len, "%12s", buf2); \ 169 | } while (0) 170 | 171 | #define PR_FREQS(_s, _val, _idx, _is2GHz, _step) \ 172 | do { \ 173 | int _i; \ 174 | int _size = sizeof((_val)[0]); \ 175 | if (_idx < 0) \ 176 | len += sprintf(buf + len, "%20s :", _s); \ 177 | else \ 178 | { \ 179 | sprintf(buf2, "%s %d", _s, _idx); \ 180 | len += sprintf(buf + len, "%20s :", buf2); \ 181 | } \ 182 | for (_i = (_idx >= 0) ? _idx : 0; _i < sizeof(_val); _i += _size) \ 183 | { \ 184 | u32 _v = ((u8*)(_val))[_i]; \ 185 | if (_v == 0 || _v == 0xff) \ 186 | sprintf(buf2, "0x%2.2X", _v); \ 187 | else \ 188 | { \ 189 | u32 _freq = FBIN2FREQ(_v, _is2GHz); \ 190 | int _chn = freq2chn(_freq); \ 191 | if (_chn < 0) \ 192 | sprintf(buf2, "%4.4d[%d+]", _freq, -_chn); \ 193 | else \ 194 | sprintf(buf2, "%4.4d[%d]", _freq, _chn); \ 195 | } \ 196 | len += sprintf(buf + len, "%*s", _step, buf2); \ 197 | } \ 198 | len += sprintf(buf + len, "\n"); \ 199 | } while (0) 200 | 201 | #define PR_PIER(_s, _v, _i) \ 202 | do { \ 203 | sprintf(buf2, "%s %d", _s, pier); \ 204 | len += sprintf(buf + len, "%20s :%7d%7d%7d\n", buf2, _v[0][pier]._i, _v[1][pier]._i, _v[2][pier]._i); \ 205 | } while (0) 206 | 207 | #define PR_PWRLEG(_s, _val, _idx) \ 208 | do { \ 209 | struct cal_tgt_pow_legacy _v; \ 210 | _v = _val[_idx]; \ 211 | sprintf(buf2, "%s %d", _s, _idx); \ 212 | len += sprintf(buf + len, "%20s :%5d%5d%5d%5d\n", buf2, _v.tPow2x[0], _v.tPow2x[1], _v.tPow2x[2], _v.tPow2x[3]); \ 213 | } while (0) 214 | 215 | #define PR_PWRHT(_s, _val, _idx) \ 216 | do { \ 217 | struct cal_tgt_pow_ht _v; \ 218 | _v = _val[_idx]; \ 219 | sprintf(buf2, "%s %d", _s, _idx); \ 220 | len += sprintf(buf + len, "%20s :%4d%4d%4d%4d%4d%4d%4d%4d%4d%4d%4d%4d%4d%4d\n", buf2, \ 221 | _v.tPow2x[0], _v.tPow2x[1], _v.tPow2x[2], _v.tPow2x[3], _v.tPow2x[4], _v.tPow2x[5], _v.tPow2x[6], _v.tPow2x[7], \ 222 | _v.tPow2x[8], _v.tPow2x[9], _v.tPow2x[10], _v.tPow2x[11], _v.tPow2x[12], _v.tPow2x[13]); \ 223 | } while (0) 224 | 225 | #define PR_PWRIDX(_s, _val, _idx, _be, _af) \ 226 | do { \ 227 | int _i; \ 228 | int _size = sizeof((_val)[0]); \ 229 | sprintf(buf2, "%s %d", _s, _idx); \ 230 | len += sprintf(buf + len, "%20s :", buf2); \ 231 | for (_i = _idx; _i < sizeof(_val); _i += _size) \ 232 | { \ 233 | u32 _v = ((u8*)(_val))[_i]; \ 234 | len += sprintf(buf + len, _be "%2.2d|%1.1d" _af, CTL_EDGE_TPOWER(_v), CTL_EDGE_FLAGS(_v)); \ 235 | } \ 236 | len += sprintf(buf + len, "\n"); \ 237 | } while (0) 238 | 239 | #define PR_CTL(_s, _val, _step) \ 240 | do { \ 241 | int _i; \ 242 | len += sprintf(buf + len, "%20s :", _s); \ 243 | for (_i = 0; _i < sizeof(_val); _i++) \ 244 | { \ 245 | len += sprintf(buf + len, "%*s", _step - 8, ""); \ 246 | len += ctl2str(buf + len, _val[_i]); \ 247 | } \ 248 | len += sprintf(buf + len, "\n"); \ 249 | } while (0) 250 | 251 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) 252 | 253 | #define PR_RTS(_s, _val, _isHT20, _is2GHz) \ 254 | do { \ 255 | int _i; \ 256 | u32 _m; \ 257 | len += sprintf(buf + len, "%20s :", _s); \ 258 | _m = 1 << 0; \ 259 | for (_i = 0; _i < 25; _i++, _m += _m) \ 260 | { \ 261 | if (_val & _m) \ 262 | len += sprintf(buf + len, " %s", rates[_i]); \ 263 | } \ 264 | if (_isHT20) \ 265 | { \ 266 | if (_is2GHz) \ 267 | len += sprintf(buf + len, " SCALE:%d", MS(_val, AR9300_PAPRD_SCALE_1)); \ 268 | else \ 269 | len += sprintf(buf + len, " HIGH_SCALE:%d", MS(_val, AR9300_PAPRD_SCALE_1)); \ 270 | _m = 1 << 28; \ 271 | for (_i = 28; _i < 32; _i++, _m += _m) \ 272 | { \ 273 | if (_val & _m) \ 274 | { \ 275 | if (_is2GHz) \ 276 | len += sprintf(buf + len, " BIT%d", _i); \ 277 | else \ 278 | len += sprintf(buf + len, " %s", rates[_i]); \ 279 | } \ 280 | } \ 281 | } \ 282 | else \ 283 | if (_is2GHz) \ 284 | { \ 285 | _m = 1 << 25; \ 286 | for (_i = 25; _i < 32; _i++, _m += _m) \ 287 | { \ 288 | if (_val & _m) \ 289 | len += sprintf(buf + len, " BIT%d", _i); \ 290 | } \ 291 | } \ 292 | else \ 293 | { \ 294 | len += sprintf(buf + len, " LOW_SCALE:%d", MS(_val, AR9300_PAPRD_SCALE_1)); \ 295 | len += sprintf(buf + len, " MID_SCALE:%d", MS(_val, AR9300_PAPRD_SCALE_2)); \ 296 | if (_val & (1 << 31)) \ 297 | len += sprintf(buf + len, " BIT%d", 31); \ 298 | } \ 299 | len += sprintf(buf + len, "\n"); \ 300 | } while (0) 301 | 302 | const char *rates[] = 303 | { 304 | "6_24", "36", "48", "54", "1L_5L", "5S", "11L", "11S", "HT20_0_8_16", "HT20_1_3_9_11_17_19", "HT20_4", "HT20_5", "HT20_6", "HT20_7", 305 | "HT20_12", "HT20_13", "HT20_14", "HT20_15", "HT20_20", "HT20_21", "HT20_22", "HT20_23", "HT40_0_8_16", "HT40_1_3_9_11_17_19", "HT40_4", 306 | "BIT25", "BIT26", "BIT27", "LOW_SCALE_DIS", "MID_SCALE_DIS", "HIGH_SCALE_DIS", "BIT31" 307 | }; 308 | 309 | void bits2str(char *buf, u32 val, int bits) 310 | { 311 | u32 mask; 312 | buf[bits] = '\0'; 313 | memset(buf, '0', bits); 314 | for (mask = 1 << (bits - 1); val && mask; buf++, mask >>= 1) 315 | { 316 | if (val & mask) 317 | { 318 | val &= ~mask; 319 | *buf = '1'; 320 | } 321 | } 322 | } 323 | 324 | enum ctl_group { 325 | CTL_FCC = 0x10, 326 | CTL_MKK = 0x40, 327 | CTL_ETSI = 0x30, 328 | }; 329 | 330 | static int ctl2str(char *buf, u8 val) 331 | { 332 | switch (val & ~CTL_MODE_M) 333 | { 334 | case CTL_FCC: 335 | strcpy(buf, "FCC_"); 336 | break; 337 | case CTL_MKK: 338 | strcpy(buf, "MKK_"); 339 | break; 340 | case CTL_ETSI: 341 | strcpy(buf, "ETSI"); 342 | break; 343 | default: 344 | strcpy(buf, "???_"); 345 | break; 346 | } 347 | 348 | buf += 4; 349 | 350 | switch (val & CTL_MODE_M) 351 | { 352 | case CTL_11A: 353 | strcpy(buf, "_11A"); 354 | break; 355 | case CTL_11B: 356 | strcpy(buf, "_11B"); 357 | break; 358 | case CTL_11G: 359 | strcpy(buf, "_11G"); 360 | break; 361 | case CTL_2GHT20: 362 | case CTL_5GHT20: 363 | strcpy(buf, "HT20"); 364 | break; 365 | case CTL_2GHT40: 366 | case CTL_5GHT40: 367 | strcpy(buf, "HT40"); 368 | break; 369 | default: 370 | strcpy(buf, "_???"); 371 | break; 372 | } 373 | 374 | return 4 + 4; 375 | } 376 | 377 | struct channels { int chn; u32 freq; }; 378 | const struct channels chns[] = 379 | { 380 | { 1, 2412 }, { 2, 2417 }, { 3, 2422 }, { 4, 2427 }, { 5, 2432 }, { 6, 2437 }, { 7, 2442 }, 381 | { 8, 2447 }, { 9, 2452 }, { 10, 2457 }, { 11, 2462 }, { 12, 2467 }, { 13, 2472 }, { 14, 2484 }, 382 | { 184, 4920 }, { 185, 4925 }, { 187, 4935 }, { 188, 4940 }, { 189, 4945 }, { 192, 4960 }, { 196, 4980 }, 383 | { 7, 5035 }, { 8, 5040 }, { 9, 5045 }, { 11, 5055 }, { 12, 5060 }, { 16, 5080 }, { 34, 5170 }, 384 | { 36, 5180 }, { 38, 5190 }, { 40, 5200 }, { 42, 5210 }, { 44, 5220 }, { 46, 5230 }, { 48, 5240 }, 385 | { 52, 5260 }, { 56, 5280 }, { 60, 5300 }, { 64, 5320 }, { 100, 5500 }, { 104, 5520 }, { 108, 5540 }, 386 | { 112, 5560 }, { 116, 5580 }, { 120, 5600 }, { 124, 5620 }, { 128, 5640 }, { 132, 5660 }, { 136, 5680 }, 387 | { 140, 5700 }, { 149, 5745 }, { 153, 5765 }, { 157, 5785 }, { 161, 5805 }, { 165, 5825 } 388 | }; 389 | 390 | const int last_chn = (sizeof(chns) / sizeof(chns[0])) - 1; 391 | 392 | static int freq2chn(u32 freq) 393 | { 394 | u32 f; 395 | int i; 396 | int b = 0; 397 | int e = last_chn; 398 | while (b <= e) 399 | { 400 | if ((f = chns[(i = (b + e) >> 1)].freq) == freq) 401 | return chns[i].chn; 402 | 403 | if (f < freq) 404 | b = i + 1; 405 | else 406 | e = i - 1; 407 | } 408 | return -chns[e].chn; 409 | } 410 | 411 | static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, struct ar9300_modal_eep_header *modal_hdr, 412 | struct ar9300_BaseExtension_1 *baseExt1, struct ar9300_BaseExtension_2 *baseExt2, int is2GHz) 413 | { 414 | char buf2[BUFSIZE]; 415 | 416 | PR_SEP(); 417 | if (is2GHz) 418 | { 419 | PR_DSC("2.4GHz Modal Header", " Chain0 Chain1 Chain2"); 420 | PR_HEXS("Ant. Control", modal_hdr->antCtrlChain, 7, 0); 421 | PR_VALS("NF Threshold", modal_hdr->noiseFloorThreshCh, 7, 0); 422 | PR_VALS("xatten1DB", modal_hdr->xatten1DB, 7, 0); 423 | PR_VALS("xatten1Margin", modal_hdr->xatten1Margin, 7, 0); 424 | PR_VAL("Temp Slope", modal_hdr->tempSlope); 425 | PR_VAL("Quick Drop", modal_hdr->quick_drop); 426 | } 427 | else 428 | { 429 | PR_DSC("5GHz Modal Header", " Chain0 Chain1 Chain2"); 430 | PR_HEXS("Ant. Control", modal_hdr->antCtrlChain, 15, -5); 431 | PR_VALS("NF Threshold", modal_hdr->noiseFloorThreshCh, 15, -5); 432 | PR_DSC("Range Chain", " Low Mid High Low Mid High Low Mid High"); 433 | PR_LMHs("xatten1DB", baseExt2->xatten1DBLow, modal_hdr->xatten1DB, baseExt2->xatten1DBHigh, 5); 434 | PR_LMHs("xatten1Margin", baseExt2->xatten1MarginLow, modal_hdr->xatten1Margin, baseExt2->xatten1MarginHigh, 5); 435 | PR_DSC("Range", " Low Mid High"); 436 | PR_LMH("Temp Slope", baseExt2->tempSlopeLow, modal_hdr->tempSlope, baseExt2->tempSlopeHigh, 5); 437 | PR_LMH("Quick Drop", baseExt1->quick_drop_low, modal_hdr->quick_drop, baseExt1->quick_drop_high, 5); 438 | } 439 | 440 | PR_FREQS("spur Frequency", modal_hdr->spurChans, -1, is2GHz, 11); 441 | PR_HEX("Ant. Common Control", modal_hdr->antCtrlCommon); 442 | PR_HEX("Ant. Common Control2", modal_hdr->antCtrlCommon2); 443 | PR_VAL("Ant. Gain", modal_hdr->antennaGain); 444 | PR_VAL("Switch Settle", modal_hdr->switchSettling); 445 | PR_VAL("Volt Slope", modal_hdr->voltSlope); 446 | 447 | PR_VAL("txEndToXpaOff", modal_hdr->txEndToXpaOff); 448 | PR_VAL("txEndToRxOn", modal_hdr->txEndToRxOn); 449 | PR_VAL("XPA Bias Level", modal_hdr->xpaBiasLvl); 450 | PR_VAL("txFrameToDataStart", modal_hdr->txFrameToDataStart); 451 | PR_VAL("txFrameToPaOn", modal_hdr->txFrameToPaOn); 452 | PR_VAL("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); 453 | PR_VAL("txClip", modal_hdr->txClip); 454 | PR_VAL("ADC Desired Size", modal_hdr->adcDesiredSize); 455 | PR_VAL("Thresh62", modal_hdr->thresh62); 456 | PR_RTS("PAPRD Rate Mask", le32_to_cpu(modal_hdr->papdRateMaskHt20), 1, is2GHz); 457 | PR_RTS("PAPRD Rate Mask HT40", le32_to_cpu(modal_hdr->papdRateMaskHt40), 0, is2GHz); 458 | PR_VAL("switch com spdt", le16_to_cpu(modal_hdr->switchcomspdt)); 459 | PR_VAL("XLNA Bias Strength", modal_hdr->xlna_bias_strength); 460 | PR_DMP("Reserved", modal_hdr->reserved); 461 | PR_DMP("Future Modal", modal_hdr->futureModal); 462 | 463 | return len; 464 | } 465 | 466 | static u32 ar9300_cal_data_per_freq_op_loop_eeprom_2G(char *buf, u32 len, 467 | struct ar9300_cal_data_per_freq_op_loop data[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS], int pier) 468 | { 469 | char buf2[BUFSIZE]; 470 | 471 | PR_PIER("Ref Power", data, refPower); 472 | PR_PIER("Volt Meas", data, voltMeas); 473 | PR_PIER("Temp Meas", data, tempMeas); 474 | PR_PIER("RX Noisefloor Cal", data, rxNoisefloorCal); 475 | PR_PIER("RX Noisefloor Pwr", data, rxNoisefloorPower); 476 | PR_PIER("RX Temp Meas", data, rxTempMeas); 477 | 478 | return len; 479 | } 480 | 481 | static u32 ar9300_cal_data_per_freq_op_loop_eeprom_5G(char *buf, u32 len, 482 | struct ar9300_cal_data_per_freq_op_loop data[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS], int pier) 483 | { 484 | char buf2[BUFSIZE]; 485 | 486 | PR_PIER("Ref Power", data, refPower); 487 | PR_PIER("Volt Meas", data, voltMeas); 488 | PR_PIER("Temp Meas", data, tempMeas); 489 | PR_PIER("RX Noisefloor Cal", data, rxNoisefloorCal); 490 | PR_PIER("RX Noisefloor Pwr", data, rxNoisefloorPower); 491 | PR_PIER("RX Temp Meas", data, rxTempMeas); 492 | 493 | return len; 494 | } 495 | 496 | u32 dump_eeprom(struct ar9300_eeprom *eep, char *buf, u32 len) 497 | { 498 | int i; 499 | char buf2[BUFSIZE]; 500 | bool allow2G = true; 501 | bool allow5G = true; 502 | struct ar9300_base_eep_hdr *pBase; 503 | struct ar9300_BaseExtension_1 *pBaseExt1; 504 | 505 | PR_SEP(); 506 | PR_VAL("EEPROM Version", eep->eepromVersion); 507 | PR_VAL("Template Version", eep->templateVersion); 508 | PR_DMP("MAC Address", eep->macAddr); 509 | PR_DMP("Cust Data", eep->custData); 510 | 511 | pBase = &eep->baseEepHeader; 512 | 513 | #ifndef FULLDUMP 514 | allow2G = !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_11G); 515 | allow5G = !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_11A); 516 | #endif 517 | 518 | PR_SEP(); 519 | PR_VAL("RegDomain1", le16_to_cpu(pBase->regDmn[0])); 520 | PR_VAL("RegDomain2", le16_to_cpu(pBase->regDmn[1])); 521 | PR_BTS("TX Mask", (u8)(pBase->txrxMask >> 4)); 522 | PR_BTS("RX Mask", (u8)(pBase->txrxMask & 0x0f)); 523 | PR_SEPVAL(); 524 | PR_BTS("Op Flags", pBase->opCapFlags.opFlags); 525 | PR_VAL("Allow 2.4GHz", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_11G)); 526 | PR_VAL("Allow 5GHz", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_11A)); 527 | if (allow2G) 528 | { 529 | PR_VAL("Disable 2.4GHz HT20", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_N_2G_HT20)); 530 | PR_VAL("Disable 2.4GHz HT40", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_N_2G_HT40)); 531 | } 532 | if (allow5G) 533 | { 534 | PR_VAL("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_N_5G_HT20)); 535 | PR_VAL("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags & AR5416_OPFLAGS_N_5G_HT40)); 536 | } 537 | PR_SEPVAL(); 538 | PR_BTS("EEP Misc", pBase->opCapFlags.eepMisc); 539 | PR_VAL("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01)); 540 | PR_SEPVAL(); 541 | PR_VAL("RF Silent", pBase->rfSilent); 542 | PR_VAL("BT Option", pBase->blueToothOptions); 543 | PR_VAL("Device Cap", pBase->deviceCap); 544 | PR_VAL("Device Type", pBase->deviceType); 545 | PR_VAL("Power Table Offset", pBase->pwrTableOffset); 546 | PR_VALS("Tuning Caps", pBase->params_for_tuning_caps, 5, 1); 547 | PR_SEPVAL(); 548 | PR_BTS("Feature Enable", pBase->featureEnable); 549 | PR_VAL("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0))); 550 | PR_VAL("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1))); 551 | PR_VAL("Enable Fast Clock", !!(pBase->featureEnable & BIT(2))); 552 | PR_VAL("Enable Doubling", !!(pBase->featureEnable & BIT(3))); 553 | PR_VAL("Internal Regulator", !!(pBase->featureEnable & BIT(4))); 554 | PR_VAL("Enable PAPRD Scale", !!(pBase->featureEnable & BIT(5))); 555 | PR_VAL("Enable Tuning Caps", !!(pBase->featureEnable & BIT(6))); 556 | PR_VAL("XPA Timing Ctrl", !!(pBase->featureEnable & BIT(7))); 557 | PR_SEPVAL(); 558 | PR_BTS("Misc Configuration", pBase->miscConfiguration); 559 | PR_VAL("Driver Strength", !!(pBase->miscConfiguration & BIT(0))); 560 | PR_VAL("Thermometer", ((pBase->miscConfiguration >> 1) & 0x3) - 1); 561 | PR_VAL("Chain Mask Reduce", !!(pBase->miscConfiguration & BIT(3))); 562 | PR_VAL("Enable Quick Drop", !!(pBase->miscConfiguration & BIT(4))); 563 | PR_VAL("Temp Slope Extension", !!(pBase->miscConfiguration & BIT(5))); 564 | PR_VAL("Enable Bias Strength", !!(pBase->miscConfiguration & BIT(6))); 565 | PR_SEPVAL(); 566 | PR_VAL("Write Enable GPIO", pBase->eepromWriteEnableGpio); 567 | PR_VAL("WLAN Disable GPIO", pBase->wlanDisableGpio); 568 | PR_VAL("WLAN LED GPIO", pBase->wlanLedGpio); 569 | PR_VAL("Rx Band Select GPIO", pBase->rxBandSelectGpio); 570 | PR_VAL("Tx Gain", pBase->txrxgain >> 4); 571 | PR_VAL("Rx Gain", pBase->txrxgain & 0xf); 572 | PR_HEX("SW Reg", pBase->swreg); 573 | 574 | pBaseExt1 = &eep->base_ext1; 575 | 576 | PR_SEP(); 577 | PR_VAL("Ant Div Control", pBaseExt1->ant_div_control); 578 | PR_DMP("Future", pBaseExt1->future); 579 | PR_SEPVAL(); 580 | PR_BTS("Misc Enable", pBaseExt1->misc_enable); 581 | PR_VAL("TX Gain Cap", !!(pBaseExt1->misc_enable & BIT(0))); 582 | PR_VAL("Uncompress Checksum", !!(pBaseExt1->misc_enable & BIT(1))); 583 | if (allow2G) 584 | PR_VAL("MinCCApwr 2.4GHz", !!(pBaseExt1->misc_enable & BIT(2))); 585 | if (allow5G) 586 | { 587 | PR_VAL("MinCCApwr 5GHz", !!(pBaseExt1->misc_enable & BIT(3))); 588 | PR_SEPVAL(); 589 | PR_VALS("Temp Slope Extension", pBaseExt1->tempslopextension, 4, -1); 590 | } 591 | 592 | if (allow2G) 593 | { 594 | PR_SEP(); 595 | PR_DSC("Calibration 2.4GHz", " Chain0 Chain1 Chain2"); 596 | for (i = 0; i < AR9300_NUM_2G_CAL_PIERS; i++) 597 | { 598 | PR_NL(); 599 | PR_FREQ("Frequency", eep->calFreqPier2G, i, 1); 600 | len = ar9300_cal_data_per_freq_op_loop_eeprom_2G(buf, len, eep->calPierData2G, i); 601 | } 602 | 603 | PR_SEP(); 604 | PR_DSC("Target 2.4GHz 11B", " 1L-5L 5S 11L 11S"); 605 | for (i = 0; i < AR9300_NUM_2G_CCK_TARGET_POWERS; i++) 606 | { 607 | PR_NL(); 608 | PR_FREQ("Frequency", eep->calTarget_freqbin_Cck, i, 1); 609 | PR_PWRLEG("Power", eep->calTargetPowerCck, i); 610 | } 611 | 612 | PR_SEP(); 613 | PR_DSC("Target 2.4GHz 11G", " 6-24 36 48 54"); 614 | for (i = 0; i < AR9300_NUM_2G_20_TARGET_POWERS; i++) 615 | { 616 | PR_NL(); 617 | PR_FREQ("Frequency", eep->calTarget_freqbin_2G, i, 1); 618 | PR_PWRLEG("Power", eep->calTargetPower2G, i); 619 | } 620 | 621 | PR_SEP(); 622 | PR_DSC("Target 2.4GHz HT20", "0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23"); 623 | for (i = 0; i < AR9300_NUM_2G_20_TARGET_POWERS; i++) 624 | { 625 | PR_NL(); 626 | PR_FREQ("Frequency", eep->calTarget_freqbin_2GHT20, i, 1); 627 | PR_PWRHT("Power", eep->calTargetPower2GHT20, i); 628 | } 629 | 630 | PR_SEP(); 631 | PR_DSC("Target 2.4GHz HT40", "0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23"); 632 | for (i = 0; i < AR9300_NUM_2G_40_TARGET_POWERS; i++) 633 | { 634 | PR_NL(); 635 | PR_FREQ("Frequency", eep->calTarget_freqbin_2GHT40, i, 1); 636 | PR_PWRHT("Power", eep->calTargetPower2GHT40, i); 637 | } 638 | 639 | PR_SEP(); 640 | PR_CTL("Regulatory 2.4GHz", eep->ctlIndex_2G, 9); 641 | for (i = 0; i < AR9300_NUM_BAND_EDGES_2G; i++) 642 | { 643 | PR_NL(); 644 | PR_FREQS("Frequency", eep->ctl_freqbin_2G, i, 1, 9); 645 | PR_PWRIDX("Power|Edge", eep->ctlPowerData_2G, i, " ", " "); 646 | } 647 | } 648 | 649 | if (allow5G) 650 | { 651 | PR_SEP(); 652 | PR_DSC("Calibration 5GHz", " Chain0 Chain1 Chain2"); 653 | for (i = 0; i < AR9300_NUM_5G_CAL_PIERS; i ++) 654 | { 655 | PR_NL(); 656 | PR_FREQ("Frequency", eep->calFreqPier5G, i, 0); 657 | len = ar9300_cal_data_per_freq_op_loop_eeprom_5G(buf, len, eep->calPierData5G, i); 658 | } 659 | 660 | PR_SEP(); 661 | PR_DSC("Target 5GHz 11A", " 6-24 36 48 54"); 662 | for (i = 0; i < AR9300_NUM_5G_20_TARGET_POWERS; i++) 663 | { 664 | PR_NL(); 665 | PR_FREQ("Frequency", eep->calTarget_freqbin_5G, i, 0); 666 | PR_PWRLEG("Power", eep->calTargetPower5G, i); 667 | } 668 | 669 | PR_SEP(); 670 | PR_DSC("Target 5GHz HT20", "0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23"); 671 | for (i = 0; i < AR9300_NUM_5G_20_TARGET_POWERS; i++) 672 | { 673 | PR_NL(); 674 | PR_FREQ("Frequency", eep->calTarget_freqbin_5GHT20, i, 0); 675 | PR_PWRHT("Power", eep->calTargetPower5GHT20, i); 676 | } 677 | 678 | PR_SEP(); 679 | PR_DSC("Target 5GHz HT40", "0-16 1-19 4 5 6 7 12 13 14 15 20 21 22 23"); 680 | for (i = 0; i < AR9300_NUM_5G_40_TARGET_POWERS; i++) 681 | { 682 | PR_NL(); 683 | PR_FREQ("Frequency", eep->calTarget_freqbin_5GHT40, i, 0); 684 | PR_PWRHT("Power", eep->calTargetPower5GHT40, i); 685 | } 686 | 687 | PR_SEP(); 688 | PR_CTL("Regulatory 5GHz", eep->ctlIndex_5G, 10); 689 | for (i = 0; i < AR9300_NUM_BAND_EDGES_5G; i++) 690 | { 691 | PR_NL(); 692 | PR_FREQS("Frequency", eep->ctl_freqbin_5G, i, 0, 10); 693 | PR_PWRIDX("Power|Edge", eep->ctlPowerData_5G, i, " ", " "); 694 | } 695 | } 696 | 697 | if (allow2G) 698 | len = ar9003_dump_modal_eeprom(buf, len, &eep->modalHeader2G, pBaseExt1, &eep->base_ext2, 1); 699 | 700 | if (allow5G) 701 | { 702 | len = ar9003_dump_modal_eeprom(buf, len, &eep->modalHeader5G, pBaseExt1, &eep->base_ext2, 0); 703 | PR_SEP(); 704 | PR_DSC("Frequency", " Low Mid High"); 705 | PR_DSC("PAPRD Scale", " <5400 >=5400 >=5700"); 706 | PR_DSC("Other", " 5180 5500 5785"); 707 | } 708 | 709 | PR_SEP(); 710 | 711 | return len; 712 | } 713 | 714 | u32 dump_fixup(struct ar9300_fixup *fixup, char *buf, u32 len) 715 | { 716 | int i; 717 | char buf2[BUFSIZE]; 718 | 719 | PR_SEP(); 720 | PR_VAL("Allow 2.4GHz", fixup->allow2G); 721 | PR_VAL("Allow 5GHz", fixup->allow5G); 722 | if (fixup->allow2G) 723 | { 724 | PR_SEP(); 725 | PR_DSC("Calibration 2.4GHz", " Chain0 Chain1 Chain2"); 726 | for (i = 0; i < AR9300_NUM_2G_CAL_PIERS; i++) 727 | { 728 | PR_NL(); 729 | PR_FREQ("Frequency", fixup->calFreqPier2G, i, 1); 730 | len = ar9300_cal_data_per_freq_op_loop_eeprom_2G(buf, len, fixup->calPierData2G, i); 731 | } 732 | } 733 | 734 | if (fixup->allow5G) 735 | { 736 | PR_SEP(); 737 | PR_DSC("Calibration 5GHz", " Chain0 Chain1 Chain2"); 738 | for (i = 0; i < AR9300_NUM_5G_CAL_PIERS; i ++) 739 | { 740 | PR_NL(); 741 | PR_FREQ("Frequency", fixup->calFreqPier5G, i, 0); 742 | len = ar9300_cal_data_per_freq_op_loop_eeprom_5G(buf, len, fixup->calPierData5G, i); 743 | } 744 | } 745 | 746 | PR_SEP(); 747 | 748 | return len; 749 | } 750 | 751 | -------------------------------------------------------------------------------- /ar9300_eeprom/src/io_eeproms.c: -------------------------------------------------------------------------------- 1 | #ifdef _MSC_VER 2 | 3 | #define _CRT_SECURE_NO_WARNINGS 4 | 5 | #include 6 | 7 | #define open _open 8 | #define read _read 9 | #define write _write 10 | #define lseek _lseek 11 | #define close _close 12 | 13 | #endif 14 | 15 | #ifdef __GNUC__ 16 | 17 | #include 18 | 19 | #define O_BINARY 0 20 | 21 | #endif 22 | 23 | #include 24 | #include 25 | #include 26 | 27 | #include "ar9300_eeprom.h" 28 | 29 | int read_eeproms(struct ar9300_eeprom eeproms[], const struct ar9300_layout *layout, char *filename) 30 | { 31 | int file; 32 | int i = 0; 33 | int offset; 34 | 35 | if ((file = open(filename, O_BINARY | O_RDONLY)) == -1) 36 | { 37 | printf("\nFile not found: '%s'.\n", filename); 38 | return -1; 39 | } 40 | 41 | for (i = 0; i < AR9300_MAX_EEPROMS && (offset = layout->offsets[i]) >= 0; i++) 42 | { 43 | struct ar9300_eeprom *eeprom = &eeproms[i]; 44 | if ((lseek(file, offset, SEEK_SET) != offset || read(file, eeprom, sizeof(struct ar9300_eeprom)) != sizeof(struct ar9300_eeprom))) 45 | { 46 | close(file); 47 | return i; 48 | } 49 | } 50 | 51 | close(file); 52 | return AR9300_MAX_EEPROMS; 53 | } 54 | 55 | static char buffer[64*1024]; 56 | int write_eeproms(struct ar9300_eeprom eeproms[], const struct ar9300_layout *layout, char *filename, char *outname) 57 | { 58 | int i; 59 | int out; 60 | int file; 61 | int bytes; 62 | int offset; 63 | 64 | if ((out = open(outname, O_BINARY | O_RDWR | O_CREAT | O_TRUNC, S_IREAD | S_IWRITE)) == -1) 65 | { 66 | printf("\nFile not open for output: '%s'.\n", outname); 67 | return -1; 68 | } 69 | 70 | if ((file = open(filename, O_BINARY | O_RDONLY)) == -1) 71 | { 72 | printf("\nFile not found: '%s'.\n", filename); 73 | close(out); 74 | return -1; 75 | } 76 | 77 | while ((bytes = read(file, buffer, sizeof(buffer))) > 0) 78 | if (write(out, buffer, bytes) != bytes) 79 | { 80 | printf("\nFile not write to output: '%s'.\n", outname); 81 | close(file); 82 | close(out); 83 | return -1; 84 | } 85 | 86 | close(file); 87 | for (i = 0; i < AR9300_MAX_EEPROMS && (offset = layout->offsets[i]) >= 0; i++) 88 | { 89 | struct ar9300_eeprom *eeprom = &eeproms[i]; 90 | if ((lseek(out, offset, SEEK_SET) != offset || write(out, eeprom, sizeof(struct ar9300_eeprom)) != sizeof(struct ar9300_eeprom))) 91 | { 92 | close(out); 93 | return i; 94 | } 95 | } 96 | 97 | close(out); 98 | return AR9300_MAX_EEPROMS; 99 | } 100 | --------------------------------------------------------------------------------