├── pda ├── _vmake ├── @_opt │ ├── _deps │ ├── vopt1fdrs3 │ ├── vopt300zid │ ├── vopt3c588b │ ├── vopt3v824b │ ├── vopt50rme7 │ ├── vopt660w0a │ ├── vopt7wt58b │ ├── vopt83df37 │ ├── vopt9sdib7 │ ├── voptash1sa │ ├── voptbwi6cb │ ├── voptbxa9v3 │ ├── voptc35h77 │ ├── voptcabc64 │ ├── voptdn6mgb │ ├── voptez711b │ ├── voptfd06v3 │ ├── voptg6tbw6 │ ├── voptgjte77 │ ├── vopth6wigb │ ├── voptjfm5f4 │ ├── voptjnf8w6 │ ├── voptkcga47 │ ├── voptmagqdb │ ├── voptmzhfdb │ ├── voptnvaz04 │ ├── voptqf55s6 │ ├── voptqza2f4 │ ├── voptrd5i2b │ ├── voptrky9wd │ ├── voptsz4knb │ ├── vopttb0w04 │ ├── vopttr0zb4 │ ├── voptvht4d7 │ ├── voptw2tebb │ ├── voptw4k6wd │ ├── voptwdw8jb │ ├── voptx8qsh3 │ ├── voptykfy17 │ ├── voptzab3ad │ ├── voptzxh5jb │ ├── voptk49cwd │ ├── vopt9jfk77 │ ├── voptjbm314 │ ├── voptq157d7 │ ├── voptbfi41b │ ├── voptcn4ew6 │ ├── voptfzz8f4 │ ├── voptrx6cjb │ ├── voptt4t127 │ ├── vopta6hsgb │ ├── vopt0wfb8b │ ├── vopt7cxacb │ ├── voptyyqvs3 │ └── vopt7fzzqa ├── @_opt1 │ ├── _deps │ ├── vopt04sih1 │ ├── vopt075frt │ ├── vopt0nx5ry │ ├── vopt0rt28z │ ├── vopt1fr7z0 │ ├── vopt1qxte1 │ ├── vopt24ri03 │ ├── vopt2cvfe1 │ ├── vopt2dn4rt │ ├── vopt392an4 │ ├── vopt3f86wz │ ├── vopt3qi9yw │ ├── vopt45gig1 │ ├── vopt48gz7z │ ├── vopt4bi21z │ ├── vopt4nhkf1 │ ├── vopt54acn3 │ ├── vopt57jqe1 │ ├── vopt6053hx │ ├── vopt6newn3 │ ├── vopt6xb0rt │ ├── vopt716w4z │ ├── vopt744ch1 │ ├── vopt7sg8it │ ├── vopt7sq6n4 │ ├── vopt867hf1 │ ├── vopt8cwej4 │ ├── vopt8k2181 │ ├── vopt964sn3 │ ├── vopt9d3bx2 │ ├── vopt9sixjz │ ├── voptagt0hx │ ├── voptb4ry71 │ ├── voptb965it │ ├── voptbazvby │ ├── voptbks8h1 │ ├── voptbwhbj4 │ ├── voptc7yge1 │ ├── voptctn543 │ ├── voptd3vm73 │ ├── voptdqfwjx │ ├── voptdxr8x2 │ ├── vopte4f5h1 │ ├── voptefgmaz │ ├── voptes20n4 │ ├── voptf6iaf1 │ ├── voptftkrby │ ├── voptfxdt41 │ ├── voptgac243 │ ├── voptgdkff1 │ ├── voptgtr5ez │ ├── vopth0bq6v │ ├── vopth26sax │ ├── vopthjgw9t │ ├── voptiaamby │ ├── voptima400 │ ├── voptiz5iaz │ ├── voptjn77f1 │ ├── voptkg0j6v │ ├── voptkx9cf1 │ ├── voptkz0zc3 │ ├── voptmhrctz │ ├── voptmsdsm4 │ ├── voptn4tzg1 │ ├── voptn6x4f1 │ ├── voptnfvfaz │ ├── voptnjtki0 │ ├── voptnmv1g1 │ ├── voptqt0901 │ ├── voptr83yjz │ ├── voptr93nm4 │ ├── voptrt6g80 │ ├── vopts1e9tz │ ├── vopts4kv00 │ ├── vopts5jm3x │ ├── voptsrkehy │ ├── voptt3ghi0 │ ├── voptt5hyf1 │ ├── voptvjn6x0 │ ├── voptvtaayt │ ├── voptvydrq2 │ ├── voptwj3mh1 │ ├── voptwm8i3x │ ├── voptwsrjm4 │ ├── voptx588ry │ ├── voptx68xe1 │ ├── voptx8abhy │ ├── voptxk9r00 │ ├── voptxr4dv0 │ ├── voptye3mq2 │ ├── voptyv5je1 │ ├── voptz8b261 │ ├── voptzyiawz │ ├── voptcdbmjx │ ├── voptdxyjf1 │ ├── vopth9rxm4 │ ├── vopt26szn3 │ ├── vopta9d3n4 │ ├── voptvexdwz │ ├── voptik42h1 │ ├── voptw7558z │ ├── voptbnwef1 │ ├── voptj35qi0 │ ├── vopt39vbit │ ├── vopt4kefh1 │ ├── voptbztraz │ ├── voptf5m800 │ ├── voptqerwq2 │ ├── vopt0mtmg1 │ ├── vopt7t9yby │ ├── vopt8q8je1 │ ├── voptkrd2kz │ ├── voptn8zhhy │ ├── voptsmibry │ ├── vopt9a1943 │ ├── vopt6xdfx2 │ ├── voptzw07rt │ ├── voptdgmt6v │ ├── vopttbgne1 │ ├── vopt44d481 │ ├── voptmmxs3x │ ├── vopttni1f1 │ ├── vopt7296mw │ ├── vopthvvifz │ └── voptxm6vf1 ├── _temp │ ├── vlog5mq2ej │ ├── vlog767e5h │ ├── vlogihgt5g │ ├── vlogjzsm0z │ ├── vlogmekyiq │ └── vlognhh4re ├── @mux_1 │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @mux_2 │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @mux_3 │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @mux_4 │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @mux_5 │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @control │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @big_@alu │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.asm64 │ ├── verilog.rw64 │ └── _primary.vhd ├── @rounding │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.asm64 │ ├── verilog.rw64 │ └── _primary.vhd ├── @small_@alu │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── test_bench │ ├── _primary.dat │ ├── _primary.dbs │ ├── _primary.vhd │ ├── verilog.asm64 │ └── verilog.rw64 ├── @incre_@decre │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @shift_@right │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd ├── @rounding_instance │ ├── _primary.dat │ ├── _primary.dbs │ └── _primary.vhd ├── @shift_@left_@right │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.asm64 │ ├── verilog.rw64 │ └── _primary.vhd ├── @floating_@point_@addition │ ├── _primary.dat │ ├── _primary.dbs │ ├── verilog.rw64 │ ├── verilog.asm64 │ └── _primary.vhd └── _info ├── README ├── vsim.wlf ├── snapshot ├── pic_1.PNG ├── pic_2.PNG ├── pic_3.PNG ├── pic_4.PNG ├── pic_5.PNG └── pic_6.PNG ├── Mux_5.v ├── Mux_5.v.bak ├── Mux_2.v ├── Mux_3.v ├── Incre_Decre.v.bak ├── Mux_4.v ├── Mux_4.v.bak ├── Mux_1.v.bak ├── Mux_1.v ├── Incre_Decre.v ├── Small_Alu.v.bak ├── Shift_Left_Right.v.bak ├── Small_Alu.v ├── Shift_Left_Right.v ├── tese_bench.v ├── tese_bench.v.bak ├── Shift_Right.v ├── Shift_Right.v.bak ├── Big_Alu.v ├── Rounding.v ├── Rounding.v.bak ├── Big_Alu.v.bak ├── Control.v.bak ├── Control.v ├── Floating_Point_Addition.v ├── Floating_Point_Addition.v.bak ├── pdas.cr.mti └── LICENSE /pda/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | cModel Technology 4 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Biinngg/Floating-Point-Addition/HEAD/README -------------------------------------------------------------------------------- /vsim.wlf: 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-------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity test_bench is 4 | end test_bench; 5 | -------------------------------------------------------------------------------- /pda/@_opt1/voptdxyjf1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity test_bench is 4 | end test_bench; 5 | -------------------------------------------------------------------------------- /pda/@_opt1/vopth9rxm4: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity test_bench is 4 | end test_bench; 5 | -------------------------------------------------------------------------------- /pda/@control/_primary.dat: -------------------------------------------------------------------------------- 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outp = mux; 9 | else 10 | outp = rounding; 11 | if(!res) 12 | outp = 0; 13 | end 14 | endmodule -------------------------------------------------------------------------------- /Mux_5.v.bak: -------------------------------------------------------------------------------- 1 | module Mux_5(clk,res,en,mux,rounding,outp); 2 | input clk,res,en; 3 | input [7:0] mux,rounding; 4 | output reg [7:0] outp; 5 | 6 | always @(posedge clk) begin 7 | if(en) 8 | outp = mux; 9 | else 10 | outp = rounding; 11 | if(!res) 12 | outp = 0; 13 | end 14 | endmodule -------------------------------------------------------------------------------- /Mux_2.v: -------------------------------------------------------------------------------- 1 | module Mux_2 (clk, res, x, y, en, out); 2 | input clk, res, en; 3 | input [31:0] x, y; 4 | output reg [31:0] out; 5 | 6 | always @(posedge clk) begin 7 | begin 8 | if(en) 9 | out = y; 10 | else 11 | out = x; 12 | end 13 | begin 14 | if(!res) 15 | out = 0; 16 | end 17 | end 18 | endmodule -------------------------------------------------------------------------------- /Mux_3.v: -------------------------------------------------------------------------------- 1 | module Mux_3 (clk, res, x, y, en, out); 2 | input clk, res, en; 3 | input [31:0] x, y; 4 | output reg [31:0] out; 5 | 6 | always @(posedge clk) begin 7 | begin 8 | if(en) 9 | out = y; 10 | else 11 | out = x; 12 | end 13 | begin 14 | if(!res) 15 | out = 0; 16 | end 17 | end 18 | endmodule -------------------------------------------------------------------------------- /pda/@_opt1/vopt26szn3: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Floating_Point_Addition is 4 | port( 5 | clk : in vl_logic; 6 | reset : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0) 9 | ); 10 | end Floating_Point_Addition; 11 | -------------------------------------------------------------------------------- /pda/@_opt1/vopta9d3n4: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Floating_Point_Addition is 4 | port( 5 | clk : in vl_logic; 6 | reset : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0) 9 | ); 10 | end Floating_Point_Addition; 11 | -------------------------------------------------------------------------------- /pda/@_opt1/voptvexdwz: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Floating_Point_Addition is 4 | port( 5 | clk : in vl_logic; 6 | reset : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0) 9 | ); 10 | end Floating_Point_Addition; 11 | -------------------------------------------------------------------------------- /pda/@floating_@point_@addition/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Floating_Point_Addition is 4 | port( 5 | clk : in vl_logic; 6 | reset : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0) 9 | ); 10 | end Floating_Point_Addition; 11 | -------------------------------------------------------------------------------- /pda/@_opt/vopt9jfk77: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Big_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(26 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(27 downto 0) 10 | ); 11 | end Big_Alu; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/voptik42h1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Big_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(26 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(27 downto 0) 10 | ); 11 | end Big_Alu; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/voptw7558z: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Big_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(26 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(27 downto 0) 10 | ); 11 | end Big_Alu; 12 | -------------------------------------------------------------------------------- /pda/@_opt/voptjbm314: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Small_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(31 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(8 downto 0) 10 | ); 11 | end Small_Alu; 12 | -------------------------------------------------------------------------------- /pda/@_opt/voptq157d7: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(7 downto 0); 8 | mux : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(26 downto 0) 10 | ); 11 | end Shift_Right; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/voptbnwef1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Small_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(31 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(8 downto 0) 10 | ); 11 | end Small_Alu; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/voptj35qi0: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Small_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(31 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(8 downto 0) 10 | ); 11 | end Small_Alu; 12 | -------------------------------------------------------------------------------- /pda/@big_@alu/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Big_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(26 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(27 downto 0) 10 | ); 11 | end Big_Alu; 12 | -------------------------------------------------------------------------------- /Incre_Decre.v.bak: -------------------------------------------------------------------------------- 1 | module Incre_Decre(clk,res,incre_bit,decre_bit,incre_en,decre_en,mux,out); 2 | input clk,res,incre_en,decre_en; 3 | input [7:0] incre_bit,decre_bit,mux; 4 | output reg [8:0] out; 5 | 6 | always @(posedge clk) begin 7 | out[8] = 0; 8 | if(incre_en) 9 | out = mux + incre_bit; 10 | else if(decre_en) 11 | out = mux - decre_bit; 12 | if(!res) 13 | out = 0; 14 | end 15 | endmodule -------------------------------------------------------------------------------- /pda/@_opt1/vopt39vbit: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(7 downto 0); 8 | mux : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(26 downto 0) 10 | ); 11 | end Shift_Right; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt4kefh1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(7 downto 0); 8 | mux : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(26 downto 0) 10 | ); 11 | end Shift_Right; 12 | -------------------------------------------------------------------------------- /pda/@_opt1/voptbztraz: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(7 downto 0); 8 | mux : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(26 downto 0) 10 | ); 11 | end Shift_Right; 12 | -------------------------------------------------------------------------------- /pda/@small_@alu/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Small_Alu is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | a : in vl_logic_vector(31 downto 0); 8 | b : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(8 downto 0) 10 | ); 11 | end Small_Alu; 12 | -------------------------------------------------------------------------------- /pda/@shift_@right/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(7 downto 0); 8 | mux : in vl_logic_vector(31 downto 0); 9 | outp : out vl_logic_vector(26 downto 0) 10 | ); 11 | end Shift_Right; 12 | -------------------------------------------------------------------------------- /Mux_4.v: -------------------------------------------------------------------------------- 1 | module Mux_4 (clk, res, en, big_alu_result, fra_result, out); 2 | input clk, res, en; 3 | input [27:0] big_alu_result, fra_result; 4 | output reg [27:0] out; 5 | 6 | always @(posedge clk) begin 7 | begin 8 | if(en) 9 | out = fra_result; 10 | else 11 | out = big_alu_result; 12 | end 13 | begin 14 | if(!res) 15 | out = 0; 16 | end 17 | end 18 | endmodule -------------------------------------------------------------------------------- /Mux_4.v.bak: -------------------------------------------------------------------------------- 1 | module Mux_4 (clk, res, big_alu_result, fra_result, en, out); 2 | input clk, res, en; 3 | input [27:0] big_alu_result, fra_result; 4 | output reg [27:0] out; 5 | 6 | always @(posedge clk) begin 7 | begin 8 | if(en) 9 | out = fra_result; 10 | else 11 | out = big_alu_result; 12 | end 13 | begin 14 | if(!res) 15 | out = 0; 16 | end 17 | end 18 | endmodule -------------------------------------------------------------------------------- /pda/@_opt/voptbfi41b: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_5 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | mux : in vl_logic_vector(7 downto 0); 9 | rounding : in vl_logic_vector(7 downto 0); 10 | outp : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_5; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/voptf5m800: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_5 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | mux : in vl_logic_vector(7 downto 0); 9 | rounding : in vl_logic_vector(7 downto 0); 10 | outp : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_5; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/voptqerwq2: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_5 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | mux : in vl_logic_vector(7 downto 0); 9 | rounding : in vl_logic_vector(7 downto 0); 10 | outp : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_5; 13 | -------------------------------------------------------------------------------- /pda/@_opt/voptcn4ew6: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_3 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_3; 13 | -------------------------------------------------------------------------------- /pda/@_opt/voptfzz8f4: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_1 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_1; 13 | -------------------------------------------------------------------------------- /pda/@_opt/voptrx6cjb: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_4 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | big_alu_result : in vl_logic_vector(27 downto 0); 8 | fra_result : in vl_logic_vector(27 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(27 downto 0) 11 | ); 12 | end Mux_4; 13 | -------------------------------------------------------------------------------- /pda/@_opt/voptt4t127: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_2 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_2; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt0mtmg1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_4 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | \out\ : out vl_logic_vector(27 downto 0) 11 | ); 12 | end Mux_4; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt7t9yby: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_2 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_2; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt8q8je1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_1 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_1; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/voptkrd2kz: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_4 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | big_alu_result : in vl_logic_vector(27 downto 0); 8 | fra_result : in vl_logic_vector(27 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(27 downto 0) 11 | ); 12 | end Mux_4; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/voptn8zhhy: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_1 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_1; 13 | -------------------------------------------------------------------------------- /pda/@_opt1/voptsmibry: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_3 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_3; 13 | -------------------------------------------------------------------------------- /pda/@mux_1/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_1 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_1; 13 | -------------------------------------------------------------------------------- /pda/@mux_2/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_2 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_2; 13 | -------------------------------------------------------------------------------- /pda/@mux_3/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_3 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | x : in vl_logic_vector(31 downto 0); 8 | y : in vl_logic_vector(31 downto 0); 9 | en : in vl_logic; 10 | \out\ : out vl_logic_vector(31 downto 0) 11 | ); 12 | end Mux_3; 13 | -------------------------------------------------------------------------------- /pda/@mux_4/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_4 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | \out\ : out vl_logic_vector(27 downto 0) 11 | ); 12 | end Mux_4; 13 | -------------------------------------------------------------------------------- /pda/@mux_5/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Mux_5 is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | en : in vl_logic; 8 | mux : in vl_logic_vector(7 downto 0); 9 | rounding : in vl_logic_vector(7 downto 0); 10 | outp : out vl_logic_vector(7 downto 0) 11 | ); 12 | end Mux_5; 13 | -------------------------------------------------------------------------------- /Mux_1.v.bak: -------------------------------------------------------------------------------- 1 | module Mux_1 (clk, res, x, y, en, out); 2 | input clk, res, en; 3 | input [31:0] x, y; 4 | reg [7:0] exp_x, exp_y; 5 | output reg [7:0] out; 6 | 7 | always @(posedge clk) 8 | begin 9 | exp_x = x[30:23]; 10 | exp_y = y[30:23]; 11 | begin 12 | if(en) 13 | out = y; 14 | else 15 | out = x; 16 | end 17 | begin 18 | if(!res) 19 | out = 0; 20 | end 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Mux_1.v: -------------------------------------------------------------------------------- 1 | module Mux_1 (clk, res, x, y, en, out); 2 | input clk, res, en; 3 | input [31:0] x, y; 4 | reg [7:0] exp_x, exp_y; 5 | output reg [7:0] out; 6 | 7 | always @(posedge clk) 8 | begin 9 | exp_x = x[30:23]; 10 | exp_y = y[30:23]; 11 | begin 12 | if(en) 13 | out = exp_y; 14 | else 15 | out = exp_x; 16 | end 17 | begin 18 | if(!res) 19 | out = 0; 20 | end 21 | end 22 | endmodule -------------------------------------------------------------------------------- /Incre_Decre.v: -------------------------------------------------------------------------------- 1 | module Incre_Decre(clk,res,incre_bit,decre_bit,incre_en,decre_en,mux,incre_decre_output); 2 | input clk,res,incre_en,decre_en; 3 | input [7:0] incre_bit,decre_bit,mux; 4 | output reg [8:0] incre_decre_output; 5 | 6 | always @(posedge clk) begin 7 | incre_decre_output[8] = 0; 8 | if(incre_en) 9 | incre_decre_output = mux + incre_bit; 10 | else if(decre_en) 11 | incre_decre_output = mux - decre_bit; 12 | if(!res) 13 | incre_decre_output = 0; 14 | end 15 | endmodule -------------------------------------------------------------------------------- /Small_Alu.v.bak: -------------------------------------------------------------------------------- 1 | module Small_Alu(clk, res, a, b, outp); 2 | input clk,res; 3 | input [31:0] a, b; 4 | reg [7:0] exp_a,exp_b; 5 | output reg [8:0] outp; 6 | 7 | always @(posedge clk) 8 | begin 9 | exp_a = a[30:23]; 10 | exp_b = b[30:23]; 11 | if(exp_a >= exp_b) 12 | outp[7:0] = exp_a - exp_b; 13 | else 14 | begin 15 | outp[7:0] = exp_b - exp_a; 16 | outp[8] = 1; 17 | end 18 | if(res == 0) 19 | outp = 0; 20 | end 21 | endmodule -------------------------------------------------------------------------------- /Shift_Left_Right.v.bak: -------------------------------------------------------------------------------- 1 | module Shift_Left_Right(clk,res,shift_left_bits,shift_right_bits, 2 | shift_left_en,shift_right_en,mux_4_output,out); 3 | input clk,res,shift_left_en,shift_right_en; 4 | input [7:0] shift_left_bits,shift_right_bits; 5 | input [27:0] mux_4_output; 6 | output reg [27:0] out; 7 | 8 | always @(posedge clk) begin 9 | if(shift_right_en) 10 | out = mux_4_output >> shift_right_bits; 11 | else if(shift_left_en) 12 | out = mux_4_output << shift_left_bits; 13 | out[27] = mux_4_output[27]; 14 | end 15 | endmodule -------------------------------------------------------------------------------- /Small_Alu.v: -------------------------------------------------------------------------------- 1 | module Small_Alu(clk, res, a, b, outp); 2 | input clk,res; 3 | input [31:0] a, b; 4 | reg [7:0] exp_a,exp_b; 5 | output reg [8:0] outp; 6 | 7 | always @(posedge clk) 8 | begin 9 | exp_a = a[30:23]; 10 | exp_b = b[30:23]; 11 | if(exp_a >= exp_b) 12 | begin 13 | outp[7:0] = exp_a - exp_b; 14 | outp[8] = 0; 15 | end 16 | else 17 | begin 18 | outp[7:0] = exp_b - exp_a; 19 | outp[8] = 1; 20 | end 21 | if(res == 0) 22 | outp = 0; 23 | end 24 | endmodule -------------------------------------------------------------------------------- /Shift_Left_Right.v: -------------------------------------------------------------------------------- 1 | module Shift_Left_Right(clk,res,shift_left_bits,shift_right_bits, 2 | shift_left_en,shift_right_en,mux_4_output,out); 3 | input clk,res,shift_left_en,shift_right_en; 4 | input [7:0] shift_left_bits,shift_right_bits; 5 | input [27:0] mux_4_output; 6 | output reg [27:0] out; 7 | 8 | always @(posedge clk) begin 9 | if(shift_right_en) 10 | out = mux_4_output >> shift_right_bits; 11 | else if(shift_left_en) 12 | out = mux_4_output << shift_left_bits; 13 | out[27] = mux_4_output[27]; 14 | out[0] = 1;//mark 15 | end 16 | endmodule -------------------------------------------------------------------------------- /pda/@_opt/vopta6hsgb: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Incre_Decre is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | incre_bit : in vl_logic_vector(7 downto 0); 8 | decre_bit : in vl_logic_vector(7 downto 0); 9 | incre_en : in vl_logic; 10 | decre_en : in vl_logic; 11 | mux : in vl_logic_vector(7 downto 0); 12 | incre_decre_output: out vl_logic_vector(8 downto 0) 13 | ); 14 | end Incre_Decre; 15 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt9a1943: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Incre_Decre is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | incre_bit : in vl_logic_vector(7 downto 0); 8 | decre_bit : in vl_logic_vector(7 downto 0); 9 | incre_en : in vl_logic; 10 | decre_en : in vl_logic; 11 | mux : in vl_logic_vector(7 downto 0); 12 | incre_decre_output: out vl_logic_vector(8 downto 0) 13 | ); 14 | end Incre_Decre; 15 | -------------------------------------------------------------------------------- /pda/@_opt/vopt0wfb8b: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Left_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift_left_bits : in vl_logic_vector(7 downto 0); 8 | shift_right_bits: in vl_logic_vector(7 downto 0); 9 | shift_left_en : in vl_logic; 10 | shift_right_en : in vl_logic; 11 | mux_4_output : in vl_logic_vector(27 downto 0); 12 | \out\ : out vl_logic_vector(27 downto 0) 13 | ); 14 | end Shift_Left_Right; 15 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt6xdfx2: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Left_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift_left_bits : in vl_logic_vector(7 downto 0); 8 | shift_right_bits: in vl_logic_vector(7 downto 0); 9 | shift_left_en : in vl_logic; 10 | shift_right_en : in vl_logic; 11 | mux_4_output : in vl_logic_vector(27 downto 0); 12 | \out\ : out vl_logic_vector(27 downto 0) 13 | ); 14 | end Shift_Left_Right; 15 | -------------------------------------------------------------------------------- /pda/@_opt1/voptzw07rt: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Left_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift_left_bits : in vl_logic_vector(7 downto 0); 8 | shift_right_bits: in vl_logic_vector(7 downto 0); 9 | shift_left_en : in vl_logic; 10 | shift_right_en : in vl_logic; 11 | mux_4_output : in vl_logic_vector(27 downto 0); 12 | \out\ : out vl_logic_vector(27 downto 0) 13 | ); 14 | end Shift_Left_Right; 15 | -------------------------------------------------------------------------------- /pda/@incre_@decre/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Incre_Decre is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | incre_bit : in vl_logic_vector(7 downto 0); 8 | decre_bit : in vl_logic_vector(7 downto 0); 9 | incre_en : in vl_logic; 10 | decre_en : in vl_logic; 11 | mux : in vl_logic_vector(7 downto 0); 12 | incre_decre_output: out vl_logic_vector(8 downto 0) 13 | ); 14 | end Incre_Decre; 15 | -------------------------------------------------------------------------------- /pda/@_opt/vopt7cxacb: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Rounding is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(27 downto 0); 8 | incre : in vl_logic_vector(8 downto 0); 9 | exp_result : out vl_logic_vector(7 downto 0); 10 | fra_result : out vl_logic_vector(27 downto 0); 11 | result : out vl_logic_vector(31 downto 0); 12 | overflow : out vl_logic 13 | ); 14 | end Rounding; 15 | -------------------------------------------------------------------------------- /pda/@_opt1/voptdgmt6v: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Rounding is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(27 downto 0); 8 | incre : in vl_logic_vector(8 downto 0); 9 | exp_result : out vl_logic_vector(7 downto 0); 10 | fra_result : out vl_logic_vector(27 downto 0); 11 | result : out vl_logic_vector(31 downto 0); 12 | overflow : out vl_logic 13 | ); 14 | end Rounding; 15 | -------------------------------------------------------------------------------- /pda/@_opt1/vopttbgne1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Rounding is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(27 downto 0); 8 | incre : in vl_logic_vector(8 downto 0); 9 | exp_result : out vl_logic_vector(7 downto 0); 10 | fra_result : out vl_logic_vector(27 downto 0); 11 | result : out vl_logic_vector(31 downto 0); 12 | overflow : out vl_logic 13 | ); 14 | end Rounding; 15 | -------------------------------------------------------------------------------- /pda/@rounding/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Rounding is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(27 downto 0); 8 | incre : in vl_logic_vector(8 downto 0); 9 | exp_result : out vl_logic_vector(7 downto 0); 10 | fra_result : out vl_logic_vector(27 downto 0); 11 | result : out vl_logic_vector(31 downto 0); 12 | overflow : out vl_logic 13 | ); 14 | end Rounding; 15 | -------------------------------------------------------------------------------- /tese_bench.v: -------------------------------------------------------------------------------- 1 | module test_bench; 2 | reg clk; //?????? 3 | reg reset; //?????? 4 | reg[31:0] x; //10 ?????????? 5 | reg[31:0] y; 6 | 7 | initial 8 | #0 clk = 1'b1; 9 | always 10 | #10 clk = ~clk; 11 | 12 | initial 13 | begin 14 | #0 reset = 1'b0; 15 | #5 reset = 1'b0; 16 | #10 reset = 1'b1; 17 | #500 $finish; 18 | end 19 | 20 | initial 21 | begin 22 | #11 x=32'b0001_1111_1111_1111_1111_1111_1111_1111; 23 | #11 y=32'b1001_1111_1111_1111_1111_1111_1111_0000; 24 | end 25 | Floating_Point_Addition 26 | test(clk,reset,x,y); 27 | endmodule -------------------------------------------------------------------------------- /pda/@shift_@left_@right/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Shift_Left_Right is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift_left_bits : in vl_logic_vector(7 downto 0); 8 | shift_right_bits: in vl_logic_vector(7 downto 0); 9 | shift_left_en : in vl_logic; 10 | shift_right_en : in vl_logic; 11 | mux_4_output : in vl_logic_vector(27 downto 0); 12 | \out\ : out vl_logic_vector(27 downto 0) 13 | ); 14 | end Shift_Left_Right; 15 | -------------------------------------------------------------------------------- /tese_bench.v.bak: -------------------------------------------------------------------------------- 1 | module test_bench; 2 | reg clk; //?????? 3 | reg reset; //?????? 4 | reg[31:0] x; //10 ?????????? 5 | reg[31:0] y; 6 | 7 | initial 8 | #0 clk = 1'b1; 9 | always 10 | #10 clk = ~clk; 11 | 12 | initial 13 | begin 14 | #0 reset = 1'b0; 15 | #5 reset = 1'b0; 16 | #10 reset = 1'b1; 17 | #500 $finish; 18 | end 19 | 20 | initial 21 | begin 22 | #11 x=32'b0001_1110_1110_0010_0010_1000_0001_1111; 23 | #11 y=32'b0001_1111_1111_1111_1111_1111_1111_0000; 24 | end 25 | Floating_Point_Addition 26 | test(clk,reset,x,y); 27 | endmodule -------------------------------------------------------------------------------- /pda/@rounding_instance/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Rounding_instance is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | shift : in vl_logic_vector(27 downto 0); 8 | incre : in vl_logic_vector(8 downto 0); 9 | exp_result : out vl_logic_vector(7 downto 0); 10 | fra_result : out vl_logic_vector(27 downto 0); 11 | result : out vl_logic_vector(31 downto 0); 12 | overflow : out vl_logic 13 | ); 14 | end Rounding_instance; 15 | -------------------------------------------------------------------------------- /Shift_Right.v: -------------------------------------------------------------------------------- 1 | module Shift_Right(clk, res, shift, mux, outp); 2 | input clk,res; 3 | input [31:0] mux; 4 | input [7:0] shift; 5 | reg [7:0] tmp; 6 | reg [26:0] fra = 0; 7 | output reg [26:0] outp; //26 for signal, 25:0 for num "1" before dot and two reserved at the end. 8 | always @(posedge clk) begin 9 | if(shift) 10 | begin 11 | fra[24:2] = mux[22:0]; //reserve two places at the end. 12 | tmp = shift - 128; 13 | fra[25] = 1; //number "1" before dot 14 | outp[24:0] = fra>>tmp; 15 | outp[26] = mux[31]; //signal 16 | end 17 | if(!res) 18 | outp = 0; 19 | end 20 | endmodule -------------------------------------------------------------------------------- /Shift_Right.v.bak: -------------------------------------------------------------------------------- 1 | module Shift_Right(clk, res, shift, mux, outp); 2 | input clk,res; 3 | input [31:0] mux; 4 | input [7:0] shift; 5 | reg [7:0] tmp; 6 | reg [26:0] fra = 0; 7 | output reg [26:0] outp; //26 for signal, 25:0 for num "1" before dot and two reserved at the end. 8 | always @(posedge clk) begin 9 | if(shift) 10 | begin 11 | fra[24:2] = mux[22:0]; //reserve two places at the end. 12 | tmp = shift - 128; 13 | fra[25] = 1; //number "1" before dot 14 | outp[24:0] = fra>>tmp; 15 | outp[26] = mux[31]; //signal 16 | outp[n] = 0; 17 | end 18 | if(!res) 19 | outp = 0; 20 | end 21 | endmodule -------------------------------------------------------------------------------- /Big_Alu.v: -------------------------------------------------------------------------------- 1 | module Big_Alu(clk, res, a, b, outp); 2 | input clk,res; 3 | input [26:0] a; 4 | input [31:0] b; 5 | reg sig_a,sig_b; 6 | reg [26:0] fra_a=0,mid; 7 | reg [26:0] fra_b=0; 8 | output reg [27:0] outp=0; //Added an overflow place at 26. 9 | 10 | always @(posedge clk) 11 | begin 12 | sig_a = a[26]; 13 | sig_b = b[31]; 14 | fra_a[25:0] = a[25:0]; 15 | fra_b[24:2] = b[22:0]; 16 | mid = 0; 17 | if(sig_a == sig_b) 18 | begin 19 | outp[27] = sig_a; 20 | outp[26:0] = fra_a + fra_b; 21 | end 22 | else 23 | begin 24 | if(fra_a > fra_b) 25 | begin 26 | outp[27] = sig_a; 27 | mid = (fra_a - fra_b)%fra_a; 28 | outp[26:0] = mid; 29 | end 30 | else if(fra_a < fra_b) 31 | begin 32 | outp[27] = sig_b; 33 | mid = (fra_b - fra_a)%fra_b; 34 | outp[26:0] = mid; 35 | end 36 | else 37 | outp = 0; 38 | end 39 | fra_b[25] = 0; 40 | if(res == 0) 41 | outp = 0; 42 | end 43 | endmodule -------------------------------------------------------------------------------- /pda/@_opt/voptyyqvs3: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Control is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | exp_diff : in vl_logic_vector(8 downto 0); 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | shift_right_bits: out vl_logic_vector(7 downto 0); 11 | shift_left_bits : out vl_logic_vector(7 downto 0); 12 | shift_right_en : out vl_logic; 13 | shift_left_en : out vl_logic; 14 | shift_right_bit : out vl_logic_vector(7 downto 0); 15 | incre_bit : out vl_logic_vector(7 downto 0); 16 | decre_bit : out vl_logic_vector(7 downto 0); 17 | incre_en : out vl_logic; 18 | decre_en : out vl_logic; 19 | mux_1_en : out vl_logic; 20 | mux_2_en : out vl_logic; 21 | mux_3_en : out vl_logic; 22 | mux_4_en : out vl_logic; 23 | mux_5_en : out vl_logic 24 | ); 25 | end Control; 26 | -------------------------------------------------------------------------------- /pda/@_opt1/vopt44d481: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Control is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | exp_diff : in vl_logic_vector(8 downto 0); 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | shift_right_bits: out vl_logic_vector(7 downto 0); 11 | shift_left_bits : out vl_logic_vector(7 downto 0); 12 | shift_right_en : out vl_logic; 13 | shift_left_en : out vl_logic; 14 | shift_right_bit : out vl_logic_vector(7 downto 0); 15 | incre_bit : out vl_logic_vector(7 downto 0); 16 | decre_bit : out vl_logic_vector(7 downto 0); 17 | incre_en : out vl_logic; 18 | decre_en : out vl_logic; 19 | mux_1_en : out vl_logic; 20 | mux_2_en : out vl_logic; 21 | mux_3_en : out vl_logic; 22 | mux_4_en : out vl_logic; 23 | mux_5_en : out vl_logic 24 | ); 25 | end Control; 26 | -------------------------------------------------------------------------------- /pda/@_opt1/voptmmxs3x: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Control is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | exp_diff : in vl_logic_vector(8 downto 0); 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | shift_right_bits: out vl_logic_vector(7 downto 0); 11 | shift_left_bits : out vl_logic_vector(7 downto 0); 12 | shift_right_en : out vl_logic; 13 | shift_left_en : out vl_logic; 14 | shift_right_bit : out vl_logic_vector(7 downto 0); 15 | incre_bit : out vl_logic_vector(7 downto 0); 16 | decre_bit : out vl_logic_vector(7 downto 0); 17 | incre_en : out vl_logic; 18 | decre_en : out vl_logic; 19 | mux_1_en : out vl_logic; 20 | mux_2_en : out vl_logic; 21 | mux_3_en : out vl_logic; 22 | mux_4_en : out vl_logic; 23 | mux_5_en : out vl_logic 24 | ); 25 | end Control; 26 | -------------------------------------------------------------------------------- /pda/@_opt1/vopttni1f1: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Control is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | exp_diff : in vl_logic_vector(8 downto 0); 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | shift_right_bits: out vl_logic_vector(7 downto 0); 11 | shift_left_bits : out vl_logic_vector(7 downto 0); 12 | shift_right_en : out vl_logic; 13 | shift_left_en : out vl_logic; 14 | shift_right_bit : out vl_logic_vector(7 downto 0); 15 | incre_bit : out vl_logic_vector(7 downto 0); 16 | decre_bit : out vl_logic_vector(7 downto 0); 17 | incre_en : out vl_logic; 18 | decre_en : out vl_logic; 19 | mux_1_en : out vl_logic; 20 | mux_2_en : out vl_logic; 21 | mux_3_en : out vl_logic; 22 | mux_4_en : out vl_logic; 23 | mux_5_en : out vl_logic 24 | ); 25 | end Control; 26 | -------------------------------------------------------------------------------- /Rounding.v: -------------------------------------------------------------------------------- 1 | module Rounding(clk,res,shift,incre, 2 | exp_result,fra_result,result,overflow); 3 | input clk,res; 4 | input [8:0] incre; 5 | input [27:0] shift; 6 | reg [24:0] fra;//Include "1" but not the two reserved places. 7 | output reg overflow; 8 | output reg [7:0] exp_result; 9 | output reg [27:0] fra_result; 10 | output reg [31:0] result; 11 | 12 | always @(posedge clk) begin 13 | if(shift) 14 | begin 15 | if(incre[8])//incase the second time exp is not overflow. 16 | overflow = 1; 17 | else 18 | overflow = 0;//reset 19 | fra [24] = 0; 20 | fra[23:0] = shift[25:2]; 21 | if(shift[1]) 22 | fra = fra+1; 23 | if(fra[24]) 24 | begin 25 | fra_result[27] = shift[27]; 26 | fra_result[26:2] = fra[24:0]; 27 | fra_result[1:0] = 1; 28 | exp_result = incre[7:0]; 29 | end 30 | else 31 | begin 32 | result[31] = shift[27]; 33 | result[30:23] = incre[7:0]; 34 | result[22:0] = fra[22:0]; 35 | end 36 | if(!res) 37 | begin 38 | fra_result = 0; 39 | result = 0; 40 | end 41 | end 42 | end 43 | endmodule -------------------------------------------------------------------------------- /Rounding.v.bak: -------------------------------------------------------------------------------- 1 | module Rounding(clk,res,shift,incre, 2 | exp_result,fra_result,result,overflow); 3 | input clk,res; 4 | input [8:0] incre; 5 | input [27:0] shift; 6 | reg [24:0] fra;//Include "1" but not the two reserved places. 7 | output reg overflow; 8 | output reg [7:0] exp_result; 9 | output reg [27:0] fra_result; 10 | output reg [31:0] result; 11 | 12 | always @(posedge clk) begin 13 | if(shift) 14 | begin 15 | if(incre[8])//incase the second time exp is not overflow. 16 | overflow = 1; 17 | else 18 | overflow = 0;//reset 19 | fra [24] = 0; 20 | fra[23:0] = shift[25:2]; 21 | if(shift[1]) 22 | fra = fra+1; 23 | if(fra[24]) 24 | begin 25 | fra_result[27] = shift[27]; 26 | fra_result[26:2] = fra[24:0]; 27 | fra_result[1:0] = 1; 28 | exp_result = incre[7:0]; 29 | end 30 | else 31 | begin 32 | result[31] = shift[27]; 33 | result[30:23] = incre[7:0]; 34 | result[22:0] = fra[23:0]; 35 | end 36 | if(!res) 37 | begin 38 | fra_result = 0; 39 | result = 0; 40 | end 41 | end 42 | end 43 | endmodule -------------------------------------------------------------------------------- /pda/@control/_primary.vhd: -------------------------------------------------------------------------------- 1 | library verilog; 2 | use verilog.vl_types.all; 3 | entity Control is 4 | port( 5 | clk : in vl_logic; 6 | res : in vl_logic; 7 | exp_diff : in vl_logic_vector(8 downto 0); 8 | big_alu_result : in vl_logic_vector(27 downto 0); 9 | fra_result : in vl_logic_vector(27 downto 0); 10 | shift_right_bits: out vl_logic_vector(7 downto 0); 11 | shift_left_bits : out vl_logic_vector(7 downto 0); 12 | shift_right_en : out vl_logic; 13 | shift_left_en : out vl_logic; 14 | shift_right_bit : out vl_logic_vector(7 downto 0); 15 | incre_bit : out vl_logic_vector(7 downto 0); 16 | decre_bit : out vl_logic_vector(7 downto 0); 17 | incre_en : out vl_logic; 18 | decre_en : out vl_logic; 19 | mux_1_en : out vl_logic; 20 | mux_2_en : out vl_logic; 21 | mux_3_en : out vl_logic; 22 | mux_4_en : out vl_logic; 23 | mux_5_en : out vl_logic 24 | ); 25 | end Control; 26 | -------------------------------------------------------------------------------- /Big_Alu.v.bak: -------------------------------------------------------------------------------- 1 | module Big_Alu(clk, res, a, b, outp); 2 | input clk,res; 3 | input [26:0] a; 4 | input [31:0] b; 5 | reg sig_a,sig_b; 6 | reg [26:0] fra_a=0,mid; 7 | reg [26:0] fra_b=0; 8 | output reg [27:0] outp=0; //Added an overflow place at 26. 9 | 10 | always @(posedge clk) 11 | begin 12 | fra_b[25] = 1; 13 | sig_a = a[26]; 14 | sig_b = b[31]; 15 | fra_a[25:0] = a[25:0]; 16 | fra_b[24:2] = b[22:0]; 17 | mid = 0; 18 | if(sig_a == sig_b) 19 | begin 20 | outp[27] = sig_a; 21 | outp[26:0] = fra_a + fra_b; 22 | end 23 | else 24 | begin 25 | if(fra_a > fra_b) 26 | begin 27 | outp[27] = sig_a; 28 | mid = (fra_a - fra_b)%fra_a; 29 | outp[26:0] = mid; 30 | end 31 | else if(fra_a < fra_b) 32 | begin 33 | outp[27] = sig_b; 34 | mid = (fra_b - fra_a)%fra_b; 35 | outp[26:0] = mid; 36 | end 37 | else 38 | outp = 0; 39 | end 40 | fra_b[25] = 0; 41 | if(res == 0) 42 | outp = 0; 43 | end 44 | endmodule -------------------------------------------------------------------------------- /Control.v.bak: -------------------------------------------------------------------------------- 1 | module Control(clk,res,exp_diff,big_alu_result, 2 | fra_result,shift_right_bits, 3 | shift_left_bits,shift_right_en,shift_left_en,shift_right_bit, 4 | incre_bit,decre_bit,incre_en,decre_en,mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en); 5 | integer i; 6 | reg [7:0] n=0; 7 | input clk,res; 8 | input [8:0] exp_diff; 9 | input [27:0] big_alu_result,fra_result; 10 | output reg shift_right_en,shift_left_en,incre_en,decre_en; 11 | output reg mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en; 12 | output reg [7:0] shift_right_bit,shift_right_bits; 13 | output reg [7:0] shift_left_bits,incre_bit,decre_bit; 14 | 15 | always @(posedge clk) begin 16 | n=0; 17 | if(exp_diff[8]) 18 | fork 19 | mux_1_en = 1; 20 | mux_2_en = 0; 21 | mux_3_en = 1; 22 | join 23 | else 24 | fork 25 | mux_1_en = 0; 26 | mux_2_en = 1; 27 | mux_3_en = 0; 28 | join 29 | if(exp_diff[7:0]>25) 30 | shift_right_bit = 25; 31 | else 32 | shift_right_bit = exp_diff[7:0]; 33 | shift_right_bit[7] = 1;//mark 34 | mux_5_en = 0; 35 | mux_4_en = 0; 36 | //the incre_decre and shift_left_right module 37 | if(big_alu_result[26]) // add and overflow. 38 | fork 39 | begin 40 | incre_en = 1; 41 | decre_en = 0; 42 | incre_bit = 1; 43 | end 44 | begin 45 | shift_right_en = 1; 46 | shift_left_en = 0; 47 | shift_right_bits = 1; 48 | end 49 | join 50 | else 51 | begin 52 | for(i=25;big_alu_result[i]==0;i=i-1) 53 | n=n+1; 54 | fork 55 | begin 56 | decre_en = 1; 57 | incre_en = 0; 58 | decre_bit = n; 59 | end 60 | begin 61 | shift_left_en = 1; 62 | shift_right_en = 0; 63 | shift_left_bits = n; 64 | end 65 | join 66 | end 67 | //Rounding module 68 | if(fra_result) 69 | begin 70 | mux_5_en = 1; 71 | mux_4_en = 1; 72 | fork 73 | begin 74 | incre_en = 1; 75 | decre_en = 0; 76 | incre_bit = 1; 77 | end 78 | begin 79 | shift_right_en = 1; 80 | shift_left_en = 0; 81 | shift_right_bits = 1; 82 | end 83 | join 84 | end 85 | //Reset 86 | if(!res) 87 | begin 88 | shift_right_en=0; 89 | shift_left_en=0; 90 | incre_en=0; 91 | decre_en=0; 92 | end 93 | end 94 | endmodule -------------------------------------------------------------------------------- /Control.v: -------------------------------------------------------------------------------- 1 | module Control(clk,res,exp_diff,big_alu_result, 2 | fra_result,shift_right_bits, 3 | shift_left_bits,shift_right_en,shift_left_en,shift_right_bit, 4 | incre_bit,decre_bit,incre_en,decre_en,mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en); 5 | integer i; 6 | reg [7:0] n=0; 7 | input clk,res; 8 | input [8:0] exp_diff; 9 | input [27:0] big_alu_result,fra_result; 10 | output reg shift_right_en,shift_left_en,incre_en,decre_en; 11 | output reg mux_1_en,mux_2_en,mux_3_en,mux_4_en,mux_5_en; 12 | output reg [7:0] shift_right_bit,shift_right_bits; 13 | output reg [7:0] shift_left_bits,incre_bit,decre_bit; 14 | 15 | always @(posedge clk) begin 16 | n=0; 17 | //Enables 18 | if(exp_diff[8]) 19 | fork 20 | mux_1_en = 1; 21 | mux_2_en = 0; 22 | mux_3_en = 1; 23 | join 24 | else 25 | fork 26 | mux_1_en = 0; 27 | mux_2_en = 1; 28 | mux_3_en = 0; 29 | join 30 | //shift_right module 31 | if(exp_diff[7:0]>25) 32 | shift_right_bit = 25; 33 | else 34 | shift_right_bit = exp_diff[7:0]; 35 | shift_right_bit[7] = 1;//mark 36 | mux_5_en = 0; 37 | mux_4_en = 0; 38 | //the incre_decre and shift_left_right module 39 | if(big_alu_result[26]) // add and overflow. 40 | fork 41 | begin 42 | incre_en = 1; 43 | decre_en = 0; 44 | incre_bit = 1; 45 | end 46 | begin 47 | shift_right_en = 1; 48 | shift_left_en = 0; 49 | shift_right_bits = 1; 50 | end 51 | join 52 | else 53 | begin 54 | for(i=25;big_alu_result[i]==0;i=i-1) 55 | n=n+1; 56 | fork 57 | begin 58 | decre_en = 1; 59 | incre_en = 0; 60 | decre_bit = n; 61 | end 62 | begin 63 | shift_left_en = 1; 64 | shift_right_en = 0; 65 | shift_left_bits = n; 66 | end 67 | join 68 | end 69 | //Rounding module 70 | if(fra_result) 71 | begin 72 | mux_5_en = 1; 73 | mux_4_en = 1; 74 | fork 75 | begin 76 | incre_en = 1; 77 | decre_en = 0; 78 | incre_bit = 1; 79 | end 80 | begin 81 | shift_right_en = 1; 82 | shift_left_en = 0; 83 | shift_right_bits = 1; 84 | end 85 | join 86 | end 87 | //Reset 88 | if(!res) 89 | begin 90 | shift_right_en=0; 91 | shift_left_en=0; 92 | incre_en=0; 93 | decre_en=0; 94 | end 95 | end 96 | endmodule -------------------------------------------------------------------------------- /Floating_Point_Addition.v: -------------------------------------------------------------------------------- 1 | //top file 2 | module Floating_Point_Addition(clk,reset,x,y); 3 | input clk,reset; 4 | input [31:0] x,y; 5 | //??????????????? 6 | wire[8:0] exp_diff; //???????????? 7 | wire mux_1_en; //???1 ???? 8 | wire mux_2_en; //???2 ???? 9 | wire mux_3_en; //???3 ???? 10 | wire[7:0] mux_1_output; //???1 ????? 11 | wire[31:0] mux_2_output; //???2 ????? 12 | wire[31:0] mux_3_output; //???3 ????? 13 | wire[7:0] shift_right_bit; //???????????????? 14 | wire[26:0] shift_right_output; //????????? 15 | 16 | wire[27:0] big_alu_result; //???????????? 17 | wire[7:0] shift_right_bits; //????????????? 18 | wire[7:0] shift_left_bits; //????????????? 19 | wire shift_right_en; //??????????????? 20 | wire shift_left_en; //??????????????? 21 | wire[27:0] mux_4_output; //???4 ????? 22 | wire mux_4_en; //???4 ???? 23 | wire[27:0] shift_left_right_output; //?????????????????? 24 | wire[7:0] incre_bit; //?????????? 25 | wire[7:0] decre_bit; //?????????? 26 | wire incre_en; //???????????? 27 | wire decre_en; //???????????? 28 | wire mux_5_en; //???5 ???? 29 | wire[7:0] mux_5_output; //???5 ????? 30 | wire[7:0] rounding_exp_result; //???????????? 31 | wire[8:0] incre_decre_output; //?????????????? 32 | wire[27:0] fra_result; //???? 33 | wire[31:0] result; 34 | wire overflow; //????? 35 | 36 | //????????????????? 37 | Small_Alu 38 | Small_Alu_instance( 39 | //???? 40 | clk, 41 | reset, 42 | x, 43 | y, 44 | //???? 45 | exp_diff //???????????????? 46 | ); 47 | 48 | //??? 49 | Control 50 | Control_instance( 51 | clk, 52 | reset, 53 | exp_diff, 54 | big_alu_result, 55 | fra_result, 56 | shift_right_bits, 57 | 58 | shift_left_bits, 59 | shift_right_en, 60 | shift_left_en, 61 | shift_right_bit, 62 | incre_bit, 63 | decre_bit, 64 | incre_en, 65 | decre_en, 66 | mux_1_en, 67 | mux_2_en, 68 | mux_3_en, 69 | mux_4_en, 70 | mux_5_en 71 | ); 72 | 73 | //???1 74 | Mux_1 75 | Mux_1_instance( 76 | clk, 77 | reset, 78 | x, 79 | y, 80 | mux_1_en, 81 | mux_1_output 82 | ); 83 | 84 | //???2 85 | Mux_2 86 | Mux_2_instance( 87 | clk, 88 | reset, 89 | x, 90 | y, 91 | mux_2_en, 92 | mux_2_output 93 | ); 94 | 95 | //???3 96 | Mux_3 97 | Mux_3_instance( 98 | clk, 99 | reset, 100 | x, 101 | y, 102 | mux_3_en, 103 | mux_3_output 104 | ); 105 | 106 | Shift_Right //???????????????? 107 | Shift_Right_instance( 108 | clk, 109 | reset, 110 | shift_right_bit, 111 | mux_2_output, 112 | shift_right_output //??shift_right_bit??mux_2_output ???? 113 | ); 114 | 115 | //??????????? 116 | Big_Alu 117 | Big_Alu_instance( 118 | clk, 119 | reset, 120 | shift_right_output, 121 | mux_3_output, 122 | big_alu_result //mux_3_output ?shift_right_output ????????big_alu_result 123 | ); 124 | 125 | //???4 126 | Mux_4 127 | Mux_4_instance( 128 | clk, 129 | reset, 130 | mux_4_en, 131 | big_alu_result, 132 | fra_result, 133 | mux_4_output 134 | ); 135 | 136 | Shift_Left_Right //??????????? 137 | Shift_Left_Right_instance( 138 | clk, 139 | reset, 140 | shift_left_bits, 141 | shift_right_bits, 142 | shift_left_en, 143 | shift_right_en, 144 | mux_4_output, 145 | shift_left_right_output 146 | ); 147 | 148 | //???5 149 | Mux_5 150 | Mux_5_instance( 151 | clk, 152 | reset, 153 | mux_5_en, 154 | mux_1_output, 155 | rounding_exp_result, 156 | mux_5_output 157 | ); 158 | 159 | Incre_Decre //??????????? 160 | Incre_Decre_instance( 161 | clk, 162 | reset, 163 | incre_bit, 164 | decre_bit, 165 | incre_en, 166 | decre_en, 167 | mux_5_output, 168 | incre_decre_output //??incre_bit ?incre_en??mux_5_output??????decre_bit ?decre_en??mux_5_output ??? 169 | ); 170 | 171 | //?????? 172 | Rounding 173 | Rounding_instance( 174 | clk, 175 | reset, 176 | shift_left_right_output, 177 | incre_decre_output, 178 | rounding_exp_result, 179 | fra_result, //???? 180 | result, 181 | overflow //???? 182 | ); 183 | 184 | endmodule -------------------------------------------------------------------------------- /Floating_Point_Addition.v.bak: -------------------------------------------------------------------------------- 1 | //top file 2 | module Floating_Point_Addition(clk,reset,x,y); 3 | input clk,reset; 4 | input [31:0] x,y; 5 | //??????????????? 6 | wire[8:0] exp_diff; //???????????? 7 | wire mux_1_en; //???1 ???? 8 | wire mux_2_en; //???2 ???? 9 | wire mux_3_en; //???3 ???? 10 | wire[7:0] mux_1_output; //???1 ????? 11 | wire[31:0] mux_2_output; //???2 ????? 12 | wire[31:0] mux_3_output; //???3 ????? 13 | wire[7:0] shift_right_bit; //???????????????? 14 | wire[26:0] shift_right_output; //????????? 15 | 16 | wire[27:0] big_alu_result; //???????????? 17 | wire[7:0] shift_right_bits; //????????????? 18 | wire[7:0] shift_left_bits; //????????????? 19 | wire shift_right_en; //??????????????? 20 | wire shift_left_en; //??????????????? 21 | wire[27:0] mux_4_output; //???4 ????? 22 | wire mux_4_en; //???4 ???? 23 | wire[5:0] shift_left_right_output; //?????????????????? 24 | wire[7:0] incre_bit; //?????????? 25 | wire[7:0] decre_bit; //?????????? 26 | wire incre_en; //???????????? 27 | wire decre_en; //???????????? 28 | wire mux_5_en; //???5 ???? 29 | wire[7:0] mux_5_output; //???5 ????? 30 | wire[7:0] rounding_exp_result; //???????????? 31 | wire[8:0] incre_decre_output; //?????????????? 32 | wire[27:0] fra_result; //???? 33 | wire[31:0] result; 34 | wire overflow; //????? 35 | 36 | //????????????????? 37 | Small_Alu 38 | Small_Alu_instance( 39 | //???? 40 | clk, 41 | reset, 42 | x, 43 | y, 44 | //???? 45 | exp_diff //???????????????? 46 | ); 47 | 48 | //??? 49 | Control 50 | Control_instance( 51 | clk, 52 | reset, 53 | exp_diff, 54 | big_alu_result, 55 | fra_result, 56 | shift_right_bits, 57 | 58 | shift_left_bits, 59 | shift_right_en, 60 | shift_left_en, 61 | shift_right_bit, 62 | incre_bit, 63 | decre_bit, 64 | incre_en, 65 | decre_en, 66 | mux_1_en, 67 | mux_2_en, 68 | mux_3_en, 69 | mux_4_en, 70 | mux_5_en 71 | ); 72 | 73 | //???1 74 | Mux_1 75 | Mux_1_instance( 76 | clk, 77 | reset, 78 | x, 79 | y, 80 | mux_1_en, 81 | mux_1_output 82 | ); 83 | 84 | //???2 85 | Mux_2 86 | Mux_2_instance( 87 | clk, 88 | reset, 89 | x, 90 | y, 91 | mux_2_en, 92 | mux_2_output 93 | ); 94 | 95 | //???3 96 | Mux_3 97 | Mux_3_instance( 98 | clk, 99 | reset, 100 | x, 101 | y, 102 | mux_3_en, 103 | mux_3_output 104 | ); 105 | 106 | Shift_Right //???????????????? 107 | Shift_Right_instance( 108 | clk, 109 | reset, 110 | shift_right_bit, 111 | mux_2_output, 112 | shift_right_output //??shift_right_bit??mux_2_output ???? 113 | ); 114 | 115 | //??????????? 116 | Big_Alu 117 | Big_Alu_instance( 118 | clk, 119 | reset, 120 | shift_right_output, 121 | mux_3_output, 122 | big_alu_result //mux_3_output ?shift_right_output ????????big_alu_result 123 | ); 124 | 125 | //???4 126 | Mux_4 127 | Mux_4_instance( 128 | clk, 129 | reset, 130 | mux_4_en, 131 | big_alu_result, 132 | fra_result, 133 | mux_4_output 134 | ); 135 | 136 | Shift_Left_Right //??????????? 137 | Shift_Left_Right_instance( 138 | clk, 139 | reset, 140 | shift_left_bits, 141 | shift_right_bits, 142 | shift_left_en, 143 | shift_right_en, 144 | mux_4_output, 145 | shift_left_right_output 146 | ); 147 | 148 | //???5 149 | Mux_5 150 | Mux_5_instance( 151 | clk, 152 | reset, 153 | mux_5_en, 154 | mux_1_output, 155 | rounding_exp_result, 156 | mux_5_output 157 | ); 158 | 159 | Incre_Decre //??????????? 160 | Incre_Decre_instance( 161 | clk, 162 | reset, 163 | incre_bit, 164 | decre_bit, 165 | incre_en, 166 | decre_en, 167 | mux_5_output, 168 | incre_decre_output //??incre_bit ?incre_en??mux_5_output??????decre_bit ?decre_en??mux_5_output ??? 169 | ); 170 | 171 | //?????? 172 | Rounding 173 | Rounding_instance( 174 | clk, 175 | reset, 176 | shift_left_right_output, 177 | incre_decre_output, 178 | rounding_exp_result, 179 | fra_result, //???? 180 | result, 181 | overflow //???? 182 | ); 183 | 184 | endmodule -------------------------------------------------------------------------------- /pdas.cr.mti: -------------------------------------------------------------------------------- 1 | C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v 2 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 3 | -- Compiling module Incre_Decre 4 | 5 | Top level modules: 6 | Incre_Decre 7 | 8 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Rounding.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Rounding.v 9 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 10 | -- Compiling module Rounding 11 | 12 | Top level modules: 13 | Rounding 14 | 15 | } {} {}} C:/modeltech64_10.0d/examples/pdas/tese_bench.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/tese_bench.v 16 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 17 | -- Compiling module test_bench 18 | 19 | Top level modules: 20 | test_bench 21 | 22 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 23 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 24 | -- Compiling module Floating_Point_Addition 25 | 26 | Top level modules: 27 | Floating_Point_Addition 28 | 29 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Mux_1.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Mux_1.v 30 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 31 | -- Compiling module Mux_1 32 | 33 | Top level modules: 34 | Mux_1 35 | 36 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Small_Alu.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Small_Alu.v 37 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 38 | -- Compiling module Small_Alu 39 | 40 | Top level modules: 41 | Small_Alu 42 | 43 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Shift_Right.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 44 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 45 | -- Compiling module Shift_Right 46 | 47 | Top level modules: 48 | Shift_Right 49 | 50 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Mux_2.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Mux_2.v 51 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 52 | -- Compiling module Mux_2 53 | 54 | Top level modules: 55 | Mux_2 56 | 57 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Mux_3.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Mux_3.v 58 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 59 | -- Compiling module Mux_3 60 | 61 | Top level modules: 62 | Mux_3 63 | 64 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 65 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 66 | -- Compiling module Shift_Left_Right 67 | 68 | Top level modules: 69 | Shift_Left_Right 70 | 71 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Mux_4.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Mux_4.v 72 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 73 | -- Compiling module Mux_4 74 | 75 | Top level modules: 76 | Mux_4 77 | 78 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Mux_5.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Mux_5.v 79 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 80 | -- Compiling module Mux_5 81 | 82 | Top level modules: 83 | Mux_5 84 | 85 | } {} {}} C:/modeltech64_10.0d/examples/pdas/Control.v {1 {vlog -work pda -vopt -nocovercells C:/modeltech64_10.0d/examples/pdas/Control.v 86 | Model Technology ModelSim SE-64 vlog 10.0d Compiler 2011.10 Oct 30 2011 87 | -- Compiling module Control 88 | 89 | Top level modules: 90 | Control 91 | 92 | } {} {}} 93 | -------------------------------------------------------------------------------- /pda/@_opt/vopt7fzzqa: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | 13 4 | cModel Technology 5 | Z0 dC:\modeltech64_10.0d\examples\FPA 6 | T_opt 7 | Z1 Vd8eVT;eA;S8=FAmEWhWiW1 8 | Z2 04 23 4 work Floating_Point_Addition fast 0 9 | Z3 =1-00224398a8ab-4eede18c-b8-20d8 10 | Z4 o-quiet -auto_acc_if_foreign -work pda 11 | Z5 n@_opt 12 | Z6 OL;O;10.0d;49 13 | Z7 dC:\modeltech64_10.0d\examples\FPA 14 | vBig_Alu 15 | Z8 IZ1fkUJU13RUj;I9lGQn]c3 16 | Z9 V:LjUmzi]959iX56eg9bVg2 17 | Z10 dC:\modeltech64_10.0d\examples\pdas 18 | Z11 w1324193890 19 | Z12 8C:/modeltech64_10.0d/examples/pdas/Big_Alu.v 20 | Z13 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| Z82 IB7hCQhlh=D2G5bJajgSYj0 149 | Z83 VP4lhMXjdmHVCklhfR0@Ge3 150 | R10 151 | Z84 w1324212483 152 | Z85 8C:/modeltech64_10.0d/examples/pdas/Mux_4.v 153 | Z86 FC:/modeltech64_10.0d/examples/pdas/Mux_4.v 154 | L0 1 155 | R14 156 | r1 157 | 31 158 | R15 159 | R16 160 | Z87 n@mux_4 161 | Z88 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_4.v| 162 | Z89 !s100 lTIXWR0^>Wc_iM2hg?^2ePP41 206 | Z113 V@]amBla6Q:^]fiN:Pb=ES;2`zH2 221 | Z117 !s108 1324211759.487000 222 | !s85 0 223 | vShift_Left_Right 224 | Z118 I^T@6V`kWlb9OY>dB`ZDG;2 225 | Z119 Vz[@TNb7Efo_jjQo_JSh:83 226 | R10 227 | Z120 w1324203703 228 | Z121 8C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 229 | Z122 FC:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 230 | L0 1 231 | R14 232 | r1 233 | 31 234 | R15 235 | R16 236 | Z123 n@shift_@left_@right 237 | Z124 !s100 z2?CDfHH`f`UUDdkM17Dd1 238 | Z125 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 239 | Z126 !s108 1324212603.940000 240 | Z127 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 241 | !s85 0 242 | vShift_Right 243 | Z128 IXL5[G;KIo3XT@iVUOKcJf1 244 | Z129 VJ5hQ5ZSo^DOdk[WCkSfK^3 245 | R10 246 | Z130 w1324193163 247 | Z131 8C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 248 | Z132 FC:/modeltech64_10.0d/examples/pdas/Shift_Right.v 249 | L0 1 250 | R14 251 | r1 252 | 31 253 | R15 254 | R16 255 | Z133 n@shift_@right 256 | Z134 !s100 5V5;CS_:SGQJ4nX8ZQFV90 257 | Z135 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 258 | Z136 !s108 1324212604.221000 259 | Z137 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 260 | !s85 0 261 | vSmall_Alu 262 | Z138 IB@>XBi:Q_N`><6VR=9a2`0 263 | Z139 V=dL4OZZ?Vmia:5@VkN2 39 | !s108 1324270884.935000 40 | !s107 C:/modeltech64_10.0d/examples/pdas/Big_Alu.v| 41 | vControl 42 | VCUGk[gA8nXcL0 43 | r1 44 | 31 45 | I_I_Jn?I49EDGdPl:>Ga3 81 | r1 82 | 31 83 | IZbdHDLJ>gI^?1 141 | R4 142 | w1324044041 143 | 8C:/modeltech64_10.0d/examples/pdas/Mux_3.v 144 | FC:/modeltech64_10.0d/examples/pdas/Mux_3.v 145 | L0 1 146 | R5 147 | R6 148 | R7 149 | n@mux_3 150 | !s85 0 151 | !s100 ;l01o9aQ]Q?0f88dKakfU3 152 | !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 153 | !s108 1324270886.727000 154 | !s107 C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 155 | vMux_4 156 | VAhg?^2ePP41 214 | V@]amBla6Q:^]fiN:Pb=ES;2`zH2 229 | !s108 1324211759.487000 230 | !s85 0 231 | vShift_Left_Right 232 | Vz[@TNb7Efo_jjQo_JSh:83 233 | r1 234 | 31 235 | IfooDj4nG?8ZMlX1>Q5:c_0 236 | R4 237 | w1324257870 238 | 8C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 239 | FC:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 240 | L0 1 241 | R5 242 | R6 243 | R7 244 | n@shift_@left_@right 245 | !s85 0 246 | !s100 n25[^3CcWVLNDF7`7D_Bn2 247 | !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 248 | !s108 1324270887.831000 249 | !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 250 | vShift_Right 251 | VJ5hQ5ZSo^DOdk[WCkSfK^3 252 | r1 253 | 31 254 | IFLFad>kCAD6XETLmzacnH3 255 | R4 256 | w1324259010 257 | 8C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 258 | FC:/modeltech64_10.0d/examples/pdas/Shift_Right.v 259 | L0 1 260 | R5 261 | R6 262 | R7 263 | n@shift_@right 264 | !s85 0 265 | !s100 9=V?C:IXQ776a?8IoPHI[ji2AGh`R0 24 | Z13 V:LjUmzi]959iX56eg9bVg2 25 | Z14 dC:\modeltech64_10.0d\examples\pdas 26 | Z15 w1324219603 27 | Z16 8C:/modeltech64_10.0d/examples/pdas/Big_Alu.v 28 | Z17 FC:/modeltech64_10.0d/examples/pdas/Big_Alu.v 29 | L0 1 30 | Z18 OL;L;10.0d;49 31 | r1 32 | 31 33 | Z19 !s102 -nocovercells 34 | Z20 o-work pda -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF 35 | Z21 n@big_@alu 36 | Z22 !s100 Gdn9CCO^^lMTzR=]o[bOo1 37 | Z23 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Big_Alu.v| 38 | Z24 !s108 1324264835.075000 39 | Z25 !s107 C:/modeltech64_10.0d/examples/pdas/Big_Alu.v| 40 | !s85 0 41 | vControl 42 | Z26 I_I_Jn?L0 44 | R14 45 | Z28 w1324263463 46 | Z29 8C:/modeltech64_10.0d/examples/pdas/Control.v 47 | Z30 FC:/modeltech64_10.0d/examples/pdas/Control.v 48 | L0 1 49 | R18 50 | r1 51 | 31 52 | R19 53 | R20 54 | Z31 n@control 55 | Z32 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Control.v| 56 | Z33 !s100 0EliB7d_Z]cFa;KSXzC]O1 57 | Z34 !s108 1324264835.331000 58 | Z35 !s107 C:/modeltech64_10.0d/examples/pdas/Control.v| 59 | !s85 0 60 | vFloating_Point_Addition 61 | Z36 I2?`K9;gjWek?U[Zjh_ZC93 62 | Z37 V7Y1J=3bHDh2V`NW=GG2SL0 63 | R14 64 | Z38 w1324213183 65 | Z39 8C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 66 | Z40 FC:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 67 | L0 2 68 | R18 69 | r1 70 | 31 71 | R19 72 | R20 73 | Z41 n@floating_@point_@addition 74 | Z42 !s100 ANEI^]MYoGjaDSXCWzj]L3 75 | Z43 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 76 | Z44 !s108 1324264835.618000 77 | Z45 !s107 C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 78 | !s85 0 79 | vIncre_Decre 80 | Z46 IZI49EDGdPl:>Ga3 82 | R14 83 | Z48 w1324212531 84 | Z49 8C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v 85 | Z50 FC:/modeltech64_10.0d/examples/pdas/Incre_Decre.v 86 | L0 1 87 | R18 88 | r1 89 | 31 90 | R19 91 | R20 92 | Z51 n@incre_@decre 93 | Z52 !s100 ?SCL8`Y8QhDjQA5MR^61=1 94 | Z53 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v| 95 | Z54 !s108 1324264835.870000 96 | Z55 !s107 C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v| 97 | !s85 0 98 | vMux_1 99 | Z56 I]GSlO9=cZzFg6]bdHDLJ>gI^?1 138 | Z77 Vab86m?4@1k[_CU:bM3IRN0 139 | R14 140 | Z78 w1324044041 141 | Z79 8C:/modeltech64_10.0d/examples/pdas/Mux_3.v 142 | Z80 FC:/modeltech64_10.0d/examples/pdas/Mux_3.v 143 | L0 1 144 | R18 145 | r1 146 | 31 147 | R19 148 | R20 149 | Z81 n@mux_3 150 | Z82 !s100 ;l01o9aQ]Q?0f88dKakfU3 151 | Z83 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 152 | Z84 !s108 1324264836.698000 153 | Z85 !s107 C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 154 | !s85 0 155 | vMux_4 156 | Z86 Iihg?^2ePP41 214 | Z117 V@]amBla6Q:^]fiN:Pb=ES;2`zH2 229 | Z121 !s108 1324211759.487000 230 | !s85 0 231 | vShift_Left_Right 232 | Z122 IfooDj4nG?8ZMlX1>Q5:c_0 233 | Z123 Vz[@TNb7Efo_jjQo_JSh:83 234 | R14 235 | Z124 w1324257870 236 | Z125 8C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 237 | Z126 FC:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 238 | L0 1 239 | R18 240 | r1 241 | 31 242 | R19 243 | R20 244 | Z127 n@shift_@left_@right 245 | Z128 !s100 n25[^3CcWVLNDF7`7D_Bn2 246 | Z129 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 247 | Z130 !s108 1324264837.783000 248 | Z131 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 249 | !s85 0 250 | vShift_Right 251 | Z132 IFLFad>kCAD6XETLmzacnH3 252 | Z133 VJ5hQ5ZSo^DOdk[WCkSfK^3 253 | R14 254 | Z134 w1324259010 255 | Z135 8C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 256 | Z136 FC:/modeltech64_10.0d/examples/pdas/Shift_Right.v 257 | L0 1 258 | R18 259 | r1 260 | 31 261 | R19 262 | R20 263 | Z137 n@shift_@right 264 | Z138 !s100 9=V?C:IXQL0 44 | R14 45 | Z28 w1324210402 46 | Z29 8C:/modeltech64_10.0d/examples/pdas/Control.v 47 | Z30 FC:/modeltech64_10.0d/examples/pdas/Control.v 48 | L0 1 49 | R18 50 | r1 51 | 31 52 | R19 53 | R20 54 | Z31 n@control 55 | Z32 !s100 iDe?WE=RQ__z3QX;LTdSH2 56 | Z33 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Control.v| 57 | Z34 !s108 1324213221.752000 58 | Z35 !s107 C:/modeltech64_10.0d/examples/pdas/Control.v| 59 | !s85 0 60 | vFloating_Point_Addition 61 | Z36 I2?`K9;gjWek?U[Zjh_ZC93 62 | Z37 V7Y1J=3bHDh2V`NW=GG2SL0 63 | R14 64 | Z38 w1324213183 65 | Z39 8C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 66 | Z40 FC:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 67 | L0 2 68 | R18 69 | r1 70 | 31 71 | R19 72 | R20 73 | Z41 n@floating_@point_@addition 74 | Z42 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 75 | Z43 !s100 ANEI^]MYoGjaDSXCWzj]L3 76 | Z44 !s108 1324213222.059000 77 | Z45 !s107 C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 78 | !s85 0 79 | vIncre_Decre 80 | Z46 IZI49EDGdPl:>Ga3 82 | R14 83 | Z48 w1324212531 84 | Z49 8C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v 85 | Z50 FC:/modeltech64_10.0d/examples/pdas/Incre_Decre.v 86 | L0 1 87 | R18 88 | r1 89 | 31 90 | R19 91 | R20 92 | Z51 n@incre_@decre 93 | Z52 !s100 ?SCL8`Y8QhDjQA5MR^61=1 94 | Z53 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v| 95 | Z54 !s108 1324213222.620000 96 | Z55 !s107 C:/modeltech64_10.0d/examples/pdas/Incre_Decre.v| 97 | !s85 0 98 | vMux_1 99 | Z56 IO<:@oIT1QBPAKljmzMW@80 100 | Z57 VggA4NMBAAPNNRj76Tdaj@0 101 | R14 102 | Z58 w1324044717 103 | Z59 8C:/modeltech64_10.0d/examples/pdas/Mux_1.v 104 | Z60 FC:/modeltech64_10.0d/examples/pdas/Mux_1.v 105 | L0 1 106 | R18 107 | r1 108 | 31 109 | R19 110 | R20 111 | Z61 n@mux_1 112 | Z62 !s100 X3OebdUQ_CGbUiK66IFo33 113 | Z63 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_1.v| 114 | Z64 !s108 1324213222.973000 115 | Z65 !s107 C:/modeltech64_10.0d/examples/pdas/Mux_1.v| 116 | !s85 0 117 | vMux_2 118 | Z66 ICoHT0?iEOK8_B358JGOL@1 119 | Z67 Vo5d7;c[3dXlZjnGCd;ePZ3 120 | R14 121 | Z68 w1324044050 122 | Z69 8C:/modeltech64_10.0d/examples/pdas/Mux_2.v 123 | Z70 FC:/modeltech64_10.0d/examples/pdas/Mux_2.v 124 | L0 1 125 | R18 126 | r1 127 | 31 128 | R19 129 | R20 130 | Z71 n@mux_2 131 | Z72 !s100 _8LTQlV;n:60lPZZ^OIa01 132 | Z73 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_2.v| 133 | Z74 !s108 1324213223.328000 134 | Z75 !s107 C:/modeltech64_10.0d/examples/pdas/Mux_2.v| 135 | !s85 0 136 | vMux_3 137 | Z76 I33VzXVI3]>bdHDLJ>gI^?1 138 | Z77 Vab86m?4@1k[_CU:bM3IRN0 139 | R14 140 | Z78 w1324044041 141 | Z79 8C:/modeltech64_10.0d/examples/pdas/Mux_3.v 142 | Z80 FC:/modeltech64_10.0d/examples/pdas/Mux_3.v 143 | L0 1 144 | R18 145 | r1 146 | 31 147 | R19 148 | R20 149 | Z81 n@mux_3 150 | Z82 !s100 ;l01o9aQ]Q?0f88dKakfU3 151 | Z83 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 152 | Z84 !s108 1324213223.632000 153 | Z85 !s107 C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 154 | !s85 0 155 | vMux_4 156 | Z86 IB7hCQhlh=D2G5bJajgSYj0 157 | Z87 VP4lhMXjdmHVCklhfR0@Ge3 158 | R14 159 | Z88 w1324212483 160 | Z89 8C:/modeltech64_10.0d/examples/pdas/Mux_4.v 161 | Z90 FC:/modeltech64_10.0d/examples/pdas/Mux_4.v 162 | L0 1 163 | R18 164 | r1 165 | 31 166 | R19 167 | R20 168 | Z91 n@mux_4 169 | Z92 !s100 lTIXWR0^>Wc_iM2hg?^2ePP41 214 | Z117 V@]amBla6Q:^]fiN:Pb=ES;2`zH2 229 | Z121 !s108 1324211759.487000 230 | !s85 0 231 | vShift_Left_Right 232 | Z122 I^T@6V`kWlb9OY>dB`ZDG;2 233 | Z123 Vz[@TNb7Efo_jjQo_JSh:83 234 | R14 235 | Z124 w1324203703 236 | Z125 8C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 237 | Z126 FC:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 238 | L0 1 239 | R18 240 | r1 241 | 31 242 | R19 243 | R20 244 | Z127 n@shift_@left_@right 245 | Z128 !s100 z2?CDfHH`f`UUDdkM17Dd1 246 | Z129 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 247 | Z130 !s108 1324213225.051000 248 | Z131 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 249 | !s85 0 250 | vShift_Right 251 | Z132 IXL5[G;KIo3XT@iVUOKcJf1 252 | Z133 VJ5hQ5ZSo^DOdk[WCkSfK^3 253 | R14 254 | Z134 w1324193163 255 | Z135 8C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 256 | Z136 FC:/modeltech64_10.0d/examples/pdas/Shift_Right.v 257 | L0 1 258 | R18 259 | r1 260 | 31 261 | R19 262 | R20 263 | Z137 n@shift_@right 264 | Z138 !s100 5V5;CS_:SGQJ4nX8ZQFV90 265 | Z139 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 266 | Z140 !s108 1324213225.409000 267 | Z141 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 268 | !s85 0 269 | vSmall_Alu 270 | Z142 IB@>XBi:Q_N`><6VR=9a2`0 271 | Z143 V=dL4OZZ?Vm:0RCOG[HnBn4nT2 290 | Z153 VEJNK5ZO7TWUP1egUA9^TR1 291 | R14 292 | Z154 w1324213009 293 | Z155 8C:/modeltech64_10.0d/examples/pdas/tese_bench.v 294 | Z156 FC:/modeltech64_10.0d/examples/pdas/tese_bench.v 295 | L0 1 296 | R18 297 | r1 298 | 31 299 | R19 300 | R20 301 | Z157 !s100 TgLlAm1X[G7hbDiW^C[>E1 302 | Z158 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/tese_bench.v| 303 | !s85 0 304 | Z159 !s108 1324213225.959000 305 | Z160 !s107 C:/modeltech64_10.0d/examples/pdas/tese_bench.v| 306 | -------------------------------------------------------------------------------- /pda/@_opt1/voptxm6vf1: -------------------------------------------------------------------------------- 1 | m255 2 | K3 3 | 13 4 | cModel Technology 5 | Z0 dC:\modeltech64_10.0d\examples\FPA 6 | T_opt 7 | Z1 Vd8eVT;eA;S8=FAmEWhWiW1 8 | Z2 04 23 4 work Floating_Point_Addition fast 0 9 | Z3 =1-00224398a8ab-4eede18c-b8-20d8 10 | Z4 o-quiet -auto_acc_if_foreign -work pda 11 | Z5 n@_opt 12 | Z6 OL;O;10.0d;49 13 | Z7 dC:\modeltech64_10.0d\examples\FPA 14 | T_opt1 15 | Z8 V2fICl2TonVkFXh0S4?3M`3 16 | Z9 04 10 4 work test_bench fast 0 17 | Z10 =1-00224398a8ab-4eee8d4a-18f-30c 18 | R4 19 | Z11 n@_opt1 20 | R6 21 | R7 22 | vBig_Alu 23 | Z12 V:LjUmzi]959iX56eg9bVg2 24 | r1 25 | 31 26 | Z13 I>776a?8IoPHI[ji2AGh`R0 27 | Z14 dC:\modeltech64_10.0d\examples\pdas 28 | Z15 w1324219603 29 | Z16 8C:/modeltech64_10.0d/examples/pdas/Big_Alu.v 30 | Z17 FC:/modeltech64_10.0d/examples/pdas/Big_Alu.v 31 | L0 1 32 | Z18 OL;L;10.0d;49 33 | Z19 !s102 -nocovercells 34 | Z20 o-work pda -nocovercells -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF 35 | Z21 n@big_@alu 36 | !s85 0 37 | Z22 !s100 Gdn9CCO^^lMTzR=]o[bOo1 38 | Z23 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Big_Alu.v| 39 | Z24 !s108 1324221283.852000 40 | Z25 !s107 C:/modeltech64_10.0d/examples/pdas/Big_Alu.v| 41 | vControl 42 | Z26 VCUGk[gA8nXcL0 43 | r1 44 | 31 45 | Z27 IinDLVC=VUSklTjaQ>PDbh0 46 | R14 47 | Z28 w1324220218 48 | Z29 8C:/modeltech64_10.0d/examples/pdas/Control.v 49 | Z30 FC:/modeltech64_10.0d/examples/pdas/Control.v 50 | L0 1 51 | R18 52 | R19 53 | R20 54 | Z31 n@control 55 | !s85 0 56 | Z32 !s100 VD8g]@iV9CjJSbF1i]>KU1 57 | Z33 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Control.v| 58 | Z34 !s108 1324221284.086000 59 | Z35 !s107 C:/modeltech64_10.0d/examples/pdas/Control.v| 60 | vFloating_Point_Addition 61 | Z36 V7Y1J=3bHDh2V`NW=GG2SL0 62 | r1 63 | 31 64 | Z37 I2?`K9;gjWek?U[Zjh_ZC93 65 | R14 66 | Z38 w1324213183 67 | Z39 8C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 68 | Z40 FC:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v 69 | L0 2 70 | R18 71 | R19 72 | R20 73 | Z41 n@floating_@point_@addition 74 | !s85 0 75 | Z42 !s100 ANEI^]MYoGjaDSXCWzj]L3 76 | Z43 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 77 | Z44 !s108 1324221284.429000 78 | Z45 !s107 C:/modeltech64_10.0d/examples/pdas/Floating_Point_Addition.v| 79 | vIncre_Decre 80 | Z46 V1[g7@0[>I49EDGdPl:>Ga3 81 | r1 82 | 31 83 | Z47 IZbdHDLJ>gI^?1 141 | R14 142 | Z78 w1324044041 143 | Z79 8C:/modeltech64_10.0d/examples/pdas/Mux_3.v 144 | Z80 FC:/modeltech64_10.0d/examples/pdas/Mux_3.v 145 | L0 1 146 | R18 147 | R19 148 | R20 149 | Z81 n@mux_3 150 | !s85 0 151 | Z82 !s100 ;l01o9aQ]Q?0f88dKakfU3 152 | Z83 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 153 | Z84 !s108 1324221285.677000 154 | Z85 !s107 C:/modeltech64_10.0d/examples/pdas/Mux_3.v| 155 | vMux_4 156 | Z86 VAhg?^2ePP41 214 | Z117 V@]amBla6Q:^]fiN:Pb=ES;2`zH2 229 | Z121 !s108 1324211759.487000 230 | !s85 0 231 | vShift_Left_Right 232 | Z122 Vz[@TNb7Efo_jjQo_JSh:83 233 | r1 234 | 31 235 | Z123 I^T@6V`kWlb9OY>dB`ZDG;2 236 | R14 237 | Z124 w1324203703 238 | Z125 8C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 239 | Z126 FC:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v 240 | L0 1 241 | R18 242 | R19 243 | R20 244 | Z127 n@shift_@left_@right 245 | !s85 0 246 | Z128 !s100 z2?CDfHH`f`UUDdkM17Dd1 247 | Z129 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 248 | Z130 !s108 1324221286.894000 249 | Z131 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Left_Right.v| 250 | vShift_Right 251 | Z132 VJ5hQ5ZSo^DOdk[WCkSfK^3 252 | r1 253 | 31 254 | Z133 IMeB8:_CIiz=@LB=EKG7_?2 255 | R14 256 | Z134 w1324217646 257 | Z135 8C:/modeltech64_10.0d/examples/pdas/Shift_Right.v 258 | Z136 FC:/modeltech64_10.0d/examples/pdas/Shift_Right.v 259 | L0 1 260 | R18 261 | R19 262 | R20 263 | Z137 n@shift_@right 264 | !s85 0 265 | Z138 !s100 CzCON_9g5@8LWIckEV0:n1 266 | Z139 !s90 -reportprogress|300|-work|pda|-vopt|-nocovercells|C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 267 | Z140 !s108 1324221287.159000 268 | Z141 !s107 C:/modeltech64_10.0d/examples/pdas/Shift_Right.v| 269 | vSmall_Alu 270 | Z142 V=dL4OZZ?Vm:nDUVf 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | 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Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | --------------------------------------------------------------------------------