├── README.md
└── TopCtrl.vhd


/README.md:
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  1 | # NISC
  2 | A single instruction set processor architecture  
  3 | This is my first time using Github.  
  4 | Currently only preliminary specifications are given and may be further refined.  
  5 | Suggestions and requests are welcome.  
  6 | When I figure out how to do it I would like to list proposals and have a vote on which to implement.  
  7 | Implementing this might be a good project for a processor design course.  
  8 | VHDL code to follow when specs are firm.
  9 | ## About NISC
 10 | NISC is my particular brand of One Instruction Set Computer (OISC) with Transport Triggered Architecture (TTA).  
 11 | The operation it performs is Move.  
 12 | I call it NISC for Null Instruction Set Computer because the set of all opcodes is the null set.  
 13 | There is no instruction which tells it to Move. It just Moves.  
 14 | It is not related to [No Instruction Set Computing](https://en.wikipedia.org/wiki/No_instruction_set_computing).  
 15 | I didn't want to call it SISC for Single Instruction Set Computer because SISC sounds like CISC and I like to avoid confusion. I wasn't sure how to pronounce OISC. I also ruled out Mono-Instuction Set Computer (MISC) because I didn't want it filed under Misc.  
 16 | Although there is no opcode, instructions take two (or three) arguments.  
 17 | The arguments are source address, destination address, and immediate data.  
 18 | The source address and destination address are always present but the immediate data is optional.  
 19 | NISC is an entire family with a scalable architecture.  
 20 | What will be described is NISC6 because data and addresses are 2 to the 6th power (64 bits). NISC5 has 32 bit data and addresses. 
 21 | ## The Controller
 22 | - There is a state machine which controls overall operation.
 23 | - There are 3 registers which are not directly visible to the programmer.
 24 |  1. SAR Source Address Register
 25 |  2. DAR Destination Address Register
 26 |  3. TMP Temporary Register
 27 | - Everything else is memory mapped starting at the beginning of memory. There is a single memory space.
 28 | - The memory is not byte addressable like many processors. Each address holds a 64 bit Word.
 29 | - It is Little Endian where applicable.
 30 | - Peripherals should be memory mapped.
 31 |  
 32 | This is the Von Neumann version with unified code and data address space.
 33 | Using a Harvard architecture with separate code and data spaces would double throughput but would require instruction invalidation for Jumps and Calls. I wanted to keep it simple.
 34 | Making data and address widths equal allows us to fetch an address in a single cycle. If the data width is less than address width then multiple cycles are needed to fetch an address. With a wider data width, both addresses may be read at once saving a cycle.
 35 | 
 36 | The state machine controller normally cycles through 4 states:
 37 |  1. Output AP, Fetch Source Address, Increment AP (Argument Pointer, same as a Program Counter)
 38 |  2. Output AP, Fetch Destination Address, Increment AP
 39 |  3. Read from Source Address into TMP
 40 |  4. Write TMP to Destination Address
 41 | and then it repeats.
 42 | 
 43 | Before it gets to state 1 the machine looks for Int and DMA Requests and will go to other states to acknowledge them. Once state 1 starts Int and DMA Requests will not be accepted again until state 4 finishes. Block instructions also alter this cycle by repeating state 3 and/or state 4 a counted number of times.
 44 | ## Address Definitions
 45 | ### Overview
 46 | Processor addresses start at the beginning of memory. 128K Words Reserved for processor internals.  
 47 | Peripherals should be mapped following the processor addresses.  
 48 | RAM is mapped after the peripherals and before ROM.  
 49 | ROM is expected at the highest part of memory.  
 50 | ### Processor Addresses
 51 | <table>
 52 | <tr>
 53 | <td>Addr</td><td>Width</td><td>Name</td><td>Read</td><td>Write</td><td>DMA Rd</td><td>DMA Wr</td><td>NOTES<br>1, 2, 3</td>
 54 | </tr>
 55 | <tr>
 56 | <td>0000</td><td>64</td><td>AP</td><td>AP</td><td>Jump</td><td>AP</td><td>AP</td><td>4</td>
 57 | </tr>
 58 | <tr>
 59 | <td>0001</td><td>64</td><td>APX</td><td>(AP++)</td><td>Call</td><td>0</td><td>no effect</td><td>5</td>
 60 | </tr>
 61 | <tr>
 62 | <td>0002</td><td>64</td><td>RND</td><td>Random</td><td>Rel Jump</td><td>RND</td><td>no effect</td><td>6</td>
 63 | </tr>
 64 | <tr>
 65 | <td>0003</td><td>64</td><td>CTR</td><td>Count</td><td> Rel Call</td><td>CTR</td><td>no effect</td><td>7</td>
 66 | </tr>
 67 | <tr>
 68 | <td>0004</td><td>64</td><td>IAR</td><td>Int Addr Reg</td><td>Int Addr</td><td>IAR</td><td>IAR</td><td>8, 9</td>
 69 | </tr>
 70 | <tr>
 71 | <td>0005</td><td>64</td><td>ICR</td><td>Int Ctrl Reg</td><td>Int Ctrl Reg</td><td>ICR</td><td>ICR</td><td>10</td>
 72 | </tr>
 73 | <tr>
 74 | <td>0006</td><td>64</td><td>DMACR</td><td>DMA Ctrl Reg</td><td>DMA Ctrl Reg</td><td>DMACR</td><td>DMACR</td><td>11</td>
 75 | </tr>
 76 | <tr>
 77 | <td>0007</td><td>64</td><td>BLKCNT</td><td> BLKCNT Reg</td><td>BLKCNT Reg</td><td>BLKCNT</td><td>BLKCNT</td><td>12</td>
 78 | </tr>
 79 | <tr>
 80 | <td>0008</td><td>64</td><td>BLKCTRL</td><td>BLKCTRL Reg</td><td> BLKCTRL Reg</td><td>BLKCTRL</td><td>BLKCTRL</td><td>13</td>
 81 | </tr>
 82 | <tr>
 83 | <td>0009</td><td>64</td><td>ACC</td><td>ACC</td><td>ACC</td><td>ACC</td><td>ACC</td><td>14</td>
 84 | </tr>
 85 | <tr>
 86 | <td>000A</td><td>64</td><td>ACCI</td><td>(ACC)</td><td>(ACC)</td><td>ACC</td><td>no effect</td><td>15</td>
 87 | </tr>
 88 | <tr>
 89 | <td>000B</td><td>64</td><td>AND</td><td>CY</td><td>TMP AND ACC=>ACC</td><td>CY</td><td>CY</td><td>16, 17</td>
 90 | </tr>
 91 | <tr>
 92 | <td>000C</td><td>64</td><td>OR</td><td>ZF</td><td>TMP OR ACC=>ACC</td><td>ZF</td><td>ZF</td><td>16, 18</td>
 93 | </tr>
 94 | <tr>
 95 | <td>000D</td><td>64</td><td>XOR</td><td>BITCNT</td><td>TMP XOR ACC=>ACC</td><td>BITCNT</td><td>BITCNT</td><td>16, 19</td>
 96 | </tr>
 97 | <tr>
 98 | <td>000E</td><td>64</td><td>ADD</td><td>BCRZ</td><td>TMP + ACC=>ACC</td><td>BCRZ</td><td>BCRZ</td><td>20</td>
 99 | </tr>
100 | <tr>
101 | <td>000F</td><td>64</td><td>ADC</td><td>BCRO</td><td>TMP + ACC + C=>ACC</td><td>BCRO</td><td>BCRO</td><td>21</td>
102 | </tr>
103 | <tr>
104 | <td>0010</td><td>64</td><td>SUB</td><td>BCLZ</td><td>ACC - TMP=>ACC</td><td>BCLZ</td><td>BCLZ</td><td>22</td>
105 | </tr>
106 | <tr>
107 | <td>0011</td><td>64</td><td>SBB</td><td>BCLO</td><td>ACC - TMP - C=>ACC</td><td>BCLO</td><td>BCLO</td><td>23</td>
108 | </tr>
109 | <tr>
110 | <td>0012</td><td>64</td><td>CMP</td><td>all 1s</td><td>adjust ZF and CY</td><td>all 1s</td><td>no effect</td><td>24</td>
111 | </tr>
112 | <tr>
113 | <td>0013</td><td>6</td><td>SWAP</td><td>TBD</td><td>ACC modified</td><td>TBD</td><td>no effect</td><td>25</td>
114 | </tr>
115 | <tr>
116 | <td>0014</td><td>64</td><td>ILVI</td><td>High ILVI</td><td>Bit interleave</td><td>High ILVI</td><td>load only</td><td>26</td>
117 | </tr>
118 | <tr>
119 | <td>0015</td><td>64</td><td>DLVI</td><td>High DLVI</td><td>Bit deinterleave</td><td>High DLVI</td><td>load only</td><td>27</td>
120 | </tr>
121 | <tr>
122 | <td>0016</td><td>64</td><td>ILVP</td><td>High ILVP</td><td>Pair interleave</td><td>High ILVP</td><td>load only</td><td>28</td>
123 | </tr>
124 | <tr>
125 | <td>0017</td><td>64</td><td>DLVP</td><td>High DLVP</td><td>Pair deinterleave</td><td>High DLVP</td><td>load only</td><td>29</td>
126 | </tr>
127 | <tr>
128 | <td>0018</td><td>64</td><td>ILVN</td><td>High ILVN</td><td>Nibble interleave</td><td>High ILVN</td><td>load only</td><td>30</td>
129 | </tr>
130 | <tr>
131 | <td>0019</td><td>64</td><td>DLVN</td><td>High DLVN</td><td>Nibble deinterleave</td><td>High DLVN</td><td>load only</td><td>31</td>
132 | </tr>
133 | <tr>
134 | <td>001A</td><td>64</td><td>ILVB</td><td>High ILVB</td><td>Byte interleave</td><td>High ILVB</td><td>load only</td><td>32</td>
135 | </tr>
136 | <tr>
137 | <td>001B</td><td>64</td><td>DLVB</td><td>High DLVB</td><td>Byte deinterleave</td><td>High DLVB</td><td>load only</td><td>33</td>
138 | </tr>
139 | <tr>
140 | <td>001C</td><td>64</td><td>ILVQ</td><td>High ILVQ</td><td>Quarter interleave</td><td>High ILVQ</td><td>load only</td><td>34</td>
141 | </tr>
142 | <tr>
143 | <td>001D</td><td>64</td><td>DLVQ</td><td>High DLVQ</td><td>Quarter deinterleave</td><td>High DLVQ</td><td>load only</td><td>35</td>
144 | </tr>
145 | <tr>
146 | <td>001E</td><td>64</td><td>ILVH</td><td>High ILVH</td><td>Half interleave</td><td>High ILVH</td><td>load only</td><td>36</td>
147 | </tr>
148 | <tr>
149 | <td>001F</td><td>64</td><td>DLVH</td><td>High DLVH</td><td>Half deinterleave</td><td>High DLVH</td><td>load only</td><td>37</td>
150 | </tr>
151 | <tr>
152 | <td>0020</td><td>64</td><td>CV</td><td>CV/NC Value</td><td>CV Value</td><td> CV Value</td><td>CV Value</td><td>38</td>
153 | </tr>
154 | <tr>
155 | <td>0021</td><td>64</td><td>NC</td><td>CV/NC Value</td><td>NC Value</td><td>NC Value</td><td>NC Value</td><td>39</td>
156 | </tr>
157 | <tr>
158 | <td>0022</td><td>64</td><td>ZV</td><td>ZV/NZ Value</td><td>ZV Value</td><td> ZV Value</td><td>ZV Value</td><td>40</td>
159 | </tr>
160 | <tr>
161 | <td>0023</td><td>64</td><td>NZ</td><td>ZV/NZ Value</td><td>NZ Value</td><td>NZ Value</td><td>NZ Value</td><td>41</td>
162 | </tr>
163 | <tr>
164 | <td>0024</td><td>64</td><td>PO</td><td>PO/PE Value</td><td>PO Value</td><td> PO Value</td><td>PO Value</td><td>42</td>
165 | </tr>
166 | <tr>
167 | <td>0025</td><td>64</td><td>PE</td><td>PO/PE Value</td><td>PE Value</td><td>PE Value</td><td>PE Value</td><td>43</td>
168 | </tr>
169 | <tr>
170 | <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>44</td>
171 | </tr>
172 | <tr>
173 | <td>0030</td><td>64</td><td>WReg0</td><td>WReg0</td><td> WReg0</td><td> WReg0</td><td>WReg0</td><td>45</td>
174 | </tr>
175 | <tr>
176 | <td>0031</td><td>64</td><td>WReg1</td><td>WReg1</td><td> WReg1</td><td> WReg1</td><td>WReg1</td><td>45</td>
177 | </tr>
178 | <tr>
179 | <td>0032</td><td>64</td><td>WReg2</td><td>WReg2</td><td> WReg2</td><td> WReg2</td><td>WReg2</td><td>45</td>
180 | </tr>
181 | <tr>
182 | <td>0033</td><td>64</td><td>WReg3</td><td>WReg3</td><td> WReg3</td><td> WReg3</td><td>WReg3</td><td>45</td>
183 | </tr>
184 | <tr>
185 | <td>0034</td><td>64</td><td>WReg4</td><td>WReg4</td><td> WReg4</td><td> WReg4</td><td>WReg4</td><td>45</td>
186 | </tr>
187 | <tr>
188 | <td>0035</td><td>64</td><td>WReg5</td><td>WReg5</td><td> WReg5</td><td> WReg5</td><td>WReg5</td><td>45</td>
189 | </tr>
190 | <tr>
191 | <td>0036</td><td>64</td><td>WReg6</td><td>WReg6</td><td> WReg6</td><td> WReg6</td><td>WReg6</td><td>45</td>
192 | </tr>
193 | <tr>
194 | <td>0037</td><td>64</td><td>WReg7</td><td>WReg7</td><td> WReg7</td><td> WReg7</td><td>WReg7</td><td>45</td>
195 | </tr>
196 | <tr>
197 | <td>0038</td><td>64</td><td>WReg8</td><td>WReg8</td><td> WReg8</td><td> WReg8</td><td>WReg8</td><td>45</td>
198 | </tr>
199 | <tr>
200 | <td>0039</td><td>64</td><td>WReg9</td><td>WReg9</td><td> WReg9</td><td> WReg9</td><td>WReg9</td><td>45</td>
201 | </tr>
202 | <tr>
203 | <td>003A</td><td>64</td><td>WRegA</td><td>WRegA</td><td> WRegA</td><td> WRegA</td><td>WRegA</td><td>45</td>
204 | </tr>
205 | <tr>
206 | <td>003B</td><td>64</td><td>WRegB</td><td>WRegB</td><td> WRegB</td><td> WRegB</td><td>WRegB</td><td>45</td>
207 | </tr>
208 | <tr>
209 | <td>003C</td><td>64</td><td>WRegC</td><td>WRegC</td><td> WRegC</td><td> WRegC</td><td>WRegC</td><td>45</td>
210 | </tr>
211 | <tr>
212 | <td>003D</td><td>64</td><td>WRegD</td><td>WRegD</td><td> WRegD</td><td> WRegD</td><td>WRegD</td><td>45</td>
213 | </tr>
214 | <tr>
215 | <td>003E</td><td>64</td><td>WRegE</td><td>WRegE</td><td> WRegE</td><td> WRegE</td><td>WRegE</td><td>45</td>
216 | </tr>
217 | <tr>
218 | <td>003F</td><td>64</td><td>WRegF</td><td>WRegF</td><td> WRegF</td><td> WRegF</td><td>WRegF</td><td>45</td>
219 | </tr>
220 | <tr>
221 | <td>0040<br>to<br>007F</td><td>64</td><td>BRLS</td><td> </td><td> </td><td> </td><td> </td><td>46</td>
222 | </tr>
223 | <tr>
224 | <td>0080</td><td>64</td><td>Cnt1</td><td>Cnt1</td><td>Cnt1</td><td>Cnt1</td><td>Cnt1</td><td>47</td>
225 | </tr>
226 | <tr>
227 | <td>0081</td><td>64</td><td>Lim1</td><td>Lim1</td><td>Lim1</td><td>Lim1</td><td>Lim1</td><td>48</td>
228 | </tr>
229 | <tr>
230 | <td>0082</td><td>64</td><td>Und1</td><td>Und1<br>or<br>Ovr1</td><td>Und1</td><td>Und1</td><td>Und1</td><td>49</td>
231 | </tr>
232 | <tr>
233 | <td>0083</td><td>64</td><td>Ovr1</td><td>Und1<br>or<br>Ovr1</td><td>Ovr1</td><td>Ovr1</td><td>Ovr1</td><td>50</td>
234 | </tr>
235 | <tr>
236 | <td>0084</td><td>64</td><td>Cnt2</td><td>Cnt2</td><td>Cnt2</td><td>Cnt2</td><td>Cnt2</td><td>51</td>
237 | </tr>
238 | <tr>
239 | <td>0085</td><td>64</td><td>Lim2</td><td>Lim2</td><td>Lim2</td><td>Lim2</td><td>Lim2</td><td>52</td>
240 | </tr>
241 | <tr>
242 | <td>0086</td><td>64</td><td>Und2</td><td>Und2<br>or<br>Ovr2</td><td>Und2</td><td>Und2</td><td>Und2</td><td>53</td>
243 | </tr>
244 | <tr>
245 | <td>0087</td><td>64</td><td>Ovr2</td><td>Und2<br>or<br>Ovr2</td><td>Ovr2</td><td>Ovr2</td><td>Ovr2</td><td>54</td>
246 | </tr>
247 | <tr>
248 | <td>0088</td><td>64</td><td>Cnt3</td><td>Cnt3</td><td>Cnt3</td><td>Cnt3</td><td>Cnt3</td><td>51</td>
249 | </tr>
250 | <tr>
251 | <td>0089</td><td>64</td><td>Lim3</td><td>Lim3</td><td>Lim3</td><td>Lim3</td><td>Lim3</td><td>52</td>
252 | </tr>
253 | <tr>
254 | <td>008A</td><td>64</td><td>Und3</td><td>Und3<br>or<br>Ovr3</td><td>Und3</td><td>Und3</td><td>Und3</td><td>53</td>
255 | </tr>
256 | <tr>
257 | <td>008B</td><td>64</td><td>Ovr3</td><td>Und3<br>or<br>Ovr3</td><td>Ovr3</td><td>Ovr3</td><td>Ovr3</td><td>54</td>
258 | </tr>
259 | <tr>
260 | <td>008C</td><td>64</td><td>Cnt4</td><td>Cnt4</td><td>Cnt4</td><td>Cnt4</td><td>Cnt4</td><td>51</td>
261 | </tr>
262 | <tr>
263 | <td>008D</td><td>64</td><td>Lim4</td><td>Lim4</td><td>Lim4</td><td>Lim4</td><td>Lim4</td><td>52</td>
264 | </tr>
265 | <tr>
266 | <td>008E</td><td>64</td><td>Und4</td><td>Und4<br>or<br>Ovr4</td><td>Und4</td><td>Und4</td><td>Und4</td><td>53</td>
267 | </tr>
268 | <tr>
269 | <td>008F</td><td>64</td><td>Ovr4</td><td>Und4<br>or<br>Ovr4</td><td>Ovr4</td><td>Ovr4</td><td>Ovr4</td><td>54</td>
270 | </tr>
271 | <tr>
272 | <td>0090</td><td>64</td><td>Cnt5</td><td>Cnt5</td><td>Cnt5</td><td>Cnt5</td><td>Cnt5</td><td>51</td>
273 | </tr>
274 | <tr>
275 | <td>0091</td><td>64</td><td>Lim5</td><td>Lim5</td><td>Lim5</td><td>Lim5</td><td>Lim5</td><td>52</td>
276 | </tr>
277 | <tr>
278 | <td>0092</td><td>64</td><td>Und5</td><td>Und5<br>or<br>Ovr5</td><td>Und5</td><td>Und5</td><td>Und5</td><td>53</td>
279 | </tr>
280 | <tr>
281 | <td>0093</td><td>64</td><td>Ovr5</td><td>Und5<br>or<br>Ovr5</td><td>Ovr5</td><td>Ovr5</td><td>Ovr5</td><td>54</td>
282 | </tr>
283 | <tr>
284 | <td>0094</td><td>64</td><td>Cnt6</td><td>Cnt6</td><td>Cnt6</td><td>Cnt6</td><td>Cnt6</td><td>51</td>
285 | </tr>
286 | <tr>
287 | <td>0095</td><td>64</td><td>Lim6</td><td>Lim6</td><td>Lim6</td><td>Lim6</td><td>Lim6</td><td>52</td>
288 | </tr>
289 | <tr>
290 | <td>0096</td><td>64</td><td>Und6</td><td>Und6<br>or<br>Ovr6</td><td>Und6</td><td>Und6</td><td>Und6</td><td>53</td>
291 | </tr>
292 | <tr>
293 | <td>0097</td><td>64</td><td>Ovr6</td><td>Und6<br>or<br>Ovr6</td><td>Ovr6</td><td>Ovr6</td><td>Ovr6</td><td>54</td>
294 | </tr>
295 | <tr>
296 | <td>0098</td><td>64</td><td>Cnt7</td><td>Cnt7</td><td>Cnt7</td><td>Cnt7</td><td>Cnt7</td><td>51</td>
297 | </tr>
298 | <tr>
299 | <td>0099</td><td>64</td><td>Lim7</td><td>Lim7</td><td>Lim7</td><td>Lim7</td><td>Lim7</td><td>52</td>
300 | </tr>
301 | <tr>
302 | <td>009A</td><td>64</td><td>Und7</td><td>Und7<br>or<br>Ovr7</td><td>Und7</td><td>Und7</td><td>Und7</td><td>53</td>
303 | </tr>
304 | <tr>
305 | <td>009B</td><td>64</td><td>Ovr7</td><td>Und7<br>or<br>Ovr7</td><td>Ovr7</td><td>Ovr7</td><td>Ovr7</td><td>54</td>
306 | </tr>
307 | <tr>
308 | <td>009C</td><td>64</td><td>Cnt8</td><td>Cnt8</td><td>Cnt8</td><td>Cnt8</td><td>Cnt8</td><td>51</td>
309 | </tr>
310 | <tr>
311 | <td>009D</td><td>64</td><td>Lim8</td><td>Lim8</td><td>Lim8</td><td>Lim8</td><td>Lim8</td><td>52</td>
312 | </tr>
313 | <tr>
314 | <td>009E</td><td>64</td><td>Und8</td><td>Und8<br>or<br>Ovr8</td><td>Und8</td><td>Und8</td><td>Und8</td><td>53</td>
315 | </tr>
316 | <tr>
317 | <td>009F</td><td>64</td><td>Ovr8</td><td>Und8<br>or<br>Ovr8</td><td>Ovr8</td><td>Ovr8</td><td>Ovr8</td><td>54</td>
318 | </tr>
319 | <tr>
320 | <td>00Ax</td><td>64</td><td>RegAx</td><td>RegAx</td><td>RegAx</td><td>RegAx</td><td>RegAx</td><td>55, 56</td>
321 | </tr>
322 | <tr>
323 | <td>00Bx</td><td>64</td><td>RegBx</td><td>(RegAx)</td><td>(RegAx)</td><td>RegAx</td><td>no effect</td><td>55, 57</td>
324 | </tr>
325 | <tr>
326 | <td>00Cx</td><td>64</td><td>RegCx</td><td>(RegAx--)</td><td>(++RegAx)</td><td>RegAx</td><td>no effect</td><td>55, 58</td>
327 | </tr>
328 | <tr>
329 | <td>00Dx</td><td>64</td><td>RegDx</td><td>(--RegAx)</td><td>(RegAx++)</td><td>RegAx</td><td>no effect</td><td>55, 59</td>
330 | </tr>
331 | <tr>
332 | <td>00Ex</td><td>64</td><td>RegEx</td><td>(RegAx++)</td><td>(--RegAx)</td><td>RegAx</td><td>no effect</td><td>55, 60</td>
333 | </tr>
334 | <tr>
335 | <td>00Fx</td><td>64</td><td>RegFx</td><td>(++RegAx)</td><td> (RegAx--)</td><td> RegAx</td><td>no effect</td><td>55, 61</td>
336 | </tr>
337 | <tr>
338 | <td>0100</td><td>64</td><td>CHOP</td><td> CHOP</td><td>CHOP</td><td>CHOP</td><td> CHOP</td><td>62</td>
339 | </tr>
340 | <tr>
341 | <td>0101</td><td>64</td><td>CHOPI</td><td>(CHOP)</td><td>(CHOP)</td><td>0</td><td>no effect</td><td>63</td>
342 | </tr>
343 | <tr>
344 | <td>0102<br>0103</td><td>32</td><td>CHOPLH<br>CHOPHH</td><td>CHOP(31 downto 0)<br>CHOP(63 downto 32)</td><td>CHOP(31 downto 0)<br>CHOP(63 downto 32)</td><td>0</td><td>no effect</td><td>64</td>
345 | </tr>
346 | <tr>
347 | <td>0104<br>0105<br>0106<br>0107</td><td>16</td><td>CHOPQ0<br>CHOPQ1<br>CHOPQ2<br>CHOPQ3</td><td>CHOP(15 downto 0)<br>CHOP(31 downto 16)<br>CHOP(47 downto 32)<br>CHOP(63 downto 48)</td><td>CHOP(15 downto 0)<br>CHOP(31 downto 16)<br>CHOP(47 downto 32)<br>CHOP(63 downto 48)</td><td>0</td><td>no effect</td><td>65</td>
348 | </tr>
349 | <tr>
350 | <td>0108<br>to<br>010F</td><td>8</td><td>CHOPB0<br>to<br>CHOPB7</td><td>CHOP(7 downto 0)<br>to<br>CHOP(63 downto 56)</td><td>CHOP(7 downto 0)<br>to<br>CHOP(63 downto 56)</td><td>0</td><td>no effect</td><td>66</td>
351 | </tr>
352 | <tr>
353 | <td>0110<br>to<br>011F</td><td>4</td><td>CHOPN0<br>to<br>CHOPN15</td><td>CHOP(3 downto 0)<br>to<br>CHOP(63 downto 60)</td><td>CHOP(3 downto 0)<br>to<br>CHOP(63 downto 60)</td><td>0</td><td>no effect</td><td>67</td>
354 | </tr>
355 | <tr>
356 | <td>0120<br>to<br>013F</td><td>2</td><td>CHOPP0<br>to<br>CHOPP31</td><td>CHOP(1 downto 0)<br>to<br>CHOP(63 downto 62)</td><td>CHOP(1 downto 0)<br>to<br>CHOP(63 downto 62)</td><td>0</td><td>no effect</td><td>68</td>
357 | </tr>
358 | <tr>
359 | <td>0140<br>to<br>017F</td><td>1</td><td>CHOPB0<br>to<br>CHOPB63</td><td>CHOP(0)<br>to<br>CHOP(63)</td><td>CHOP(0)<br>to<br>CHOP(63)</td><td>0</td><td>no effect</td><td>69</td>
360 | </tr>
361 | <tr>
362 | <td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td> </td><td>44</td>
363 | </tr>
364 | <tr>
365 | <td>10000<br>to<br>1FFFF</td><td>64</td><td>CONST</td><td>0000<br>to<br>FFFF</td><td>no effect</td><td>0000<br>to<br>FFFF</td><td>no effect</td><td>70</td>
366 | </tr>
367 | </table>
368 | 
369 | NOTES:
370 | 1. DMA Read and Write must be different to avoid triggering the TTA effects.
371 | 2. Only the 4 lowest hex digits of address are shown. The high 12 digits are all 0's.
372 | 3. Addresses not shown (skipped) are undefined and should Read as 0. Write should have no effect.
373 | 4. Argument Pointer is the same as a Program Counter. Reset sets all bits.
374 | 5. Reading APX reads from memory pointed to by AP and increments AP. Writing APX pushes AP onto the stack and loads AP (Call).
375 |   - Reading APX is the only instruction which uses the third argument as immediate data.
376 | 6. RND is an LFSR (Read only) which shifts on each clock. Writing adds to AP (Relative Jump).
377 | 7. CTR is an up-counter incremented on every clock. Writing CTR pushes AP onto the stack and adds to AP (Relative Call).
378 | 8. Interrupt Address Register holds the address of the ISR (Interrupt Service Routine) called during Interrupt Acknowledge.
379 | 9. Only one interrupt is implemented in processor. External interrupt controller may expand this.
380 | 10. Interrupt Control Register is a work in progress. Enable/Disable Bit is a minimum.
381 | 11. DMA Control defaults to enabled and can be used for debugging, allowing a single processor cycle then reading all registers.
382 | 12. BLKCNT is a counter with the number of times to repeat an instruction, counts after Write cycle when enabled.
383 | 13. BLKCTRL controls block operation. When loaded, the next instruction is a block instruction.
384 |   - Bit 0 - Setting this bit starts a Block Instruction
385 |   - Bit 1 - 0 = decrement Block Counter, 1 = increment Block Counter
386 |   - Bit 2 - 1 = increment SAR
387 |   - Bit 3 - 1 = decrement SAR, when Bit 2 and Bit 3 are the same SAR is unchanged
388 |   - Bit 4 - 1 = increment DAR
389 |   - Bit 5 - 1 = decrement DAR, when Bit 4 and Bit 5 sre the same DAR is unchanged
390 |   - Bit 6 - 1 = read only once, write using same data. Bits 2 and 3 are ignored. Typically used for block fill.
391 | 14. Accumulator is affected by writes to this and the following 7 addresses.
392 | 15. Accumulator Indirect uses ACC as a pointer to memory.
393 | 16. Write clears Carry Flag. Zero Flag is set if all ACC bits are zero, cleared otherwise.
394 | 17. Write to AND causes data to be ANDed with ACC. Reading returns CY (Carry Flag).
395 | 18. Write to OR causes data to be ORed with ACC. Reading returns ZF (Zero Flag).
396 | 19. Write to XOR causes data to be XORed with ACC. Reading returns BITCNT (Count of set bits in ACC) from 0 to 64.
397 | 20. Write to ADD adds data to ACC. CY and ZF are adjusted appropriately. BCRZ is bit count from right (LSB) to first zero.
398 | 21. Write to ADC adds data and CY to ACC. CY and ZF are adjusted. BCRO is bit count from right to first 1 (0 to 64).
399 | 22. Write to SUB subtracts data from ACC. CY and ZF are adjusted. BCLZ is bit count from left (MSB) to first zero.
400 | 23. Write to SBB subtracts data and CY from ACC. CY and ZF are adjusted. BCLZ is bit count from left to first 1 bit.
401 | 24. CMP is compare. ZF and CY are adjusted as if value was subtracted from ACC. ACC is unchanged.
402 | 25. Swaps parts of ACC. TBD means To Be Determined.
403 |   - Bit 0 swaps Bits within Pairs
404 |   - Bit 1 swaps Pairs within Nibbles
405 |   - Bit 2 swaps Nibbles within Bytes
406 |   - Bit 3 swaps Bytes within Quarter Words
407 |   - Bit 4 swaps Quarter Words within Half Words
408 |   - Bit 5 swaps Half Words within ACC
409 | 26. Individual Bits are interleaved with Bits of ACC. Low order bits are in ACC. High order bits are available here.
410 | 27. Individual Bits are deinterleaved with Bits of ACC. Odd bits in ACC. Even bits are available here.
411 | 28. Bit Pairs are interleaved with Bits of ACC. Low order Pairs are in ACC. High order Pairs are available here.
412 | 29. Bit Pairs are deinterleaved with Bits of ACC. Odd Pairs in ACC. Even Pairs are available here.
413 | 30. Nibbles are interleaved with ACC. Low order Nibbles are in ACC. High order Nibbles are available here.
414 | 31. Nibbles are deinterleaved with ACC. Odd Nibbles in ACC. Even Nibbles are available here.
415 | 32. Bytes are interleaved with ACC. Low order Bytes are in ACC. High order Bytes are available here.
416 | 33. Byte are deinterleaved with ACC. Odd Bytes in ACC. Even Bytes are available here.
417 | 34. Quarter Words are interleaved with ACC. Low order Quarters are in ACC. High order Quarters are available here.
418 | 35. Quarter Words are deinterleaved with ACC. Odd Quarters in ACC. Even Quarters are available here.
419 | 36. Half Words are interleaved with ACC. Low Halves are in ACC. High Halves are available here.
420 | 37. Half Words are deinterleaved with ACC. Odd Halves in ACC. Even Halves are available here.
421 | 38. Write to CV sets the value returned when reading either CV or NC if CY is set when reading.
422 | 39. Write to NC sets the value returned when reading either CV or NC if CY is clear when reading.
423 | 40. Write to ZV sets the value returned when reading either ZV or NZ if ZF is set when reading.
424 | 41. Write to NZ sets the value returned when reading either ZV or NZ if ZF is clear when reading.
425 | 42. Write to PO sets the value returned when reading either PO or PE if BITCNT(0) is set when reading. Parity odd.
426 | 43. Write to PE sets the value returned when reading either PO or PE if BITCNT(0) is clear when reading. Parity even.
427 | 44. Space for more stuff.
428 | 45. Working Registers. These 16 registers do nothing special. They are just like RAM except they never generate wait states.
429 | 46. Barrel Rotate. There is only one register here. All addresses in this range read and write to it rotated relative to their addresses. Write to 30 and read from 31 rotates one bit to the right. Write to 38 and read from 30 rotates 8 bits to the left.
430 | 47. Unsigned counter which counts down when Und1 is read and counts up when Ovr1 is read.
431 | 48. Unsigned Limit register against which Cnt1 is compared.
432 | 49. Unsigned register which returns Und1 if Cnt1 =< Lim1 else returns Ovr1. Reading decrements Cnt1. DMA Rd does not affect Cnt1.
433 | 50. Unsigned register which returns Ovr1 if Cnt1 >= Lim1 else returns Und1. Reading increments Cnt1. DMA Rd does not affect Cnt1.
434 | 51. Unsigned counter similar to Cnt1.
435 | 52. Unsigned Limit register similar to Lim1.
436 | 53. Unsigned register similar to Und1.
437 | 54. Unsigned register similar to Ovr1.
438 | 55. x here means all values from 0 to F.
439 | 56. There are sixteen registers.
440 | 57. These addresses use the Ax registers as memory pointers for read and write.
441 | 58. These addresses use the Ax registers as stack pointers. Postdecremented read, Preincremented write.
442 | 59. These addresses use the Ax registers as stack pointers. Predecremented read, Postincremented write.
443 | 60. These addresses use the Ax registers as stack pointers. Postincremented read, Predecremented write.
444 | 61. These addresses use the Ax registers as stack pointers. Preincremented read, Postdecremented write.
445 |   - 00FF is the system stack used for Call and Relative Call when the AP gets pushed.
446 | 62. There is only one register in the next 0x80 addresses. It gets CHOPped into pieces and put back together.
447 | 63. CHOP may be used as a memory pointer by using this address.
448 | 64. CHOP Low Half and Chop High Half are read and written here. They are in the low bits of a read. The high bits of the read are all zeroes. Only the low bits of a write are used. The high bits of the write are irrelevant and ignored.
449 | 65. CHOP in 4 16-bit quarters. Upper bits are zeroes for read and don't care for write.
450 | 66. CHOP 8 Bytes.
451 | 67. CHOP 16 Nibbles (4 Bits each).
452 | 68. CHOP Pairs of Bits. There are 32 of them.
453 | 69. CHOP Bits, all 64 of them individually addressable.
454 | 70. Small constant ROM. There is not actually a ROM here. With a little bit of hardware we can detect reads in this range and return the low 16 bits of address, eliminating the need to store small constants in the 0000-FFFF range in memory or to use them as immediate data in APX read instruction. With the huge memory space we have, I don't consider this wasteful.
455 | 


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/TopCtrl.vhd:
--------------------------------------------------------------------------------
  1 | -- TopCtrl.vhdl
  2 | -- Version 2.0
  3 | -- Overall Machine State Controller for NISC
  4 | -- Word Size = Addr Size for this model
  5 | -- Interrupt Control
  6 | -- DMA Control
  7 | -- 4 cycle and block multi-cycle
  8 | -- Fetch Src Addr
  9 | -- Fetch Dst Addr
 10 | -- Read Src
 11 | -- Write Dest
 12 | 
 13 | library IEEE;
 14 | use IEEE.STD_LOGIC_1164.ALL;
 15 | use IEEE.STD_LOGIC_ARITH.ALL;
 16 | use IEEE.STD_LOGIC_UNSIGNED.ALL;
 17 | 
 18 | entity TopCtrl is
 19 |     Port ( CLK       : in std_logic;      -- System Clock
 20 |            Reset_In  : in std_logic;      -- Reset Signal
 21 |            Ready     : in std_logic;      -- Ready Signal
 22 |            Rept      : in std_logic;      -- Block Repeat (repeats Read and Write)
 23 |            UseFSrc   : in std_logic;      -- Use First Source (Reads once and repeats Write)
 24 |            BUSRQ     : in std_logic;      -- DMA Bus Request
 25 |            INTRQ     : in std_logic;      -- Interrupt Request
 26 |            DMA_EN    : in std_logic;      -- DMA Enabled Status
 27 |            INT_EN    : in std_logic;      -- Interrupt Enabled Status
 28 |            Reset_Out : out std_logic;     -- System Reset
 29 |            BUSACK    : out std_logic;     -- Bus Grant Acknowledged
 30 |            INTACK    : out std_logic;     -- Interrupt Acknowledged
 31 |            Fetch     : out std_logic;     -- Instruction Fetch Cycle
 32 |            SorD      : out std_logic;     -- Fetch SrcAddr or DstAddr
 33 |            Mem_RD    : out std_logic;     -- Memory Read Cycle
 34 |            Mem_WR    : out std_logic);    -- Memory Write Cycle
 35 | end TopCtrl;
 36 | 
 37 | architecture Behavioral of TopCtrl is
 38 | 
 39 | type CycleCtrl_type is (State_Reset, State_BusGrant, State_IntStart, State_IntFinish, State_FetchSA, State_FetchDA, State_SourceRd, State_DestWr);
 40 | 
 41 | signal TopState : CycleCtrl_type := State_Reset;
 42 | 
 43 | signal reset_i   : std_logic;
 44 | signal busack_p  : std_logic;
 45 | signal intack_p  : std_logic;
 46 | signal fetch_p   : std_logic;
 47 | signal Mem_RD_p  : std_logic;
 48 | signal Mem_WR_p  : std_logic;
 49 | signal ready_i   : std_logic;
 50 | signal DMA_EN_i  : std_logic;
 51 | signal INT_EN_i  : std_logic;
 52 | signal SorD_i    : std_logic;
 53 | 
 54 | begin
 55 | 
 56 | TopCtrl_State : process (CLK, Reset_In) is
 57 | 
 58 | begin
 59 |    if rising_edge(CLK) then
 60 |       if Reset_In='1' then
 61 |          TopState <= State_Reset;
 62 |       else
 63 |          case TopState is
 64 | -- Reset
 65 |             when State_Reset =>
 66 |                if (Reset_In = '1') then
 67 |                   TopState <= State_Reset;
 68 |                elsif (BUSRQ = '1' AND DMA_EN_i = '1') then
 69 |                   TopState <= State_BusGrant;
 70 |                elsif (INTRQ = '1' AND INT_EN_i = '1') then
 71 |                   TopState <= State_IntStart;
 72 |                else
 73 |                   TopState <= State_FetchSA;
 74 |                end if;
 75 | -- DMA (External)
 76 |             when State_BusGrant =>
 77 |                if (BUSRQ = '1') then
 78 |                         TopState <= State_BusGrant;   -- continue bus grant
 79 |                elsif (BUSRQ = '0') then
 80 |                   if (INTRQ = '1' AND INT_EN_i = '1') then
 81 |                       TopState <= State_IntStart;  -- service interrupt
 82 |                   else
 83 |                       TopState <= State_FetchSA;  -- resume processing
 84 |                   end if; 
 85 |                end if;
 86 | -- INT
 87 |             when State_IntStart =>                -- PC --> Stack
 88 |                if (ready_i = '0') then
 89 |                   TopState <= State_IntStart;
 90 |                elsif (ready_i = '1') then
 91 |                   TopState <= State_IntFinish;
 92 |                end if;
 93 |                
 94 |             when State_IntFinish =>               -- ISR Addr --> PC
 95 |                if (ready_i = '0') then
 96 |                   TopState <= State_IntFinish;
 97 |                elsif (ready_i = '1') then
 98 |                   if (BUSRQ = '1' AND DMA_EN_i = '1') then
 99 |                      TopState <= State_BusGrant;  -- bus grant
100 |                   else
101 |                       TopState <= State_FetchSA;  -- resume processing
102 |                   end if;
103 |                end if;
104 | -- Source Addr Fetch
105 |             when State_FetchSA =>           -- Get Src Addr
106 |                if (ready_i = '0') then
107 |                   TopState <= State_FetchSA;
108 |                elsif (ready_i = '1') then
109 |                   TopState <= State_FetchDA;
110 |                end if;
111 | 
112 | -- Dest Addr Fetch
113 |             when State_FetchDA =>            -- Get Dest Addr
114 |                if (ready_i = '0') then
115 |                   TopState <= State_FetchDA;
116 |                elsif (ready_i = '1') then
117 |                   TopState <= State_SourceRd;
118 |                end if;
119 | -- Source RD
120 |             when State_SourceRd =>             -- Read from Src Addr
121 |                if (ready_i = '0') then
122 |                   TopState <= State_SourceRd;
123 |                elsif (ready_i = '1') then
124 |                   TopState <= State_DestWr;
125 |                end if;
126 | -- Dest WR
127 |             when State_DestWr =>                 -- Write to Dest Addr
128 |                if (ready_i = '0') then
129 |                   TopState <= State_DestWr;
130 |                elsif (ready_i = '1') then
131 |                   if (Rept = '1') then         -- Block Mode
132 |                      if (UseFSrc = '1') then       -- Block Fill
133 |                         TopState <= State_DestWr;
134 |                      else
135 |                         TopState <= State_SourceRd;
136 |                      end if;
137 |                   elsif (BUSRQ = '1' AND DMA_EN_i = '1') then
138 |                       TopState <= State_BusGrant;
139 |                   elsif (INTRQ = '1' AND INT_EN_i = '1') then
140 |                       TopState <= State_IntStart;
141 |                   else
142 |                       TopState <= State_FetchSA;
143 |                   end if;
144 |                end if;
145 |             when others =>
146 |                     TopState <= State_Reset;
147 |          end case;
148 |       end if;
149 |    end if;
150 | end process;
151 | 
152 | 
153 | ready_i <= Ready;
154 | DMA_EN_i <= DMA_EN;
155 | INT_EN_i <= INT_EN;
156 | 
157 | -- signal assignment statements for combinatorial outputs
158 | 
159 | reset_i <= '1' when (TopState = State_Reset) else
160 |            '0';
161 | 
162 | busack_p <= '1' when (TopState = State_BusGrant) else
163 |             '0';
164 | 
165 | intack_p <=  '1' when (TopState = State_IntStart) else
166 |              '1' when (TopState = State_IntFinish) else
167 |              '0';
168 | 
169 | fetch_p <= '1' when (TopState = State_FetchSA) or (TopState = State_FetchDA) else
170 |            '0';
171 | 
172 | SorD_i <= '1' when (TopState = State_FetchDA) else
173 |           '0';
174 | 
175 | Mem_RD_p <=  '1' when (TopState = State_SourceRd) else
176 |              '0';
177 | 
178 | Mem_WR_p <= '1' when (TopState = State_DestWr) else
179 |             '1' when (TopState = State_IntStart) else
180 |             '0';
181 | 
182 | Reset_Out <= reset_i;
183 | BUSACK <= busack_p;
184 | INTACK <= intack_p;
185 | Fetch <= fetch_p;
186 | SorD <= SorD_i;
187 | Mem_RD <= Mem_RD_p;
188 | Mem_WR <= Mem_WR_p;
189 | 
190 | end Behavioral;
191 | 


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