├── .gitmodules ├── Hardware ├── OpenICE V1.0b.pdf └── PMOD_SubCard │ ├── 7segment │ ├── README.md │ └── v1.0a │ │ ├── 7segment-cache.lib │ │ ├── 7segment-rescue.dcm │ │ ├── 7segment-rescue.lib │ │ ├── 7segment-sch.pdf │ │ ├── 7segment.kicad_pcb │ │ ├── 7segment.pro │ │ ├── 7segment.sch │ │ ├── 7segment_gerber.zip │ │ ├── fp-info-cache │ │ ├── fp-lib-table │ │ └── sym-lib-table │ ├── DIP-SWICH │ ├── README.md │ └── v1.0a │ │ ├── dip-switch │ │ ├── dip-switch-cache.lib │ │ ├── dip-switch-rescue.dcm │ │ ├── dip-switch-rescue.lib │ │ ├── dip-switch-sch.pdf │ │ ├── dip-switch.kicad_pcb │ │ ├── dip-switch.kicad_pcb-bak │ │ ├── dip-switch.pro │ │ ├── dip-switch.sch │ │ ├── fp-info-cache │ │ ├── fp-lib-table │ │ └── sym-lib-table │ ├── NES │ ├── NES.pdf │ └── NES.png │ ├── VGA │ ├── PMOD_VGA.pdf │ └── openicev2_2.opj │ ├── key-array │ ├── PCB │ │ └── KEY_ARRAY.brd │ └── SCH │ │ └── PMOD_KEY-ARRAY.pdf │ └── key-led │ └── SCH │ └── PMOD_KeyLed.pdf ├── README.md ├── demo ├── Pin_Out │ └── openice.pcf ├── Refence │ ├── .gitignore │ ├── README.md │ └── up5k-demos │ │ ├── README.md │ │ ├── gameboy │ │ ├── .gitignore │ │ ├── boot_rom.dat │ │ ├── boot_rom.v │ │ ├── cartridge.v │ │ ├── data_io.v │ │ ├── flashmem.v │ │ ├── gb.qpf │ │ ├── gb.qsf │ │ ├── gb.v │ │ ├── gb_mist.v │ │ ├── gbc_snd.vhd │ │ ├── iram.v │ │ ├── lcd.v │ │ ├── osd.v │ │ ├── pll.v │ │ ├── readme.md │ │ ├── sigma_delta_dac.v │ │ ├── sprite.v │ │ ├── sprite_sort.v │ │ ├── sprites.v │ │ ├── t80 │ │ │ ├── GBse.vhd │ │ │ ├── T80.vhd │ │ │ ├── T8080se.vhd │ │ │ ├── T80_ALU.vhd │ │ │ ├── T80_MCode.vhd │ │ │ ├── T80_Pack.vhd │ │ │ ├── T80_Reg.vhd │ │ │ ├── T80_RegX.vhd │ │ │ ├── T80a.vhd │ │ │ ├── T80se.vhd │ │ │ ├── T80sed.vhd │ │ │ └── Z80.vhd │ │ ├── timer.v │ │ ├── user_io.v │ │ ├── video.v │ │ ├── vram.v │ │ └── zpram.v │ │ ├── nes │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── MicroCode.v │ │ ├── NES_ice40.v │ │ ├── README.md │ │ ├── README_OLD.md │ │ ├── apu.v │ │ ├── cart_mem.v │ │ ├── compat.v │ │ ├── cpu.v │ │ ├── flashmem.v │ │ ├── generic_ram.v │ │ ├── hq2x.v │ │ ├── image │ │ │ ├── FC手柄信号定义.jpg │ │ │ ├── NES Games.png │ │ │ └── 小霸王FC游戏机.jpg │ │ ├── main.mk │ │ ├── main_mem.v │ │ ├── mmu.v │ │ ├── nes.v │ │ ├── nes_palette_fceux.txt │ │ ├── nes_palette_unsaturatedv6.txt │ │ ├── oam_palette.txt │ │ ├── pll.v │ │ ├── ppu.v │ │ ├── rom │ │ │ ├── games │ │ │ │ ├── 139.nes │ │ │ │ ├── 92.nes │ │ │ │ ├── 93-contra.nes │ │ │ │ ├── Beyondtime.nes │ │ │ │ └── smb.nes │ │ │ ├── nes2bin.py │ │ │ ├── smb.nes │ │ │ └── 游戏说明.txt │ │ ├── scan_double.v │ │ ├── sigma_delta_dac.v │ │ ├── up5k.pcf │ │ ├── up_spram.v │ │ └── video.v │ │ ├── neshdmi │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── Makefile.old │ │ ├── MicroCode.v │ │ ├── NES_ice40.v │ │ ├── README.md │ │ ├── apu.v │ │ ├── cart_mem.v │ │ ├── compat.v │ │ ├── cpu.v │ │ ├── flashmem.v │ │ ├── generic_ram.v │ │ ├── hq2x.v │ │ ├── main.mk │ │ ├── main_mem.v │ │ ├── mmu.v │ │ ├── nes.v │ │ ├── nes_palette_fceux.txt │ │ ├── nes_palette_unsaturatedv6.txt │ │ ├── oam_palette.txt │ │ ├── pll.v │ │ ├── ppu.v │ │ ├── rom │ │ │ └── nes2bin.py │ │ ├── scan_double.v │ │ ├── sigma_delta_dac.v │ │ ├── up5k.pcf │ │ ├── up_spram.v │ │ └── video.v │ │ └── nesmx │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── MicroCode.v │ │ ├── NES_ice40.v │ │ ├── README.md │ │ ├── apu.v │ │ ├── blackicemx.pcf │ │ ├── cart_mem.v │ │ ├── compat.v │ │ ├── cpu.v │ │ ├── flashmem.v │ │ ├── generic_ram.v │ │ ├── hq2x.v │ │ ├── main.mk │ │ ├── main_mem.v │ │ ├── mmu.v │ │ ├── nes.v │ │ ├── nes_palette_fceux.txt │ │ ├── nes_palette_unsaturatedv6.txt │ │ ├── oam_palette.txt │ │ ├── pll.v │ │ ├── ppu.v │ │ ├── rom │ │ └── nes2bin.py │ │ ├── scan_double.v │ │ ├── sdram.v │ │ ├── sigma_delta_dac.v │ │ └── video.v └── verilog │ ├── 00_run_led │ ├── Makefile │ ├── Run_LED.v │ ├── openice.pcf │ ├── run_led.asc │ ├── run_led.bin │ └── run_led.blif │ ├── 01_sb_rgba_blink │ ├── .gitignore │ ├── LICENSE │ ├── Makefile │ ├── blink.pcf │ └── blink.v │ ├── 02_RGB LED │ ├── Makefile │ ├── leds.bin │ └── leds.v │ ├── 03_pll_uart │ ├── make_bin.sh │ ├── openice.pcf │ ├── pll_uart_mirror.asc │ ├── pll_uart_mirror.bin │ ├── pll_uart_mirror.blif │ ├── pll_uart_mirror.v │ ├── uart_baud_tick_gen.v │ ├── uart_rx.v │ └── uart_tx.v │ ├── 04_Dial Switch │ ├── dial_switch.asc │ ├── dial_switch.bin │ ├── dial_switch.blif │ ├── dial_switch.v │ └── make_bin.sh │ ├── 05_7seg_count │ ├── 7seg_count.asc │ ├── 7seg_count.bin │ ├── 7seg_count.blif │ ├── 7seg_count.rpt │ ├── 7seg_count.v │ ├── Makefile │ └── make_bin.sh │ ├── 06_pwm_rgbled │ ├── Makefile │ ├── pwm.v │ ├── top.asc │ ├── top.bin │ ├── top.blif │ └── top.v │ ├── 07_pwm_led │ ├── Makefile │ ├── pwm.v │ ├── top.asc │ ├── top.bin │ ├── top.blif │ └── top.v │ ├── 08_pll │ ├── Makefile │ ├── README.md │ ├── top.asc │ ├── top.bin │ ├── top.blif │ ├── top.json │ └── top.v │ ├── 09_music │ ├── Makefile │ ├── chip.txt │ ├── music.pcf │ └── music.v │ ├── 10_music2 │ ├── Makefile │ ├── chip.txt │ ├── music.pcf │ └── music.v │ ├── 11_music2a │ ├── Makefile │ ├── chip.txt │ ├── music.pcf │ └── music.v │ ├── 12_music3 │ ├── Makefile │ ├── chip.txt │ ├── divide_by12.v │ ├── music.pcf │ └── music.v │ ├── 13_music4 │ ├── Makefile │ ├── chip.txt │ ├── music.pcf │ └── music.v │ ├── 14_ws2812 │ ├── 5k.pcf │ ├── 8k.pcf │ ├── Makefile │ ├── README.md │ ├── gtk-ws2812.gtkw │ ├── gtkwave.png │ ├── test.vcd │ ├── top.v │ ├── ws2812.jpg │ ├── ws2812.out │ ├── ws2812.sby │ ├── ws2812.v │ ├── ws2812_formal.gtkw │ └── ws2812_tb.v │ ├── 15_bram │ ├── Makefile │ ├── README.md │ ├── explicit_bram.v │ ├── implicit_bram.v │ └── top.v │ ├── 16_dsp │ ├── Makefile │ ├── README.md │ ├── calc.v │ ├── calc_dsp.v │ └── top.v │ ├── 17_flash │ ├── Makefile │ ├── README.md │ ├── flash_master │ │ ├── flash_program.sh │ │ └── prog.hex │ ├── spi_master.v │ └── top.v │ ├── 18_vga_pong │ ├── Makefile │ ├── hvsync_generator.v │ ├── main.mk │ ├── pong.pcf │ └── pong.v │ └── 19_vga_rotate │ ├── Makefile │ ├── README.md │ ├── pinmap.pcf │ └── top.v ├── doc ├── AdvancediCE40SPII2CHardenedIPUsageGuide.pdf ├── Datasheet │ ├── C116647_轻触开关，5.2_5.2_1.5，2.55N，100000次，贴片_2018-12-13.PDF │ ├── C375571_1206红绿蓝三色LED发光二极管_2019-07-29.PDF │ ├── C393939_TYPE-C母座16PIN快充闪充USB3.0沉板母座连接器_2019-05-21.pdf │ ├── C437199_1N5819_2019-10-12.PDF │ ├── SRV05-4.pdf │ └── lm1117-3.3中文资料-数据手册-参数.pdf ├── Digilent-Pmod_Interface_Specification.pdf ├── FPGA-DS-02053-5-6-Package-Diagrams.pdf ├── FPGA-TN-02001-3-1-iCE40-Programming-Configuration.pdf ├── OpenICE-PCB.png ├── OpenICE.jpg ├── iCE40 UltraPlus Breakout Board.pdf ├── iCE40 UltraPlus Family Data Sheet.pdf ├── iCE40HardwareChecklist.pdf ├── iCE40sysCLOCKPLLDesignandUsageGuide.pdf ├── oshug.pdf ├── 构图.png └── 框图.png └── tools ├── README.md ├── icesprog ├── icesprog.arm ├── icesprog.x64.linux └── icesprog.x64.macos /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "demo/Refence/up5k_6502/up5k_6502"] 2 | path = demo/Refence/up5k_6502/up5k_6502 3 | url = https://github.com/emeb/up5k_6502.git 4 | [submodule "demo/Refence/up5k_6502/up5k_6502"] 5 | path = demo/Refence/up5k_6502/up5k_6502 6 | url = https://github.com/emeb/up5k_6502.git 7 | [submodule "demo/Refence/picorv32/picorv32"] 8 | path = demo/Refence/picorv32/picorv32 9 | url = https://github.com/cliffordwolf/picorv32.git 10 | [submodule "demo/Refence/VexRiscv/VexRiscv"] 11 | path = demo/Refence/VexRiscv/VexRiscv 12 | url = https://github.com/wuxx/VexRiscv.git 13 | [submodule "demo/Refence/icicle/icicle"] 14 | path = demo/Refence/icicle/icicle 15 | url = https://github.com/grahamedgecombe/icicle.git 16 | [submodule "demo/Refence/litex-buildenv/litex-buildenv"] 17 | path = demo/Refence/litex-buildenv/litex-buildenv 18 | url = https://github.com/wuxx/litex-buildenv.git 19 | [submodule "demo/Refence/iceZ0mb1e/iceZ0mb1e"] 20 | path = demo/Refence/iceZ0mb1e/iceZ0mb1e 21 | url = https://github.com/wuxx/iceZ0mb1e.git 22 | -------------------------------------------------------------------------------- /Hardware/OpenICE V1.0b.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/OpenICE V1.0b.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/README.md: -------------------------------------------------------------------------------- 1 | FROM https://github.com/icebreaker-fpga/icebreaker 2 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/7segment-cache.lib: -------------------------------------------------------------------------------- 1 | EESchema-LIBRARY Version 2.4 2 | #encoding utf-8 3 | # 4 | #End Library 5 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/7segment-rescue.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/7segment-sch.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/7segment/v1.0a/7segment-sch.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/7segment.pro: -------------------------------------------------------------------------------- 1 | update=Tue 09 Apr 2019 12:05:06 AM PDT 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [schematic_editor] 16 | version=1 17 | PageLayoutDescrFile= 18 | PlotDirectoryName= 19 | SubpartIdSeparator=0 20 | SubpartFirstId=65 21 | NetFmtName= 22 | SpiceAjustPassiveValues=0 23 | LabSize=50 24 | ERC_TestSimilarLabels=1 25 | [pcbnew] 26 | version=1 27 | PageLayoutDescrFile= 28 | LastNetListRead= 29 | CopperLayerCount=2 30 | BoardThickness=1.6 31 | AllowMicroVias=0 32 | AllowBlindVias=0 33 | RequireCourtyardDefinitions=0 34 | ProhibitOverlappingCourtyards=1 35 | MinTrackWidth=0.15 36 | MinViaDiameter=0.5 37 | MinViaDrill=0.3 38 | MinMicroViaDiameter=0.2 39 | MinMicroViaDrill=0.09999999999999999 40 | MinHoleToHole=0.25 41 | TrackWidth1=0.15 42 | TrackWidth2=0.2 43 | TrackWidth3=0.25 44 | TrackWidth4=0.3 45 | ViaDiameter1=0.5 46 | ViaDrill1=0.3 47 | dPairWidth1=0.2 48 | dPairGap1=0.25 49 | dPairViaGap1=0.25 50 | SilkLineWidth=0.15 51 | SilkTextSizeV=1 52 | SilkTextSizeH=1 53 | SilkTextSizeThickness=0.15 54 | SilkTextItalic=0 55 | SilkTextUpright=1 56 | CopperLineWidth=0.2 57 | CopperTextSizeV=1.5 58 | CopperTextSizeH=1.5 59 | CopperTextThickness=0.3 60 | CopperTextItalic=0 61 | CopperTextUpright=1 62 | EdgeCutLineWidth=0.15 63 | CourtyardLineWidth=0.05 64 | OthersLineWidth=0.15 65 | OthersTextSizeV=1 66 | OthersTextSizeH=1 67 | OthersTextSizeThickness=0.15 68 | OthersTextItalic=0 69 | OthersTextUpright=1 70 | SolderMaskClearance=0.05 71 | SolderMaskMinWidth=0.05 72 | SolderPasteClearance=0 73 | SolderPasteRatio=-0 74 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/7segment_gerber.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/7segment/v1.0a/7segment_gerber.zip -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/fp-info-cache: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name pkl_allegro)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_allegro.pretty)(options "")(descr "")) 3 | (lib (name pkl_beaglebone)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_beaglebone.pretty)(options "")(descr "")) 4 | (lib (name pkl_buttons_switches)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_buttons_switches.pretty)(options "")(descr "")) 5 | (lib (name pkl_connectors)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_connectors.pretty)(options "")(descr "")) 6 | (lib (name pkl_dipol)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_dipol.pretty)(options "")(descr "")) 7 | (lib (name pkl_fiducials)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_fiducials.pretty)(options "")(descr "")) 8 | (lib (name pkl_housings_bga)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_bga.pretty)(options "")(descr "")) 9 | (lib (name pkl_housings_dfn_qfn)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_dfn_qfn.pretty)(options "")(descr "")) 10 | (lib (name pkl_housings_power)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_power.pretty)(options "")(descr "")) 11 | (lib (name pkl_housings_qfp)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_qfp.pretty)(options "")(descr "")) 12 | (lib (name pkl_housings_soic)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_soic.pretty)(options "")(descr "")) 13 | (lib (name pkl_housings_sop)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_sop.pretty)(options "")(descr "")) 14 | (lib (name pkl_housings_sot)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_sot.pretty)(options "")(descr "")) 15 | (lib (name pkl_jst)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_jst.pretty)(options "")(descr "")) 16 | (lib (name pkl_jumpers)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_jumpers.pretty)(options "")(descr "")) 17 | (lib (name pkl_led)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_led.pretty)(options "")(descr "")) 18 | (lib (name pkl_logos)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_logos.pretty)(options "")(descr "")) 19 | (lib (name pkl_mechanical)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_mechanical.pretty)(options "")(descr "")) 20 | (lib (name pkl_misc)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_misc.pretty)(options "")(descr "")) 21 | (lib (name pkl_ms)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_ms.pretty)(options "")(descr "")) 22 | (lib (name pkl_murata)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_murata.pretty)(options "")(descr "")) 23 | (lib (name pkl_pads)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_pads.pretty)(options "")(descr "")) 24 | (lib (name pkl_pin_headers)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_pin_headers.pretty)(options "")(descr "")) 25 | (lib (name pkl_samtec)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_samtec.pretty)(options "")(descr "")) 26 | (lib (name pkl_st)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_st.pretty)(options "")(descr "")) 27 | (lib (name pkl_tag_connect)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_tag_connect.pretty)(options "")(descr "")) 28 | ) 29 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/7segment/v1.0a/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name pkl_texas)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_texas.lib)(options "")(descr "")) 3 | (lib (name pkl_tag_connect)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_tag_connect.lib)(options "")(descr "")) 4 | (lib (name pkl_silabs)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_silabs.lib)(options "")(descr "")) 5 | (lib (name pkl_sensor)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_sensor.lib)(options "")(descr "")) 6 | (lib (name pkl_power)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_power.lib)(options "")(descr "")) 7 | (lib (name pkl_molex)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_molex.lib)(options "")(descr "")) 8 | (lib (name pkl_misc)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_misc.lib)(options "")(descr "")) 9 | (lib (name pkl_memory)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_memory.lib)(options "")(descr "")) 10 | (lib (name pkl_maxim)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_maxim.lib)(options "")(descr "")) 11 | (lib (name pkl_logos)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_logos.lib)(options "")(descr "")) 12 | (lib (name pkl_linear)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_linear.lib)(options "")(descr "")) 13 | (lib (name pkl_lattice)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_lattice.lib)(options "")(descr "")) 14 | (lib (name pkl_ftdi)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_ftdi.lib)(options "")(descr "")) 15 | (lib (name pkl_device)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_device.lib)(options "")(descr "")) 16 | (lib (name pkl_cypress)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_cypress.lib)(options "")(descr "")) 17 | (lib (name pkl_conn)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_conn.lib)(options "")(descr "")) 18 | (lib (name pkl_analog_devices)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_analog_devices.lib)(options "")(descr "")) 19 | (lib (name pkl_st)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_st.lib)(options "")(descr "")) 20 | (lib (name 7segment-rescue)(type Legacy)(uri ${KIPRJMOD}/7segment-rescue.lib)(options "")(descr "")) 21 | ) 22 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/README.md: -------------------------------------------------------------------------------- 1 | FROM https://github.com/icebreaker-fpga/icebreaker 2 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/dip-switch: -------------------------------------------------------------------------------- 1 | Reference, Quantity, Value, Footprint, Datasheet, Key, Source 2 | J1 ,1,"PMOD","pkl_connectors:PMODHeader_2x06_P2.54mm_Horizontal","~","conn-th-01in-6-2-hdr-ra","ANY" 3 | R1 R2 ,2,"10k","pkl_dipol:R_Array_Convex_4x0402","","res-0402cv-array-4-10k","" 4 | SW1 ,1,"SW_DIP_x08","Button_Switch_THT:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm","","sw-dip-8-01in-pitch","" -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/dip-switch-rescue.dcm: -------------------------------------------------------------------------------- 1 | EESchema-DOCLIB Version 2.0 2 | # 3 | #End Doc Library 4 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/dip-switch-sch.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/dip-switch-sch.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/dip-switch.pro: -------------------------------------------------------------------------------- 1 | update=Tue 09 Apr 2019 10:31:36 PM PDT 2 | version=1 3 | last_client=kicad 4 | [general] 5 | version=1 6 | RootSch= 7 | BoardNm= 8 | [cvpcb] 9 | version=1 10 | NetIExt=net 11 | [eeschema] 12 | version=1 13 | LibDir= 14 | [eeschema/libraries] 15 | [schematic_editor] 16 | version=1 17 | PageLayoutDescrFile= 18 | PlotDirectoryName= 19 | SubpartIdSeparator=0 20 | SubpartFirstId=65 21 | NetFmtName= 22 | SpiceAjustPassiveValues=0 23 | LabSize=50 24 | ERC_TestSimilarLabels=1 25 | [pcbnew] 26 | version=1 27 | PageLayoutDescrFile= 28 | LastNetListRead= 29 | CopperLayerCount=2 30 | BoardThickness=1.6 31 | AllowMicroVias=0 32 | AllowBlindVias=0 33 | RequireCourtyardDefinitions=0 34 | ProhibitOverlappingCourtyards=1 35 | MinTrackWidth=0.2 36 | MinViaDiameter=0.5 37 | MinViaDrill=0.3 38 | MinMicroViaDiameter=0.2 39 | MinMicroViaDrill=0.09999999999999999 40 | MinHoleToHole=0.25 41 | TrackWidth1=0.2 42 | TrackWidth2=0.25 43 | TrackWidth3=0.3 44 | ViaDiameter1=0.5 45 | ViaDrill1=0.3 46 | dPairWidth1=0.2 47 | dPairGap1=0.25 48 | dPairViaGap1=0.25 49 | SilkLineWidth=0.15 50 | SilkTextSizeV=1 51 | SilkTextSizeH=1 52 | SilkTextSizeThickness=0.15 53 | SilkTextItalic=0 54 | SilkTextUpright=1 55 | CopperLineWidth=0.2 56 | CopperTextSizeV=1.5 57 | CopperTextSizeH=1.5 58 | CopperTextThickness=0.3 59 | CopperTextItalic=0 60 | CopperTextUpright=1 61 | EdgeCutLineWidth=0.15 62 | CourtyardLineWidth=0.05 63 | OthersLineWidth=0.15 64 | OthersTextSizeV=1 65 | OthersTextSizeH=1 66 | OthersTextSizeThickness=0.15 67 | OthersTextItalic=0 68 | OthersTextUpright=1 69 | SolderMaskClearance=0.05 70 | SolderMaskMinWidth=0.05 71 | SolderPasteClearance=0 72 | SolderPasteRatio=-0 73 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/fp-info-cache: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/fp-lib-table: -------------------------------------------------------------------------------- 1 | (fp_lib_table 2 | (lib (name pkl_allegro)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_allegro.pretty)(options "")(descr "")) 3 | (lib (name pkl_beaglebone)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_beaglebone.pretty)(options "")(descr "")) 4 | (lib (name pkl_buttons_switches)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_buttons_switches.pretty)(options "")(descr "")) 5 | (lib (name pkl_connectors)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_connectors.pretty)(options "")(descr "")) 6 | (lib (name pkl_dipol)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_dipol.pretty)(options "")(descr "")) 7 | (lib (name pkl_fiducials)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_fiducials.pretty)(options "")(descr "")) 8 | (lib (name pkl_housings_bga)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_bga.pretty)(options "")(descr "")) 9 | (lib (name pkl_housings_dfn_qfn)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_dfn_qfn.pretty)(options "")(descr "")) 10 | (lib (name pkl_housings_power)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_power.pretty)(options "")(descr "")) 11 | (lib (name pkl_housings_qfp)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_qfp.pretty)(options "")(descr "")) 12 | (lib (name pkl_housings_soic)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_soic.pretty)(options "")(descr "")) 13 | (lib (name pkl_housings_sop)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_sop.pretty)(options "")(descr "")) 14 | (lib (name pkl_housings_sot)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_housings_sot.pretty)(options "")(descr "")) 15 | (lib (name pkl_jst)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_jst.pretty)(options "")(descr "")) 16 | (lib (name pkl_jumpers)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_jumpers.pretty)(options "")(descr "")) 17 | (lib (name pkl_led)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_led.pretty)(options "")(descr "")) 18 | (lib (name pkl_logos)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_logos.pretty)(options "")(descr "")) 19 | (lib (name pkl_mechanical)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_mechanical.pretty)(options "")(descr "")) 20 | (lib (name pkl_misc)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_misc.pretty)(options "")(descr "")) 21 | (lib (name pkl_ms)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_ms.pretty)(options "")(descr "")) 22 | (lib (name pkl_murata)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_murata.pretty)(options "")(descr "")) 23 | (lib (name pkl_pads)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_pads.pretty)(options "")(descr "")) 24 | (lib (name pkl_pin_headers)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_pin_headers.pretty)(options "")(descr "")) 25 | (lib (name pkl_samtec)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_samtec.pretty)(options "")(descr "")) 26 | (lib (name pkl_st)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_st.pretty)(options "")(descr "")) 27 | (lib (name pkl_tag_connect)(type KiCad)(uri ${KIPRJMOD}/../../lib/pkl/pkl_tag_connect.pretty)(options "")(descr "")) 28 | ) 29 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/DIP-SWICH/v1.0a/sym-lib-table: -------------------------------------------------------------------------------- 1 | (sym_lib_table 2 | (lib (name pkl_texas)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_texas.lib)(options "")(descr "")) 3 | (lib (name pkl_tag_connect)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_tag_connect.lib)(options "")(descr "")) 4 | (lib (name pkl_silabs)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_silabs.lib)(options "")(descr "")) 5 | (lib (name pkl_sensor)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_sensor.lib)(options "")(descr "")) 6 | (lib (name pkl_power)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_power.lib)(options "")(descr "")) 7 | (lib (name pkl_molex)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_molex.lib)(options "")(descr "")) 8 | (lib (name pkl_misc)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_misc.lib)(options "")(descr "")) 9 | (lib (name pkl_memory)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_memory.lib)(options "")(descr "")) 10 | (lib (name pkl_maxim)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_maxim.lib)(options "")(descr "")) 11 | (lib (name pkl_logos)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_logos.lib)(options "")(descr "")) 12 | (lib (name pkl_linear)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_linear.lib)(options "")(descr "")) 13 | (lib (name pkl_lattice)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_lattice.lib)(options "")(descr "")) 14 | (lib (name pkl_ftdi)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_ftdi.lib)(options "")(descr "")) 15 | (lib (name pkl_device)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_device.lib)(options "")(descr "")) 16 | (lib (name pkl_cypress)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_cypress.lib)(options "")(descr "")) 17 | (lib (name pkl_conn)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_conn.lib)(options "")(descr "")) 18 | (lib (name pkl_analog_devices)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_analog_devices.lib)(options "")(descr "")) 19 | (lib (name pkl_st)(type Legacy)(uri ${KIPRJMOD}/../../lib/pkl/pkl_st.lib)(options "")(descr "")) 20 | (lib (name dip-switch-rescue)(type Legacy)(uri ${KIPRJMOD}/dip-switch-rescue.lib)(options "")(descr "")) 21 | ) 22 | -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/NES/NES.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/NES/NES.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/NES/NES.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/NES/NES.png -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/VGA/PMOD_VGA.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/VGA/PMOD_VGA.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/VGA/openicev2_2.opj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/VGA/openicev2_2.opj -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/key-array/PCB/KEY_ARRAY.brd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/key-array/PCB/KEY_ARRAY.brd -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/key-array/SCH/PMOD_KEY-ARRAY.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/key-array/SCH/PMOD_KEY-ARRAY.pdf -------------------------------------------------------------------------------- /Hardware/PMOD_SubCard/key-led/SCH/PMOD_KeyLed.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/Hardware/PMOD_SubCard/key-led/SCH/PMOD_KeyLed.pdf -------------------------------------------------------------------------------- /demo/Pin_Out/openice.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RESET Button 5 | set_io -nowarn RST_n 27 6 | 7 | # RS232 8 | set_io -nowarn TX 6 9 | set_io -nowarn RX 9 10 | 11 | 12 | # RGB LED Driver 13 | set_io -nowarn LED_RED_N 39 14 | set_io -nowarn LED_GRN_N 40 15 | set_io -nowarn LED_BLU_N 41 16 | 17 | # SPI Flash 18 | set_io -nowarn FLASH_SCK 15 19 | set_io -nowarn FLASH_SSB 16 20 | set_io -nowarn FLASH_IO0 14 21 | set_io -nowarn FLASH_IO1 17 22 | set_io -nowarn FLASH_IO2 12 23 | set_io -nowarn FLASH_IO3 13 24 | 25 | # PMOD 1A 26 | set_io -nowarn P1A1 4 27 | set_io -nowarn P1A2 2 28 | set_io -nowarn P1A3 47 29 | set_io -nowarn P1A4 45 30 | set_io -nowarn P1A7 3 31 | set_io -nowarn P1A8 48 32 | set_io -nowarn P1A9 46 33 | set_io -nowarn P1A10 44 34 | 35 | # PMOD 1B 36 | set_io -nowarn P1B1 43 37 | set_io -nowarn P1B2 38 38 | set_io -nowarn P1B3 34 39 | set_io -nowarn P1B4 31 40 | set_io -nowarn P1B7 42 41 | set_io -nowarn P1B8 36 42 | set_io -nowarn P1B9 32 43 | set_io -nowarn P1B10 28 44 | 45 | # PMOD 2 46 | set_io -nowarn P2_1 27 47 | set_io -nowarn P2_2 25 48 | set_io -nowarn P2_3 21 49 | set_io -nowarn P2_4 19 50 | set_io -nowarn P2_7 26 51 | set_io -nowarn P2_8 23 52 | set_io -nowarn P2_9 20 53 | set_io -nowarn P2_10 18 54 | 55 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 56 | set_io -nowarn LED0 4 57 | set_io -nowarn LED1 3 58 | set_io -nowarn LED2 2 59 | set_io -nowarn LED3 48 60 | set_io -nowarn LED4 47 61 | set_io -nowarn LED5 46 62 | set_io -nowarn LED6 45 63 | set_io -nowarn LED7 44 64 | 65 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 66 | set_io -nowarn BTN0 4 67 | set_io -nowarn BTN1 3 68 | set_io -nowarn BTN2 2 69 | set_io -nowarn BTN3 48 70 | set_io -nowarn BTN4 47 71 | set_io -nowarn BTN5 46 72 | set_io -nowarn BTN6 45 73 | set_io -nowarn BTN7 44 74 | 75 | # Dial switch-->PMOD1B 76 | set_io -nowarn SWICH[0] 43 77 | set_io -nowarn SWICH[1] 38 78 | set_io -nowarn SWICH[2] 34 79 | set_io -nowarn SWICH[3] 31 80 | set_io -nowarn SWICH[4] 42 81 | set_io -nowarn SWICH[5] 36 82 | set_io -nowarn SWICH[6] 32 83 | set_io -nowarn SWICH[7] 28 84 | 85 | -------------------------------------------------------------------------------- /demo/Refence/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | -------------------------------------------------------------------------------- /demo/Refence/README.md: -------------------------------------------------------------------------------- 1 | # picorv32 2 | https://github.com/cliffordwolf/picorv32.git 3 | ## build & run 4 | `picocom -b 115200 /dev/ttyUSB0` 5 | `make ` 6 | 7 | sudo icesprog ` 8 | 9 | # VexRiscv 10 | 11 | # [OpenFPGA-ICE](https://github.com/OpenFPGA-ICE) 12 | 13 | https://github.com/wuxx/VexRiscv.git 14 | ## build & run 15 | `picocom -b 115200 /dev/ttyACM0` 16 | `cd scripts/Murax/iCESugar && make prog` 17 | 18 | # icicle 19 | https://github.com/grahamedgecombe/icicle.git 20 | ## build & run 21 | `picocom -b 9600 /dev/ttyACM0` 22 | `make BOARD=icesugar flash` 23 | 24 | # litex-fupy 25 | https://github.com/wuxx/litex-buildenv.git 26 | ## build 27 | `picocom -b 115200 /dev/ttyACM0` 28 | `./build_micropython.sh` 29 | ## how to test: connect the P27 to a LED 30 | >>import litex 31 | >>l = litex.LED(1) 32 | >>l.on() 33 | >>l.off() 34 | 35 | 36 | # up5k_6502 (commit-id 18610cb) 37 | https://github.com/emeb/up5k_6502.git 38 | ## build & run 39 | `picocom -b 9600 /dev/ttyACM0` 40 | `cd icestorm && make && make prog` 41 | 42 | # iceZ0mb1e 43 | https://github.com/wuxx/iceZ0mb1e.git 44 | ## build & run 45 | `picocom -b 9600 /dev/ttyACM0` 46 | `make firmware && make fpga && make flash` 47 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/README.md: -------------------------------------------------------------------------------- 1 | # ice40 demos mostly for the UltraPlus 2 | 3 | This is a project of mine to develop cool demos for the ice40 FPGAs 4 | using the icoTC toolchain (Yosys, arachne-pnr and icestorm). 5 | 6 | At the moment there is a working port of the MIST NES core, see the nes 7 | folder for more information. 8 | 9 | I'm going to work on a Gameboy core at some point but first that will 10 | need a CPU in Verilog instead of VHDL. 11 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.asc 3 | *.blif 4 | *.exp 5 | *.glb 6 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/boot_rom.dat: -------------------------------------------------------------------------------- 1 | 31 2 | FE 3 | FF 4 | AF 5 | 21 6 | FF 7 | 9F 8 | 32 9 | CB 10 | 7C 11 | 20 12 | FB 13 | 21 14 | 26 15 | FF 16 | 0E 17 | 11 18 | 3E 19 | 80 20 | 32 21 | E2 22 | 0C 23 | 3E 24 | F3 25 | E2 26 | 32 27 | 3E 28 | 77 29 | 77 30 | 3E 31 | FC 32 | E0 33 | 47 34 | F0 35 | 50 36 | FE 37 | 42 38 | 28 39 | 75 40 | 11 41 | 04 42 | 01 43 | 21 44 | 10 45 | 80 46 | 1A 47 | 4F 48 | CD 49 | A0 50 | 00 51 | CD 52 | A0 53 | 00 54 | 13 55 | 7B 56 | FE 57 | 34 58 | 20 59 | F2 60 | 11 61 | B2 62 | 00 63 | 06 64 | 08 65 | 1A 66 | 22 67 | 22 68 | 13 69 | 05 70 | 20 71 | F9 72 | 3E 73 | 19 74 | EA 75 | 10 76 | 99 77 | 21 78 | 2F 79 | 99 80 | 0E 81 | 0C 82 | 3D 83 | 28 84 | 08 85 | 32 86 | 0D 87 | 20 88 | F9 89 | 2E 90 | 0F 91 | 18 92 | F3 93 | 67 94 | 3E 95 | 64 96 | 57 97 | E0 98 | 42 99 | 3E 100 | 91 101 | E0 102 | 40 103 | 04 104 | 1E 105 | 02 106 | 0E 107 | 0C 108 | F0 109 | 44 110 | FE 111 | 90 112 | 20 113 | FA 114 | 0D 115 | 20 116 | F7 117 | 1D 118 | 20 119 | F2 120 | 0E 121 | 13 122 | 24 123 | 7C 124 | 1E 125 | 83 126 | FE 127 | 62 128 | 28 129 | 06 130 | 1E 131 | C1 132 | FE 133 | 64 134 | 20 135 | 06 136 | 7B 137 | E2 138 | 0C 139 | 3E 140 | 87 141 | E2 142 | F0 143 | 42 144 | 90 145 | E0 146 | 42 147 | 15 148 | 20 149 | D2 150 | 05 151 | 20 152 | 64 153 | 16 154 | 20 155 | 18 156 | CB 157 | E0 158 | 40 159 | 18 160 | 5C 161 | 06 162 | 04 163 | C5 164 | CB 165 | 11 166 | 17 167 | C1 168 | CB 169 | 11 170 | 17 171 | 05 172 | 20 173 | F5 174 | 22 175 | 22 176 | 22 177 | 22 178 | C9 179 | 3C 180 | 42 181 | A5 182 | 81 183 | A5 184 | 99 185 | 42 186 | 3C 187 | FF 188 | FF 189 | FF 190 | FF 191 | FF 192 | FF 193 | FF 194 | FF 195 | FF 196 | FF 197 | FF 198 | FF 199 | FF 200 | FF 201 | FF 202 | FF 203 | FF 204 | FF 205 | FF 206 | FF 207 | FF 208 | FF 209 | FF 210 | FF 211 | FF 212 | FF 213 | FF 214 | FF 215 | FF 216 | FF 217 | FF 218 | FF 219 | FF 220 | FF 221 | FF 222 | FF 223 | FF 224 | FF 225 | FF 226 | FF 227 | FF 228 | FF 229 | FF 230 | FF 231 | FF 232 | FF 233 | FF 234 | FF 235 | FF 236 | FF 237 | FF 238 | FF 239 | FF 240 | FF 241 | FF 242 | FF 243 | FF 244 | FF 245 | FF 246 | FF 247 | FF 248 | FF 249 | FF 250 | FF 251 | FF 252 | FF 253 | 3E 254 | 01 255 | E0 256 | 50 257 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/boot_rom.v: -------------------------------------------------------------------------------- 1 | module boot_rom ( 2 | address, 3 | clock, 4 | q); 5 | 6 | input [7:0] address; 7 | input clock; 8 | output reg [7:0] q; 9 | 10 | reg [7:0] rom [0:255]; 11 | $readmemh(rom, "boot_rom.dat") 12 | 13 | always@(posedge clk) 14 | q <= rom[address]; 15 | 16 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/cartridge.v: -------------------------------------------------------------------------------- 1 | /* 2 | Cartridge memory with SPI loader 3 | */ 4 | module gb_cartridge ( 5 | input clk, 6 | input reset, 7 | input [15:0] cart_addr, 8 | output [7:0] cart_dout, 9 | output ready, 10 | 11 | output spi_sck, 12 | output spi_csn, 13 | output spi_mosi, 14 | input spi_miso); 15 | 16 | reg load_done; 17 | initial load_done = 1'b0; 18 | assign ready = load_done; 19 | 20 | wire [13:0] mem_addr; 21 | wire [31:0] mem_din; 22 | wire [31:0] mem_dout; 23 | wire mem_wren; 24 | 25 | SB_SPRAM256KA spram_0 26 | ( 27 | .ADDRESS(mem_addr), 28 | .DATAIN(mem_din[15:0]), 29 | .MASKWREN(4'b1111), 30 | .WREN(wren), 31 | .CHIPSELECT(1'b1), 32 | .CLOCK(clk), 33 | .STANDBY(1'b0), 34 | .SLEEP(1'b0), 35 | .POWEROFF(1'b1), 36 | .DATAOUT(mem_dout[15:0]) 37 | ); 38 | 39 | SB_SPRAM256KA spram_1 40 | ( 41 | .ADDRESS(mem_addr), 42 | .DATAIN(mem_din[31:16]), 43 | .MASKWREN(4'b1111), 44 | .WREN(wren), 45 | .CHIPSELECT(1'b1), 46 | .CLOCK(clk), 47 | .STANDBY(1'b0), 48 | .SLEEP(1'b0), 49 | .POWEROFF(1'b1), 50 | .DATAOUT(mem_dout[31:16]) 51 | ); 52 | 53 | reg [13:0] load_addr; 54 | wire [31:0] load_data; 55 | wire load_wren; 56 | 57 | assign mem_addr = load_done ? cart_addr[14:1] : load_addr; 58 | assign mem_din = load_data; 59 | assign mem_wren = load_done ? 1'b0 : load_wren; 60 | assign cart_dout = cart_addr[1] ? (cart_addr[0] ? mem_dout[31:24] : mem_dout[23:16]) : 61 | (cart_addr[0] ? mem_dout[15:08] : mem_dout[07:00]); 62 | 63 | wire flashmem_valid = !load_done; 64 | wire flashmem_ready; 65 | assign load_wren = flashmem_ready; 66 | wire flashmem_rstn = !reset; 67 | wire [23:0] flashmem_addr = 24'h100000 | {load_addr, 2'b00}; 68 | 69 | always @(posedge reset or posedge clk) 70 | begin 71 | if (reset == 1'b1) begin 72 | load_done <= 1'b0; 73 | load_addr <= 14'h0000; 74 | end else begin 75 | if (flashmem_ready == 1'b1) begin 76 | if (load_addr == 14'h3FFF) begin 77 | load_done <= 1'b1; 78 | end else begin 79 | load_addr <= load_addr + 1'b1; 80 | end; 81 | end 82 | end 83 | end 84 | 85 | module icosoc_flashmem ( 86 | .clk(clk) 87 | .resetn(resetn), 88 | .valid(flashmem_valid), 89 | .ready(flashmem_ready), 90 | .addr(flashmem_addr), 91 | .rdata(load_data), 92 | 93 | 94 | .spi_cs(spi_csn), 95 | .spi_sclk(spi_sck), 96 | .spi_mosi(spi_mosi), 97 | .spi_miso(spi_miso) 98 | ); 99 | 100 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/data_io.v: -------------------------------------------------------------------------------- 1 | // 2 | // data_io.v 3 | // 4 | // io controller writable ram for the MiST board 5 | // https://github.com/mist-devel 6 | // 7 | // Copyright (c) 2015 Till Harbaum 8 | // 9 | // This source file is free software: you can redistribute it and/or modify 10 | // it under the terms of the GNU General Public License as published 11 | // by the Free Software Foundation, either version 3 of the License, or 12 | // (at your option) any later version. 13 | // 14 | // This source file is distributed in the hope that it will be useful, 15 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | // GNU General Public License for more details. 18 | // 19 | // You should have received a copy of the GNU General Public License 20 | // along with this program. If not, see . 21 | // 22 | 23 | module data_io ( 24 | // io controller spi interface 25 | input sck, 26 | input ss, 27 | input sdi, 28 | 29 | output downloading, // signal indicating an active download 30 | output reg [4:0] index, // menu index used to upload the file 31 | 32 | // external ram interface 33 | input clk, 34 | output reg wr, 35 | output reg [23:0] addr, 36 | output reg [15:0] data 37 | ); 38 | 39 | // ********************************************************************************* 40 | // spi client 41 | // ********************************************************************************* 42 | 43 | // this core supports only the display related OSD commands 44 | // of the minimig 45 | reg [14:0] sbuf; 46 | reg [7:0] cmd; 47 | reg [4:0] cnt; 48 | reg rclk; 49 | 50 | reg [23:0] laddr; 51 | reg [15:0] ldata; 52 | 53 | localparam UIO_FILE_TX = 8'h53; 54 | localparam UIO_FILE_TX_DAT = 8'h54; 55 | localparam UIO_FILE_INDEX = 8'h55; 56 | 57 | assign downloading = downloading_reg; 58 | reg downloading_reg = 1'b0; 59 | 60 | // data_io has its own SPI interface to the io controller 61 | always@(posedge sck, posedge ss) begin 62 | if(ss == 1'b1) 63 | cnt <= 5'd0; 64 | else begin 65 | rclk <= 1'b0; 66 | 67 | // don't shift in last bit. It is evaluated directly 68 | // when writing to ram 69 | if(cnt != 23) 70 | sbuf <= { sbuf[13:0], sdi}; 71 | 72 | // count 0-7 8-15 16-23 8-15 16-23 ... 73 | if(cnt < 23) cnt <= cnt + 4'd1; 74 | else cnt <= 4'd8; 75 | 76 | // finished command byte 77 | if(cnt == 7) 78 | cmd <= {sbuf[6:0], sdi}; 79 | 80 | // prepare/end transmission 81 | if((cmd == UIO_FILE_TX) && (cnt == 15)) begin 82 | // prepare 83 | if(sdi) begin 84 | // download rom to address 0 85 | laddr <= 24'h0 - 24'd1; 86 | downloading_reg <= 1'b1; 87 | end else 88 | downloading_reg <= 1'b0; 89 | end 90 | 91 | // command 0x54: UIO_FILE_TX 92 | if((cmd == UIO_FILE_TX_DAT) && (cnt == 23)) begin 93 | ldata <= {sbuf, sdi}; 94 | laddr <= laddr + 24'd1; 95 | rclk <= 1'b1; 96 | end 97 | 98 | // expose file (menu) index 99 | if((cmd == UIO_FILE_INDEX) && (cnt == 15)) 100 | index <= {sbuf[3:0], sdi}; 101 | end 102 | end 103 | 104 | reg rclkD, rclkD2; 105 | always@(posedge clk) begin 106 | // bring all signals from spi clock domain into local clock domain 107 | rclkD <= rclk; 108 | rclkD2 <= rclkD; 109 | wr <= 1'b0; 110 | 111 | if(rclkD && !rclkD2) begin 112 | addr <= laddr; 113 | data <= ldata; 114 | wr <= 1'b1; 115 | end 116 | end 117 | 118 | endmodule 119 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/flashmem.v: -------------------------------------------------------------------------------- 1 | module icosoc_flashmem ( 2 | input clk, resetn, 3 | 4 | input valid, 5 | output reg ready, 6 | input [23:0] addr, 7 | output reg [31:0] rdata, 8 | 9 | output reg spi_cs, 10 | output reg spi_sclk, 11 | output reg spi_mosi, 12 | input spi_miso 13 | ); 14 | reg [7:0] buffer; 15 | reg [3:0] xfer_cnt; 16 | reg [3:0] state; 17 | 18 | always @(posedge clk) begin 19 | ready <= 0; 20 | if (!resetn || !valid || ready) begin 21 | spi_cs <= 1; 22 | spi_sclk <= 1; 23 | xfer_cnt <= 0; 24 | state <= 0; 25 | end else begin 26 | spi_cs <= 0; 27 | if (xfer_cnt) begin 28 | if (spi_sclk) begin 29 | spi_sclk <= 0; 30 | spi_mosi <= buffer[7]; 31 | end else begin 32 | spi_sclk <= 1; 33 | buffer <= {buffer, spi_miso}; 34 | xfer_cnt <= xfer_cnt - 1; 35 | end 36 | end else 37 | case (state) 38 | 0: begin 39 | buffer <= 'h03; 40 | xfer_cnt <= 8; 41 | state <= 1; 42 | end 43 | 1: begin 44 | buffer <= addr[23:16]; 45 | xfer_cnt <= 8; 46 | state <= 2; 47 | end 48 | 2: begin 49 | buffer <= addr[15:8]; 50 | xfer_cnt <= 8; 51 | state <= 3; 52 | end 53 | 3: begin 54 | buffer <= addr[7:0]; 55 | xfer_cnt <= 8; 56 | state <= 4; 57 | end 58 | 4: begin 59 | xfer_cnt <= 8; 60 | state <= 5; 61 | end 62 | 5: begin 63 | rdata[7:0] <= buffer; 64 | xfer_cnt <= 8; 65 | state <= 6; 66 | end 67 | 6: begin 68 | rdata[15:8] <= buffer; 69 | xfer_cnt <= 8; 70 | state <= 7; 71 | end 72 | 7: begin 73 | rdata[23:16] <= buffer; 74 | xfer_cnt <= 8; 75 | state <= 8; 76 | end 77 | 8: begin 78 | rdata[31:24] <= buffer; 79 | ready <= 1; 80 | end 81 | endcase 82 | end 83 | end 84 | endmodule 85 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/gb.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2010 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 20 | # Version 10.1 Build 153 11/29/2010 SJ Full Version 21 | # Date created = 11:11:11 June 13, 2011 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "10.1" 26 | DATE = "11:11:11 June 13, 2011" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "gb" 31 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/gb_mist.v: -------------------------------------------------------------------------------- 1 | // 2 | // gb_mist.v 3 | // 4 | // Gameboy for the iCE40 UltraPlus 5 | // 6 | // Copyright (c) 2015 Till Harbaum 7 | // Copyright (c) 2017 David Shah 8 | // 9 | // This source file is free software: you can redistribute it and/or modify 10 | // it under the terms of the GNU General Public License as published 11 | // by the Free Software Foundation, either version 3 of the License, or 12 | // (at your option) any later version. 13 | // 14 | // This source file is distributed in the hope that it will be useful, 15 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | // GNU General Public License for more details. 18 | // 19 | // You should have received a copy of the GNU General Public License 20 | // along with this program. If not, see . 21 | // 22 | 23 | module gb_mist ( 24 | 25 | //flash interface 26 | output spi_csn, 27 | output spi_sck, 28 | output spi_mosi, 29 | input spi_miso, 30 | 31 | input [7:0] joystick; 32 | // video 33 | output VGA_HS, 34 | output VGA_VS, 35 | output [1:0] VGA_O 36 | ); 37 | 38 | assign LED = 1'b0; // light led 39 | 40 | wire reset = (reset_cnt != 0); 41 | reg [9:0] reset_cnt; 42 | always @(posedge clk24) begin 43 | if(!pll_locked) 44 | reset_cnt <= 10'd1023; 45 | else 46 | if(reset_cnt != 0) 47 | reset_cnt <= reset_cnt - 10'd1; 48 | end 49 | 50 | wire cart_ready; 51 | wire gb_reset = (!cart_ready) || reset; 52 | 53 | wire card_rd, cart_wr; 54 | wire [7:0] cart_di; 55 | 56 | gb_cartridge cart_i ( 57 | .clk(clk4), 58 | .reset(reset), 59 | .cart_addr(cart_addr), 60 | .cart_dout(cart_do), 61 | .ready(cart_ready), 62 | 63 | .spi_sck(spi_sck), 64 | .spi_csn(spi_csn), 65 | .spi_mosi(spi_mosi), 66 | .spi_miso(spi_miso)); 67 | 68 | wire lcd_clkena; 69 | wire [1:0] lcd_data; 70 | wire [1:0] lcd_mode; 71 | wire lcd_on; 72 | 73 | wire [15:0] audio_left; 74 | wire [15:0] audio_right; 75 | 76 | // the gameboy itself 77 | gb gb ( 78 | .reset ( gb_reset ), 79 | .clk ( clk4 ), // the whole gameboy runs on 4mhnz 80 | 81 | .fast_boot ( status[2] ), 82 | .joystick ( joystick ), 83 | 84 | // interface to the "external" game cartridge 85 | .cart_addr ( cart_addr ), 86 | .cart_rd ( cart_rd ), 87 | .cart_wr ( cart_wr ), 88 | .cart_do ( cart_do ), 89 | .cart_di ( cart_di ), 90 | 91 | // audio 92 | .audio_l ( audio_left ), 93 | .audio_r ( audio_right ), 94 | 95 | // interface to the lcd 96 | .lcd_clkena ( lcd_clkena ), 97 | .lcd_data ( lcd_data ), 98 | .lcd_mode ( lcd_mode ), 99 | .lcd_on ( lcd_on ) 100 | ); 101 | 102 | 103 | 104 | // the lcd to vga converter 105 | wire [1:0] video_d; 106 | wire video_hs, video_vs; 107 | 108 | lcd lcd_i ( 109 | .pclk ( clk8 ), 110 | .clk ( clk4 ), 111 | 112 | .tint ( status[1] ), 113 | 114 | // serial interface 115 | .clkena ( lcd_clkena ), 116 | .data ( lcd_data ), 117 | .mode ( lcd_mode ), // used to detect begin of new lines and frames 118 | .on ( lcd_on ), 119 | 120 | .hs ( video_hs ), 121 | .vs ( video_vs ), 122 | .dout ( video_d ) 123 | ); 124 | 125 | assign VGA_HS = video_hs; 126 | assign VGA_VS = video_vs; 127 | assign VGA_O = video_d; 128 | 129 | 130 | reg clk4; // 4.194304 MHz CPU clock and GB pixel clock 131 | always @(posedge clk8) 132 | clk4 <= !clk4; 133 | 134 | reg clk8; // 8.388608 MHz VGA pixel clock 135 | always @(posedge clk16) 136 | clk8 <= !clk8; 137 | 138 | reg clk16; // 16.777216 MHz 139 | always @(posedge clk32) 140 | clk16 <= !clk16; 141 | 142 | 143 | wire clk24; 144 | 145 | pll pll_i ( 146 | .clock_in(clk24), 147 | .clock_out(clk32), 148 | .locked(pll_locked) 149 | ); 150 | 151 | SB_HFOSC #( 152 | .CLKHF_DIV("0b01") 153 | ) iosc ( 154 | .CLKHFEN(1'b1), 155 | .CLKHFPU(1'b1), 156 | .CLKHF(clk24) 157 | ); 158 | 159 | endmodule 160 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/iram.v: -------------------------------------------------------------------------------- 1 | 2 | module iram ( 3 | address, 4 | clock, 5 | data, 6 | wren, 7 | q); 8 | 9 | input [12:0] address; 10 | input clock; 11 | input [7:0] data; 12 | input wren; 13 | output [7:0] q; 14 | 15 | `ifdef iram_use_spram 16 | SB_SPRAM256KA spram_i 17 | ( 18 | .ADDRESS({1'b0, address}), 19 | .DATAIN({8'b0, data}), 20 | .MASKWREN(4'b0011), 21 | .WREN(wren), 22 | .CHIPSELECT(1'b1), 23 | .CLOCK(clk), 24 | .STANDBY(1'b0), 25 | .SLEEP(1'b0), 26 | .POWEROFF(1'b1), 27 | .DATAOUT(q) 28 | ); 29 | 30 | `else 31 | reg [7:0] ram[0:8191]; 32 | reg [7:0] q_pre; 33 | always @(posedge clock) 34 | begin 35 | if(wren) 36 | ram[address] <= data; 37 | q_pre <= ram[address]; 38 | end 39 | assign q = q_pre; 40 | `endif -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/lcd.v: -------------------------------------------------------------------------------- 1 | // Gameboy for the MiST 2 | // (c) 2015 Till Harbaum 3 | 4 | // The gameboy lcd runs from a shift register which is filled at 4194304 pixels/sec 5 | 6 | module lcd ( 7 | input clk, 8 | input clkena, 9 | input [1:0] data, 10 | input [1:0] mode, 11 | 12 | input tint, 13 | 14 | // pixel clock 15 | input pclk, 16 | input on, 17 | 18 | // VGA output 19 | output reg hs, 20 | output reg vs, 21 | output [1:0] dout, 22 | ); 23 | 24 | // Mode 00: h-blank 25 | // Mode 01: v-blank 26 | // Mode 10: oam 27 | // Mode 11: oam and vram 28 | 29 | // space for 2*160 pixel 30 | reg [7:0] shift_reg_wptr; 31 | reg p_toggle; 32 | reg [1:0] shift_reg [511:0]; 33 | reg [1:0] last_mode_in; 34 | 35 | // shift register input 36 | always @(posedge clk) begin 37 | last_mode_in <= mode; 38 | 39 | // end of vsync 40 | if(clkena) begin 41 | shift_reg[{p_toggle, shift_reg_wptr}] <= data; 42 | shift_reg_wptr <= shift_reg_wptr + 8'd1; 43 | end 44 | 45 | // reset write pointer at end of hsync phase 46 | if((mode != 2'b00) && (last_mode_in == 2'b00)) begin 47 | shift_reg_wptr <= 8'd0; 48 | p_toggle <= !p_toggle; 49 | end 50 | end 51 | 52 | // 53 | parameter H = 160; // width of visible area 54 | parameter HFP = 24; // unused time before hsync 55 | parameter HS = 20; // width of hsync 56 | parameter HBP = 24; // unused time after hsync 57 | // total = 228 58 | 59 | parameter V = 576; // height of visible area 60 | parameter VFP = 2; // unused time before vsync 61 | parameter VS = 2; // width of vsync 62 | parameter VBP = 36; // unused time after vsync 63 | // total = 616 64 | 65 | reg[7:0] h_cnt; // horizontal pixel counter 66 | reg[9:0] v_cnt; // vertical pixel counter 67 | 68 | // horizontal pixel counter 69 | reg [1:0] last_mode_h; 70 | always@(posedge pclk) begin 71 | last_mode_h <= mode; 72 | 73 | if(h_cnt==H+HFP+HS+HBP-1) h_cnt <= 0; 74 | else h_cnt <= h_cnt + 1; 75 | 76 | // generate negative hsync signal 77 | if(h_cnt == H+HFP) hs <= 1'b0; 78 | if(h_cnt == H+HFP+HS) hs <= 1'b1; 79 | 80 | // synchronize to input mode 81 | // end of hblank 82 | if((mode == 2'b10) && (last_mode_h == 2'b00)) 83 | h_cnt <= 0; 84 | end 85 | 86 | // veritical pixel counter 87 | reg [1:0] last_mode_v; 88 | always@(posedge pclk) begin 89 | // the vertical counter is processed at the begin of each hsync 90 | if(h_cnt == H+HFP+HS+HBP-1) begin 91 | if(v_cnt==VS+VFP+V+VBP-1) v_cnt <= 0; 92 | else v_cnt <= v_cnt + 1; 93 | 94 | // generate positive vsync signal 95 | if(v_cnt == V+VFP) vs <= 1'b1; 96 | if(v_cnt == V+VFP+VS) vs <= 1'b0; 97 | 98 | last_mode_v <= mode; 99 | 100 | // synchronize to input mode 101 | // end of mode 01 (vblank) 102 | // make and offset of - 4 for the 4 line delay of the scandoubler 103 | if((mode != 2'b01) && (last_mode_v == 2'b01)) 104 | v_cnt <= 616-4; 105 | end 106 | end 107 | 108 | // ------------------------------------------------------------------------------- 109 | // ------------------------------- pixel generator ------------------------------- 110 | // ------------------------------------------------------------------------------- 111 | reg blank; 112 | reg [1:0] pixel_reg; 113 | reg [7:0] shift_reg_rptr; 114 | 115 | always@(posedge pclk) begin 116 | // visible area? 117 | if((v_cnt < V) && (h_cnt < H)) begin 118 | blank <= 1'b0; 119 | pixel_reg <= shift_reg[{!p_toggle, shift_reg_rptr}]; 120 | shift_reg_rptr <= shift_reg_rptr + 8'd1; 121 | end else begin 122 | blank <= 1'b1; 123 | shift_reg_rptr <= 8'd0; 124 | end 125 | end 126 | 127 | wire [1:0] pixel = on?pixel_reg:2'b00; 128 | 129 | assign dout = pixel; 130 | endmodule 131 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 24.000 MHz 9 | * Requested output frequency: 33.554 MHz 10 | * Achieved output frequency: 33.750 MHz 11 | */ 12 | 13 | module pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_CORE #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0001), // DIVR = 1 22 | .DIVF(7'b0101100), // DIVF = 44 23 | .DIVQ(3'b100), // DIVQ = 4 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .REFERENCECLK(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/readme.md: -------------------------------------------------------------------------------- 1 | Source code for Gameboy for MIST, modified for ice40 2 | ==================================================== 3 | 4 | This is source code of a gameboy implementation for the ic40-up5k, based 5 | on the MIST gameboy core. -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/sprite.v: -------------------------------------------------------------------------------- 1 | // 2 | // sprite.v 3 | // 4 | // Gameboy for the MIST board https://github.com/mist-devel 5 | // 6 | // Copyright (c) 2015 Till Harbaum 7 | // 8 | // This source file is free software: you can redistribute it and/or modify 9 | // it under the terms of the GNU General Public License as published 10 | // by the Free Software Foundation, either version 3 of the License, or 11 | // (at your option) any later version. 12 | // 13 | // This source file is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program. If not, see . 20 | // 21 | 22 | module sprite ( 23 | input clk, 24 | input size16, 25 | 26 | input [7:0] v_cnt, 27 | input [7:0] h_cnt, 28 | 29 | output [7:0] x, 30 | 31 | // interface to read pixel data from memory 32 | output [10:0] addr, 33 | input [1:0] ds, 34 | input [7:0] data, 35 | 36 | output pixel_active, 37 | output pixel_cmap, 38 | output pixel_prio, 39 | output [1:0] pixel_data, 40 | 41 | input oam_wr, 42 | input [1:0] oam_addr, 43 | input [7:0] oam_di, 44 | output [7:0] oam_do 45 | ); 46 | 47 | // x position for priority detection. Invisible sprites are far to the right and 48 | // have minimum priority 49 | assign x = v_visible?x_pos:8'hff; 50 | 51 | // register used to store pixel data for current line 52 | reg [7:0] data0; 53 | reg [7:0] data1; 54 | 55 | always @(posedge clk) begin 56 | if(ds[0]) data0 <= data; 57 | if(ds[1]) data1 <= data; 58 | end 59 | 60 | wire [7:0] height = size16?8'd16:8'd8; 61 | 62 | wire v_visible = (v_cnt + 8'd16 >= y_pos) && (v_cnt + 8'd16 < y_pos + height); 63 | wire visible = v_visible && (h_cnt + 8'd8 >= x_pos) && (h_cnt < x_pos); 64 | 65 | // x position within sprite, mirror horizontally if required 66 | wire [2:0] col_n = h_cnt - x_pos; 67 | wire [2:0] col = flags[1]?col_n:~col_n; 68 | 69 | assign pixel_data = { data1[col], data0[col] }; 70 | assign pixel_active = (pixel_data != 0) && visible; 71 | 72 | // y position within sprite, mirror vertically if required 73 | wire [3:0] row_n = v_cnt - y_pos; 74 | wire [3:0] row = flags[2]?~row_n:row_n; 75 | 76 | // 16 pixel tall sprites use one more rwo counter bit and the lsb 77 | // of the tile index is ignored 78 | wire [10:0] addr8 = { tile , row[2:0]}; 79 | wire [10:0] addr16 = { tile[7:1] , row}; 80 | assign addr = size16?addr16:addr8; 81 | 82 | assign pixel_cmap = flags[0]; 83 | assign pixel_prio = flags[3]; 84 | 85 | reg [7:0] y_pos; 86 | reg [7:0] x_pos; 87 | reg [7:0] tile; 88 | reg [3:0] flags; 89 | 90 | always @(posedge clk) begin 91 | if(oam_wr) begin 92 | case(oam_addr) 93 | 0: y_pos <= oam_di; 94 | 1: x_pos <= oam_di; 95 | 2: tile <= oam_di; 96 | 3: flags <= oam_di[7:4]; 97 | endcase 98 | end 99 | end 100 | 101 | assign oam_do = 102 | (oam_addr == 0)?y_pos: 103 | (oam_addr == 1)?x_pos: 104 | (oam_addr == 2)?tile: 105 | { flags, 4'h0 }; 106 | 107 | endmodule 108 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/sprite_sort.v: -------------------------------------------------------------------------------- 1 | // 2 | // sprite_sort.v 3 | // 4 | // Gameboy for the MIST board https://github.com/mist-devel 5 | // 6 | // Copyright (c) 2015 Till Harbaum 7 | // 8 | // This source file is free software: you can redistribute it and/or modify 9 | // it under the terms of the GNU General Public License as published 10 | // by the Free Software Foundation, either version 3 of the License, or 11 | // (at your option) any later version. 12 | // 13 | // This source file is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program. If not, see . 20 | // 21 | 22 | module sprite_sort #( 23 | parameter WIDTH = 40 24 | )( 25 | // system signals 26 | input clk, 27 | input load, 28 | 29 | // sort 30 | input [8*WIDTH-1:0] x, 31 | output [6*WIDTH-1:0] idx 32 | ); 33 | 34 | wire [7:0] in [WIDTH-1:0]; 35 | 36 | generate 37 | genvar i; 38 | 39 | // map 1d input array onto 2d work array 40 | // and 2d result array into 1d output array 41 | for(i=0;i values[2*i+1]; 67 | assign int_val[2*i+0] = swap0[i]?values[2*i+1]:values[2*i+0]; 68 | assign int_val[2*i+1] = swap0[i]?values[2*i+0]:values[2*i+1]; 69 | assign int_idx[2*i+0] = swap0[i]?index[2*i+1]:index[2*i+0]; 70 | assign int_idx[2*i+1] = swap0[i]?index[2*i+0]:index[2*i+1]; 71 | end 72 | 73 | // 2nd stage 74 | assign sort_val[0] = int_val[0]; 75 | assign sort_idx[0] = int_idx[0]; 76 | assign sort_val[WIDTH-1] = int_val[WIDTH-1]; 77 | assign sort_idx[WIDTH-1] = int_idx[WIDTH-1]; 78 | for(i=0;i int_val[2*i+2]; 80 | assign sort_val[2*i+1] = swap1[i]?int_val[2*i+2]:int_val[2*i+1]; 81 | assign sort_val[2*i+2] = swap1[i]?int_val[2*i+1]:int_val[2*i+2]; 82 | assign sort_idx[2*i+1] = swap1[i]?int_idx[2*i+2]:int_idx[2*i+1]; 83 | assign sort_idx[2*i+2] = swap1[i]?int_idx[2*i+1]:int_idx[2*i+2]; 84 | end 85 | 86 | for(i=0;i 7 | // 8 | // This source file is free software: you can redistribute it and/or modify 9 | // it under the terms of the GNU General Public License as published 10 | // by the Free Software Foundation, either version 3 of the License, or 11 | // (at your option) any later version. 12 | // 13 | // This source file is distributed in the hope that it will be useful, 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 | // GNU General Public License for more details. 17 | // 18 | // You should have received a copy of the GNU General Public License 19 | // along with this program. If not, see . 20 | // 21 | 22 | module timer ( 23 | input reset, 24 | input clk, // 4 Mhz cpu clock 25 | 26 | output reg irq, 27 | 28 | // cpu register interface 29 | input cpu_sel, 30 | input [1:0] cpu_addr, 31 | input cpu_wr, 32 | input [7:0] cpu_di, 33 | output [7:0] cpu_do 34 | ); 35 | 36 | // input: 4Mhz 37 | // clk_div[0] = 2Mhz 38 | // clk_div[1] = 1Mhz 39 | // clk_div[2] = 524khz 40 | // clk_div[3] = 262khz 41 | // clk_div[4] = 131khz 42 | // clk_div[5] = 65khz 43 | // clk_div[6] = 32khz 44 | // clk_div[7] = 16khz 45 | // clk_div[8] = 8khz 46 | // clk_div[9] = 4khz 47 | 48 | reg [9:0] clk_div; 49 | always @(posedge clk) 50 | clk_div <= clk_div + 10'd1; 51 | 52 | reg [7:0] div; 53 | reg [7:0] tma; 54 | reg [7:0] tima; 55 | reg [2:0] tac; 56 | 57 | always @(posedge clk) begin 58 | if(reset) begin 59 | tima <= 8'h00; 60 | tma <= 8'h00; 61 | tac <= 8'h00; 62 | irq <= 1'b0; 63 | end else begin 64 | irq <= 1'b0; 65 | 66 | if(clk_div[7:0] == 0) // 16kHz 67 | div <= div + 8'd1; 68 | 69 | // timer enabled? 70 | if(tac[2]) begin 71 | // timer frequency 72 | if(((tac[1:0] == 2'b00) && (clk_div[9:0] == 0)) || // 4 khz 73 | ((tac[1:0] == 2'b01) && (clk_div[3:0] == 0)) || // 262 khz 74 | ((tac[1:0] == 2'b10) && (clk_div[5:0] == 0)) || // 65 khz 75 | ((tac[1:0] == 2'b11) && (clk_div[7:0] == 0))) begin // 16 khz 76 | 77 | if(tima != 8'hff) 78 | tima <= tima + 8'd1; 79 | else begin 80 | irq <= 1'b1; // irq when timer overflows 81 | tima <= tma; // reload timer 82 | end 83 | end 84 | end 85 | 86 | if(cpu_sel && cpu_wr) begin 87 | case(cpu_addr) 88 | 2'b00: div <= 8'h00; // writing clears counter 89 | 2'b01: tima <= cpu_di; 90 | 2'b10: tma <= cpu_di; 91 | 2'b11: tac <= cpu_di[2:0]; 92 | endcase 93 | end 94 | end 95 | end 96 | 97 | assign cpu_do = 98 | (cpu_addr == 2'b00)?div: 99 | (cpu_addr == 2'b01)?tima: 100 | (cpu_addr == 2'b10)?tma: 101 | {5'b00000, tac}; 102 | 103 | endmodule 104 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/vram.v: -------------------------------------------------------------------------------- 1 | module vram ( 2 | address, 3 | clock, 4 | data, 5 | wren, 6 | q); 7 | 8 | input [12:0] address; 9 | input clock; 10 | input [7:0] data; 11 | input wren; 12 | output [7:0] q; 13 | 14 | `ifdef vram_use_spram 15 | SB_SPRAM256KA spram_i 16 | ( 17 | .ADDRESS({1'b0, address}), 18 | .DATAIN({8'b0, data}), 19 | .MASKWREN(4'b0011), 20 | .WREN(wren), 21 | .CHIPSELECT(1'b1), 22 | .CLOCK(clk), 23 | .STANDBY(1'b0), 24 | .SLEEP(1'b0), 25 | .POWEROFF(1'b1), 26 | .DATAOUT(q) 27 | ); 28 | 29 | `else 30 | reg [7:0] ram[0:8191]; 31 | reg [7:0] q_pre; 32 | always @(posedge clock) 33 | begin 34 | if(wren) 35 | ram[address] <= data; 36 | q_pre <= ram[address]; 37 | end 38 | assign q = q_pre; 39 | `endif -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/gameboy/zpram.v: -------------------------------------------------------------------------------- 1 | module zpram ( 2 | address, 3 | clock, 4 | data, 5 | wren, 6 | q); 7 | 8 | input [7:0] address; 9 | input clock; 10 | input [7:0] data; 11 | input wren; 12 | output reg [7:0] q; 13 | 14 | reg [7:0] ram[0:255]; 15 | 16 | always @(posedge clock) 17 | begin 18 | if(wren) 19 | ram[address] <= data; 20 | q <= ram[address]; 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/.gitignore: -------------------------------------------------------------------------------- 1 | *.asc 2 | *.bin 3 | *.blif 4 | *.exp 5 | *.vvp 6 | *.blog 7 | *.log 8 | *.vlog 9 | *.json 10 | *.rpt 11 | 12 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = nes 2 | 3 | TOP = NES_ice40 4 | PIN_DEF = up5k.pcf 5 | DEVICE = up5k 6 | ADD_SRC = $(wildcard *.v) 7 | FREQ = 8 8 | #USE_ARACHNEPNR = Y 9 | 10 | include main.mk 11 | 12 | GAMES = $(sort $(wildcard rom/game*.nes)) 13 | IMAGES = $(GAMES:.nes=.bin) 14 | 15 | rom/games.bin: $(IMAGES) 16 | cat $^ > $@ 17 | 18 | up5kprog_game: rom/games.bin 19 | iceprog -o 1024k rom/games.bin 20 | 21 | image: 22 | truncate -s 1048576 nes.bin 23 | cat nes.bin rom/game_smb.bin > nes_smb.bin 24 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/README.md: -------------------------------------------------------------------------------- 1 | # 基于开源FPGA-OpeniCE的NES游戏 2 | ![OpenNES](https://github.com/OpenFPGA-ICE/OpenICE/blob/master/demo/Refence/up5k-demos/nes/image/%E5%B0%8F%E9%9C%B8%E7%8E%8BFC%E6%B8%B8%E6%88%8F%E6%9C%BA.jpg?raw=true) 3 | 4 | ## 硬件连接 5 | 所需硬件 6 | ### [PMOD VGA扩展板](https://github.com/OpenFPGA-ICE/OpenICE/tree/master/Hardware/PMOD_SubCard/VGA) 7 | ### [PMOD NES扩展板](https://github.com/OpenFPGA-ICE/OpenICE/tree/master/Hardware/PMOD_SubCard/NES) 8 | ### FC手柄 9 | 最好选用原装手柄。 10 | 11 | 手柄的协议如图所示： 12 | ![OpenNES](https://github.com/OpenFPGA-ICE/OpenICE/blob/master/demo/Refence/up5k-demos/nes/image/FC%E6%89%8B%E6%9F%84%E4%BF%A1%E5%8F%B7%E5%AE%9A%E4%B9%89.jpg?raw=true) 13 | 原理比较简单：协议共有3个信号，Latch、Clock、Data、Latch用于锁存按键值，给一个Latch高电平脉冲，然后在每个clock周期的低电平时读Data，即可依次读出8个按键的值，A、B、SELECT、START、Up、Down、Left、Right。VCC可以直接接3.3V即可。（注意实际上Clock只需7拍即可，Latch脉冲低电平后即可读出第一个按键A的值，后续7个Clock脉冲读出其他7个按键） 14 | 15 | ### 扬声器 16 | 将上诉硬件和主板按照下面图片连接 17 | ![OpenNES](https://github.com/OpenFPGA-ICE/OpenICE/blob/master/demo/Refence/up5k-demos/nes/image/NES%20Games.png?raw=true) 18 | ## 综合编译下载 19 | ``` 20 | git clone https://github.com/OpenFPGA-ICE/OpenICE/tree/master/demo/Refence/up5k-demos/nes 21 | cd nes 22 | make 23 | ``` 24 | make会综合出FC系统的bitstream文件nes.bin，使用icesprog可以进行烧录 25 | 26 | ```sudo icesprog nes.bin``` 27 | 28 | 随后，需要将游戏ROM文件打包并烧录至flash偏移1M中，FC启动之后会从此处读ROM文件运行。 29 | ``` 30 | cd rom 31 | sudo chmod 777 nes2bin 32 | ./nes2bin.py games/139.nes 139.bin 33 | sudo chmod 777 139.bin 34 | sudo icesprog -o 0x100000 139.bin 35 | ``` 36 | 烧写的游戏是绿色军团，也可自行打包其他nes游戏，可以到[52nes](http://www.52nes.com/)下载其他游戏。 37 | 下有以下几种游戏： 38 | 超时空要塞无敌版 Beyondtime 39 | 93超级魂斗罗(中文) 93-contra 40 | 绿色兵团无限人 76 41 | 绿色兵团金身无敌版 92 42 | 赤色要塞无敌版 139 43 | 冒险岛经典版 smb 44 | 45 | 46 | ## 演示视频 47 | 48 | [B站演示视频](https://www.bilibili.com/video/bv1G54y1U7yN) -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/README_OLD.md: -------------------------------------------------------------------------------- 1 | # Port of the MIST NES core to ice40 2 | 3 | This port of the NES MIST core is currently designed for the upduino 4 | board, with a VGA DAC and connection to a NES controller added. 5 | 6 | Currently it can run any NROM, MMC1, UNROM or CNROM game requiring 7 | either less than 64kB PRG and CHR ROM, or less than 128kB PRG ROM and 8 | 8kB CHR RAM. Sound is a tiny bit big for the 5k UltraPlus so is not 9 | included. By removing all the mappers - and some registers needed for 10 | reliable performance - you can just about get it to fit but it uses 11 | every single PLB in the device. 12 | 13 | It would be much better suited to a 8k board with more external RAM. 14 | Then you would have room for bigger games (up to the size of the board's 15 | RAM), more mapper support (e.g. MMC3) and sound. The only changes needed 16 | would be changing cart_mem to use external RAM instead of UltraPlus 17 | SPRAM, and creating a new Makefile and pcf file. 18 | 19 | 'Streaming' games from SQI flash might be just about doable from a 20 | timing point of view but I don't think there are enough PLBs available 21 | at present on the 5k, and it would probably be quite a bit of work for 22 | it to work reliably. 23 | 24 | I'll probably port this to my icoBoard with a VGA PMOD at some point, 25 | which could end up being a very nice platform for this. 26 | 27 | Credit to the original developer of the NES core, Ludvig Strigeus for 28 | making such an awesome project! Like the original core this is licensed 29 | under the GNU GPL. 30 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/compat.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | module MUXCY(output O, input CI, input DI, input S); 4 | assign O = S ? CI : DI; 5 | endmodule 6 | module MUXCY_L(output LO, input CI, input DI, input S); 7 | assign LO = S ? CI : DI; 8 | endmodule 9 | module MUXCY_D(output LO, output O, input CI, input DI, input S); 10 | assign LO = S ? CI : DI; 11 | assign O = LO; 12 | endmodule 13 | module XORCY(output O, input CI, input LI); 14 | assign O = CI ^ LI; 15 | endmodule 16 | module XOR2(output O, input I0, input I1); 17 | assign O = I0 ^ I1; 18 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/flashmem.v: -------------------------------------------------------------------------------- 1 | // SPI flash memory interface, taken from the icosoc project 2 | 3 | module icosoc_flashmem ( 4 | input clk, reset, 5 | 6 | input valid, 7 | output reg ready, 8 | input [23:0] addr, 9 | output reg [31:0] rdata, 10 | 11 | output reg spi_cs, 12 | output reg spi_sclk, 13 | output reg spi_mosi, 14 | input spi_miso 15 | ); 16 | reg [7:0] buffer; 17 | reg [3:0] xfer_cnt; 18 | reg [3:0] state; 19 | 20 | always @(posedge clk) begin 21 | ready <= 0; 22 | if (reset || !valid || ready) begin 23 | spi_cs <= 1; 24 | spi_sclk <= 1; 25 | xfer_cnt <= 0; 26 | state <= 0; 27 | end else begin 28 | spi_cs <= 0; 29 | if (xfer_cnt) begin 30 | if (spi_sclk) begin 31 | spi_sclk <= 0; 32 | spi_mosi <= buffer[7]; 33 | end else begin 34 | spi_sclk <= 1; 35 | buffer <= {buffer, spi_miso}; 36 | xfer_cnt <= xfer_cnt - 1; 37 | end 38 | end else 39 | case (state) 40 | 0: begin 41 | buffer <= 'h03; 42 | xfer_cnt <= 8; 43 | state <= 1; 44 | end 45 | 1: begin 46 | buffer <= addr[23:16]; 47 | xfer_cnt <= 8; 48 | state <= 2; 49 | end 50 | 2: begin 51 | buffer <= addr[15:8]; 52 | xfer_cnt <= 8; 53 | state <= 3; 54 | end 55 | 3: begin 56 | buffer <= addr[7:0]; 57 | xfer_cnt <= 8; 58 | state <= 4; 59 | end 60 | 4: begin 61 | xfer_cnt <= 8; 62 | state <= 5; 63 | end 64 | 5: begin 65 | rdata[7:0] <= buffer; 66 | xfer_cnt <= 8; 67 | state <= 6; 68 | end 69 | 6: begin 70 | rdata[15:8] <= buffer; 71 | xfer_cnt <= 8; 72 | state <= 7; 73 | end 74 | 7: begin 75 | rdata[23:16] <= buffer; 76 | xfer_cnt <= 8; 77 | state <= 8; 78 | end 79 | 8: begin 80 | rdata[31:24] <= buffer; 81 | ready <= 1; 82 | end 83 | endcase 84 | end 85 | end 86 | endmodule 87 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/generic_ram.v: -------------------------------------------------------------------------------- 1 | // Simple, platform-agnostic single-ported RAM 2 | 3 | module generic_ram(clock, reset, address, wren, write_data, read_data); 4 | 5 | parameter integer WIDTH = 8; 6 | parameter integer WORDS = 2048; 7 | localparam ADDR_BITS = $clog2(WORDS-1); 8 | 9 | input clock; 10 | input reset; 11 | input [ADDR_BITS-1:0] address; 12 | input wren; 13 | input [WIDTH-1:0] write_data; 14 | output reg [WIDTH-1:0] read_data; 15 | 16 | reg [WIDTH-1:0] mem[0:WORDS-1]; 17 | 18 | reg [ADDR_BITS-1:0] a_prereg; 19 | reg [WIDTH-1:0] d_prereg; 20 | reg wren_prereg; 21 | 22 | always @(posedge clock) begin 23 | if (reset == 1'b1) begin 24 | wren_prereg <= 0; 25 | a_prereg <= 0; 26 | d_prereg <= 0; 27 | end else begin 28 | wren_prereg <= wren; 29 | a_prereg <= address; 30 | d_prereg <= write_data; 31 | end 32 | 33 | 34 | read_data <= mem[a_prereg]; 35 | if (wren_prereg) mem[a_prereg] <= d_prereg; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/image/FC手柄信号定义.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/image/FC手柄信号定义.jpg -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/image/NES Games.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/image/NES Games.png -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/image/小霸王FC游戏机.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/image/小霸王FC游戏机.jpg -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -blif $@' $(ADD_SRC) 6 | 7 | %.json: $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -json $@' $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --placer heap --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack -s $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | iceprog $< 42 | 43 | sudo-prog: $(PROJ).bin 44 | @echo 'Executing prog as root!!!' 45 | sudo iceprog $< 46 | 47 | clean: 48 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 49 | 50 | .SECONDARY: 51 | .PHONY: all prog clean 52 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/main_mem.v: -------------------------------------------------------------------------------- 1 | /* 2 | This memory device contains both system memory 3 | and cartridge data. 4 | */ 5 | 6 | module main_mem( 7 | input clock, reset, 8 | 9 | input reload, 10 | input [3:0] index, 11 | 12 | output load_done, 13 | output [31:0] flags_out, 14 | //NES interface 15 | input [21:0] mem_addr, 16 | input mem_rd_cpu, mem_rd_ppu, 17 | input mem_wr, 18 | output reg [7:0] mem_q_cpu, mem_q_ppu, 19 | input [7:0] mem_d, 20 | 21 | //Flash load interface 22 | output flash_csn, 23 | output flash_sck, 24 | output flash_mosi, 25 | input flash_miso); 26 | 27 | // Compress the 4MB logical address space to our limited available space 28 | // In the future a more sophisticated memory system will keep games in 29 | // SQI flash to expand the space available 30 | 31 | // Also may consider changing this based on mapper to make the most 32 | // of limited memory 33 | 34 | wire prgrom_en, chrrom_en, vram_en, cpuram_en, cartram_en; 35 | 36 | // Mapping 37 | // 0... : PRG : lower 64kB SPRAM 38 | // 10.. : CHR : upper 64kB SPRAM 39 | // 1100 : CHR-VRAM : dedicated 2kB RAM 40 | // 1110 : CPU-RAM : dedicated 2kB RAM 41 | // 1111 : CART-RAM : dedicated 2kB RAM 42 | 43 | assign prgrom_en = !mem_addr[21]; 44 | assign chrrom_en = mem_addr[21] & !mem_addr[20]; 45 | assign vram_en = mem_addr[21] & mem_addr[20] & !mem_addr[19] & !mem_addr[18]; 46 | assign cpuram_en = mem_addr[21] & mem_addr[20] & mem_addr[19] & !mem_addr[18]; 47 | assign cartram_en = mem_addr[21] & mem_addr[20] & mem_addr[19] & mem_addr[18]; 48 | 49 | wire [20:0] segment_addr = prgrom_en ? mem_addr[20:0] : (chrrom_en ? {1'b0, mem_addr[19:0]} : {3'b0, mem_addr[17:0]}); 50 | 51 | wire [7:0] cpuram_read_data, vram_read_data, cart_read_data; 52 | wire rden = mem_rd_cpu | mem_rd_ppu; 53 | 54 | always@(posedge clock or posedge reset) 55 | begin 56 | if (reset == 1'b1) begin 57 | mem_q_cpu <= 0; 58 | mem_q_ppu <= 0; 59 | end else begin 60 | if (mem_rd_cpu) 61 | mem_q_cpu <= cpuram_en ? cpuram_read_data : (vram_en ? vram_read_data : cart_read_data); 62 | if (mem_rd_ppu) 63 | mem_q_ppu <= cpuram_en ? cpuram_read_data : (vram_en ? vram_read_data : cart_read_data); 64 | end; 65 | end 66 | 67 | cart_mem cart_i ( 68 | .clock(clock), 69 | .reset(reset), 70 | .reload(reload), 71 | .index(index), 72 | .cart_ready(load_done), 73 | .flags_out(flags_out), 74 | .address(segment_addr), 75 | .prg_sel(prgrom_en), 76 | .chr_sel(chrrom_en), 77 | .ram_sel(cartram_en), 78 | .rden(rden), 79 | .wren(mem_wr), 80 | .write_data(mem_d), 81 | .read_data(cart_read_data), 82 | 83 | //Flash load interface 84 | .flash_csn(flash_csn), 85 | .flash_sck(flash_sck), 86 | .flash_mosi(flash_mosi), 87 | .flash_miso(flash_miso) 88 | ); 89 | 90 | generic_ram #( 91 | .WIDTH(8), 92 | .WORDS(2048) 93 | ) cpuram_i ( 94 | .clock(clock), 95 | .reset(reset), 96 | .address(segment_addr[10:0]), 97 | .wren(mem_wr&cpuram_en), 98 | .write_data(mem_d), 99 | .read_data(cpuram_read_data) 100 | ); 101 | 102 | generic_ram #( 103 | .WIDTH(8), 104 | .WORDS(2048) 105 | ) vram_i ( 106 | .clock(clock), 107 | .reset(reset), 108 | .address(segment_addr[10:0]), 109 | .wren(mem_wr&vram_en), 110 | .write_data(mem_d), 111 | .read_data(vram_read_data) 112 | ); 113 | 114 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/nes_palette_fceux.txt: -------------------------------------------------------------------------------- 1 | 39ce 2 | 4464 3 | 5400 4 | 4c08 5 | 3811 6 | 0815 7 | 0014 8 | 002f 9 | 00a8 10 | 0100 11 | 0140 12 | 08e0 13 | 2ce3 14 | 0000 15 | 0000 16 | 0000 17 | 5ef7 18 | 75c0 19 | 74e4 20 | 7810 21 | 5c17 22 | 2c1c 23 | 00bb 24 | 0539 25 | 01d1 26 | 0240 27 | 02a0 28 | 1e40 29 | 4600 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7ee7 35 | 7e4b 36 | 7e28 37 | 7dfe 38 | 59df 39 | 31df 40 | 1e7f 41 | 1efe 42 | 0b50 43 | 2769 44 | 4feb 45 | 6fa0 46 | 3def 47 | 0000 48 | 0000 49 | 7fff 50 | 7f95 51 | 7f58 52 | 7f3a 53 | 7f1f 54 | 6f1f 55 | 5aff 56 | 577f 57 | 539f 58 | 53fc 59 | 5fd5 60 | 67f6 61 | 7bf3 62 | 6318 63 | 0000 64 | 0000 65 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/nes_palette_unsaturatedv6.txt: -------------------------------------------------------------------------------- 1 | 35ad 2 | 4060 3 | 4823 4 | 4027 5 | 302b 6 | 140b 7 | 004a 8 | 0068 9 | 00c6 10 | 0121 11 | 0120 12 | 0d00 13 | 2ce0 14 | 0000 15 | 0000 16 | 0000 17 | 5ad6 18 | 6943 19 | 74c9 20 | 748e 21 | 5873 22 | 3074 23 | 0cb4 24 | 0130 25 | 01ac 26 | 0205 27 | 0220 28 | 2200 29 | 49e0 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7eac 35 | 7e32 36 | 7dd7 37 | 7ddc 38 | 65be 39 | 361e 40 | 167b 41 | 02f7 42 | 0350 43 | 1f6b 44 | 3f49 45 | 6729 46 | 294a 47 | 0000 48 | 0000 49 | 7fff 50 | 7f98 51 | 7f5a 52 | 7f3c 53 | 7f3f 54 | 7b3f 55 | 635f 56 | 577e 57 | 4fbd 58 | 4fda 59 | 5bd7 60 | 67d6 61 | 77d6 62 | 5ef7 63 | 0000 64 | 0000 -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/oam_palette.txt: -------------------------------------------------------------------------------- 1 | 0F 2 | 2C 3 | 10 4 | 1C 5 | 0F 6 | 37 7 | 27 8 | 07 9 | 0F 10 | 28 11 | 16 12 | 07 13 | 0F 14 | 28 15 | 0F 16 | 2C 17 | 0F 18 | 0F 19 | 2C 20 | 11 21 | 0F 22 | 0F 23 | 20 24 | 38 25 | 0F 26 | 0F 27 | 15 28 | 27 29 | 0F 30 | 0F 31 | 11 32 | 3C -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 12.000 MHz 9 | * Requested output frequency: 21.500 MHz 10 | * Achieved output frequency: 21.375 MHz 11 | */ 12 | 13 | module pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_PAD #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0000), // DIVR = 0 22 | .DIVF(7'b0111000), // DIVF = 56 23 | .DIVQ(3'b101), // DIVQ = 5 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .PACKAGEPIN(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/games/139.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/games/139.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/games/92.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/games/92.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/games/93-contra.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/games/93-contra.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/games/Beyondtime.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/games/Beyondtime.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/games/smb.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/games/smb.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/nes2bin.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import os, sys, re 4 | 5 | prg_alloc = 64*1024 6 | chr_alloc = 64*1024 7 | 8 | prg_dat = bytearray() 9 | chr_dat = bytearray() 10 | header = None 11 | with open(sys.argv[1], 'rb') as f: 12 | header = f.read(16) 13 | prg_size = header[4] * 16384 14 | chr_size = header[5] * 8192 15 | assert prg_size <= 2 * prg_alloc #PRG can spill into CHR sometimes 16 | prg_dat = f.read(prg_size) 17 | if prg_size > prg_alloc: 18 | assert chr_size == 0 19 | else: 20 | assert chr_size <= chr_alloc 21 | chr_dat = f.read(chr_size) 22 | 23 | prg_dat = bytearray(prg_dat) 24 | chr_dat = bytearray(chr_dat) 25 | 26 | for i in range(prg_size, prg_alloc): 27 | prg_dat.append(prg_dat[i % prg_size]) 28 | if prg_size > prg_alloc: 29 | for i in range(prg_size, 2*prg_alloc): 30 | prg_dat.append(prg_dat[i % prg_size]) 31 | else: 32 | for i in range(chr_size, chr_alloc): 33 | if chr_size == 0: 34 | chr_dat.append(0) 35 | else: 36 | chr_dat.append(chr_dat[i % chr_size]) 37 | 38 | out_flags = 0x0 39 | mapper = (header[6] >> 4) & 0x0F 40 | mapper |= header[7] & 0xF0 41 | out_flags |= mapper 42 | 43 | mirroring = header[6] & 0x01 44 | fourscreen = (header[6] >> 3) & 0x01 45 | 46 | prg_mask = 0 47 | if prg_size <= 16*1024: 48 | prg_mask = 0 49 | elif prg_size <= 32*1024: 50 | prg_mask = 1 51 | elif prg_size <= 64*1024: 52 | prg_mask = 2 53 | elif prg_size <= 128*1024: 54 | prg_mask = 3 55 | elif prg_size <= 256*1024: 56 | prg_mask = 4 57 | elif prg_size <= 512*1024: 58 | prg_mask = 5 59 | elif prg_size <= 1024*1024: 60 | prg_mask = 6 61 | else: 62 | prg_mask = 7 63 | 64 | chr_mask = 0 65 | if chr_size <= 8*1024: 66 | chr_mask = 0 67 | elif chr_size <= 16*1024: 68 | chr_mask = 1 69 | elif chr_size <= 32*1024: 70 | chr_mask = 2 71 | elif chr_size <= 64*1024: 72 | chr_mask = 3 73 | elif chr_size <= 128*1024: 74 | chr_mask = 4 75 | elif chr_size <= 256*1024: 76 | chr_mask = 5 77 | elif chr_size <= 512*1024: 78 | chr_mask = 6 79 | else: 80 | chr_mask = 7 81 | 82 | if chr_size == 0: 83 | has_chr_ram = 1 84 | else: 85 | has_chr_ram = 0 86 | 87 | out_flags |= (prg_mask << 8) 88 | out_flags |= (chr_mask << 11) 89 | out_flags |= (mirroring << 14) 90 | out_flags |= (has_chr_ram << 15) 91 | out_flags |= (fourscreen << 16) 92 | 93 | with open(sys.argv[2], 'wb') as f: 94 | f.write(prg_dat) 95 | f.write(chr_dat) 96 | # Append mapper, size and other flags to end of data 97 | f.write(bytes([(out_flags) & 0xFF, (out_flags >> 8) & 0xFF, (out_flags >> 16) & 0xFF, (out_flags >> 24) & 0xFF])) 98 | f.write(bytearray(256*1024 - (prg_alloc + chr_alloc + 4))) # pad to 256kB total -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/smb.nes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/Refence/up5k-demos/nes/rom/smb.nes -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/rom/游戏说明.txt: -------------------------------------------------------------------------------- 1 | 超时空要塞无敌版 Beyondtime 2 | 93超级魂(中文) 93-contra 3 | 绿色兵团无限人 76 4 | 绿色兵团金身无敌版 92 5 | 赤色要塞无敌版 139 6 | 冒险岛经典版 smb 7 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/scan_double.v: -------------------------------------------------------------------------------- 1 | module scan_double(input clk, 2 | input [14:0] inputpixel, 3 | input reset_frame, 4 | input reset_line, 5 | input [9:0] read_x, 6 | output reg [14:0] outpixel); 7 | reg [1:0] frac; 8 | reg [14:0] linebuf[0:255]; 9 | reg [8:0] write_x; 10 | 11 | always @(posedge clk) 12 | begin 13 | if(reset_line) 14 | begin 15 | frac <= 2'b00; 16 | write_x <= 9'd0; 17 | end else begin 18 | frac <= frac + 1; 19 | if (frac == 2) 20 | if (write_x < 256) 21 | write_x <= write_x + 1; 22 | end 23 | end 24 | 25 | wire write_en = ((frac == 2) && (write_x < 256)) ? 1'b1 : 1'b0; 26 | 27 | always @(posedge clk) 28 | begin 29 | outpixel <= linebuf[read_x[8:1]]; 30 | if(write_en) 31 | linebuf[write_x[7:0]] <= inputpixel; 32 | end 33 | 34 | 35 | 36 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | module sigma_delta_dac( 2 | output reg DACout, //Average Output feeding analog lowpass 3 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 4 | input CLK, 5 | input CEN, 6 | input RESET 7 | ); 8 | 9 | parameter MSBI = 7; 10 | 11 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 12 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 13 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 14 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 15 | 16 | always @ (*) 17 | DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 18 | 19 | always @(*) 20 | DeltaAdder = DACin + DeltaB; 21 | 22 | always @(*) 23 | SigmaAdder = DeltaAdder + SigmaLatch; 24 | 25 | always @(posedge CLK) 26 | begin 27 | SigmaLatch <= SigmaAdder; 28 | DACout <= SigmaLatch[MSBI+2]; 29 | end 30 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/up5k.pcf: -------------------------------------------------------------------------------- 1 | set_io clock_12 35 2 | set_io LED0 26 3 | set_io LED1 27 4 | 5 | set_io VGA_HS 42 6 | set_io VGA_VS 36 7 | set_io VGA_B[3] 44 8 | set_io VGA_B[2] 46 9 | set_io VGA_B[1] 48 10 | set_io VGA_B[0] 3 11 | set_io VGA_G[3] 31 12 | set_io VGA_G[2] 34 13 | set_io VGA_G[1] 38 14 | set_io VGA_G[0] 43 15 | set_io VGA_R[3] 45 16 | set_io VGA_R[2] 47 17 | set_io VGA_R[1] 2 18 | set_io VGA_R[0] 4 19 | 20 | 21 | set_io AUDIO_O 23 22 | set_io joy_strobe 20 23 | set_io joy_clock 19 24 | set_io joy_data 18 25 | 26 | set_io flash_sck 15 27 | set_io flash_csn 16 28 | set_io flash_mosi 14 29 | set_io flash_miso 17 30 | 31 | set_io buttons 21 32 | 33 | #set_io buttons[0] 10 34 | #set_io buttons[1] 20 35 | #set_io buttons[2] 6 36 | #set_io buttons[3] 18 37 | #set_io buttons[4] 4 38 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/up_spram.v: -------------------------------------------------------------------------------- 1 | module up_spram ( 2 | input clk, 3 | input [3:0] wen, 4 | input [21:0] addr, 5 | input [31:0] wdata, 6 | output [31:0] rdata 7 | ); 8 | 9 | wire cs_0, cs_1; 10 | wire [31:0] rdata_0, rdata_1; 11 | 12 | assign cs_0 = !addr[14]; 13 | assign cs_1 = addr[14]; 14 | assign rdata = addr[14] ? rdata_1 : rdata_0; 15 | 16 | 17 | SB_SPRAM256KA ram00 18 | ( 19 | .ADDRESS(addr[13:0]), 20 | .DATAIN(wdata[15:0]), 21 | .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), 22 | .WREN(wen[1]|wen[0]), 23 | .CHIPSELECT(cs_0), 24 | .CLOCK(clk), 25 | .STANDBY(1'b0), 26 | .SLEEP(1'b0), 27 | .POWEROFF(1'b1), 28 | .DATAOUT(rdata_0[15:0]) 29 | ); 30 | 31 | SB_SPRAM256KA ram01 32 | ( 33 | .ADDRESS(addr[13:0]), 34 | .DATAIN(wdata[31:16]), 35 | .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), 36 | .WREN(wen[3]|wen[2]), 37 | .CHIPSELECT(cs_0), 38 | .CLOCK(clk), 39 | .STANDBY(1'b0), 40 | .SLEEP(1'b0), 41 | .POWEROFF(1'b1), 42 | .DATAOUT(rdata_0[31:16]) 43 | ); 44 | 45 | 46 | SB_SPRAM256KA ram10 47 | ( 48 | .ADDRESS(addr[13:0]), 49 | .DATAIN(wdata[15:0]), 50 | .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), 51 | .WREN(wen[1]|wen[0]), 52 | .CHIPSELECT(cs_1), 53 | .CLOCK(clk), 54 | .STANDBY(1'b0), 55 | .SLEEP(1'b0), 56 | .POWEROFF(1'b1), 57 | .DATAOUT(rdata_1[15:0]) 58 | ); 59 | 60 | SB_SPRAM256KA ram11 61 | ( 62 | .ADDRESS(addr[13:0]), 63 | .DATAIN(wdata[31:16]), 64 | .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), 65 | .WREN(wen[3]|wen[2]), 66 | .CHIPSELECT(cs_1), 67 | .CLOCK(clk), 68 | .STANDBY(1'b0), 69 | .SLEEP(1'b0), 70 | .POWEROFF(1'b1), 71 | .DATAOUT(rdata_1[31:16]) 72 | ); 73 | 74 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nes/video.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | 4 | module video( 5 | input clk, 6 | input [5:0] color, 7 | input [8:0] count_h, 8 | input [8:0] count_v, 9 | input mode, 10 | input ypbpr, 11 | input smoothing, 12 | input scanlines, 13 | input overscan, 14 | input palette, 15 | 16 | 17 | output VGA_HS, 18 | output VGA_VS, 19 | output [3:0] VGA_R, 20 | output [3:0] VGA_G, 21 | output [3:0] VGA_B, 22 | 23 | output osd_visible 24 | ); 25 | 26 | reg clk2 = 1'b0; 27 | always @(posedge clk) clk2 <= ~clk2; 28 | wire clkv = mode ? clk2 : clk; 29 | 30 | wire [5:0] R_out, G_out, B_out; 31 | 32 | 33 | 34 | // NTSC UnsaturatedV6 palette 35 | //see: http://www.firebrandx.com/nespalette.html 36 | /*reg [15:0] pal_unsat_lut[0:63]; 37 | initial $readmemh("nes_palette_unsaturatedv6.txt", pal_unsat_lut);*/ 38 | 39 | // FCEUX palette 40 | reg [15:0] pal_fcelut[0:63]; 41 | initial $readmemh("nes_palette_fceux.txt", pal_fcelut); 42 | 43 | wire [14:0] pixel = pal_fcelut[color][14:0]; 44 | 45 | // Horizontal and vertical counters 46 | reg [9:0] h, v; 47 | wire hpicture = (h < 512); // 512 lines of picture 48 | wire hend = (h == 681); // End of line, 682 pixels. 49 | wire vpicture = (v < (480 >> mode)); // 480 lines of picture 50 | wire vend = (v == (523 >> mode)); // End of picture, 524 lines. (Should really be 525 according to NTSC spec) 51 | 52 | wire [14:0] doubler_pixel; 53 | wire doubler_sync; 54 | 55 | scan_double doubler(clk, pixel, 56 | count_v[8], // reset_frame 57 | (count_h[8:3] == 42), // reset_line 58 | {v[0], h[9] ? 9'd0 : h[8:0] + 9'd1}, // 0-511 for line 1, or 512-1023 for line 2. 59 | doubler_pixel); // pixel is outputted 60 | 61 | 62 | reg [8:0] old_count_v; 63 | wire sync_frame = (old_count_v == 9'd511) && (count_v == 9'd0); 64 | 65 | assign doubler_sync = sync_frame; 66 | 67 | always @(posedge clkv) begin 68 | h <= (hend || (mode ? sync_frame : doubler_sync)) ? 10'd0 : h + 10'd1; 69 | if(mode ? sync_frame : doubler_sync) v <= 0; 70 | else if (hend) v <= vend ? 10'd0 : v + 10'd1; 71 | 72 | old_count_v <= count_v; 73 | end 74 | 75 | wire [14:0] pixel_v = (!hpicture || !vpicture) ? 15'd0 : mode ? pixel : doubler_pixel; 76 | wire darker = !mode && v[0] && scanlines; 77 | 78 | // display overlay to hide overscan area 79 | // based on Mario3, DoubleDragon2, Shadow of the Ninja 80 | wire ol = overscan && ( (h > 512-16) || 81 | (h < 20) || 82 | (v < (mode ? 6 : 12)) || 83 | (v > (mode ? 240-10 : 480-20)) 84 | ); 85 | 86 | wire [4:0] vga_r = ol ? {4'b0, pixel_v[4:4]} : (darker ? {1'b0, pixel_v[4:1]} : pixel_v[4:0]); 87 | wire [4:0] vga_g = ol ? {4'b0, pixel_v[9:9]} : (darker ? {1'b0, pixel_v[9:6]} : pixel_v[9:5]); 88 | wire [4:0] vga_b = ol ? {4'b0, pixel_v[14:14]} : (darker ? {1'b0, pixel_v[14:11]} : pixel_v[14:10]); 89 | wire sync_h = ((h >= (512 + 23 + (mode ? 18 : 35))) && (h < (512 + 23 + (mode ? 18 : 35) + 82))); 90 | wire sync_v = ((v >= (mode ? 240 + 5 : 480 + 10)) && (v < (mode ? 240 + 14 : 480 + 12))); 91 | 92 | 93 | assign VGA_HS = !sync_h; 94 | assign VGA_VS = !sync_v; 95 | assign VGA_R = vga_r[4:1]; 96 | assign VGA_G = vga_g[4:1]; 97 | assign VGA_B = vga_b[4:1]; 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/.gitignore: -------------------------------------------------------------------------------- 1 | *.asc 2 | *.bin 3 | *.blif 4 | *.nes 5 | *.exp 6 | *.vvp 7 | *.blog 8 | *.log 9 | *.vlog 10 | *.json 11 | *.rpt 12 | 13 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = nes 2 | 3 | TOP = NES_ice40 4 | PIN_DEF = up5k.pcf 5 | DEVICE = up5k 6 | ADD_SRC = $(wildcard *.v) 7 | FREQ = 8 8 | #USE_ARACHNEPNR = Y 9 | 10 | include main.mk 11 | 12 | GAMES = $(sort $(wildcard rom/game*.nes)) 13 | IMAGES = $(GAMES:.nes=.bin) 14 | 15 | rom/games.bin: $(IMAGES) 16 | cat $^ > $@ 17 | 18 | up5kprog_game: rom/games.bin 19 | iceprog -o 1024k rom/games.bin 20 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/Makefile.old: -------------------------------------------------------------------------------- 1 | ARACHNE = arachne-pnr 2 | ARACHNE_ARGS = -s 2 3 | ICEPACK = icepack 4 | ICETIME = icetime 5 | ICEPROG = iceprog 6 | SOURCES = $(wildcard *.v) 7 | # ---- iCE40 UP5k Breakout Board ---- 8 | 9 | 10 | up5knes.blif: $(SOURCES) 11 | yosys -ql up5knes.log -p 'synth_ice40 -top NES_ice40 -blif up5knes.blif' $^ 12 | 13 | up5knes_syn.v: up5knes.blif 14 | yosys -p 'read_blif -wideports up5knes.blif; write_verilog up5knes_syn.v' 15 | 16 | up5knes.asc: up5k.pcf up5knes.blif 17 | $(ARACHNE) -d 5k $(ARACHNE_ARGS) -o up5knes.asc -p up5k.pcf up5knes.blif 18 | 19 | up5knes.bin: up5knes.asc 20 | # $(ICETIME) -d up5k -c 12 -mtr up5knes.rpt up5knes.asc 21 | $(ICEPACK) up5knes.asc up5knes.bin 22 | 23 | rom/game%.bin: rom/game%.nes 24 | rom/nes2bin.py $^ $@ 25 | 26 | GAMES = $(sort $(wildcard rom/game*.nes)) 27 | IMAGES = $(GAMES:.nes=.bin) 28 | 29 | rom/games.bin: $(IMAGES) 30 | cat $^ > $@ 31 | 32 | up5kprog: up5knes.bin 33 | $(ICEPROG) up5knes.bin 34 | 35 | 36 | up5kprog_game: rom/games.bin 37 | $(ICEPROG) -o 1024k rom/games.bin 38 | 39 | 40 | 41 | # ---- Clean ---- 42 | 43 | clean: 44 | rm -f up5knes.blif up5knes.log up5knes.asc up5knes.rpt up5knes.bin 45 | 46 | .PHONY: up5kprog up5kprog_fw clean 47 | 48 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/README.md: -------------------------------------------------------------------------------- 1 | # Port of the MIST NES core to ice40 2 | 3 | This port of the NES MIST core is currently designed for the upduino 4 | board, with a VGA DAC and connection to a NES controller added. 5 | 6 | Currently it can run any NROM, MMC1, UNROM or CNROM game requiring 7 | either less than 64kB PRG and CHR ROM, or less than 128kB PRG ROM and 8 | 8kB CHR RAM. Sound is a tiny bit big for the 5k UltraPlus so is not 9 | included. By removing all the mappers - and some registers needed for 10 | reliable performance - you can just about get it to fit but it uses 11 | every single PLB in the device. 12 | 13 | It would be much better suited to a 8k board with more external RAM. 14 | Then you would have room for bigger games (up to the size of the board's 15 | RAM), more mapper support (e.g. MMC3) and sound. The only changes needed 16 | would be changing cart_mem to use external RAM instead of UltraPlus 17 | SPRAM, and creating a new Makefile and pcf file. 18 | 19 | 'Streaming' games from SQI flash might be just about doable from a 20 | timing point of view but I don't think there are enough PLBs available 21 | at present on the 5k, and it would probably be quite a bit of work for 22 | it to work reliably. 23 | 24 | I'll probably port this to my icoBoard with a VGA PMOD at some point, 25 | which could end up being a very nice platform for this. 26 | 27 | Credit to the original developer of the NES core, Ludvig Strigeus for 28 | making such an awesome project! Like the original core this is licensed 29 | under the GNU GPL. 30 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/compat.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | module MUXCY(output O, input CI, input DI, input S); 4 | assign O = S ? CI : DI; 5 | endmodule 6 | module MUXCY_L(output LO, input CI, input DI, input S); 7 | assign LO = S ? CI : DI; 8 | endmodule 9 | module MUXCY_D(output LO, output O, input CI, input DI, input S); 10 | assign LO = S ? CI : DI; 11 | assign O = LO; 12 | endmodule 13 | module XORCY(output O, input CI, input LI); 14 | assign O = CI ^ LI; 15 | endmodule 16 | module XOR2(output O, input I0, input I1); 17 | assign O = I0 ^ I1; 18 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/flashmem.v: -------------------------------------------------------------------------------- 1 | // SPI flash memory interface, taken from the icosoc project 2 | 3 | module icosoc_flashmem ( 4 | input clk, reset, 5 | 6 | input valid, 7 | output reg ready, 8 | input [23:0] addr, 9 | output reg [31:0] rdata, 10 | 11 | output reg spi_cs, 12 | output reg spi_sclk, 13 | output reg spi_mosi, 14 | input spi_miso 15 | ); 16 | reg [7:0] buffer; 17 | reg [3:0] xfer_cnt; 18 | reg [3:0] state; 19 | 20 | always @(posedge clk) begin 21 | ready <= 0; 22 | if (reset || !valid || ready) begin 23 | spi_cs <= 1; 24 | spi_sclk <= 1; 25 | xfer_cnt <= 0; 26 | state <= 0; 27 | end else begin 28 | spi_cs <= 0; 29 | if (xfer_cnt) begin 30 | if (spi_sclk) begin 31 | spi_sclk <= 0; 32 | spi_mosi <= buffer[7]; 33 | end else begin 34 | spi_sclk <= 1; 35 | buffer <= {buffer, spi_miso}; 36 | xfer_cnt <= xfer_cnt - 1; 37 | end 38 | end else 39 | case (state) 40 | 0: begin 41 | buffer <= 'h03; 42 | xfer_cnt <= 8; 43 | state <= 1; 44 | end 45 | 1: begin 46 | buffer <= addr[23:16]; 47 | xfer_cnt <= 8; 48 | state <= 2; 49 | end 50 | 2: begin 51 | buffer <= addr[15:8]; 52 | xfer_cnt <= 8; 53 | state <= 3; 54 | end 55 | 3: begin 56 | buffer <= addr[7:0]; 57 | xfer_cnt <= 8; 58 | state <= 4; 59 | end 60 | 4: begin 61 | xfer_cnt <= 8; 62 | state <= 5; 63 | end 64 | 5: begin 65 | rdata[7:0] <= buffer; 66 | xfer_cnt <= 8; 67 | state <= 6; 68 | end 69 | 6: begin 70 | rdata[15:8] <= buffer; 71 | xfer_cnt <= 8; 72 | state <= 7; 73 | end 74 | 7: begin 75 | rdata[23:16] <= buffer; 76 | xfer_cnt <= 8; 77 | state <= 8; 78 | end 79 | 8: begin 80 | rdata[31:24] <= buffer; 81 | ready <= 1; 82 | end 83 | endcase 84 | end 85 | end 86 | endmodule 87 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/generic_ram.v: -------------------------------------------------------------------------------- 1 | // Simple, platform-agnostic single-ported RAM 2 | 3 | module generic_ram(clock, reset, address, wren, write_data, read_data); 4 | 5 | parameter integer WIDTH = 8; 6 | parameter integer WORDS = 2048; 7 | localparam ADDR_BITS = $clog2(WORDS-1); 8 | 9 | input clock; 10 | input reset; 11 | input [ADDR_BITS-1:0] address; 12 | input wren; 13 | input [WIDTH-1:0] write_data; 14 | output reg [WIDTH-1:0] read_data; 15 | 16 | reg [WIDTH-1:0] mem[0:WORDS-1]; 17 | 18 | reg [ADDR_BITS-1:0] a_prereg; 19 | reg [WIDTH-1:0] d_prereg; 20 | reg wren_prereg; 21 | 22 | always @(posedge clock) begin 23 | if (reset == 1'b1) begin 24 | wren_prereg <= 0; 25 | a_prereg <= 0; 26 | d_prereg <= 0; 27 | end else begin 28 | wren_prereg <= wren; 29 | a_prereg <= address; 30 | d_prereg <= write_data; 31 | end 32 | 33 | 34 | read_data <= mem[a_prereg]; 35 | if (wren_prereg) mem[a_prereg] <= d_prereg; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -blif $@' $(ADD_SRC) 6 | 7 | %.json: $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -json $@' $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --placer heap --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack -s $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | iceprog $< 42 | 43 | sudo-prog: $(PROJ).bin 44 | @echo 'Executing prog as root!!!' 45 | sudo iceprog $< 46 | 47 | clean: 48 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 49 | 50 | .SECONDARY: 51 | .PHONY: all prog clean 52 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/main_mem.v: -------------------------------------------------------------------------------- 1 | /* 2 | This memory device contains both system memory 3 | and cartridge data. 4 | */ 5 | 6 | module main_mem( 7 | input clock, reset, 8 | 9 | input reload, 10 | input [3:0] index, 11 | 12 | output load_done, 13 | output [31:0] flags_out, 14 | //NES interface 15 | input [21:0] mem_addr, 16 | input mem_rd_cpu, mem_rd_ppu, 17 | input mem_wr, 18 | output reg [7:0] mem_q_cpu, mem_q_ppu, 19 | input [7:0] mem_d, 20 | 21 | //Flash load interface 22 | output flash_csn, 23 | output flash_sck, 24 | output flash_mosi, 25 | input flash_miso); 26 | 27 | // Compress the 4MB logical address space to our limited available space 28 | // In the future a more sophisticated memory system will keep games in 29 | // SQI flash to expand the space available 30 | 31 | // Also may consider changing this based on mapper to make the most 32 | // of limited memory 33 | 34 | wire prgrom_en, chrrom_en, vram_en, cpuram_en, cartram_en; 35 | 36 | // Mapping 37 | // 0... : PRG : lower 64kB SPRAM 38 | // 10.. : CHR : upper 64kB SPRAM 39 | // 1100 : CHR-VRAM : dedicated 2kB RAM 40 | // 1110 : CPU-RAM : dedicated 2kB RAM 41 | // 1111 : CART-RAM : dedicated 2kB RAM 42 | 43 | assign prgrom_en = !mem_addr[21]; 44 | assign chrrom_en = mem_addr[21] & !mem_addr[20]; 45 | assign vram_en = mem_addr[21] & mem_addr[20] & !mem_addr[19] & !mem_addr[18]; 46 | assign cpuram_en = mem_addr[21] & mem_addr[20] & mem_addr[19] & !mem_addr[18]; 47 | assign cartram_en = mem_addr[21] & mem_addr[20] & mem_addr[19] & mem_addr[18]; 48 | 49 | wire [20:0] segment_addr = prgrom_en ? mem_addr[20:0] : (chrrom_en ? {1'b0, mem_addr[19:0]} : {3'b0, mem_addr[17:0]}); 50 | 51 | wire [7:0] cpuram_read_data, vram_read_data, cart_read_data; 52 | wire rden = mem_rd_cpu | mem_rd_ppu; 53 | 54 | always@(posedge clock or posedge reset) 55 | begin 56 | if (reset == 1'b1) begin 57 | mem_q_cpu <= 0; 58 | mem_q_ppu <= 0; 59 | end else begin 60 | if (mem_rd_cpu) 61 | mem_q_cpu <= cpuram_en ? cpuram_read_data : (vram_en ? vram_read_data : cart_read_data); 62 | if (mem_rd_ppu) 63 | mem_q_ppu <= cpuram_en ? cpuram_read_data : (vram_en ? vram_read_data : cart_read_data); 64 | end; 65 | end 66 | 67 | cart_mem cart_i ( 68 | .clock(clock), 69 | .reset(reset), 70 | .reload(reload), 71 | .index(index), 72 | .cart_ready(load_done), 73 | .flags_out(flags_out), 74 | .address(segment_addr), 75 | .prg_sel(prgrom_en), 76 | .chr_sel(chrrom_en), 77 | .ram_sel(cartram_en), 78 | .rden(rden), 79 | .wren(mem_wr), 80 | .write_data(mem_d), 81 | .read_data(cart_read_data), 82 | 83 | //Flash load interface 84 | .flash_csn(flash_csn), 85 | .flash_sck(flash_sck), 86 | .flash_mosi(flash_mosi), 87 | .flash_miso(flash_miso) 88 | ); 89 | 90 | generic_ram #( 91 | .WIDTH(8), 92 | .WORDS(2048) 93 | ) cpuram_i ( 94 | .clock(clock), 95 | .reset(reset), 96 | .address(segment_addr[10:0]), 97 | .wren(mem_wr&cpuram_en), 98 | .write_data(mem_d), 99 | .read_data(cpuram_read_data) 100 | ); 101 | 102 | generic_ram #( 103 | .WIDTH(8), 104 | .WORDS(2048) 105 | ) vram_i ( 106 | .clock(clock), 107 | .reset(reset), 108 | .address(segment_addr[10:0]), 109 | .wren(mem_wr&vram_en), 110 | .write_data(mem_d), 111 | .read_data(vram_read_data) 112 | ); 113 | 114 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/nes_palette_fceux.txt: -------------------------------------------------------------------------------- 1 | 39ce 2 | 4464 3 | 5400 4 | 4c08 5 | 3811 6 | 0815 7 | 0014 8 | 002f 9 | 00a8 10 | 0100 11 | 0140 12 | 08e0 13 | 2ce3 14 | 0000 15 | 0000 16 | 0000 17 | 5ef7 18 | 75c0 19 | 74e4 20 | 7810 21 | 5c17 22 | 2c1c 23 | 00bb 24 | 0539 25 | 01d1 26 | 0240 27 | 02a0 28 | 1e40 29 | 4600 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7ee7 35 | 7e4b 36 | 7e28 37 | 7dfe 38 | 59df 39 | 31df 40 | 1e7f 41 | 1efe 42 | 0b50 43 | 2769 44 | 4feb 45 | 6fa0 46 | 3def 47 | 0000 48 | 0000 49 | 7fff 50 | 7f95 51 | 7f58 52 | 7f3a 53 | 7f1f 54 | 6f1f 55 | 5aff 56 | 577f 57 | 539f 58 | 53fc 59 | 5fd5 60 | 67f6 61 | 7bf3 62 | 6318 63 | 0000 64 | 0000 65 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/nes_palette_unsaturatedv6.txt: -------------------------------------------------------------------------------- 1 | 35ad 2 | 4060 3 | 4823 4 | 4027 5 | 302b 6 | 140b 7 | 004a 8 | 0068 9 | 00c6 10 | 0121 11 | 0120 12 | 0d00 13 | 2ce0 14 | 0000 15 | 0000 16 | 0000 17 | 5ad6 18 | 6943 19 | 74c9 20 | 748e 21 | 5873 22 | 3074 23 | 0cb4 24 | 0130 25 | 01ac 26 | 0205 27 | 0220 28 | 2200 29 | 49e0 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7eac 35 | 7e32 36 | 7dd7 37 | 7ddc 38 | 65be 39 | 361e 40 | 167b 41 | 02f7 42 | 0350 43 | 1f6b 44 | 3f49 45 | 6729 46 | 294a 47 | 0000 48 | 0000 49 | 7fff 50 | 7f98 51 | 7f5a 52 | 7f3c 53 | 7f3f 54 | 7b3f 55 | 635f 56 | 577e 57 | 4fbd 58 | 4fda 59 | 5bd7 60 | 67d6 61 | 77d6 62 | 5ef7 63 | 0000 64 | 0000 -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/oam_palette.txt: -------------------------------------------------------------------------------- 1 | 0F 2 | 2C 3 | 10 4 | 1C 5 | 0F 6 | 37 7 | 27 8 | 07 9 | 0F 10 | 28 11 | 16 12 | 07 13 | 0F 14 | 28 15 | 0F 16 | 2C 17 | 0F 18 | 0F 19 | 2C 20 | 11 21 | 0F 22 | 0F 23 | 20 24 | 38 25 | 0F 26 | 0F 27 | 15 28 | 27 29 | 0F 30 | 0F 31 | 11 32 | 3C -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 12.000 MHz 9 | * Requested output frequency: 21.500 MHz 10 | * Achieved output frequency: 21.375 MHz 11 | */ 12 | 13 | module pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_PAD #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0000), // DIVR = 0 22 | .DIVF(7'b0111000), // DIVF = 56 23 | .DIVQ(3'b101), // DIVQ = 5 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .PACKAGEPIN(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/rom/nes2bin.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import os, sys, re 4 | 5 | prg_alloc = 64*1024 6 | chr_alloc = 64*1024 7 | 8 | prg_dat = bytearray() 9 | chr_dat = bytearray() 10 | header = None 11 | with open(sys.argv[1], 'rb') as f: 12 | header = f.read(16) 13 | prg_size = header[4] * 16384 14 | print(prg_size) 15 | chr_size = header[5] * 8192 16 | print(chr_size) 17 | assert prg_size <= 2 * prg_alloc #PRG can spill into CHR sometimes 18 | prg_dat = f.read(prg_size) 19 | if prg_size > prg_alloc: 20 | assert chr_size == 0 21 | else: 22 | assert chr_size <= chr_alloc 23 | chr_dat = f.read(chr_size) 24 | 25 | prg_dat = bytearray(prg_dat) 26 | chr_dat = bytearray(chr_dat) 27 | 28 | for i in range(prg_size, prg_alloc): 29 | prg_dat.append(prg_dat[i % prg_size]) 30 | if prg_size > prg_alloc: 31 | for i in range(prg_size, 2*prg_alloc): 32 | prg_dat.append(prg_dat[i % prg_size]) 33 | else: 34 | for i in range(chr_size, chr_alloc): 35 | if chr_size == 0: 36 | chr_dat.append(0) 37 | else: 38 | chr_dat.append(chr_dat[i % chr_size]) 39 | 40 | out_flags = 0x0 41 | mapper = (header[6] >> 4) & 0x0F 42 | mapper |= header[7] & 0xF0 43 | out_flags |= mapper 44 | 45 | mirroring = header[6] & 0x01 46 | fourscreen = (header[6] >> 3) & 0x01 47 | 48 | prg_mask = 0 49 | if prg_size <= 16*1024: 50 | prg_mask = 0 51 | elif prg_size <= 32*1024: 52 | prg_mask = 1 53 | elif prg_size <= 64*1024: 54 | prg_mask = 2 55 | elif prg_size <= 128*1024: 56 | prg_mask = 3 57 | elif prg_size <= 256*1024: 58 | prg_mask = 4 59 | elif prg_size <= 512*1024: 60 | prg_mask = 5 61 | elif prg_size <= 1024*1024: 62 | prg_mask = 6 63 | else: 64 | prg_mask = 7 65 | 66 | chr_mask = 0 67 | if chr_size <= 8*1024: 68 | chr_mask = 0 69 | elif chr_size <= 16*1024: 70 | chr_mask = 1 71 | elif chr_size <= 32*1024: 72 | chr_mask = 2 73 | elif chr_size <= 64*1024: 74 | chr_mask = 3 75 | elif chr_size <= 128*1024: 76 | chr_mask = 4 77 | elif chr_size <= 256*1024: 78 | chr_mask = 5 79 | elif chr_size <= 512*1024: 80 | chr_mask = 6 81 | else: 82 | chr_mask = 7 83 | 84 | if chr_size == 0: 85 | has_chr_ram = 1 86 | else: 87 | has_chr_ram = 0 88 | 89 | out_flags |= (prg_mask << 8) 90 | out_flags |= (chr_mask << 11) 91 | out_flags |= (mirroring << 14) 92 | out_flags |= (has_chr_ram << 15) 93 | out_flags |= (fourscreen << 16) 94 | 95 | with open(sys.argv[2], 'wb') as f: 96 | f.write(prg_dat) 97 | f.write(chr_dat) 98 | # Append mapper, size and other flags to end of data 99 | f.write(bytes([(out_flags) & 0xFF, (out_flags >> 8) & 0xFF, (out_flags >> 16) & 0xFF, (out_flags >> 24) & 0xFF])) 100 | f.write(bytearray(256*1024 - (prg_alloc + chr_alloc + 4))) # pad to 256kB total 101 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/scan_double.v: -------------------------------------------------------------------------------- 1 | module scan_double(input clk, 2 | input [14:0] inputpixel, 3 | input reset_frame, 4 | input reset_line, 5 | input [9:0] read_x, 6 | output reg [14:0] outpixel); 7 | reg [1:0] frac; 8 | reg [14:0] linebuf[0:255]; 9 | reg [8:0] write_x; 10 | 11 | always @(posedge clk) 12 | begin 13 | if(reset_line) 14 | begin 15 | frac <= 2'b00; 16 | write_x <= 9'd0; 17 | end else begin 18 | frac <= frac + 1; 19 | if (frac == 2) 20 | if (write_x < 256) 21 | write_x <= write_x + 1; 22 | end 23 | end 24 | 25 | wire write_en = ((frac == 2) && (write_x < 256)) ? 1'b1 : 1'b0; 26 | 27 | always @(posedge clk) 28 | begin 29 | outpixel <= linebuf[read_x[8:1]]; 30 | if(write_en) 31 | linebuf[write_x[7:0]] <= inputpixel; 32 | end 33 | 34 | 35 | 36 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | module sigma_delta_dac( 2 | output reg DACout, //Average Output feeding analog lowpass 3 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 4 | input CLK, 5 | input CEN, 6 | input RESET 7 | ); 8 | 9 | parameter MSBI = 7; 10 | 11 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 12 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 13 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 14 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 15 | 16 | always @ (*) 17 | DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 18 | 19 | always @(*) 20 | DeltaAdder = DACin + DeltaB; 21 | 22 | always @(*) 23 | SigmaAdder = DeltaAdder + SigmaLatch; 24 | 25 | always @(posedge CLK) 26 | begin 27 | SigmaLatch <= SigmaAdder; 28 | DACout <= SigmaLatch[MSBI+2]; 29 | end 30 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/up5k.pcf: -------------------------------------------------------------------------------- 1 | set_io clock_12 35 2 | set_io LED0 37 3 | set_io LED1 11 4 | 5 | set_io VGA_CK 38 6 | set_io VGA_DE 32 7 | set_io VGA_HS 31 8 | set_io VGA_VS 28 9 | set_io VGA_B[3] 43 10 | set_io VGA_B[2] 42 11 | set_io VGA_B[1] 36 12 | set_io VGA_B[0] 34 13 | set_io VGA_G[3] 47 14 | set_io VGA_G[2] 46 15 | set_io VGA_G[1] 45 16 | set_io VGA_G[0] 44 17 | set_io VGA_R[3] 4 18 | set_io VGA_R[2] 3 19 | set_io VGA_R[1] 2 20 | set_io VGA_R[0] 48 21 | 22 | set_io -nowarn AUDIO_O 19 23 | set_io joy_strobe 25 24 | set_io joy_clock 27 25 | set_io joy_data 21 26 | 27 | set_io flash_sck 15 28 | set_io flash_csn 16 29 | set_io flash_mosi 14 30 | set_io flash_miso 17 31 | 32 | set_io buttons 10 33 | 34 | #set_io buttons[0] 10 35 | #set_io buttons[1] 20 36 | #set_io buttons[2] 19 37 | #set_io buttons[3] 18 38 | #set_io buttons[4] 32 39 | 40 | #set_io leds[0] 27 41 | #set_io leds[1] 25 42 | #set_io leds[2] 21 43 | #set_io leds[3] 19 44 | #set_io leds[4] 26 45 | #set_io leds[5] 23 46 | #set_io leds[6] 20 47 | #set_io leds[7] 18 48 | 49 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/up_spram.v: -------------------------------------------------------------------------------- 1 | module up_spram ( 2 | input clk, 3 | input [3:0] wen, 4 | input [21:0] addr, 5 | input [31:0] wdata, 6 | output [31:0] rdata 7 | ); 8 | 9 | wire cs_0, cs_1; 10 | wire [31:0] rdata_0, rdata_1; 11 | 12 | assign cs_0 = !addr[14]; 13 | assign cs_1 = addr[14]; 14 | assign rdata = addr[14] ? rdata_1 : rdata_0; 15 | 16 | 17 | SB_SPRAM256KA ram00 18 | ( 19 | .ADDRESS(addr[13:0]), 20 | .DATAIN(wdata[15:0]), 21 | .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), 22 | .WREN(wen[1]|wen[0]), 23 | .CHIPSELECT(cs_0), 24 | .CLOCK(clk), 25 | .STANDBY(1'b0), 26 | .SLEEP(1'b0), 27 | .POWEROFF(1'b1), 28 | .DATAOUT(rdata_0[15:0]) 29 | ); 30 | 31 | SB_SPRAM256KA ram01 32 | ( 33 | .ADDRESS(addr[13:0]), 34 | .DATAIN(wdata[31:16]), 35 | .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), 36 | .WREN(wen[3]|wen[2]), 37 | .CHIPSELECT(cs_0), 38 | .CLOCK(clk), 39 | .STANDBY(1'b0), 40 | .SLEEP(1'b0), 41 | .POWEROFF(1'b1), 42 | .DATAOUT(rdata_0[31:16]) 43 | ); 44 | 45 | 46 | SB_SPRAM256KA ram10 47 | ( 48 | .ADDRESS(addr[13:0]), 49 | .DATAIN(wdata[15:0]), 50 | .MASKWREN({wen[1], wen[1], wen[0], wen[0]}), 51 | .WREN(wen[1]|wen[0]), 52 | .CHIPSELECT(cs_1), 53 | .CLOCK(clk), 54 | .STANDBY(1'b0), 55 | .SLEEP(1'b0), 56 | .POWEROFF(1'b1), 57 | .DATAOUT(rdata_1[15:0]) 58 | ); 59 | 60 | SB_SPRAM256KA ram11 61 | ( 62 | .ADDRESS(addr[13:0]), 63 | .DATAIN(wdata[31:16]), 64 | .MASKWREN({wen[3], wen[3], wen[2], wen[2]}), 65 | .WREN(wen[3]|wen[2]), 66 | .CHIPSELECT(cs_1), 67 | .CLOCK(clk), 68 | .STANDBY(1'b0), 69 | .SLEEP(1'b0), 70 | .POWEROFF(1'b1), 71 | .DATAOUT(rdata_1[31:16]) 72 | ); 73 | 74 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/neshdmi/video.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | 4 | module video( 5 | input clk, 6 | input [5:0] color, 7 | input [8:0] count_h, 8 | input [8:0] count_v, 9 | input mode, 10 | input ypbpr, 11 | input smoothing, 12 | input scanlines, 13 | input overscan, 14 | input palette, 15 | 16 | 17 | output VGA_HS, 18 | output VGA_VS, 19 | output [3:0] VGA_R, 20 | output [3:0] VGA_G, 21 | output [3:0] VGA_B, 22 | 23 | output active, 24 | 25 | output osd_visible 26 | ); 27 | 28 | reg clk2 = 1'b0; 29 | always @(posedge clk) clk2 <= ~clk2; 30 | wire clkv = mode ? clk2 : clk; 31 | 32 | wire [5:0] R_out, G_out, B_out; 33 | 34 | 35 | 36 | // NTSC UnsaturatedV6 palette 37 | //see: http://www.firebrandx.com/nespalette.html 38 | /*reg [15:0] pal_unsat_lut[0:63]; 39 | initial $readmemh("nes_palette_unsaturatedv6.txt", pal_unsat_lut);*/ 40 | 41 | // FCEUX palette 42 | reg [15:0] pal_fcelut[0:63]; 43 | initial $readmemh("nes_palette_fceux.txt", pal_fcelut); 44 | 45 | wire [14:0] pixel = pal_fcelut[color][14:0]; 46 | 47 | // Horizontal and vertical counters 48 | reg [9:0] h, v; 49 | wire hpicture = (h < 512); // 512 lines of picture 50 | wire hend = (h == 681); // End of line, 682 pixels. 51 | wire vpicture = (v < (480 >> mode)); // 480 lines of picture 52 | wire vend = (v == (523 >> mode)); // End of picture, 524 lines. (Should really be 525 according to NTSC spec) 53 | 54 | wire [14:0] doubler_pixel; 55 | wire doubler_sync; 56 | 57 | scan_double doubler(clk, pixel, 58 | count_v[8], // reset_frame 59 | (count_h[8:3] == 42), // reset_line 60 | {v[0], h[9] ? 9'd0 : h[8:0] + 9'd1}, // 0-511 for line 1, or 512-1023 for line 2. 61 | doubler_pixel); // pixel is outputted 62 | 63 | assign active = h < 512 && v < 480; 64 | 65 | reg [8:0] old_count_v; 66 | wire sync_frame = (old_count_v == 9'd511) && (count_v == 9'd0); 67 | 68 | assign doubler_sync = sync_frame; 69 | 70 | always @(posedge clkv) begin 71 | h <= (hend || (mode ? sync_frame : doubler_sync)) ? 10'd0 : h + 10'd1; 72 | if(mode ? sync_frame : doubler_sync) v <= 0; 73 | else if (hend) v <= vend ? 10'd0 : v + 10'd1; 74 | 75 | old_count_v <= count_v; 76 | end 77 | 78 | wire [14:0] pixel_v = (!hpicture || !vpicture) ? 15'd0 : mode ? pixel : doubler_pixel; 79 | wire darker = !mode && v[0] && scanlines; 80 | 81 | // display overlay to hide overscan area 82 | // based on Mario3, DoubleDragon2, Shadow of the Ninja 83 | wire ol = overscan && ( (h > 512-16) || 84 | (h < 20) || 85 | (v < (mode ? 6 : 12)) || 86 | (v > (mode ? 240-10 : 480-20)) 87 | ); 88 | 89 | wire [4:0] vga_r = ol ? {4'b0, pixel_v[4:4]} : (darker ? {1'b0, pixel_v[4:1]} : pixel_v[4:0]); 90 | wire [4:0] vga_g = ol ? {4'b0, pixel_v[9:9]} : (darker ? {1'b0, pixel_v[9:6]} : pixel_v[9:5]); 91 | wire [4:0] vga_b = ol ? {4'b0, pixel_v[14:14]} : (darker ? {1'b0, pixel_v[14:11]} : pixel_v[14:10]); 92 | wire sync_h = ((h >= (512 + 23 + (mode ? 18 : 35))) && (h < (512 + 23 + (mode ? 18 : 35) + 82))); 93 | wire sync_v = ((v >= (mode ? 240 + 5 : 480 + 10)) && (v < (mode ? 240 + 14 : 480 + 12))); 94 | 95 | 96 | assign VGA_HS = !sync_h; 97 | assign VGA_VS = !sync_v; 98 | assign VGA_R = vga_r[4:1]; 99 | assign VGA_G = vga_g[4:1]; 100 | assign VGA_B = vga_b[4:1]; 101 | 102 | endmodule 103 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/.gitignore: -------------------------------------------------------------------------------- 1 | *.asc 2 | *.bin 3 | *.blif 4 | *.nes 5 | *.exp 6 | *.vvp 7 | *.blog 8 | *.log 9 | *.vlog 10 | *.json 11 | *.rpt 12 | 13 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = nes 2 | 3 | TOP = NES_ice40 4 | PIN_DEF = blackicemx.pcf 5 | DEVICE = hx8k 6 | PACKAGE = tq144:4k 7 | ADD_SRC = $(wildcard *.v) 8 | FREQ = 8 9 | #USE_ARACHNEPNR = Y 10 | 11 | include main.mk 12 | 13 | GAMES = $(sort $(wildcard rom/game*.nes)) 14 | IMAGES = $(GAMES:.nes=.bin) 15 | 16 | rom/games.bin: $(IMAGES) 17 | cat $^ > $@ 18 | 19 | up5kprog_game: rom/games.bin 20 | iceprog -o 1024k rom/games.bin 21 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/README.md: -------------------------------------------------------------------------------- 1 | # Port of the MIST NES core to ice40 2 | 3 | This port of the NES MIST core is currently designed for the upduino 4 | board, with a VGA DAC and connection to a NES controller added. 5 | 6 | Currently it can run any NROM, MMC1, UNROM or CNROM game requiring 7 | either less than 64kB PRG and CHR ROM, or less than 128kB PRG ROM and 8 | 8kB CHR RAM. Sound is a tiny bit big for the 5k UltraPlus so is not 9 | included. By removing all the mappers - and some registers needed for 10 | reliable performance - you can just about get it to fit but it uses 11 | every single PLB in the device. 12 | 13 | It would be much better suited to a 8k board with more external RAM. 14 | Then you would have room for bigger games (up to the size of the board's 15 | RAM), more mapper support (e.g. MMC3) and sound. The only changes needed 16 | would be changing cart_mem to use external RAM instead of UltraPlus 17 | SPRAM, and creating a new Makefile and pcf file. 18 | 19 | 'Streaming' games from SQI flash might be just about doable from a 20 | timing point of view but I don't think there are enough PLBs available 21 | at present on the 5k, and it would probably be quite a bit of work for 22 | it to work reliably. 23 | 24 | I'll probably port this to my icoBoard with a VGA PMOD at some point, 25 | which could end up being a very nice platform for this. 26 | 27 | Credit to the original developer of the NES core, Ludvig Strigeus for 28 | making such an awesome project! Like the original core this is licensed 29 | under the GNU GPL. 30 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/blackicemx.pcf: -------------------------------------------------------------------------------- 1 | set_io clock_25 60 2 | 3 | set_io LED0 55 4 | set_io LED1 56 5 | 6 | set_io VGA_HS 1 7 | set_io VGA_VS 2 8 | set_io VGA_B[3] 135 9 | set_io VGA_B[2] 134 10 | set_io VGA_B[1] 137 11 | set_io VGA_B[0] 136 12 | set_io VGA_G[3] 4 13 | set_io VGA_G[2] 3 14 | set_io VGA_G[1] 144 15 | set_io VGA_G[0] 143 16 | set_io VGA_R[3] 139 17 | set_io VGA_R[2] 138 18 | set_io VGA_R[1] 142 19 | set_io VGA_R[0] 141 20 | 21 | set_io -nowarn AUDIO_O 26 22 | set_io joy_strobe 22 23 | set_io joy_clock 21 24 | set_io joy_data 25 25 | 26 | set_io flash_sck 70 27 | set_io flash_csn 71 28 | set_io flash_mosi 67 29 | set_io flash_miso 68 30 | 31 | set_io buttons 49 32 | 33 | # SRAM 34 | set_io sd_addr[0] 117 35 | set_io sd_addr[1] 119 36 | set_io sd_addr[2] 121 37 | set_io sd_addr[3] 124 38 | set_io sd_addr[4] 130 39 | set_io sd_addr[5] 125 40 | set_io sd_addr[6] 122 41 | set_io sd_addr[7] 120 42 | set_io sd_addr[8] 118 43 | set_io sd_addr[9] 116 44 | set_io sd_addr[10] 115 45 | 46 | set_io sd_ba 114 47 | 48 | set_io sd_data[0] 78 49 | set_io sd_data[1] 79 50 | set_io sd_data[2] 80 51 | set_io sd_data[3] 81 52 | set_io sd_data[4] 82 53 | set_io sd_data[5] 83 54 | set_io sd_data[6] 84 55 | set_io sd_data[7] 85 56 | set_io sd_data[8] 87 57 | set_io sd_data[9] 88 58 | set_io sd_data[10] 90 59 | set_io sd_data[11] 91 60 | set_io sd_data[12] 95 61 | set_io sd_data[13] 96 62 | set_io sd_data[14] 97 63 | set_io sd_data[15] 98 64 | 65 | set_io sd_dqm[0] 93 66 | set_io sd_dqm[1] 94 67 | 68 | set_io sd_we 107 69 | set_io sd_cas 110 70 | set_io sd_ras 112 71 | set_io sd_cs 113 72 | set_io sd_cke 128 73 | 74 | set_io sd_clk 129 75 | 76 | set_io diag[0] 34 77 | set_io diag[1] 33 78 | set_io diag[2] 29 79 | set_io diag[3] 28 80 | set_io diag[4] 38 81 | set_io diag[5] 37 82 | set_io diag[6] 32 83 | set_io diag[7] 31 84 | set_io diag[8] 16 85 | set_io diag[9] 15 86 | set_io diag[10] 10 87 | set_io diag[11] 9 88 | set_io diag[12] 18 89 | set_io diag[13] 17 90 | set_io diag[14] 12 91 | set_io diag[15] 11 92 | 93 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/compat.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | module MUXCY(output O, input CI, input DI, input S); 4 | assign O = S ? CI : DI; 5 | endmodule 6 | module MUXCY_L(output LO, input CI, input DI, input S); 7 | assign LO = S ? CI : DI; 8 | endmodule 9 | module MUXCY_D(output LO, output O, input CI, input DI, input S); 10 | assign LO = S ? CI : DI; 11 | assign O = LO; 12 | endmodule 13 | module XORCY(output O, input CI, input LI); 14 | assign O = CI ^ LI; 15 | endmodule 16 | module XOR2(output O, input I0, input I1); 17 | assign O = I0 ^ I1; 18 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/flashmem.v: -------------------------------------------------------------------------------- 1 | // SPI flash memory interface, taken from the icosoc project 2 | 3 | module icosoc_flashmem ( 4 | input clk, reset, 5 | 6 | input valid, 7 | output reg ready, 8 | input [23:0] addr, 9 | output reg [15:0] rdata, 10 | 11 | output reg spi_cs, 12 | output reg spi_sclk, 13 | output reg spi_mosi, 14 | input spi_miso 15 | ); 16 | reg [7:0] buffer; 17 | reg [3:0] xfer_cnt; 18 | reg [2:0] state; 19 | reg wake; 20 | reg [15:0] delay; 21 | 22 | always @(posedge clk) begin 23 | ready <= 0; 24 | if (reset || !valid || ready) begin 25 | spi_cs <= 1; 26 | spi_sclk <= 1; 27 | xfer_cnt <= 0; 28 | state <= 0; 29 | if (reset) wake <= 1; 30 | end else begin 31 | spi_cs <= 0; 32 | if (xfer_cnt) begin 33 | if (spi_sclk) begin 34 | spi_sclk <= 0; 35 | spi_mosi <= buffer[7]; 36 | end else begin 37 | spi_sclk <= 1; 38 | buffer <= {buffer, spi_miso}; 39 | xfer_cnt <= xfer_cnt - 1; 40 | end 41 | end else if (delay > 0) begin 42 | delay <= delay - 1; 43 | spi_cs <= 1; 44 | end else if (wake) begin 45 | buffer <= 'hab; // wake 46 | xfer_cnt <= 8; 47 | delay <= 'hffff; 48 | wake <= 0; 49 | end else 50 | case (state) 51 | 0: begin 52 | buffer <= 'h03; 53 | xfer_cnt <= 8; 54 | state <= 1; 55 | end 56 | 1: begin 57 | buffer <= addr[23:16]; 58 | xfer_cnt <= 8; 59 | state <= 2; 60 | end 61 | 2: begin 62 | buffer <= addr[15:8]; 63 | xfer_cnt <= 8; 64 | state <= 3; 65 | end 66 | 3: begin 67 | buffer <= addr[7:0]; 68 | xfer_cnt <= 8; 69 | state <= 4; 70 | end 71 | 4: begin 72 | xfer_cnt <= 8; 73 | state <= 5; 74 | end 75 | 5: begin 76 | rdata[7:0] <= buffer; 77 | xfer_cnt <= 8; 78 | state <= 6; 79 | end 80 | 6: begin 81 | rdata[15:8] <= buffer; 82 | ready <= 1; 83 | end 84 | endcase 85 | end 86 | end 87 | endmodule 88 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/generic_ram.v: -------------------------------------------------------------------------------- 1 | // Simple, platform-agnostic single-ported RAM 2 | 3 | module generic_ram(clock, reset, address, wren, write_data, read_data); 4 | 5 | parameter integer WIDTH = 8; 6 | parameter integer WORDS = 2048; 7 | localparam ADDR_BITS = $clog2(WORDS-1); 8 | 9 | input clock; 10 | input reset; 11 | input [ADDR_BITS-1:0] address; 12 | input wren; 13 | input [WIDTH-1:0] write_data; 14 | output reg [WIDTH-1:0] read_data; 15 | 16 | reg [WIDTH-1:0] mem[0:WORDS-1]; 17 | 18 | reg [ADDR_BITS-1:0] a_prereg; 19 | reg [WIDTH-1:0] d_prereg; 20 | reg wren_prereg; 21 | 22 | always @(posedge clock) begin 23 | if (reset == 1'b1) begin 24 | wren_prereg <= 0; 25 | a_prereg <= 0; 26 | d_prereg <= 0; 27 | end else begin 28 | wren_prereg <= wren; 29 | a_prereg <= address; 30 | d_prereg <= write_data; 31 | end 32 | 33 | 34 | read_data <= mem[a_prereg]; 35 | if (wren_prereg) mem[a_prereg] <= d_prereg; 36 | end 37 | 38 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -blif $@' $(ADD_SRC) 6 | 7 | %.json: $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -top ${TOP} -json $@' $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --placer heap --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | stty -F /dev/ttyACM0 raw 42 | cat $< >/dev/ttyACM0 43 | 44 | sudo-prog: $(PROJ).bin 45 | @echo 'Executing prog as root!!!' 46 | sudo iceprog $< 47 | 48 | clean: 49 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 50 | 51 | .SECONDARY: 52 | .PHONY: all prog clean 53 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/nes_palette_fceux.txt: -------------------------------------------------------------------------------- 1 | 39ce 2 | 4464 3 | 5400 4 | 4c08 5 | 3811 6 | 0815 7 | 0014 8 | 002f 9 | 00a8 10 | 0100 11 | 0140 12 | 08e0 13 | 2ce3 14 | 0000 15 | 0000 16 | 0000 17 | 5ef7 18 | 75c0 19 | 74e4 20 | 7810 21 | 5c17 22 | 2c1c 23 | 00bb 24 | 0539 25 | 01d1 26 | 0240 27 | 02a0 28 | 1e40 29 | 4600 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7ee7 35 | 7e4b 36 | 7e28 37 | 7dfe 38 | 59df 39 | 31df 40 | 1e7f 41 | 1efe 42 | 0b50 43 | 2769 44 | 4feb 45 | 6fa0 46 | 3def 47 | 0000 48 | 0000 49 | 7fff 50 | 7f95 51 | 7f58 52 | 7f3a 53 | 7f1f 54 | 6f1f 55 | 5aff 56 | 577f 57 | 539f 58 | 53fc 59 | 5fd5 60 | 67f6 61 | 7bf3 62 | 6318 63 | 0000 64 | 0000 65 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/nes_palette_unsaturatedv6.txt: -------------------------------------------------------------------------------- 1 | 35ad 2 | 4060 3 | 4823 4 | 4027 5 | 302b 6 | 140b 7 | 004a 8 | 0068 9 | 00c6 10 | 0121 11 | 0120 12 | 0d00 13 | 2ce0 14 | 0000 15 | 0000 16 | 0000 17 | 5ad6 18 | 6943 19 | 74c9 20 | 748e 21 | 5873 22 | 3074 23 | 0cb4 24 | 0130 25 | 01ac 26 | 0205 27 | 0220 28 | 2200 29 | 49e0 30 | 0000 31 | 0000 32 | 0000 33 | 7fff 34 | 7eac 35 | 7e32 36 | 7dd7 37 | 7ddc 38 | 65be 39 | 361e 40 | 167b 41 | 02f7 42 | 0350 43 | 1f6b 44 | 3f49 45 | 6729 46 | 294a 47 | 0000 48 | 0000 49 | 7fff 50 | 7f98 51 | 7f5a 52 | 7f3c 53 | 7f3f 54 | 7b3f 55 | 635f 56 | 577e 57 | 4fbd 58 | 4fda 59 | 5bd7 60 | 67d6 61 | 77d6 62 | 5ef7 63 | 0000 64 | 0000 -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/oam_palette.txt: -------------------------------------------------------------------------------- 1 | 0F 2 | 2C 3 | 10 4 | 1C 5 | 0F 6 | 37 7 | 27 8 | 07 9 | 0F 10 | 28 11 | 16 12 | 07 13 | 0F 14 | 28 15 | 0F 16 | 2C 17 | 0F 18 | 0F 19 | 2C 20 | 11 21 | 0F 22 | 0F 23 | 20 24 | 38 25 | 0F 26 | 0F 27 | 15 28 | 27 29 | 0F 30 | 0F 31 | 11 32 | 3C -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/pll.v: -------------------------------------------------------------------------------- 1 | /** 2 | * PLL configuration 3 | * 4 | * This Verilog module was generated automatically 5 | * using the icepll tool from the IceStorm project. 6 | * Use at your own risk. 7 | * 8 | * Given input frequency: 25.000 MHz 9 | * Requested output frequency: 43.000 MHz 10 | * Achieved output frequency: 42.969 MHz 11 | */ 12 | 13 | module pll( 14 | input clock_in, 15 | output clock_out, 16 | output locked 17 | ); 18 | 19 | SB_PLL40_CORE #( 20 | .FEEDBACK_PATH("SIMPLE"), 21 | .DIVR(4'b0001), // DIVR = 1 22 | .DIVF(7'b0110110), // DIVF = 54 23 | .DIVQ(3'b100), // DIVQ = 4 24 | .FILTER_RANGE(3'b001) // FILTER_RANGE = 1 25 | ) uut ( 26 | .LOCK(locked), 27 | .RESETB(1'b1), 28 | .BYPASS(1'b0), 29 | .REFERENCECLK(clock_in), 30 | .PLLOUTCORE(clock_out) 31 | ); 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/rom/nes2bin.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | import os, sys, re 4 | 5 | prg_alloc = 64*1024 6 | chr_alloc = 64*1024 7 | 8 | prg_dat = bytearray() 9 | chr_dat = bytearray() 10 | header = None 11 | with open(sys.argv[1], 'rb') as f: 12 | header = f.read(16) 13 | prg_size = header[4] * 16384 14 | chr_size = header[5] * 8192 15 | assert prg_size <= 2 * prg_alloc #PRG can spill into CHR sometimes 16 | prg_dat = f.read(prg_size) 17 | if prg_size > prg_alloc: 18 | assert chr_size == 0 19 | else: 20 | assert chr_size <= chr_alloc 21 | chr_dat = f.read(chr_size) 22 | 23 | prg_dat = bytearray(prg_dat) 24 | chr_dat = bytearray(chr_dat) 25 | 26 | for i in range(prg_size, prg_alloc): 27 | prg_dat.append(prg_dat[i % prg_size]) 28 | if prg_size > prg_alloc: 29 | for i in range(prg_size, 2*prg_alloc): 30 | prg_dat.append(prg_dat[i % prg_size]) 31 | else: 32 | for i in range(chr_size, chr_alloc): 33 | if chr_size == 0: 34 | chr_dat.append(0) 35 | else: 36 | chr_dat.append(chr_dat[i % chr_size]) 37 | 38 | out_flags = 0x0 39 | mapper = (header[6] >> 4) & 0x0F 40 | mapper |= header[7] & 0xF0 41 | out_flags |= mapper 42 | 43 | mirroring = header[6] & 0x01 44 | fourscreen = (header[6] >> 3) & 0x01 45 | 46 | prg_mask = 0 47 | if prg_size <= 16*1024: 48 | prg_mask = 0 49 | elif prg_size <= 32*1024: 50 | prg_mask = 1 51 | elif prg_size <= 64*1024: 52 | prg_mask = 2 53 | elif prg_size <= 128*1024: 54 | prg_mask = 3 55 | elif prg_size <= 256*1024: 56 | prg_mask = 4 57 | elif prg_size <= 512*1024: 58 | prg_mask = 5 59 | elif prg_size <= 1024*1024: 60 | prg_mask = 6 61 | else: 62 | prg_mask = 7 63 | 64 | chr_mask = 0 65 | if chr_size <= 8*1024: 66 | chr_mask = 0 67 | elif chr_size <= 16*1024: 68 | chr_mask = 1 69 | elif chr_size <= 32*1024: 70 | chr_mask = 2 71 | elif chr_size <= 64*1024: 72 | chr_mask = 3 73 | elif chr_size <= 128*1024: 74 | chr_mask = 4 75 | elif chr_size <= 256*1024: 76 | chr_mask = 5 77 | elif chr_size <= 512*1024: 78 | chr_mask = 6 79 | else: 80 | chr_mask = 7 81 | 82 | if chr_size == 0: 83 | has_chr_ram = 1 84 | else: 85 | has_chr_ram = 0 86 | 87 | out_flags |= (prg_mask << 8) 88 | out_flags |= (chr_mask << 11) 89 | out_flags |= (mirroring << 14) 90 | out_flags |= (has_chr_ram << 15) 91 | out_flags |= (fourscreen << 16) 92 | 93 | with open(sys.argv[2], 'wb') as f: 94 | f.write(prg_dat) 95 | f.write(chr_dat) 96 | # Append mapper, size and other flags to end of data 97 | f.write(bytes([(out_flags) & 0xFF, (out_flags >> 8) & 0xFF, (out_flags >> 16) & 0xFF, (out_flags >> 24) & 0xFF])) 98 | f.write(bytearray(256*1024 - (prg_alloc + chr_alloc + 4))) # pad to 256kB total -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/scan_double.v: -------------------------------------------------------------------------------- 1 | module scan_double(input clk, 2 | input [14:0] inputpixel, 3 | input reset_frame, 4 | input reset_line, 5 | input [9:0] read_x, 6 | output reg [14:0] outpixel); 7 | reg [1:0] frac; 8 | reg [14:0] linebuf[0:255]; 9 | reg [8:0] write_x; 10 | 11 | always @(posedge clk) 12 | begin 13 | if(reset_line) 14 | begin 15 | frac <= 2'b00; 16 | write_x <= 9'd0; 17 | end else begin 18 | frac <= frac + 1; 19 | if (frac == 2) 20 | if (write_x < 256) 21 | write_x <= write_x + 1; 22 | end 23 | end 24 | 25 | wire write_en = ((frac == 2) && (write_x < 256)) ? 1'b1 : 1'b0; 26 | 27 | always @(posedge clk) 28 | begin 29 | outpixel <= linebuf[read_x[8:1]]; 30 | if(write_en) 31 | linebuf[write_x[7:0]] <= inputpixel; 32 | end 33 | 34 | 35 | 36 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/sigma_delta_dac.v: -------------------------------------------------------------------------------- 1 | module sigma_delta_dac( 2 | output reg DACout, //Average Output feeding analog lowpass 3 | input [MSBI:0] DACin, //DAC input (excess 2**MSBI) 4 | input CLK, 5 | input CEN, 6 | input RESET 7 | ); 8 | 9 | parameter MSBI = 7; 10 | 11 | reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder 12 | reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder 13 | reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder 14 | reg [MSBI+2:0] DeltaB; //B input of Delta Adder 15 | 16 | always @ (*) 17 | DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1); 18 | 19 | always @(*) 20 | DeltaAdder = DACin + DeltaB; 21 | 22 | always @(*) 23 | SigmaAdder = DeltaAdder + SigmaLatch; 24 | 25 | always @(posedge CLK) 26 | begin 27 | SigmaLatch <= SigmaAdder; 28 | DACout <= SigmaLatch[MSBI+2]; 29 | end 30 | endmodule -------------------------------------------------------------------------------- /demo/Refence/up5k-demos/nesmx/video.v: -------------------------------------------------------------------------------- 1 | // Copyright (c) 2012-2013 Ludvig Strigeus 2 | // This program is GPL Licensed. See COPYING for the full license. 3 | 4 | module video( 5 | input clk, 6 | input [5:0] color, 7 | input [8:0] count_h, 8 | input [8:0] count_v, 9 | input mode, 10 | input ypbpr, 11 | input smoothing, 12 | input scanlines, 13 | input overscan, 14 | input palette, 15 | 16 | 17 | output VGA_HS, 18 | output VGA_VS, 19 | output [3:0] VGA_R, 20 | output [3:0] VGA_G, 21 | output [3:0] VGA_B, 22 | 23 | output osd_visible 24 | ); 25 | 26 | reg clk2 = 1'b0; 27 | always @(posedge clk) clk2 <= ~clk2; 28 | wire clkv = mode ? clk2 : clk; 29 | 30 | wire [5:0] R_out, G_out, B_out; 31 | 32 | 33 | 34 | // NTSC UnsaturatedV6 palette 35 | //see: http://www.firebrandx.com/nespalette.html 36 | /*reg [15:0] pal_unsat_lut[0:63]; 37 | initial $readmemh("nes_palette_unsaturatedv6.txt", pal_unsat_lut);*/ 38 | 39 | // FCEUX palette 40 | reg [15:0] pal_fcelut[0:63]; 41 | initial $readmemh("nes_palette_fceux.txt", pal_fcelut); 42 | 43 | wire [14:0] pixel = pal_fcelut[color][14:0]; 44 | 45 | // Horizontal and vertical counters 46 | reg [9:0] h, v; 47 | wire hpicture = (h < 512); // 512 lines of picture 48 | wire hend = (h == 681); // End of line, 682 pixels. 49 | wire vpicture = (v < (480 >> mode)); // 480 lines of picture 50 | wire vend = (v == (523 >> mode)); // End of picture, 524 lines. (Should really be 525 according to NTSC spec) 51 | 52 | wire [14:0] doubler_pixel; 53 | wire doubler_sync; 54 | 55 | scan_double doubler(clk, pixel, 56 | count_v[8], // reset_frame 57 | (count_h[8:3] == 42), // reset_line 58 | {v[0], h[9] ? 9'd0 : h[8:0] + 9'd1}, // 0-511 for line 1, or 512-1023 for line 2. 59 | doubler_pixel); // pixel is outputted 60 | 61 | 62 | reg [8:0] old_count_v; 63 | wire sync_frame = (old_count_v == 9'd511) && (count_v == 9'd0); 64 | 65 | assign doubler_sync = sync_frame; 66 | 67 | always @(posedge clkv) begin 68 | h <= (hend || (mode ? sync_frame : doubler_sync)) ? 10'd0 : h + 10'd1; 69 | if(mode ? sync_frame : doubler_sync) v <= 0; 70 | else if (hend) v <= vend ? 10'd0 : v + 10'd1; 71 | 72 | old_count_v <= count_v; 73 | end 74 | 75 | wire [14:0] pixel_v = (!hpicture || !vpicture) ? 15'd0 : mode ? pixel : doubler_pixel; 76 | wire darker = !mode && v[0] && scanlines; 77 | 78 | // display overlay to hide overscan area 79 | // based on Mario3, DoubleDragon2, Shadow of the Ninja 80 | wire ol = overscan && ( (h > 512-16) || 81 | (h < 20) || 82 | (v < (mode ? 6 : 12)) || 83 | (v > (mode ? 240-10 : 480-20)) 84 | ); 85 | 86 | wire [4:0] vga_r = ol ? {4'b0, pixel_v[4:4]} : (darker ? {1'b0, pixel_v[4:1]} : pixel_v[4:0]); 87 | wire [4:0] vga_g = ol ? {4'b0, pixel_v[9:9]} : (darker ? {1'b0, pixel_v[9:6]} : pixel_v[9:5]); 88 | wire [4:0] vga_b = ol ? {4'b0, pixel_v[14:14]} : (darker ? {1'b0, pixel_v[14:11]} : pixel_v[14:10]); 89 | wire sync_h = ((h >= (512 + 23 + (mode ? 18 : 35))) && (h < (512 + 23 + (mode ? 18 : 35) + 82))); 90 | wire sync_v = ((v >= (mode ? 240 + 5 : 480 + 10)) && (v < (mode ? 240 + 14 : 480 + 12))); 91 | 92 | 93 | assign VGA_HS = !sync_h; 94 | assign VGA_VS = !sync_v; 95 | assign VGA_R = vga_r[4:1]; 96 | assign VGA_G = vga_g[4:1]; 97 | assign VGA_B = vga_b[4:1]; 98 | 99 | endmodule 100 | -------------------------------------------------------------------------------- /demo/verilog/00_run_led/Makefile: -------------------------------------------------------------------------------- 1 | filename = Run_LED 2 | pcf_file = openice.pcf 3 | 4 | ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}') 5 | ${warning iCELink path: $(ICELINK_DIR)} 6 | 7 | build: 8 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 9 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 10 | icepack $(filename).asc $(filename).bin 11 | 12 | 13 | clean: 14 | rm -rf $(filename).blif $(filename).asc $(filename).bin 15 | -------------------------------------------------------------------------------- /demo/verilog/00_run_led/Run_LED.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | //***************************************// 3 | //# @Author: 碎碎思 4 | //# @Date: 2019-04-14 19:54:50 5 | //# @Last Modified by: zlk 6 | //# @Last Modified time: 2019-04-14 21:36:06 7 | //****************************************// 8 | module Run_LED 9 | ( 10 | input CLK, 11 | input RST_n, 12 | output LED0, 13 | output LED1, 14 | output LED2, 15 | output LED3, 16 | output LED4, 17 | output LED5, 18 | output LED6, 19 | output LED7 20 | ); 21 | 22 | 23 | //////////////////////////////////////////// 24 | 25 | 26 | reg [7:0]LED; 27 | 28 | 29 | //////////////////////////////////////////// 30 | // 31 | //首先定义一个时间计数寄存器counter，每当达到预定的100ms时， 32 | //计数寄存器就清零，否则的话寄存器就加1。 33 | //然后计算计数器计数的最大值。时钟频率为12MHZ， 34 | //也就是周期为1/12M 为83ns，要计数的最大值为T100MS= 100ms/83ns-1 = 120_4818。 35 | // 36 | 37 | reg[24:0] counter; 38 | parameter T100MS = 25'd120_4818; 39 | 40 | always @ (posedge CLK or negedge RST_n) 41 | 42 | if(!RST_n) //高电平复位 43 | 44 | counter<=25'd0; 45 | 46 | else if(counter==T100MS) 47 | 48 | counter<=25'd0; 49 | 50 | else 51 | 52 | counter<=counter+1'b1; 53 | //////////////////////////////////////////// 54 | always @ (posedge CLK or negedge RST_n) 55 | 56 | if(!RST_n) 57 | 58 | LED<=8'b1111_1111; //初值，最低位led[0]灯亮 59 | 60 | else if(counter==T100MS) 61 | 62 | begin 63 | 64 | if(LED==8'b0000_0000) //当溢出最高位时 65 | 66 | LED<=8'b1111_1111; //回到复位时的状态 67 | 68 | else 69 | 70 | LED<=LED<<1; //循环左移一位 71 | 72 | end 73 | 74 | assign {LED0,LED1,LED2,LED3,LED4,LED5,LED6,LED7}=LED; 75 | 76 | endmodule // Run_LED 77 | -------------------------------------------------------------------------------- /demo/verilog/00_run_led/openice.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RESET Button 5 | set_io -nowarn RST_n 43 6 | 7 | # RS232 8 | set_io -nowarn RX 6 9 | set_io -nowarn TX 9 10 | 11 | 12 | # RGB LED Driver 13 | set_io -nowarn LED_RED_N 39 14 | set_io -nowarn LED_GRN_N 40 15 | set_io -nowarn LED_BLU_N 41 16 | 17 | # SPI Flash 18 | set_io -nowarn FLASH_SCK 15 19 | set_io -nowarn FLASH_SSB 16 20 | set_io -nowarn FLASH_IO0 14 21 | set_io -nowarn FLASH_IO1 17 22 | set_io -nowarn FLASH_IO2 12 23 | set_io -nowarn FLASH_IO3 13 24 | 25 | # PMOD 1A 26 | set_io -nowarn P1A1 4 27 | set_io -nowarn P1A2 2 28 | set_io -nowarn P1A3 47 29 | set_io -nowarn P1A4 45 30 | set_io -nowarn P1A7 3 31 | set_io -nowarn P1A8 48 32 | set_io -nowarn P1A9 46 33 | set_io -nowarn P1A10 44 34 | 35 | # PMOD 1B 36 | set_io -nowarn P1B1 43 37 | set_io -nowarn P1B2 38 38 | set_io -nowarn P1B3 34 39 | set_io -nowarn P1B4 31 40 | set_io -nowarn P1B7 42 41 | set_io -nowarn P1B8 36 42 | set_io -nowarn P1B9 32 43 | set_io -nowarn P1B10 28 44 | 45 | # PMOD 2 46 | set_io -nowarn P2_1 27 47 | set_io -nowarn P2_2 25 48 | set_io -nowarn P2_3 21 49 | set_io -nowarn P2_4 19 50 | set_io -nowarn P2_7 26 51 | set_io -nowarn P2_8 23 52 | set_io -nowarn P2_9 20 53 | set_io -nowarn P2_10 18 54 | 55 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 56 | set_io -nowarn LED0 4 57 | set_io -nowarn LED1 3 58 | set_io -nowarn LED2 2 59 | set_io -nowarn LED3 48 60 | set_io -nowarn LED4 47 61 | set_io -nowarn LED5 46 62 | set_io -nowarn LED6 45 63 | set_io -nowarn LED7 44 64 | 65 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 66 | set_io -nowarn BTN0 4 67 | set_io -nowarn BTN1 3 68 | set_io -nowarn BTN2 2 69 | set_io -nowarn BTN3 48 70 | set_io -nowarn BTN4 47 71 | set_io -nowarn BTN5 46 72 | set_io -nowarn BTN6 45 73 | set_io -nowarn BTN7 44 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /demo/verilog/00_run_led/run_led.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/00_run_led/run_led.bin -------------------------------------------------------------------------------- /demo/verilog/01_sb_rgba_blink/.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | *.asc 3 | *.bin 4 | *.blif 5 | *.json 6 | -------------------------------------------------------------------------------- /demo/verilog/01_sb_rgba_blink/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = blink 2 | PIN_DEF = blink.pcf 3 | DEVICE = up5k 4 | PACKAGE = sg48 5 | 6 | ARACHNE = arachne-pnr 7 | ARACHNE_ARGS = 8 | NEXTPNR = nextpnr-ice40 9 | NEXTPNR_ARGS = 10 | ICEPACK = icepack 11 | ICETIME = icetime 12 | ICEPROG = iceprog 13 | 14 | PNR ?= arachne 15 | 16 | all: $(PROJ).bin $(TESTBENCHES) 17 | 18 | %.blif %.json: %.v 19 | yosys -p 'synth_ice40 -top $(PROJ) -blif $*.blif -json $*.json' $< 20 | 21 | ifeq ($(PNR),next) 22 | %.asc: $(PIN_DEF) %.json 23 | $(NEXTPNR) $(NEXTPNR_ARGS) --$(DEVICE) --package $(PACKAGE) --json $*.json --pcf $(PIN_DEF) --asc $@ 24 | else 25 | %.asc: $(PIN_DEF) %.blif 26 | $(ARACHNE) $(ARACHNE_ARGS) -l -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) -o $@ -p $^ -P $(PACKAGE) 27 | endif 28 | 29 | %.bin: %.asc 30 | $(ICEPACK) $< $@ 31 | 32 | %.rpt: %.asc 33 | $(ICETIME) -d $(DEVICE) -mtr $@ $< 34 | 35 | prog: $(PROJ).bin 36 | $(ICEPROG) $< 37 | 38 | sudo-prog: $(PROJ).bin 39 | @echo 'Executing prog as root!!!' 40 | sudo $(ICEPROG) $< 41 | 42 | clean: 43 | rm -f $(PROJ).blif $(PROJ).json $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(TESTBENCHES) *.vcd 44 | 45 | .SECONDARY: 46 | .PHONY: all prog clean 47 | -------------------------------------------------------------------------------- /demo/verilog/01_sb_rgba_blink/blink.pcf: -------------------------------------------------------------------------------- 1 | set_io rgb[0] 39 2 | set_io rgb[1] 40 3 | set_io rgb[2] 41 4 | -------------------------------------------------------------------------------- /demo/verilog/01_sb_rgba_blink/blink.v: -------------------------------------------------------------------------------- 1 | /* 2 | * blink.v 3 | * 4 | * CC0 1.0 Universal - See LICENSE in this directory 5 | * 6 | * Copyright (C) 2018 Sylvain Munaut 7 | * 8 | * vim: ts=4 sw=4 9 | */ 10 | 11 | `default_nettype none 12 | 13 | module blink ( 14 | output wire [2:0] rgb, 15 | ); 16 | 17 | reg [27:0] cnt; 18 | wire rgb_pwm[2:0]; 19 | wire clk; 20 | 21 | SB_HFOSC osc_I ( 22 | .CLKHFPU(1'b1), 23 | .CLKHFEN(1'b1), 24 | .CLKHF(clk) 25 | ); 26 | 27 | always @(posedge clk) 28 | cnt <= cnt + 1; 29 | 30 | assign rgb_pwm[0] = cnt[27] & (cnt[2:0] == 3'b000); 31 | assign rgb_pwm[1] = cnt[26] & (cnt[2:0] == 3'b000); 32 | assign rgb_pwm[2] = cnt[25] & (cnt[2:0] == 3'b000); 33 | 34 | SB_RGBA_DRV #( 35 | .CURRENT_MODE("0b1"), 36 | .RGB0_CURRENT("0b000001"), 37 | .RGB1_CURRENT("0b000001"), 38 | .RGB2_CURRENT("0b000001") 39 | ) rgb_drv_I ( 40 | .RGBLEDEN(1'b1), 41 | .RGB0PWM(rgb_pwm[0]), 42 | .RGB1PWM(rgb_pwm[1]), 43 | .RGB2PWM(rgb_pwm[2]), 44 | .CURREN(1'b1), 45 | .RGB0(rgb[0]), 46 | .RGB1(rgb[1]), 47 | .RGB2(rgb[2]) 48 | ); 49 | 50 | endmodule // blink 51 | 52 | -------------------------------------------------------------------------------- /demo/verilog/02_RGB LED/Makefile: -------------------------------------------------------------------------------- 1 | filename = leds 2 | pcf_file = ../../../common/io.pcf 3 | 4 | ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}') 5 | ${warning iCELink path: $(ICELINK_DIR)} 6 | 7 | build: 8 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 9 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 10 | icepack $(filename).asc $(filename).bin 11 | 12 | prog_flash: 13 | @if [ -d '$(ICELINK_DIR)' ]; \ 14 | then \ 15 | cp $(filename).bin $(ICELINK_DIR); \ 16 | else \ 17 | echo "iCELink not found"; \ 18 | exit 1; \ 19 | fi 20 | 21 | clean: 22 | rm -rf $(filename).blif $(filename).asc $(filename).bin 23 | -------------------------------------------------------------------------------- /demo/verilog/02_RGB LED/leds.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/02_RGB LED/leds.bin -------------------------------------------------------------------------------- /demo/verilog/02_RGB LED/leds.v: -------------------------------------------------------------------------------- 1 | //light up the leds according to a counter to cycle through every one 2 | 3 | /* 4 | b[25] b[24] b[23] 5 | 0 0 0 black (all off) 6 | 0 0 1 red 7 | 0 1 0 green 8 | 0 1 1 yellow (red + green) 9 | 1 0 0 blue 10 | 1 0 1 magenta (red + blue) 11 | 1 1 0 cyan (green + blue) 12 | 1 1 1 white 13 | */ 14 | 15 | module top(input [3:0] SW, input clk, output LED_R, output LED_G, output LED_B); 16 | reg [25:0] counter; 17 | 18 | assign LED_R = ~counter[23]; 19 | assign LED_G = ~counter[24]; 20 | assign LED_B = ~counter[25]; 21 | 22 | initial begin 23 | counter = 0; 24 | end 25 | 26 | always @(posedge clk) 27 | begin 28 | counter <= counter + 1; 29 | end 30 | endmodule // top 31 | -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/make_bin.sh: -------------------------------------------------------------------------------- 1 | yosys -p "synth_ice40 -blif pll_uart_mirror.blif" pll_uart_mirror.v uart_baud_tick_gen.v uart_rx.v uart_tx.v 2 | 3 | arachne-pnr -d 5k -p openice.pcf pll_uart_mirror.blif -o pll_uart_mirror.asc 4 | 5 | icepack pll_uart_mirror.asc pll_uart_mirror.bin 6 | 7 | -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/openice.pcf: -------------------------------------------------------------------------------- 1 | # 12 MHz clock 2 | set_io -nowarn CLK 35 3 | 4 | # RESET Button 5 | set_io -nowarn RST_n 43 6 | 7 | # RS232 8 | set_io -nowarn TX 6 9 | set_io -nowarn RX 9 10 | 11 | 12 | # RGB LED Driver 13 | set_io -nowarn LEDR_N 39 14 | set_io -nowarn LEDG_N 40 15 | set_io -nowarn LEDB_N 41 16 | 17 | # SPI Flash 18 | set_io -nowarn FLASH_SCK 15 19 | set_io -nowarn FLASH_SSB 16 20 | set_io -nowarn FLASH_IO0 14 21 | set_io -nowarn FLASH_IO1 17 22 | set_io -nowarn FLASH_IO2 12 23 | set_io -nowarn FLASH_IO3 13 24 | 25 | # PMOD 1A 26 | set_io -nowarn P1A1 4 27 | set_io -nowarn P1A2 2 28 | set_io -nowarn P1A3 47 29 | set_io -nowarn P1A4 45 30 | set_io -nowarn P1A7 3 31 | set_io -nowarn P1A8 48 32 | set_io -nowarn P1A9 46 33 | set_io -nowarn P1A10 44 34 | 35 | # PMOD 1B 36 | set_io -nowarn P1B1 43 37 | set_io -nowarn P1B2 38 38 | set_io -nowarn P1B3 34 39 | set_io -nowarn P1B4 31 40 | set_io -nowarn P1B7 42 41 | set_io -nowarn P1B8 36 42 | set_io -nowarn P1B9 32 43 | set_io -nowarn P1B10 28 44 | 45 | # PMOD 2 46 | set_io -nowarn P2_1 27 47 | set_io -nowarn P2_2 25 48 | set_io -nowarn P2_3 21 49 | set_io -nowarn P2_4 19 50 | set_io -nowarn P2_7 26 51 | set_io -nowarn P2_8 23 52 | set_io -nowarn P2_9 20 53 | set_io -nowarn P2_10 18 54 | 55 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 56 | set_io -nowarn LED0 4 57 | set_io -nowarn LED1 3 58 | set_io -nowarn LED2 2 59 | set_io -nowarn LED3 48 60 | set_io -nowarn LED4 47 61 | set_io -nowarn LED5 46 62 | set_io -nowarn LED6 45 63 | set_io -nowarn LED7 44 64 | 65 | # LEDs and Buttons (PMOD swich&led)-->PMOD1A 66 | set_io -nowarn BTN0 4 67 | set_io -nowarn BTN1 3 68 | set_io -nowarn BTN2 2 69 | set_io -nowarn BTN3 48 70 | set_io -nowarn BTN4 47 71 | set_io -nowarn BTN5 46 72 | set_io -nowarn BTN6 45 73 | set_io -nowarn BTN7 44 74 | 75 | 76 | 77 | -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/pll_uart_mirror.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/03_pll_uart/pll_uart_mirror.bin -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/pll_uart_mirror.v: -------------------------------------------------------------------------------- 1 | /* 2 | * icebreaker examples - Async uart mirror using pll 3 | * 4 | * Copyright (C) 2018 Piotr Esden-Tempski 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module top ( 21 | input CLK, 22 | input RX, 23 | output TX, 24 | output LEDR_N, 25 | output LEDG_N 26 | ); 27 | 28 | wire clk_42mhz; 29 | //assign clk_42mhz = CLK; 30 | SB_PLL40_PAD #( 31 | .DIVR(4'b0000), 32 | // 42MHz 33 | .DIVF(7'b0110111), 34 | .DIVQ(3'b100), 35 | .FILTER_RANGE(3'b001), 36 | .FEEDBACK_PATH("SIMPLE"), 37 | .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"), 38 | .FDA_FEEDBACK(4'b0000), 39 | .DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"), 40 | .FDA_RELATIVE(4'b0000), 41 | .SHIFTREG_DIV_MODE(2'b00), 42 | .PLLOUT_SELECT("GENCLK"), 43 | .ENABLE_ICEGATE(1'b0) 44 | ) usb_pll_inst ( 45 | .PACKAGEPIN(CLK), 46 | .PLLOUTCORE(clk_42mhz), 47 | //.PLLOUTGLOBAL(), 48 | .EXTFEEDBACK(), 49 | .DYNAMICDELAY(), 50 | .RESETB(1'b1), 51 | .BYPASS(1'b0), 52 | .LATCHINPUTVALUE(), 53 | //.LOCK(), 54 | //.SDI(), 55 | //.SDO(), 56 | //.SCLK() 57 | ); 58 | 59 | /* local parameters */ 60 | //localparam clk_freq = 12_000_000; // 12MHz 61 | localparam clk_freq = 42_000_000; // 42MHz 62 | //localparam baud = 57600; 63 | localparam baud = 115200; 64 | 65 | 66 | /* instantiate the rx1 module */ 67 | wire reg rx1_ready; 68 | wire reg [7:0] rx1_data; 69 | uart_rx #(clk_freq, baud) urx1 ( 70 | .clk(clk_42mhz), 71 | .rx(RX), 72 | .rx_ready(rx1_ready), 73 | .rx_data(rx1_data), 74 | ); 75 | 76 | /* instantiate the tx1 module */ 77 | wire reg tx1_start; 78 | wire reg [7:0] tx1_data; 79 | wire reg tx1_busy; 80 | uart_tx #(clk_freq, baud) utx1 ( 81 | .clk(clk_42mhz), 82 | .tx_start(tx1_start), 83 | .tx_data(tx1_data), 84 | .tx(TX), 85 | .tx_busy(tx1_busy) 86 | ); 87 | 88 | // Send the received data immediately back 89 | 90 | wire reg [7:0] data_buf; 91 | wire reg data_flag = 0; 92 | wire reg data_check_busy = 0; 93 | always @(posedge clk_42mhz) begin 94 | 95 | // we got a new data strobe 96 | // let's save it and set a flag 97 | if(rx1_ready && ~data_flag) begin 98 | data_buf <= rx1_data; 99 | data_flag <= 1; 100 | data_check_busy <= 1; 101 | end 102 | 103 | // new data flag is set let's try to send it 104 | if(data_flag) begin 105 | 106 | // First check if the previous transmission is over 107 | if(data_check_busy) begin 108 | if(~tx1_busy) begin 109 | data_check_busy <= 0; 110 | end // if(~tx1_busy) 111 | 112 | end else begin // try to send waiting for busy to go high to make sure 113 | if(~tx1_busy) begin 114 | tx1_data <= data_buf; 115 | tx1_start <= 1'b1; 116 | LEDR_N <= ~data_buf[0]; 117 | LEDG_N <= ~data_buf[1]; 118 | end else begin // Yey we did it! 119 | tx1_start <= 1'b0; 120 | data_flag <= 0; 121 | end 122 | end 123 | end 124 | end 125 | 126 | // Loopback the TX and RX lines with no processing 127 | // Useful as a sanity check ;-) 128 | //assign TX = RX; 129 | 130 | endmodule 131 | -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/uart_baud_tick_gen.v: -------------------------------------------------------------------------------- 1 | /* 2 | * icebreaker examples - Async uart baud tick generator module 3 | * 4 | * Copyright (C) 2018 Piotr Esden-Tempski 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | /*** 21 | * This module generates a bit baud tick multiplied by the oversampling parameter. 22 | */ 23 | module baud_tick_gen( 24 | input clk, enable, 25 | output tick); 26 | parameter clk_freq = 12000000; 27 | parameter baud = 115200; 28 | parameter oversampling = 1; 29 | 30 | function integer log2(input integer v); begin log2=0; while(v >> log2) log2 = log2 + 1; end endfunction 31 | 32 | localparam acc_width = log2(clk_freq / baud) + 8; // +/- 2% max timing error over a byte 33 | 34 | reg [acc_width:0] acc = 0; 35 | 36 | localparam shiftlimiter = log2((baud * oversampling) >> (31 - acc_width)); // this makes sure inc calculation doesn't overflow (verilog uses 32bit variables internally) 37 | localparam inc = ((baud * oversampling << (acc_width - shiftlimiter)) + (clk_freq >> (shiftlimiter + 1))) / (clk_freq >> shiftlimiter); // Calculate accumulate increment 38 | //initial $display("acc_width %d, shiftlimit %d, inc %d", acc_width, shiftlimiter, inc); 39 | 40 | always @(posedge clk) if (enable) acc <= acc[acc_width-1:0] + inc[acc_width:0]; else acc <= inc[acc_width:0]; 41 | assign tick = acc[acc_width]; 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /demo/verilog/03_pll_uart/uart_tx.v: -------------------------------------------------------------------------------- 1 | /* 2 | * icebreaker examples - Async uart tx module 3 | * 4 | * Copyright (C) 2018 Piotr Esden-Tempski 5 | * 6 | * Permission to use, copy, modify, and/or distribute this software for any 7 | * purpose with or without fee is hereby granted, provided that the above 8 | * copyright notice and this permission notice appear in all copies. 9 | * 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 | * 18 | */ 19 | 20 | module uart_tx( 21 | input clk, 22 | input tx_start, 23 | input [7:0] tx_data, 24 | output tx, 25 | output tx_busy); 26 | 27 | parameter clk_freq = 12000000; 28 | parameter baud = 115200; 29 | 30 | wire bit_tick; 31 | baud_tick_gen #(clk_freq, baud) tickgen(.clk(clk), .enable(tx_busy), .tick(bit_tick)); 32 | 33 | localparam 34 | IDLE = 4'b0000, // tx = high 35 | BIT_START = 4'b0100, // tx = low 36 | BIT0 = 4'b1000, // tx = data bit 0 37 | BIT1 = 4'b1001, // tx = data bit 1 38 | BIT2 = 4'b1010, // tx = data bit 2 39 | BIT3 = 4'b1011, // tx = data bit 3 40 | BIT4 = 4'b1100, // tx = data bit 4 41 | BIT5 = 4'b1101, // tx = data bit 5 42 | BIT6 = 4'b1110, // tx = data bit 6 43 | BIT7 = 4'b1111, // tx = data bit 7 44 | BIT_STOP1 = 4'b0010, // tx = high 45 | BIT_STOP2 = 4'b0011; // tx = high 46 | 47 | reg [3:0] tx_state = IDLE; 48 | wire tx_ready = (tx_state == 0); 49 | assign tx_busy = ~tx_ready; 50 | 51 | reg [7:0] tx_shift = 0; 52 | always @(posedge clk) 53 | begin 54 | if (tx_ready & tx_start) 55 | tx_shift <= tx_data; 56 | else 57 | if (tx_state[3] & bit_tick) 58 | tx_shift <= (tx_shift >> 1); 59 | 60 | case (tx_state) 61 | IDLE: if(tx_start) tx_state <= BIT_START; 62 | BIT_START: if(bit_tick) tx_state <= BIT0; 63 | BIT0: if(bit_tick) tx_state <= BIT1; 64 | BIT1: if(bit_tick) tx_state <= BIT2; 65 | BIT2: if(bit_tick) tx_state <= BIT3; 66 | BIT3: if(bit_tick) tx_state <= BIT4; 67 | BIT4: if(bit_tick) tx_state <= BIT5; 68 | BIT5: if(bit_tick) tx_state <= BIT6; 69 | BIT6: if(bit_tick) tx_state <= BIT7; 70 | BIT7: if(bit_tick) tx_state <= BIT_STOP1; 71 | BIT_STOP1: if(bit_tick) tx_state <= BIT_STOP2; 72 | BIT_STOP2: if(bit_tick) tx_state <= IDLE; 73 | default: if(bit_tick) tx_state <= IDLE; 74 | endcase 75 | 76 | end 77 | 78 | // high if state START, STOP1, STOP2 79 | // | high if transmitting bits and bit is 1 80 | // | | 81 | // V V 82 | assign tx = (tx_state < 4) | (tx_state[3] & tx_shift[0]); 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /demo/verilog/04_Dial Switch/dial_switch.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/04_Dial Switch/dial_switch.bin -------------------------------------------------------------------------------- /demo/verilog/04_Dial Switch/dial_switch.blif: -------------------------------------------------------------------------------- 1 | # Generated by Yosys 0.9+1706 (git sha1 c244b27b, clang 6.0.0-1ubuntu2 -fPIC -Os) 2 | 3 | .model dial_switch 4 | .inputs CLK RST_n SWICH[0] SWICH[1] SWICH[2] SWICH[3] SWICH[4] SWICH[5] SWICH[6] SWICH[7] 5 | .outputs LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 6 | .names $false 7 | .names $true 8 | 1 9 | .names $undef 10 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[0] O=LED0 11 | .attr module_not_derived 00000000000000000000000000000001 12 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 13 | .param LUT_INIT 0000000011111111 14 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[1] O=LED1 15 | .attr module_not_derived 00000000000000000000000000000001 16 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 17 | .param LUT_INIT 0000000011111111 18 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[2] O=LED2 19 | .attr module_not_derived 00000000000000000000000000000001 20 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 21 | .param LUT_INIT 0000000011111111 22 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[3] O=LED3 23 | .attr module_not_derived 00000000000000000000000000000001 24 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 25 | .param LUT_INIT 0000000011111111 26 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[4] O=LED4 27 | .attr module_not_derived 00000000000000000000000000000001 28 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 29 | .param LUT_INIT 0000000011111111 30 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[5] O=LED5 31 | .attr module_not_derived 00000000000000000000000000000001 32 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 33 | .param LUT_INIT 0000000011111111 34 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[6] O=LED6 35 | .attr module_not_derived 00000000000000000000000000000001 36 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 37 | .param LUT_INIT 0000000011111111 38 | .gate SB_LUT4 I0=$false I1=$false I2=$false I3=SWICH[7] O=LED7 39 | .attr module_not_derived 00000000000000000000000000000001 40 | .attr src "/usr/local/bin/../share/yosys/ice40/cells_map.v:41" 41 | .param LUT_INIT 0000000011111111 42 | .end 43 | -------------------------------------------------------------------------------- /demo/verilog/04_Dial Switch/dial_switch.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | //***************************************// 3 | //# @Author: 碎碎思 4 | //# @Date: 2019-04-14 19:54:50 5 | //# @Last Modified by: zlk 6 | //# @Last Modified time: 2019-04-14 21:36:06 7 | //****************************************// 8 | module dial_switch 9 | ( 10 | input CLK, 11 | input RST_n, 12 | 13 | input [7:0] SWICH, 14 | 15 | output LED0, 16 | output LED1, 17 | output LED2, 18 | output LED3, 19 | output LED4, 20 | output LED5, 21 | output LED6, 22 | output LED7 23 | ); 24 | 25 | wire [7:0]SWICH; 26 | 27 | 28 | //////////////////////////////////////////// 29 | 30 | 31 | assign {LED7,LED6,LED5,LED4,LED3,LED2,LED1,LED0}=~SWICH; 32 | 33 | endmodule // 34 | -------------------------------------------------------------------------------- /demo/verilog/04_Dial Switch/make_bin.sh: -------------------------------------------------------------------------------- 1 | yosys -p "synth_ice40 -blif dial_switch.blif" dial_switch.v 2 | 3 | arachne-pnr -d 5k -p ../openice.pcf dial_switch.blif -o dial_switch.asc 4 | 5 | icepack dial_switch.asc dial_switch.bin 6 | 7 | -------------------------------------------------------------------------------- /demo/verilog/05_7seg_count/7seg_count.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/05_7seg_count/7seg_count.bin -------------------------------------------------------------------------------- /demo/verilog/05_7seg_count/7seg_count.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | // Attach 7 segment display PMOD to Icebreaker PMOD1A port. 4 | 5 | module top( 6 | input CLK, 7 | output P1A1, 8 | output P1A2, 9 | output P1A3, 10 | output P1A4, 11 | output P1A7, 12 | output P1A8, 13 | output P1A9, 14 | output P1A10 15 | ); 16 | 17 | // Wiring external pins. 18 | reg [6:0] seg_pins_n; 19 | reg digit_sel; 20 | assign {P1A9, P1A8, P1A7, P1A4, P1A3, P1A2, P1A1} = seg_pins_n; 21 | assign P1A10 = digit_sel; 22 | 23 | // counter increments at CLK = 12 MHz. 24 | // ones digit increments at ~6Hz. 25 | // display refreshes at 375 KHz. 26 | reg [29:0] counter; 27 | wire [3:0] ones = counter[21+:4]; 28 | wire [3:0] tens = counter[25+:4]; 29 | wire [2:0] display_state = counter[2+:3]; 30 | 31 | reg [6:0] ones_segments; 32 | reg [6:0] tens_segments; 33 | 34 | digit_to_segments ones2segs(CLK, ones, ones_segments); 35 | digit_to_segments tens2segs(CLK, tens, tens_segments); 36 | 37 | always @(posedge CLK) begin 38 | counter <= counter + 1; 39 | 40 | // Switch seg_pins_n off during digit_sel transitions 41 | // to prevent flicker. Each digit has 25% duty cycle. 42 | case (display_state) 43 | 0, 1: seg_pins_n <= ~ones_segments; 44 | 2: seg_pins_n <= ~0; 45 | 3: digit_sel <= 0; 46 | 4, 5: seg_pins_n <= ~tens_segments; 47 | 6: seg_pins_n <= ~0; 48 | 7: digit_sel <= 1; 49 | endcase 50 | end 51 | 52 | endmodule // top 53 | 54 | // Get the segments to illuminate to display a single hex digit. 55 | // N.B., This is positive logic. Display needs negative. 56 | module digit_to_segments(input clk, 57 | input [3:0] digit, 58 | output reg[6:0] segments 59 | ); 60 | always @(posedge clk) 61 | case (digit) 62 | 0: segments <= 7'b0111111; 63 | 1: segments <= 7'b0000110; 64 | 2: segments <= 7'b1011011; 65 | 3: segments <= 7'b1001111; 66 | 4: segments <= 7'b1100110; 67 | 5: segments <= 7'b1101101; 68 | 6: segments <= 7'b1111101; 69 | 7: segments <= 7'b0000111; 70 | 8: segments <= 7'b1111111; 71 | 9: segments <= 7'b1101111; 72 | 4'hA: segments <= 7'b1110111; 73 | 4'hB: segments <= 7'b1111100; 74 | 4'hC: segments <= 7'b0111001; 75 | 4'hD: segments <= 7'b1011110; 76 | 4'hE: segments <= 7'b1111001; 77 | 4'hF: segments <= 7'b1110001; 78 | endcase 79 | 80 | endmodule 81 | -------------------------------------------------------------------------------- /demo/verilog/05_7seg_count/Makefile: -------------------------------------------------------------------------------- 1 | PROJ := 7seg_count 2 | PIN_DEF := ../icebreaker.pcf 3 | DEVICE := up5k 4 | 5 | include ../main.mk 6 | 7 | 8 | -------------------------------------------------------------------------------- /demo/verilog/05_7seg_count/make_bin.sh: -------------------------------------------------------------------------------- 1 | yosys -p "synth_ice40 -blif 7seg_count.blif" 7seg_count.v 2 | 3 | arachne-pnr -d 5k -p ../openice.pcf 7seg_count.blif -o 7seg_count.asc 4 | 5 | icepack 7seg_count.asc 7seg_count.bin 6 | 7 | -------------------------------------------------------------------------------- /demo/verilog/06_pwm_rgbled/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | 4 | ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}') 5 | ${warning iCELink path: $(ICELINK_DIR)} 6 | 7 | build: 8 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 9 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 10 | icepack $(filename).asc $(filename).bin 11 | 12 | prog: #for sram 13 | iceprog -S $(filename).bin 14 | 15 | 16 | 17 | 18 | clean: 19 | rm -rf $(filename).blif $(filename).asc #$(filename).bin 20 | -------------------------------------------------------------------------------- /demo/verilog/06_pwm_rgbled/pwm.v: -------------------------------------------------------------------------------- 1 | //pwm module, outputs a pulse width according to the value written 2 | //max width 255 cycles 3 | 4 | module pwm(input clk, input en, input [7:0] value_input, output out); 5 | reg [7:0] counter; 6 | reg [7:0] value; //max 255 7 | 8 | assign out = (counter < value); 9 | 10 | initial begin 11 | counter = 0; 12 | value = 255; 13 | end 14 | 15 | always @(posedge clk) 16 | begin 17 | counter <= counter + 1; 18 | 19 | if(en == 1'b1) begin 20 | value <= value_input; 21 | end; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/verilog/06_pwm_rgbled/top.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/06_pwm_rgbled/top.bin -------------------------------------------------------------------------------- /demo/verilog/06_pwm_rgbled/top.v: -------------------------------------------------------------------------------- 1 | `include "pwm.v" 2 | 3 | //light up the leds using the pwm module, starts at lowest value and then goes slowly to 4 | //128, then back to 0 5 | 6 | module top( input CLK, output LED_RED_N, output LED_GRN_N, output LED_BLU_N); 7 | 8 | reg [17:0] counter; 9 | reg [6:0] val_pwm; //only make it go to 128 (half brightness) 10 | 11 | //io for the pwm module 12 | wire pwm_en_write; 13 | wire [7:0] pwm_value_write; 14 | wire pwm_out; 15 | 16 | pwm pwm_inst( 17 | .clk(CLK), .en(pwm_en_write), .value_input(pwm_value_write), .out(pwm_out) 18 | ); 19 | 20 | //leds are active low 21 | assign LED_RED_N = ~pwm_out; 22 | assign LED_GRN_N = ~pwm_out; 23 | assign LED_BLU_N = ~pwm_out; 24 | 25 | initial begin 26 | pwm_en_write = 1; 27 | pwm_value_write = 0; 28 | val_pwm = 0; 29 | end 30 | 31 | always @(posedge CLK) 32 | begin 33 | 34 | pwm_en_write = 0; 35 | counter <= counter + 1; 36 | 37 | if(counter == 0) begin 38 | val_pwm <= val_pwm + 1; //increase the width of pwm 39 | pwm_en_write = 1; 40 | pwm_value_write <= val_pwm; 41 | end 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /demo/verilog/07_pwm_led/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | 4 | ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}') 5 | ${warning iCELink path: $(ICELINK_DIR)} 6 | 7 | build: 8 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 9 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 10 | icepack $(filename).asc $(filename).bin 11 | 12 | prog: #for sram 13 | iceprog -S $(filename).bin 14 | 15 | 16 | 17 | 18 | clean: 19 | rm -rf $(filename).blif $(filename).asc #$(filename).bin 20 | -------------------------------------------------------------------------------- /demo/verilog/07_pwm_led/pwm.v: -------------------------------------------------------------------------------- 1 | //pwm module, outputs a pulse width according to the value written 2 | //max width 255 cycles 3 | 4 | module pwm(input clk, input en, input [7:0] value_input, output out); 5 | reg [7:0] counter; 6 | reg [7:0] value; //max 255 7 | 8 | assign out = (counter < value); 9 | 10 | initial begin 11 | counter = 0; 12 | value = 255; 13 | end 14 | 15 | always @(posedge clk) 16 | begin 17 | counter <= counter + 1; 18 | 19 | if(en == 1'b1) begin 20 | value <= value_input; 21 | end; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /demo/verilog/07_pwm_led/top.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/07_pwm_led/top.bin -------------------------------------------------------------------------------- /demo/verilog/07_pwm_led/top.v: -------------------------------------------------------------------------------- 1 | `include "pwm.v" 2 | 3 | //light up the leds using the pwm module, starts at lowest value and then goes slowly to 4 | //128, then back to 0 5 | 6 | module top( input CLK, output LED ); 7 | 8 | reg [17:0] counter; 9 | reg [6:0] val_pwm; //only make it go to 128 (half brightness) 10 | 11 | //io for the pwm module 12 | wire pwm_en_write; 13 | wire [7:0] pwm_value_write; 14 | wire pwm_out; 15 | 16 | pwm pwm_inst( 17 | .clk(CLK), .en(pwm_en_write), .value_input(pwm_value_write), .out(pwm_out) 18 | ); 19 | 20 | //leds are active low 21 | assign LED = pwm_out; 22 | 23 | 24 | initial begin 25 | pwm_en_write = 1; 26 | pwm_value_write = 0; 27 | val_pwm = 0; 28 | end 29 | 30 | always @(posedge CLK) 31 | begin 32 | 33 | pwm_en_write = 0; 34 | counter <= counter + 1; 35 | 36 | if(counter == 0) begin 37 | val_pwm <= val_pwm + 1; //increase the width of pwm 38 | pwm_en_write = 1; 39 | pwm_value_write <= val_pwm; 40 | end 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /demo/verilog/08_pll/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | 4 | ICELINK_DIR=$(shell df | grep iCELink | awk '{print $$6}') 5 | ${warning iCELink path: $(ICELINK_DIR)} 6 | 7 | build: 8 | yosys -p "synth_ice40 -json $(filename).json -blif $(filename).blif" $(filename).v 9 | # arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 10 | nextpnr-ice40 --up5k --package sg48 --json $(filename).json --pcf $(pcf_file) --asc $(filename).asc --freq 48 11 | icepack $(filename).asc $(filename).bin 12 | 13 | clean: 14 | rm -rf $(filename).blif $(filename).asc $(filename).bin 15 | -------------------------------------------------------------------------------- /demo/verilog/08_pll/README.md: -------------------------------------------------------------------------------- 1 | # PLL and clock example 2 | 3 | This example shows how to use the internal oscillators as clocks and use the unique PLL in the iCE40 Ultraplus. 4 | 5 | The example blinks the LED at two different frequencies, one is the internal oscillator at 48MHz, the other clock is at 24MHz. 6 | The 24MHz frequency is obtained from the PLL, taking as input the 48MHz clock. 7 | 8 | The ice40 ultraplus has two internal clocks, 48MHz and 10KHz, the clock can be used, by taking the output signal of the `SB_HFOSC` module for the 48MHz freq and the `SB_LFOSC` for the 10KHz. 9 | 10 | The PLL module can be used either as `SB_PLL40_CORE` or `SB_PLL40_PAD`, the PAD will take an external IO clock as input (such as the 12MHz used in the breakout board). The CORE will take a signal clock (such as the internal one). 11 | 12 | It seems that if the CORE_PLL is used with an internal clock, it is not possible to have the 12MHz external clock. 13 | 14 | To get the configuration for the PLL, the `icepll` tool was used and it gives the parameters for the PLL to achieve the desired frequency: 15 | 16 | ``` 17 | ./icepll -i 48 -o 24 18 | 19 | F_PLLIN: 48.000 MHz (given) 20 | F_PLLOUT: 24.000 MHz (requested) 21 | F_PLLOUT: 24.000 MHz (achieved) 22 | 23 | FEEDBACK: SIMPLE 24 | F_PFD: 48.000 MHz 25 | F_VCO: 768.000 MHz 26 | 27 | DIVR: 0 (4'b0000) 28 | DIVF: 15 (7'b0001111) 29 | DIVQ: 5 (3'b101) 30 | 31 | FILTER_RANGE: 4 (3'b100) 32 | ``` 33 | 34 | The `nextpnr-ice40` tool is used for routing as it provides timing analysis. It is possible to set the clock constraints with a python file, however a simple frequency for all clocks can be used by adding `-freq 48` to the parameters for 48MHz clock. 35 | The output will be: 36 | 37 | ``` 38 | Info: Max frequency for clock 'clk_48mhz': 56.27 MHz (PASS at 48.00 MHz) 39 | Info: Max frequency for clock 'clk_24mhz_$glb_clk': 60.85 MHz (PASS at 48.00 MHz) 40 | 41 | Info: Max delay posedge clk_24mhz_$glb_clk -> : 9.98 ns 42 | Info: Max delay posedge clk_48mhz -> : 8.66 ns 43 | ``` 44 | -------------------------------------------------------------------------------- /demo/verilog/08_pll/top.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/08_pll/top.bin -------------------------------------------------------------------------------- /demo/verilog/08_pll/top.v: -------------------------------------------------------------------------------- 1 | //input external 12MHz clk disabled, as we are using the PLL with internal oscillator, having both don't seem possible 2 | module top(/*input clk,*/ output LED_RED_N, output LED_GRN_N, output LED_BLU_N); 3 | wire clk_48mhz; //internal 4 | wire clk_10khz; //internal 5 | wire clk_24mhz; 6 | 7 | reg [2:0] led; 8 | reg [24:0] counter_slow; 9 | reg [24:0] counter_fast; 10 | 11 | //leds are active low 12 | assign LED_RED_N = ~led[0]; 13 | assign LED_GRN_N = ~led[1]; 14 | assign LED_BLU_N = ~led[2]; 15 | 16 | //internal oscillators seen as modules 17 | SB_HFOSC SB_HFOSC_inst( 18 | .CLKHFEN(1), 19 | .CLKHFPU(1), 20 | .CLKHF(clk_48mhz) 21 | ); 22 | 23 | //10khz used for low power applications (or sleep mode) 24 | SB_LFOSC SB_LFOSC_inst( 25 | .CLKLFEN(1), 26 | .CLKLFPU(1), 27 | .CLKLF(clk_10khz) 28 | ); 29 | 30 | // // PLL pad with external clock, 31 | // // outputs 32MHz 32 | // SB_PLL40_PAD #( 33 | // .FEEDBACK_PATH("SIMPLE"), 34 | // .PLLOUT_SELECT("GENCLK"), 35 | // .DIVR(4'b0000), 36 | // .DIVF(7'b1010100), 37 | // .DIVQ(3'b101), 38 | // .FILTER_RANGE(3'b001), 39 | // ) SB_PLL40_CORE_inst ( 40 | // .RESETB(1'b1), 41 | // .BYPASS(1'b0), 42 | // .PACKAGEPIN(clk), 43 | // .PLLOUTCORE(clk_32mhz), 44 | // ); 45 | 46 | SB_PLL40_CORE #( 47 | .FEEDBACK_PATH("SIMPLE"), 48 | .PLLOUT_SELECT("GENCLK"), 49 | .DIVR(4'b0000), 50 | .DIVF(7'b0001111), 51 | .DIVQ(3'b101), 52 | .FILTER_RANGE(3'b100), 53 | ) SB_PLL40_CORE_inst ( 54 | .RESETB(1'b1), 55 | .BYPASS(1'b0), 56 | .PLLOUTCORE(clk_24mhz), 57 | .REFERENCECLK(clk_48mhz) 58 | ); 59 | 60 | initial begin 61 | led = 0; 62 | counter_slow = 0; 63 | counter_fast = 0; 64 | end 65 | 66 | always @(posedge clk_24mhz) 67 | begin 68 | counter_slow <= counter_slow + 1; 69 | if (counter_slow == 24*1024*1024) begin //will update led every second 70 | led[0] <= ~led[0]; 71 | counter_slow <= 0; 72 | end 73 | end 74 | 75 | always @(posedge clk_48mhz) 76 | begin 77 | counter_fast <= counter_fast + 1; 78 | if (counter_fast == 24*1024*1024) begin //will update led every 1/2 seconds 79 | led[1] <= ~led[1]; 80 | counter_fast <= 0; 81 | end 82 | end 83 | 84 | endmodule 85 | -------------------------------------------------------------------------------- /demo/verilog/09_music/Makefile: -------------------------------------------------------------------------------- 1 | chip.bin: music.v music.pcf 2 | yosys -q -p "synth_ice40 -blif chip.blif" music.v 3 | arachne-pnr -d 5k -P sg48 -p music.pcf chip.blif -o chip.txt 4 | icepack chip.txt chip.bin 5 | 6 | .PHONY: upload 7 | upload: 8 | cat chip.bin >/dev/ttyUSB0 9 | 10 | .PHONY: clean 11 | clean: 12 | $(RM) -f chip.blif chip.txt chip.ex chip.bin 13 | -------------------------------------------------------------------------------- /demo/verilog/09_music/music.pcf: -------------------------------------------------------------------------------- 1 | set_io speaker 34 2 | 3 | set_io clk 35 4 | 5 | -------------------------------------------------------------------------------- /demo/verilog/09_music/music.v: -------------------------------------------------------------------------------- 1 | module music(clk, speaker); 2 | input clk; 3 | output speaker; 4 | parameter clkdivider = 100000000/440/2; 5 | 6 | reg [16:0] counter; 7 | always @(posedge clk) if(counter==0) counter <= clkdivider-1; else counter <= counter-1; 8 | 9 | reg speaker; 10 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 11 | endmodule 12 | -------------------------------------------------------------------------------- /demo/verilog/10_music2/Makefile: -------------------------------------------------------------------------------- 1 | chip.bin: music.v music.pcf 2 | yosys -q -p "synth_ice40 -blif chip.blif" music.v 3 | arachne-pnr -d 5k -P sg48 -p music.pcf chip.blif -o chip.txt 4 | icepack chip.txt chip.bin 5 | 6 | .PHONY: upload 7 | prog_flash: 8 | icesprog chip.bin 9 | 10 | .PHONY: clean 11 | clean: 12 | $(RM) -f chip.blif chip.txt chip.ex chip.bin 13 | -------------------------------------------------------------------------------- /demo/verilog/10_music2/music.pcf: -------------------------------------------------------------------------------- 1 | set_io speaker 34 2 | 3 | set_io clk 35 4 | 5 | -------------------------------------------------------------------------------- /demo/verilog/10_music2/music.v: -------------------------------------------------------------------------------- 1 | module music(clk, speaker); 2 | input clk; 3 | output speaker; 4 | parameter clkdivider = 100000000/440/2; 5 | 6 | reg [23:0] tone; 7 | always @(posedge clk) tone <= tone+1; 8 | 9 | reg [16:0] counter; 10 | always @(posedge clk) if(counter==0) counter <= (tone[23] ? clkdivider-1 : clkdivider/2-1); else counter <= counter-1; 11 | 12 | reg speaker; 13 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 14 | endmodule 15 | -------------------------------------------------------------------------------- /demo/verilog/11_music2a/Makefile: -------------------------------------------------------------------------------- 1 | chip.bin: music.v music.pcf 2 | yosys -q -p "synth_ice40 -blif chip.blif" music.v 3 | arachne-pnr -d 5k -P sg48 -p music.pcf chip.blif -o chip.txt 4 | icepack chip.txt chip.bin 5 | 6 | .PHONY: prog_flash 7 | prog_flash: 8 | icesprog chip.bin 9 | 10 | .PHONY: clean 11 | clean: 12 | $(RM) -f chip.blif chip.txt chip.ex chip.bin 13 | -------------------------------------------------------------------------------- /demo/verilog/11_music2a/music.pcf: -------------------------------------------------------------------------------- 1 | set_io speaker 34 2 | 3 | set_io clk 35 4 | 5 | -------------------------------------------------------------------------------- /demo/verilog/11_music2a/music.v: -------------------------------------------------------------------------------- 1 | module music(clk, speaker); 2 | input clk; 3 | output speaker; 4 | 5 | reg [27:0] tone; 6 | always @(posedge clk) tone <= tone+1; 7 | 8 | wire [6:0] fastsweep = (tone[22] ? tone[21:15] : ~tone[21:15]); 9 | wire [6:0] slowsweep = (tone[25] ? tone[24:18] : ~tone[24:18]); 10 | wire [16:0] clkdivider = {2'b01, (tone[27] ? slowsweep : fastsweep), 6'b00000000}; 11 | 12 | reg [14:0] counter; 13 | always @(posedge clk) if(counter==0) counter <= clkdivider; else counter <= counter-1; 14 | 15 | reg speaker; 16 | always @(posedge clk) if(counter==0) speaker <= ~speaker; 17 | endmodule 18 | -------------------------------------------------------------------------------- /demo/verilog/12_music3/Makefile: -------------------------------------------------------------------------------- 1 | chip.bin: music.v music.pcf divide_by12.v 2 | yosys -q -p "synth_ice40 -blif chip.blif" music.v divide_by12.v 3 | arachne-pnr -d 5k -P sg48 -p music.pcf chip.blif -o chip.txt 4 | icepack chip.txt chip.bin 5 | 6 | .PHONY: prog_flash 7 | prog_flash: 8 | icesprog chip.bin 9 | 10 | .PHONY: clean 11 | clean: 12 | $(RM) -f chip.blif chip.txt chip.ex chip.bin 13 | -------------------------------------------------------------------------------- /demo/verilog/12_music3/divide_by12.v: -------------------------------------------------------------------------------- 1 | module divide_by12(numer, quotient, remain); 2 | input [5:0] numer; 3 | output [2:0] quotient; 4 | output [3:0] remain; 5 | 6 | reg [2:0] quotient; 7 | reg [3:0] remain_bit3_bit2; 8 | 9 | assign remain = {remain_bit3_bit2, numer[1:0]}; // the first 2 bits are copied through 10 | 11 | always @(numer[5:2]) // and just do a divide by "3" on the remaining bits 12 | case(numer[5:2]) 13 | 0: begin quotient=0; remain_bit3_bit2=0; end 14 | 1: begin quotient=0; remain_bit3_bit2=1; end 15 | 2: begin quotient=0; remain_bit3_bit2=2; end 16 | 3: begin quotient=1; remain_bit3_bit2=0; end 17 | 4: begin quotient=1; remain_bit3_bit2=1; end 18 | 5: begin quotient=1; remain_bit3_bit2=2; end 19 | 6: begin quotient=2; remain_bit3_bit2=0; end 20 | 7: begin quotient=2; remain_bit3_bit2=1; end 21 | 8: begin quotient=2; remain_bit3_bit2=2; end 22 | 9: begin quotient=3; remain_bit3_bit2=0; end 23 | 10: begin quotient=3; remain_bit3_bit2=1; end 24 | 11: begin quotient=3; remain_bit3_bit2=2; end 25 | 12: begin quotient=4; remain_bit3_bit2=0; end 26 | 13: begin quotient=4; remain_bit3_bit2=1; end 27 | 14: begin quotient=4; remain_bit3_bit2=2; end 28 | 15: begin quotient=5; remain_bit3_bit2=0; end 29 | endcase 30 | endmodule 31 | -------------------------------------------------------------------------------- /demo/verilog/12_music3/music.pcf: -------------------------------------------------------------------------------- 1 | set_io speaker 34 2 | 3 | set_io clk 35 4 | 5 | -------------------------------------------------------------------------------- /demo/verilog/12_music3/music.v: -------------------------------------------------------------------------------- 1 | module music(clk, speaker); 2 | input clk; 3 | output speaker; 4 | 5 | reg [27:0] tone; 6 | always @(posedge clk) tone <= tone+1; 7 | 8 | wire [5:0] fullnote = tone[27:22]; 9 | 10 | wire [2:0] octave; 11 | wire [3:0] note; 12 | divide_by12 divby12(.numer(fullnote[5:0]), .quotient(octave), .remain(note)); 13 | 14 | reg [10:0] clkdivider; 15 | always @(note) 16 | case(note) 17 | 0: clkdivider = (512-1) << 2; // A 18 | 1: clkdivider = (483-1) << 2; // A#/Bb 19 | 2: clkdivider = (456-1) << 2; // B 20 | 3: clkdivider = (431-1) << 2; // C 21 | 4: clkdivider = (406-1) << 2; // C#/Db 22 | 5: clkdivider = (384-1) << 2; // D 23 | 6: clkdivider = (362-1) << 2; // D#/Eb 24 | 7: clkdivider = (342-1) << 2; // E 25 | 8: clkdivider = (323-1) << 2; // F 26 | 9: clkdivider = (304-1) << 2; // F#/Gb 27 | 10: clkdivider = (287-1) << 2; // G 28 | 11: clkdivider = (271-1) << 2; // G#/Ab 29 | 12: clkdivider = 0; // should never happen 30 | 13: clkdivider = 0; // should never happen 31 | 14: clkdivider = 0; // should never happen 32 | 15: clkdivider = 0; // should never happen 33 | endcase 34 | 35 | reg [8:0] counter_note; 36 | always @(posedge clk) if(counter_note==0) counter_note <= clkdivider; else counter_note <= counter_note-1; 37 | 38 | reg [7:0] counter_octave; 39 | always @(posedge clk) 40 | if(counter_note==0) 41 | begin 42 | if(counter_octave==0) 43 | counter_octave <= (octave==0?255:octave==1?127:octave==2?63:octave==3?31:octave==4?15:7); 44 | else 45 | counter_octave <= counter_octave-1; 46 | end 47 | 48 | reg speaker; 49 | always @(posedge clk) if(counter_note==0 && counter_octave==0) speaker <= ~speaker; 50 | endmodule 51 | -------------------------------------------------------------------------------- /demo/verilog/13_music4/Makefile: -------------------------------------------------------------------------------- 1 | chip.bin: music.v music.pcf 2 | yosys -q -p "synth_ice40 -blif chip.blif" music.v 3 | arachne-pnr -d 5k -P sg48 -p music.pcf chip.blif -o chip.txt 4 | icepack chip.txt chip.bin 5 | 6 | .PHONY: prog_flash 7 | prog_flash: 8 | icesprog chip.bin 9 | 10 | .PHONY: clean 11 | clean: 12 | $(RM) -f chip.blif chip.txt chip.ex chip.bin 13 | -------------------------------------------------------------------------------- /demo/verilog/13_music4/music.pcf: -------------------------------------------------------------------------------- 1 | set_io speaker 34 2 | 3 | set_io clk 35 4 | 5 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/5k.pcf: -------------------------------------------------------------------------------- 1 | 2 | ### Clock 3 | set_io clk 35 4 | 5 | set_io --warn-no-port ws_data 45 6 | 7 | 8 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/8k.pcf: -------------------------------------------------------------------------------- 1 | ################################### 2 | # Physical constraints file (pcf) # 3 | # for iCE40HX8K-CT256 # 4 | ################################### 5 | 6 | 7 | ### Clock 8 | set_io clk J3 9 | 10 | ### LEDs 11 | set_io --warn-no-port LED[0] B5 12 | set_io --warn-no-port LED[1] B4 13 | set_io --warn-no-port LED[2] A2 14 | set_io --warn-no-port LED[3] A1 15 | set_io --warn-no-port LED[4] C5 16 | set_io --warn-no-port LED[5] C4 17 | set_io --warn-no-port LED[6] B3 18 | set_io --warn-no-port LED[7] C3 19 | 20 | set_io --warn-no-port ws_data C16 21 | 22 | 23 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/Makefile: -------------------------------------------------------------------------------- 1 | PACKAGE = sg48 2 | DEVICE = up5k 3 | PROJ = ws2812 4 | PIN_DEF = 5k.pcf 5 | SEED = 10 6 | SHELL := /bin/bash # Use bash syntax 7 | BUILD_DIR = ./build 8 | SRC_DIR = ./ 9 | TEST_DIR = ./ 10 | 11 | all: $(BUILD_DIR) $(BUILD_DIR)/$(PROJ).bin 12 | #all: $(BUILD_DIR)/$(PROJ).bin $(BUILD_DIR)/$(PROJ).rpt formal 13 | 14 | MODULES = ws2812.v 15 | VERILOG = top.v $(MODULES) 16 | SRC = $(foreach ii,$(VERILOG),$(addprefix $(SRC_DIR)/, $(ii))) 17 | 18 | # $@ The file name of the target of the rule.rule 19 | # $< first pre requisite 20 | # $^ names of all preerquisites 21 | 22 | $(BUILD_DIR): 23 | mkdir -p $(BUILD_DIR) 24 | 25 | # rules for building the blif file 26 | $(BUILD_DIR)/%.json: $(SRC) 27 | yosys -l $(BUILD_DIR)/build.log -p 'synth_ice40 -top top -json $(BUILD_DIR)/$(PROJ).json' $(SRC) 28 | 29 | # asc 30 | $(BUILD_DIR)/%.asc: $(BUILD_DIR)/%.json $(PIN_DEF) 31 | nextpnr-ice40 -l $(BUILD_DIR)/nextpnr.log --seed $(SEED) --freq 20 --package $(PACKAGE) --$(DEVICE) --asc $@ --pcf $(PIN_DEF) --json $< 32 | 33 | # bin, for programming 34 | $(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.asc 35 | icepack $< $@ 36 | 37 | # timing 38 | $(BUILD_DIR)/%.rpt: $(BUILD_DIR)/%.asc 39 | icetime -d $(DEVICE) -mtr $@ $< 40 | 41 | debug: 42 | iverilog -o ws2812.out ws2812.v ws2812_tb.v 43 | vvp ws2812.out -fst 44 | gtkwave test.vcd gtk-ws2812.gtkw 45 | 46 | prog: $(BUILD_DIR)/$(PROJ).bin 47 | icesprog $< 48 | 49 | formal: 50 | sby -f $(PROJ).sby || gtkwave $(PROJ)/engine_0/*vcd ws2812_formal.gtkw 51 | 52 | clean: 53 | rm -f $(BUILD_DIR)/* 54 | 55 | #secondary needed or make will remove useful intermediate files 56 | .SECONDARY: 57 | .PHONY: all prog clean formal debug 58 | 59 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/README.md: -------------------------------------------------------------------------------- 1 | # WS2812 core 2 | 3 | adapt from https://github.com/mattvenn/ws2812-core.git 4 | 5 | very simple WS2812 LED driver written in Verilog. Demonstrates timing is working. 6 | 7 | * Parameter NUM_LEDS sets the number of LEDs in the chain (up to 255) 8 | * Data is RGB format, 24 bits. 9 | * Data for each LED is loaded with the write signal 10 | * expects clock to be 12 MHz 11 | 12 | ![ws2812](ws2812.jpg) 13 | 14 | # Makefile 15 | 16 | make debug 17 | 18 | Use iverilog to run the testbench and show the results with gtkwave 19 | 20 | ![gtkwave](gtkwave.png) 21 | 22 | make formal 23 | 24 | Use symbiyosys to formally prove certain aspects of the core 25 | 26 | make prog 27 | 28 | Synthesise and program bitstream to 8k dev board. 29 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/gtk-ws2812.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Wed Sep 5 16:38:43 2018 4 | [*] 5 | [dumpfile] "/home/matt/work/fpga/ws2812/test.vcd" 6 | [dumpfile_mtime] "Wed Sep 5 16:38:01 2018" 7 | [dumpfile_size] 2803 8 | [savefile] "/home/matt/work/fpga/ws2812/gtk-ws2812.gtkw" 9 | [timestart] 0 10 | [size] 2308 1042 11 | [pos] -1 -1 12 | *-10.028861 7335 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] test. 14 | [sst_width] 253 15 | [signals_width] 371 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 314 18 | @28 19 | test.ws2812_inst.clk 20 | test.ws2812_inst.reset 21 | @24 22 | test.ws2812_inst.rgb_counter[4:0] 23 | test.ws2812_inst.bit_counter[9:0] 24 | @22 25 | test.ws2812_inst.led_counter[3:0] 26 | @28 27 | test.ws2812_inst.state[1:0] 28 | @200 29 | - 30 | @28 31 | test.ws2812_inst.data 32 | @200 33 | - 34 | @29 35 | test.ws2812_inst.write 36 | @22 37 | test.ws2812_inst.led_num[7:0] 38 | test.ws2812_inst.rgb_data[23:0] 39 | test.ws2812_inst.\led_reg[0][23:0] 40 | @200 41 | - 42 | [pattern_trace] 1 43 | [pattern_trace] 0 44 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/gtkwave.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/14_ws2812/gtkwave.png -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/test.vcd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/14_ws2812/test.vcd -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/top.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module top ( 4 | input clk, 5 | output ws_data 6 | ); 7 | 8 | localparam NUM_LEDS = 64; 9 | 10 | reg reset = 1; 11 | always @(posedge clk) 12 | reset <= 0; 13 | 14 | reg [18:0] count = 0; 15 | reg [1:0] color_ind = 0; 16 | always @(posedge clk) begin 17 | count <= count + 1; 18 | if (&count) begin 19 | if (led_num == NUM_LEDS) begin 20 | led_num <= 0; 21 | color_ind <= color_ind + 1; 22 | case (color_ind) 23 | 2'b00 : led_rgb_data <= 24'h10_00_00; 24 | 2'b01 : led_rgb_data <= 24'h00_10_00; 25 | 2'b10 : led_rgb_data <= 24'h00_00_10; 26 | 2'b11 : led_rgb_data <= 24'h10_10_10; 27 | endcase 28 | end else 29 | led_num <= led_num + 1; 30 | end 31 | end 32 | 33 | reg [23:0] led_rgb_data = 24'h00_00_10; 34 | reg [7:0] led_num = 0; 35 | wire led_write = &count; 36 | 37 | ws2812 #(.NUM_LEDS(NUM_LEDS)) ws2812_inst(.data(ws_data), .clk(clk), .reset(reset), .rgb_data(led_rgb_data), .led_num(led_num), .write(led_write)); 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/ws2812.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/demo/verilog/14_ws2812/ws2812.jpg -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/ws2812.sby: -------------------------------------------------------------------------------- 1 | [options] 2 | mode prove 3 | depth 30 4 | 5 | [engines] 6 | smtbmc 7 | 8 | [script] 9 | read -formal ws2812.v 10 | prep -top ws2812 11 | 12 | [files] 13 | ws2812.v 14 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/ws2812_formal.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI 3 | [*] Tue Sep 4 15:11:19 2018 4 | [*] 5 | [dumpfile] "/home/matt/work/fpga/ws2812/ws2812/engine_0/trace.vcd" 6 | [dumpfile_mtime] "Tue Sep 4 15:10:51 2018" 7 | [dumpfile_size] 1110 8 | [savefile] "/home/matt/work/fpga/ws2812/hit_proc_formal.gtkw" 9 | [timestart] 0 10 | [size] 1715 892 11 | [pos] 946 119 12 | *-4.296556 290 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [sst_width] 253 14 | [signals_width] 385 15 | [sst_expanded] 1 16 | [sst_vpaned_height] 260 17 | @28 18 | ws2812.clk 19 | ws2812.reset 20 | @24 21 | ws2812.bit_counter[9:0] 22 | ws2812.rgb_counter[4:0] 23 | ws2812.led_counter[3:0] 24 | @28 25 | ws2812.data 26 | ws2812.state[1:0] 27 | @22 28 | ws2812.led_num[7:0] 29 | @28 30 | ws2812.write 31 | @23 32 | ws2812.rgb_data[23:0] 33 | @22 34 | ws2812.led_reg<0>[23:0] 35 | [pattern_trace] 1 36 | [pattern_trace] 0 37 | -------------------------------------------------------------------------------- /demo/verilog/14_ws2812/ws2812_tb.v: -------------------------------------------------------------------------------- 1 | module test; 2 | 3 | reg clk = 0; 4 | reg reset = 1; 5 | reg [7:0] led_num = 0; 6 | reg write = 0; 7 | reg [23:0] rgb_data = 0; 8 | 9 | initial begin 10 | $dumpfile("test.vcd"); 11 | $dumpvars(0,test); 12 | $dumpvars(1,ws2812_inst.led_reg[0]); 13 | # 20 14 | reset <= 0; 15 | # 10 16 | led_num <= 0; 17 | rgb_data <= 24'hAA_CC_DD; 18 | write <= 1; 19 | # 2; 20 | write <= 0; 21 | 22 | 23 | repeat (6) begin 24 | wait(ws2812_inst.led_counter == 0); 25 | wait(ws2812_inst.state == 1); 26 | end 27 | 28 | $finish; 29 | end 30 | 31 | ws2812 #(.NUM_LEDS(4)) ws2812_inst(.clk(clk), .reset(reset), .rgb_data(rgb_data), .led_num(led_num), .write(write)); 32 | /* Make a regular pulsing clock. */ 33 | always #1 clk = !clk; 34 | 35 | endmodule // test 36 | 37 | -------------------------------------------------------------------------------- /demo/verilog/15_bram/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | 4 | ICEPROG = iceprog 5 | 6 | build: 7 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 8 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 9 | icepack $(filename).asc $(filename).bin 10 | 11 | recode: 12 | rm -f $(REAL_HEX) $(filename).bin 13 | $(MAKE) prog 14 | 15 | prog: $(filename).bin 16 | $(ICEPROG) $< 17 | 18 | sudo-prog: $(filename).bin 19 | @echo 'Executing prog as root!!!' 20 | sudo $(ICEPROG) $< 21 | # -S -IB 22 | clean: 23 | rm -rf $(filename).blif $(filename).asc $(filename).bin 24 | -------------------------------------------------------------------------------- /demo/verilog/15_bram/README.md: -------------------------------------------------------------------------------- 1 | # BRAM example 2 | 3 | The goal of this example was to understand how yosys infer BRAM from verlog arrays. 4 | The ice40 ultraplus has 30 BRAM of 4kbit, and each BRAM can save a lot of LUT logic, so understanding how they are used is important. 5 | 6 | Two versions of a simple memory module are implemented, on is implemented using a verilog array to be transformed into a BRAM durin synthesis, 7 | the other one using an explicit BRAM module (SB_RAM40_4K) used to compare its behaviour with the inferred one. 8 | 9 | Once the fpga is programmed, it will store the value `3'b010` (green) at address 0x14 and `3'b110` (light blue) at address 0x15. 10 | It will then read address 0x14 and display it on the LED, wait 24M cycles (2sec at 12MHz) read 0x15 and display it. 11 | 12 | A few things I have learned doing this example: 13 | - It isn't possible to do a read and write at the same time to a bram (should have a rd_en and wr_en signals) 14 | - Both read and write to the verilog array should be clocked so that it can be "inferrable", ```data_out <= mem[rd_addr]```, instead of ```assign data_out = mem[rd_addr]``` 15 | - In the implicit bram, ```data_out <= mem[rd_addr]```, should be the only assignment to ```data_out```, any other assignment will cause yosys to use logic instead of bram 16 | - BRAMs, at least when inferred and when programming the fgpa with the sram, need a small amount of cycles (~60) to be init, this seems to be a hardware issue. 17 | -------------------------------------------------------------------------------- /demo/verilog/15_bram/explicit_bram.v: -------------------------------------------------------------------------------- 1 | //manualy using the bram to implement a small memory 2 | 3 | module explicit_bram(input wire clk, input wire rd_en, input wire wr_en, input wire [7:0] rd_addr, input wire [7:0] wr_addr, input wire [15:0] data_in, output reg [15:0] data_out, output reg valid_out); 4 | 5 | wire [15:0] rdata; 6 | reg [10:0] raddr; 7 | reg [10:0] waddr; 8 | reg [15:0] mask; 9 | reg [15:0] wdata; 10 | reg rclke; 11 | reg re; 12 | reg wclke; 13 | reg we; 14 | 15 | SB_RAM40_4K SB_RAM40_4K_inst( 16 | .RDATA(rdata), .RADDR(raddr), .WADDR(waddr), .MASK(mask), .WDATA(wdata), .RCLKE(rclke), .RCLK(clk), .RE(re), .WCLKE(wclke), .WCLK(clk), .WE(we) 17 | ); 18 | 19 | initial begin 20 | raddr = 0; 21 | waddr = 0; 22 | mask = 0; //active low 23 | wdata = 0; 24 | rclke = 1; 25 | re = 0; 26 | wclke = 1; 27 | we = 0; 28 | end 29 | 30 | always @(posedge clk) 31 | begin 32 | 33 | if(wr_en == 1) begin 34 | waddr <= wr_addr; 35 | wdata <= data_in; 36 | we <= 1; 37 | end 38 | if (rd_en == 1) begin 39 | raddr <= rd_addr; 40 | re <= 1; 41 | valid_out <= 1; 42 | data_out <= rdata; 43 | end 44 | end 45 | endmodule 46 | -------------------------------------------------------------------------------- /demo/verilog/15_bram/implicit_bram.v: -------------------------------------------------------------------------------- 1 | //this should be transformed into a bram when doing a synthesis in yosys 0.8 2 | //and it should be equivalent to the explicit_bram.v 3 | 4 | module implicit_bram(input wire clk, input wire rd_en, input wire wr_en, input wire [7:0] rd_addr, input wire [7:0] wr_addr, input wire [15:0] data_in, output reg [15:0] data_out, output reg valid_out); 5 | 6 | reg [15:0] memory [0:255]; 7 | integer i; 8 | 9 | initial begin 10 | for(i = 0; i <= 255; i=i+1) begin 11 | memory[i] = 16'b001; 12 | end 13 | // data_out = 0; //should not exist if we want bram to be inferred 14 | valid_out = 0; 15 | end 16 | 17 | always @(posedge clk) 18 | begin 19 | // default 20 | valid_out <= 0; 21 | 22 | if(wr_en) begin 23 | memory[wr_addr] <= data_in; 24 | end 25 | if (rd_en) begin 26 | data_out <= memory[rd_addr]; 27 | valid_out <= 1; 28 | end 29 | end 30 | endmodule 31 | -------------------------------------------------------------------------------- /demo/verilog/16_dsp/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | ICEPROG = iceprog 4 | 5 | build: 6 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 7 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 8 | icepack $(filename).asc $(filename).bin 9 | 10 | sudo-prog: $(filename).bin 11 | @echo 'Executing prog as root!!!' 12 | sudo $(ICEPROG) $< 13 | 14 | clean: 15 | rm -rf $(filename).blif $(filename).asc $(filename).bin 16 | -------------------------------------------------------------------------------- /demo/verilog/16_dsp/README.md: -------------------------------------------------------------------------------- 1 | # DSP example on ice40 ultraplus 2 | 3 | This example show how to use the DSP blocks (`SB_MAC16`) within the ice40 ultraplus fpga to implement MAC (multiply and accumulate) operations. The sequence of operations are the following: 4 | 5 | ``` 6 | a <- 127 7 | a <- a + (a*5) 8 | a <- a + (a*a) 9 | a == 581406 10 | ``` 11 | If the result of this calculation is correct, it will light up the LED as white. 12 | 13 | Two implementations of this calculation are made, one without DSP `calc.v` and the other using a DSP block `calc_dsp.v`, they apply the above calculation one operation per cycle and light up the led if the result is correct. 14 | 15 | DSP block can be added to a module as `SB_MAC16`, they need some parameters in order to define if they will be used as multipliers or adders, in this example, the DSP is used as a MAC with 16x16bits inputs and 32bit output, by putting `2` to the two parameters `TOPADDSUB_LOWERINPUT` and `BOTADDSUB_LOWERINPUT`. 16 | 17 | Here are the fpga elements usage for both implementations, the multiplications have a serious impact on logic cell usage when not using a DSP: 18 | 19 | | element | calc.v | calc_dsp.v | 20 | |---|---|---| 21 | | LCs | 1280 | 64 | 22 | | MAC16s | 0 | 1 | 23 | 24 | The two modules, with and without the dsp are in the `top.v` file, only one can be used at once. 25 | 26 | To note that in a very recent or future implementation of yosys, it will be able to infer DSP from the verilog (https://twitter.com/oe1cxw/status/1098647996445659136?lang=en). 27 | -------------------------------------------------------------------------------- /demo/verilog/16_dsp/calc.v: -------------------------------------------------------------------------------- 1 | module calc(input clk, output correct); 2 | reg [3:0] state; 3 | reg [31:0] value; 4 | reg out_val; 5 | 6 | assign correct = out_val; 7 | 8 | initial begin 9 | state = 0; 10 | value = 0; 11 | out_val = 0; 12 | end 13 | 14 | always @(posedge clk) 15 | begin 16 | 17 | if(state < 15) 18 | begin 19 | state <= state + 1; 20 | end 21 | 22 | case (state) 23 | 0: begin 24 | value <= 127; 25 | end 26 | 1: begin 27 | value <= value + (value*5); 28 | end 29 | 2: begin 30 | value <= value + (value*value); 31 | end 32 | 3: begin 33 | if(value == 581406) 34 | begin 35 | out_val <= 1; 36 | end 37 | end 38 | default: begin 39 | end 40 | endcase 41 | 42 | end 43 | endmodule 44 | -------------------------------------------------------------------------------- /demo/verilog/16_dsp/calc_dsp.v: -------------------------------------------------------------------------------- 1 | module calc_dsp(input clk, output correct); 2 | reg [3:0] state; 3 | reg out_val; 4 | 5 | assign correct = out_val; 6 | reg dsp_ce; 7 | reg [15:0] dsp_c; 8 | reg [15:0] dsp_a; 9 | reg [15:0] dsp_b; 10 | reg [15:0] dsp_d; 11 | reg dsp_irsttop; 12 | reg dsp_irstbot; 13 | reg dsp_orsttop; 14 | reg dsp_orstbot; 15 | reg dsp_ahold; 16 | reg dsp_bhold; 17 | reg dsp_chold; 18 | reg dsp_dhold; 19 | reg dsp_oholdtop; 20 | reg dsp_oholdbot; 21 | reg dsp_addsubtop; 22 | reg dsp_addsubbot; 23 | reg dsp_oloadtop; 24 | reg dsp_oloadbot; 25 | reg dsp_ci; 26 | 27 | wire [31:0] dsp_o; 28 | wire dsp_co; 29 | 30 | //setup the dsp, parameters TOPADDSUB_LOWERINPUT and BOTADDSUB_LOWERINPUT at 2 means we can use MAC operations 31 | SB_MAC16 #(.C_REG(0), .A_REG(0), .B_REG(0), .D_REG(0), .TOP_8x8_MULT_REG(0), .BOT_8x8_MULT_REG(0), 32 | .PIPELINE_16x16_MULT_REG1(0), .PIPELINE_16x16_MULT_REG2(0), .TOPOUTPUT_SELECT(0), .TOPADDSUB_LOWERINPUT(2), 33 | .TOPADDSUB_UPPERINPUT(0), .TOPADDSUB_CARRYSELECT(0), .BOTOUTPUT_SELECT(0), .BOTADDSUB_LOWERINPUT(2), .BOTADDSUB_UPPERINPUT(0), 34 | .BOTADDSUB_CARRYSELECT(0), .MODE_8x8(0), .A_SIGNED(0), .B_SIGNED(0)) 35 | SB_MAC16_inst( 36 | .CLK(clk), .CE(dsp_ce), .C(dsp_c), .A(dsp_a), .B(dsp_b), .D(dsp_d), 37 | .IRSTTOP(dsp_irsttop), .IRSTBOT(dsp_irstbot), .ORSTTOP(dsp_orsttop), .ORSTBOT(dsp_orstbot), 38 | .AHOLD(dsp_ahold), .BHOLD(dsp_bhold), .CHOLD(dsp_chold), .DHOLD(dsp_dhold), .OHOLDTOP(dsp_oholdtop), .OHOLDBOT(dsp_oholdbot), 39 | .ADDSUBTOP(dsp_addsubtop), .ADDSUBBOT(dsp_addsubbot), .OLOADTOP(dsp_oloadtop), .OLOADBOT(dsp_oloadbot), 40 | .CI(dsp_ci), .O(dsp_o), .CO(dsp_co) 41 | ); 42 | 43 | initial begin 44 | state = 0; 45 | out_val = 0; 46 | dsp_ce = 1; 47 | end 48 | 49 | always @(posedge clk) 50 | begin 51 | //default for the dsp 52 | dsp_ce <= 1; 53 | dsp_c <= 0; 54 | dsp_a <= 0; 55 | dsp_b <= 0; 56 | dsp_d <= 0; 57 | dsp_irsttop <= 0; 58 | dsp_irstbot <= 0; 59 | dsp_orsttop <= 0; 60 | dsp_orstbot <= 0; 61 | dsp_ahold <= 0; 62 | dsp_bhold <= 0; 63 | dsp_chold <= 0; 64 | dsp_dhold <= 0; 65 | dsp_oholdtop <= 0; 66 | dsp_oholdbot <= 0; 67 | dsp_addsubtop <= 0; 68 | dsp_addsubbot <= 0; 69 | dsp_oloadtop <= 0; 70 | dsp_oloadbot <= 0; 71 | dsp_ci <= 0; 72 | 73 | if(state < 15) 74 | begin 75 | state <= state + 1; 76 | end 77 | 78 | case (state) 79 | 0: begin // a <- 127 80 | dsp_d <= 127; 81 | dsp_oloadbot <= 1; //load in accumulator for bottom (lowest 16bits) 82 | end 83 | 1: begin // a <- 127 + (127*5) 84 | dsp_a <= dsp_o[15:0]; 85 | dsp_b <= 5; 86 | end 87 | 2: begin // a <- 762 + (762*762) 88 | dsp_a <= dsp_o[15:0]; 89 | dsp_b <= dsp_o[15:0]; 90 | end 91 | 3: begin 92 | if(dsp_o[31:0] == 581406) 93 | begin 94 | out_val <= 1; 95 | end 96 | end 97 | default: begin 98 | end 99 | endcase 100 | 101 | end 102 | endmodule 103 | -------------------------------------------------------------------------------- /demo/verilog/16_dsp/top.v: -------------------------------------------------------------------------------- 1 | `include "calc.v" 2 | `include "calc_dsp.v" 3 | 4 | module top(input CLK, output LED_RED_N, output LED_GRN_N, output LED_BLU_N); 5 | 6 | wire correct; 7 | 8 | //implementation without DSP 9 | // calc calc_inst( 10 | // .clk(clk), .correct(correct) 11 | // ); 12 | 13 | //implementation with DSP 14 | calc_dsp calc_dsp_inst( 15 | .clk(CLK), .correct(correct) 16 | ); 17 | 18 | //leds are active low 19 | assign LED_RED_N = ~correct; 20 | assign LED_GRN_N = ~correct; 21 | assign LED_BLU_N = ~correct; 22 | 23 | initial begin 24 | end 25 | 26 | always @(posedge CLK) 27 | begin 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /demo/verilog/17_flash/Makefile: -------------------------------------------------------------------------------- 1 | filename = top 2 | pcf_file = ../../pin_io/openice.pcf 3 | ICEPROG = iceprog 4 | 5 | build: 6 | yosys -p "synth_ice40 -blif $(filename).blif" $(filename).v 7 | arachne-pnr -d 5k -P sg48 -p $(pcf_file) $(filename).blif -o $(filename).asc 8 | icepack $(filename).asc $(filename).bin 9 | 10 | #prog: #for sram, not useful to read flash 11 | # iceprog -S $(filename).bin 12 | 13 | sudo-prog: $(filename).bin 14 | @echo 'Executing prog as root!!!' 15 | sudo $(ICEPROG) $< 16 | 17 | clean: 18 | rm -rf $(filename).blif $(filename).asc $(filename).bin 19 | -------------------------------------------------------------------------------- /demo/verilog/17_flash/README.md: -------------------------------------------------------------------------------- 1 | # Flash reading from the iCE40 UltraPlus 2 | 3 | The goal of this example is to read, from the ice40 ultraplus some data in the flash using the SPI as master. 4 | 5 | The flash_master folder contains the script and image to write in the flash at 1MB or 0x100000 offset 6 | 7 | The program `flash_master/prog.hex` which only contains the bytes `00, 01, 02, 03, 04` in binary format should be programmed to the fpga using the `flash_master/flash_program.sh`, which will write the .hex in the flash of the fpga with a 1MB offset. 8 | After that, the fpga can be programmed with `make prog`, the fpga will then wait 2 sec before accessing the flash, reading the byte at 0x100002 which should be 02, and display it on the LED (green). 9 | 10 | Don't forget to put the breakout board in flash mode using the jumpers on J6! 11 | 12 | flash chip: N25Q032A13ESC40F, datasheet can be found here: https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_32mb_3v_65nm.pdf 13 | 14 | minimal erase cycle: 100k 15 | 16 | Needs ~833Kb for the fpga bitstream (this is why `prog.hex` is written at 1MB) 17 | 18 | The flash chip has 32Mb or 4MB 19 | 20 | 1 make 21 | 2 make sudo-prog 22 | 3 sudo iceprog -o 0x100000 flash_master/prog.hex 23 | 24 | 25 | 26 | -------------------------------------------------------------------------------- /demo/verilog/17_flash/flash_master/flash_program.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | #write a simple hex to the flash with an offset of 1MB (starts at 0x100000) 4 | #iceprog -o 1M -n prog.hex 5 | 6 | icesprog -o 0x100000 prog.bin 7 | -------------------------------------------------------------------------------- /demo/verilog/17_flash/flash_master/prog.hex: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /demo/verilog/17_flash/top.v: -------------------------------------------------------------------------------- 1 | `include "spi_master.v" 2 | 3 | //this top verilog design sends a read request as well as an address (0x100000 or 1MB) to to the master spi module. 4 | //in flash master, prog.hex is written in the flash at the 0x100000 offset and contains 00, 01, 02, 03, 04 5 | //some of these values are read and displayed on the LED 6 | 7 | module top(input CLK, output LED_RED_N, output LED_GRN_N, output LED_BLU_N, output SPI_SCK, output SPI_SS, input SPI_IO0, output SPI_IO1); 8 | 9 | reg spi_reset; 10 | wire spi_addr_buffer_free; 11 | reg spi_addr_en; 12 | reg [23:0] spi_addr_data; 13 | wire spi_rd_data_available; 14 | reg spi_rd_ack; 15 | wire [31:0] spi_rd_data; 16 | 17 | parameter IDLE = 0, INIT=IDLE+1, SEND_ADDR_SPI=INIT+1, WAIT_READ_DATA=SEND_ADDR_SPI+1, DISPLAY_LED=WAIT_READ_DATA+1; 18 | 19 | reg [3:0] state; 20 | 21 | //from ice40 ultraplus datasheet, the miso/mosi are inverted in the ice40 when in flash-prog mode 22 | //ice_MOSI is flash_MISO (in) 23 | //ice_MISO is flash_MOSI (out) 24 | spi_master spi_master_inst(.clk(CLK), .reset(spi_reset), 25 | .SPI_SCK(SPI_SCK), .SPI_SS(SPI_SS), .SPI_MOSI(SPI_IO1), .SPI_MISO(SPI_IO0), 26 | .addr_buffer_free(spi_addr_buffer_free), .addr_en(spi_addr_en), .addr_data(spi_addr_data), 27 | .rd_data_available(spi_rd_data_available), .rd_ack(spi_rd_ack), .rd_data(spi_rd_data) 28 | ); 29 | 30 | reg [2:0] led; 31 | 32 | reg [23:0] spi_recv_data_reg; 33 | reg handle_data; 34 | 35 | reg [15:0] reg_bits_inversion; 36 | reg [31:0] counter; 37 | 38 | assign LED_RED_N = ~led[0]; 39 | assign LED_GRN_N = ~led[1]; 40 | assign LED_BLU_N = ~led[2]; 41 | 42 | initial begin 43 | spi_reset = 0; 44 | spi_addr_en = 0; 45 | spi_addr_data = 24'h100000; //1MB offset 46 | spi_rd_ack = 0; 47 | 48 | led = 0; 49 | spi_recv_data_reg = 0; 50 | handle_data = 0; 51 | 52 | state = INIT; 53 | 54 | counter = 0; 55 | end 56 | 57 | always @(posedge CLK) 58 | begin 59 | 60 | //defaults 61 | spi_rd_ack <= 0; 62 | spi_addr_en <= 0; 63 | 64 | case (state) 65 | INIT: begin 66 | counter <= counter + 1; 67 | //wait a bit before starting the SPI 68 | //if the spi module is started immediately, the behaviour seems strange 69 | if(counter == 32'h1000000) begin 70 | state <= SEND_ADDR_SPI; 71 | end 72 | end 73 | SEND_ADDR_SPI: begin 74 | // spi_addr_data <= 24'h100000; 75 | spi_addr_en <= 1; 76 | state <= WAIT_READ_DATA; 77 | end 78 | WAIT_READ_DATA: begin 79 | if(spi_rd_data_available == 1) begin 80 | //reads the three LSB of the third byte, so 0x100002, which should be 0x02 (green) 81 | //31:24 is the first byte, 23:16 the second and 15:8 is the third 82 | led <= spi_rd_data[10:8]; 83 | state <= DISPLAY_LED; 84 | spi_rd_ack <= 1; //resets the spi module back to read address 85 | end 86 | end 87 | 88 | DISPLAY_LED: begin 89 | //do nothing 90 | end 91 | endcase 92 | end 93 | 94 | endmodule 95 | -------------------------------------------------------------------------------- /demo/verilog/18_vga_pong/Makefile: -------------------------------------------------------------------------------- 1 | PROJ = pong 2 | 3 | PIN_DEF = pong.pcf 4 | DEVICE = up5k 5 | PACKAGE = sg48 6 | FREQ = 13 7 | ADD_SRC = hvsync_generator.v 8 | 9 | include ./main.mk 10 | -------------------------------------------------------------------------------- /demo/verilog/18_vga_pong/hvsync_generator.v: -------------------------------------------------------------------------------- 1 | module hvsync_generator(clk, vga_h_sync, vga_v_sync, inDisplayArea, CounterX, CounterY); 2 | input clk; 3 | output vga_h_sync, vga_v_sync; 4 | output inDisplayArea; 5 | output [9:0] CounterX; 6 | output [8:0] CounterY; 7 | 8 | ////////////////////////////////////////////////// 9 | reg [9:0] CounterX; 10 | reg [8:0] CounterY; 11 | wire CounterXmaxed = (CounterX==10'h2FF); 12 | 13 | always @(posedge clk) 14 | if(CounterXmaxed) 15 | CounterX <= 0; 16 | else 17 | CounterX <= CounterX + 1; 18 | 19 | always @(posedge clk) 20 | if(CounterXmaxed) CounterY <= CounterY + 1; 21 | 22 | reg vga_HS, vga_VS; 23 | always @(posedge clk) 24 | begin 25 | vga_HS <= (CounterX[9:4]==6'h2D); // change this value to move the display horizontally 26 | vga_VS <= (CounterY==500); // change this value to move the display vertically 27 | end 28 | 29 | reg inDisplayArea; 30 | always @(posedge clk) 31 | if(inDisplayArea==0) 32 | inDisplayArea <= (CounterXmaxed) && (CounterY<480); 33 | else 34 | inDisplayArea <= !(CounterX==639); 35 | 36 | assign vga_h_sync = ~vga_HS; 37 | assign vga_v_sync = ~vga_VS; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /demo/verilog/18_vga_pong/main.mk: -------------------------------------------------------------------------------- 1 | 2 | all: $(PROJ).rpt $(PROJ).bin 3 | 4 | %.blif: %.v $(ADD_SRC) $(ADD_DEPS) 5 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -blif $@' $< $(ADD_SRC) 6 | 7 | %.json: %.v $(ADD_SRC) $(ADD_DEPS) 8 | yosys -ql $*.log $(if $(USE_ARACHNEPNR),-DUSE_ARACHNEPNR) -p 'synth_ice40 -json $@' $< $(ADD_SRC) 9 | 10 | ifeq ($(USE_ARACHNEPNR),) 11 | %.asc: $(PIN_DEF) %.json 12 | nextpnr-ice40 --$(DEVICE) $(if $(PACKAGE),--package $(PACKAGE)) $(if $(FREQ),--freq $(FREQ)) --json $(filter-out $<,$^) --pcf $< --asc $@ 13 | else 14 | %.asc: $(PIN_DEF) %.blif 15 | arachne-pnr -d $(subst up,,$(subst hx,,$(subst lp,,$(DEVICE)))) $(if $(PACKAGE),-P $(PACKAGE)) -o $@ -p $^ 16 | endif 17 | 18 | 19 | %.bin: %.asc 20 | icepack $< $@ 21 | 22 | %.rpt: %.asc 23 | icetime $(if $(FREQ),-c $(FREQ)) -d $(DEVICE) -mtr $@ $< 24 | 25 | %_tb: %_tb.v %.v 26 | iverilog -o $@ $^ 27 | 28 | %_tb.vcd: %_tb 29 | vvp -N $< +vcd=$@ 30 | 31 | %_syn.v: %.blif 32 | yosys -p 'read_blif -wideports $^; write_verilog $@' 33 | 34 | %_syntb: %_tb.v %_syn.v 35 | iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v` 36 | 37 | %_syntb.vcd: %_syntb 38 | vvp -N $< +vcd=$@ 39 | 40 | prog: $(PROJ).bin 41 | iceprog $< 42 | 43 | sudo-prog: $(PROJ).bin 44 | @echo 'Executing prog as root!!!' 45 | sudo iceprog $< 46 | 47 | clean: 48 | rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin $(PROJ).json $(PROJ).log $(ADD_CLEAN) 49 | 50 | .SECONDARY: 51 | .PHONY: all prog clean 52 | -------------------------------------------------------------------------------- /demo/verilog/18_vga_pong/pong.pcf: -------------------------------------------------------------------------------- 1 | set_io clk12 35 2 | set_io vga_h_sync 42 3 | set_io vga_v_sync 36 4 | set_io vga_R 4 5 | set_io vga_R1 2 6 | set_io vga_R2 47 7 | set_io vga_R3 45 8 | 9 | set_io vga_G 43 10 | set_io vga_G1 38 11 | set_io vga_G2 34 12 | set_io vga_G3 31 13 | 14 | set_io vga_B 3 15 | set_io vga_B1 48 16 | set_io vga_B2 46 17 | set_io vga_B3 44 18 | 19 | set_io quadA 27 20 | set_io quadB 25 21 | 22 | -------------------------------------------------------------------------------- /demo/verilog/19_vga_rotate/Makefile: -------------------------------------------------------------------------------- 1 | # Project setup 2 | PROJ = vga-rotation 3 | DEVICE = 5k 4 | FOOTPRINT = sg48 5 | YOSYS_OPTS= -noautowire # Generate errors if wires were implicitly created 6 | ICEPROG = iceprog 7 | 8 | # Files 9 | FILES = top.v 10 | 11 | .PHONY: all clean burn 12 | 13 | all: 14 | # synthesize using Yosys 15 | yosys -ql pong.log -p 'synth_ice40 -json top.json' top.v 16 | # Place and route using arachne 17 | nextpnr-ice40 --up5k --package sg48 --freq 13 --json top.json --pcf pinmap.pcf --asc top.asc 18 | icetime -c 13 -d up5k -mtr top.rpt top.asc 19 | # Convert to bitstream using IcePack 20 | icepack top.asc top.bin 21 | 22 | sudo-prog: top.bin 23 | @echo 'Executing prog as root!!!' 24 | sudo $(ICEPROG) $< 25 | 26 | clean: 27 | rm *.asc *.rpt *.json *.log *.bin 28 | -------------------------------------------------------------------------------- /demo/verilog/19_vga_rotate/README.md: -------------------------------------------------------------------------------- 1 | ### A simple rotation+animation effect output over 8 color VGA. 2 | 3 | 4 | 5 | ![Imgur](http://i.imgur.com/hkCxPVC.jpg) 6 | -------------------------------------------------------------------------------- /demo/verilog/19_vga_rotate/pinmap.pcf: -------------------------------------------------------------------------------- 1 | set_io --warn-no-port r0 4 2 | set_io --warn-no-port g0 43 3 | set_io --warn-no-port b0 3 4 | set_io --warn-no-port hsync 42 5 | set_io --warn-no-port vsync 36 6 | set_io --warn-no-port clk_out 27 7 | set_io --warn-no-port clk_in 35 8 | -------------------------------------------------------------------------------- /doc/AdvancediCE40SPII2CHardenedIPUsageGuide.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/doc/AdvancediCE40SPII2CHardenedIPUsageGuide.pdf -------------------------------------------------------------------------------- /doc/Datasheet/C116647_轻触开关，5.2_5.2_1.5，2.55N，100000次，贴片_2018-12-13.PDF: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/doc/Datasheet/C116647_轻触开关，5.2_5.2_1.5，2.55N，100000次，贴片_2018-12-13.PDF -------------------------------------------------------------------------------- /doc/Datasheet/C375571_1206红绿蓝三色LED发光二极管_2019-07-29.PDF: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BitOpenFPGA/OpenICE/e46bd3eecd98d5c837db9ca0c7692e0a529f21ad/doc/Datasheet/C375571_1206红绿蓝三色LED发光二极管_2019-07-29.PDF -------------------------------------------------------------------------------- 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