├── .gitignore ├── LICENSE ├── Makefile ├── README.md ├── banner.png ├── footer.png ├── lib ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32L4xx │ │ │ └── Include │ │ │ ├── stm32l496xx.h │ │ │ ├── stm32l4xx.h │ │ │ └── system_stm32l4xx.h │ └── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_armclang_ltm.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv81mml.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm35p.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h └── STM32L4xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32l4xx_hal.h │ ├── stm32l4xx_hal_cortex.h │ ├── stm32l4xx_hal_def.h │ ├── stm32l4xx_hal_dma.h │ ├── stm32l4xx_hal_dma_ex.h │ ├── stm32l4xx_hal_exti.h │ ├── stm32l4xx_hal_flash.h │ ├── stm32l4xx_hal_flash_ex.h │ ├── stm32l4xx_hal_flash_ramfunc.h │ ├── stm32l4xx_hal_gpio.h │ ├── stm32l4xx_hal_gpio_ex.h │ ├── stm32l4xx_hal_i2c.h │ ├── stm32l4xx_hal_i2c_ex.h │ ├── stm32l4xx_hal_pwr.h │ ├── stm32l4xx_hal_pwr_ex.h │ ├── stm32l4xx_hal_rcc.h │ ├── stm32l4xx_hal_rcc_ex.h │ ├── stm32l4xx_hal_tim.h │ └── stm32l4xx_hal_tim_ex.h │ └── Src │ ├── stm32l4xx_hal.c │ ├── stm32l4xx_hal_cortex.c │ ├── stm32l4xx_hal_dma.c │ ├── stm32l4xx_hal_dma_ex.c │ ├── stm32l4xx_hal_exti.c │ ├── stm32l4xx_hal_flash.c │ ├── stm32l4xx_hal_flash_ex.c │ ├── stm32l4xx_hal_flash_ramfunc.c │ ├── stm32l4xx_hal_gpio.c │ ├── stm32l4xx_hal_i2c.c │ ├── stm32l4xx_hal_i2c_ex.c │ ├── stm32l4xx_hal_pwr.c │ ├── stm32l4xx_hal_pwr_ex.c │ ├── stm32l4xx_hal_rcc.c │ ├── stm32l4xx_hal_rcc_ex.c │ ├── stm32l4xx_hal_tim.c │ └── stm32l4xx_hal_tim_ex.c ├── project.yml ├── src ├── bsp │ ├── stm32l4xx_hal_conf.h │ ├── stm32l4xx_hal_msp.c │ ├── stm32l4xx_it.c │ ├── stm32l4xx_it.h │ ├── sys.c │ ├── sys.h │ ├── syscalls.c │ ├── sysmem.c │ └── system_stm32l4xx.c ├── main.c └── main.h ├── startup ├── STM32L496AGIX_FLASH.ld └── startup_stm32l496agix.s └── test ├── bsp └── test_sys.c ├── support └── .gitkeep └── test_main.c /.gitignore: -------------------------------------------------------------------------------- 1 | # Folders to ignore 2 | .vscode/ 3 | build/ 4 | 5 | # Exclude Object Files 6 | *.o 7 | *.map 8 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 BojanG72 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ################################################### 2 | ## TOP LEVEL MAKEFILE ## 3 | ################################################### 4 | 5 | # This makefile is used to wrap some of the ceedling 6 | # commands to make them easier to run in the terminal 7 | 8 | all: 9 | @echo " " 10 | @echo "#################################################################" 11 | @echo " Supported Commands " 12 | @echo "#################################################################" 13 | @echo " " 14 | @echo " make clean --- Remove all build artifacts ---" 15 | @echo " make release --- Run all unit tests and build release images ---" 16 | @echo " make build --- Build release image only ---" 17 | @echo " make test --- Run all unit tests ---" 18 | @echo " " 19 | 20 | # Remove all the build artifacts 21 | .PHONY: clean 22 | clean: 23 | ceedling clobber 24 | rm stmBase.map 25 | 26 | # Run all unit tests and build release image 27 | .PHONY: release 28 | release: 29 | ceedling verbosity[4] test:all release 30 | 31 | # Run all unit tests 32 | .PHONY: test 33 | test: 34 | ceedling test:all 35 | 36 | # Build release image only 37 | .PHONY: build 38 | fw_stm32: 39 | ceedling release -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ![Banner](https://github.com/BojanG72/STM32-Ceedling-Base/blob/main/banner.png) 2 | 3 | # STM32 & Ceedling Base Project 4 | 5 | ![GitHub](https://img.shields.io/github/last-commit/bojang72/stm32-ceedling-base) 6 | ![GitHub](https://img.shields.io/github/license/bojang72/STM32-Ceedling-Base) 7 | 8 | I created this project as a starting point for anyone looking to create production quality firmware for an embedded system running an STM32 9 | microcontroller. This project makes use of the [ceedling](http://www.throwtheswitch.org/ceedling) build system. I chose to centre this project 10 | around ceedling, because for software to be production quality it must contain unit tests. I found ceedling to be the easiest build system 11 | that incorporates unit testing for firmware development. 12 | 13 | This project is currently setup to compile for the STM32L496AG MCU, becuase I happen to have a dev kit with that processor. I included both the CMSIS, and 14 | HAL libraries for the MCU. If you would like to compile for a different MCU, you would need to replace the libraries in the lib folder as well as the startup code and linker script. The startup file and linker script is located in the startup folder. 15 | 16 | The ceedling project.yml file has been setup to compile for a cortex M4 processor when the release command is run, and will compile with whatever the default GCC compiler is 17 | installed on your host machine when the test command is run. 18 | 19 | # Table of contents 20 | 21 | - [Project Title](#project-title) 22 | - [Table of contents](#table-of-contents) 23 | - [Installation](#installation) 24 | - [Usage](#usage) 25 | - [License](#license) 26 | - [Footer](#footer) 27 | 28 | # Installation 29 | [(Back to top)](#table-of-contents) 30 | 31 | This project has a couple dependencies that are required before you can build and run the tests. 32 | 1) The Ceedling build system ---> [Here](http://www.throwtheswitch.org/ceedling) 33 | 2) GCC compiler for your host machine ---> [Here](https://gcc.gnu.org/install/binaries.html) 34 | 3) GCC compiler for your target ---> [Here](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads) 35 | 36 | Make sure you install the correct toolchain for your setup. The toolchains will vary depending on if your host machine is running linux or windows. The target compiler I listed here is for ARM MCUs, if your MCU is not ARM based then you will need to find the correct compiler for your MCU and modify the .yml file to use that compiler instead. 37 | 38 | Finally, make sure that you update your environment variables so that you can access these tools from anywhere in your host system. A simple way to check if they were installed correctly is to check the version for each of the tools from the terminal 39 | 40 | ``` 41 | ceedling version 42 | ``` 43 | ``` 44 | gcc --version 45 | ``` 46 | ``` 47 | arm-none-eabi-gcc --version 48 | ``` 49 | 50 | Once you have all the dependancies installed, you can then clone this repo and try to build and test the project. 51 | 52 | ``` 53 | git clone https://github.com/BojanG72/STM32-Ceedling-Base.git 54 | ``` 55 | 56 | # Usage 57 | [(Back to top)](#table-of-contents) 58 | 59 | To compile and run the unit tests on your host machine, navigate to the project folder and run the following command 60 | ``` 61 | ceedling test:all 62 | ``` 63 | To compile and build the binaries for the taget machine, run the following command 64 | ``` 65 | ceedling release 66 | ``` 67 | I like to run the following command for building the binaries and running all tests 68 | ``` 69 | ceedling verbosity[5] clobber test:all release 70 | ``` 71 | the verbosity command enables ceedling to print out all the traces generated by the compiler, which is very useful for debugging. The clobber command will remove all 72 | the previous artifacts generated by the compiler. This allows for a clean build each time. The release command will build the release binaries and the test:all command will run the unit tests. 73 | 74 | Depending on which editor or IDE you choose to use, you can create a hotkey to run this command at the push of a button. Additionally, because it can be run from the command line, this can be easily incorporated into whatever CI/CD pipeline you decide to use. If you do not have a CI/CD pipeline setup, I would highly recommend it for production level firmware. 75 | 76 | # License 77 | [(Back to top)](#table-of-contents) 78 | 79 | [MIT License](https://github.com/BojanG72/STM32-Ceedling-Base/blob/main/LICENSE) 80 | 81 | # Footer 82 | [(Back to top)](#table-of-contents) 83 | 84 | Leave a star in GitHub, and share this repo if you found it helpful. 85 | 86 | 87 | ![Footer](https://github.com/BojanG72/STM32-Ceedling-Base/blob/main/footer.png) 88 | -------------------------------------------------------------------------------- /banner.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BojanG72/STM32-Ceedling-Base/42baab22f893cf9116f3d00fa90af7016a6bb0cf/banner.png -------------------------------------------------------------------------------- /footer.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BojanG72/STM32-Ceedling-Base/42baab22f893cf9116f3d00fa90af7016a6bb0cf/footer.png -------------------------------------------------------------------------------- /lib/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BojanG72/STM32-Ceedling-Base/42baab22f893cf9116f3d00fa90af7016a6bb0cf/lib/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h -------------------------------------------------------------------------------- /lib/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS STM32L4xx Device Peripheral Access Layer Header File. 6 | * 7 | * The file is the unique include file that the application programmer 8 | * is using in the C source code, usually in main.c. This file contains: 9 | * - Configuration section that allows to select: 10 | * - The STM32L4xx device used in the target application 11 | * - To use or not the peripheral�s drivers in application code(i.e. 12 | * code will be based on direct access to peripheral�s registers 13 | * rather than drivers API), this option is controlled by 14 | * "#define USE_HAL_DRIVER" 15 | * 16 | ****************************************************************************** 17 | * @attention 18 | * 19 | *

© Copyright (c) 2017 STMicroelectronics. 20 | * All rights reserved.

21 | * 22 | * This software component is licensed by ST under Apache License, Version 2.0, 23 | * the "License"; You may not use this file except in compliance with the 24 | * License. You may obtain a copy of the License at: 25 | * opensource.org/licenses/Apache-2.0 26 | * 27 | ****************************************************************************** 28 | */ 29 | 30 | /** @addtogroup CMSIS 31 | * @{ 32 | */ 33 | 34 | /** @addtogroup stm32l4xx 35 | * @{ 36 | */ 37 | 38 | #ifndef __STM32L4xx_H 39 | #define __STM32L4xx_H 40 | 41 | #ifdef __cplusplus 42 | extern "C" { 43 | #endif /* __cplusplus */ 44 | 45 | /** @addtogroup Library_configuration_section 46 | * @{ 47 | */ 48 | 49 | /** 50 | * @brief STM32 Family 51 | */ 52 | #if !defined (STM32L4) 53 | #define STM32L4 54 | #endif /* STM32L4 */ 55 | 56 | /* Uncomment the line below according to the target STM32L4 device used in your 57 | application 58 | */ 59 | 60 | #if !defined (STM32L412xx) && !defined (STM32L422xx) && \ 61 | !defined (STM32L431xx) && !defined (STM32L432xx) && !defined (STM32L433xx) && !defined (STM32L442xx) && !defined (STM32L443xx) && \ 62 | !defined (STM32L451xx) && !defined (STM32L452xx) && !defined (STM32L462xx) && \ 63 | !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx) && \ 64 | !defined (STM32L496xx) && !defined (STM32L4A6xx) && \ 65 | !defined (STM32L4P5xx) && !defined (STM32L4Q5xx) && \ 66 | !defined (STM32L4R5xx) && !defined (STM32L4R7xx) && !defined (STM32L4R9xx) && !defined (STM32L4S5xx) && !defined (STM32L4S7xx) && !defined (STM32L4S9xx) 67 | /* #define STM32L412xx */ /*!< STM32L412xx Devices */ 68 | /* #define STM32L422xx */ /*!< STM32L422xx Devices */ 69 | /* #define STM32L431xx */ /*!< STM32L431xx Devices */ 70 | /* #define STM32L432xx */ /*!< STM32L432xx Devices */ 71 | /* #define STM32L433xx */ /*!< STM32L433xx Devices */ 72 | /* #define STM32L442xx */ /*!< STM32L442xx Devices */ 73 | /* #define STM32L443xx */ /*!< STM32L443xx Devices */ 74 | /* #define STM32L451xx */ /*!< STM32L451xx Devices */ 75 | /* #define STM32L452xx */ /*!< STM32L452xx Devices */ 76 | /* #define STM32L462xx */ /*!< STM32L462xx Devices */ 77 | /* #define STM32L471xx */ /*!< STM32L471xx Devices */ 78 | /* #define STM32L475xx */ /*!< STM32L475xx Devices */ 79 | /* #define STM32L476xx */ /*!< STM32L476xx Devices */ 80 | /* #define STM32L485xx */ /*!< STM32L485xx Devices */ 81 | /* #define STM32L486xx */ /*!< STM32L486xx Devices */ 82 | #define STM32L496xx /*!< STM32L496xx Devices */ 83 | /* #define STM32L4A6xx */ /*!< STM32L4A6xx Devices */ 84 | /* #define STM32L4P5xx */ /*!< STM32L4Q5xx Devices */ 85 | /* #define STM32L4R5xx */ /*!< STM32L4R5xx Devices */ 86 | /* #define STM32L4R7xx */ /*!< STM32L4R7xx Devices */ 87 | /* #define STM32L4R9xx */ /*!< STM32L4R9xx Devices */ 88 | /* #define STM32L4S5xx */ /*!< STM32L4S5xx Devices */ 89 | /* #define STM32L4S7xx */ /*!< STM32L4S7xx Devices */ 90 | /* #define STM32L4S9xx */ /*!< STM32L4S9xx Devices */ 91 | #endif 92 | 93 | /* Tip: To avoid modifying this file each time you need to switch between these 94 | devices, you can define the device in your toolchain compiler preprocessor. 95 | */ 96 | #if !defined (USE_HAL_DRIVER) 97 | /** 98 | * @brief Comment the line below if you will not use the peripherals drivers. 99 | In this case, these drivers will not be included and the application code will 100 | be based on direct access to peripherals registers 101 | */ 102 | /*#define USE_HAL_DRIVER */ 103 | #endif /* USE_HAL_DRIVER */ 104 | 105 | /** 106 | * @brief CMSIS Device version number 107 | */ 108 | #define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ 109 | #define __STM32L4_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */ 110 | #define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ 111 | #define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ 112 | #define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\ 113 | |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\ 114 | |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\ 115 | |(__STM32L4_CMSIS_VERSION_RC)) 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @addtogroup Device_Included 122 | * @{ 123 | */ 124 | 125 | #if defined(STM32L412xx) 126 | #include "stm32l412xx.h" 127 | #elif defined(STM32L422xx) 128 | #include "stm32l422xx.h" 129 | #elif defined(STM32L431xx) 130 | #include "stm32l431xx.h" 131 | #elif defined(STM32L432xx) 132 | #include "stm32l432xx.h" 133 | #elif defined(STM32L433xx) 134 | #include "stm32l433xx.h" 135 | #elif defined(STM32L442xx) 136 | #include "stm32l442xx.h" 137 | #elif defined(STM32L443xx) 138 | #include "stm32l443xx.h" 139 | #elif defined(STM32L451xx) 140 | #include "stm32l451xx.h" 141 | #elif defined(STM32L452xx) 142 | #include "stm32l452xx.h" 143 | #elif defined(STM32L462xx) 144 | #include "stm32l462xx.h" 145 | #elif defined(STM32L471xx) 146 | #include "stm32l471xx.h" 147 | #elif defined(STM32L475xx) 148 | #include "stm32l475xx.h" 149 | #elif defined(STM32L476xx) 150 | #include "stm32l476xx.h" 151 | #elif defined(STM32L485xx) 152 | #include "stm32l485xx.h" 153 | #elif defined(STM32L486xx) 154 | #include "stm32l486xx.h" 155 | #elif defined(STM32L496xx) 156 | #include "stm32l496xx.h" 157 | #elif defined(STM32L4A6xx) 158 | #include "stm32l4a6xx.h" 159 | #elif defined(STM32L4P5xx) 160 | #include "stm32l4p5xx.h" 161 | #elif defined(STM32L4Q5xx) 162 | #include "stm32l4q5xx.h" 163 | #elif defined(STM32L4R5xx) 164 | #include "stm32l4r5xx.h" 165 | #elif defined(STM32L4R7xx) 166 | #include "stm32l4r7xx.h" 167 | #elif defined(STM32L4R9xx) 168 | #include "stm32l4r9xx.h" 169 | #elif defined(STM32L4S5xx) 170 | #include "stm32l4s5xx.h" 171 | #elif defined(STM32L4S7xx) 172 | #include "stm32l4s7xx.h" 173 | #elif defined(STM32L4S9xx) 174 | #include "stm32l4s9xx.h" 175 | #else 176 | #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)" 177 | #endif 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** @addtogroup Exported_types 184 | * @{ 185 | */ 186 | typedef enum 187 | { 188 | RESET = 0, 189 | SET = !RESET 190 | } FlagStatus, ITStatus; 191 | 192 | typedef enum 193 | { 194 | DISABLE = 0, 195 | ENABLE = !DISABLE 196 | } FunctionalState; 197 | #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 198 | 199 | typedef enum 200 | { 201 | SUCCESS = 0, 202 | ERROR = !SUCCESS 203 | } ErrorStatus; 204 | 205 | /** 206 | * @} 207 | */ 208 | 209 | 210 | /** @addtogroup Exported_macros 211 | * @{ 212 | */ 213 | #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 214 | 215 | #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 216 | 217 | #define READ_BIT(REG, BIT) ((REG) & (BIT)) 218 | 219 | #define CLEAR_REG(REG) ((REG) = (0x0)) 220 | 221 | #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 222 | 223 | #define READ_REG(REG) ((REG)) 224 | 225 | #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 226 | 227 | #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) 228 | 229 | 230 | /** 231 | * @} 232 | */ 233 | 234 | #if defined (USE_HAL_DRIVER) 235 | #include "stm32l4xx_hal.h" 236 | #endif /* USE_HAL_DRIVER */ 237 | 238 | #ifdef __cplusplus 239 | } 240 | #endif /* __cplusplus */ 241 | 242 | #endif /* __STM32L4xx_H */ 243 | /** 244 | * @} 245 | */ 246 | 247 | /** 248 | * @} 249 | */ 250 | 251 | 252 | 253 | 254 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 255 | -------------------------------------------------------------------------------- /lib/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32l4xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device System Source File for STM32L4xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under Apache License, Version 2.0, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/Apache-2.0 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32l4xx_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32L4XX_H 32 | #define __SYSTEM_STM32L4XX_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32L4xx_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32L4xx_System_Exported_Variables 48 | * @{ 49 | */ 50 | /* The SystemCoreClock variable is updated in three ways: 51 | 1) by calling CMSIS function SystemCoreClockUpdate() 52 | 2) by calling HAL API function HAL_RCC_GetSysClockFreq() 53 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 54 | Note: If you use this function to configure the system clock; then there 55 | is no need to call the 2 first functions listed above, since SystemCoreClock 56 | variable is updated automatically. 57 | */ 58 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 59 | 60 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 61 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 62 | extern const uint32_t MSIRangeTable[12]; /*!< MSI ranges table values */ 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @addtogroup STM32L4xx_System_Exported_Constants 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @addtogroup STM32L4xx_System_Exported_Macros 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @addtogroup STM32L4xx_System_Exported_Functions 85 | * @{ 86 | */ 87 | 88 | extern void SystemInit(void); 89 | extern void SystemCoreClockUpdate(void); 90 | /** 91 | * @} 92 | */ 93 | 94 | #ifdef __cplusplus 95 | } 96 | #endif 97 | 98 | #endif /*__SYSTEM_STM32L4XX_H */ 99 | 100 | /** 101 | * @} 102 | */ 103 | 104 | /** 105 | * @} 106 | */ 107 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 108 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.1.0 5 | * @date 09. October 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6.6 LTM (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) 41 | #include "cmsis_armclang_ltm.h" 42 | 43 | /* 44 | * Arm Compiler above 6.10.1 (armclang) 45 | */ 46 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) 47 | #include "cmsis_armclang.h" 48 | 49 | 50 | /* 51 | * GNU Compiler 52 | */ 53 | #elif defined ( __GNUC__ ) 54 | #include "cmsis_gcc.h" 55 | 56 | 57 | /* 58 | * IAR Compiler 59 | */ 60 | #elif defined ( __ICCARM__ ) 61 | #include 62 | 63 | 64 | /* 65 | * TI Arm Compiler 66 | */ 67 | #elif defined ( __TI_ARM__ ) 68 | #include 69 | 70 | #ifndef __ASM 71 | #define __ASM __asm 72 | #endif 73 | #ifndef __INLINE 74 | #define __INLINE inline 75 | #endif 76 | #ifndef __STATIC_INLINE 77 | #define __STATIC_INLINE static inline 78 | #endif 79 | #ifndef __STATIC_FORCEINLINE 80 | #define __STATIC_FORCEINLINE __STATIC_INLINE 81 | #endif 82 | #ifndef __NO_RETURN 83 | #define __NO_RETURN __attribute__((noreturn)) 84 | #endif 85 | #ifndef __USED 86 | #define __USED __attribute__((used)) 87 | #endif 88 | #ifndef __WEAK 89 | #define __WEAK __attribute__((weak)) 90 | #endif 91 | #ifndef __PACKED 92 | #define __PACKED __attribute__((packed)) 93 | #endif 94 | #ifndef __PACKED_STRUCT 95 | #define __PACKED_STRUCT struct __attribute__((packed)) 96 | #endif 97 | #ifndef __PACKED_UNION 98 | #define __PACKED_UNION union __attribute__((packed)) 99 | #endif 100 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 101 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 102 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 103 | #endif 104 | #ifndef __UNALIGNED_UINT16_WRITE 105 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 106 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 107 | #endif 108 | #ifndef __UNALIGNED_UINT16_READ 109 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 110 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 111 | #endif 112 | #ifndef __UNALIGNED_UINT32_WRITE 113 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 114 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 115 | #endif 116 | #ifndef __UNALIGNED_UINT32_READ 117 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 118 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 119 | #endif 120 | #ifndef __ALIGNED 121 | #define __ALIGNED(x) __attribute__((aligned(x))) 122 | #endif 123 | #ifndef __RESTRICT 124 | #define __RESTRICT __restrict 125 | #endif 126 | #ifndef __COMPILER_BARRIER 127 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 128 | #define __COMPILER_BARRIER() (void)0 129 | #endif 130 | 131 | 132 | /* 133 | * TASKING Compiler 134 | */ 135 | #elif defined ( __TASKING__ ) 136 | /* 137 | * The CMSIS functions have been implemented as intrinsics in the compiler. 138 | * Please use "carm -?i" to get an up to date list of all intrinsics, 139 | * Including the CMSIS ones. 140 | */ 141 | 142 | #ifndef __ASM 143 | #define __ASM __asm 144 | #endif 145 | #ifndef __INLINE 146 | #define __INLINE inline 147 | #endif 148 | #ifndef __STATIC_INLINE 149 | #define __STATIC_INLINE static inline 150 | #endif 151 | #ifndef __STATIC_FORCEINLINE 152 | #define __STATIC_FORCEINLINE __STATIC_INLINE 153 | #endif 154 | #ifndef __NO_RETURN 155 | #define __NO_RETURN __attribute__((noreturn)) 156 | #endif 157 | #ifndef __USED 158 | #define __USED __attribute__((used)) 159 | #endif 160 | #ifndef __WEAK 161 | #define __WEAK __attribute__((weak)) 162 | #endif 163 | #ifndef __PACKED 164 | #define __PACKED __packed__ 165 | #endif 166 | #ifndef __PACKED_STRUCT 167 | #define __PACKED_STRUCT struct __packed__ 168 | #endif 169 | #ifndef __PACKED_UNION 170 | #define __PACKED_UNION union __packed__ 171 | #endif 172 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 173 | struct __packed__ T_UINT32 { uint32_t v; }; 174 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 175 | #endif 176 | #ifndef __UNALIGNED_UINT16_WRITE 177 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 178 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 179 | #endif 180 | #ifndef __UNALIGNED_UINT16_READ 181 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 182 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 183 | #endif 184 | #ifndef __UNALIGNED_UINT32_WRITE 185 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 186 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 187 | #endif 188 | #ifndef __UNALIGNED_UINT32_READ 189 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 190 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 191 | #endif 192 | #ifndef __ALIGNED 193 | #define __ALIGNED(x) __align(x) 194 | #endif 195 | #ifndef __RESTRICT 196 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 197 | #define __RESTRICT 198 | #endif 199 | #ifndef __COMPILER_BARRIER 200 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 201 | #define __COMPILER_BARRIER() (void)0 202 | #endif 203 | 204 | 205 | /* 206 | * COSMIC Compiler 207 | */ 208 | #elif defined ( __CSMC__ ) 209 | #include 210 | 211 | #ifndef __ASM 212 | #define __ASM _asm 213 | #endif 214 | #ifndef __INLINE 215 | #define __INLINE inline 216 | #endif 217 | #ifndef __STATIC_INLINE 218 | #define __STATIC_INLINE static inline 219 | #endif 220 | #ifndef __STATIC_FORCEINLINE 221 | #define __STATIC_FORCEINLINE __STATIC_INLINE 222 | #endif 223 | #ifndef __NO_RETURN 224 | // NO RETURN is automatically detected hence no warning here 225 | #define __NO_RETURN 226 | #endif 227 | #ifndef __USED 228 | #warning No compiler specific solution for __USED. __USED is ignored. 229 | #define __USED 230 | #endif 231 | #ifndef __WEAK 232 | #define __WEAK __weak 233 | #endif 234 | #ifndef __PACKED 235 | #define __PACKED @packed 236 | #endif 237 | #ifndef __PACKED_STRUCT 238 | #define __PACKED_STRUCT @packed struct 239 | #endif 240 | #ifndef __PACKED_UNION 241 | #define __PACKED_UNION @packed union 242 | #endif 243 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 244 | @packed struct T_UINT32 { uint32_t v; }; 245 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 246 | #endif 247 | #ifndef __UNALIGNED_UINT16_WRITE 248 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 249 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 250 | #endif 251 | #ifndef __UNALIGNED_UINT16_READ 252 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 253 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 254 | #endif 255 | #ifndef __UNALIGNED_UINT32_WRITE 256 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 257 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 258 | #endif 259 | #ifndef __UNALIGNED_UINT32_READ 260 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 261 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 262 | #endif 263 | #ifndef __ALIGNED 264 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 265 | #define __ALIGNED(x) 266 | #endif 267 | #ifndef __RESTRICT 268 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 269 | #define __RESTRICT 270 | #endif 271 | #ifndef __COMPILER_BARRIER 272 | #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. 273 | #define __COMPILER_BARRIER() (void)0 274 | #endif 275 | 276 | 277 | #else 278 | #error Unknown compiler. 279 | #endif 280 | 281 | 282 | #endif /* __CMSIS_COMPILER_H */ 283 | 284 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.3 5 | * @date 24. June 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2019 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ 107 | (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ 108 | (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ 109 | (((MPU_RASR_ENABLE_Msk)))) 110 | 111 | /** 112 | * MPU Region Attribute and Size Register Value 113 | * 114 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 115 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 116 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 117 | * \param IsShareable Region is shareable between multiple bus masters. 118 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 119 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 120 | * \param SubRegionDisable Sub-region disable field. 121 | * \param Size Region size of the region to be configured, for example 4K, 8K. 122 | */ 123 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 124 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 125 | 126 | /** 127 | * MPU Memory Access Attribute for strongly ordered memory. 128 | * - TEX: 000b 129 | * - Shareable 130 | * - Non-cacheable 131 | * - Non-bufferable 132 | */ 133 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 134 | 135 | /** 136 | * MPU Memory Access Attribute for device memory. 137 | * - TEX: 000b (if shareable) or 010b (if non-shareable) 138 | * - Shareable or non-shareable 139 | * - Non-cacheable 140 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 141 | * 142 | * \param IsShareable Configures the device memory as shareable or non-shareable. 143 | */ 144 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 145 | 146 | /** 147 | * MPU Memory Access Attribute for normal memory. 148 | * - TEX: 1BBb (reflecting outer cacheability rules) 149 | * - Shareable or non-shareable 150 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 151 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 152 | * 153 | * \param OuterCp Configures the outer cache policy. 154 | * \param InnerCp Configures the inner cache policy. 155 | * \param IsShareable Configures the memory as shareable or non-shareable. 156 | */ 157 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 158 | 159 | /** 160 | * MPU Memory Access Attribute non-cacheable policy. 161 | */ 162 | #define ARM_MPU_CACHEP_NOCACHE 0U 163 | 164 | /** 165 | * MPU Memory Access Attribute write-back, write and read allocate policy. 166 | */ 167 | #define ARM_MPU_CACHEP_WB_WRA 1U 168 | 169 | /** 170 | * MPU Memory Access Attribute write-through, no write allocate policy. 171 | */ 172 | #define ARM_MPU_CACHEP_WT_NWA 2U 173 | 174 | /** 175 | * MPU Memory Access Attribute write-back, no write allocate policy. 176 | */ 177 | #define ARM_MPU_CACHEP_WB_NWA 3U 178 | 179 | 180 | /** 181 | * Struct for a single MPU Region 182 | */ 183 | typedef struct { 184 | uint32_t RBAR; //!< The region base address register value (RBAR) 185 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 186 | } ARM_MPU_Region_t; 187 | 188 | /** Enable the MPU. 189 | * \param MPU_Control Default access permissions for unconfigured regions. 190 | */ 191 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 192 | { 193 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 194 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 195 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 196 | #endif 197 | __DSB(); 198 | __ISB(); 199 | } 200 | 201 | /** Disable the MPU. 202 | */ 203 | __STATIC_INLINE void ARM_MPU_Disable(void) 204 | { 205 | __DMB(); 206 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 207 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 208 | #endif 209 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | MPU->RNR = rnr; 218 | MPU->RASR = 0U; 219 | } 220 | 221 | /** Configure an MPU region. 222 | * \param rbar Value for RBAR register. 223 | * \param rsar Value for RSAR register. 224 | */ 225 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 226 | { 227 | MPU->RBAR = rbar; 228 | MPU->RASR = rasr; 229 | } 230 | 231 | /** Configure the given MPU region. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rsar Value for RSAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 237 | { 238 | MPU->RNR = rnr; 239 | MPU->RBAR = rbar; 240 | MPU->RASR = rasr; 241 | } 242 | 243 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 244 | * \param dst Destination data is copied to. 245 | * \param src Source data is copied from. 246 | * \param len Amount of data words to be copied. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 249 | { 250 | uint32_t i; 251 | for (i = 0U; i < len; ++i) 252 | { 253 | dst[i] = src[i]; 254 | } 255 | } 256 | 257 | /** Load the given number of MPU regions from a table. 258 | * \param table Pointer to the MPU configuration table. 259 | * \param cnt Amount of regions to be configured. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 262 | { 263 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 264 | while (cnt > MPU_TYPE_RALIASES) { 265 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 266 | table += MPU_TYPE_RALIASES; 267 | cnt -= MPU_TYPE_RALIASES; 268 | } 269 | ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 270 | } 271 | 272 | #endif 273 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU 4 | * @version V5.1.0 5 | * @date 08. March 2019 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2019 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | #if defined(MPU_RLAR_PXN_Pos) 105 | 106 | /** \brief Region Limit Address Register with PXN value 107 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 108 | * \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. 109 | * \param IDX The attribute index to be associated with this memory region. 110 | */ 111 | #define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ 112 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 113 | ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ 114 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 115 | (MPU_RLAR_EN_Msk)) 116 | 117 | #endif 118 | 119 | /** 120 | * Struct for a single MPU Region 121 | */ 122 | typedef struct { 123 | uint32_t RBAR; /*!< Region Base Address Register value */ 124 | uint32_t RLAR; /*!< Region Limit Address Register value */ 125 | } ARM_MPU_Region_t; 126 | 127 | /** Enable the MPU. 128 | * \param MPU_Control Default access permissions for unconfigured regions. 129 | */ 130 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 131 | { 132 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 133 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 134 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 135 | #endif 136 | __DSB(); 137 | __ISB(); 138 | } 139 | 140 | /** Disable the MPU. 141 | */ 142 | __STATIC_INLINE void ARM_MPU_Disable(void) 143 | { 144 | __DMB(); 145 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 146 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 147 | #endif 148 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 149 | } 150 | 151 | #ifdef MPU_NS 152 | /** Enable the Non-secure MPU. 153 | * \param MPU_Control Default access permissions for unconfigured regions. 154 | */ 155 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 156 | { 157 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 158 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 159 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 160 | #endif 161 | __DSB(); 162 | __ISB(); 163 | } 164 | 165 | /** Disable the Non-secure MPU. 166 | */ 167 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 168 | { 169 | __DMB(); 170 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 171 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 172 | #endif 173 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 174 | } 175 | #endif 176 | 177 | /** Set the memory attribute encoding to the given MPU. 178 | * \param mpu Pointer to the MPU to be configured. 179 | * \param idx The attribute index to be set [0-7] 180 | * \param attr The attribute value to be set. 181 | */ 182 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 183 | { 184 | const uint8_t reg = idx / 4U; 185 | const uint32_t pos = ((idx % 4U) * 8U); 186 | const uint32_t mask = 0xFFU << pos; 187 | 188 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 189 | return; // invalid index 190 | } 191 | 192 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 193 | } 194 | 195 | /** Set the memory attribute encoding. 196 | * \param idx The attribute index to be set [0-7] 197 | * \param attr The attribute value to be set. 198 | */ 199 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 200 | { 201 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 202 | } 203 | 204 | #ifdef MPU_NS 205 | /** Set the memory attribute encoding to the Non-secure MPU. 206 | * \param idx The attribute index to be set [0-7] 207 | * \param attr The attribute value to be set. 208 | */ 209 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 210 | { 211 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 212 | } 213 | #endif 214 | 215 | /** Clear and disable the given MPU region of the given MPU. 216 | * \param mpu Pointer to MPU to be used. 217 | * \param rnr Region number to be cleared. 218 | */ 219 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 220 | { 221 | mpu->RNR = rnr; 222 | mpu->RLAR = 0U; 223 | } 224 | 225 | /** Clear and disable the given MPU region. 226 | * \param rnr Region number to be cleared. 227 | */ 228 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 229 | { 230 | ARM_MPU_ClrRegionEx(MPU, rnr); 231 | } 232 | 233 | #ifdef MPU_NS 234 | /** Clear and disable the given Non-secure MPU region. 235 | * \param rnr Region number to be cleared. 236 | */ 237 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 238 | { 239 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 240 | } 241 | #endif 242 | 243 | /** Configure the given MPU region of the given MPU. 244 | * \param mpu Pointer to MPU to be used. 245 | * \param rnr Region number to be configured. 246 | * \param rbar Value for RBAR register. 247 | * \param rlar Value for RLAR register. 248 | */ 249 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 250 | { 251 | mpu->RNR = rnr; 252 | mpu->RBAR = rbar; 253 | mpu->RLAR = rlar; 254 | } 255 | 256 | /** Configure the given MPU region. 257 | * \param rnr Region number to be configured. 258 | * \param rbar Value for RBAR register. 259 | * \param rlar Value for RLAR register. 260 | */ 261 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 262 | { 263 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 264 | } 265 | 266 | #ifdef MPU_NS 267 | /** Configure the given Non-secure MPU region. 268 | * \param rnr Region number to be configured. 269 | * \param rbar Value for RBAR register. 270 | * \param rlar Value for RLAR register. 271 | */ 272 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 273 | { 274 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 275 | } 276 | #endif 277 | 278 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 279 | * \param dst Destination data is copied to. 280 | * \param src Source data is copied from. 281 | * \param len Amount of data words to be copied. 282 | */ 283 | __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 284 | { 285 | uint32_t i; 286 | for (i = 0U; i < len; ++i) 287 | { 288 | dst[i] = src[i]; 289 | } 290 | } 291 | 292 | /** Load the given number of MPU regions from a table to the given MPU. 293 | * \param mpu Pointer to the MPU registers to be used. 294 | * \param rnr First region number to be configured. 295 | * \param table Pointer to the MPU configuration table. 296 | * \param cnt Amount of regions to be configured. 297 | */ 298 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 299 | { 300 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 301 | if (cnt == 1U) { 302 | mpu->RNR = rnr; 303 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 304 | } else { 305 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 306 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 307 | 308 | mpu->RNR = rnrBase; 309 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 310 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 311 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 312 | table += c; 313 | cnt -= c; 314 | rnrOffset = 0U; 315 | rnrBase += MPU_TYPE_RALIASES; 316 | mpu->RNR = rnrBase; 317 | } 318 | 319 | ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 320 | } 321 | } 322 | 323 | /** Load the given number of MPU regions from a table. 324 | * \param rnr First region number to be configured. 325 | * \param table Pointer to the MPU configuration table. 326 | * \param cnt Amount of regions to be configured. 327 | */ 328 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 329 | { 330 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 331 | } 332 | 333 | #ifdef MPU_NS 334 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 335 | * \param rnr First region number to be configured. 336 | * \param table Pointer to the MPU configuration table. 337 | * \param cnt Amount of regions to be configured. 338 | */ 339 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 340 | { 341 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 342 | } 343 | #endif 344 | 345 | #endif 346 | 347 | -------------------------------------------------------------------------------- /lib/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2017 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef STM32L4xx_HAL_DEF_H 23 | #define STM32L4xx_HAL_DEF_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32l4xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00, 42 | HAL_ERROR = 0x01, 43 | HAL_BUSY = 0x02, 44 | HAL_TIMEOUT = 0x03 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00, 53 | HAL_LOCKED = 0x01 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macros -----------------------------------------------------------*/ 57 | 58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 59 | 60 | #define HAL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 64 | 65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 66 | do{ \ 67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 69 | } while(0) 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__: specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) 87 | 88 | #if (USE_RTOS == 1) 89 | /* Reserved for future use */ 90 | #error " USE_RTOS should be 0 in the current HAL release " 91 | #else 92 | #define __HAL_LOCK(__HANDLE__) \ 93 | do{ \ 94 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 95 | { \ 96 | return HAL_BUSY; \ 97 | } \ 98 | else \ 99 | { \ 100 | (__HANDLE__)->Lock = HAL_LOCKED; \ 101 | } \ 102 | }while (0) 103 | 104 | #define __HAL_UNLOCK(__HANDLE__) \ 105 | do{ \ 106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 107 | }while (0) 108 | #endif /* USE_RTOS */ 109 | 110 | 111 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 112 | #ifndef __weak 113 | #define __weak __attribute__((weak)) 114 | #endif 115 | #ifndef __packed 116 | #define __packed __attribute__((packed)) 117 | #endif 118 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 119 | #ifndef __weak 120 | #define __weak __attribute__((weak)) 121 | #endif /* __weak */ 122 | #ifndef __packed 123 | #define __packed __attribute__((__packed__)) 124 | #endif /* __packed */ 125 | #endif /* __GNUC__ */ 126 | 127 | 128 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 129 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 130 | #ifndef __ALIGN_BEGIN 131 | #define __ALIGN_BEGIN 132 | #endif 133 | #ifndef __ALIGN_END 134 | #define __ALIGN_END __attribute__ ((aligned (4))) 135 | #endif 136 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 137 | #ifndef __ALIGN_END 138 | #define __ALIGN_END __attribute__ ((aligned (4))) 139 | #endif /* __ALIGN_END */ 140 | #ifndef __ALIGN_BEGIN 141 | #define __ALIGN_BEGIN 142 | #endif /* __ALIGN_BEGIN */ 143 | #else 144 | #ifndef __ALIGN_END 145 | #define __ALIGN_END 146 | #endif /* __ALIGN_END */ 147 | #ifndef __ALIGN_BEGIN 148 | #if defined (__CC_ARM) /* ARM Compiler V5 */ 149 | #define __ALIGN_BEGIN __align(4) 150 | #elif defined (__ICCARM__) /* IAR Compiler */ 151 | #define __ALIGN_BEGIN 152 | #endif /* __CC_ARM */ 153 | #endif /* __ALIGN_BEGIN */ 154 | #endif /* __GNUC__ */ 155 | 156 | /** 157 | * @brief __RAM_FUNC definition 158 | */ 159 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) 160 | /* ARM Compiler V4/V5 and V6 161 | -------------------------- 162 | RAM functions are defined using the toolchain options. 163 | Functions that are executed in RAM should reside in a separate source module. 164 | Using the 'Options for File' dialog you can simply change the 'Code / Const' 165 | area of a module to a memory space in physical RAM. 166 | Available memory areas are declared in the 'Target' tab of the 'Options for Target' 167 | dialog. 168 | */ 169 | #define __RAM_FUNC 170 | 171 | #elif defined ( __ICCARM__ ) 172 | /* ICCARM Compiler 173 | --------------- 174 | RAM functions are defined using a specific toolchain keyword "__ramfunc". 175 | */ 176 | #define __RAM_FUNC __ramfunc 177 | 178 | #elif defined ( __GNUC__ ) 179 | /* GNU Compiler 180 | ------------ 181 | RAM functions are defined using a specific toolchain attribute 182 | "__attribute__((section(".RamFunc")))". 183 | */ 184 | #define __RAM_FUNC __attribute__((section(".RamFunc"))) 185 | 186 | #endif 187 | 188 | /** 189 | * @brief __NOINLINE definition 190 | */ 191 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 192 | /* ARM V4/V5 and V6 & GNU Compiler 193 | ------------------------------- 194 | */ 195 | #define __NOINLINE __attribute__ ( (noinline) ) 196 | 197 | #elif defined ( __ICCARM__ ) 198 | /* ICCARM Compiler 199 | --------------- 200 | */ 201 | #define __NOINLINE _Pragma("optimize = no_inline") 202 | 203 | #endif 204 | 205 | 206 | #ifdef __cplusplus 207 | } 208 | #endif 209 | 210 | #endif /* STM32L4xx_HAL_DEF_H */ 211 | 212 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 213 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_dma_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of DMA HAL extension module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_HAL_DMA_EX_H 22 | #define STM32L4xx_HAL_DMA_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | #if defined(DMAMUX1) 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32l4xx_hal_def.h" 32 | 33 | /** @addtogroup STM32L4xx_HAL_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup DMAEx 38 | * @{ 39 | */ 40 | 41 | /* Exported types ------------------------------------------------------------*/ 42 | /** @defgroup DMAEx_Exported_Types DMAEx Exported Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief HAL DMA Synchro definition 48 | */ 49 | 50 | 51 | /** 52 | * @brief HAL DMAMUX Synchronization configuration structure definition 53 | */ 54 | typedef struct 55 | { 56 | uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode. 57 | This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */ 58 | 59 | uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized. 60 | This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */ 61 | 62 | FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled 63 | This parameter can take the value ENABLE or DISABLE*/ 64 | 65 | 66 | FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached. 67 | This parameter can take the value ENABLE or DISABLE */ 68 | 69 | uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event 70 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 71 | 72 | 73 | }HAL_DMA_MuxSyncConfigTypeDef; 74 | 75 | 76 | /** 77 | * @brief HAL DMAMUX request generator parameters structure definition 78 | */ 79 | typedef struct 80 | { 81 | uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator 82 | This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */ 83 | 84 | uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated. 85 | This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */ 86 | 87 | uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event 88 | This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 89 | 90 | }HAL_DMA_MuxRequestGeneratorConfigTypeDef; 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /* Exported constants --------------------------------------------------------*/ 97 | /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants 98 | * @{ 99 | */ 100 | 101 | /** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection 102 | * @{ 103 | */ 104 | #define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */ 105 | #define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */ 106 | #define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */ 107 | #define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */ 108 | #define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */ 109 | #define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */ 110 | #define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */ 111 | #define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */ 112 | #define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */ 113 | #define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */ 114 | #define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */ 115 | #define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */ 116 | #define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */ 117 | #define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */ 118 | #define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */ 119 | #define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */ 120 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */ 121 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */ 122 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */ 123 | #define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */ 124 | #define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */ 125 | #define HAL_DMAMUX1_SYNC_LPTIM2_OUT 21U /*!< Synchronization Signal is LPTIM2 OUT */ 126 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 127 | #define HAL_DMAMUX1_SYNC_DSI_TE 22U /*!< Synchronization Signal is DSI Tearing Effect */ 128 | #define HAL_DMAMUX1_SYNC_DSI_EOT 23U /*!< Synchronization Signal is DSI End of refresh */ 129 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 130 | #define HAL_DMAMUX1_SYNC_DMA2D_EOT 24U /*!< Synchronization Signal is DMA2D End of Transfer */ 131 | #define HAL_DMAMUX1_SYNC_LDTC_IT 25U /*!< Synchronization Signal is LDTC IT */ 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection 138 | * @{ 139 | */ 140 | #define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */ 141 | #define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */ 142 | #define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */ 143 | #define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */ 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection 150 | * @{ 151 | */ 152 | 153 | #define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */ 154 | #define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */ 155 | #define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */ 156 | #define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */ 157 | #define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */ 158 | #define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */ 159 | #define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */ 160 | #define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */ 161 | #define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */ 162 | #define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */ 163 | #define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */ 164 | #define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */ 165 | #define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */ 166 | #define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */ 167 | #define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */ 168 | #define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */ 169 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */ 170 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */ 171 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */ 172 | #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */ 173 | #define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */ 174 | #define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 21U /*!< Request generator Signal is LPTIM2 OUT */ 175 | #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 176 | #define HAL_DMAMUX1_REQ_GEN_DSI_TE 22U /*!< Request generator Signal is DSI Tearing Effect */ 177 | #define HAL_DMAMUX1_REQ_GEN_DSI_EOT 23U /*!< Request generator Signal is DSI End of refresh */ 178 | #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 179 | #define HAL_DMAMUX1_REQ_GEN_DMA2D_EOT 24U /*!< Request generator Signal is DMA2D End of Transfer */ 180 | #define HAL_DMAMUX1_REQ_GEN_LTDC_IT 25U /*!< Request generator Signal is LTDC IT */ 181 | 182 | /** 183 | * @} 184 | */ 185 | 186 | /** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection 187 | * @{ 188 | */ 189 | #define HAL_DMAMUX_REQ_GEN_NO_EVENT 0U /*!< block request generator events */ 190 | #define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */ 191 | #define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */ 192 | #define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */ 193 | 194 | /** 195 | * @} 196 | */ 197 | 198 | /** 199 | * @} 200 | */ 201 | 202 | /* Exported macro ------------------------------------------------------------*/ 203 | 204 | /* Exported functions --------------------------------------------------------*/ 205 | /** @addtogroup DMAEx_Exported_Functions 206 | * @{ 207 | */ 208 | 209 | /* IO operation functions *****************************************************/ 210 | /** @addtogroup DMAEx_Exported_Functions_Group1 211 | * @{ 212 | */ 213 | 214 | /* ------------------------- REQUEST -----------------------------------------*/ 215 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, 216 | HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig); 217 | HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma); 218 | HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma); 219 | /* -------------------------------------------------------------------------- */ 220 | 221 | /* ------------------------- SYNCHRO -----------------------------------------*/ 222 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig); 223 | /* -------------------------------------------------------------------------- */ 224 | 225 | void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); 226 | 227 | /** 228 | * @} 229 | */ 230 | 231 | /** 232 | * @} 233 | */ 234 | 235 | 236 | /* Private defines -----------------------------------------------------------*/ 237 | /* Private macros ------------------------------------------------------------*/ 238 | /** @defgroup DMAEx_Private_Macros DMAEx Private Macros 239 | * @brief DMAEx private macros 240 | * @{ 241 | */ 242 | 243 | #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LDTC_IT) 244 | 245 | #define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) 246 | 247 | #define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \ 248 | ((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \ 249 | ((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \ 250 | ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING)) 251 | 252 | #define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE)) 253 | 254 | #define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \ 255 | ((EVENT) == ENABLE)) 256 | 257 | #define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LTDC_IT) 258 | 259 | #define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U)) 260 | 261 | #define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \ 262 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \ 263 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \ 264 | ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING)) 265 | 266 | /** 267 | * @} 268 | */ 269 | 270 | 271 | /** 272 | * @} 273 | */ 274 | 275 | /** 276 | * @} 277 | */ 278 | 279 | #endif /* DMAMUX1 */ 280 | 281 | #ifdef __cplusplus 282 | } 283 | #endif 284 | 285 | #endif /* STM32L4xx_HAL_DMA_H */ 286 | 287 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 288 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_flash_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of FLASH HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_HAL_FLASH_EX_H 22 | #define STM32L4xx_HAL_FLASH_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32l4xx_hal_def.h" 30 | 31 | /** @addtogroup STM32L4xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASHEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /* Exported constants --------------------------------------------------------*/ 42 | #if defined (FLASH_CFGR_LVEN) 43 | /** @addtogroup FLASHEx_Exported_Constants 44 | * @{ 45 | */ 46 | /** @defgroup FLASHEx_LVE_PIN_CFG FLASHEx LVE pin configuration 47 | * @{ 48 | */ 49 | #define FLASH_LVE_PIN_CTRL 0x00000000U /*!< LVE FLASH pin controlled by power controller */ 50 | #define FLASH_LVE_PIN_FORCED FLASH_CFGR_LVEN /*!< LVE FLASH pin enforced to low (external SMPS used) */ 51 | /** 52 | * @} 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | #endif /* FLASH_CFGR_LVEN */ 59 | 60 | /* Exported macro ------------------------------------------------------------*/ 61 | 62 | /* Exported functions --------------------------------------------------------*/ 63 | /** @addtogroup FLASHEx_Exported_Functions 64 | * @{ 65 | */ 66 | 67 | /* Extended Program operation functions *************************************/ 68 | /** @addtogroup FLASHEx_Exported_Functions_Group1 69 | * @{ 70 | */ 71 | HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); 72 | HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 73 | HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 74 | void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 75 | /** 76 | * @} 77 | */ 78 | 79 | #if defined (FLASH_CFGR_LVEN) 80 | /** @addtogroup FLASHEx_Exported_Functions_Group2 81 | * @{ 82 | */ 83 | HAL_StatusTypeDef HAL_FLASHEx_ConfigLVEPin(uint32_t ConfigLVE); 84 | /** 85 | * @} 86 | */ 87 | #endif /* FLASH_CFGR_LVEN */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /* Private function ----------------------------------------------------------*/ 94 | /** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions 95 | * @{ 96 | */ 97 | void FLASH_PageErase(uint32_t Page, uint32_t Banks); 98 | void FLASH_FlushCaches(void); 99 | /** 100 | * @} 101 | */ 102 | 103 | /* Private macros ------------------------------------------------------------*/ 104 | /** 105 | @cond 0 106 | */ 107 | #if defined (FLASH_CFGR_LVEN) 108 | #define IS_FLASH_LVE_PIN(CFG) (((CFG) == FLASH_LVE_PIN_CTRL) || ((CFG) == FLASH_LVE_PIN_FORCED)) 109 | #endif /* FLASH_CFGR_LVEN */ 110 | /** 111 | @endcond 112 | */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | #ifdef __cplusplus 123 | } 124 | #endif 125 | 126 | #endif /* STM32L4xx_HAL_FLASH_EX_H */ 127 | 128 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 129 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_flash_ramfunc.h 4 | * @author MCD Application Team 5 | * @brief Header file of FLASH RAMFUNC driver. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_FLASH_RAMFUNC_H 22 | #define STM32L4xx_FLASH_RAMFUNC_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32l4xx_hal_def.h" 30 | 31 | /** @addtogroup STM32L4xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH_RAMFUNC 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported macro ------------------------------------------------------------*/ 41 | /* Exported functions --------------------------------------------------------*/ 42 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions 43 | * @{ 44 | */ 45 | 46 | /** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 47 | * @{ 48 | */ 49 | /* Peripheral Control functions ************************************************/ 50 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); 51 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); 52 | #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 53 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig); 54 | #endif 55 | /** 56 | * @} 57 | */ 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** 68 | * @} 69 | */ 70 | 71 | #ifdef __cplusplus 72 | } 73 | #endif 74 | 75 | #endif /* STM32L4xx_FLASH_RAMFUNC_H */ 76 | 77 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 78 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_gpio.h 4 | * @author MCD Application Team 5 | * @brief Header file of GPIO HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_HAL_GPIO_H 22 | #define STM32L4xx_HAL_GPIO_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32l4xx_hal_def.h" 30 | 31 | /** @addtogroup STM32L4xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup GPIO 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /** @defgroup GPIO_Exported_Types GPIO Exported Types 42 | * @{ 43 | */ 44 | /** 45 | * @brief GPIO Init structure definition 46 | */ 47 | typedef struct 48 | { 49 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 50 | This parameter can be any value of @ref GPIO_pins */ 51 | 52 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 53 | This parameter can be a value of @ref GPIO_mode */ 54 | 55 | uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. 56 | This parameter can be a value of @ref GPIO_pull */ 57 | 58 | uint32_t Speed; /*!< Specifies the speed for the selected pins. 59 | This parameter can be a value of @ref GPIO_speed */ 60 | 61 | uint32_t Alternate; /*!< Peripheral to be connected to the selected pins 62 | This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ 63 | }GPIO_InitTypeDef; 64 | 65 | /** 66 | * @brief GPIO Bit SET and Bit RESET enumeration 67 | */ 68 | typedef enum 69 | { 70 | GPIO_PIN_RESET = 0U, 71 | GPIO_PIN_SET 72 | }GPIO_PinState; 73 | /** 74 | * @} 75 | */ 76 | 77 | /* Exported constants --------------------------------------------------------*/ 78 | /** @defgroup GPIO_Exported_Constants GPIO Exported Constants 79 | * @{ 80 | */ 81 | /** @defgroup GPIO_pins GPIO pins 82 | * @{ 83 | */ 84 | #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ 85 | #define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ 86 | #define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ 87 | #define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ 88 | #define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ 89 | #define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ 90 | #define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ 91 | #define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ 92 | #define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ 93 | #define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ 94 | #define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ 95 | #define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ 96 | #define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ 97 | #define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ 98 | #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ 99 | #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ 100 | #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ 101 | 102 | #define GPIO_PIN_MASK (0x0000FFFFu) /* PIN mask for assert test */ 103 | /** 104 | * @} 105 | */ 106 | 107 | /** @defgroup GPIO_mode GPIO mode 108 | * @brief GPIO Configuration Mode 109 | * Elements values convention: 0xX0yz00YZ 110 | * - X : GPIO mode or EXTI Mode 111 | * - y : External IT or Event trigger detection 112 | * - z : IO configuration on External IT or Event 113 | * - Y : Output type (Push Pull or Open Drain) 114 | * - Z : IO Direction mode (Input, Output, Alternate or Analog) 115 | * @{ 116 | */ 117 | #define GPIO_MODE_INPUT (0x00000000u) /*!< Input Floating Mode */ 118 | #define GPIO_MODE_OUTPUT_PP (0x00000001u) /*!< Output Push Pull Mode */ 119 | #define GPIO_MODE_OUTPUT_OD (0x00000011u) /*!< Output Open Drain Mode */ 120 | #define GPIO_MODE_AF_PP (0x00000002u) /*!< Alternate Function Push Pull Mode */ 121 | #define GPIO_MODE_AF_OD (0x00000012u) /*!< Alternate Function Open Drain Mode */ 122 | #define GPIO_MODE_ANALOG (0x00000003u) /*!< Analog Mode */ 123 | #define GPIO_MODE_ANALOG_ADC_CONTROL (0x0000000Bu) /*!< Analog Mode for ADC conversion */ 124 | #define GPIO_MODE_IT_RISING (0x10110000u) /*!< External Interrupt Mode with Rising edge trigger detection */ 125 | #define GPIO_MODE_IT_FALLING (0x10210000u) /*!< External Interrupt Mode with Falling edge trigger detection */ 126 | #define GPIO_MODE_IT_RISING_FALLING (0x10310000u) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 127 | #define GPIO_MODE_EVT_RISING (0x10120000u) /*!< External Event Mode with Rising edge trigger detection */ 128 | #define GPIO_MODE_EVT_FALLING (0x10220000u) /*!< External Event Mode with Falling edge trigger detection */ 129 | #define GPIO_MODE_EVT_RISING_FALLING (0x10320000u) /*!< External Event Mode with Rising/Falling edge trigger detection */ 130 | /** 131 | * @} 132 | */ 133 | 134 | /** @defgroup GPIO_speed GPIO speed 135 | * @brief GPIO Output Maximum frequency 136 | * @{ 137 | */ 138 | #define GPIO_SPEED_FREQ_LOW (0x00000000u) /*!< range up to 5 MHz, please refer to the product datasheet */ 139 | #define GPIO_SPEED_FREQ_MEDIUM (0x00000001u) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */ 140 | #define GPIO_SPEED_FREQ_HIGH (0x00000002u) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */ 141 | #define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003u) /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */ 142 | /** 143 | * @} 144 | */ 145 | 146 | /** @defgroup GPIO_pull GPIO pull 147 | * @brief GPIO Pull-Up or Pull-Down Activation 148 | * @{ 149 | */ 150 | #define GPIO_NOPULL (0x00000000u) /*!< No Pull-up or Pull-down activation */ 151 | #define GPIO_PULLUP (0x00000001u) /*!< Pull-up activation */ 152 | #define GPIO_PULLDOWN (0x00000002u) /*!< Pull-down activation */ 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /* Exported macro ------------------------------------------------------------*/ 162 | /** @defgroup GPIO_Exported_Macros GPIO Exported Macros 163 | * @{ 164 | */ 165 | 166 | /** 167 | * @brief Check whether the specified EXTI line flag is set or not. 168 | * @param __EXTI_LINE__ specifies the EXTI line flag to check. 169 | * This parameter can be GPIO_PIN_x where x can be(0..15) 170 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 171 | */ 172 | #define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) 173 | 174 | /** 175 | * @brief Clear the EXTI's line pending flags. 176 | * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. 177 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 178 | * @retval None 179 | */ 180 | #define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) 181 | 182 | /** 183 | * @brief Check whether the specified EXTI line is asserted or not. 184 | * @param __EXTI_LINE__ specifies the EXTI line to check. 185 | * This parameter can be GPIO_PIN_x where x can be(0..15) 186 | * @retval The new state of __EXTI_LINE__ (SET or RESET). 187 | */ 188 | #define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__)) 189 | 190 | /** 191 | * @brief Clear the EXTI's line pending bits. 192 | * @param __EXTI_LINE__ specifies the EXTI lines to clear. 193 | * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) 194 | * @retval None 195 | */ 196 | #define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__)) 197 | 198 | /** 199 | * @brief Generate a Software interrupt on selected EXTI line. 200 | * @param __EXTI_LINE__ specifies the EXTI line to check. 201 | * This parameter can be GPIO_PIN_x where x can be(0..15) 202 | * @retval None 203 | */ 204 | #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__)) 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /* Private macros ------------------------------------------------------------*/ 211 | /** @addtogroup GPIO_Private_Macros GPIO Private Macros 212 | * @{ 213 | */ 214 | #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) 215 | 216 | #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ 217 | (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) 218 | 219 | #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ 220 | ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ 221 | ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ 222 | ((__MODE__) == GPIO_MODE_AF_PP) ||\ 223 | ((__MODE__) == GPIO_MODE_AF_OD) ||\ 224 | ((__MODE__) == GPIO_MODE_IT_RISING) ||\ 225 | ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ 226 | ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ 227 | ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ 228 | ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ 229 | ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ 230 | ((__MODE__) == GPIO_MODE_ANALOG) ||\ 231 | ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL)) 232 | 233 | #define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ 234 | ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ 235 | ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ 236 | ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) 237 | 238 | #define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ 239 | ((__PULL__) == GPIO_PULLUP) || \ 240 | ((__PULL__) == GPIO_PULLDOWN)) 241 | /** 242 | * @} 243 | */ 244 | 245 | /* Include GPIO HAL Extended module */ 246 | #include "stm32l4xx_hal_gpio_ex.h" 247 | 248 | /* Exported functions --------------------------------------------------------*/ 249 | /** @addtogroup GPIO_Exported_Functions GPIO Exported Functions 250 | * @{ 251 | */ 252 | 253 | /** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 254 | * @brief Initialization and Configuration functions 255 | * @{ 256 | */ 257 | 258 | /* Initialization and de-initialization functions *****************************/ 259 | void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); 260 | void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); 261 | 262 | /** 263 | * @} 264 | */ 265 | 266 | /** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 267 | * @{ 268 | */ 269 | 270 | /* IO operation functions *****************************************************/ 271 | GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 272 | void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); 273 | void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 274 | HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 275 | void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); 276 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); 277 | 278 | /** 279 | * @} 280 | */ 281 | 282 | /** 283 | * @} 284 | */ 285 | 286 | /** 287 | * @} 288 | */ 289 | 290 | /** 291 | * @} 292 | */ 293 | 294 | #ifdef __cplusplus 295 | } 296 | #endif 297 | 298 | #endif /* STM32L4xx_HAL_GPIO_H */ 299 | 300 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 301 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_i2c_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of I2C HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_HAL_I2C_EX_H 22 | #define STM32L4xx_HAL_I2C_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32l4xx_hal_def.h" 30 | 31 | /** @addtogroup STM32L4xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup I2CEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter 46 | * @{ 47 | */ 48 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U 49 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 50 | /** 51 | * @} 52 | */ 53 | 54 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus 55 | * @{ 56 | */ 57 | #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ 58 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ 59 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ 60 | #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 61 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ 62 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ 63 | #else 64 | #define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ 65 | #define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ 66 | #endif 67 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ 68 | #if defined(SYSCFG_CFGR1_I2C2_FMP) 69 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ 70 | #else 71 | #define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ 72 | #endif 73 | #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ 74 | #if defined(SYSCFG_CFGR1_I2C4_FMP) 75 | #define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ 76 | #else 77 | #define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ 78 | #endif 79 | /** 80 | * @} 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | 87 | /* Exported macro ------------------------------------------------------------*/ 88 | /** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros 89 | * @{ 90 | */ 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /* Exported functions --------------------------------------------------------*/ 97 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions 98 | * @{ 99 | */ 100 | 101 | /** @addtogroup I2CEx_Exported_Functions_Group1 I2C Extended Filter Mode Functions 102 | * @{ 103 | */ 104 | /* Peripheral Control functions ************************************************/ 105 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); 106 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @addtogroup I2CEx_Exported_Functions_Group2 I2C Extended WakeUp Mode Functions 112 | * @{ 113 | */ 114 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); 115 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); 116 | /** 117 | * @} 118 | */ 119 | 120 | /** @addtogroup I2CEx_Exported_Functions_Group3 I2C Extended FastModePlus Functions 121 | * @{ 122 | */ 123 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); 124 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); 125 | /** 126 | * @} 127 | */ 128 | 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /* Private constants ---------------------------------------------------------*/ 135 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants 136 | * @{ 137 | */ 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /* Private macros ------------------------------------------------------------*/ 144 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros 145 | * @{ 146 | */ 147 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ 148 | ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 149 | 150 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 151 | 152 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ 153 | ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ 154 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ 155 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ 156 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ 157 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ 158 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ 159 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \ 160 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4))) 161 | /** 162 | * @} 163 | */ 164 | 165 | /* Private Functions ---------------------------------------------------------*/ 166 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions 167 | * @{ 168 | */ 169 | /* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */ 170 | /** 171 | * @} 172 | */ 173 | 174 | /** 175 | * @} 176 | */ 177 | 178 | /** 179 | * @} 180 | */ 181 | 182 | #ifdef __cplusplus 183 | } 184 | #endif 185 | 186 | #endif /* STM32L4xx_HAL_I2C_EX_H */ 187 | 188 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 189 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2017 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32L4xx_HAL_PWR_H 22 | #define STM32L4xx_HAL_PWR_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32l4xx_hal_def.h" 30 | 31 | /** @addtogroup STM32L4xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWR 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | 41 | /** @defgroup PWR_Exported_Types PWR Exported Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief PWR PVD configuration structure definition 47 | */ 48 | typedef struct 49 | { 50 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 51 | This parameter can be a value of @ref PWR_PVD_detection_level. */ 52 | 53 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 54 | This parameter can be a value of @ref PWR_PVD_Mode. */ 55 | }PWR_PVDTypeDef; 56 | 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /* Exported constants --------------------------------------------------------*/ 63 | 64 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 65 | * @{ 66 | */ 67 | 68 | 69 | /** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels 70 | * @{ 71 | */ 72 | #define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */ 73 | #define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */ 74 | #define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */ 75 | #define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */ 76 | #define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */ 77 | #define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */ 78 | #define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */ 79 | #define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */ 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode 85 | * @{ 86 | */ 87 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */ 88 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ 89 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ 90 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 91 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ 92 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ 93 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ 94 | /** 95 | * @} 96 | */ 97 | 98 | 99 | 100 | 101 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode 102 | * @{ 103 | */ 104 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */ 105 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */ 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 111 | * @{ 112 | */ 113 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */ 114 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */ 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 120 | * @{ 121 | */ 122 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */ 123 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */ 124 | /** 125 | * @} 126 | */ 127 | 128 | 129 | /** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line 130 | * @{ 131 | */ 132 | #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line 138 | * @{ 139 | */ 140 | #define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */ 141 | /** 142 | * @} 143 | */ 144 | 145 | /** 146 | * @} 147 | */ 148 | 149 | /* Exported macros -----------------------------------------------------------*/ 150 | /** @defgroup PWR_Exported_Macros PWR Exported Macros 151 | * @{ 152 | */ 153 | 154 | /** @brief Check whether or not a specific PWR flag is set. 155 | * @param __FLAG__ specifies the flag to check. 156 | * This parameter can be one of the following values: 157 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event 158 | * was received from the WKUP pin 1. 159 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event 160 | * was received from the WKUP pin 2. 161 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event 162 | * was received from the WKUP pin 3. 163 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event 164 | * was received from the WKUP pin 4. 165 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event 166 | * was received from the WKUP pin 5. 167 | * @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system 168 | * entered StandBy mode. 169 | * @arg @ref PWR_FLAG_EXT_SMPS External SMPS Ready Flag. When available on device, indicates 170 | * that external switch can be closed to connect to the external SMPS, when the Range 2 171 | * of internal regulator is ready. 172 | * @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on 173 | * the internal wakeup line. 174 | * @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the 175 | * low-power regulator is ready. 176 | * @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the 177 | * regulator is ready in main mode or is in low-power mode. 178 | * @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready 179 | * in the selected voltage range or is still changing to the required voltage level. 180 | * @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is 181 | * below or above the selected PVD threshold. 182 | * @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is 183 | * is below or above PVM1 threshold (applicable when USB feature is supported). 184 | @if STM32L486xx 185 | * @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is 186 | * is below or above PVM2 threshold (applicable when VDDIO2 is present on device). 187 | @endif 188 | * @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is 189 | * is below or above PVM3 threshold. 190 | * @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is 191 | * is below or above PVM4 threshold. 192 | * 193 | * @retval The new state of __FLAG__ (TRUE or FALSE). 194 | */ 195 | #define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\ 196 | (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\ 197 | (PWR->SR2 & (1U << ((__FLAG__) & 31U))) ) 198 | 199 | /** @brief Clear a specific PWR flag. 200 | * @param __FLAG__ specifies the flag to clear. 201 | * This parameter can be one of the following values: 202 | * @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event 203 | * was received from the WKUP pin 1. 204 | * @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event 205 | * was received from the WKUP pin 2. 206 | * @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event 207 | * was received from the WKUP pin 3. 208 | * @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event 209 | * was received from the WKUP pin 4. 210 | * @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event 211 | * was received from the WKUP pin 5. 212 | * @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags. 213 | * @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system 214 | * entered Standby mode. 215 | * @retval None 216 | */ 217 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\ 218 | (PWR->SCR = (__FLAG__)) :\ 219 | (PWR->SCR = (1U << ((__FLAG__) & 31U))) ) 220 | /** 221 | * @brief Enable the PVD Extended Interrupt Line. 222 | * @retval None 223 | */ 224 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 225 | 226 | /** 227 | * @brief Disable the PVD Extended Interrupt Line. 228 | * @retval None 229 | */ 230 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 231 | 232 | /** 233 | * @brief Enable the PVD Event Line. 234 | * @retval None 235 | */ 236 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) 237 | 238 | /** 239 | * @brief Disable the PVD Event Line. 240 | * @retval None 241 | */ 242 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD) 243 | 244 | /** 245 | * @brief Enable the PVD Extended Interrupt Rising Trigger. 246 | * @retval None 247 | */ 248 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 249 | 250 | /** 251 | * @brief Disable the PVD Extended Interrupt Rising Trigger. 252 | * @retval None 253 | */ 254 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 255 | 256 | /** 257 | * @brief Enable the PVD Extended Interrupt Falling Trigger. 258 | * @retval None 259 | */ 260 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 261 | 262 | 263 | /** 264 | * @brief Disable the PVD Extended Interrupt Falling Trigger. 265 | * @retval None 266 | */ 267 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 268 | 269 | 270 | /** 271 | * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. 272 | * @retval None 273 | */ 274 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 275 | do { \ 276 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 277 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 278 | } while(0) 279 | 280 | /** 281 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 282 | * @retval None 283 | */ 284 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 285 | do { \ 286 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 287 | __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 288 | } while(0) 289 | 290 | /** 291 | * @brief Generate a Software interrupt on selected EXTI line. 292 | * @retval None 293 | */ 294 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) 295 | 296 | /** 297 | * @brief Check whether or not the PVD EXTI interrupt flag is set. 298 | * @retval EXTI PVD Line Status. 299 | */ 300 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD) 301 | 302 | /** 303 | * @brief Clear the PVD EXTI interrupt flag. 304 | * @retval None 305 | */ 306 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD) 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | 313 | /* Private macros --------------------------------------------------------*/ 314 | /** @addtogroup PWR_Private_Macros PWR Private Macros 315 | * @{ 316 | */ 317 | 318 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 319 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 320 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 321 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 322 | 323 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\ 324 | ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ 325 | ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ 326 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 327 | ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ 328 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ 329 | ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 330 | 331 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 332 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 333 | 334 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 335 | 336 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) 337 | 338 | /** 339 | * @} 340 | */ 341 | 342 | /* Include PWR HAL Extended module */ 343 | #include "stm32l4xx_hal_pwr_ex.h" 344 | 345 | /* Exported functions --------------------------------------------------------*/ 346 | 347 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 348 | * @{ 349 | */ 350 | 351 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 352 | * @{ 353 | */ 354 | 355 | /* Initialization and de-initialization functions *******************************/ 356 | void HAL_PWR_DeInit(void); 357 | void HAL_PWR_EnableBkUpAccess(void); 358 | void HAL_PWR_DisableBkUpAccess(void); 359 | 360 | /** 361 | * @} 362 | */ 363 | 364 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 365 | * @{ 366 | */ 367 | 368 | /* Peripheral Control functions ************************************************/ 369 | HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 370 | void HAL_PWR_EnablePVD(void); 371 | void HAL_PWR_DisablePVD(void); 372 | 373 | 374 | /* WakeUp pins configuration functions ****************************************/ 375 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); 376 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 377 | 378 | /* Low Power modes configuration functions ************************************/ 379 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 380 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 381 | void HAL_PWR_EnterSTANDBYMode(void); 382 | 383 | void HAL_PWR_EnableSleepOnExit(void); 384 | void HAL_PWR_DisableSleepOnExit(void); 385 | void HAL_PWR_EnableSEVOnPend(void); 386 | void HAL_PWR_DisableSEVOnPend(void); 387 | 388 | void HAL_PWR_PVDCallback(void); 389 | 390 | 391 | /** 392 | * @} 393 | */ 394 | 395 | /** 396 | * @} 397 | */ 398 | 399 | /** 400 | * @} 401 | */ 402 | 403 | /** 404 | * @} 405 | */ 406 | 407 | #ifdef __cplusplus 408 | } 409 | #endif 410 | 411 | 412 | #endif /* STM32L4xx_HAL_PWR_H */ 413 | 414 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 415 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_dma_ex.c 4 | * @author MCD Application Team 5 | * @brief DMA Extension HAL module driver 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the DMA Extension peripheral: 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### How to use this driver ##### 13 | ============================================================================== 14 | [..] 15 | The DMA Extension HAL driver can be used as follows: 16 | 17 | (+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. 18 | (+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. 19 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used 20 | to respectively enable/disable the request generator. 21 | 22 | (+) To handle the DMAMUX Interrupts, the function HAL_DMAEx_MUX_IRQHandler should be called from 23 | the DMAMUX IRQ handler i.e DMAMUX1_OVR_IRQHandler. 24 | As only one interrupt line is available for all DMAMUX channels and request generators , HAL_DMAEx_MUX_IRQHandler should be 25 | called with, as parameter, the appropriate DMA handle as many as used DMAs in the user project 26 | (exception done if a given DMA is not using the DMAMUX SYNC block neither a request generator) 27 | 28 | -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. 29 | -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. 30 | -@- In Multi (Double) buffer mode, it is possible to update the base address for 31 | the AHB memory port on the fly (DMA_CM0ARx or DMA_CM1ARx) when the channel is enabled. 32 | 33 | 34 | @endverbatim 35 | ****************************************************************************** 36 | * @attention 37 | * 38 | *

© Copyright (c) 2017 STMicroelectronics. 39 | * All rights reserved.

40 | * 41 | * This software component is licensed by ST under BSD 3-Clause license, 42 | * the "License"; You may not use this file except in compliance with the 43 | * License. You may obtain a copy of the License at: 44 | * opensource.org/licenses/BSD-3-Clause 45 | * 46 | ****************************************************************************** 47 | */ 48 | 49 | /* Includes ------------------------------------------------------------------*/ 50 | #include "stm32l4xx_hal.h" 51 | 52 | #if defined(DMAMUX1) 53 | 54 | /** @addtogroup STM32L4xx_HAL_Driver 55 | * @{ 56 | */ 57 | 58 | /** @defgroup DMAEx DMAEx 59 | * @brief DMA Extended HAL module driver 60 | * @{ 61 | */ 62 | 63 | #ifdef HAL_DMA_MODULE_ENABLED 64 | 65 | /* Private typedef -----------------------------------------------------------*/ 66 | /* Private define ------------------------------------------------------------*/ 67 | /* Private macro -------------------------------------------------------------*/ 68 | /* Private variables ---------------------------------------------------------*/ 69 | /* Private Constants ---------------------------------------------------------*/ 70 | /* Private function prototypes -----------------------------------------------*/ 71 | /* Private functions ---------------------------------------------------------*/ 72 | 73 | 74 | /** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions 75 | * @{ 76 | */ 77 | 78 | /** @defgroup DMAEx_Exported_Functions_Group1 DMAEx Extended features functions 79 | * @brief Extended features functions 80 | * 81 | @verbatim 82 | =============================================================================== 83 | ##### Extended features functions ##### 84 | =============================================================================== 85 | [..] This section provides functions allowing to: 86 | 87 | (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. 88 | (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. 89 | Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used 90 | to respectively enable/disable the request generator. 91 | 92 | @endverbatim 93 | * @{ 94 | */ 95 | 96 | 97 | /** 98 | * @brief Configure the DMAMUX synchronization parameters for a given DMA channel (instance). 99 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 100 | * the configuration information for the specified DMA channel. 101 | * @param pSyncConfig : pointer to HAL_DMA_MuxSyncConfigTypeDef : contains the DMAMUX synchronization parameters 102 | * @retval HAL status 103 | */ 104 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig) 105 | { 106 | /* Check the parameters */ 107 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 108 | 109 | assert_param(IS_DMAMUX_SYNC_SIGNAL_ID(pSyncConfig->SyncSignalID)); 110 | 111 | assert_param(IS_DMAMUX_SYNC_POLARITY(pSyncConfig-> SyncPolarity)); 112 | assert_param(IS_DMAMUX_SYNC_STATE(pSyncConfig->SyncEnable)); 113 | assert_param(IS_DMAMUX_SYNC_EVENT(pSyncConfig->EventEnable)); 114 | assert_param(IS_DMAMUX_SYNC_REQUEST_NUMBER(pSyncConfig->RequestNumber)); 115 | 116 | /*Check if the DMA state is ready */ 117 | if(hdma->State == HAL_DMA_STATE_READY) 118 | { 119 | /* Process Locked */ 120 | __HAL_LOCK(hdma); 121 | 122 | /* Set the new synchronization parameters (and keep the request ID filled during the Init)*/ 123 | MODIFY_REG( hdma->DMAmuxChannel->CCR, \ 124 | (~DMAMUX_CxCR_DMAREQ_ID) , \ 125 | ((pSyncConfig->SyncSignalID) << DMAMUX_CxCR_SYNC_ID_Pos) | ((pSyncConfig->RequestNumber - 1U) << DMAMUX_CxCR_NBREQ_Pos) | \ 126 | pSyncConfig->SyncPolarity | ((uint32_t)pSyncConfig->SyncEnable << DMAMUX_CxCR_SE_Pos) | \ 127 | ((uint32_t)pSyncConfig->EventEnable << DMAMUX_CxCR_EGE_Pos)); 128 | 129 | /* Process UnLocked */ 130 | __HAL_UNLOCK(hdma); 131 | 132 | return HAL_OK; 133 | } 134 | else 135 | { 136 | /*DMA State not Ready*/ 137 | return HAL_ERROR; 138 | } 139 | } 140 | 141 | /** 142 | * @brief Configure the DMAMUX request generator block used by the given DMA channel (instance). 143 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 144 | * the configuration information for the specified DMA channel. 145 | * @param pRequestGeneratorConfig : pointer to HAL_DMA_MuxRequestGeneratorConfigTypeDef : 146 | * contains the request generator parameters. 147 | * 148 | * @retval HAL status 149 | */ 150 | HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig) 151 | { 152 | /* Check the parameters */ 153 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 154 | 155 | assert_param(IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(pRequestGeneratorConfig->SignalID)); 156 | 157 | assert_param(IS_DMAMUX_REQUEST_GEN_POLARITY(pRequestGeneratorConfig->Polarity)); 158 | assert_param(IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(pRequestGeneratorConfig->RequestNumber)); 159 | 160 | /* check if the DMA state is ready 161 | and DMA is using a DMAMUX request generator block 162 | */ 163 | if((hdma->State == HAL_DMA_STATE_READY) && (hdma->DMAmuxRequestGen != 0U)) 164 | { 165 | /* Process Locked */ 166 | __HAL_LOCK(hdma); 167 | 168 | /* Set the request generator new parameters */ 169 | hdma->DMAmuxRequestGen->RGCR = pRequestGeneratorConfig->SignalID | \ 170 | ((pRequestGeneratorConfig->RequestNumber - 1U) << DMAMUX_RGxCR_GNBREQ_Pos)| \ 171 | pRequestGeneratorConfig->Polarity; 172 | /* Process UnLocked */ 173 | __HAL_UNLOCK(hdma); 174 | 175 | return HAL_OK; 176 | } 177 | else 178 | { 179 | return HAL_ERROR; 180 | } 181 | } 182 | 183 | /** 184 | * @brief Enable the DMAMUX request generator block used by the given DMA channel (instance). 185 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 186 | * the configuration information for the specified DMA channel. 187 | * @retval HAL status 188 | */ 189 | HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma) 190 | { 191 | /* Check the parameters */ 192 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 193 | 194 | /* check if the DMA state is ready 195 | and DMA is using a DMAMUX request generator block 196 | */ 197 | if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) 198 | { 199 | 200 | /* Enable the request generator*/ 201 | hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_GE; 202 | 203 | return HAL_OK; 204 | } 205 | else 206 | { 207 | return HAL_ERROR; 208 | } 209 | } 210 | 211 | /** 212 | * @brief Disable the DMAMUX request generator block used by the given DMA channel (instance). 213 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 214 | * the configuration information for the specified DMA channel. 215 | * @retval HAL status 216 | */ 217 | HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma) 218 | { 219 | /* Check the parameters */ 220 | assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 221 | 222 | /* check if the DMA state is ready 223 | and DMA is using a DMAMUX request generator block 224 | */ 225 | if((hdma->State != HAL_DMA_STATE_RESET) && (hdma->DMAmuxRequestGen != 0)) 226 | { 227 | 228 | /* Disable the request generator*/ 229 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_GE; 230 | 231 | return HAL_OK; 232 | } 233 | else 234 | { 235 | return HAL_ERROR; 236 | } 237 | } 238 | 239 | /** 240 | * @brief Handles DMAMUX interrupt request. 241 | * @param hdma pointer to a DMA_HandleTypeDef structure that contains 242 | * the configuration information for the specified DMA channel. 243 | * @retval None 244 | */ 245 | void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma) 246 | { 247 | /* Check for DMAMUX Synchronization overrun */ 248 | if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) 249 | { 250 | /* Disable the synchro overrun interrupt */ 251 | hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 252 | 253 | /* Clear the DMAMUX synchro overrun flag */ 254 | hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 255 | 256 | /* Update error code */ 257 | hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; 258 | 259 | if(hdma->XferErrorCallback != NULL) 260 | { 261 | /* Transfer error callback */ 262 | hdma->XferErrorCallback(hdma); 263 | } 264 | } 265 | 266 | if(hdma->DMAmuxRequestGen != 0) 267 | { 268 | /* if using a DMAMUX request generator block Check for DMAMUX request generator overrun */ 269 | if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) 270 | { 271 | /* Disable the request gen overrun interrupt */ 272 | hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 273 | 274 | /* Clear the DMAMUX request generator overrun flag */ 275 | hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 276 | 277 | /* Update error code */ 278 | hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; 279 | 280 | if(hdma->XferErrorCallback != NULL) 281 | { 282 | /* Transfer error callback */ 283 | hdma->XferErrorCallback(hdma); 284 | } 285 | } 286 | } 287 | } 288 | 289 | /** 290 | * @} 291 | */ 292 | 293 | /** 294 | * @} 295 | */ 296 | 297 | #endif /* HAL_DMA_MODULE_ENABLED */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | #endif /* DMAMUX1 */ 308 | 309 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 310 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_flash_ramfunc.c 4 | * @author MCD Application Team 5 | * @brief FLASH RAMFUNC driver. 6 | * This file provides a Flash firmware functions which should be 7 | * executed from internal SRAM 8 | * + FLASH HalfPage Programming 9 | * + FLASH Power Down in Run mode 10 | * 11 | * @verbatim 12 | ============================================================================== 13 | ##### Flash RAM functions ##### 14 | ============================================================================== 15 | 16 | *** ARM Compiler *** 17 | -------------------- 18 | [..] RAM functions are defined using the toolchain options. 19 | Functions that are executed in RAM should reside in a separate 20 | source module. Using the 'Options for File' dialog you can simply change 21 | the 'Code / Const' area of a module to a memory space in physical RAM. 22 | Available memory areas are declared in the 'Target' tab of the 23 | Options for Target' dialog. 24 | 25 | *** ICCARM Compiler *** 26 | ----------------------- 27 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". 28 | 29 | *** GNU Compiler *** 30 | -------------------- 31 | [..] RAM functions are defined using a specific toolchain attribute 32 | "__attribute__((section(".RamFunc")))". 33 | 34 | @endverbatim 35 | ****************************************************************************** 36 | * @attention 37 | * 38 | *

© Copyright (c) 2017 STMicroelectronics. 39 | * All rights reserved.

40 | * 41 | * This software component is licensed by ST under BSD 3-Clause license, 42 | * the "License"; You may not use this file except in compliance with the 43 | * License. You may obtain a copy of the License at: 44 | * opensource.org/licenses/BSD-3-Clause 45 | * 46 | ****************************************************************************** 47 | */ 48 | 49 | /* Includes ------------------------------------------------------------------*/ 50 | #include "stm32l4xx_hal.h" 51 | 52 | /** @addtogroup STM32L4xx_HAL_Driver 53 | * @{ 54 | */ 55 | 56 | /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC 57 | * @brief FLASH functions executed from RAM 58 | * @{ 59 | */ 60 | 61 | #ifdef HAL_FLASH_MODULE_ENABLED 62 | 63 | /* Private typedef -----------------------------------------------------------*/ 64 | /* Private define ------------------------------------------------------------*/ 65 | /* Private macro -------------------------------------------------------------*/ 66 | /* Private variables ---------------------------------------------------------*/ 67 | /* Private function prototypes -----------------------------------------------*/ 68 | /* Exported functions -------------------------------------------------------*/ 69 | 70 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions 71 | * @{ 72 | */ 73 | 74 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 75 | * @brief Data transfers functions 76 | * 77 | @verbatim 78 | =============================================================================== 79 | ##### ramfunc functions ##### 80 | =============================================================================== 81 | [..] 82 | This subsection provides a set of functions that should be executed from RAM. 83 | 84 | @endverbatim 85 | * @{ 86 | */ 87 | 88 | /** 89 | * @brief Enable the Power down in Run Mode 90 | * @note This function should be called and executed from SRAM memory 91 | * @retval HAL status 92 | */ 93 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) 94 | { 95 | /* Enable the Power Down in Run mode*/ 96 | __HAL_FLASH_POWER_DOWN_ENABLE(); 97 | 98 | return HAL_OK; 99 | 100 | } 101 | 102 | /** 103 | * @brief Disable the Power down in Run Mode 104 | * @note This function should be called and executed from SRAM memory 105 | * @retval HAL status 106 | */ 107 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) 108 | { 109 | /* Disable the Power Down in Run mode*/ 110 | __HAL_FLASH_POWER_DOWN_DISABLE(); 111 | 112 | return HAL_OK; 113 | } 114 | 115 | #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 116 | /** 117 | * @brief Program the FLASH DBANK User Option Byte. 118 | * 119 | * @note To configure the user option bytes, the option lock bit OPTLOCK must 120 | * be cleared with the call of the HAL_FLASH_OB_Unlock() function. 121 | * @note To modify the DBANK option byte, no PCROP region should be defined. 122 | * To deactivate PCROP, user should perform RDP changing 123 | * 124 | * @param DBankConfig The FLASH DBANK User Option Byte value. 125 | * This parameter can be one of the following values: 126 | * @arg OB_DBANK_128_BITS: Single-bank with 128-bits data 127 | * @arg OB_DBANK_64_BITS: Dual-bank with 64-bits data 128 | * 129 | * @retval HAL status 130 | */ 131 | __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig) 132 | { 133 | uint32_t count, reg; 134 | HAL_StatusTypeDef status = HAL_ERROR; 135 | 136 | /* Process Locked */ 137 | __HAL_LOCK(&pFlash); 138 | 139 | /* Check if the PCROP is disabled */ 140 | reg = FLASH->PCROP1SR; 141 | if (reg > FLASH->PCROP1ER) 142 | { 143 | reg = FLASH->PCROP2SR; 144 | if (reg > FLASH->PCROP2ER) 145 | { 146 | /* Disable Flash prefetch */ 147 | __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); 148 | 149 | if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != 0U) 150 | { 151 | /* Disable Flash instruction cache */ 152 | __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); 153 | 154 | /* Flush Flash instruction cache */ 155 | __HAL_FLASH_INSTRUCTION_CACHE_RESET(); 156 | } 157 | 158 | if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != 0U) 159 | { 160 | /* Disable Flash data cache */ 161 | __HAL_FLASH_DATA_CACHE_DISABLE(); 162 | 163 | /* Flush Flash data cache */ 164 | __HAL_FLASH_DATA_CACHE_RESET(); 165 | } 166 | 167 | /* Disable WRP zone 1 of 1st bank if needed */ 168 | reg = FLASH->WRP1AR; 169 | if (((reg & FLASH_WRP1AR_WRP1A_STRT) >> FLASH_WRP1AR_WRP1A_STRT_Pos) <= 170 | ((reg & FLASH_WRP1AR_WRP1A_END) >> FLASH_WRP1AR_WRP1A_END_Pos)) 171 | { 172 | MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), FLASH_WRP1AR_WRP1A_STRT); 173 | } 174 | 175 | /* Disable WRP zone 2 of 1st bank if needed */ 176 | reg = FLASH->WRP1BR; 177 | if (((reg & FLASH_WRP1BR_WRP1B_STRT) >> FLASH_WRP1BR_WRP1B_STRT_Pos) <= 178 | ((reg & FLASH_WRP1BR_WRP1B_END) >> FLASH_WRP1BR_WRP1B_END_Pos)) 179 | { 180 | MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), FLASH_WRP1BR_WRP1B_STRT); 181 | } 182 | 183 | /* Disable WRP zone 1 of 2nd bank if needed */ 184 | reg = FLASH->WRP2AR; 185 | if (((reg & FLASH_WRP2AR_WRP2A_STRT) >> FLASH_WRP2AR_WRP2A_STRT_Pos) <= 186 | ((reg & FLASH_WRP2AR_WRP2A_END) >> FLASH_WRP2AR_WRP2A_END_Pos)) 187 | { 188 | MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), FLASH_WRP2AR_WRP2A_STRT); 189 | } 190 | 191 | /* Disable WRP zone 2 of 2nd bank if needed */ 192 | reg = FLASH->WRP2BR; 193 | if (((reg & FLASH_WRP2BR_WRP2B_STRT) >> FLASH_WRP2BR_WRP2B_STRT_Pos) <= 194 | ((reg & FLASH_WRP2BR_WRP2B_END) >> FLASH_WRP2BR_WRP2B_END_Pos)) 195 | { 196 | MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), FLASH_WRP2BR_WRP2B_STRT); 197 | } 198 | 199 | /* Modify the DBANK user option byte */ 200 | MODIFY_REG(FLASH->OPTR, FLASH_OPTR_DBANK, DBankConfig); 201 | 202 | /* Set OPTSTRT Bit */ 203 | SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 204 | 205 | /* Wait for last operation to be completed */ 206 | /* 8 is the number of required instruction cycles for the below loop statement (timeout expressed in ms) */ 207 | count = FLASH_TIMEOUT_VALUE * (SystemCoreClock / 8U / 1000U); 208 | do 209 | { 210 | if (count == 0U) 211 | { 212 | break; 213 | } 214 | count--; 215 | } while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET); 216 | 217 | /* If the option byte program operation is completed, disable the OPTSTRT Bit */ 218 | CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT); 219 | 220 | /* Set the bit to force the option byte reloading */ 221 | SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); 222 | } 223 | } 224 | 225 | /* Process Unlocked */ 226 | __HAL_UNLOCK(&pFlash); 227 | 228 | return status; 229 | } 230 | #endif 231 | 232 | /** 233 | * @} 234 | */ 235 | 236 | /** 237 | * @} 238 | */ 239 | #endif /* HAL_FLASH_MODULE_ENABLED */ 240 | 241 | 242 | 243 | /** 244 | * @} 245 | */ 246 | 247 | /** 248 | * @} 249 | */ 250 | 251 | 252 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 253 | 254 | 255 | -------------------------------------------------------------------------------- /lib/STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32l4xx_hal_i2c_ex.c 4 | * @author MCD Application Team 5 | * @brief I2C Extended HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of I2C Extended peripheral: 8 | * + Extended features functions 9 | * 10 | @verbatim 11 | ============================================================================== 12 | ##### I2C peripheral Extended features ##### 13 | ============================================================================== 14 | 15 | [..] Comparing to other previous devices, the I2C interface for STM32L4xx 16 | devices contains the following additional features 17 | 18 | (+) Possibility to disable or enable Analog Noise Filter 19 | (+) Use of a configured Digital Noise Filter 20 | (+) Disable or enable wakeup from Stop mode(s) 21 | (+) Disable or enable Fast Mode Plus 22 | 23 | ##### How to use this driver ##### 24 | ============================================================================== 25 | [..] This driver provides functions to configure Noise Filter and Wake Up Feature 26 | (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() 27 | (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() 28 | (#) Configure the enable or disable of I2C Wake Up Mode using the functions : 29 | (++) HAL_I2CEx_EnableWakeUp() 30 | (++) HAL_I2CEx_DisableWakeUp() 31 | (#) Configure the enable or disable of fast mode plus driving capability using the functions : 32 | (++) HAL_I2CEx_EnableFastModePlus() 33 | (++) HAL_I2CEx_DisableFastModePlus() 34 | @endverbatim 35 | ****************************************************************************** 36 | * @attention 37 | * 38 | *

© Copyright (c) 2017 STMicroelectronics. 39 | * All rights reserved.

40 | * 41 | * This software component is licensed by ST under BSD 3-Clause license, 42 | * the "License"; You may not use this file except in compliance with the 43 | * License. You may obtain a copy of the License at: 44 | * opensource.org/licenses/BSD-3-Clause 45 | * 46 | ****************************************************************************** 47 | */ 48 | 49 | /* Includes ------------------------------------------------------------------*/ 50 | #include "stm32l4xx_hal.h" 51 | 52 | /** @addtogroup STM32L4xx_HAL_Driver 53 | * @{ 54 | */ 55 | 56 | /** @defgroup I2CEx I2CEx 57 | * @brief I2C Extended HAL module driver 58 | * @{ 59 | */ 60 | 61 | #ifdef HAL_I2C_MODULE_ENABLED 62 | 63 | /* Private typedef -----------------------------------------------------------*/ 64 | /* Private define ------------------------------------------------------------*/ 65 | /* Private macro -------------------------------------------------------------*/ 66 | /* Private variables ---------------------------------------------------------*/ 67 | /* Private function prototypes -----------------------------------------------*/ 68 | /* Private functions ---------------------------------------------------------*/ 69 | 70 | /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions 71 | * @{ 72 | */ 73 | 74 | /** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions 75 | * @brief Extended features functions 76 | * 77 | @verbatim 78 | =============================================================================== 79 | ##### Extended features functions ##### 80 | =============================================================================== 81 | [..] This section provides functions allowing to: 82 | (+) Configure Noise Filters 83 | (+) Configure Wake Up Feature 84 | (+) Configure Fast Mode Plus 85 | 86 | @endverbatim 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Configure I2C Analog noise filter. 92 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 93 | * the configuration information for the specified I2Cx peripheral. 94 | * @param AnalogFilter New state of the Analog filter. 95 | * @retval HAL status 96 | */ 97 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) 98 | { 99 | /* Check the parameters */ 100 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 101 | assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); 102 | 103 | if (hi2c->State == HAL_I2C_STATE_READY) 104 | { 105 | /* Process Locked */ 106 | __HAL_LOCK(hi2c); 107 | 108 | hi2c->State = HAL_I2C_STATE_BUSY; 109 | 110 | /* Disable the selected I2C peripheral */ 111 | __HAL_I2C_DISABLE(hi2c); 112 | 113 | /* Reset I2Cx ANOFF bit */ 114 | hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 115 | 116 | /* Set analog filter bit*/ 117 | hi2c->Instance->CR1 |= AnalogFilter; 118 | 119 | __HAL_I2C_ENABLE(hi2c); 120 | 121 | hi2c->State = HAL_I2C_STATE_READY; 122 | 123 | /* Process Unlocked */ 124 | __HAL_UNLOCK(hi2c); 125 | 126 | return HAL_OK; 127 | } 128 | else 129 | { 130 | return HAL_BUSY; 131 | } 132 | } 133 | 134 | /** 135 | * @brief Configure I2C Digital noise filter. 136 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 137 | * the configuration information for the specified I2Cx peripheral. 138 | * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. 139 | * @retval HAL status 140 | */ 141 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) 142 | { 143 | uint32_t tmpreg; 144 | 145 | /* Check the parameters */ 146 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 147 | assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); 148 | 149 | if (hi2c->State == HAL_I2C_STATE_READY) 150 | { 151 | /* Process Locked */ 152 | __HAL_LOCK(hi2c); 153 | 154 | hi2c->State = HAL_I2C_STATE_BUSY; 155 | 156 | /* Disable the selected I2C peripheral */ 157 | __HAL_I2C_DISABLE(hi2c); 158 | 159 | /* Get the old register value */ 160 | tmpreg = hi2c->Instance->CR1; 161 | 162 | /* Reset I2Cx DNF bits [11:8] */ 163 | tmpreg &= ~(I2C_CR1_DNF); 164 | 165 | /* Set I2Cx DNF coefficient */ 166 | tmpreg |= DigitalFilter << 8U; 167 | 168 | /* Store the new register value */ 169 | hi2c->Instance->CR1 = tmpreg; 170 | 171 | __HAL_I2C_ENABLE(hi2c); 172 | 173 | hi2c->State = HAL_I2C_STATE_READY; 174 | 175 | /* Process Unlocked */ 176 | __HAL_UNLOCK(hi2c); 177 | 178 | return HAL_OK; 179 | } 180 | else 181 | { 182 | return HAL_BUSY; 183 | } 184 | } 185 | 186 | /** 187 | * @brief Enable I2C wakeup from Stop mode(s). 188 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 189 | * the configuration information for the specified I2Cx peripheral. 190 | * @retval HAL status 191 | */ 192 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) 193 | { 194 | /* Check the parameters */ 195 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 196 | 197 | if (hi2c->State == HAL_I2C_STATE_READY) 198 | { 199 | /* Process Locked */ 200 | __HAL_LOCK(hi2c); 201 | 202 | hi2c->State = HAL_I2C_STATE_BUSY; 203 | 204 | /* Disable the selected I2C peripheral */ 205 | __HAL_I2C_DISABLE(hi2c); 206 | 207 | /* Enable wakeup from stop mode */ 208 | hi2c->Instance->CR1 |= I2C_CR1_WUPEN; 209 | 210 | __HAL_I2C_ENABLE(hi2c); 211 | 212 | hi2c->State = HAL_I2C_STATE_READY; 213 | 214 | /* Process Unlocked */ 215 | __HAL_UNLOCK(hi2c); 216 | 217 | return HAL_OK; 218 | } 219 | else 220 | { 221 | return HAL_BUSY; 222 | } 223 | } 224 | 225 | /** 226 | * @brief Disable I2C wakeup from Stop mode(s). 227 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 228 | * the configuration information for the specified I2Cx peripheral. 229 | * @retval HAL status 230 | */ 231 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) 232 | { 233 | /* Check the parameters */ 234 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 235 | 236 | if (hi2c->State == HAL_I2C_STATE_READY) 237 | { 238 | /* Process Locked */ 239 | __HAL_LOCK(hi2c); 240 | 241 | hi2c->State = HAL_I2C_STATE_BUSY; 242 | 243 | /* Disable the selected I2C peripheral */ 244 | __HAL_I2C_DISABLE(hi2c); 245 | 246 | /* Enable wakeup from stop mode */ 247 | hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); 248 | 249 | __HAL_I2C_ENABLE(hi2c); 250 | 251 | hi2c->State = HAL_I2C_STATE_READY; 252 | 253 | /* Process Unlocked */ 254 | __HAL_UNLOCK(hi2c); 255 | 256 | return HAL_OK; 257 | } 258 | else 259 | { 260 | return HAL_BUSY; 261 | } 262 | } 263 | 264 | /** 265 | * @brief Enable the I2C fast mode plus driving capability. 266 | * @param ConfigFastModePlus Selects the pin. 267 | * This parameter can be one of the @ref I2CEx_FastModePlus values 268 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected 269 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 270 | * on each one of the following pins PB6, PB7, PB8 and PB9. 271 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 272 | * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 273 | * @note For all I2C2 pins fast mode plus driving capability can be enabled 274 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 275 | * @note For all I2C3 pins fast mode plus driving capability can be enabled 276 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 277 | * @note For all I2C4 pins fast mode plus driving capability can be enabled 278 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 279 | * @retval None 280 | */ 281 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) 282 | { 283 | /* Check the parameter */ 284 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 285 | 286 | /* Enable SYSCFG clock */ 287 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 288 | 289 | /* Enable fast mode plus driving capability for selected pin */ 290 | SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 291 | } 292 | 293 | /** 294 | * @brief Disable the I2C fast mode plus driving capability. 295 | * @param ConfigFastModePlus Selects the pin. 296 | * This parameter can be one of the @ref I2CEx_FastModePlus values 297 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected 298 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 299 | * on each one of the following pins PB6, PB7, PB8 and PB9. 300 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 301 | * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 302 | * @note For all I2C2 pins fast mode plus driving capability can be disabled 303 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 304 | * @note For all I2C3 pins fast mode plus driving capability can be disabled 305 | * only by using I2C_FASTMODEPLUS_I2C3 parameter. 306 | * @note For all I2C4 pins fast mode plus driving capability can be disabled 307 | * only by using I2C_FASTMODEPLUS_I2C4 parameter. 308 | * @retval None 309 | */ 310 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) 311 | { 312 | /* Check the parameter */ 313 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 314 | 315 | /* Enable SYSCFG clock */ 316 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 317 | 318 | /* Disable fast mode plus driving capability for selected pin */ 319 | CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 320 | } 321 | 322 | /** 323 | * @} 324 | */ 325 | 326 | /** 327 | * @} 328 | */ 329 | 330 | #endif /* HAL_I2C_MODULE_ENABLED */ 331 | /** 332 | * @} 333 | */ 334 | 335 | /** 336 | * @} 337 | */ 338 | 339 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 340 | -------------------------------------------------------------------------------- /project.yml: -------------------------------------------------------------------------------- 1 | --- 2 | 3 | # Notes: 4 | # This example project is setup to build release binaries for an ARM cortex M4 processor 5 | 6 | :project: 7 | :use_exceptions: FALSE 8 | :use_test_preprocessor: TRUE 9 | :use_auxiliary_dependencies: TRUE 10 | :build_root: build 11 | :release_build: TRUE 12 | :test_file_prefix: test_ 13 | :which_ceedling: gem 14 | :ceedling_version: 0.31.1 15 | :default_tasks: 16 | - test:all 17 | 18 | #:test_build: 19 | # :use_assembly: TRUE 20 | 21 | :release_build: 22 | :output: stmBase 23 | :use_assembly: TRUE 24 | :artifacts: 25 | - stmBase.map 26 | 27 | :environment: 28 | 29 | :extension: 30 | :executable: .elf 31 | 32 | :paths: 33 | :test: 34 | - +:test/** 35 | - -:test/support 36 | :source: 37 | - src/** 38 | - lib/** 39 | - startup/** 40 | :include: 41 | 42 | :release_toolchain_include: 43 | - lib/CMSIS/Device/ST/STM32L4xx/Include/** 44 | - lib/CMSIS/Include/** 45 | - lib/STM32L4xx_HAL_Driver/Inc/** 46 | - lib/STM32L4xx_HAL_Driver/Inc/Legacy/** 47 | - src/bsp/ 48 | :support: 49 | - test/support 50 | 51 | :defines: 52 | # in order to add common defines: 53 | # 1) remove the trailing [] from the :common: section 54 | # 2) add entries to the :common: section (e.g. :test: has TEST defined) 55 | :common: &common_defines [] 56 | :test: 57 | - *common_defines 58 | - TEST 59 | :test_preprocess: 60 | - *common_defines 61 | - TEST 62 | 63 | :cmock: 64 | :mock_prefix: mock_ 65 | :when_no_prototypes: :warn 66 | :enforce_strict_ordering: TRUE 67 | :plugins: 68 | - :ignore 69 | - :callback 70 | :treat_as: 71 | uint8: HEX8 72 | uint16: HEX16 73 | uint32: UINT32 74 | int8: INT8 75 | bool: UINT8 76 | 77 | # Add -gcov to the plugins list to make sure of the gcov plugin 78 | # You will need to have gcov and gcovr both installed to make it work. 79 | # For more information on these options, see docs in plugins/gcov 80 | :gcov: 81 | :reports: 82 | - HtmlDetailed 83 | :gcovr: 84 | :html_medium_threshold: 75 85 | :html_high_threshold: 90 86 | 87 | :tools: 88 | :release_compiler: 89 | :executable: arm-none-eabi-gcc #exists in system search path 90 | :arguments: 91 | - ${1} 92 | - -DTARGET 93 | - -mcpu=cortex-m4 94 | - -mthumb 95 | - -mfpu=fpv4-sp-d16 96 | - -mfloat-abi=hard 97 | - -g 98 | - -Isrc/ 99 | - -I"$": COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE 100 | - -Wall 101 | - -Os 102 | - -c 103 | - -o ${2} 104 | :release_linker: 105 | :executable: arm-none-eabi-gcc 106 | :arguments: 107 | - ${1} 108 | - -DTARGET 109 | - -Isrc/ 110 | - -I"$": COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE 111 | - -mcpu=cortex-m4 112 | - -mthumb 113 | - -mfpu=fpv4-sp-d16 114 | - -mfloat-abi=hard 115 | - -Wl,-Map="stmBase.map" 116 | - -g 117 | - -T"startup/STM32L496AGIX_FLASH.ld" 118 | - --specs=nosys.specs 119 | - -o ${2}.elf 120 | :release_assembler: 121 | :executable: arm-none-eabi-gcc 122 | :arguments: 123 | - ${1} 124 | - -DTARGET 125 | - -I"$": COLLECTION_PATHS_RELEASE_TOOLCHAIN_INCLUDE 126 | - -mcpu=cortex-m4 127 | - -mthumb 128 | - -mfpu=fpv4-sp-d16 129 | - -mfloat-abi=hard 130 | - -g 131 | - -Wall 132 | - -Os 133 | - -c 134 | - -o ${2} 135 | 136 | # LIBRARIES 137 | # These libraries are automatically injected into the build process. Those specified as 138 | # common will be used in all types of builds. Otherwise, libraries can be injected in just 139 | # tests or releases. These options are MERGED with the options in supplemental yaml files. 140 | :libraries: 141 | :placement: :end 142 | :flag: "-l${1}" 143 | :path_flag: "-L ${1}" 144 | :system: [] # for example, you might list 'm' to grab the math library 145 | :test: [] 146 | :release: [] 147 | 148 | :plugins: 149 | :load_paths: 150 | - "#{Ceedling.load_path}" 151 | :enabled: 152 | - stdout_pretty_tests_report 153 | - module_generator 154 | ... 155 | -------------------------------------------------------------------------------- /src/bsp/stm32l4xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32l4xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | __HAL_RCC_PWR_CLK_ENABLE(); 72 | 73 | /* System interrupt init*/ 74 | 75 | /* USER CODE BEGIN MspInit 1 */ 76 | 77 | /* USER CODE END MspInit 1 */ 78 | } 79 | 80 | /* USER CODE BEGIN 1 */ 81 | 82 | /* USER CODE END 1 */ 83 | 84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 85 | -------------------------------------------------------------------------------- /src/bsp/stm32l4xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32l4xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32l4xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN PD */ 35 | 36 | /* USER CODE END PD */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN PM */ 40 | 41 | /* USER CODE END PM */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* Private user code ---------------------------------------------------------*/ 54 | /* USER CODE BEGIN 0 */ 55 | 56 | /* USER CODE END 0 */ 57 | 58 | /* External variables --------------------------------------------------------*/ 59 | 60 | /* USER CODE BEGIN EV */ 61 | 62 | /* USER CODE END EV */ 63 | 64 | /******************************************************************************/ 65 | /* Cortex-M4 Processor Interruption and Exception Handlers */ 66 | /******************************************************************************/ 67 | /** 68 | * @brief This function handles Non maskable interrupt. 69 | */ 70 | void NMI_Handler(void) 71 | { 72 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 73 | 74 | /* USER CODE END NonMaskableInt_IRQn 0 */ 75 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 76 | while (1) 77 | { 78 | } 79 | /* USER CODE END NonMaskableInt_IRQn 1 */ 80 | } 81 | 82 | /** 83 | * @brief This function handles Hard fault interrupt. 84 | */ 85 | void HardFault_Handler(void) 86 | { 87 | /* USER CODE BEGIN HardFault_IRQn 0 */ 88 | 89 | /* USER CODE END HardFault_IRQn 0 */ 90 | while (1) 91 | { 92 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 93 | /* USER CODE END W1_HardFault_IRQn 0 */ 94 | } 95 | } 96 | 97 | /** 98 | * @brief This function handles Memory management fault. 99 | */ 100 | void MemManage_Handler(void) 101 | { 102 | /* USER CODE BEGIN MemoryManagement_IRQn 0 */ 103 | 104 | /* USER CODE END MemoryManagement_IRQn 0 */ 105 | while (1) 106 | { 107 | /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ 108 | /* USER CODE END W1_MemoryManagement_IRQn 0 */ 109 | } 110 | } 111 | 112 | /** 113 | * @brief This function handles Prefetch fault, memory access fault. 114 | */ 115 | void BusFault_Handler(void) 116 | { 117 | /* USER CODE BEGIN BusFault_IRQn 0 */ 118 | 119 | /* USER CODE END BusFault_IRQn 0 */ 120 | while (1) 121 | { 122 | /* USER CODE BEGIN W1_BusFault_IRQn 0 */ 123 | /* USER CODE END W1_BusFault_IRQn 0 */ 124 | } 125 | } 126 | 127 | /** 128 | * @brief This function handles Undefined instruction or illegal state. 129 | */ 130 | void UsageFault_Handler(void) 131 | { 132 | /* USER CODE BEGIN UsageFault_IRQn 0 */ 133 | 134 | /* USER CODE END UsageFault_IRQn 0 */ 135 | while (1) 136 | { 137 | /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ 138 | /* USER CODE END W1_UsageFault_IRQn 0 */ 139 | } 140 | } 141 | 142 | /** 143 | * @brief This function handles System service call via SWI instruction. 144 | */ 145 | void SVC_Handler(void) 146 | { 147 | /* USER CODE BEGIN SVCall_IRQn 0 */ 148 | 149 | /* USER CODE END SVCall_IRQn 0 */ 150 | /* USER CODE BEGIN SVCall_IRQn 1 */ 151 | 152 | /* USER CODE END SVCall_IRQn 1 */ 153 | } 154 | 155 | /** 156 | * @brief This function handles Debug monitor. 157 | */ 158 | void DebugMon_Handler(void) 159 | { 160 | /* USER CODE BEGIN DebugMonitor_IRQn 0 */ 161 | 162 | /* USER CODE END DebugMonitor_IRQn 0 */ 163 | /* USER CODE BEGIN DebugMonitor_IRQn 1 */ 164 | 165 | /* USER CODE END DebugMonitor_IRQn 1 */ 166 | } 167 | 168 | /** 169 | * @brief This function handles Pendable request for system service. 170 | */ 171 | void PendSV_Handler(void) 172 | { 173 | /* USER CODE BEGIN PendSV_IRQn 0 */ 174 | 175 | /* USER CODE END PendSV_IRQn 0 */ 176 | /* USER CODE BEGIN PendSV_IRQn 1 */ 177 | 178 | /* USER CODE END PendSV_IRQn 1 */ 179 | } 180 | 181 | /** 182 | * @brief This function handles System tick timer. 183 | */ 184 | void SysTick_Handler(void) 185 | { 186 | /* USER CODE BEGIN SysTick_IRQn 0 */ 187 | 188 | /* USER CODE END SysTick_IRQn 0 */ 189 | HAL_IncTick(); 190 | /* USER CODE BEGIN SysTick_IRQn 1 */ 191 | 192 | /* USER CODE END SysTick_IRQn 1 */ 193 | } 194 | 195 | /******************************************************************************/ 196 | /* STM32L4xx Peripheral Interrupt Handlers */ 197 | /* Add here the Interrupt Handlers for the used peripherals. */ 198 | /* For the available peripheral interrupt handler names, */ 199 | /* please refer to the startup file (startup_stm32l4xx.s). */ 200 | /******************************************************************************/ 201 | 202 | /* USER CODE BEGIN 1 */ 203 | 204 | /* USER CODE END 1 */ 205 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 206 | -------------------------------------------------------------------------------- /src/bsp/stm32l4xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32l4xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32L4xx_IT_H 23 | #define __STM32L4xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void MemManage_Handler(void); 53 | void BusFault_Handler(void); 54 | void UsageFault_Handler(void); 55 | void SVC_Handler(void); 56 | void DebugMon_Handler(void); 57 | void PendSV_Handler(void); 58 | void SysTick_Handler(void); 59 | /* USER CODE BEGIN EFP */ 60 | 61 | /* USER CODE END EFP */ 62 | 63 | #ifdef __cplusplus 64 | } 65 | #endif 66 | 67 | #endif /* __STM32L4xx_IT_H */ 68 | 69 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 70 | -------------------------------------------------------------------------------- /src/bsp/sys.c: -------------------------------------------------------------------------------- 1 | #include "sys.h" 2 | -------------------------------------------------------------------------------- /src/bsp/sys.h: -------------------------------------------------------------------------------- 1 | #ifndef SYS_H 2 | #define SYS_H 3 | 4 | 5 | #endif // SYS_H 6 | -------------------------------------------------------------------------------- /src/bsp/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include 33 | 34 | 35 | /* Variables */ 36 | extern int __io_putchar(int ch) __attribute__((weak)); 37 | extern int __io_getchar(void) __attribute__((weak)); 38 | 39 | 40 | char *__env[1] = { 0 }; 41 | char **environ = __env; 42 | 43 | 44 | /* Functions */ 45 | void initialise_monitor_handles() 46 | { 47 | } 48 | 49 | int _getpid(void) 50 | { 51 | return 1; 52 | } 53 | 54 | int _kill(int pid, int sig) 55 | { 56 | errno = EINVAL; 57 | return -1; 58 | } 59 | 60 | void _exit (int status) 61 | { 62 | _kill(status, -1); 63 | while (1) {} /* Make sure we hang here */ 64 | } 65 | 66 | __attribute__((weak)) int _read(int file, char *ptr, int len) 67 | { 68 | int DataIdx; 69 | 70 | for (DataIdx = 0; DataIdx < len; DataIdx++) 71 | { 72 | *ptr++ = __io_getchar(); 73 | } 74 | 75 | return len; 76 | } 77 | 78 | __attribute__((weak)) int _write(int file, char *ptr, int len) 79 | { 80 | int DataIdx; 81 | 82 | for (DataIdx = 0; DataIdx < len; DataIdx++) 83 | { 84 | __io_putchar(*ptr++); 85 | } 86 | return len; 87 | } 88 | 89 | int _close(int file) 90 | { 91 | return -1; 92 | } 93 | 94 | 95 | int _fstat(int file, struct stat *st) 96 | { 97 | st->st_mode = S_IFCHR; 98 | return 0; 99 | } 100 | 101 | int _isatty(int file) 102 | { 103 | return 1; 104 | } 105 | 106 | int _lseek(int file, int ptr, int dir) 107 | { 108 | return 0; 109 | } 110 | 111 | int _open(char *path, int flags, ...) 112 | { 113 | /* Pretend like we always fail */ 114 | return -1; 115 | } 116 | 117 | int _wait(int *status) 118 | { 119 | errno = ECHILD; 120 | return -1; 121 | } 122 | 123 | int _unlink(char *name) 124 | { 125 | errno = ENOENT; 126 | return -1; 127 | } 128 | 129 | int _times(struct tms *buf) 130 | { 131 | return -1; 132 | } 133 | 134 | int _stat(char *file, struct stat *st) 135 | { 136 | st->st_mode = S_IFCHR; 137 | return 0; 138 | } 139 | 140 | int _link(char *old, char *new) 141 | { 142 | errno = EMLINK; 143 | return -1; 144 | } 145 | 146 | int _fork(void) 147 | { 148 | errno = EAGAIN; 149 | return -1; 150 | } 151 | 152 | int _execve(char *name, char **argv, char **env) 153 | { 154 | errno = ENOMEM; 155 | return -1; 156 | } 157 | -------------------------------------------------------------------------------- /src/bsp/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | 28 | /** 29 | * Pointer to the current high watermark of the heap usage 30 | */ 31 | static uint8_t *__sbrk_heap_end = NULL; 32 | 33 | /** 34 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 35 | * and others from the C library 36 | * 37 | * @verbatim 38 | * ############################################################################ 39 | * # .data # .bss # newlib heap # MSP stack # 40 | * # # # # Reserved by _Min_Stack_Size # 41 | * ############################################################################ 42 | * ^-- RAM start ^-- _end _estack, RAM end --^ 43 | * @endverbatim 44 | * 45 | * This implementation starts allocating at the '_end' linker symbol 46 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 47 | * The implementation considers '_estack' linker symbol to be RAM end 48 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 49 | * reserved size, please increase the '_Min_Stack_Size'. 50 | * 51 | * @param incr Memory size 52 | * @return Pointer to allocated memory 53 | */ 54 | void *_sbrk(ptrdiff_t incr) 55 | { 56 | extern uint8_t _end; /* Symbol defined in the linker script */ 57 | extern uint8_t _estack; /* Symbol defined in the linker script */ 58 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 59 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 60 | const uint8_t *max_heap = (uint8_t *)stack_limit; 61 | uint8_t *prev_heap_end; 62 | 63 | /* Initialize heap end at first call */ 64 | if (NULL == __sbrk_heap_end) 65 | { 66 | __sbrk_heap_end = &_end; 67 | } 68 | 69 | /* Protect heap from growing into the reserved MSP stack */ 70 | if (__sbrk_heap_end + incr > max_heap) 71 | { 72 | errno = ENOMEM; 73 | return (void *)-1; 74 | } 75 | 76 | prev_heap_end = __sbrk_heap_end; 77 | __sbrk_heap_end += incr; 78 | 79 | return (void *)prev_heap_end; 80 | } 81 | -------------------------------------------------------------------------------- /src/bsp/system_stm32l4xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32l4xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File 6 | * 7 | * This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32l4xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * After each device reset the MSI (4 MHz) is used as system clock source. 22 | * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to 23 | * configure the system clock before to branch to main program. 24 | * 25 | * This file configures the system clock as follows: 26 | *============================================================================= 27 | *----------------------------------------------------------------------------- 28 | * System Clock source | MSI 29 | *----------------------------------------------------------------------------- 30 | * SYSCLK(Hz) | 4000000 31 | *----------------------------------------------------------------------------- 32 | * HCLK(Hz) | 4000000 33 | *----------------------------------------------------------------------------- 34 | * AHB Prescaler | 1 35 | *----------------------------------------------------------------------------- 36 | * APB1 Prescaler | 1 37 | *----------------------------------------------------------------------------- 38 | * APB2 Prescaler | 1 39 | *----------------------------------------------------------------------------- 40 | * PLL_M | 1 41 | *----------------------------------------------------------------------------- 42 | * PLL_N | 8 43 | *----------------------------------------------------------------------------- 44 | * PLL_P | 7 45 | *----------------------------------------------------------------------------- 46 | * PLL_Q | 2 47 | *----------------------------------------------------------------------------- 48 | * PLL_R | 2 49 | *----------------------------------------------------------------------------- 50 | * PLLSAI1_P | NA 51 | *----------------------------------------------------------------------------- 52 | * PLLSAI1_Q | NA 53 | *----------------------------------------------------------------------------- 54 | * PLLSAI1_R | NA 55 | *----------------------------------------------------------------------------- 56 | * PLLSAI2_P | NA 57 | *----------------------------------------------------------------------------- 58 | * PLLSAI2_Q | NA 59 | *----------------------------------------------------------------------------- 60 | * PLLSAI2_R | NA 61 | *----------------------------------------------------------------------------- 62 | * Require 48MHz for USB OTG FS, | Disabled 63 | * SDIO and RNG clock | 64 | *----------------------------------------------------------------------------- 65 | *============================================================================= 66 | ****************************************************************************** 67 | * @attention 68 | * 69 | *

© Copyright (c) 2017 STMicroelectronics. 70 | * All rights reserved.

71 | * 72 | * This software component is licensed by ST under Apache License, Version 2.0, 73 | * the "License"; You may not use this file except in compliance with the 74 | * License. You may obtain a copy of the License at: 75 | * opensource.org/licenses/Apache-2.0 76 | * 77 | ****************************************************************************** 78 | */ 79 | 80 | /** @addtogroup CMSIS 81 | * @{ 82 | */ 83 | 84 | /** @addtogroup stm32l4xx_system 85 | * @{ 86 | */ 87 | 88 | /** @addtogroup STM32L4xx_System_Private_Includes 89 | * @{ 90 | */ 91 | 92 | #include "stm32l4xx.h" 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @addtogroup STM32L4xx_System_Private_TypesDefinitions 99 | * @{ 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @addtogroup STM32L4xx_System_Private_Defines 107 | * @{ 108 | */ 109 | 110 | #if !defined (HSE_VALUE) 111 | #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ 112 | #endif /* HSE_VALUE */ 113 | 114 | #if !defined (MSI_VALUE) 115 | #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ 116 | #endif /* MSI_VALUE */ 117 | 118 | #if !defined (HSI_VALUE) 119 | #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ 120 | #endif /* HSI_VALUE */ 121 | 122 | /* Note: Following vector table addresses must be defined in line with linker 123 | configuration. */ 124 | /*!< Uncomment the following line if you need to relocate the vector table 125 | anywhere in Flash or Sram, else the vector table is kept at the automatic 126 | remap of boot address selected */ 127 | /* #define USER_VECT_TAB_ADDRESS */ 128 | 129 | #if defined(USER_VECT_TAB_ADDRESS) 130 | /*!< Uncomment the following line if you need to relocate your vector Table 131 | in Sram else user remap will be done in Flash. */ 132 | /* #define VECT_TAB_SRAM */ 133 | 134 | #if defined(VECT_TAB_SRAM) 135 | #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. 136 | This value must be a multiple of 0x200. */ 137 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 138 | This value must be a multiple of 0x200. */ 139 | #else 140 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. 141 | This value must be a multiple of 0x200. */ 142 | #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. 143 | This value must be a multiple of 0x200. */ 144 | #endif /* VECT_TAB_SRAM */ 145 | #endif /* USER_VECT_TAB_ADDRESS */ 146 | 147 | /******************************************************************************/ 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @addtogroup STM32L4xx_System_Private_Macros 153 | * @{ 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** @addtogroup STM32L4xx_System_Private_Variables 161 | * @{ 162 | */ 163 | /* The SystemCoreClock variable is updated in three ways: 164 | 1) by calling CMSIS function SystemCoreClockUpdate() 165 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 166 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 167 | Note: If you use this function to configure the system clock; then there 168 | is no need to call the 2 first functions listed above, since SystemCoreClock 169 | variable is updated automatically. 170 | */ 171 | uint32_t SystemCoreClock = 4000000U; 172 | 173 | const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; 174 | const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; 175 | const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ 176 | 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; 177 | /** 178 | * @} 179 | */ 180 | 181 | /** @addtogroup STM32L4xx_System_Private_FunctionPrototypes 182 | * @{ 183 | */ 184 | 185 | /** 186 | * @} 187 | */ 188 | 189 | /** @addtogroup STM32L4xx_System_Private_Functions 190 | * @{ 191 | */ 192 | 193 | /** 194 | * @brief Setup the microcontroller system. 195 | * @retval None 196 | */ 197 | 198 | void SystemInit(void) 199 | { 200 | #if defined(USER_VECT_TAB_ADDRESS) 201 | /* Configure the Vector Table location -------------------------------------*/ 202 | SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; 203 | #endif 204 | 205 | /* FPU settings ------------------------------------------------------------*/ 206 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 207 | SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ 208 | #endif 209 | 210 | /* Reset the RCC clock configuration to the default reset state ------------*/ 211 | /* Set MSION bit */ 212 | RCC->CR |= RCC_CR_MSION; 213 | 214 | /* Reset CFGR register */ 215 | RCC->CFGR = 0x00000000U; 216 | 217 | /* Reset HSEON, CSSON , HSION, and PLLON bits */ 218 | RCC->CR &= 0xEAF6FFFFU; 219 | 220 | /* Reset PLLCFGR register */ 221 | RCC->PLLCFGR = 0x00001000U; 222 | 223 | /* Reset HSEBYP bit */ 224 | RCC->CR &= 0xFFFBFFFFU; 225 | 226 | /* Disable all interrupts */ 227 | RCC->CIER = 0x00000000U; 228 | } 229 | 230 | /** 231 | * @brief Update SystemCoreClock variable according to Clock Register Values. 232 | * The SystemCoreClock variable contains the core clock (HCLK), it can 233 | * be used by the user application to setup the SysTick timer or configure 234 | * other parameters. 235 | * 236 | * @note Each time the core clock (HCLK) changes, this function must be called 237 | * to update SystemCoreClock variable value. Otherwise, any configuration 238 | * based on this variable will be incorrect. 239 | * 240 | * @note - The system frequency computed by this function is not the real 241 | * frequency in the chip. It is calculated based on the predefined 242 | * constant and the selected clock source: 243 | * 244 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) 245 | * 246 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) 247 | * 248 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) 249 | * 250 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) 251 | * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. 252 | * 253 | * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value 254 | * 4 MHz) but the real value may vary depending on the variations 255 | * in voltage and temperature. 256 | * 257 | * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value 258 | * 16 MHz) but the real value may vary depending on the variations 259 | * in voltage and temperature. 260 | * 261 | * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value 262 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 263 | * frequency of the crystal used. Otherwise, this function may 264 | * have wrong result. 265 | * 266 | * - The result of this function could be not correct when using fractional 267 | * value for HSE crystal. 268 | * 269 | * @retval None 270 | */ 271 | void SystemCoreClockUpdate(void) 272 | { 273 | uint32_t tmp, msirange, pllvco, pllsource, pllm, pllr; 274 | 275 | /* Get MSI Range frequency--------------------------------------------------*/ 276 | if ((RCC->CR & RCC_CR_MSIRGSEL) == 0U) 277 | { /* MSISRANGE from RCC_CSR applies */ 278 | msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; 279 | } 280 | else 281 | { /* MSIRANGE from RCC_CR applies */ 282 | msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; 283 | } 284 | /*MSI frequency range in HZ*/ 285 | msirange = MSIRangeTable[msirange]; 286 | 287 | /* Get SYSCLK source -------------------------------------------------------*/ 288 | switch (RCC->CFGR & RCC_CFGR_SWS) 289 | { 290 | case 0x00: /* MSI used as system clock source */ 291 | SystemCoreClock = msirange; 292 | break; 293 | 294 | case 0x04: /* HSI used as system clock source */ 295 | SystemCoreClock = HSI_VALUE; 296 | break; 297 | 298 | case 0x08: /* HSE used as system clock source */ 299 | SystemCoreClock = HSE_VALUE; 300 | break; 301 | 302 | case 0x0C: /* PLL used as system clock source */ 303 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN 304 | SYSCLK = PLL_VCO / PLLR 305 | */ 306 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 307 | pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; 308 | 309 | switch (pllsource) 310 | { 311 | case 0x02: /* HSI used as PLL clock source */ 312 | pllvco = (HSI_VALUE / pllm); 313 | break; 314 | 315 | case 0x03: /* HSE used as PLL clock source */ 316 | pllvco = (HSE_VALUE / pllm); 317 | break; 318 | 319 | default: /* MSI used as PLL clock source */ 320 | pllvco = (msirange / pllm); 321 | break; 322 | } 323 | pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); 324 | pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; 325 | SystemCoreClock = pllvco/pllr; 326 | break; 327 | 328 | default: 329 | SystemCoreClock = msirange; 330 | break; 331 | } 332 | /* Compute HCLK clock frequency --------------------------------------------*/ 333 | /* Get HCLK prescaler */ 334 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; 335 | /* HCLK clock frequency */ 336 | SystemCoreClock >>= tmp; 337 | } 338 | 339 | 340 | /** 341 | * @} 342 | */ 343 | 344 | /** 345 | * @} 346 | */ 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 353 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include "main.h" 2 | 3 | #ifdef TEST 4 | #define LOOP 5 | #else 6 | #define LOOP while(1) 7 | #include "stm32l4xx.h" 8 | int main ( void ) 9 | { 10 | #ifdef TARGET 11 | return AppMain(); 12 | #else 13 | return 0; 14 | #endif 15 | } 16 | #endif // TEST 17 | 18 | 19 | int AppMain( void ) 20 | { 21 | 22 | LOOP 23 | { 24 | 25 | } 26 | return 0; 27 | } 28 | -------------------------------------------------------------------------------- /src/main.h: -------------------------------------------------------------------------------- 1 | #ifndef MAIN_H 2 | #define MAIN_H 3 | 4 | #ifdef TARGET 5 | #include "stm32l4xx_hal.h" 6 | #endif // TARGET 7 | 8 | int AppMain( void ); 9 | 10 | #endif // MAIN_H 11 | -------------------------------------------------------------------------------- /startup/STM32L496AGIX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** @brief : Linker script for STM32L496AGIx Device from STM32L4 series 9 | ** 1024Kbytes FLASH 10 | ** 256Kbytes RAM 11 | ** 64Kbytes RAM2 12 | ** 13 | ** Set heap size, stack size and stack location according 14 | ** to application requirements. 15 | ** 16 | ** Set memory bank area and size if external memory is used 17 | ** 18 | ** Target : STMicroelectronics STM32 19 | ** 20 | ** Distribution: The file is distributed as is, without any warranty 21 | ** of any kind. 22 | ** 23 | ****************************************************************************** 24 | ** @attention 25 | ** 26 | **

© Copyright (c) 2021 STMicroelectronics. 27 | ** All rights reserved.

28 | ** 29 | ** This software component is licensed by ST under BSD 3-Clause license, 30 | ** the "License"; You may not use this file except in compliance with the 31 | ** License. You may obtain a copy of the License at: 32 | ** opensource.org/licenses/BSD-3-Clause 33 | ** 34 | ****************************************************************************** 35 | */ 36 | 37 | /* Entry Point */ 38 | ENTRY(Reset_Handler) 39 | 40 | /* Highest address of the user mode stack */ 41 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 42 | 43 | _Min_Heap_Size = 0x200; /* required amount of heap */ 44 | _Min_Stack_Size = 0x400; /* required amount of stack */ 45 | 46 | /* Memories definition */ 47 | MEMORY 48 | { 49 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K 50 | RAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 64K 51 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K 52 | } 53 | 54 | /* Sections */ 55 | SECTIONS 56 | { 57 | /* The startup code into "FLASH" Rom type memory */ 58 | .isr_vector : 59 | { 60 | . = ALIGN(4); 61 | KEEP(*(.isr_vector)) /* Startup code */ 62 | . = ALIGN(4); 63 | } >FLASH 64 | 65 | /* The program code and other data into "FLASH" Rom type memory */ 66 | .text : 67 | { 68 | . = ALIGN(4); 69 | *(.text) /* .text sections (code) */ 70 | *(.text*) /* .text* sections (code) */ 71 | *(.glue_7) /* glue arm to thumb code */ 72 | *(.glue_7t) /* glue thumb to arm code */ 73 | *(.eh_frame) 74 | 75 | KEEP (*(.init)) 76 | KEEP (*(.fini)) 77 | 78 | . = ALIGN(4); 79 | _etext = .; /* define a global symbols at end of code */ 80 | } >FLASH 81 | 82 | /* Constant data into "FLASH" Rom type memory */ 83 | .rodata : 84 | { 85 | . = ALIGN(4); 86 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 87 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 88 | . = ALIGN(4); 89 | } >FLASH 90 | 91 | .ARM.extab : { 92 | . = ALIGN(4); 93 | *(.ARM.extab* .gnu.linkonce.armextab.*) 94 | . = ALIGN(4); 95 | } >FLASH 96 | 97 | .ARM : { 98 | . = ALIGN(4); 99 | __exidx_start = .; 100 | *(.ARM.exidx*) 101 | __exidx_end = .; 102 | . = ALIGN(4); 103 | } >FLASH 104 | 105 | .preinit_array : 106 | { 107 | . = ALIGN(4); 108 | PROVIDE_HIDDEN (__preinit_array_start = .); 109 | KEEP (*(.preinit_array*)) 110 | PROVIDE_HIDDEN (__preinit_array_end = .); 111 | . = ALIGN(4); 112 | } >FLASH 113 | 114 | .init_array : 115 | { 116 | . = ALIGN(4); 117 | PROVIDE_HIDDEN (__init_array_start = .); 118 | KEEP (*(SORT(.init_array.*))) 119 | KEEP (*(.init_array*)) 120 | PROVIDE_HIDDEN (__init_array_end = .); 121 | . = ALIGN(4); 122 | } >FLASH 123 | 124 | .fini_array : 125 | { 126 | . = ALIGN(4); 127 | PROVIDE_HIDDEN (__fini_array_start = .); 128 | KEEP (*(SORT(.fini_array.*))) 129 | KEEP (*(.fini_array*)) 130 | PROVIDE_HIDDEN (__fini_array_end = .); 131 | . = ALIGN(4); 132 | } >FLASH 133 | 134 | /* Used by the startup to initialize data */ 135 | _sidata = LOADADDR(.data); 136 | 137 | /* Initialized data sections into "RAM" Ram type memory */ 138 | .data : 139 | { 140 | . = ALIGN(4); 141 | _sdata = .; /* create a global symbol at data start */ 142 | *(.data) /* .data sections */ 143 | *(.data*) /* .data* sections */ 144 | *(.RamFunc) /* .RamFunc sections */ 145 | *(.RamFunc*) /* .RamFunc* sections */ 146 | 147 | . = ALIGN(4); 148 | _edata = .; /* define a global symbol at data end */ 149 | 150 | } >RAM AT> FLASH 151 | 152 | /* Uninitialized data section into "RAM" Ram type memory */ 153 | . = ALIGN(4); 154 | .bss : 155 | { 156 | /* This is used by the startup in order to initialize the .bss section */ 157 | _sbss = .; /* define a global symbol at bss start */ 158 | __bss_start__ = _sbss; 159 | *(.bss) 160 | *(.bss*) 161 | *(COMMON) 162 | 163 | . = ALIGN(4); 164 | _ebss = .; /* define a global symbol at bss end */ 165 | __bss_end__ = _ebss; 166 | } >RAM 167 | 168 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 169 | ._user_heap_stack : 170 | { 171 | . = ALIGN(8); 172 | PROVIDE ( end = . ); 173 | PROVIDE ( _end = . ); 174 | . = . + _Min_Heap_Size; 175 | . = . + _Min_Stack_Size; 176 | . = ALIGN(8); 177 | } >RAM 178 | 179 | /* Remove information from the compiler libraries */ 180 | /DISCARD/ : 181 | { 182 | libc.a ( * ) 183 | libm.a ( * ) 184 | libgcc.a ( * ) 185 | } 186 | 187 | .ARM.attributes 0 : { *(.ARM.attributes) } 188 | } 189 | -------------------------------------------------------------------------------- /startup/startup_stm32l496agix.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32l496xx.s 4 | * @author MCD Application Team 5 | * @brief STM32L496xx devices vector table GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address, 10 | * - Configure the clock system 11 | * - Branches to main in the C library (which eventually 12 | * calls main()). 13 | * After Reset the Cortex-M4 processor is in Thread mode, 14 | * priority is Privileged, and the Stack is set to Main. 15 | ****************************************************************************** 16 | * @attention 17 | * 18 | *

© Copyright (c) 2017 STMicroelectronics. 19 | * All rights reserved.

20 | * 21 | * This software component is licensed by ST under Apache License, Version 2.0, 22 | * the "License"; You may not use this file except in compliance with the 23 | * License. You may obtain a copy of the License at: 24 | * opensource.org/licenses/Apache-2.0 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | .syntax unified 30 | .cpu cortex-m4 31 | .fpu softvfp 32 | .thumb 33 | 34 | .global g_pfnVectors 35 | .global Default_Handler 36 | 37 | /* start address for the initialization values of the .data section. 38 | defined in linker script */ 39 | .word _sidata 40 | /* start address for the .data section. defined in linker script */ 41 | .word _sdata 42 | /* end address for the .data section. defined in linker script */ 43 | .word _edata 44 | /* start address for the .bss section. defined in linker script */ 45 | .word _sbss 46 | /* end address for the .bss section. defined in linker script */ 47 | .word _ebss 48 | 49 | .equ BootRAM, 0xF1E0F85F 50 | /** 51 | * @brief This is the code that gets called when the processor first 52 | * starts execution following a reset event. Only the absolutely 53 | * necessary set is performed, after which the application 54 | * supplied main() routine is called. 55 | * @param None 56 | * @retval : None 57 | */ 58 | 59 | .section .text.Reset_Handler 60 | .weak Reset_Handler 61 | .type Reset_Handler, %function 62 | Reset_Handler: 63 | ldr sp, =_estack /* Set stack pointer */ 64 | 65 | /* Call the clock system initialization function.*/ 66 | bl SystemInit 67 | 68 | /* Copy the data segment initializers from flash to SRAM */ 69 | movs r1, #0 70 | b LoopCopyDataInit 71 | 72 | CopyDataInit: 73 | ldr r3, =_sidata 74 | ldr r3, [r3, r1] 75 | str r3, [r0, r1] 76 | adds r1, r1, #4 77 | 78 | LoopCopyDataInit: 79 | ldr r0, =_sdata 80 | ldr r3, =_edata 81 | adds r2, r0, r1 82 | cmp r2, r3 83 | bcc CopyDataInit 84 | ldr r2, =_sbss 85 | b LoopFillZerobss 86 | /* Zero fill the bss segment. */ 87 | FillZerobss: 88 | movs r3, #0 89 | str r3, [r2], #4 90 | 91 | LoopFillZerobss: 92 | ldr r3, = _ebss 93 | cmp r2, r3 94 | bcc FillZerobss 95 | 96 | /* Call static constructors */ 97 | bl __libc_init_array 98 | /* Call the application's entry point.*/ 99 | bl main 100 | 101 | LoopForever: 102 | b LoopForever 103 | 104 | .size Reset_Handler, .-Reset_Handler 105 | 106 | /** 107 | * @brief This is the code that gets called when the processor receives an 108 | * unexpected interrupt. This simply enters an infinite loop, preserving 109 | * the system state for examination by a debugger. 110 | * 111 | * @param None 112 | * @retval : None 113 | */ 114 | .section .text.Default_Handler,"ax",%progbits 115 | Default_Handler: 116 | Infinite_Loop: 117 | b Infinite_Loop 118 | .size Default_Handler, .-Default_Handler 119 | /****************************************************************************** 120 | * 121 | * The minimal vector table for a Cortex-M4. Note that the proper constructs 122 | * must be placed on this to ensure that it ends up at physical address 123 | * 0x0000.0000. 124 | * 125 | ******************************************************************************/ 126 | .section .isr_vector,"a",%progbits 127 | .type g_pfnVectors, %object 128 | .size g_pfnVectors, .-g_pfnVectors 129 | 130 | 131 | g_pfnVectors: 132 | .word _estack 133 | .word Reset_Handler 134 | .word NMI_Handler 135 | .word HardFault_Handler 136 | .word MemManage_Handler 137 | .word BusFault_Handler 138 | .word UsageFault_Handler 139 | .word 0 140 | .word 0 141 | .word 0 142 | .word 0 143 | .word SVC_Handler 144 | .word DebugMon_Handler 145 | .word 0 146 | .word PendSV_Handler 147 | .word SysTick_Handler 148 | .word WWDG_IRQHandler 149 | .word PVD_PVM_IRQHandler 150 | .word TAMP_STAMP_IRQHandler 151 | .word RTC_WKUP_IRQHandler 152 | .word FLASH_IRQHandler 153 | .word RCC_IRQHandler 154 | .word EXTI0_IRQHandler 155 | .word EXTI1_IRQHandler 156 | .word EXTI2_IRQHandler 157 | .word EXTI3_IRQHandler 158 | .word EXTI4_IRQHandler 159 | .word DMA1_Channel1_IRQHandler 160 | .word DMA1_Channel2_IRQHandler 161 | .word DMA1_Channel3_IRQHandler 162 | .word DMA1_Channel4_IRQHandler 163 | .word DMA1_Channel5_IRQHandler 164 | .word DMA1_Channel6_IRQHandler 165 | .word DMA1_Channel7_IRQHandler 166 | .word ADC1_2_IRQHandler 167 | .word CAN1_TX_IRQHandler 168 | .word CAN1_RX0_IRQHandler 169 | .word CAN1_RX1_IRQHandler 170 | .word CAN1_SCE_IRQHandler 171 | .word EXTI9_5_IRQHandler 172 | .word TIM1_BRK_TIM15_IRQHandler 173 | .word TIM1_UP_TIM16_IRQHandler 174 | .word TIM1_TRG_COM_TIM17_IRQHandler 175 | .word TIM1_CC_IRQHandler 176 | .word TIM2_IRQHandler 177 | .word TIM3_IRQHandler 178 | .word TIM4_IRQHandler 179 | .word I2C1_EV_IRQHandler 180 | .word I2C1_ER_IRQHandler 181 | .word I2C2_EV_IRQHandler 182 | .word I2C2_ER_IRQHandler 183 | .word SPI1_IRQHandler 184 | .word SPI2_IRQHandler 185 | .word USART1_IRQHandler 186 | .word USART2_IRQHandler 187 | .word USART3_IRQHandler 188 | .word EXTI15_10_IRQHandler 189 | .word RTC_Alarm_IRQHandler 190 | .word DFSDM1_FLT3_IRQHandler 191 | .word TIM8_BRK_IRQHandler 192 | .word TIM8_UP_IRQHandler 193 | .word TIM8_TRG_COM_IRQHandler 194 | .word TIM8_CC_IRQHandler 195 | .word ADC3_IRQHandler 196 | .word FMC_IRQHandler 197 | .word SDMMC1_IRQHandler 198 | .word TIM5_IRQHandler 199 | .word SPI3_IRQHandler 200 | .word UART4_IRQHandler 201 | .word UART5_IRQHandler 202 | .word TIM6_DAC_IRQHandler 203 | .word TIM7_IRQHandler 204 | .word DMA2_Channel1_IRQHandler 205 | .word DMA2_Channel2_IRQHandler 206 | .word DMA2_Channel3_IRQHandler 207 | .word DMA2_Channel4_IRQHandler 208 | .word DMA2_Channel5_IRQHandler 209 | .word DFSDM1_FLT0_IRQHandler 210 | .word DFSDM1_FLT1_IRQHandler 211 | .word DFSDM1_FLT2_IRQHandler 212 | .word COMP_IRQHandler 213 | .word LPTIM1_IRQHandler 214 | .word LPTIM2_IRQHandler 215 | .word OTG_FS_IRQHandler 216 | .word DMA2_Channel6_IRQHandler 217 | .word DMA2_Channel7_IRQHandler 218 | .word LPUART1_IRQHandler 219 | .word QUADSPI_IRQHandler 220 | .word I2C3_EV_IRQHandler 221 | .word I2C3_ER_IRQHandler 222 | .word SAI1_IRQHandler 223 | .word SAI2_IRQHandler 224 | .word SWPMI1_IRQHandler 225 | .word TSC_IRQHandler 226 | .word LCD_IRQHandler 227 | .word 0 228 | .word RNG_IRQHandler 229 | .word FPU_IRQHandler 230 | .word CRS_IRQHandler 231 | .word I2C4_EV_IRQHandler 232 | .word I2C4_ER_IRQHandler 233 | .word DCMI_IRQHandler 234 | .word CAN2_TX_IRQHandler 235 | .word CAN2_RX0_IRQHandler 236 | .word CAN2_RX1_IRQHandler 237 | .word CAN2_SCE_IRQHandler 238 | .word DMA2D_IRQHandler 239 | 240 | 241 | /******************************************************************************* 242 | * 243 | * Provide weak aliases for each Exception handler to the Default_Handler. 244 | * As they are weak aliases, any function with the same name will override 245 | * this definition. 246 | * 247 | *******************************************************************************/ 248 | 249 | .weak NMI_Handler 250 | .thumb_set NMI_Handler,Default_Handler 251 | 252 | .weak HardFault_Handler 253 | .thumb_set HardFault_Handler,Default_Handler 254 | 255 | .weak MemManage_Handler 256 | .thumb_set MemManage_Handler,Default_Handler 257 | 258 | .weak BusFault_Handler 259 | .thumb_set BusFault_Handler,Default_Handler 260 | 261 | .weak UsageFault_Handler 262 | .thumb_set UsageFault_Handler,Default_Handler 263 | 264 | .weak SVC_Handler 265 | .thumb_set SVC_Handler,Default_Handler 266 | 267 | .weak DebugMon_Handler 268 | .thumb_set DebugMon_Handler,Default_Handler 269 | 270 | .weak PendSV_Handler 271 | .thumb_set PendSV_Handler,Default_Handler 272 | 273 | .weak SysTick_Handler 274 | .thumb_set SysTick_Handler,Default_Handler 275 | 276 | .weak WWDG_IRQHandler 277 | .thumb_set WWDG_IRQHandler,Default_Handler 278 | 279 | .weak PVD_PVM_IRQHandler 280 | .thumb_set PVD_PVM_IRQHandler,Default_Handler 281 | 282 | .weak TAMP_STAMP_IRQHandler 283 | .thumb_set TAMP_STAMP_IRQHandler,Default_Handler 284 | 285 | .weak RTC_WKUP_IRQHandler 286 | .thumb_set RTC_WKUP_IRQHandler,Default_Handler 287 | 288 | .weak FLASH_IRQHandler 289 | .thumb_set FLASH_IRQHandler,Default_Handler 290 | 291 | .weak RCC_IRQHandler 292 | .thumb_set RCC_IRQHandler,Default_Handler 293 | 294 | .weak EXTI0_IRQHandler 295 | .thumb_set EXTI0_IRQHandler,Default_Handler 296 | 297 | .weak EXTI1_IRQHandler 298 | .thumb_set EXTI1_IRQHandler,Default_Handler 299 | 300 | .weak EXTI2_IRQHandler 301 | .thumb_set EXTI2_IRQHandler,Default_Handler 302 | 303 | .weak EXTI3_IRQHandler 304 | .thumb_set EXTI3_IRQHandler,Default_Handler 305 | 306 | .weak EXTI4_IRQHandler 307 | .thumb_set EXTI4_IRQHandler,Default_Handler 308 | 309 | .weak DMA1_Channel1_IRQHandler 310 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 311 | 312 | .weak DMA1_Channel2_IRQHandler 313 | .thumb_set DMA1_Channel2_IRQHandler,Default_Handler 314 | 315 | .weak DMA1_Channel3_IRQHandler 316 | .thumb_set DMA1_Channel3_IRQHandler,Default_Handler 317 | 318 | .weak DMA1_Channel4_IRQHandler 319 | .thumb_set DMA1_Channel4_IRQHandler,Default_Handler 320 | 321 | .weak DMA1_Channel5_IRQHandler 322 | .thumb_set DMA1_Channel5_IRQHandler,Default_Handler 323 | 324 | .weak DMA1_Channel6_IRQHandler 325 | .thumb_set DMA1_Channel6_IRQHandler,Default_Handler 326 | 327 | .weak DMA1_Channel7_IRQHandler 328 | .thumb_set DMA1_Channel7_IRQHandler,Default_Handler 329 | 330 | .weak ADC1_2_IRQHandler 331 | .thumb_set ADC1_2_IRQHandler,Default_Handler 332 | 333 | .weak CAN1_TX_IRQHandler 334 | .thumb_set CAN1_TX_IRQHandler,Default_Handler 335 | 336 | .weak CAN1_RX0_IRQHandler 337 | .thumb_set CAN1_RX0_IRQHandler,Default_Handler 338 | 339 | .weak CAN1_RX1_IRQHandler 340 | .thumb_set CAN1_RX1_IRQHandler,Default_Handler 341 | 342 | .weak CAN1_SCE_IRQHandler 343 | .thumb_set CAN1_SCE_IRQHandler,Default_Handler 344 | 345 | .weak EXTI9_5_IRQHandler 346 | .thumb_set EXTI9_5_IRQHandler,Default_Handler 347 | 348 | .weak TIM1_BRK_TIM15_IRQHandler 349 | .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler 350 | 351 | .weak TIM1_UP_TIM16_IRQHandler 352 | .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler 353 | 354 | .weak TIM1_TRG_COM_TIM17_IRQHandler 355 | .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler 356 | 357 | .weak TIM1_CC_IRQHandler 358 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 359 | 360 | .weak TIM2_IRQHandler 361 | .thumb_set TIM2_IRQHandler,Default_Handler 362 | 363 | .weak TIM3_IRQHandler 364 | .thumb_set TIM3_IRQHandler,Default_Handler 365 | 366 | .weak TIM4_IRQHandler 367 | .thumb_set TIM4_IRQHandler,Default_Handler 368 | 369 | .weak I2C1_EV_IRQHandler 370 | .thumb_set I2C1_EV_IRQHandler,Default_Handler 371 | 372 | .weak I2C1_ER_IRQHandler 373 | .thumb_set I2C1_ER_IRQHandler,Default_Handler 374 | 375 | .weak I2C2_EV_IRQHandler 376 | .thumb_set I2C2_EV_IRQHandler,Default_Handler 377 | 378 | .weak I2C2_ER_IRQHandler 379 | .thumb_set I2C2_ER_IRQHandler,Default_Handler 380 | 381 | .weak SPI1_IRQHandler 382 | .thumb_set SPI1_IRQHandler,Default_Handler 383 | 384 | .weak SPI2_IRQHandler 385 | .thumb_set SPI2_IRQHandler,Default_Handler 386 | 387 | .weak USART1_IRQHandler 388 | .thumb_set USART1_IRQHandler,Default_Handler 389 | 390 | .weak USART2_IRQHandler 391 | .thumb_set USART2_IRQHandler,Default_Handler 392 | 393 | .weak USART3_IRQHandler 394 | .thumb_set USART3_IRQHandler,Default_Handler 395 | 396 | .weak EXTI15_10_IRQHandler 397 | .thumb_set EXTI15_10_IRQHandler,Default_Handler 398 | 399 | .weak RTC_Alarm_IRQHandler 400 | .thumb_set RTC_Alarm_IRQHandler,Default_Handler 401 | 402 | .weak DFSDM1_FLT3_IRQHandler 403 | .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler 404 | 405 | .weak TIM8_BRK_IRQHandler 406 | .thumb_set TIM8_BRK_IRQHandler,Default_Handler 407 | 408 | .weak TIM8_UP_IRQHandler 409 | .thumb_set TIM8_UP_IRQHandler,Default_Handler 410 | 411 | .weak TIM8_TRG_COM_IRQHandler 412 | .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler 413 | 414 | .weak TIM8_CC_IRQHandler 415 | .thumb_set TIM8_CC_IRQHandler,Default_Handler 416 | 417 | .weak ADC3_IRQHandler 418 | .thumb_set ADC3_IRQHandler,Default_Handler 419 | 420 | .weak FMC_IRQHandler 421 | .thumb_set FMC_IRQHandler,Default_Handler 422 | 423 | .weak SDMMC1_IRQHandler 424 | .thumb_set SDMMC1_IRQHandler,Default_Handler 425 | 426 | .weak TIM5_IRQHandler 427 | .thumb_set TIM5_IRQHandler,Default_Handler 428 | 429 | .weak SPI3_IRQHandler 430 | .thumb_set SPI3_IRQHandler,Default_Handler 431 | 432 | .weak UART4_IRQHandler 433 | .thumb_set UART4_IRQHandler,Default_Handler 434 | 435 | .weak UART5_IRQHandler 436 | .thumb_set UART5_IRQHandler,Default_Handler 437 | 438 | .weak TIM6_DAC_IRQHandler 439 | .thumb_set TIM6_DAC_IRQHandler,Default_Handler 440 | 441 | .weak TIM7_IRQHandler 442 | .thumb_set TIM7_IRQHandler,Default_Handler 443 | 444 | .weak DMA2_Channel1_IRQHandler 445 | .thumb_set DMA2_Channel1_IRQHandler,Default_Handler 446 | 447 | .weak DMA2_Channel2_IRQHandler 448 | .thumb_set DMA2_Channel2_IRQHandler,Default_Handler 449 | 450 | .weak DMA2_Channel3_IRQHandler 451 | .thumb_set DMA2_Channel3_IRQHandler,Default_Handler 452 | 453 | .weak DMA2_Channel4_IRQHandler 454 | .thumb_set DMA2_Channel4_IRQHandler,Default_Handler 455 | 456 | .weak DMA2_Channel5_IRQHandler 457 | .thumb_set DMA2_Channel5_IRQHandler,Default_Handler 458 | 459 | .weak DFSDM1_FLT0_IRQHandler 460 | .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler 461 | 462 | .weak DFSDM1_FLT1_IRQHandler 463 | .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler 464 | 465 | .weak DFSDM1_FLT2_IRQHandler 466 | .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler 467 | 468 | .weak COMP_IRQHandler 469 | .thumb_set COMP_IRQHandler,Default_Handler 470 | 471 | .weak LPTIM1_IRQHandler 472 | .thumb_set LPTIM1_IRQHandler,Default_Handler 473 | 474 | .weak LPTIM2_IRQHandler 475 | .thumb_set LPTIM2_IRQHandler,Default_Handler 476 | 477 | .weak OTG_FS_IRQHandler 478 | .thumb_set OTG_FS_IRQHandler,Default_Handler 479 | 480 | .weak DMA2_Channel6_IRQHandler 481 | .thumb_set DMA2_Channel6_IRQHandler,Default_Handler 482 | 483 | .weak DMA2_Channel7_IRQHandler 484 | .thumb_set DMA2_Channel7_IRQHandler,Default_Handler 485 | 486 | .weak LPUART1_IRQHandler 487 | .thumb_set LPUART1_IRQHandler,Default_Handler 488 | 489 | .weak QUADSPI_IRQHandler 490 | .thumb_set QUADSPI_IRQHandler,Default_Handler 491 | 492 | .weak I2C3_EV_IRQHandler 493 | .thumb_set I2C3_EV_IRQHandler,Default_Handler 494 | 495 | .weak I2C3_ER_IRQHandler 496 | .thumb_set I2C3_ER_IRQHandler,Default_Handler 497 | 498 | .weak SAI1_IRQHandler 499 | .thumb_set SAI1_IRQHandler,Default_Handler 500 | 501 | .weak SAI2_IRQHandler 502 | .thumb_set SAI2_IRQHandler,Default_Handler 503 | 504 | .weak SWPMI1_IRQHandler 505 | .thumb_set SWPMI1_IRQHandler,Default_Handler 506 | 507 | .weak TSC_IRQHandler 508 | .thumb_set TSC_IRQHandler,Default_Handler 509 | 510 | .weak LCD_IRQHandler 511 | .thumb_set LCD_IRQHandler,Default_Handler 512 | 513 | .weak RNG_IRQHandler 514 | .thumb_set RNG_IRQHandler,Default_Handler 515 | 516 | .weak FPU_IRQHandler 517 | .thumb_set FPU_IRQHandler,Default_Handler 518 | 519 | .weak CRS_IRQHandler 520 | .thumb_set CRS_IRQHandler,Default_Handler 521 | 522 | .weak I2C4_EV_IRQHandler 523 | .thumb_set I2C4_EV_IRQHandler,Default_Handler 524 | 525 | .weak I2C4_ER_IRQHandler 526 | .thumb_set I2C4_ER_IRQHandler,Default_Handler 527 | 528 | .weak DCMI_IRQHandler 529 | .thumb_set DCMI_IRQHandler,Default_Handler 530 | 531 | .weak CAN2_TX_IRQHandler 532 | .thumb_set CAN2_TX_IRQHandler,Default_Handler 533 | 534 | .weak CAN2_RX0_IRQHandler 535 | .thumb_set CAN2_RX0_IRQHandler,Default_Handler 536 | 537 | .weak CAN2_RX1_IRQHandler 538 | .thumb_set CAN2_RX1_IRQHandler,Default_Handler 539 | 540 | .weak CAN2_SCE_IRQHandler 541 | .thumb_set CAN2_SCE_IRQHandler,Default_Handler 542 | 543 | .weak DMA2D_IRQHandler 544 | .thumb_set FPU_IRQHandler,Default_Handler 545 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 546 | -------------------------------------------------------------------------------- /test/bsp/test_sys.c: -------------------------------------------------------------------------------- 1 | #ifdef TEST 2 | 3 | #include "unity.h" 4 | 5 | #include "sys.h" 6 | 7 | void setUp(void) 8 | { 9 | } 10 | 11 | void tearDown(void) 12 | { 13 | } 14 | 15 | void test_sys_NeedToImplement(void) 16 | { 17 | TEST_IGNORE_MESSAGE("Need to Implement sys"); 18 | } 19 | 20 | #endif // TEST 21 | -------------------------------------------------------------------------------- /test/support/.gitkeep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BojanG72/STM32-Ceedling-Base/42baab22f893cf9116f3d00fa90af7016a6bb0cf/test/support/.gitkeep -------------------------------------------------------------------------------- /test/test_main.c: -------------------------------------------------------------------------------- 1 | #ifdef TEST 2 | 3 | #include "unity.h" 4 | 5 | #include "main.h" 6 | 7 | void setUp(void) 8 | { 9 | } 10 | 11 | void tearDown(void) 12 | { 13 | } 14 | 15 | void test_main_NeedToImplement(void) 16 | { 17 | TEST_IGNORE_MESSAGE("Need to Implement main"); 18 | } 19 | 20 | #endif // TEST 21 | --------------------------------------------------------------------------------