├── project ├── build.properties └── plugins.sbt ├── .VSCodeCounter ├── 2023-02-01_21-02-12 │ ├── diff.csv │ ├── diff-details.md │ ├── diff.md │ ├── results.md │ ├── diff.txt │ ├── details.md │ ├── results.csv │ └── results.json ├── 2023-02-02_16-39-50 │ ├── diff.md │ ├── results.md │ ├── diff.csv │ ├── diff-details.md │ ├── details.md │ ├── diff.txt │ └── results.csv ├── 2023-02-02_13-59-40 │ ├── diff.md │ ├── results.md │ ├── diff.csv │ ├── diff-details.md │ ├── details.md │ ├── diff.txt │ └── results.csv ├── 2023-01-31_16-38-39 │ ├── results.md │ ├── diff.md │ ├── details.md │ ├── results.csv │ └── results.json └── 2023-01-31_16-38-27 │ ├── results.md │ ├── diff.md │ ├── results.csv │ ├── details.md │ └── results.json ├── Ladder.assets ├── image-20230424133440805.png └── image-20230424133510727.png ├── csrc ├── devices.h ├── log.cpp ├── log.h ├── memory.h ├── memory.cpp ├── devices.cpp └── disasm.cc ├── genrtl ├── Full_Adder.v ├── front_end_control.v ├── Interrupt_Mask.v └── PC_Gen.v ├── src └── test │ └── scala │ └── ladder │ ├── cache │ ├── S011HD1P_dpi.scala │ ├── AxiLite.scala │ ├── data_array.scala │ ├── axi_arbiter.scala │ └── icache.scala │ ├── back_end │ ├── arch_regfile.scala │ ├── interrupt_mask.scala │ ├── regfile.scala │ ├── execute │ │ └── mul_div │ │ │ ├── booth.scala │ │ │ ├── mul.scala │ │ │ └── div.scala │ ├── rename │ │ ├── rename_table.scala │ │ └── rename.scala │ └── dispatch │ │ └── dispatch.scala │ ├── front_end │ ├── fetch_queue.scala │ ├── if2_if3.scala │ ├── if1_if2.scala │ ├── front_end_control.scala │ ├── pc_gen.scala │ ├── fetchres.scala │ ├── branch_presolve.scala │ └── front_end.scala │ ├── muldiv_test.scala │ ├── dpic.scala │ ├── CPU_top.scala │ ├── ladder.scala │ ├── dpic-axi-ver.scala │ ├── consts.scala │ └── CPU_top_with_dpic.scala1 ├── README.md ├── .github └── workflows │ ├── test.yml │ └── template-cleanup.yml ├── vsrc ├── S011HD1P_X32Y2D128_BW.v └── dpi-funcs.v1 ├── Makefile └── verilogtestbench ├── top_tb.v ├── tb.v └── front_end_tb.v /project/build.properties: -------------------------------------------------------------------------------- 1 | sbt.version = 1.8.0 2 | -------------------------------------------------------------------------------- /project/plugins.sbt: -------------------------------------------------------------------------------- 1 | logLevel := Level.Warn 2 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/diff.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "", "comment", "blank", "total" 2 | "Total", "-", , 0, 0, 0 -------------------------------------------------------------------------------- /Ladder.assets/image-20230424133440805.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Boucii/RISC-V-Ladder/HEAD/Ladder.assets/image-20230424133440805.png -------------------------------------------------------------------------------- /Ladder.assets/image-20230424133510727.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Boucii/RISC-V-Ladder/HEAD/Ladder.assets/image-20230424133510727.png -------------------------------------------------------------------------------- /csrc/devices.h: -------------------------------------------------------------------------------- 1 | void kbd_update(); 2 | uint32_t key_dequeue(); 3 | void init_keymap(); 4 | void init_screen(); 5 | void update_screen(); 6 | -------------------------------------------------------------------------------- /csrc/log.cpp: -------------------------------------------------------------------------------- 1 | #include "log.h" 2 | ofstream fout("./build/npc_log.txt",ios::out|ios::trunc); 3 | 4 | void LogInit(){ 5 | assert(fout.is_open()&&fout); 6 | } 7 | void Log(string content){ 8 | fout< 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | using namespace std; 10 | void Log(string content); 11 | void LogInit(); 12 | -------------------------------------------------------------------------------- /csrc/memory.h: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | int mem_init(); 6 | uint64_t pmem_read(int addr); 7 | int pmem_write(uint64_t content,uint64_t addr,uint32_t len); 8 | int free_memory(); 9 | long load_img(char ** argv); 10 | -------------------------------------------------------------------------------- /genrtl/Full_Adder.v: -------------------------------------------------------------------------------- 1 | module Full_Adder( 2 | input io_i_a, 3 | input io_i_b, 4 | input io_i_cin, 5 | output io_o_s, 6 | output io_o_cout 7 | ); 8 | assign io_o_s = io_i_a ^ io_i_b ^ io_i_cin; // @[wallace_tree.scala 23:31] 9 | assign io_o_cout = io_i_a & io_i_b | io_i_a & io_i_cin | io_i_b & io_i_cin; // @[wallace_tree.scala 24:58] 10 | endmodule 11 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/diff-details.md: -------------------------------------------------------------------------------- 1 | # Diff Details 2 | 3 | Date : 2023-02-01 21:02:12 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details 10 | 11 | ## Files 12 | | filename | language | code | comment | blank | total | 13 | | :--- | :--- | ---: | ---: | ---: | ---: | 14 | 15 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details -------------------------------------------------------------------------------- /src/test/scala/ladder/cache/S011HD1P_dpi.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class S011HD1P_X32Y2D128_BW extends BlackBox{ 11 | val io = IO(new Bundle{ 12 | val Q = Output(UInt(128.W)) 13 | val CLK = Input(Clock()) 14 | val CEN = Input(Bool()) 15 | val WEN = Input(Bool()) 16 | val BWEN = Input(UInt(128.W)) 17 | val A = Input(UInt(6.W)) 18 | val D = Input(UInt(128.W)) 19 | }) 20 | } 21 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/diff.md: -------------------------------------------------------------------------------- 1 | # Diff Summary 2 | 3 | Date : 2023-02-01 21:02:12 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | 15 | ## Directories 16 | | path | files | code | comment | blank | total | 17 | | :--- | ---: | ---: | ---: | ---: | ---: | 18 | 19 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # RISC-V Ladder 2 | 3 | 好风凭借力,送我上青云 4 | 5 | 6 | 7 | RISC-V Ladder is an dual-issued, 10 staged, out-of-order riscv64 core in chisel programming lanuage. 8 | 9 | ![image-20230424133510727](./Ladder.assets/image-20230424133510727.png) 10 | 11 | Sbt is used to build the chisel files. Verilator is used to run simulations. 12 | 13 | the basic file structure is as following: 14 | 15 | ``` 16 | -csrc //verilator csrs 17 | -genrtl //chisel generated verilog files 18 | -project //sbt configs 19 | -src //chisel source code 20 | -verilogtestbench //some testbenches 21 | -vsrc //vsrcs for dpi-c function 22 | ``` 23 | 24 | RISC-V Ladder is finished under [YSYX project]([一生一芯计划 (oscc.cc)](https://ysyx.oscc.cc/)). -------------------------------------------------------------------------------- /.github/workflows/test.yml: -------------------------------------------------------------------------------- 1 | name: Continuous Integration 2 | 3 | on: [push, pull_request] 4 | 5 | jobs: 6 | ci: 7 | name: ci 8 | runs-on: ubuntu-latest 9 | steps: 10 | - name: Checkout 11 | uses: actions/checkout@v2 12 | - name: Cleanup 13 | run: sed -i "s/%NAME%/test/g" build.sc 14 | - name: Setup Scala 15 | uses: olafurpg/setup-scala@v10 16 | with: 17 | java-version: adopt@1.8 18 | - name: Setup Mill 19 | uses: jodersky/setup-mill@v0.2.3 20 | with: 21 | mill-version: 0.9.7 22 | - name: Cache Scala 23 | uses: coursier/cache-action@v5 24 | - name: SBT Test 25 | run: sbt test 26 | - name: mill Test 27 | run: mill _.test 28 | -------------------------------------------------------------------------------- /vsrc/S011HD1P_X32Y2D128_BW.v: -------------------------------------------------------------------------------- 1 | module S011HD1P_X32Y2D128_BW( 2 | Q, CLK, CEN, WEN, BWEN, A, D 3 | ); 4 | parameter Bits = 128; 5 | parameter Word_Depth = 64; 6 | parameter Add_Width = 6; 7 | parameter Wen_Width = 128; 8 | 9 | output reg [Bits-1:0] Q; 10 | input CLK; 11 | input CEN; 12 | input WEN; 13 | input [Wen_Width-1:0] BWEN; 14 | input [Add_Width-1:0] A; 15 | input [Bits-1:0] D; 16 | 17 | wire cen = ~CEN; 18 | wire wen = ~WEN; 19 | wire [Wen_Width-1:0] bwen = ~BWEN; 20 | 21 | reg [Bits-1:0] ram [0:Word_Depth-1]; 22 | always @(posedge CLK) begin 23 | if(cen && wen) begin 24 | ram[A] <= (D & bwen) | (ram[A] & ~bwen); 25 | end 26 | Q <= cen && !wen ? ram[A] : {4{$random}}; 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/diff.md: -------------------------------------------------------------------------------- 1 | # Diff Summary 2 | 3 | Date : 2023-02-02 16:39:50 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 10 files, 359 codes, 0 comments, 0 blanks, all 359 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 9 | 222 | 0 | 0 | 222 | 15 | | JSON | 1 | 137 | 0 | 0 | 137 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 10 | 359 | 0 | 0 | 359 | 21 | 22 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/diff.md: -------------------------------------------------------------------------------- 1 | # Diff Summary 2 | 3 | Date : 2023-02-02 13:59:40 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 10 files, 17700 codes, 1 comments, 2 blanks, all 17703 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | JSON | 1 | 17,570 | 0 | 0 | 17,570 | 15 | | Verilog | 9 | 130 | 1 | 2 | 133 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 10 | 17,700 | 1 | 2 | 17,703 | 21 | 22 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-39/results.md: -------------------------------------------------------------------------------- 1 | # Summary 2 | 3 | Date : 2023-01-31 16:38:39 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 37 files, 148776 codes, 23 comments, 35 blanks, all 148834 lines 8 | 9 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 35 | 131,155 | 23 | 35 | 131,213 | 15 | | JSON | 2 | 17,621 | 0 | 0 | 17,621 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 37 | 148,776 | 23 | 35 | 148,834 | 21 | 22 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/results.md: -------------------------------------------------------------------------------- 1 | # Summary 2 | 3 | Date : 2023-02-01 21:02:12 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 37 files, 148776 codes, 23 comments, 35 blanks, all 148834 lines 8 | 9 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 35 | 131,155 | 23 | 35 | 131,213 | 15 | | JSON | 2 | 17,621 | 0 | 0 | 17,621 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 37 | 148,776 | 23 | 35 | 148,834 | 21 | 22 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/results.md: -------------------------------------------------------------------------------- 1 | # Summary 2 | 3 | Date : 2023-02-02 13:59:40 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 40 files, 166476 codes, 24 comments, 37 blanks, all 166537 lines 8 | 9 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 37 | 131,285 | 24 | 37 | 131,346 | 15 | | JSON | 3 | 35,191 | 0 | 0 | 35,191 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 40 | 166,476 | 24 | 37 | 166,537 | 21 | 22 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/results.md: -------------------------------------------------------------------------------- 1 | # Summary 2 | 3 | Date : 2023-02-02 16:39:50 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 40 files, 166835 codes, 24 comments, 37 blanks, all 166896 lines 8 | 9 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 37 | 131,507 | 24 | 37 | 131,568 | 15 | | JSON | 3 | 35,328 | 0 | 0 | 35,328 | 16 | 17 | ## Directories 18 | | path | files | code | comment | blank | total | 19 | | :--- | ---: | ---: | ---: | ---: | ---: | 20 | | . | 40 | 166,835 | 24 | 37 | 166,896 | 21 | 22 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/arch_regfile.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Arch_RegFile extends Module { 12 | val io = IO(new Bundle{ 13 | val i_pregs = Input(Vec(128,UInt(64.W))) 14 | val i_rename_table = Input(Vec(32,UInt(7.W))) 15 | val i_csrs = Input(Vec(4,UInt(64.W))) 16 | 17 | val o_arch_regs = Output(Vec(32,UInt(64.W))) 18 | val o_csr_regs = Output(Vec(4,UInt(64.W))) 19 | }) 20 | for(i <- 0 until 32){ 21 | io.o_arch_regs(i) := io.i_pregs(io.i_rename_table(i)) 22 | } 23 | for(i<-0 until 4){ 24 | io.o_csr_regs(i) := io.i_csrs(i) 25 | } 26 | } 27 | -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/fetch_queue.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Fetch_Queue extends Module 12 | { 13 | val io = IO(new Bundle { 14 | val in = Flipped(Decoupled(new fetch_pack())) 15 | val out = Decoupled(new fetch_pack()) 16 | val full = Output(Bool()) 17 | val empty = Output(Bool()) 18 | val i_flush = Input(Bool()) 19 | }) 20 | val queue = Module(new Queue(new fetch_pack(), entries=64)) 21 | queue.reset := reset.asBool()||io.i_flush 22 | queue.io.enq <> io.in 23 | io.out <> queue.io.deq 24 | 25 | io.out.bits := queue.io.deq.bits 26 | io.out.valid := queue.io.deq.valid && (!queue.reset.asBool()) 27 | queue.io.deq.ready := io.out.ready 28 | 29 | io.full := !queue.io.enq.ready 30 | io.empty := !queue.io.deq.valid 31 | } -------------------------------------------------------------------------------- /genrtl/front_end_control.v: -------------------------------------------------------------------------------- 1 | module front_end_control( 2 | input io_i_pc_redirect_valid, 3 | input io_i_icache_data_valid, 4 | input io_i_icache_addr_ready, 5 | input io_i_branch_resolve_pack_valid, 6 | input io_i_branch_resolve_pack_mispred, 7 | input io_i_branch_presolve_pack_valid, 8 | input io_i_branch_presolve_pack_taken, 9 | input io_i_fetch_queue_full, 10 | output io_o_stage1_stall, 11 | output io_o_stage2_stall, 12 | output io_o_stage1_flush, 13 | output io_o_stage2_flush, 14 | output io_o_fetch_queue_flush 15 | ); 16 | assign io_o_stage1_stall = (~io_i_icache_addr_ready | io_o_stage2_stall) & ~io_o_stage1_flush; // @[front_end_control.scala 36:72] 17 | assign io_o_stage2_stall = (io_i_fetch_queue_full | ~io_i_icache_data_valid) & ~io_o_stage2_flush; // @[front_end_control.scala 35:78] 18 | assign io_o_stage1_flush = io_o_stage2_flush | io_i_branch_presolve_pack_valid & io_i_branch_presolve_pack_taken; // @[front_end_control.scala 33:43] 19 | assign io_o_stage2_flush = io_o_fetch_queue_flush; // @[front_end_control.scala 32:22] 20 | assign io_o_fetch_queue_flush = io_i_pc_redirect_valid | io_i_branch_resolve_pack_valid & 21 | io_i_branch_resolve_pack_mispred; // @[front_end_control.scala 31:53] 22 | endmodule 23 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/diff.txt: -------------------------------------------------------------------------------- 1 | Date : 2023-02-01 21:02:12 2 | Directory : d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl 3 | Total : 0 files, 0 codes, 0 comments, 0 blanks, all 0 lines 4 | 5 | Languages 6 | +----------+------------+------------+------------+------------+------------+ 7 | | language | files | code | comment | blank | total | 8 | +----------+------------+------------+------------+------------+------------+ 9 | +----------+------------+------------+------------+------------+------------+ 10 | 11 | Directories 12 | +------+------------+------------+------------+------------+------------+ 13 | | path | files | code | comment | blank | total | 14 | +------+------------+------------+------------+------------+------------+ 15 | +------+------------+------------+------------+------------+------------+ 16 | 17 | Files 18 | +----------+----------+------------+------------+------------+------------+ 19 | | filename | language | code | comment | blank | total | 20 | +----------+----------+------------+------------+------------+------------+ 21 | | Total | | 0 | 0 | 0 | 0 | 22 | +----------+----------+------------+------------+------------+------------+ -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/diff.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", 5, 0, 0, 0, 5 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 22, 0, 0, 0, 22 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v", "Verilog", 4, 0, 0, 0, 4 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 8, 0, 0, 0, 8 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", 24, 0, 0, 0, 24 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", 22, 0, 0, 0, 22 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 2, 0, 0, 0, 2 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json", "JSON", 0, 137, 0, 0, 137 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v", "Verilog", 33, 0, 0, 0, 33 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", 102, 0, 0, 0, 102 12 | "Total", "-", 222, 137, 0, 0, 359 -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/diff-details.md: -------------------------------------------------------------------------------- 1 | # Diff Details 2 | 3 | Date : 2023-02-02 16:39:50 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 10 files, 359 codes, 0 comments, 0 blanks, all 359 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details 10 | 11 | ## Files 12 | | filename | language | code | comment | blank | total | 13 | | :--- | :--- | ---: | ---: | ---: | ---: | 14 | | [genrtl/BRU.v](/genrtl/BRU.v) | Verilog | 5 | 0 | 0 | 5 | 15 | | [genrtl/Back_End_With_Decode.v](/genrtl/Back_End_With_Decode.v) | Verilog | 22 | 0 | 0 | 22 | 16 | | [genrtl/Decoder.v](/genrtl/Decoder.v) | Verilog | 4 | 0 | 0 | 4 | 17 | | [genrtl/Execute.v](/genrtl/Execute.v) | Verilog | 8 | 0 | 0 | 8 | 18 | | [genrtl/Fetch_Queue.v](/genrtl/Fetch_Queue.v) | Verilog | 24 | 0 | 0 | 24 | 19 | | [genrtl/Front_End.v](/genrtl/Front_End.v) | Verilog | 22 | 0 | 0 | 22 | 20 | | [genrtl/LSU.v](/genrtl/LSU.v) | Verilog | 2 | 0 | 0 | 2 | 21 | | [genrtl/Ladder.anno.json](/genrtl/Ladder.anno.json) | JSON | 137 | 0 | 0 | 137 | 22 | | [genrtl/Ladder.v](/genrtl/Ladder.v) | Verilog | 33 | 0 | 0 | 33 | 23 | | [genrtl/Queue.v](/genrtl/Queue.v) | Verilog | 102 | 0 | 0 | 102 | 24 | 25 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/diff.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", -2, 0, 0, 0, -2 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 16, 0, 0, 0, 16 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 4, 0, 0, 0, 4 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", -24, 0, 0, 0, -24 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", -26, 0, 0, 0, -26 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Interrupt_Mask.v", "Verilog", 79, 0, 1, 1, 81 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 18, 0, 0, 0, 18 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json", "JSON", 0, 17570, 0, 0, 17570 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v", "Verilog", 167, 0, 0, 1, 168 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", -102, 0, 0, 0, -102 12 | "Total", "-", 130, 17570, 1, 2, 17703 -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/diff-details.md: -------------------------------------------------------------------------------- 1 | # Diff Details 2 | 3 | Date : 2023-02-02 13:59:40 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 10 files, 17700 codes, 1 comments, 2 blanks, all 17703 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details 10 | 11 | ## Files 12 | | filename | language | code | comment | blank | total | 13 | | :--- | :--- | ---: | ---: | ---: | ---: | 14 | | [genrtl/BRU.v](/genrtl/BRU.v) | Verilog | -2 | 0 | 0 | -2 | 15 | | [genrtl/Back_End_With_Decode.v](/genrtl/Back_End_With_Decode.v) | Verilog | 16 | 0 | 0 | 16 | 16 | | [genrtl/Execute.v](/genrtl/Execute.v) | Verilog | 4 | 0 | 0 | 4 | 17 | | [genrtl/Fetch_Queue.v](/genrtl/Fetch_Queue.v) | Verilog | -24 | 0 | 0 | -24 | 18 | | [genrtl/Front_End.v](/genrtl/Front_End.v) | Verilog | -26 | 0 | 0 | -26 | 19 | | [genrtl/Interrupt_Mask.v](/genrtl/Interrupt_Mask.v) | Verilog | 79 | 1 | 1 | 81 | 20 | | [genrtl/LSU.v](/genrtl/LSU.v) | Verilog | 18 | 0 | 0 | 18 | 21 | | [genrtl/Ladder.anno.json](/genrtl/Ladder.anno.json) | JSON | 17,570 | 0 | 0 | 17,570 | 22 | | [genrtl/Ladder.v](/genrtl/Ladder.v) | Verilog | 167 | 0 | 1 | 168 | 23 | | [genrtl/Queue.v](/genrtl/Queue.v) | Verilog | -102 | 0 | 0 | -102 | 24 | 25 | [Summary](results.md) / [Details](details.md) / [Diff Summary](diff.md) / Diff Details -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-27/results.md: -------------------------------------------------------------------------------- 1 | # Summary 2 | 3 | Date : 2023-01-31 16:38:27 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\src\\test\\scala\\ladder 6 | 7 | Total : 33 files, 2691 codes, 493 comments, 489 blanks, all 3673 lines 8 | 9 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Scala | 33 | 2,691 | 493 | 489 | 3,673 | 15 | 16 | ## Directories 17 | | path | files | code | comment | blank | total | 18 | | :--- | ---: | ---: | ---: | ---: | ---: | 19 | | . | 33 | 2,691 | 493 | 489 | 3,673 | 20 | | . (Files) | 6 | 508 | 200 | 71 | 779 | 21 | | back_end | 18 | 1,808 | 253 | 355 | 2,416 | 22 | | back_end (Files) | 4 | 271 | 18 | 33 | 322 | 23 | | back_end\\commit | 1 | 161 | 40 | 31 | 232 | 24 | | back_end\\dispatch | 1 | 38 | 8 | 6 | 52 | 25 | | back_end\\execute | 6 | 820 | 86 | 161 | 1,067 | 26 | | back_end\\execute (Files) | 2 | 463 | 63 | 101 | 627 | 27 | | back_end\\execute\\mul_div | 4 | 357 | 23 | 60 | 440 | 28 | | back_end\\issue | 2 | 246 | 41 | 61 | 348 | 29 | | back_end\\rename | 4 | 272 | 60 | 63 | 395 | 30 | | front_end | 9 | 375 | 40 | 63 | 478 | 31 | 32 | Summary / [Details](details.md) / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/if2_if3.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | import chisel3._ 3 | import chisel3.ExplicitCompileOptions.Strict 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class IF2_IF3 extends Module 11 | { 12 | val io=IO(new Bundle{ 13 | val i_stall = Input(Bool()) 14 | val i_flush = Input(Bool()) 15 | val i_fetch_valid = Input(Bool()) 16 | val o_fetch_valid = Output(Bool()) 17 | 18 | val i_pc = Input(UInt(64.W)) 19 | val o_pc = Output(UInt(64.W)) 20 | 21 | val i_branch_predict_pack = Input(new branch_predict_pack()) 22 | val o_branch_predict_pack = Output(new branch_predict_pack()) 23 | }) 24 | val pc = RegInit(0.U(64.W)); 25 | pc := Mux(io.i_flush, 0.U, Mux(io.i_stall, pc, io.i_pc)) 26 | io.o_pc := pc; 27 | 28 | val branch_predict_pack = RegInit(0.U.asTypeOf(new branch_predict_pack())); 29 | branch_predict_pack := Mux(io.i_flush, 0.U.asTypeOf(new branch_predict_pack()), Mux(io.i_stall, branch_predict_pack, io.i_branch_predict_pack)) 30 | branch_predict_pack.valid := Mux(io.i_flush, false.B, Mux(io.i_stall, branch_predict_pack.valid, io.i_branch_predict_pack.valid)) 31 | io.o_branch_predict_pack :=branch_predict_pack 32 | 33 | val fetch_valid = RegInit(false.B) 34 | fetch_valid := Mux(io.i_flush, false.B, Mux(io.i_stall, fetch_valid, io.i_fetch_valid)) 35 | io.o_fetch_valid := fetch_valid 36 | } 37 | -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/interrupt_mask.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.BitPat 9 | import chisel3.util.experimental.decode._ 10 | import chisel3.experimental.BundleLiterals._ 11 | 12 | //this module is used in the following scenario: 13 | //when executing a store in lsu, and the memory returns in more than one cycle( weather it's for cache miss or anything else) 14 | //if an interrupt occurs, due to the axi bus transactions can't br canceled, we must finish the store instruction and then deal 15 | //with the interrupt. When the store is commited(commit_ptr changed), we can go on unmask the interrupt signal. 16 | class Interrupt_Mask extends Module with consts{ 17 | val io = IO(new Bundle{ 18 | val i_lsu_uop_valid = Input(Bool()) 19 | val i_rob_idx = Input(UInt(rob_idx_len.W)) 20 | val i_lsu_uop_rob_idx = Input(UInt(rob_idx_len.W)) 21 | 22 | val i_interrupt = Input(Bool()) 23 | val o_interrupt_with_mask = Output(Bool()) 24 | }) 25 | val mask = RegInit(false.B) 26 | val next_mask = Wire(Bool()) 27 | mask := next_mask 28 | val cmt_ptr = RegInit(0.U(rob_idx_len.W)) 29 | next_mask := mask 30 | when(io.i_lsu_uop_valid && io.i_lsu_uop_rob_idx===io.i_rob_idx){ 31 | next_mask := true.B 32 | cmt_ptr := io.i_rob_idx 33 | } 34 | when(mask===true.B && io.i_rob_idx =/= cmt_ptr){ 35 | next_mask := false.B 36 | } 37 | io.o_interrupt_with_mask := Mux(next_mask,false.B,io.i_interrupt) 38 | } 39 | -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/if1_if2.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | import chisel3._ 3 | import chisel3.ExplicitCompileOptions.Strict 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class IF1_IF2 extends Module 11 | { 12 | val io=IO(new Bundle{ 13 | val i_stall = Input(Bool()) 14 | val i_flush = Input(Bool()) 15 | val o_fetch_valid = Output(Bool()) 16 | 17 | val i_pc = Input(UInt(64.W)) 18 | val o_pc = Output(UInt(64.W)) 19 | 20 | val i_branch_predict_pack = Input(new branch_predict_pack()) 21 | val o_branch_predict_pack = Output(new branch_predict_pack()) 22 | 23 | }) 24 | val pc = RegInit(0.U(64.W)); 25 | pc := Mux(io.i_flush, 0.U, Mux(io.i_stall, pc, io.i_pc)) 26 | //io.o_pc := pc; 27 | io.o_pc := Mux(io.i_flush||io.i_stall, 0.U ,pc) 28 | 29 | val branch_predict_pack = RegInit(0.U.asTypeOf(new branch_predict_pack())); 30 | branch_predict_pack := Mux(io.i_flush, 0.U.asTypeOf(new branch_predict_pack()), Mux(io.i_stall, branch_predict_pack, io.i_branch_predict_pack)) 31 | branch_predict_pack.valid := Mux(io.i_flush, false.B, Mux(io.i_stall, branch_predict_pack.valid, io.i_branch_predict_pack.valid)) 32 | io.o_branch_predict_pack :=branch_predict_pack 33 | io.o_branch_predict_pack.valid := Mux(io.i_flush||io.i_stall, false.B, branch_predict_pack.valid) 34 | 35 | val fetch_valid = RegInit(false.B) 36 | fetch_valid := Mux(io.i_flush, false.B, Mux(io.i_stall, fetch_valid, true.B)) 37 | io.o_fetch_valid := Mux(io.i_flush||io.i_stall, false.B ,fetch_valid) 38 | } 39 | -------------------------------------------------------------------------------- /src/test/scala/ladder/muldiv_test.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.BitPat 9 | import chisel3.util.experimental.decode._ 10 | import chisel3.experimental.BundleLiterals._ 11 | 12 | class divtest extends AnyFreeSpec with ChiselScalatestTester { 13 | "Gcd should calculate proper greatest common denominator" in { 14 | test(new Execute()).withAnnotations(Seq( WriteVcdAnnotation )) { c => 15 | //initial input: 16 | 17 | c.io.i_issue_res_packs(0).valid.poke(false.B) 18 | c.io.i_issue_res_packs(0).rob_idx.poke(0.U) 19 | c.io.i_issue_res_packs(1).valid.poke(false.B) 20 | c.io.i_exception.poke(false.B) 21 | c.io.i_rollback_valid.poke(false.B) 22 | //initial combinational logic output: 23 | 24 | c.io.o_ex_res_packs(0).valid.expect(false.B) 25 | c.io.o_ex_res_packs(0).uop.dst_value.expect(0.U) 26 | c.io.o_ex_res_packs(1).valid.expect(false.B) 27 | c.io.o_ex_res_packs(1).uop.dst_value.expect(0.U) 28 | c.io.o_branch_resolve_pack.valid.expect(false.B) 29 | 30 | 31 | //clock=0 32 | c.clock.step(1) 33 | c.io.i_issue_res_packs(0).valid.poke(true.B) 34 | c.io.i_issue_res_packs(0).func_code.poke(16.U) 35 | c.io.i_issue_res_packs(0).src1_value.poke(9.U) 36 | c.io.i_issue_res_packs(0).src2_value.poke(4.U) 37 | c.io.i_issue_res_packs(0).alu_sel.poke(0.U) 38 | c.io.i_issue_res_packs(0).inst.poke(0x02114233) 39 | c.io.i_issue_res_packs(1).valid.poke(false.B) 40 | 41 | 42 | //clock=1 43 | c.clock.step(1) 44 | 45 | 46 | //clock=2.0 47 | for(i <- 0 until 70){ 48 | c.clock.step(1) 49 | } 50 | 51 | }} 52 | } 53 | //test -- -DwriteVcd=1 54 | //test -- -DwriteVcd=1 --debug -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-27/diff.md: -------------------------------------------------------------------------------- 1 | # Diff Summary 2 | 3 | Date : 2023-01-31 16:38:27 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\src\\test\\scala\\ladder 6 | 7 | Total : 70 files, -146078 codes, 470 comments, 454 blanks, all -145154 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Scala | 33 | 2,691 | 493 | 489 | 3,673 | 15 | | JSON | 2 | -17,621 | 0 | 0 | -17,621 | 16 | | Verilog | 35 | -131,148 | -23 | -35 | -131,206 | 17 | 18 | ## Directories 19 | | path | files | code | comment | blank | total | 20 | | :--- | ---: | ---: | ---: | ---: | ---: | 21 | | . | 70 | -146,078 | 470 | 454 | -145,154 | 22 | | . (Files) | 6 | 508 | 200 | 71 | 779 | 23 | | .. | 37 | -148,769 | -23 | -35 | -148,827 | 24 | | ..\\.. | 37 | -148,769 | -23 | -35 | -148,827 | 25 | | ..\\..\\.. | 37 | -148,769 | -23 | -35 | -148,827 | 26 | | ..\\..\\..\\.. | 37 | -148,769 | -23 | -35 | -148,827 | 27 | | ..\\..\\..\\..\\genrtl | 37 | -148,769 | -23 | -35 | -148,827 | 28 | | back_end | 18 | 1,808 | 253 | 355 | 2,416 | 29 | | back_end (Files) | 4 | 271 | 18 | 33 | 322 | 30 | | back_end\\commit | 1 | 161 | 40 | 31 | 232 | 31 | | back_end\\dispatch | 1 | 38 | 8 | 6 | 52 | 32 | | back_end\\execute | 6 | 820 | 86 | 161 | 1,067 | 33 | | back_end\\execute (Files) | 2 | 463 | 63 | 101 | 627 | 34 | | back_end\\execute\\mul_div | 4 | 357 | 23 | 60 | 440 | 35 | | back_end\\issue | 2 | 246 | 41 | 61 | 348 | 36 | | back_end\\rename | 4 | 272 | 60 | 63 | 395 | 37 | | front_end | 9 | 375 | 40 | 63 | 478 | 38 | 39 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/front_end_control.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class front_end_control extends Module 12 | { 13 | val io =IO(new Bundle { 14 | val i_pc_redirect_valid = Input(new Bool()) 15 | val i_icache_data_valid = Input(Bool()) 16 | val i_icache_addr_ready = Input(Bool()) 17 | //val i_cache_fetch_valid = Input(Bool())//aka.valid fetch 18 | val i_branch_resolve_pack = Input(new branch_resolve_pack()) 19 | val i_branch_presolve_pack = Input(new branch_presolve_pack()) 20 | val i_fetch_queue_full = Input(Bool()) 21 | 22 | val o_stage1_stall = Output(Bool()) 23 | val o_stage2_stall = Output(Bool()) 24 | //val o_stage3_stall = Output(Bool())//this is actually stage3 fetch invalid 25 | 26 | val o_stage1_flush = Output(Bool()) 27 | val o_stage2_flush = Output(Bool()) 28 | //val o_stage3_flush = Output(Bool())//means flush everything inside fetchqueue 29 | val o_fetch_queue_flush = Output(Bool()) 30 | }) 31 | io.o_fetch_queue_flush := io.i_pc_redirect_valid || (io.i_branch_resolve_pack.valid && io.i_branch_resolve_pack.mispred) 32 | io.o_stage2_flush := io.o_fetch_queue_flush 33 | io.o_stage1_flush := io.o_stage2_flush || (io.i_branch_presolve_pack.valid && io.i_branch_presolve_pack.taken) 34 | 35 | io.o_stage2_stall := (io.i_fetch_queue_full || (!io.i_icache_data_valid)) &&(!io.o_stage2_flush)///?? 36 | io.o_stage1_stall := (!io.i_icache_addr_ready || io.o_stage2_stall) && (!io.o_stage1_flush) 37 | } 38 | -------------------------------------------------------------------------------- /.github/workflows/template-cleanup.yml: -------------------------------------------------------------------------------- 1 | # Workflow to cleanup projects created from this template 2 | # Adapted from workflow of the same name in https://github.com/JetBrains/intellij-platform-plugin-template 3 | # SPDX-License-Identifier: Apache-2.0 4 | 5 | name: Template Cleanup 6 | on: 7 | push: 8 | branches: [main] 9 | 10 | jobs: 11 | # Triggered on first push to repos created from the template 12 | template-cleanup: 13 | name: Template Cleanup 14 | runs-on: ubuntu-latest 15 | if: github.event.repository.name != 'chisel-template' 16 | steps: 17 | 18 | - name: Checkout 19 | uses: actions/checkout@v2 20 | 21 | - name: Cleanup 22 | run: | 23 | export LC_CTYPE=C 24 | export LANG=C 25 | 26 | # Prepare variables 27 | NAME="${GITHUB_REPOSITORY##*/}" 28 | ORG="$GITHUB_REPOSITORY_OWNER" 29 | SAFE_ORG=$(echo $ORG | sed 's/[^a-zA-Z0-9]//g' | tr '[:upper:]' '[:lower:]') 30 | GROUP="com.github.$SAFE_ORG" 31 | 32 | # Replace placeholders 33 | sed -i "s/%NAME%/$NAME/g" build.sbt build.sc README.md 34 | sed -i "s/%REPOSITORY%/${GITHUB_REPOSITORY/\//\\/}/g" README.md 35 | sed -i "s/%ORGANIZATION%/$GROUP/g" build.sbt 36 | 37 | # Remove lines marked with #REMOVE-ON-CLEANUP# 38 | sed -i '/#REMOVE-ON-CLEANUP#/d' README.md 39 | 40 | rm -rf \ 41 | .github/workflows/template-cleanup.yml \ 42 | LICENSE 43 | 44 | - name: Commit 45 | run: | 46 | git config --local user.email "action@github.com" 47 | git config --local user.name "GitHub Action" 48 | git add . 49 | git commit -m "Template cleanup" 50 | 51 | - name: Push changes 52 | uses: ad-m/github-push-action@v0.6.0 53 | with: 54 | branch: main 55 | github_token: ${{ secrets.GITHUB_TOKEN }} 56 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | BUILD_DIR = ./build 2 | 3 | VSRCS = $(shell find $(abspath ./genrtl) -name "*.v") $(shell find $(abspath ./vsrc) -name "*.v") 4 | CSRCS = $(shell find $(abspath ./csrc) -name "*.c" -or -name "*.cc" -or -name "*.cpp") 5 | 6 | CXXFLAGS += $(shell llvm-config-14 --cxxflags) 7 | CXXFLAGS += -g 8 | CXXFLAGS += -O3 9 | CXXFLAGS += -fsanitize=address 10 | CXXFLAGS += -DVL_THREADED 11 | 12 | CXXFLAGS += -L$(NEMU_HOME)/build/ 13 | CXXFLAGS += -lriscv64-nemu-interpreter-so 14 | 15 | LDFLAGS += -ldl 16 | LDFLAGS += $(shell llvm-config-14 --ldflags) 17 | LDFLAGS += $(shell llvm-config-14 --libs all) 18 | LDFLAGS +=-fsanitize=address 19 | LDFLAGS +=-L$(NEMU_HOME)/build/ 20 | LDFLAGS += -lSDL2 21 | 22 | VERILATORFLAGS += -O3 --x-assign fast --x-initial fast --noassert --inline-mult 50000 23 | VERILATORFLAGS += --threads 2 -Wno-UNOPTTHREADS 24 | #--threads-dpi none 25 | #--trace-depth 3 --instr-count-dpi 300 26 | #VERILATORFLAGS += -Wwarn-WIDTH 27 | 28 | verilog: 29 | $(call git_commit, "generate verilog") 30 | sbt "test:runMain Ladder.GenVerilog " 31 | #--Wall --Werror" #-Werror=silent-truncation 32 | #sbt "Test/runMain Ladder.Genverilog" 33 | make sim 34 | 35 | genwave: 36 | verilator --cc --exe --trace --build -CFLAGS -g -Isim/ $(CSRCS) $(VSRCS) 37 | 38 | sim: 39 | $(call git_commit, "sim RTL") # DO NOT REMOVE THIS LINE!!! 40 | #verilator $(VERILATORFLAGS) --cc --exe -j 14 --build --top-module Ladder -CFLAGS "$(CXXFLAGS)" -LDFLAGS "$(LDFLAGS)" -I./genrtl/ $(VSRCS) $(CSRCS) --Mdir $(BUILD_DIR) 41 | verilator $(VERILATORFLAGS) --cc --exe -j 14 --build --trace --top-module Ladder -CFLAGS "$(CXXFLAGS)" -LDFLAGS "$(LDFLAGS)" -I./genrtl/ $(VSRCS) $(CSRCS) --Mdir $(BUILD_DIR) 42 | 43 | wave: 44 | @echo $(IMAGE) 45 | ./build/VLadder $(IMAGE) 46 | #gtkwave wave.vcd 47 | 48 | debug: 49 | #@echo "Hello from npc" 50 | @echo $(IMAGE) 51 | gdb -tui --args ./build/VLadder $(IMAGE) 52 | 53 | gtk: 54 | gtkwave wave.vcd 55 | 56 | clean: 57 | rm -r build/ 58 | rm -r genrtl/ 59 | 60 | include ../Makefile 61 | .PHONY: verilog genwave sim wave debug gtk clean 62 | -------------------------------------------------------------------------------- /src/test/scala/ladder/dpic.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class dpic extends BlackBox{ 12 | val io = IO(new Bundle{ 13 | val clk = Input(Clock()) 14 | val stop = Input(Bool()) 15 | 16 | val data_valid = Output(Bool()) 17 | val data_ready = Input(Bool()) 18 | val addr_ready = Output(Bool()) 19 | val addr_valid = Input(Bool()) 20 | val Mwout = Input(Bool()) 21 | val Maddr = Input(UInt(64.W)) 22 | val Men = Input(Bool()) 23 | val Mlen = Input(UInt(32.W)) 24 | val MdataIn = Output(UInt(64.W)) 25 | val MdataOut = Input(UInt(64.W)) 26 | 27 | //regfile dpi 28 | val regs0 = Input(UInt(64.W)) 29 | val regs1 = Input(UInt(64.W)) 30 | val regs2 = Input(UInt(64.W)) 31 | val regs3 = Input(UInt(64.W)) 32 | val regs4 = Input(UInt(64.W)) 33 | val regs5 = Input(UInt(64.W)) 34 | val regs6 = Input(UInt(64.W)) 35 | val regs7 = Input(UInt(64.W)) 36 | val regs8 = Input(UInt(64.W)) 37 | val regs9 = Input(UInt(64.W)) 38 | val regs10 = Input(UInt(64.W)) 39 | val regs11 = Input(UInt(64.W)) 40 | val regs12 = Input(UInt(64.W)) 41 | val regs13 = Input(UInt(64.W)) 42 | val regs14 = Input(UInt(64.W)) 43 | val regs15 = Input(UInt(64.W)) 44 | val regs16 = Input(UInt(64.W)) 45 | val regs17 = Input(UInt(64.W)) 46 | val regs18 = Input(UInt(64.W)) 47 | val regs19 = Input(UInt(64.W)) 48 | val regs20 = Input(UInt(64.W)) 49 | val regs21 = Input(UInt(64.W)) 50 | val regs22 = Input(UInt(64.W)) 51 | val regs23 = Input(UInt(64.W)) 52 | val regs24 = Input(UInt(64.W)) 53 | val regs25 = Input(UInt(64.W)) 54 | val regs26 = Input(UInt(64.W)) 55 | val regs27 = Input(UInt(64.W)) 56 | val regs28 = Input(UInt(64.W)) 57 | val regs29 = Input(UInt(64.W)) 58 | val regs30 = Input(UInt(64.W)) 59 | val regs31 = Input(UInt(64.W)) 60 | }) 61 | } 62 | -------------------------------------------------------------------------------- /src/test/scala/ladder/cache/AxiLite.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | class AxiLiteAddr(val addrWidth: Int) extends Bundle { 7 | val addr = UInt(addrWidth.W) 8 | val prot = UInt(3.W) // optional, but included by vivado 9 | } 10 | 11 | object AxiLiteAddr { 12 | def apply(addrWidth: Int) = new AxiLiteAddr(addrWidth) 13 | } 14 | 15 | class AxiLiteWriteData(val dataWidth: Int) extends Bundle { 16 | //require(dataWidth == 32 || dataWidth == 64, "AxiLite `dataWidth` must be 32 or 64") 17 | val data = UInt(dataWidth.W) 18 | val strb = UInt((dataWidth / 8).W) 19 | } 20 | 21 | object AxiLiteWriteData { 22 | def apply(dataWidth: Int) = new AxiLiteWriteData(dataWidth) 23 | } 24 | 25 | class AxiLiteReadData(val dataWidth: Int) extends Bundle { 26 | //require(dataWidth == 32 || dataWidth == 64, "AxiLite `dataWidth` must be 32 or 64") 27 | val data = UInt(dataWidth.W) 28 | val resp = UInt(2.W) 29 | } 30 | 31 | object AxiLiteReadData { 32 | def apply(dataWidth: Int) = new AxiLiteReadData(dataWidth) 33 | } 34 | 35 | class AxiLiteSlave(val addrWidth: Int, val dataWidth: Int) extends Bundle { 36 | val readAddr = Flipped(Decoupled(AxiLiteAddr(addrWidth))) 37 | val readData = Decoupled(AxiLiteReadData(dataWidth)) 38 | 39 | val writeAddr = Flipped(Decoupled(AxiLiteAddr(addrWidth))) 40 | val writeData = Flipped(Decoupled(AxiLiteWriteData(dataWidth))) 41 | val writeResp = Decoupled(UInt(2.W)) 42 | } 43 | 44 | object AxiLiteSlave { 45 | def apply(addrWidth: Int, dataWidth: Int) = 46 | new AxiLiteSlave(addrWidth = addrWidth, dataWidth = dataWidth) 47 | } 48 | 49 | class AxiLiteMaster(val addrWidth: Int, val dataWidth: Int) extends Bundle { 50 | val readAddr = Decoupled(AxiLiteAddr(addrWidth)) 51 | val readData = Flipped(Decoupled(AxiLiteReadData(dataWidth))) 52 | 53 | val writeAddr = Decoupled(AxiLiteAddr(addrWidth)) 54 | val writeData = Decoupled(AxiLiteWriteData(dataWidth)) 55 | val writeResp = Flipped(Decoupled(UInt(2.W))) 56 | } 57 | 58 | object AxiLiteMaster { 59 | def apply(addrWidth: Int, dataWidth: Int) = 60 | new AxiLiteMaster(addrWidth = addrWidth, dataWidth = dataWidth) 61 | } 62 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-39/diff.md: -------------------------------------------------------------------------------- 1 | # Diff Summary 2 | 3 | Date : 2023-01-31 16:38:39 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\genrtl 6 | 7 | Total : 70 files, 146085 codes, -470 comments, -454 blanks, all 145161 lines 8 | 9 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) 10 | 11 | ## Languages 12 | | language | files | code | comment | blank | total | 13 | | :--- | ---: | ---: | ---: | ---: | ---: | 14 | | Verilog | 35 | 131,155 | 23 | 35 | 131,213 | 15 | | JSON | 2 | 17,621 | 0 | 0 | 17,621 | 16 | | Scala | 33 | -2,691 | -493 | -489 | -3,673 | 17 | 18 | ## Directories 19 | | path | files | code | comment | blank | total | 20 | | :--- | ---: | ---: | ---: | ---: | ---: | 21 | | . | 70 | 146,085 | -470 | -454 | 145,161 | 22 | | . (Files) | 37 | 148,776 | 23 | 35 | 148,834 | 23 | | .. | 33 | -2,691 | -493 | -489 | -3,673 | 24 | | ..\\src | 33 | -2,691 | -493 | -489 | -3,673 | 25 | | ..\\src\\test | 33 | -2,691 | -493 | -489 | -3,673 | 26 | | ..\\src\\test\\scala | 33 | -2,691 | -493 | -489 | -3,673 | 27 | | ..\\src\\test\\scala\\ladder | 33 | -2,691 | -493 | -489 | -3,673 | 28 | | ..\\src\\test\\scala\\ladder (Files) | 6 | -508 | -200 | -71 | -779 | 29 | | ..\\src\\test\\scala\\ladder\\back_end | 18 | -1,808 | -253 | -355 | -2,416 | 30 | | ..\\src\\test\\scala\\ladder\\back_end (Files) | 4 | -271 | -18 | -33 | -322 | 31 | | ..\\src\\test\\scala\\ladder\\back_end\\commit | 1 | -161 | -40 | -31 | -232 | 32 | | ..\\src\\test\\scala\\ladder\\back_end\\dispatch | 1 | -38 | -8 | -6 | -52 | 33 | | ..\\src\\test\\scala\\ladder\\back_end\\execute | 6 | -820 | -86 | -161 | -1,067 | 34 | | ..\\src\\test\\scala\\ladder\\back_end\\execute (Files) | 2 | -463 | -63 | -101 | -627 | 35 | | ..\\src\\test\\scala\\ladder\\back_end\\execute\\mul_div | 4 | -357 | -23 | -60 | -440 | 36 | | ..\\src\\test\\scala\\ladder\\back_end\\issue | 2 | -246 | -41 | -61 | -348 | 37 | | ..\\src\\test\\scala\\ladder\\back_end\\rename | 4 | -272 | -60 | -63 | -395 | 38 | | ..\\src\\test\\scala\\ladder\\front_end | 9 | -375 | -40 | -63 | -478 | 39 | 40 | [Summary](results.md) / [Details](details.md) / Diff Summary / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/regfile.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | //64bit regfile with 4 read ports, 2 write ports,with write to read bypass 12 | class RegFile extends Module { 13 | val io = IO(new Bundle { 14 | val i_raddr1 = Input(UInt(7.W)) 15 | val i_raddr2 = Input(UInt(7.W)) 16 | val i_raddr3 = Input(UInt(7.W)) 17 | val i_raddr4 = Input(UInt(7.W)) 18 | 19 | val o_rdata1 = Output(UInt(64.W)) 20 | val o_rdata2 = Output(UInt(64.W)) 21 | val o_rdata3 = Output(UInt(64.W)) 22 | val o_rdata4 = Output(UInt(64.W)) 23 | 24 | val i_waddr1 = Input(UInt(7.W)) 25 | val i_waddr2 = Input(UInt(7.W)) 26 | 27 | val i_wdata1 = Input(UInt(64.W)) 28 | val i_wdata2 = Input(UInt(64.W)) 29 | 30 | val i_wenable1 = Input(Bool()) 31 | val i_wenable2 = Input(Bool()) 32 | 33 | //for debug and dpi-c 34 | val o_pregs = Output(Vec(128,UInt(64.W))) 35 | }) 36 | 37 | val regfile = RegInit(VecInit(Seq.fill(128)(0.U(64.W)))) 38 | val debug_regs = Wire(Vec(128,UInt(64.W))) 39 | 40 | debug_regs := regfile 41 | dontTouch(debug_regs) 42 | io.o_pregs := regfile 43 | 44 | when(io.i_wenable1) { 45 | regfile(io.i_waddr1) := io.i_wdata1 46 | } 47 | 48 | when(io.i_wenable2) { 49 | regfile(io.i_waddr2) := io.i_wdata2 50 | } 51 | 52 | io.o_rdata1 := MuxCase(regfile(io.i_raddr1),Seq( 53 | (io.i_wenable1 && io.i_waddr1 === io.i_raddr1) -> io.i_wdata1, 54 | (io.i_wenable2 && io.i_waddr2 === io.i_raddr1) -> io.i_wdata2 55 | )) 56 | io.o_rdata2 := MuxCase(regfile(io.i_raddr2),Seq( 57 | (io.i_wenable1 && io.i_waddr1 === io.i_raddr2) -> io.i_wdata1, 58 | (io.i_wenable2 && io.i_waddr2 === io.i_raddr2) -> io.i_wdata2 59 | )) 60 | io.o_rdata3 := MuxCase(regfile(io.i_raddr3),Seq( 61 | (io.i_wenable1 && io.i_waddr1 === io.i_raddr3) -> io.i_wdata1, 62 | (io.i_wenable2 && io.i_waddr2 === io.i_raddr3) -> io.i_wdata2 63 | )) 64 | io.o_rdata4 := MuxCase(regfile(io.i_raddr4),Seq( 65 | (io.i_wenable1 && io.i_waddr1 === io.i_raddr4) -> io.i_wdata1, 66 | (io.i_wenable2 && io.i_waddr2 === io.i_raddr4) -> io.i_wdata2 67 | )) 68 | } -------------------------------------------------------------------------------- /src/test/scala/ladder/cache/data_array.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class Data_Array extends Module{ 11 | val io = IO(new Bundle{ 12 | val i_ren = Input(Bool()) 13 | val i_wen = Input(Bool()) 14 | val i_wstrb = Input(UInt(16.W)) 15 | val i_addr = Input(UInt(7.W)) 16 | val i_wdata = Input(UInt(128.W)) 17 | val o_rdata = Output(UInt(128.W)) 18 | }) 19 | val wen_external = Wire(UInt(2.W)) 20 | val ren_external = Wire(UInt(2.W)) 21 | val cen_external = Wire(UInt(2.W)) 22 | val bwen_external = Wire(Vec(16,UInt(8.W))) 23 | val q_external = Wire(Vec(2,UInt(128.W))) 24 | wen_external := MuxCase(0.U,Seq( 25 | (io.i_addr(6) === "b0".U) -> "b01".U, 26 | (io.i_addr(6) === "b1".U) -> "b10".U, 27 | )) & Fill(2,io.i_wen) 28 | ren_external := MuxCase(0.U,Seq( 29 | (io.i_addr(6) === "b0".U) -> "b01".U, 30 | (io.i_addr(6) === "b1".U) -> "b10".U, 31 | )) & Fill(2,io.i_ren) 32 | cen_external := (wen_external | ren_external) 33 | for(i <- 0 to 15){ 34 | bwen_external(i) := Fill(8,~io.i_wstrb(i)) 35 | } 36 | val srams = Seq.fill(2)(Module(new S011HD1P_X32Y2D128_BW())) 37 | for(i <- 0 to 1){ 38 | srams(i).io.CLK := clock 39 | //srams(i).io.CEN := ~cen_external(i) 40 | srams(i).io.CEN := 0.U 41 | srams(i).io.WEN := ~wen_external(i) 42 | srams(i).io.BWEN := bwen_external.asUInt() 43 | srams(i).io.A := io.i_addr(5,0) 44 | srams(i).io.D := io.i_wdata 45 | q_external(i) := srams(i).io.Q 46 | } 47 | val ren_external_reg = RegInit(0.U(2.W)) 48 | ren_external_reg := ren_external 49 | 50 | val last_wen = RegInit(false.B) 51 | val last_waddr = RegInit(0.U(7.W)) 52 | val last_wdata = RegInit(0.U(128.W)) 53 | 54 | last_wen := io.i_wen 55 | last_waddr := io.i_addr 56 | last_wdata := io.i_wdata 57 | 58 | io.o_rdata := Mux(last_wen && last_waddr===io.i_addr,last_wdata, 59 | MuxCase(0.U,Seq( 60 | (ren_external_reg === "b01".U) -> q_external(0), 61 | (ren_external_reg === "b10".U) -> q_external(1), 62 | )) 63 | ) 64 | } 65 | -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/pc_gen.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | import chisel3._ 3 | import chisel3.ExplicitCompileOptions.Strict 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class PC_Gen extends Module 11 | { 12 | val io=IO(new Bundle{ 13 | val i_stall = Input(Bool()) 14 | val i_pc_redirect_valid = Input(new Bool()) 15 | val i_pc_redirect_target = Input(UInt(64.W)) 16 | 17 | val i_branch_predict_pack = Input(new branch_predict_pack()) 18 | val i_branch_presolve_pack = Input(new branch_presolve_pack()) 19 | val i_branch_resolve_pack = Input(new branch_resolve_pack()) 20 | 21 | val o_pc = Output(UInt(64.W)) 22 | }) 23 | 24 | val pc = RegInit(0x80000000L.U(64.W)); 25 | val npc = Wire(UInt(64.W)); 26 | 27 | //o_pc is not guaranteed to aligned to fetch pack address 28 | //addr passed to icache is guaranteed to aligned to it 29 | //and the pc passed to later stages are not aligned to fetch address 30 | //so they can tell if the first inst of the fetchres is valid 31 | io.o_pc := pc 32 | when(io.i_pc_redirect_valid){//interrupt, exception or ecall, mret 33 | npc := io.i_pc_redirect_target 34 | }.elsewhen(io.i_branch_resolve_pack.valid && io.i_branch_resolve_pack.mispred){//branch mispredict 35 | npc := io.i_branch_resolve_pack.target 36 | }.elsewhen(io.i_branch_presolve_pack.valid && io.i_branch_presolve_pack.taken){//mispred a non-br as br and tk,redirect 37 | //why do we add 8 when pc(2)==1? 38 | //when valid mispred on 1st of a fetchpack, it means it mispred a non-br to a br. 39 | //the presolver then tells to mark the 2nd inst valid, so the inst after the 1st of the fetch pack is already fetched. 40 | npc := io.i_branch_presolve_pack.pc + Mux(io.i_branch_presolve_pack.pc(2),4.U,8.U) 41 | }.elsewhen(io.i_stall){ 42 | npc := pc 43 | //when made prediction about the first of a fetch pack, but pc is the second one, ignore prediction 44 | }.elsewhen(io.i_branch_predict_pack.valid && io.i_branch_predict_pack.taken && !(io.i_branch_predict_pack.select === 0.U && pc(2) === 1.U)){ 45 | npc := io.i_branch_predict_pack.target 46 | }.otherwise{ 47 | npc := pc + Mux(pc(2),4.U(64.W),8.U(64.W)) 48 | } 49 | 50 | pc := npc; 51 | 52 | } 53 | -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/execute/mul_div/booth.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chisel3._ 6 | import chisel3.ExplicitCompileOptions.Strict 7 | import chiseltest._ 8 | import org.scalatest.freespec.AnyFreeSpec 9 | import chisel3.util._ 10 | import chisel3.util.BitPat 11 | import chisel3.util.experimental.decode._ 12 | import chisel3.experimental.BundleLiterals._ 13 | 14 | //64 bits radix-8 booth multiplier 15 | class Partial_Products_Gen extends Module{ 16 | val io = IO(new Bundle{ 17 | val i_x = Input(UInt(131.W)) 18 | val i_y = Input(UInt(67.W)) 19 | 20 | val o_partial_products = Output(Vec(22, UInt(131.W))) 21 | }) 22 | val xtimes1 = Wire(UInt(131.W)) 23 | val xtimes2 = Wire(UInt(131.W)) 24 | val xtimes3 = Wire(UInt(131.W)) 25 | val xtimes4 = Wire(UInt(131.W)) 26 | val xtimes1_com = Wire(UInt(131.W)) 27 | val xtimes2_com = Wire(UInt(131.W)) 28 | val xtimes3_com = Wire(UInt(131.W)) 29 | val xtimes4_com = Wire(UInt(131.W)) 30 | 31 | xtimes1 := io.i_x 32 | xtimes2 := io.i_x << 1 33 | xtimes3 := (io.i_x << 1) + io.i_x 34 | xtimes4 := io.i_x << 2 35 | xtimes1_com := ~xtimes1 + 1.U 36 | xtimes2_com := ~xtimes2 + 1.U 37 | xtimes3_com := ~xtimes3 + 1.U 38 | xtimes4_com := ~xtimes4 + 1.U 39 | 40 | val pp_gen_bits = Wire(Vec(22,UInt(4.W))) 41 | for(i <- 0 until 22){ 42 | pp_gen_bits(i) := io.i_y(3*i+3,3*i) 43 | } 44 | for(i<-0 until 22){ 45 | io.o_partial_products(i) := MuxCase(0.U(131.W),Seq( 46 | (pp_gen_bits(i) === 0.U) -> 0.U, 47 | (pp_gen_bits(i) === 1.U) -> xtimes1, 48 | (pp_gen_bits(i) === 2.U) -> xtimes1, 49 | (pp_gen_bits(i) === 3.U) -> xtimes2, 50 | (pp_gen_bits(i) === 4.U) -> xtimes2, 51 | (pp_gen_bits(i) === 5.U) -> xtimes3, 52 | (pp_gen_bits(i) === 6.U) -> xtimes3, 53 | (pp_gen_bits(i) === 7.U) -> xtimes4, 54 | (pp_gen_bits(i) === 8.U) -> xtimes4_com, 55 | (pp_gen_bits(i) === 9.U) -> xtimes3_com, 56 | (pp_gen_bits(i) === 10.U) -> xtimes3_com, 57 | (pp_gen_bits(i) === 11.U) -> xtimes2_com, 58 | (pp_gen_bits(i) === 12.U) -> xtimes2_com, 59 | (pp_gen_bits(i) === 13.U) -> xtimes1_com, 60 | (pp_gen_bits(i) === 14.U) -> xtimes1_com, 61 | (pp_gen_bits(i) === 15.U) -> 0.U 62 | )) << i*3 63 | } 64 | } 65 | -------------------------------------------------------------------------------- /src/test/scala/ladder/CPU_top.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Ladder_nodpic extends Module { 12 | val io = IO(new Bundle { 13 | //icache io 14 | val icache_io = new IcacheIO() 15 | //dcache io 16 | val dcache_io = new DcacheIO() 17 | val i_interrupt = Input(Bool()) 18 | }) 19 | val front_end = Module(new Front_End()) 20 | val back_end = Module(new Back_End_With_Decode()) 21 | 22 | //connect front end input 23 | val last_branch_resolve_pack = RegInit(0.U.asTypeOf(new branch_resolve_pack())) 24 | last_branch_resolve_pack := back_end.io.o_branch_resolve_pack 25 | //when backend branch resolve flush, the front end just have to flush one cycle 26 | front_end.io.i_branch_resolve_pack := Mux(last_branch_resolve_pack.asUInt === back_end.io.o_branch_resolve_pack.asUInt, 27 | 0.U.asTypeOf(new branch_resolve_pack()), back_end.io.o_branch_resolve_pack) 28 | front_end.io.i_pc_redirect_valid := back_end.io.o_pc_redirect_valid 29 | front_end.io.i_pc_redirect_target := back_end.io.o_pc_redirect_target 30 | 31 | front_end.io.icache_io.i_addr_ready := io.icache_io.i_addr_ready 32 | front_end.io.icache_io.i_data_valid := io.icache_io.i_data_valid 33 | io.icache_io.o_wen := front_end.io.icache_io.o_wen 34 | io.icache_io.o_addr := front_end.io.icache_io.o_addr 35 | io.icache_io.o_addr_valid := front_end.io.icache_io.o_addr_valid 36 | front_end.io.icache_io.i_data := io.icache_io.i_data 37 | 38 | //connect back end input 39 | back_end.io.i_fetch_pack <> front_end.io.o_fetch_pack 40 | back_end.io.i_interrupt := io.i_interrupt 41 | 42 | back_end.io.dcache_io.data_valid := io.dcache_io.data_valid 43 | back_end.io.dcache_io.MdataIn := io.dcache_io.MdataIn 44 | io.dcache_io.addr_valid :=back_end.io.dcache_io.addr_valid 45 | io.dcache_io.data_ready :=back_end.io.dcache_io.data_ready 46 | back_end.io.dcache_io.addr_ready := io.dcache_io.addr_ready 47 | 48 | io.dcache_io.Mwout :=back_end.io.dcache_io.Mwout 49 | io.dcache_io.Maddr :=back_end.io.dcache_io.Maddr 50 | io.dcache_io.Men :=back_end.io.dcache_io.Men 51 | io.dcache_io.Mlen :=back_end.io.dcache_io.Mlen 52 | io.dcache_io.MdataOut :=back_end.io.dcache_io.MdataOut 53 | } 54 | -------------------------------------------------------------------------------- /genrtl/Interrupt_Mask.v: -------------------------------------------------------------------------------- 1 | module Interrupt_Mask( 2 | input clock, 3 | input reset, 4 | input io_i_lsu_uop_valid, 5 | input [3:0] io_i_rob_idx, 6 | input [3:0] io_i_lsu_uop_rob_idx, 7 | input io_i_interrupt, 8 | output io_o_interrupt_with_mask 9 | ); 10 | `ifdef RANDOMIZE_REG_INIT 11 | reg [31:0] _RAND_0; 12 | reg [31:0] _RAND_1; 13 | `endif // RANDOMIZE_REG_INIT 14 | reg mask; // @[interrupt_mask.scala 25:23] 15 | reg [3:0] cmt_ptr; // @[interrupt_mask.scala 28:26] 16 | wire _GEN_0 = io_i_lsu_uop_valid & io_i_lsu_uop_rob_idx == io_i_rob_idx | mask; // @[interrupt_mask.scala 29:15 30:68 31:19] 17 | wire next_mask = mask & io_i_rob_idx != cmt_ptr ? 1'h0 : _GEN_0; // @[interrupt_mask.scala 34:52 35:19] 18 | assign io_o_interrupt_with_mask = next_mask ? 1'h0 : io_i_interrupt; // @[interrupt_mask.scala 37:36] 19 | always @(posedge clock) begin 20 | if (reset) begin // @[interrupt_mask.scala 25:23] 21 | mask <= 1'h0; // @[interrupt_mask.scala 25:23] 22 | end else if (mask & io_i_rob_idx != cmt_ptr) begin // @[interrupt_mask.scala 34:52] 23 | mask <= 1'h0; // @[interrupt_mask.scala 35:19] 24 | end else begin 25 | mask <= _GEN_0; 26 | end 27 | if (reset) begin // @[interrupt_mask.scala 28:26] 28 | cmt_ptr <= 4'h0; // @[interrupt_mask.scala 28:26] 29 | end else if (io_i_lsu_uop_valid & io_i_lsu_uop_rob_idx == io_i_rob_idx) begin // @[interrupt_mask.scala 30:68] 30 | cmt_ptr <= io_i_rob_idx; // @[interrupt_mask.scala 32:17] 31 | end 32 | end 33 | // Register and memory initialization 34 | `ifdef RANDOMIZE_GARBAGE_ASSIGN 35 | `define RANDOMIZE 36 | `endif 37 | `ifdef RANDOMIZE_INVALID_ASSIGN 38 | `define RANDOMIZE 39 | `endif 40 | `ifdef RANDOMIZE_REG_INIT 41 | `define RANDOMIZE 42 | `endif 43 | `ifdef RANDOMIZE_MEM_INIT 44 | `define RANDOMIZE 45 | `endif 46 | `ifndef RANDOM 47 | `define RANDOM $random 48 | `endif 49 | `ifdef RANDOMIZE_MEM_INIT 50 | integer initvar; 51 | `endif 52 | `ifndef SYNTHESIS 53 | `ifdef FIRRTL_BEFORE_INITIAL 54 | `FIRRTL_BEFORE_INITIAL 55 | `endif 56 | initial begin 57 | `ifdef RANDOMIZE 58 | `ifdef INIT_RANDOM 59 | `INIT_RANDOM 60 | `endif 61 | `ifndef VERILATOR 62 | `ifdef RANDOMIZE_DELAY 63 | #`RANDOMIZE_DELAY begin end 64 | `else 65 | #0.002 begin end 66 | `endif 67 | `endif 68 | `ifdef RANDOMIZE_REG_INIT 69 | _RAND_0 = {1{`RANDOM}}; 70 | mask = _RAND_0[0:0]; 71 | _RAND_1 = {1{`RANDOM}}; 72 | cmt_ptr = _RAND_1[3:0]; 73 | `endif // RANDOMIZE_REG_INIT 74 | `endif // RANDOMIZE 75 | end // initial 76 | `ifdef FIRRTL_AFTER_INITIAL 77 | `FIRRTL_AFTER_INITIAL 78 | `endif 79 | `endif // SYNTHESIS 80 | endmodule 81 | -------------------------------------------------------------------------------- /src/test/scala/ladder/ladder.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.BitPat 9 | import chisel3.util.experimental.decode._ 10 | import chisel3.experimental.BundleLiterals._ 11 | import chisel3.stage._ 12 | 13 | //test:runMain Ladder.GenVerilog 14 | object GenVerilog extends App{ 15 | (new ChiselStage).execute( 16 | Array( 17 | "-X", "verilog", 18 | "-e", "verilog", 19 | "--target-dir", "genrtl"), 20 | Seq(ChiselGeneratorAnnotation(() => new Ladder())) 21 | ) 22 | } 23 | 24 | /* 25 | class GCDSpec extends AnyFreeSpec with ChiselScalatestTester { 26 | "Gcd should calculate proper greatest common denominator" in { 27 | test(new Back_End_With_Decode()).withAnnotations(Seq( WriteVcdAnnotation )) { c => 28 | c.io.i_fetch_pack.valid.poke(false.B) 29 | c.io.i_fetch_pack.bits.pc.poke(0.U) 30 | c.io.i_fetch_pack.bits.insts(0).poke(0.U) 31 | c.io.i_fetch_pack.bits.insts(1).poke(0.U) 32 | c.io.i_fetch_pack.bits.branch_predict_packs(0).valid.poke(false.B) 33 | c.io.i_fetch_pack.bits.branch_predict_packs(1).valid.poke(false.B) 34 | c.clock.step(1) 35 | c.io.i_fetch_pack.bits.pc.poke(0.U) 36 | c.io.i_fetch_pack.bits.insts(0).poke(0x00508093.U) 37 | c.io.i_fetch_pack.bits.insts(1).poke(0x00419263.U) 38 | 39 | c.io.i_fetch_pack.bits.branch_predict_packs(1).valid.poke(true.B) 40 | c.io.i_fetch_pack.bits.branch_predict_packs(1).is_branch.poke(true.B) 41 | c.io.i_fetch_pack.bits.branch_predict_packs(1).taken.poke(false.B) 42 | c.io.i_fetch_pack.bits.branch_predict_packs(1).target.poke(0.U) 43 | c.io.i_fetch_pack.valid.poke(true.B) 44 | c.clock.step(1) 45 | c.io.i_fetch_pack.bits.pc.poke(0.U) 46 | c.io.i_fetch_pack.bits.insts(0).poke(0x00510113.U) 47 | c.io.i_fetch_pack.bits.insts(1).poke(0x00510213.U) 48 | c.io.i_fetch_pack.bits.branch_predict_packs(0).valid.poke(false.B) 49 | c.io.i_fetch_pack.bits.branch_predict_packs(1).valid.poke(false.B) 50 | c.clock.step(1) 51 | c.io.i_fetch_pack.bits.pc.poke(0.U) 52 | c.io.i_fetch_pack.bits.insts(0).poke(0x00520113.U) 53 | c.io.i_fetch_pack.bits.insts(1).poke(0x00528213.U) 54 | c.clock.step(1) 55 | c.io.i_fetch_pack.bits.pc.poke(0.U) 56 | c.io.i_fetch_pack.bits.insts(0).poke(0x00110233.U) 57 | c.io.i_fetch_pack.bits.insts(1).poke(0x00110233.U) 58 | c.clock.step(1) 59 | c.io.i_fetch_pack.valid.poke(false.B) 60 | c.clock.step(1) 61 | c.io.i_fetch_pack.valid.poke(false.B) 62 | c.clock.step(1) 63 | c.clock.step(1) 64 | c.clock.step(1) 65 | c.clock.step(1) 66 | c.clock.step(1) 67 | c.clock.step(1) 68 | 69 | }} 70 | } 71 | //test -- -DwriteVcd=1 72 | //test -- -DwriteVcd=1 --debug 73 | */ 74 | -------------------------------------------------------------------------------- /src/test/scala/ladder/dpic-axi-ver.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class dpic_axi_ver extends BlackBox{ 11 | val io = IO(new Bundle{ 12 | val clk = Input(Clock()) 13 | val rst = Input(Reset()) 14 | val stop = Input(Bool()) 15 | 16 | val axi_readAddr_ready =Output(UInt(1.W)) 17 | val axi_readAddr_valid =Input(UInt(1.W)) 18 | val axi_readAddr_bits_addr =Input(UInt(64.W)) 19 | val axi_readAddr_bits_prot =Input(UInt(3.W)) 20 | val axi_readData_ready =Input(UInt(1.W)) 21 | val axi_readData_valid =Output(UInt(1.W)) 22 | val axi_readData_bits_data =Output(UInt(128.W)) 23 | val axi_readData_bits_resp =Output(UInt(2.W)) 24 | val axi_writeAddr_ready =Output(UInt(1.W)) 25 | val axi_writeAddr_valid =Input(UInt(1.W)) 26 | val axi_writeAddr_bits_addr =Input(UInt(64.W)) 27 | val axi_writeAddr_bits_prot =Input(UInt(3.W)) 28 | val axi_writeData_ready =Output(UInt(1.W)) 29 | val axi_writeData_valid =Input(UInt(1.W)) 30 | val axi_writeData_bits_data =Input(UInt(128.W)) 31 | val axi_writeData_bits_strb =Input(UInt(16.W)) 32 | val axi_writeResp_ready =Input(UInt(1.W)) 33 | val axi_writeResp_valid =Output(UInt(1.W)) 34 | val axi_writeResp_bits =Output(UInt(2.W)) 35 | 36 | //regfile dpi 37 | val regs0 = Input(UInt(64.W)) 38 | val regs1 = Input(UInt(64.W)) 39 | val regs2 = Input(UInt(64.W)) 40 | val regs3 = Input(UInt(64.W)) 41 | val regs4 = Input(UInt(64.W)) 42 | val regs5 = Input(UInt(64.W)) 43 | val regs6 = Input(UInt(64.W)) 44 | val regs7 = Input(UInt(64.W)) 45 | val regs8 = Input(UInt(64.W)) 46 | val regs9 = Input(UInt(64.W)) 47 | val regs10 = Input(UInt(64.W)) 48 | val regs11 = Input(UInt(64.W)) 49 | val regs12 = Input(UInt(64.W)) 50 | val regs13 = Input(UInt(64.W)) 51 | val regs14 = Input(UInt(64.W)) 52 | val regs15 = Input(UInt(64.W)) 53 | val regs16 = Input(UInt(64.W)) 54 | val regs17 = Input(UInt(64.W)) 55 | val regs18 = Input(UInt(64.W)) 56 | val regs19 = Input(UInt(64.W)) 57 | val regs20 = Input(UInt(64.W)) 58 | val regs21 = Input(UInt(64.W)) 59 | val regs22 = Input(UInt(64.W)) 60 | val regs23 = Input(UInt(64.W)) 61 | val regs24 = Input(UInt(64.W)) 62 | val regs25 = Input(UInt(64.W)) 63 | val regs26 = Input(UInt(64.W)) 64 | val regs27 = Input(UInt(64.W)) 65 | val regs28 = Input(UInt(64.W)) 66 | val regs29 = Input(UInt(64.W)) 67 | val regs30 = Input(UInt(64.W)) 68 | val regs31 = Input(UInt(64.W)) 69 | }) 70 | } 71 | 72 | -------------------------------------------------------------------------------- /verilogtestbench/top_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define RANDOMIZE_REG_INIT 3 | `define RANDOMIZE_MEM_INIT 4 | `define RANDOMIZE_GARBAGE_ASSIGN 5 | `define RANDOMIZE_INVALID_ASSIGN 6 | 7 | module Ladder_tb; 8 | // Inputs 9 | reg clk; 10 | reg resetn; 11 | 12 | reg [63:0] io_icache_io_i_data; 13 | reg io_icache_io_i_addr_ready; 14 | reg io_icache_io_i_data_valid; 15 | reg io_dcache_io_data_valid; 16 | reg io_dcache_io_addr_ready; 17 | reg [63:0] io_dcache_io_MdataIn; 18 | reg io_i_interrupt; 19 | 20 | 21 | Ladder uut1 ( 22 | .clock(clk), 23 | .reset(!resetn), 24 | .io_icache_io_o_wen(io_icache_io_o_wen), 25 | .io_icache_io_o_addr(io_icache_io_o_addr), 26 | .io_icache_io_i_data(io_icache_io_i_data), 27 | .io_icache_io_i_addr_ready(io_icache_io_i_addr_ready), 28 | .io_icache_io_o_addr_valid(io_icache_io_o_addr_valid), 29 | .io_icache_io_i_data_valid(io_icache_io_i_data_valid), 30 | .io_dcache_io_data_valid(io_dcache_io_data_valid), 31 | .io_dcache_io_data_ready(io_dcache_io_data_ready), 32 | .io_dcache_io_addr_valid(io_dcache_io_addr_valid), 33 | .io_dcache_io_addr_ready(io_dcache_io_addr_ready), 34 | .io_dcache_io_Mwout(io_dcache_io_Mwout), 35 | .io_dcache_io_Maddr(io_dcache_io_Maddr), 36 | .io_dcache_io_Men(io_dcache_io_Men), 37 | .io_dcache_io_Mlen(io_dcache_io_Mlen), 38 | .io_dcache_io_MdataIn(io_dcache_io_MdataIn), 39 | .io_dcache_io_MdataOut(io_dcache_io_MdataOut), 40 | .io_i_interrupt(io_i_interrupt) 41 | ); 42 | 43 | initial begin 44 | // Initialize Inputs 45 | clk = 0; 46 | resetn = 0; 47 | 48 | io_icache_io_i_data = 64'h0; 49 | io_icache_io_i_addr_ready = 1'b0; 50 | io_icache_io_i_data_valid = 1'b0; 51 | io_dcache_io_data_valid = 1'b0; 52 | io_dcache_io_addr_ready = 1'b0; 53 | io_dcache_io_MdataIn = 64'b0; 54 | io_i_interrupt = 1'b0; 55 | 56 | #10; 57 | io_icache_io_i_addr_ready = 1'b1; 58 | io_icache_io_i_data_valid = 1'b1; 59 | io_icache_io_i_data[31:0] = 32'h00508093; 60 | io_icache_io_i_data[63:32] = 32'h00508113; 61 | 62 | #100; 63 | resetn = 1; 64 | 65 | #10; 66 | io_icache_io_i_data[31:0] = 32'h00510113;//x2=5 67 | io_icache_io_i_data[63:32] = 32'h00508093;//x1=5 68 | 69 | #20; 70 | io_icache_io_i_data[31:0] = 32'h022081b3;//x3 = 25 71 | io_icache_io_i_data[63:32] = 32'h00508093; //x1=10 72 | #10; 73 | io_icache_io_i_data[31:0] = 32'h40110133;//sub x2, x2 ,x1 74 | io_icache_io_i_data[63:32] = 32'h00110233;//add x4, x2 ,x1 75 | 76 | #15 77 | io_icache_io_i_addr_ready = 1'b0; 78 | io_icache_io_i_data_valid = 1'b0; 79 | 80 | #300 81 | $finish(1); 82 | end 83 | always #5 clk = ~clk; 84 | 85 | endmodule -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/fetchres.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | /* Things to do with presolve mispred 11 | *1.fetch_pc(2)==0, predict.sel==0, if predict wrong(mistaken non-br to br), if pred tk, flush the previous stages, make insts(1) valid. o_predict_pack.valid=false 12 | * if pred ntk, do not flush, insts(1) valid, o_predict_pack.valid=false 13 | *2.fetch_pc(2)==0, predict.sel==1, if predict wrong, if pred tk, flush the previous stages, o_predict_pack.valid=false 14 | * if pred ntk, do not flush, o_predict_pack.valid=false 15 | *3.fetch_pc(2)==1,predict.sel==0, disable presolve to avoid control flow change(or modify to make more fine-grained control) 16 | *4.fetch_pc(2)==1,predict.sel==1,same as above 17 | * 18 | * why disable predict pack on a mispred? 19 | * because when mispred, the entry in btb will be marked as invalid 20 | * and when this inst goes into bru, it will add an entry in btb 21 | */ 22 | 23 | class Fetch_Res extends Module{ 24 | val io =IO( new Bundle{ 25 | val i_pc = Input(UInt(64.W)) 26 | val i_flush = Input(Bool()) 27 | val i_stall = Input(Bool()) 28 | val i_fetch_res = Input(UInt(64.W)) 29 | val i_branch_predict_pack = Input(new branch_predict_pack()) 30 | val i_branch_presolve_pack = Input(new branch_presolve_pack()) 31 | 32 | val o_fetch_pack = Decoupled(new fetch_pack()) 33 | val o_fetch_pack_with_presolve = Decoupled(new fetch_pack()) 34 | }) 35 | io.o_fetch_pack.valid := (io.o_fetch_pack.bits.valids(0) || io.o_fetch_pack.bits.valids(1)) 36 | io.o_fetch_pack.bits.valids(0) := !io.i_stall && !io.i_pc(2) && !io.i_flush 37 | io.o_fetch_pack.bits.valids(1) := !io.i_stall && !io.i_flush && 38 | !(io.i_branch_predict_pack.valid && io.i_branch_predict_pack.taken && io.i_branch_predict_pack.select === 0.U && io.i_pc(2) === 0.U) 39 | io.o_fetch_pack.bits.pc := Cat(io.i_pc(63,3),0.U(3.W)) 40 | io.o_fetch_pack.bits.insts(0) := io.i_fetch_res(31,0) 41 | io.o_fetch_pack.bits.insts(1) := io.i_fetch_res(63,32) 42 | io.o_fetch_pack.bits.branch_predict_pack := io.i_branch_predict_pack 43 | 44 | io.o_fetch_pack_with_presolve.bits := io.o_fetch_pack.bits 45 | io.o_fetch_pack_with_presolve.valid := (io.o_fetch_pack_with_presolve.bits.valids(0) || io.o_fetch_pack_with_presolve.bits.valids(1)) 46 | io.o_fetch_pack_with_presolve.bits.valids(0) := io.o_fetch_pack.bits.valids(0) 47 | io.o_fetch_pack_with_presolve.bits.valids(1) := !io.i_stall && !io.i_flush && ( 48 | !(io.i_branch_predict_pack.valid && io.i_branch_predict_pack.taken && io.i_branch_predict_pack.select === 0.U && io.i_pc(2) === 0.U) || 49 | ((io.i_branch_predict_pack.valid && io.i_branch_predict_pack.taken && io.i_branch_predict_pack.select === 0.U && io.i_pc(2) === 0.U) && 50 | (io.i_branch_presolve_pack.valid && io.i_branch_presolve_pack.taken)) 51 | ) 52 | 53 | when(io.i_branch_presolve_pack.valid){ 54 | io.o_fetch_pack_with_presolve.bits.branch_predict_pack.valid := false.B 55 | } 56 | } 57 | -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/rename/rename_table.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3._ 8 | import chisel3.ExplicitCompileOptions.Strict 9 | import chisel3.util._ 10 | import chisel3.util.experimental.decode._ 11 | import chisel3.experimental.BundleLiterals._ 12 | 13 | class rename_req_pack extends Bundle 14 | { 15 | val arch_rs1 = UInt(5.W) 16 | val arch_rs2 = UInt(5.W) 17 | val arch_dst = UInt(5.W) 18 | } 19 | class rename_res_pack extends Bundle 20 | { 21 | val phy_rs1 = UInt(7.W) 22 | val phy_rs2 = UInt(7.W) 23 | val phy_dst = UInt(7.W) 24 | } 25 | class Rename_Table extends Module{ 26 | val io=IO(new Bundle{ 27 | val i_rename_req_packs=Input(Vec(2,new rename_req_pack())) 28 | val o_rename_res_packs=Output(Vec(2,new rename_res_pack())) 29 | 30 | val i_allocation_pack=Input(Vec(2,new uop())) 31 | 32 | val i_commit_packs=Input(Vec(2,new commit_pack())) 33 | val i_rollback_packs=Input(Vec(2,new rollback_pack())) 34 | 35 | val i_exception=Input(Bool()) 36 | //val i_branch_backuptables //well....what to do with this one.. 37 | 38 | //for decode and dpi-c arch regs 39 | val o_commit_rename_table = Output(Vec(32,UInt(7.W))) 40 | }) 41 | val rename_table = RegInit(VecInit(Seq.fill(32)(0.U(7.W)))) 42 | val commit_rename_table = RegInit(VecInit(Seq.fill(32)(0.U(7.W)))) 43 | io.o_commit_rename_table:=commit_rename_table 44 | 45 | //write logic 46 | when(io.i_commit_packs(0).valid){ 47 | commit_rename_table(io.i_commit_packs(0).uop.arch_dst):=io.i_commit_packs(0).uop.phy_dst 48 | } 49 | when(io.i_commit_packs(1).valid){ 50 | commit_rename_table(io.i_commit_packs(1).uop.arch_dst):=io.i_commit_packs(1).uop.phy_dst 51 | } 52 | //rollback_packs(0)=rob(allocate-1) and rollback(1) = rob(allocate-2) 53 | //must rollback in this order: rollback_packs(0) first, then rollback_packs(1) 54 | //or else when of the same arch dst, rollback res might be wrong 55 | //the same reason why allocation and commit should use the default order 56 | when(io.i_rollback_packs(0).valid){ 57 | rename_table(io.i_rollback_packs(0).uop.arch_dst):=io.i_rollback_packs(0).uop.stale_dst 58 | } 59 | 60 | when(io.i_rollback_packs(1).valid){ 61 | rename_table(io.i_rollback_packs(1).uop.arch_dst):=io.i_rollback_packs(1).uop.stale_dst 62 | } 63 | 64 | when(io.i_allocation_pack(0).valid && io.i_allocation_pack(0).arch_dst =/= 0.U){ 65 | rename_table(io.i_allocation_pack(0).arch_dst):=io.i_allocation_pack(0).phy_dst 66 | } 67 | when(io.i_allocation_pack(1).valid && io.i_allocation_pack(1).arch_dst =/= 0.U){ 68 | rename_table(io.i_allocation_pack(1).arch_dst):=io.i_allocation_pack(1).phy_dst 69 | } 70 | 71 | //read logic 72 | for(i<-0 until 2){ 73 | io.o_rename_res_packs(i).phy_rs1:=rename_table(io.i_rename_req_packs(i).arch_rs1) 74 | io.o_rename_res_packs(i).phy_rs2:=rename_table(io.i_rename_req_packs(i).arch_rs2) 75 | io.o_rename_res_packs(i).phy_dst:=rename_table(io.i_rename_req_packs(i).arch_dst) 76 | } 77 | 78 | //exception logic 79 | when(io.i_exception){ 80 | rename_table:=commit_rename_table 81 | } 82 | } 83 | -------------------------------------------------------------------------------- /genrtl/PC_Gen.v: -------------------------------------------------------------------------------- 1 | module PC_Gen( 2 | input clock, 3 | input reset, 4 | input io_i_stall, 5 | input io_i_pc_redirect_valid, 6 | input [63:0] io_i_pc_redirect_target, 7 | input io_i_branch_predict_pack_valid, 8 | input [63:0] io_i_branch_predict_pack_target, 9 | input io_i_branch_predict_pack_select, 10 | input io_i_branch_predict_pack_taken, 11 | input io_i_branch_presolve_pack_valid, 12 | input io_i_branch_presolve_pack_taken, 13 | input [63:0] io_i_branch_presolve_pack_pc, 14 | input io_i_branch_resolve_pack_valid, 15 | input io_i_branch_resolve_pack_mispred, 16 | input [63:0] io_i_branch_resolve_pack_target, 17 | output [63:0] io_o_pc 18 | ); 19 | `ifdef RANDOMIZE_REG_INIT 20 | reg [63:0] _RAND_0; 21 | `endif // RANDOMIZE_REG_INIT 22 | reg [63:0] pc; // @[pc_gen.scala 24:21] 23 | wire [3:0] _npc_T_1 = io_i_branch_presolve_pack_pc[2] ? 4'h4 : 4'h8; // @[pc_gen.scala 40:50] 24 | wire [63:0] _GEN_5 = {{60'd0}, _npc_T_1}; // @[pc_gen.scala 40:45] 25 | wire [63:0] _npc_T_3 = io_i_branch_presolve_pack_pc + _GEN_5; // @[pc_gen.scala 40:45] 26 | wire [63:0] _npc_T_5 = pc[2] ? 64'h4 : 64'h8; // @[pc_gen.scala 47:24] 27 | wire [63:0] _npc_T_7 = pc + _npc_T_5; // @[pc_gen.scala 47:19] 28 | wire [63:0] _GEN_0 = io_i_branch_predict_pack_valid & io_i_branch_predict_pack_taken & ~(~ 29 | io_i_branch_predict_pack_select & pc[2]) ? io_i_branch_predict_pack_target : _npc_T_7; // @[pc_gen.scala 44:144 45:13 47:13] 30 | wire [63:0] _GEN_1 = io_i_stall ? pc : _GEN_0; // @[pc_gen.scala 41:27 42:13] 31 | assign io_o_pc = pc; // @[pc_gen.scala 31:13] 32 | always @(posedge clock) begin 33 | if (reset) begin // @[pc_gen.scala 24:21] 34 | pc <= 64'h80000000; // @[pc_gen.scala 24:21] 35 | end else if (io_i_pc_redirect_valid) begin // @[pc_gen.scala 32:33] 36 | pc <= io_i_pc_redirect_target; // @[pc_gen.scala 33:13] 37 | end else if (io_i_branch_resolve_pack_valid & io_i_branch_resolve_pack_mispred) begin // @[pc_gen.scala 34:83] 38 | pc <= io_i_branch_resolve_pack_target; // @[pc_gen.scala 35:13] 39 | end else if (io_i_branch_presolve_pack_valid & io_i_branch_presolve_pack_taken) begin // @[pc_gen.scala 36:83] 40 | pc <= _npc_T_3; // @[pc_gen.scala 40:13] 41 | end else begin 42 | pc <= _GEN_1; 43 | end 44 | end 45 | // Register and memory initialization 46 | `ifdef RANDOMIZE_GARBAGE_ASSIGN 47 | `define RANDOMIZE 48 | `endif 49 | `ifdef RANDOMIZE_INVALID_ASSIGN 50 | `define RANDOMIZE 51 | `endif 52 | `ifdef RANDOMIZE_REG_INIT 53 | `define RANDOMIZE 54 | `endif 55 | `ifdef RANDOMIZE_MEM_INIT 56 | `define RANDOMIZE 57 | `endif 58 | `ifndef RANDOM 59 | `define RANDOM $random 60 | `endif 61 | `ifdef RANDOMIZE_MEM_INIT 62 | integer initvar; 63 | `endif 64 | `ifndef SYNTHESIS 65 | `ifdef FIRRTL_BEFORE_INITIAL 66 | `FIRRTL_BEFORE_INITIAL 67 | `endif 68 | initial begin 69 | `ifdef RANDOMIZE 70 | `ifdef INIT_RANDOM 71 | `INIT_RANDOM 72 | `endif 73 | `ifndef VERILATOR 74 | `ifdef RANDOMIZE_DELAY 75 | #`RANDOMIZE_DELAY begin end 76 | `else 77 | #0.002 begin end 78 | `endif 79 | `endif 80 | `ifdef RANDOMIZE_REG_INIT 81 | _RAND_0 = {2{`RANDOM}}; 82 | pc = _RAND_0[63:0]; 83 | `endif // RANDOMIZE_REG_INIT 84 | `endif // RANDOMIZE 85 | end // initial 86 | `ifdef FIRRTL_AFTER_INITIAL 87 | `FIRRTL_AFTER_INITIAL 88 | `endif 89 | `endif // SYNTHESIS 90 | endmodule 91 | -------------------------------------------------------------------------------- /csrc/memory.cpp: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | 9 | extern uint64_t img_size; 10 | uint8_t *mem=nullptr; 11 | int size=0x8000000; 12 | int mem_init(){ 13 | mem=new uint8_t[size]; 14 | std::cout<<"mem defined\n"; 15 | return 0; 16 | } 17 | 18 | 19 | uint64_t pmem_read(int addr){ 20 | //std::cout<<"mem read: 0x"<=2){ 40 | mem[addr-0x80000000+1]=content>>8; 41 | if(len>=4){ 42 | mem[addr-0x80000000+2]=content>>16; 43 | mem[addr-0x80000000+3]=content>>24; 44 | if(len==8){ 45 | mem[addr-0x80000000+4]=content>>32; 46 | mem[addr-0x80000000+5]=content>>40; 47 | mem[addr-0x80000000+6]=content>>48; 48 | mem[addr-0x80000000+7]=content>>56; 49 | } 50 | } 51 | } 52 | } 53 | 54 | 55 | return 0; 56 | } 57 | int free_memory(){ 58 | delete mem; 59 | return 0; 60 | } 61 | 62 | char name[30]="sim/demorevert.txt"; 63 | char *img_file=name; 64 | 65 | long load_img(char ** argv){ 66 | 67 | char *img = argv[1]; 68 | if(img_file==NULL&&img==NULL){ 69 | std::cout<<"no img is given,please specify a img\n"; 70 | return -1; 71 | } 72 | if(img!=NULL){ 73 | std::cout<<"using specified img\n"; 74 | img_file=img; 75 | }else{ 76 | std::cout<<"using default img\n"; 77 | } 78 | 79 | //打印输出当前路径 80 | char *buffer; 81 | //也可以将buffer作为输出参数 82 | if((buffer = getcwd(NULL, 0)) == NULL) 83 | { 84 | perror("getcwd error"); 85 | } 86 | else 87 | { 88 | printf("path:%s\n", buffer); 89 | free(buffer); 90 | } 91 | 92 | std::cout<<"trying to find img\n"; 93 | FILE *fp =fopen(img_file,"rb"); 94 | if(fp==NULL){ 95 | std::cout<<"open failed\n"; 96 | } 97 | //assert(fp, "Can not open '%s'", img_file); 98 | 99 | fseek(fp, 0, SEEK_END); 100 | long size = ftell(fp); 101 | img_size=size; 102 | 103 | std::cout<<"the img is "<uopvalid 46 | //!stall && rbk ->uopvalid 47 | //stall && !rbk -> false 48 | //!stall && !rbk ->uopvalid 49 | 50 | io.o_rob_allocation_reqs(0).valid:=Mux(((io.i_reservation_station_full || io.i_rob_busy) && !(io.i_branch_resolve_pack.mispred && io.i_branch_resolve_pack.valid)) ,false.B,uops(0).valid) 51 | io.o_rob_allocation_reqs(1).valid:=Mux(((io.i_reservation_station_full || io.i_rob_busy) && !(io.i_branch_resolve_pack.mispred && io.i_branch_resolve_pack.valid)) ,false.B,uops(1).valid) 52 | 53 | io.o_rob_allocation_reqs(0).uop := uops(0) 54 | io.o_rob_allocation_reqs(1).uop := uops(1) 55 | 56 | io.o_dispatch_packs(0) := uops(0) 57 | io.o_dispatch_packs(1) := uops(1) 58 | io.o_dispatch_packs(0).valid := uops(0).valid 59 | io.o_dispatch_packs(1).valid := uops(1).valid 60 | when((io.i_branch_resolve_pack.valid&&io.i_branch_resolve_pack.mispred)||stall){ 61 | io.o_dispatch_packs(0).valid:=false.B 62 | io.o_dispatch_packs(1).valid:=false.B 63 | } 64 | io.o_dispatch_packs(0).rob_idx:=io.i_rob_allocation_ress(0).rob_idx 65 | io.o_dispatch_packs(1).rob_idx:=io.i_rob_allocation_ress(1).rob_idx 66 | } 67 | -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/execute/mul_div/mul.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chisel3._ 6 | import chisel3.ExplicitCompileOptions.Strict 7 | import chiseltest._ 8 | import org.scalatest.freespec.AnyFreeSpec 9 | import chisel3.util._ 10 | import chisel3.util.BitPat 11 | import chisel3.util.experimental.decode._ 12 | import chisel3.experimental.BundleLiterals._ 13 | 14 | //64 bits radix-8 booth multiplier 15 | class Multiplier extends Module{ 16 | val io = IO(new Bundle{ 17 | val i_mul_valid = Input(Bool()) 18 | val i_flush = Input(Bool()) 19 | val i_mulw = Input(Bool()) 20 | val i_mul_signed = Input(UInt(2.W)) 21 | val i_multiplicand = Input(UInt(64.W)) 22 | val i_multiplier = Input(UInt(64.W)) 23 | val o_mul_ready = Output(Bool()) 24 | val o_out_valid = Output(Bool()) 25 | val o_result_hi = Output(UInt(64.W)) 26 | val o_result_lo = Output(UInt(64.W)) 27 | }) 28 | val state = RegInit(0.U(3.W)) 29 | val next_state = Wire(UInt(3.W)) 30 | state := next_state 31 | next_state := Mux(io.i_flush, 0.U, state + 1.U) 32 | 33 | io.o_out_valid := Mux(state===7.U, true.B, false.B) 34 | io.o_mul_ready := Mux(state===0.U, true.B, false.B) 35 | 36 | val multiplier = Reg(UInt(64.W)) 37 | val multiplicand = Reg(UInt(64.W)) 38 | multiplier := Mux(io.i_mul_valid, io.i_multiplier, multiplier) 39 | multiplicand := Mux(io.i_mul_valid, io.i_multiplicand, multiplicand) 40 | 41 | val partial_products = Wire(Vec(22, UInt(131.W)) ) 42 | //reotate left by 3 each partial product, 22 pps, (22-1)*3+64+1(sign/unsigned ext)+2(pp*4 overflow) +1(flip by bit and +1 overflow) 43 | val booth_x = Wire(UInt(131.W)) 44 | //scan 4b each time, so [65,62],[62,59]....[2,-1] 45 | val booth_y = Wire(UInt(67.W)) 46 | val x_64 = Wire(UInt(131.W)) 47 | val y_64 = Wire(UInt(67.W)) 48 | //val x_32 = Wire(UInt(131.W)) 49 | //val y_32 = Wire(UInt(67.W)) 50 | 51 | x_64 := MuxCase(0.U, Seq( 52 | (io.i_mul_signed === 0.U) -> Cat(0.U(67.W),multiplicand), 53 | (io.i_mul_signed === 1.U) -> 0.U(131.W), 54 | (io.i_mul_signed === 2.U) -> Cat(Fill(67,multiplicand(63)),multiplicand), 55 | (io.i_mul_signed === 3.U) -> Cat(Fill(67,multiplicand(63)),multiplicand) 56 | )) 57 | y_64 := MuxCase(0.U, Seq( 58 | (io.i_mul_signed === 0.U) -> Cat(Cat(0.U(2.W),multiplier),0.U(1.W)), 59 | (io.i_mul_signed === 1.U) -> 0.U(67.W), 60 | (io.i_mul_signed === 2.U) -> Cat(Cat(0.U(2.W),multiplier),0.U(1.W)), 61 | (io.i_mul_signed === 3.U) -> Cat(Cat(Fill(2,multiplier(63)),multiplier),0.U(1.W)) 62 | )) 63 | //x_32 := Cat(Fill(99,multiplicand(31)),multiplicand(31,0)) 64 | //y_32 := Cat(Cat(Fill(34,multiplier(31)),multiplier(31,0)),0.U(1.W)) 65 | 66 | //booth_x := Mux(io.i_mulw, x_32, x_64) 67 | //booth_y := Mux(io.i_mulw, y_32, y_64) 68 | booth_x := x_64 69 | booth_y := y_64 70 | 71 | val partial_products_gen = Module(new Partial_Products_Gen()) 72 | val wallace = Module(new Wallace_Tree()) 73 | 74 | partial_products_gen.io.i_x := booth_x 75 | partial_products_gen.io.i_y := booth_y 76 | partial_products := partial_products_gen.io.o_partial_products 77 | 78 | val cout = Wire(UInt(131.W)) 79 | val sout = Wire(UInt(131.W)) 80 | 81 | wallace.io.i_partial_products := partial_products 82 | cout := wallace.io.o_c 83 | sout := wallace.io.o_s 84 | 85 | val sum = Wire(UInt(131.W)) 86 | sum := (cout<<1) + sout 87 | 88 | when(io.i_mulw){ 89 | io.o_result_hi := Fill(64,sum(31)) 90 | io.o_result_lo := Cat(Fill(32,sum(31)),sum(31,0)) 91 | }.otherwise{ 92 | io.o_result_hi := sum(127,64) 93 | io.o_result_lo := sum(63,0) 94 | } 95 | } -------------------------------------------------------------------------------- /src/test/scala/ladder/consts.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | 12 | trait params{ 13 | def ROB_size =8 14 | def rob_idx_len = (log2Ceil(ROB_size)+1) 15 | require(isPow2(ROB_size)) 16 | } 17 | trait consts{ 18 | def RS_size =8 19 | def rs_idx_len = log2Ceil(RS_size) 20 | require(isPow2(RS_size)) 21 | 22 | def ROB_size =8 23 | def rob_idx_len = (log2Ceil(ROB_size)+1) 24 | require(isPow2(ROB_size)) 25 | 26 | def X = BitPat("b?") 27 | def N = BitPat("b0") 28 | def Y = BitPat("b1") 29 | //SRC_TYPE 30 | val SRC_RS = 0.U(3.W) 31 | val SRC_ZERO = 1.U(3.W) 32 | val SRC_PC = 2.U(3.W) 33 | val SRC_IMM = 3.U(3.W) 34 | val SRC_N = 4.U(3.W) 35 | 36 | //Funtion_Code 37 | val FU_ALU = 1.U(7.W) 38 | val FU_BRU = 2.U(7.W) 39 | val FU_MEM = 4.U(7.W) 40 | val FU_MUL = 8.U(7.W) 41 | val FU_DIV = 16.U(7.W) 42 | val FU_CSR = 32.U(7.W) 43 | val FU_NUL = 64.U(7.W) 44 | 45 | //BRANCH_TYPE 46 | val BR_N = 0.U(4.W)//none 47 | val BR_NE = 1.U(4.W) 48 | val BR_EQ = 2.U(4.W) 49 | val BR_GE = 3.U(4.W) 50 | val BR_GEU = 4.U(4.W) 51 | val BR_LT = 5.U(4.W) 52 | val BR_LTU = 6.U(4.W) 53 | val BR_J = 7.U(4.W) 54 | val BR_JR = 8.U(4.W) 55 | 56 | //Mem_Type 57 | val MEM_N = 0.U(3.W) 58 | val MEM_W = 1.U(3.W) 59 | val MEM_R = 2.U(3.W) 60 | val MEM_FENCEI = 3.U(3.W) 61 | 62 | //INST_TYPE 63 | val R_TYPE = 0.U(7.W) 64 | val I_TYPE = 1.U(7.W) 65 | val S_TYPE = 2.U(7.W) 66 | val B_TYPE = 3.U(7.W) 67 | val U_TYPE = 4.U(7.W) 68 | val J_TYPE = 5.U(7.W) 69 | val N_TYPE = 6.U(7.W) 70 | 71 | //CSR_SEL 72 | //this is multiplexed with ALU_SEL 73 | //TODO:rename this field to operate_code ,not alu_sel 74 | val CSR_NON = 0.U(5.W) 75 | val CSR_CSRRC = 1.U(5.W) 76 | val CSR_CSRRW = 2.U(5.W) 77 | val CSR_CSRRS = 3.U(5.W) 78 | val CSR_ECALL = 4.U(5.W) 79 | val CSR_MRET = 5.U(5.W) 80 | val CSR_EBREAK = 6.U(5.W) 81 | //ALU_SEL 82 | /* 83 | val ALU_NONE = 0.U(4.W) 84 | val ALU_ADD = 1.U(4.W) 85 | val ALU_SUB = 2.U(4.W) 86 | 87 | val ALU_AND = 3.U(4.W) 88 | val ALU_OR = 4.U(4.W) 89 | val ALU_XOR = 5.U(4.W) 90 | 91 | val ALU_SL = 6.U(4.W) 92 | val ALU_SRL = 7.U(4.W) 93 | val ALU_SRA = 8.U(4.W) 94 | 95 | val ALU_SLT = 9.U(4.W) 96 | val ALU_SLTU = 10.U(4.W) 97 | */ 98 | val ALU_NONE = 0.U(5.W) 99 | val ALU_AUIPC = 1.U(5.W) 100 | val ALU_ADDI = 2.U(5.W) 101 | val ALU_SLTI = 3.U(5.W) 102 | val ALU_SLTIU = 4.U(5.W) 103 | val ALU_XORI = 5.U(5.W) 104 | val ALU_ORI = 6.U(5.W) 105 | val ALU_ANDI = 7.U(5.W) 106 | val ALU_ADDIW = 8.U(5.W) 107 | val ALU_SLLI = 9.U(5.W) 108 | val ALU_SRLI = 10.U(5.W) 109 | val ALU_SRAI = 11.U(5.W) 110 | val ALU_SLLIW = 12.U(5.W) 111 | val ALU_SRLIW = 13.U(5.W) 112 | val ALU_SRAIW = 14.U(5.W) 113 | val ALU_ADD = 15.U(5.W) 114 | val ALU_SUB = 16.U(5.W) 115 | val ALU_SLL = 17.U(5.W) 116 | val ALU_SLT = 18.U(5.W) 117 | val ALU_SLTU = 19.U(5.W) 118 | val ALU_XOR = 20.U(5.W) 119 | val ALU_SRL = 21.U(5.W) 120 | val ALU_SRA = 22.U(5.W) 121 | val ALU_OR = 23.U(5.W) 122 | val ALU_AND = 24.U(5.W) 123 | val ALU_ADDW = 25.U(5.W) 124 | val ALU_SUBW = 26.U(5.W) 125 | val ALU_SLLW = 27.U(5.W) 126 | val ALU_SRLW = 28.U(5.W) 127 | val ALU_SRAW = 29.U(5.W) 128 | val ALU_LUI = 30.U(5.W) 129 | } 130 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/diff.txt: -------------------------------------------------------------------------------- 1 | Date : 2023-02-02 16:39:50 2 | Directory : d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl 3 | Total : 10 files, 359 codes, 0 comments, 0 blanks, all 359 lines 4 | 5 | Languages 6 | +----------+------------+------------+------------+------------+------------+ 7 | | language | files | code | comment | blank | total | 8 | +----------+------------+------------+------------+------------+------------+ 9 | | Verilog | 9 | 222 | 0 | 0 | 222 | 10 | | JSON | 1 | 137 | 0 | 0 | 137 | 11 | +----------+------------+------------+------------+------------+------------+ 12 | 13 | Directories 14 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 15 | | path | files | code | comment | blank | total | 16 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 17 | | . | 10 | 359 | 0 | 0 | 359 | 18 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 19 | 20 | Files 21 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ 22 | | filename | language | code | comment | blank | total | 23 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ 24 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v | Verilog | 5 | 0 | 0 | 5 | 25 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v | Verilog | 22 | 0 | 0 | 22 | 26 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v | Verilog | 4 | 0 | 0 | 4 | 27 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v | Verilog | 8 | 0 | 0 | 8 | 28 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v | Verilog | 24 | 0 | 0 | 24 | 29 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v | Verilog | 22 | 0 | 0 | 22 | 30 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v | Verilog | 2 | 0 | 0 | 2 | 31 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json | JSON | 137 | 0 | 0 | 137 | 32 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v | Verilog | 33 | 0 | 0 | 33 | 33 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v | Verilog | 102 | 0 | 0 | 102 | 34 | | Total | | 359 | 0 | 0 | 359 | 35 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/diff.txt: -------------------------------------------------------------------------------- 1 | Date : 2023-02-02 13:59:40 2 | Directory : d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl 3 | Total : 10 files, 17700 codes, 1 comments, 2 blanks, all 17703 lines 4 | 5 | Languages 6 | +----------+------------+------------+------------+------------+------------+ 7 | | language | files | code | comment | blank | total | 8 | +----------+------------+------------+------------+------------+------------+ 9 | | JSON | 1 | 17,570 | 0 | 0 | 17,570 | 10 | | Verilog | 9 | 130 | 1 | 2 | 133 | 11 | +----------+------------+------------+------------+------------+------------+ 12 | 13 | Directories 14 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 15 | | path | files | code | comment | blank | total | 16 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 17 | | . | 10 | 17,700 | 1 | 2 | 17,703 | 18 | +---------------------------------------------------------------------------------------------------+------------+------------+------------+------------+------------+ 19 | 20 | Files 21 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ 22 | | filename | language | code | comment | blank | total | 23 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ 24 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v | Verilog | -2 | 0 | 0 | -2 | 25 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v | Verilog | 16 | 0 | 0 | 16 | 26 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v | Verilog | 4 | 0 | 0 | 4 | 27 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v | Verilog | -24 | 0 | 0 | -24 | 28 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v | Verilog | -26 | 0 | 0 | -26 | 29 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Interrupt_Mask.v | Verilog | 79 | 1 | 1 | 81 | 30 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v | Verilog | 18 | 0 | 0 | 18 | 31 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json | JSON | 17,570 | 0 | 0 | 17,570 | 32 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v | Verilog | 167 | 0 | 1 | 168 | 33 | | d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v | Verilog | -102 | 0 | 0 | -102 | 34 | | Total | | 17,700 | 1 | 2 | 17,703 | 35 | +---------------------------------------------------------------------------------------------------+----------+------------+------------+------------+------------+ -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/branch_presolve.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | //TODO: debug branchpresolvepack, add taken,remove target 11 | //no its actually specify the case that its not a branch but predicted as a branch and taken, and modify pcgen accordingly 12 | class Branch_Presolve extends Module{ 13 | val io=IO(new Bundle{ 14 | val i_fetch_pack = Input(new fetch_pack()) 15 | val o_branch_presolve_pack = Output(new branch_presolve_pack()) 16 | }) 17 | val branch_decoder0 =decoder(QMCMinimizer,io.i_fetch_pack.insts(0), 18 | TruthTable(Seq( 19 | BitPat("b?????????????????000?????1100011") -> BitPat("b0100"),//BEQ 20 | BitPat("b?????????????????001?????1100011") -> BitPat("b0100"),//BNE 21 | BitPat("b?????????????????100?????1100011") -> BitPat("b0100"),//BLT 22 | BitPat("b?????????????????101?????1100011") -> BitPat("b0100"),//BGE 23 | BitPat("b?????????????????110?????1100011") -> BitPat("b0100"),//BLTU 24 | BitPat("b?????????????????111?????1100011") -> BitPat("b0100"),//BGEU 25 | BitPat("b?????????????????000?????1100111") -> BitPat("b1000"),//JALR 26 | BitPat("b?????????????????????????1101111") -> BitPat("b1000"),//JAL 27 | //BitPat("b00110000001000000000000000000000") -> BitPat("b0010"),//MRET 28 | ), BitPat("b0000"))) 29 | 30 | val branch_decoder1 = decoder(QMCMinimizer , io.i_fetch_pack.insts(1) , TruthTable 31 | ( 32 | Seq( 33 | BitPat("b?????????????????000?????1100011") -> BitPat("b0100"),//BEQ 34 | BitPat("b?????????????????001?????1100011") -> BitPat("b0100"),//BNE 35 | BitPat("b?????????????????100?????1100011") -> BitPat("b0100"),//BLT 36 | BitPat("b?????????????????101?????1100011") -> BitPat("b0100"),//BGE 37 | BitPat("b?????????????????110?????1100011") -> BitPat("b0100"),//BLTU 38 | BitPat("b?????????????????111?????1100011") -> BitPat("b0100"),//BGEU 39 | BitPat("b?????????????????000?????1100111") -> BitPat("b1000"),//JALR 40 | BitPat("b?????????????????????????1101111") -> BitPat("b1000"),//JAL 41 | //BitPat("b00110000001000000000000000000000") -> BitPat("b0010")//MRET how to add this and ecall 42 | ), BitPat("b0000"))//BitPat.dontCare(4)) 43 | ) 44 | val br0 = branch_decoder0(0) || branch_decoder0(1) || branch_decoder0(2) || branch_decoder0(3) 45 | val br1 = branch_decoder1(0) || branch_decoder1(1) || branch_decoder1(2) || branch_decoder1(3) 46 | //branch_presolve_valid is mispred, only when mispred a non-br to a br, and taken was predicted, presolve is valid. 47 | //another case of mispred a br to a non-br can't resolve by presolve if it's really going to take the branch, 48 | //and according to the bpu policy of only write btb on a branch taken, this case will be ignored now. 49 | //other cases actually would not cause a control flow redirect, so will be ignored 50 | io.o_branch_presolve_pack.valid := (io.i_fetch_pack.valids(0) && !br0 && io.i_fetch_pack.branch_predict_pack.valid && 51 | io.i_fetch_pack.branch_predict_pack.taken && io.i_fetch_pack.branch_predict_pack.select === 0.U) || 52 | (io.i_fetch_pack.valids(1) && !br1 && io.i_fetch_pack.branch_predict_pack.valid && 53 | io.i_fetch_pack.branch_predict_pack.taken && io.i_fetch_pack.branch_predict_pack.select === 1.U) 54 | io.o_branch_presolve_pack.pc := Cat(io.i_fetch_pack.pc(63,3),0.U(3.W)) + Mux((io.i_fetch_pack.valids(0) && !br0 && io.i_fetch_pack.branch_predict_pack.valid && 55 | io.i_fetch_pack.branch_predict_pack.taken && io.i_fetch_pack.branch_predict_pack.select === 0.U),0.U,4.U) 56 | io.o_branch_presolve_pack.taken := io.i_fetch_pack.branch_predict_pack.taken // this field seems to be redundent 57 | } 58 | -------------------------------------------------------------------------------- /csrc/devices.cpp: -------------------------------------------------------------------------------- 1 | /*************************************************************************************** 2 | * Copyright (c) 2014-2022 Zihao Yu, Nanjing University 3 | * 4 | * NEMU is licensed under Mulan PSL v2. 5 | * You can use this software according to the terms and conditions of the Mulan PSL v2. 6 | * You may obtain a copy of Mulan PSL v2 at: 7 | * http://license.coscl.org.cn/MulanPSL2 8 | * 9 | * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10 | * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11 | * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12 | * 13 | * See the Mulan PSL v2 for more details. 14 | ***************************************************************************************/ 15 | #define KEYDOWN_MASK 0x8000 16 | #define concat_temp(x, y) x ## y 17 | #define concat(x, y) concat_temp(x, y) 18 | #define MAP(c, f) c(f) 19 | 20 | #include 21 | #include 22 | #include "devices.h" 23 | 24 | // Note that this is not the standard 25 | #define _KEYS(f) \ 26 | f(ESCAPE) f(F1) f(F2) f(F3) f(F4) f(F5) f(F6) f(F7) f(F8) f(F9) f(F10) f(F11) f(F12) \ 27 | f(GRAVE) f(1) f(2) f(3) f(4) f(5) f(6) f(7) f(8) f(9) f(0) f(MINUS) f(EQUALS) f(BACKSPACE) \ 28 | f(TAB) f(Q) f(W) f(E) f(R) f(T) f(Y) f(U) f(I) f(O) f(P) f(LEFTBRACKET) f(RIGHTBRACKET) f(BACKSLASH) \ 29 | f(CAPSLOCK) f(A) f(S) f(D) f(F) f(G) f(H) f(J) f(K) f(L) f(SEMICOLON) f(APOSTROPHE) f(RETURN) \ 30 | f(LSHIFT) f(Z) f(X) f(C) f(V) f(B) f(N) f(M) f(COMMA) f(PERIOD) f(SLASH) f(RSHIFT) \ 31 | f(LCTRL) f(APPLICATION) f(LALT) f(SPACE) f(RALT) f(RCTRL) \ 32 | f(UP) f(DOWN) f(LEFT) f(RIGHT) f(INSERT) f(DELETE) f(HOME) f(END) f(PAGEUP) f(PAGEDOWN) 33 | 34 | #define _KEY_NAME(k) _KEY_##k, 35 | 36 | enum { 37 | _KEY_NONE = 0, 38 | MAP(_KEYS, _KEY_NAME) 39 | }; 40 | 41 | #define SDL_KEYMAP(k) keymap[concat(SDL_SCANCODE_, k)] = concat(_KEY_, k); 42 | static uint32_t keymap[256] = {}; 43 | 44 | void init_keymap() { 45 | MAP(_KEYS, SDL_KEYMAP) 46 | } 47 | 48 | #define KEY_QUEUE_LEN 1024 49 | static int key_queue[KEY_QUEUE_LEN] = {}; 50 | static int key_f = 0, key_r = 0; 51 | 52 | static void key_enqueue(uint32_t am_scancode) { 53 | key_queue[key_r] = am_scancode; 54 | key_r = (key_r + 1) % KEY_QUEUE_LEN; 55 | assert(key_r != key_f); 56 | } 57 | 58 | uint32_t key_dequeue() { 59 | uint32_t key = _KEY_NONE; 60 | if (key_f != key_r) { 61 | key = key_queue[key_f]; 62 | key_f = (key_f + 1) % KEY_QUEUE_LEN; 63 | } 64 | return key; 65 | } 66 | 67 | void send_key(uint8_t scancode, bool is_keydown) { 68 | //printf("send key\n"); 69 | if (keymap[scancode] != _KEY_NONE) { 70 | uint32_t am_scancode = keymap[scancode] | (is_keydown ? KEYDOWN_MASK : 0); 71 | key_enqueue(am_scancode); 72 | } 73 | } 74 | 75 | void kbd_update() { 76 | 77 | SDL_Event event; 78 | while (SDL_PollEvent(&event)) { 79 | switch (event.type) { 80 | case SDL_KEYDOWN: 81 | case SDL_KEYUP: { 82 | uint8_t k = event.key.keysym.scancode; 83 | bool is_keydown = (event.key.type == SDL_KEYDOWN); 84 | send_key(k, is_keydown); 85 | break; 86 | } 87 | 88 | default: break; 89 | } 90 | } 91 | } 92 | //---------------------VGA----------------------------- 93 | #define SCREEN_W 400 94 | #define SCREEN_H 300 95 | char *vmem=new char[SCREEN_H*SCREEN_W*4]; 96 | 97 | uint8_t *vga_sync = new uint8_t(); 98 | 99 | static SDL_Renderer *renderer = NULL; 100 | static SDL_Texture *texture = NULL; 101 | 102 | void init_screen() { 103 | SDL_Window *window = NULL; 104 | char title[128]; 105 | sprintf(title,"RISCV64-NPC"); 106 | SDL_Init(SDL_INIT_VIDEO); 107 | SDL_CreateWindowAndRenderer( 108 | SCREEN_W, 109 | SCREEN_H, 110 | 0, &window, &renderer); 111 | SDL_SetWindowTitle(window, title); 112 | texture = SDL_CreateTexture(renderer, SDL_PIXELFORMAT_ARGB8888, 113 | SDL_TEXTUREACCESS_STATIC, SCREEN_W, SCREEN_H); 114 | } 115 | 116 | void update_screen() { 117 | SDL_UpdateTexture(texture, NULL, vmem, SCREEN_W * sizeof(uint32_t)); 118 | SDL_RenderClear(renderer); 119 | SDL_RenderCopy(renderer, texture, NULL, NULL); 120 | SDL_RenderPresent(renderer); 121 | } 122 | 123 | void vga_update_screen() { 124 | if(*vga_sync){ 125 | update_screen(); 126 | *vga_sync=0; 127 | } 128 | } 129 | -------------------------------------------------------------------------------- /verilogtestbench/tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define RANDOMIZE_REG_INIT 3 | `define RANDOMIZE_MEM_INIT 4 | `define RANDOMIZE_GARBAGE_ASSIGN 5 | `define RANDOMIZE_INVALID_ASSIGN 6 | 7 | module back_end; 8 | // Inputs 9 | reg clk; 10 | reg resetn; 11 | 12 | reg fetch_pack_valid; 13 | reg [63:0] pc; 14 | reg [31:0] insts_0; 15 | reg [31:0] insts_1; 16 | reg branch_predict_pack_valid; 17 | reg [63:0] branch_predict_pack_target; 18 | reg branch_predict_pack_select; 19 | reg branch_predict_pack_taken; 20 | reg [3:0] branch_predict_pack_branch_type; 21 | reg fetch_pack_valid0; 22 | reg fetch_pack_valid1; 23 | 24 | reg dcache_io_valid; 25 | reg [63:0] dcache_io_MdataIn; 26 | 27 | reg i_interrupt; 28 | 29 | // Instantiate the Unit Under Test (UUT) 30 | Back_End_With_Decode uut ( 31 | .clock(clk), 32 | .reset(!resetn), 33 | .io_i_fetch_pack_valid(fetch_pack_valid), 34 | .io_i_fetch_pack_bits_pc(pc), 35 | .io_i_fetch_pack_bits_insts_0(insts_0), 36 | .io_i_fetch_pack_bits_insts_1(insts_1), 37 | 38 | .io_i_fetch_pack_bits_branch_predict_pack_valid(branch_predict_pack_valid), 39 | .io_i_fetch_pack_bits_branch_predict_pack_target(branch_predict_pack_target), 40 | .io_i_fetch_pack_bits_branch_predict_pack_branch_type(branch_predict_pack_branch_type), 41 | .io_i_fetch_pack_bits_branch_predict_pack_select(branch_predict_pack_selec), 42 | .io_i_fetch_pack_bits_branch_predict_pack_taken(branch_predict_pack_taken), 43 | 44 | .io_i_interrupt(i_interrupt), 45 | .io_i_fetch_pack_bits_valids_0(fetch_pack_valid0), 46 | .io_i_fetch_pack_bits_valids_1(fetch_pack_valid1), 47 | 48 | .io_dcache_io_data_valid(dcache_io_valid), 49 | .io_dcache_io_addr_ready(dcache_io_valid), 50 | .io_dcache_io_MdataIn(dcache_io_MdataIn) 51 | ); 52 | 53 | initial begin 54 | // Initialize Inputs 55 | clk = 0; 56 | resetn = 0; 57 | 58 | i_interrupt = 1'b0; 59 | fetch_pack_valid0 = 1'b0; 60 | fetch_pack_valid1 = 1'b0; 61 | fetch_pack_valid = 1'b0; 62 | pc = 64'h00000000; 63 | insts_0 = 32'h00000000; 64 | insts_1 = 32'h00000000; 65 | 66 | branch_predict_pack_valid = 1'b0; 67 | branch_predict_pack_target = 64'b0; 68 | branch_predict_pack_select = 1'b0 ; 69 | branch_predict_pack_taken = 1'b0; 70 | branch_predict_pack_branch_type= 4'b0; 71 | 72 | dcache_io_valid = 1'b0; 73 | dcache_io_MdataIn = 64'h0000000000000000; 74 | 75 | #10; 76 | fetch_pack_valid = 1'b1; 77 | pc = 64'h00000004; 78 | fetch_pack_valid0 = 1'b1; 79 | fetch_pack_valid1 = 1'b1; 80 | fetch_pack_valid = 1'b1; 81 | insts_0 = 32'h00508093; //x1=5 82 | //insts_1 = 32'h0030a2a3; //x3 = 内存5 83 | insts_1 = 32'h0030a2a3; //x3 = 内存5 84 | 85 | #100; 86 | resetn = 1; 87 | #10 88 | fetch_pack_valid1 = 1'b0; 89 | insts_0 = 32'h0030a2a3; 90 | #10 91 | fetch_pack_valid0 = 1'b0; 92 | fetch_pack_valid1 = 1'b0; 93 | fetch_pack_valid = 1'b0; 94 | #70 95 | i_interrupt = 1'b1; 96 | #10 97 | branch_predict_pack_valid = 1'b0; 98 | fetch_pack_valid0 = 1'b0; 99 | fetch_pack_valid1 = 1'b0; 100 | fetch_pack_valid = 1'b0; 101 | #200; 102 | //should stuck on insts1 103 | dcache_io_MdataIn = 64'h0000000000004321; 104 | dcache_io_valid = 1'b1; 105 | 106 | //passed 107 | 108 | /* 109 | #10; 110 | insts_0 = 32'h34109173; 111 | insts_1 = 32'h3411a173; 112 | 113 | #10 114 | insts_0=32'h30200073;//mret ,redirect to pc=15 115 | insts_1=32'h3410b273;//should be flushed 116 | //insts_1=32'h30200073; 117 | //should all be flushed 118 | #10; 119 | insts_0 = 32'h34109173; 120 | insts_1 = 32'h3411a173; 121 | 122 | #10 123 | insts_0=32'h30200073;//mret ,redirect to pc=15 124 | insts_1=32'h3410b273;//should be flushed 125 | //insts_1=32'h30200073; 126 | */ 127 | #10 128 | fetch_pack_valid = 1'b0; 129 | 130 | #200 131 | $finish(1); 132 | end 133 | always #5 clk = ~clk; 134 | 135 | endmodule -------------------------------------------------------------------------------- /vsrc/dpi-funcs.v1: -------------------------------------------------------------------------------- 1 | import "DPI-C" function void set_gpr_ptr(input logic [63:0] a []); 2 | import "DPI-C" function void pmem_read_dpi(input longint raddr, output longint rdata); 3 | import "DPI-C" function void pmem_write_dpi(input longint waddr, input longint wdata, input byte wmask); 4 | 5 | module automatic dpic 6 | ( 7 | input wire clk, 8 | input wire stop, 9 | 10 | //regfile dpi 11 | input wire[63:0] regs0, 12 | input wire[63:0] regs1, 13 | input wire[63:0] regs2, 14 | input wire[63:0] regs3, 15 | input wire[63:0] regs4, 16 | input wire[63:0] regs5, 17 | input wire[63:0] regs6, 18 | input wire[63:0] regs7, 19 | input wire[63:0] regs8, 20 | input wire[63:0] regs9, 21 | input wire[63:0] regs10, 22 | input wire[63:0] regs11, 23 | input wire[63:0] regs12, 24 | input wire[63:0] regs13, 25 | input wire[63:0] regs14, 26 | input wire[63:0] regs15, 27 | input wire[63:0] regs16, 28 | input wire[63:0] regs17, 29 | input wire[63:0] regs18, 30 | input wire[63:0] regs19, 31 | input wire[63:0] regs20, 32 | input wire[63:0] regs21, 33 | input wire[63:0] regs22, 34 | input wire[63:0] regs23, 35 | input wire[63:0] regs24, 36 | input wire[63:0] regs25, 37 | input wire[63:0] regs26, 38 | input wire[63:0] regs27, 39 | input wire[63:0] regs28, 40 | input wire[63:0] regs29, 41 | input wire[63:0] regs30, 42 | input wire[63:0] regs31, 43 | 44 | //dcache 45 | output data_valid, 46 | input data_ready, 47 | input addr_valid, 48 | output addr_ready, 49 | 50 | input Mwout, 51 | input [63:0] Maddr, 52 | input Men, 53 | input [31:0] Mlen, 54 | output [63:0] MdataIn, 55 | input [63:0] MdataOut 56 | ); 57 | 58 | wire[63:0] regs[0:31]; 59 | 60 | assign regs[0] = regs0; 61 | assign regs[1] = regs1; 62 | assign regs[2] = regs2; 63 | assign regs[3] = regs3; 64 | assign regs[4] = regs4; 65 | assign regs[5] = regs5; 66 | assign regs[6] = regs6; 67 | assign regs[7] = regs7; 68 | assign regs[8] = regs8; 69 | assign regs[9] = regs9; 70 | assign regs[10] = regs10; 71 | assign regs[11] = regs11; 72 | assign regs[12] = regs12; 73 | assign regs[13] = regs13; 74 | assign regs[14] = regs14; 75 | assign regs[15] = regs15; 76 | assign regs[16] = regs16; 77 | assign regs[17] = regs17; 78 | assign regs[18] = regs18; 79 | assign regs[19] = regs19; 80 | assign regs[20] = regs20; 81 | assign regs[21] = regs21; 82 | assign regs[22] = regs22; 83 | assign regs[23] = regs23; 84 | assign regs[24] = regs24; 85 | assign regs[25] = regs25; 86 | assign regs[26] = regs26; 87 | assign regs[27] = regs27; 88 | assign regs[28] = regs28; 89 | assign regs[29] = regs29; 90 | assign regs[30] = regs30; 91 | assign regs[31] = regs31; 92 | 93 | initial set_gpr_ptr(regs); // rf为通用寄存器的二维数组变量 94 | 95 | export "DPI-C" function Check; 96 | function bit Check(); 97 | return stop; 98 | endfunction 99 | 100 | reg [7:0] wmask; 101 | 102 | always @(*) begin 103 | case(Mlen) 104 | 1: wmask = 8'h01; 105 | 2: wmask = 8'h03; 106 | 4: wmask = 8'h0f; 107 | 8: wmask = 8'hff; 108 | default: assign wmask = 8'h00; 109 | endcase 110 | end 111 | 112 | //we are setting 3 cycles of mem delay 113 | reg [63:0] mem_buf0; 114 | reg [63:0] mem_buf1; 115 | reg [63:0] mem_buf2; 116 | 117 | reg mem_req0; 118 | reg mem_req1; 119 | reg mem_req2; 120 | 121 | always @(posedge clk) begin 122 | mem_buf2 = mem_buf1; 123 | mem_buf1 = mem_buf0; 124 | 125 | mem_req2 = mem_req1; 126 | mem_req1 = mem_req0; 127 | end 128 | 129 | //assign data_valid = mem_req2; 130 | assign data_valid = mem_req0; 131 | assign addr_ready = 1'b1; 132 | 133 | //assign MdataIn = mem_buf2; 134 | assign MdataIn = mem_buf0; 135 | 136 | always @(posedge clk) begin 137 | if(Men && !Mwout && addr_valid) begin 138 | pmem_read_dpi(Maddr, mem_buf0); 139 | mem_req0 = 1'b1; 140 | end else if(Men && Mwout && addr_valid && data_ready)begin 141 | pmem_write_dpi(Maddr, MdataOut,wmask); 142 | mem_req0 = 1'b0;//only mem read need to wait for data valid, mem write just pass. 143 | //and mem_req 4 write must not be 1 since it will influce the 144 | //data valid signal later 145 | end else begin 146 | mem_buf0 = 64'b0; 147 | mem_req0 = 1'b0; 148 | end 149 | 150 | end 151 | 152 | endmodule 153 | -------------------------------------------------------------------------------- /src/test/scala/ladder/front_end/front_end.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Front_End extends Module 12 | { 13 | val io = IO(new Bundle{ 14 | //connect icache 15 | val icache_io = new IcacheIO() 16 | 17 | //from back_end 18 | val i_branch_resolve_pack = Input(new branch_resolve_pack()) 19 | //val i_back_end_stall = Input(new Bool())// this is kinda unessesary 20 | 21 | val i_pc_redirect_valid = Input(new Bool()) 22 | val i_pc_redirect_target = Input(UInt(64.W)) 23 | 24 | //to back_end 25 | val o_fetch_pack = Decoupled(new fetch_pack()) 26 | }) 27 | val pc_gen = Module(new PC_Gen()) 28 | val bpu = Module(new BPU()) 29 | val if1_if2 = Module(new IF1_IF2()) 30 | val if2_if3 = Module(new IF2_IF3()) 31 | val branch_presolve = Module(new Branch_Presolve()) 32 | val fetch_queue = Module(new Fetch_Queue()) 33 | val front_end_control = Module(new front_end_control()) 34 | val fetch_res = Module(new Fetch_Res()) 35 | 36 | /*fetch control*/ 37 | front_end_control.io.i_pc_redirect_valid := io.i_pc_redirect_valid 38 | front_end_control.io.i_icache_addr_ready := io.icache_io.i_addr_ready 39 | front_end_control.io.i_icache_data_valid := io.icache_io.i_data_valid 40 | front_end_control.io.i_branch_presolve_pack := branch_presolve.io.o_branch_presolve_pack 41 | front_end_control.io.i_branch_resolve_pack := io.i_branch_resolve_pack 42 | front_end_control.io.i_fetch_queue_full := fetch_queue.io.full 43 | 44 | 45 | /*stage 1 : fetch and predict*/ 46 | pc_gen.io.i_stall := front_end_control.io.o_stage1_stall 47 | pc_gen.io.i_pc_redirect_valid := io.i_pc_redirect_valid 48 | pc_gen.io.i_pc_redirect_target := io.i_pc_redirect_target 49 | pc_gen.io.i_branch_predict_pack := bpu.io.o_branch_predict_pack 50 | pc_gen.io.i_branch_presolve_pack := branch_presolve.io.o_branch_presolve_pack 51 | pc_gen.io.i_branch_resolve_pack := io.i_branch_resolve_pack 52 | 53 | io.icache_io.o_wen := false.B 54 | io.icache_io.o_addr := Cat(pc_gen.io.o_pc(63,3),0.U(3.W)) 55 | io.icache_io.o_addr_valid := front_end_control.io.o_stage1_stall 56 | //io.icache_io.o_rwen := pc_gen.io.o_stage1_flush 57 | io.icache_io.o_stall1 := front_end_control.io.o_stage1_stall||front_end_control.io.o_stage1_flush 58 | io.icache_io.o_stall2 := front_end_control.io.o_stage2_stall||front_end_control.io.o_stage1_flush 59 | 60 | bpu.io.i_addr := pc_gen.io.o_pc 61 | bpu.io.i_branch_presolve_pack := branch_presolve.io.o_branch_presolve_pack 62 | bpu.io.i_branch_resolve_pack := io.i_branch_resolve_pack 63 | 64 | /*stage 1 and stage 2*/ 65 | if1_if2.io.i_stall := front_end_control.io.o_stage1_stall 66 | if1_if2.io.i_flush := front_end_control.io.o_stage1_flush 67 | if1_if2.io.i_pc := pc_gen.io.o_pc 68 | if1_if2.io.i_branch_predict_pack := bpu.io.o_branch_predict_pack 69 | 70 | /*stage 2 : fetching, and generate predict (1cycle delayed)*/ 71 | 72 | /*stage 2 and stage 3*/ 73 | if2_if3.io.i_stall := front_end_control.io.o_stage2_stall 74 | if2_if3.io.i_flush := front_end_control.io.o_stage2_flush //|| !if1_if2.io.o_fetch_valid 75 | if2_if3.io.i_pc := if1_if2.io.o_pc 76 | if2_if3.io.i_branch_predict_pack := if1_if2.io.o_branch_predict_pack 77 | if2_if3.io.i_fetch_valid := if1_if2.io.o_fetch_valid 78 | 79 | /*stage 3 : fetch to fetch queue, presolve branch*/ 80 | branch_presolve.io.i_fetch_pack := fetch_res.io.o_fetch_pack.bits 81 | fetch_res.io.o_fetch_pack.ready := true.B //this is ugly, remove this decouple later 82 | 83 | fetch_res.io.i_pc := if2_if3.io.o_pc 84 | fetch_res.io.i_flush := front_end_control.io.o_fetch_queue_flush || !if2_if3.io.o_fetch_valid 85 | fetch_res.io.i_stall := front_end_control.io.o_stage2_stall//this port and flush port is used to prevent write fetchqueue 86 | fetch_res.io.i_branch_presolve_pack := branch_presolve.io.o_branch_presolve_pack 87 | fetch_res.io.i_fetch_res := io.icache_io.i_data 88 | fetch_res.io.i_branch_predict_pack := if2_if3.io.o_branch_predict_pack 89 | 90 | fetch_queue.io.in <> fetch_res.io.o_fetch_pack_with_presolve 91 | fetch_queue.io.i_flush := front_end_control.io.o_fetch_queue_flush 92 | 93 | /*connect to back_end*/ 94 | io.o_fetch_pack <> fetch_queue.io.out 95 | } 96 | 97 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-39/results.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\ALU.v", "Verilog", 349, 0, 1, 1, 351 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Arch_RegFile.v", "Verilog", 4259, 0, 0, 1, 4260 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BPU.v", "Verilog", 56061, 0, 1, 1, 56063 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", 312, 0, 1, 1, 314 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.anno.json", "JSON", 0, 17589, 0, 0, 17589 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 2556, 0, 0, 1, 2557 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Branch_Presolve.v", "Verilog", 61, 0, 0, 1, 62 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Busy_Table.v", "Verilog", 565, 0, 1, 1, 567 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR.v", "Verilog", 239, 0, 1, 1, 241 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR_BF.v", "Verilog", 197, 0, 1, 1, 199 12 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\DIV.v", "Verilog", 255, 0, 1, 1, 257 13 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v", "Verilog", 1740, 0, 1, 1, 1742 14 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Dispatch.v", "Verilog", 635, 0, 1, 1, 637 15 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Divider.v", "Verilog", 173, 0, 1, 1, 175 16 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 1251, 0, 0, 1, 1252 17 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", 102, 0, 0, 1, 103 18 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Res.v", "Verilog", 30, 0, 0, 1, 31 19 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.anno.json", "JSON", 0, 32, 0, 0, 32 20 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", 378, 0, 0, 1, 379 21 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Full_Adder.v", "Verilog", 10, 0, 0, 1, 11 22 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF1_IF2.v", "Verilog", 120, 0, 1, 1, 122 23 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF2_IF3.v", "Verilog", 121, 0, 1, 1, 123 24 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 282, 0, 1, 1, 284 25 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\MUL.v", "Verilog", 268, 0, 1, 1, 270 26 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Multiplier.v", "Verilog", 238, 0, 1, 1, 240 27 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\PC_Gen.v", "Verilog", 85, 0, 1, 1, 87 28 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Partial_Products_Gen.v", "Verilog", 958, 0, 0, 1, 959 29 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", 353, 0, 1, 1, 355 30 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\RegFile.v", "Verilog", 3149, 0, 1, 1, 3151 31 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename.v", "Verilog", 1017, 0, 1, 1, 1019 32 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename_Table.v", "Verilog", 1676, 0, 1, 1, 1678 33 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reorder_Buffer.v", "Verilog", 25665, 0, 1, 1, 25667 34 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station.v", "Verilog", 21036, 0, 1, 1, 21038 35 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station_Slot.v", "Verilog", 564, 0, 1, 1, 566 36 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree.v", "Verilog", 6091, 0, 0, 1, 6092 37 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree_Cell.v", "Verilog", 334, 0, 0, 1, 335 38 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\front_end_control.v", "Verilog", 25, 0, 0, 1, 26 39 | "Total", "-", 131155, 17621, 23, 35, 148834 -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/results.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\ALU.v", "Verilog", 349, 0, 1, 1, 351 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Arch_RegFile.v", "Verilog", 4259, 0, 0, 1, 4260 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BPU.v", "Verilog", 56061, 0, 1, 1, 56063 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", 312, 0, 1, 1, 314 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.anno.json", "JSON", 0, 17589, 0, 0, 17589 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 2556, 0, 0, 1, 2557 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Branch_Presolve.v", "Verilog", 61, 0, 0, 1, 62 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Busy_Table.v", "Verilog", 565, 0, 1, 1, 567 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR.v", "Verilog", 239, 0, 1, 1, 241 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR_BF.v", "Verilog", 197, 0, 1, 1, 199 12 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\DIV.v", "Verilog", 255, 0, 1, 1, 257 13 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v", "Verilog", 1740, 0, 1, 1, 1742 14 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Dispatch.v", "Verilog", 635, 0, 1, 1, 637 15 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Divider.v", "Verilog", 173, 0, 1, 1, 175 16 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 1251, 0, 0, 1, 1252 17 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", 102, 0, 0, 1, 103 18 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Res.v", "Verilog", 30, 0, 0, 1, 31 19 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.anno.json", "JSON", 0, 32, 0, 0, 32 20 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", 378, 0, 0, 1, 379 21 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Full_Adder.v", "Verilog", 10, 0, 0, 1, 11 22 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF1_IF2.v", "Verilog", 120, 0, 1, 1, 122 23 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF2_IF3.v", "Verilog", 121, 0, 1, 1, 123 24 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 282, 0, 1, 1, 284 25 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\MUL.v", "Verilog", 268, 0, 1, 1, 270 26 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Multiplier.v", "Verilog", 238, 0, 1, 1, 240 27 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\PC_Gen.v", "Verilog", 85, 0, 1, 1, 87 28 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Partial_Products_Gen.v", "Verilog", 958, 0, 0, 1, 959 29 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", 353, 0, 1, 1, 355 30 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\RegFile.v", "Verilog", 3149, 0, 1, 1, 3151 31 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename.v", "Verilog", 1017, 0, 1, 1, 1019 32 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename_Table.v", "Verilog", 1676, 0, 1, 1, 1678 33 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reorder_Buffer.v", "Verilog", 25665, 0, 1, 1, 25667 34 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station.v", "Verilog", 21036, 0, 1, 1, 21038 35 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station_Slot.v", "Verilog", 564, 0, 1, 1, 566 36 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree.v", "Verilog", 6091, 0, 0, 1, 6092 37 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree_Cell.v", "Verilog", 334, 0, 0, 1, 335 38 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\front_end_control.v", "Verilog", 25, 0, 0, 1, 26 39 | "Total", "-", 131155, 17621, 23, 35, 148834 -------------------------------------------------------------------------------- /verilogtestbench/front_end_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | `define RANDOMIZE_REG_INIT 3 | `define RANDOMIZE_MEM_INIT 4 | `define RANDOMIZE_GARBAGE_ASSIGN 5 | `define RANDOMIZE_INVALID_ASSIGN 6 | 7 | module front_end_tb; 8 | // Inputs 9 | reg clk; 10 | reg resetn; 11 | 12 | reg [63:0] io_icache_io_i_data; 13 | reg io_icache_io_i_data_valid; 14 | reg io_icache_io_i_addr_ready; 15 | reg io_i_branch_resolve_pack_valid; 16 | reg io_i_branch_resolve_pack_mispred; 17 | reg io_i_branch_resolve_pack_taken; 18 | reg [63:0] io_i_branch_resolve_pack_pc; 19 | reg [63:0] io_i_branch_resolve_pack_target; 20 | reg [7:0] io_i_branch_resolve_pack_rob_idx; 21 | reg io_i_branch_resolve_pack_prediction_valid; 22 | reg [2:0] io_i_branch_resolve_pack_branch_type; 23 | reg io_i_pc_redirect_valid; 24 | reg [63:0] io_i_pc_redirect_target; 25 | reg io_o_fetch_pack_ready; 26 | 27 | // Instantiate the Unit Under Test (UUT) 28 | Front_End uut ( 29 | .clock(clk), 30 | .reset(!resetn), 31 | .io_icache_io_i_data(io_icache_io_i_data), 32 | .io_icache_io_i_data_valid(io_icache_io_i_data_valid), 33 | .io_icache_io_i_addr_ready(io_icache_io_i_addr_ready), 34 | .io_i_branch_resolve_pack_valid(io_i_branch_resolve_pack_valid), 35 | .io_i_branch_resolve_pack_mispred(io_i_branch_resolve_pack_mispred), 36 | .io_i_branch_resolve_pack_taken(io_i_branch_resolve_pack_taken), 37 | .io_i_branch_resolve_pack_pc(io_i_branch_resolve_pack_pc), 38 | .io_i_branch_resolve_pack_target(io_i_branch_resolve_pack_target), 39 | .io_i_branch_resolve_pack_rob_idx(io_i_branch_resolve_pack_rob_idx), 40 | .io_i_branch_resolve_pack_prediction_valid(io_i_branch_resolve_pack_prediction_valid), 41 | .io_i_branch_resolve_pack_branch_type(io_i_branch_resolve_pack_branch_type), 42 | .io_i_pc_redirect_valid(io_i_pc_redirect_valid), 43 | .io_i_pc_redirect_target(io_i_pc_redirect_target), 44 | .io_o_fetch_pack_ready(io_o_fetch_pack_ready) 45 | ); 46 | 47 | initial begin 48 | // Initialize Inputs 49 | clk = 0; 50 | resetn = 0; 51 | 52 | io_icache_io_i_data=64'b0; 53 | io_icache_io_i_data_valid=1'b0; 54 | io_icache_io_i_addr_ready=1'b0; 55 | io_i_branch_resolve_pack_valid=1'b0; 56 | io_i_branch_resolve_pack_mispred=1'b0; 57 | io_i_branch_resolve_pack_taken=1'b0; 58 | io_i_branch_resolve_pack_pc=64'b0; 59 | io_i_branch_resolve_pack_target=64'b0; 60 | io_i_branch_resolve_pack_rob_idx=8'b0; 61 | io_i_branch_resolve_pack_prediction_valid=1'b0; 62 | io_i_branch_resolve_pack_branch_type=3'b0; 63 | io_i_pc_redirect_valid=1'b0; 64 | io_i_pc_redirect_target=64'b0; 65 | io_o_fetch_pack_ready=1'b0; 66 | 67 | #10; 68 | 69 | io_o_fetch_pack_ready = 1'b1; 70 | io_icache_io_i_addr_ready = 1'b1; 71 | #100; 72 | resetn = 1; 73 | 74 | #10; 75 | io_i_branch_resolve_pack_valid = 1'b1; 76 | io_i_branch_resolve_pack_mispred = 1'b0; 77 | io_i_branch_resolve_pack_taken = 1'b1; 78 | io_i_branch_resolve_pack_prediction_valid = 1'b1; 79 | io_i_branch_resolve_pack_pc = 64'h1230; 80 | io_i_branch_resolve_pack_target = 64'h5678; 81 | 82 | io_icache_io_i_data_valid = 1'b1; 83 | io_icache_io_i_data[31:0] = 32'h00510113; 84 | io_icache_io_i_data[63:32] = 32'h00510213; 85 | 86 | #10 87 | io_i_branch_resolve_pack_valid = 1'b0; 88 | io_icache_io_i_data[31:0] = 32'h00110233; 89 | io_icache_io_i_data[63:32] =32'h40110133; 90 | #20 91 | io_i_pc_redirect_valid = 1'b1; 92 | io_i_pc_redirect_target = 64'h8; 93 | #30 94 | io_i_pc_redirect_valid = 1'b0; 95 | io_i_branch_resolve_pack_valid = 1'b1; 96 | io_i_branch_resolve_pack_mispred = 1'b1; 97 | io_i_branch_resolve_pack_taken = 1'b1; 98 | io_i_branch_resolve_pack_prediction_valid = 1'b1; 99 | io_i_branch_resolve_pack_pc = 64'h4328; 100 | io_i_branch_resolve_pack_target = 64'h890a; 101 | 102 | 103 | #10 104 | io_i_branch_resolve_pack_valid = 1'b0; 105 | io_i_pc_redirect_valid = 1'b0; 106 | // fetch_pack_valid = 1'b0; 107 | #20 108 | io_i_pc_redirect_valid = 1'b1; 109 | io_i_pc_redirect_target = 64'h61230; 110 | #10 111 | io_i_pc_redirect_valid = 1'b0; 112 | 113 | #100 114 | $finish(1); 115 | end 116 | always #5 clk = ~clk; 117 | 118 | endmodule -------------------------------------------------------------------------------- /csrc/disasm.cc: -------------------------------------------------------------------------------- 1 | #if defined(__GNUC__) && !defined(__clang__) 2 | #pragma GCC diagnostic push 3 | #pragma GCC diagnostic ignored "-Wmaybe-uninitialized" 4 | #endif 5 | 6 | #include 7 | #include "llvm/MC/MCAsmInfo.h" 8 | #include "llvm/MC/MCContext.h" 9 | #include "llvm/MC/MCDisassembler/MCDisassembler.h" 10 | #include "llvm/MC/MCInstPrinter.h" 11 | #if LLVM_VERSION_MAJOR >= 14 12 | #include "llvm/MC/TargetRegistry.h" 13 | #else 14 | #include "llvm/Support/TargetRegistry.h" 15 | #endif 16 | #include "llvm/Support/TargetSelect.h" 17 | 18 | #if defined(__GNUC__) && !defined(__clang__) 19 | #pragma GCC diagnostic pop 20 | #endif 21 | 22 | #if LLVM_VERSION_MAJOR < 11 23 | #error Please use LLVM with major version >= 11 24 | #endif 25 | 26 | using namespace llvm; 27 | 28 | static llvm::MCDisassembler *gDisassembler = nullptr; 29 | static llvm::MCSubtargetInfo *gSTI = nullptr; 30 | static llvm::MCInstPrinter *gIP = nullptr; 31 | 32 | void init_disasm(const char *triple) { 33 | llvm::InitializeAllTargetInfos(); 34 | llvm::InitializeAllTargetMCs(); 35 | llvm::InitializeAllAsmParsers(); 36 | llvm::InitializeAllDisassemblers(); 37 | 38 | std::string errstr; 39 | std::string gTriple(triple); 40 | 41 | llvm::MCInstrInfo *gMII = nullptr; 42 | llvm::MCRegisterInfo *gMRI = nullptr; 43 | auto target = llvm::TargetRegistry::lookupTarget(gTriple, errstr); 44 | if (!target) { 45 | llvm::errs() << "Can't find target for " << gTriple << ": " << errstr << "\n"; 46 | assert(0); 47 | } 48 | 49 | MCTargetOptions MCOptions; 50 | gSTI = target->createMCSubtargetInfo(gTriple, "", ""); 51 | std::string isa = target->getName(); 52 | if (isa == "riscv32" || isa == "riscv64") { 53 | gSTI->ApplyFeatureFlag("+m"); 54 | gSTI->ApplyFeatureFlag("+a"); 55 | gSTI->ApplyFeatureFlag("+c"); 56 | gSTI->ApplyFeatureFlag("+f"); 57 | gSTI->ApplyFeatureFlag("+d"); 58 | } 59 | gMII = target->createMCInstrInfo(); 60 | gMRI = target->createMCRegInfo(gTriple); 61 | auto AsmInfo = target->createMCAsmInfo(*gMRI, gTriple, MCOptions); 62 | #if LLVM_VERSION_MAJOR >= 13 63 | auto llvmTripleTwine = Twine(triple); 64 | auto llvmtriple = llvm::Triple(llvmTripleTwine); 65 | auto Ctx = new llvm::MCContext(llvmtriple,AsmInfo, gMRI, nullptr); 66 | #else 67 | auto Ctx = new llvm::MCContext(AsmInfo, gMRI, nullptr); 68 | #endif 69 | gDisassembler = target->createMCDisassembler(*gSTI, *Ctx); 70 | gIP = target->createMCInstPrinter(llvm::Triple(gTriple), 71 | AsmInfo->getAssemblerDialect(), *AsmInfo, *gMII, *gMRI); 72 | gIP->setPrintImmHex(true); 73 | #if LLVM_VERSION_MAJOR >= 11 74 | gIP->setPrintBranchImmAsAddress(true); 75 | #endif 76 | } 77 | 78 | void disassemble(char *str, int size, uint64_t pc, uint8_t *code, int nbyte) { 79 | /* 80 | MCInst inst; 81 | llvm::ArrayRef arr(code, nbyte); 82 | uint64_t dummy_size=0 ; 83 | std::string s1; 84 | raw_string_ostream os1(s1); 85 | gDisassembler->getInstruction(inst, dummy_size, arr, pc,s1); //llvm::nulls()); 86 | std::string s; 87 | raw_string_ostream os(s); 88 | gIP->printInst(&inst, pc, "", *gSTI, os); 89 | 90 | int skip = s.find_first_not_of('\t'); 91 | const char *p = s.c_str() + skip; 92 | assert((int)s.length() - skip < size); 93 | strcpy(str, p);*/ 94 | MCInst inst; 95 | llvm::ArrayRef arr(code, nbyte); 96 | uint64_t dummy_size ; 97 | std::string s1; 98 | raw_string_ostream os1(s1); 99 | gDisassembler->getInstruction(inst, dummy_size, arr, pc, os1);// llvm::nulls()); 100 | 101 | std::string s; 102 | raw_string_ostream os(s); 103 | gIP->printInst(&inst, pc, "", *gSTI, os); 104 | 105 | int skip = s.find_first_not_of('\t'); 106 | const char *p = s.c_str() + skip; 107 | assert((int)s.length() - skip < size); 108 | //std::cout<<"aaa"< arr(code, nbyte); 118 | llvm::MCDisassembler::DecodeStatus decode_result = 119 | gDisassembler->getInstruction(inst, inst_size, arr, pc, 120 | llvm::nulls()); 121 | 122 | switch (decode_result) { 123 | case llvm::MCDisassembler::Fail: { 124 | printf("Invalid instruction encoding encountered at"); 125 | break; 126 | } 127 | case llvm::MCDisassembler::SoftFail: { 128 | printf("Potentially undefined instruction encoding encountered at"); 129 | // fall-through 130 | } 131 | case llvm::MCDisassembler::Success : { 132 | std::string s; 133 | raw_string_ostream os(s); 134 | gIP->printInst(&inst, pc, "", *gSTI, os); 135 | printf("%s",s.c_str()); 136 | */ 137 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-27/results.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Scala", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\arch_regfile.scala", "Scala", 17, 0, 3, 20 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\commit\rob.scala", "Scala", 161, 40, 31, 232 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\csr.scala", "Scala", 86, 7, 8, 101 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\decoder.scala", "Scala", 115, 9, 10, 134 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\dispatch\dispatch.scala", "Scala", 38, 8, 6, 52 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\execute.scala", "Scala", 120, 33, 33, 186 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\execute_unit.scala", "Scala", 343, 30, 68, 441 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\mul_div\booth.scala", "Scala", 56, 1, 6, 63 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\mul_div\div.scala", "Scala", 103, 2, 18, 123 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\mul_div\mul.scala", "Scala", 71, 9, 13, 93 12 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\execute\mul_div\wallace_tree.scala", "Scala", 127, 11, 23, 161 13 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\issue\reservation_station.scala", "Scala", 109, 32, 30, 171 14 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\issue\reservation_station_slot.scala", "Scala", 137, 9, 31, 177 15 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\regfile.scala", "Scala", 53, 2, 12, 67 16 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\rename\busy_table.scala", "Scala", 69, 14, 18, 101 17 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\rename\free_list.scala", "Scala", 89, 27, 21, 137 18 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\rename\rename.scala", "Scala", 54, 14, 15, 83 19 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\back_end\rename\rename_table.scala", "Scala", 60, 5, 9, 74 20 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\backend_with_decode.scala", "Scala", 103, 23, 21, 147 21 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\consts.scala", "Scala", 80, 25, 7, 112 22 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\defs.scala", "Scala", 118, 84, 22, 224 23 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\branch_predictor.scala", "Scala", 87, 20, 9, 116 24 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\branch_presolve.scala", "Scala", 48, 8, 3, 59 25 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\fetch_queue.scala", "Scala", 26, 0, 4, 30 26 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\fetchres.scala", "Scala", 24, 0, 3, 27 27 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\front_end.scala", "Scala", 62, 12, 19, 93 28 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\front_end_control.scala", "Scala", 31, 0, 5, 36 29 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\if1_if2.scala", "Scala", 30, 0, 7, 37 30 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\if2_if3.scala", "Scala", 31, 0, 6, 37 31 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\front_end\pc_gen.scala", "Scala", 36, 0, 7, 43 32 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\insts.scala", "Scala", 154, 10, 8, 172 33 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\ladder.scala", "Scala", 18, 51, 2, 71 34 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\src\test\scala\ladder\muldiv_test.scala", "Scala", 35, 7, 11, 53 35 | "Total", "-", 2691, 493, 489, 3673 -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_13-59-40/results.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\ALU.v", "Verilog", 349, 0, 1, 1, 351 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Arch_RegFile.v", "Verilog", 4259, 0, 0, 1, 4260 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BPU.v", "Verilog", 56061, 0, 1, 1, 56063 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", 310, 0, 1, 1, 312 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.anno.json", "JSON", 0, 17589, 0, 0, 17589 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 2572, 0, 0, 1, 2573 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Branch_Presolve.v", "Verilog", 61, 0, 0, 1, 62 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Busy_Table.v", "Verilog", 565, 0, 1, 1, 567 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR.v", "Verilog", 239, 0, 1, 1, 241 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR_BF.v", "Verilog", 197, 0, 1, 1, 199 12 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\DIV.v", "Verilog", 255, 0, 1, 1, 257 13 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v", "Verilog", 1740, 0, 1, 1, 1742 14 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Dispatch.v", "Verilog", 635, 0, 1, 1, 637 15 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Divider.v", "Verilog", 173, 0, 1, 1, 175 16 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 1255, 0, 0, 1, 1256 17 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", 78, 0, 0, 1, 79 18 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Res.v", "Verilog", 30, 0, 0, 1, 31 19 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.anno.json", "JSON", 0, 32, 0, 0, 32 20 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", 352, 0, 0, 1, 353 21 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Full_Adder.v", "Verilog", 10, 0, 0, 1, 11 22 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF1_IF2.v", "Verilog", 120, 0, 1, 1, 122 23 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF2_IF3.v", "Verilog", 121, 0, 1, 1, 123 24 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Interrupt_Mask.v", "Verilog", 79, 0, 1, 1, 81 25 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 300, 0, 1, 1, 302 26 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json", "JSON", 0, 17570, 0, 0, 17570 27 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v", "Verilog", 167, 0, 0, 1, 168 28 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\MUL.v", "Verilog", 268, 0, 1, 1, 270 29 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Multiplier.v", "Verilog", 238, 0, 1, 1, 240 30 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\PC_Gen.v", "Verilog", 85, 0, 1, 1, 87 31 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Partial_Products_Gen.v", "Verilog", 958, 0, 0, 1, 959 32 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", 251, 0, 1, 1, 253 33 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\RegFile.v", "Verilog", 3149, 0, 1, 1, 3151 34 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename.v", "Verilog", 1017, 0, 1, 1, 1019 35 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename_Table.v", "Verilog", 1676, 0, 1, 1, 1678 36 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reorder_Buffer.v", "Verilog", 25665, 0, 1, 1, 25667 37 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station.v", "Verilog", 21036, 0, 1, 1, 21038 38 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station_Slot.v", "Verilog", 564, 0, 1, 1, 566 39 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree.v", "Verilog", 6091, 0, 0, 1, 6092 40 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree_Cell.v", "Verilog", 334, 0, 0, 1, 335 41 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\front_end_control.v", "Verilog", 25, 0, 0, 1, 26 42 | "Total", "-", 131285, 35191, 24, 37, 166537 -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-02_16-39-50/results.csv: -------------------------------------------------------------------------------- 1 | "filename", "language", "Verilog", "JSON", "comment", "blank", "total" 2 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\ALU.v", "Verilog", 349, 0, 1, 1, 351 3 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Arch_RegFile.v", "Verilog", 4259, 0, 0, 1, 4260 4 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BPU.v", "Verilog", 56061, 0, 1, 1, 56063 5 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\BRU.v", "Verilog", 315, 0, 1, 1, 317 6 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.anno.json", "JSON", 0, 17589, 0, 0, 17589 7 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Back_End_With_Decode.v", "Verilog", 2594, 0, 0, 1, 2595 8 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Branch_Presolve.v", "Verilog", 61, 0, 0, 1, 62 9 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Busy_Table.v", "Verilog", 565, 0, 1, 1, 567 10 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR.v", "Verilog", 239, 0, 1, 1, 241 11 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\CSR_BF.v", "Verilog", 197, 0, 1, 1, 199 12 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\DIV.v", "Verilog", 255, 0, 1, 1, 257 13 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Decoder.v", "Verilog", 1744, 0, 1, 1, 1746 14 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Dispatch.v", "Verilog", 635, 0, 1, 1, 637 15 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Divider.v", "Verilog", 173, 0, 1, 1, 175 16 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Execute.v", "Verilog", 1263, 0, 0, 1, 1264 17 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Queue.v", "Verilog", 102, 0, 0, 1, 103 18 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Fetch_Res.v", "Verilog", 30, 0, 0, 1, 31 19 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.anno.json", "JSON", 0, 32, 0, 0, 32 20 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Front_End.v", "Verilog", 374, 0, 0, 1, 375 21 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Full_Adder.v", "Verilog", 10, 0, 0, 1, 11 22 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF1_IF2.v", "Verilog", 120, 0, 1, 1, 122 23 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\IF2_IF3.v", "Verilog", 121, 0, 1, 1, 123 24 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Interrupt_Mask.v", "Verilog", 79, 0, 1, 1, 81 25 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\LSU.v", "Verilog", 302, 0, 1, 1, 304 26 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.anno.json", "JSON", 0, 17707, 0, 0, 17707 27 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Ladder.v", "Verilog", 200, 0, 0, 1, 201 28 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\MUL.v", "Verilog", 268, 0, 1, 1, 270 29 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Multiplier.v", "Verilog", 238, 0, 1, 1, 240 30 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\PC_Gen.v", "Verilog", 85, 0, 1, 1, 87 31 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Partial_Products_Gen.v", "Verilog", 958, 0, 0, 1, 959 32 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Queue.v", "Verilog", 353, 0, 1, 1, 355 33 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\RegFile.v", "Verilog", 3149, 0, 1, 1, 3151 34 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename.v", "Verilog", 1017, 0, 1, 1, 1019 35 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Rename_Table.v", "Verilog", 1676, 0, 1, 1, 1678 36 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reorder_Buffer.v", "Verilog", 25665, 0, 1, 1, 25667 37 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station.v", "Verilog", 21036, 0, 1, 1, 21038 38 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Reservation_Station_Slot.v", "Verilog", 564, 0, 1, 1, 566 39 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree.v", "Verilog", 6091, 0, 0, 1, 6092 40 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\Wallace_Tree_Cell.v", "Verilog", 334, 0, 0, 1, 335 41 | "d:\StudyDocuments\OOOCoreDesign\sbttest\chisel-template - ladder_be\genrtl\front_end_control.v", "Verilog", 25, 0, 0, 1, 26 42 | "Total", "-", 131507, 35328, 24, 37, 166896 -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/execute/mul_div/div.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chisel3._ 6 | import chisel3.ExplicitCompileOptions.Strict 7 | import chiseltest._ 8 | import org.scalatest.freespec.AnyFreeSpec 9 | import chisel3.util._ 10 | import chisel3.util.BitPat 11 | import chisel3.util.experimental.decode._ 12 | import chisel3.experimental.BundleLiterals._ 13 | 14 | class Divider extends Module{ 15 | val io = IO(new Bundle{ 16 | val i_dividend = Input(UInt(64.W)) 17 | val i_divisor = Input(UInt(64.W)) 18 | val i_div_valid = Input(Bool()) 19 | val i_divw = Input(Bool()) 20 | val i_div_signed = Input(Bool()) 21 | val i_flush = Input(Bool()) 22 | 23 | val o_out_ready = Output(Bool()) 24 | val o_out_valid = Output(Bool()) 25 | val o_quotient = Output(UInt(64.W)) 26 | val o_remainder = Output(UInt(64.W)) 27 | }) 28 | val state = RegInit(0.U(7.W)) 29 | val next_state = Wire(UInt(7.W)) 30 | 31 | //state =0 :free 65:finished 32 | next_state := MuxCase(state + 1.U,Seq( 33 | (state>65.U || state===65.U) -> 0.U, 34 | (state===0.U) -> Mux(io.i_div_valid, 1.U , 0.U) 35 | )) 36 | state := Mux(io.i_flush, 0.U, next_state) 37 | 38 | io.o_out_ready := state === 0.U 39 | io.o_out_valid := state === 65.U 40 | 41 | val quotient_sign = Wire(UInt(1.W)) 42 | val remainder_sign = Wire(UInt(1.W)) 43 | 44 | when(!io.i_div_signed){ 45 | quotient_sign := 1.U 46 | }.otherwise{ 47 | when(io.i_divw){ 48 | quotient_sign := (io.i_dividend(31) & io.i_divisor(31)) || (!io.i_dividend(31) & !io.i_divisor(31)) 49 | }.otherwise{ 50 | quotient_sign := (io.i_dividend(63) & io.i_divisor(63)) || (!io.i_dividend(63) & !io.i_divisor(63)) 51 | } 52 | } 53 | when(!io.i_div_signed){ 54 | remainder_sign := 1.U 55 | }.otherwise{ 56 | when(io.i_divw){ 57 | remainder_sign := (!io.i_dividend(31) & io.i_divisor(31)) || (!io.i_dividend(31) & !io.i_divisor(31)) 58 | }.otherwise{ 59 | remainder_sign := (!io.i_dividend(63) & io.i_divisor(63)) || (!io.i_dividend(63) & !io.i_divisor(63)) 60 | } 61 | } 62 | val dividend_unsigned = Wire(UInt(64.W)) 63 | val divisor_unsigned = Wire(UInt(64.W)) 64 | 65 | when(!io.i_div_signed){ 66 | when(io.i_divw){ 67 | dividend_unsigned := io.i_dividend(31,0) 68 | divisor_unsigned := io.i_divisor(31,0) 69 | }.otherwise{ 70 | dividend_unsigned := io.i_dividend 71 | divisor_unsigned := io.i_divisor 72 | } 73 | }.otherwise{ 74 | when(io.i_divw){ 75 | dividend_unsigned := Cat(Fill(32,0.U(1.W)),Mux(io.i_dividend(31), (~io.i_dividend + 1.U)(31,0), io.i_dividend(31,0))) 76 | divisor_unsigned := Cat(Fill(32,0.U(1.W)),Mux(io.i_divisor(31), (~io.i_divisor + 1.U)(31,0), io.i_divisor(31,0))) 77 | }.otherwise{ 78 | dividend_unsigned := Mux(io.i_dividend(63), ~io.i_dividend + 1.U, io.i_dividend) 79 | divisor_unsigned := Mux(io.i_divisor(63), ~io.i_divisor + 1.U, io.i_divisor) 80 | } 81 | } 82 | 83 | val signs = Reg(UInt(2.W)) 84 | when(state === 1.U){ 85 | signs := Cat(remainder_sign, quotient_sign) //1 for positive , 0 for negative 86 | } 87 | 88 | val div_temp = Wire(UInt(128.W)) 89 | val temp_op1 = Reg(UInt(128.W)) 90 | val temp_op2 = Reg(UInt(128.W)) 91 | 92 | div_temp := temp_op1 - temp_op2 93 | 94 | //if 1st cyc, temp_op1 <- unsigned dividend, if otherwise, if quotient last cyc <0, temp_op1 <- div_temp 95 | temp_op1 := Mux(next_state === 1.U, Cat(0.U(64.W), dividend_unsigned), Mux(!div_temp(127),div_temp,temp_op1)) 96 | temp_op2 := Mux(next_state === 1.U, Cat(Cat(0.U(1.W), divisor_unsigned),0.U(63.W)), Cat(0.U(1.W),temp_op2(127,1)))//shift divisor right by 1 each time 97 | 98 | val ans = RegInit(0.U(64.W)) 99 | val next_ans = Wire(UInt(64.W)) 100 | ans:=next_ans 101 | 102 | next_ans := MuxCase(0.U,Seq( 103 | (state > 0.U && state < 65.U) -> Cat(ans(62,0),~(div_temp(127,127))), 104 | (state === 0.U) -> 0.U, 105 | (state === 65.U) -> ans 106 | )) 107 | 108 | val quotient_signed = Wire(UInt(64.W)) 109 | val remainder_signed = Wire(UInt(64.W)) 110 | 111 | when(io.i_divw){ 112 | quotient_signed := Mux(signs(0),ans,Cat(Fill(32,1.U(1.W)),~ans(31,0)+1.U)) 113 | }.otherwise{ 114 | quotient_signed := Mux(signs(0),ans,~ans+1.U) 115 | } 116 | when(io.i_divw){ 117 | remainder_signed := Mux(signs(1),temp_op1,Cat(Fill(32,1.U(1.W)),~temp_op1(31,0)+1.U)) 118 | }.otherwise{ 119 | remainder_signed := Mux(signs(1),temp_op1,~temp_op1+1.U) 120 | } 121 | 122 | io.o_quotient := quotient_signed 123 | io.o_remainder := remainder_signed 124 | 125 | } -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-27/details.md: -------------------------------------------------------------------------------- 1 | # Details 2 | 3 | Date : 2023-01-31 16:38:27 4 | 5 | Directory d:\\StudyDocuments\\OOOCoreDesign\\sbttest\\chisel-template - ladder_be\\src\\test\\scala\\ladder 6 | 7 | Total : 33 files, 2691 codes, 493 comments, 489 blanks, all 3673 lines 8 | 9 | [Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md) 10 | 11 | ## Files 12 | | filename | language | code | comment | blank | total | 13 | | :--- | :--- | ---: | ---: | ---: | ---: | 14 | | [src/test/scala/ladder/back_end/arch_regfile.scala](/src/test/scala/ladder/back_end/arch_regfile.scala) | Scala | 17 | 0 | 3 | 20 | 15 | | [src/test/scala/ladder/back_end/commit/rob.scala](/src/test/scala/ladder/back_end/commit/rob.scala) | Scala | 161 | 40 | 31 | 232 | 16 | | [src/test/scala/ladder/back_end/csr.scala](/src/test/scala/ladder/back_end/csr.scala) | Scala | 86 | 7 | 8 | 101 | 17 | | [src/test/scala/ladder/back_end/decoder.scala](/src/test/scala/ladder/back_end/decoder.scala) | Scala | 115 | 9 | 10 | 134 | 18 | | [src/test/scala/ladder/back_end/dispatch/dispatch.scala](/src/test/scala/ladder/back_end/dispatch/dispatch.scala) | Scala | 38 | 8 | 6 | 52 | 19 | | [src/test/scala/ladder/back_end/execute/execute.scala](/src/test/scala/ladder/back_end/execute/execute.scala) | Scala | 120 | 33 | 33 | 186 | 20 | | [src/test/scala/ladder/back_end/execute/execute_unit.scala](/src/test/scala/ladder/back_end/execute/execute_unit.scala) | Scala | 343 | 30 | 68 | 441 | 21 | | [src/test/scala/ladder/back_end/execute/mul_div/booth.scala](/src/test/scala/ladder/back_end/execute/mul_div/booth.scala) | Scala | 56 | 1 | 6 | 63 | 22 | | [src/test/scala/ladder/back_end/execute/mul_div/div.scala](/src/test/scala/ladder/back_end/execute/mul_div/div.scala) | Scala | 103 | 2 | 18 | 123 | 23 | | [src/test/scala/ladder/back_end/execute/mul_div/mul.scala](/src/test/scala/ladder/back_end/execute/mul_div/mul.scala) | Scala | 71 | 9 | 13 | 93 | 24 | | [src/test/scala/ladder/back_end/execute/mul_div/wallace_tree.scala](/src/test/scala/ladder/back_end/execute/mul_div/wallace_tree.scala) | Scala | 127 | 11 | 23 | 161 | 25 | | [src/test/scala/ladder/back_end/issue/reservation_station.scala](/src/test/scala/ladder/back_end/issue/reservation_station.scala) | Scala | 109 | 32 | 30 | 171 | 26 | | [src/test/scala/ladder/back_end/issue/reservation_station_slot.scala](/src/test/scala/ladder/back_end/issue/reservation_station_slot.scala) | Scala | 137 | 9 | 31 | 177 | 27 | | [src/test/scala/ladder/back_end/regfile.scala](/src/test/scala/ladder/back_end/regfile.scala) | Scala | 53 | 2 | 12 | 67 | 28 | | [src/test/scala/ladder/back_end/rename/busy_table.scala](/src/test/scala/ladder/back_end/rename/busy_table.scala) | Scala | 69 | 14 | 18 | 101 | 29 | | [src/test/scala/ladder/back_end/rename/free_list.scala](/src/test/scala/ladder/back_end/rename/free_list.scala) | Scala | 89 | 27 | 21 | 137 | 30 | | [src/test/scala/ladder/back_end/rename/rename.scala](/src/test/scala/ladder/back_end/rename/rename.scala) | Scala | 54 | 14 | 15 | 83 | 31 | | [src/test/scala/ladder/back_end/rename/rename_table.scala](/src/test/scala/ladder/back_end/rename/rename_table.scala) | Scala | 60 | 5 | 9 | 74 | 32 | | [src/test/scala/ladder/backend_with_decode.scala](/src/test/scala/ladder/backend_with_decode.scala) | Scala | 103 | 23 | 21 | 147 | 33 | | [src/test/scala/ladder/consts.scala](/src/test/scala/ladder/consts.scala) | Scala | 80 | 25 | 7 | 112 | 34 | | [src/test/scala/ladder/defs.scala](/src/test/scala/ladder/defs.scala) | Scala | 118 | 84 | 22 | 224 | 35 | | [src/test/scala/ladder/front_end/branch_predictor.scala](/src/test/scala/ladder/front_end/branch_predictor.scala) | Scala | 87 | 20 | 9 | 116 | 36 | | [src/test/scala/ladder/front_end/branch_presolve.scala](/src/test/scala/ladder/front_end/branch_presolve.scala) | Scala | 48 | 8 | 3 | 59 | 37 | | [src/test/scala/ladder/front_end/fetch_queue.scala](/src/test/scala/ladder/front_end/fetch_queue.scala) | Scala | 26 | 0 | 4 | 30 | 38 | | [src/test/scala/ladder/front_end/fetchres.scala](/src/test/scala/ladder/front_end/fetchres.scala) | Scala | 24 | 0 | 3 | 27 | 39 | | [src/test/scala/ladder/front_end/front_end.scala](/src/test/scala/ladder/front_end/front_end.scala) | Scala | 62 | 12 | 19 | 93 | 40 | | [src/test/scala/ladder/front_end/front_end_control.scala](/src/test/scala/ladder/front_end/front_end_control.scala) | Scala | 31 | 0 | 5 | 36 | 41 | | [src/test/scala/ladder/front_end/if1_if2.scala](/src/test/scala/ladder/front_end/if1_if2.scala) | Scala | 30 | 0 | 7 | 37 | 42 | | [src/test/scala/ladder/front_end/if2_if3.scala](/src/test/scala/ladder/front_end/if2_if3.scala) | Scala | 31 | 0 | 6 | 37 | 43 | | [src/test/scala/ladder/front_end/pc_gen.scala](/src/test/scala/ladder/front_end/pc_gen.scala) | Scala | 36 | 0 | 7 | 43 | 44 | | [src/test/scala/ladder/insts.scala](/src/test/scala/ladder/insts.scala) | Scala | 154 | 10 | 8 | 172 | 45 | | [src/test/scala/ladder/ladder.scala](/src/test/scala/ladder/ladder.scala) | Scala | 18 | 51 | 2 | 71 | 46 | | [src/test/scala/ladder/muldiv_test.scala](/src/test/scala/ladder/muldiv_test.scala) | Scala | 35 | 7 | 11 | 53 | 47 | 48 | [Summary](results.md) / Details / [Diff Summary](diff.md) / [Diff Details](diff-details.md) -------------------------------------------------------------------------------- /src/test/scala/ladder/cache/axi_arbiter.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.util._ 5 | 6 | class AXI4Lite_Arbiter extends Module { 7 | val io = IO(new Bundle { 8 | val in1 = Flipped(new AxiLiteMaster(64,128)) 9 | val in2 = Flipped(new AxiLiteMaster(64,128)) 10 | val out = new AxiLiteMaster(64,128) 11 | }) 12 | val s_idle :: s_in1 :: s_in2 :: Nil = Enum(3) 13 | val state = RegInit(0.U(2.W)) 14 | val in1Request = io.in1.writeAddr.valid || io.in1.readAddr.valid 15 | val in2Request = io.in2.writeAddr.valid || io.in2.readAddr.valid 16 | val in1done = ((io.in1.writeResp.valid && io.in1.writeResp.ready) || (io.in1.readData.valid && io.in1.readData.ready)) 17 | val in2done = ((io.in2.writeResp.valid && io.in2.writeResp.ready) || (io.in2.readData.valid && io.in2.readData.ready)) 18 | 19 | //dcache has a higher priority than icache 20 | state := MuxCase(state,Seq( 21 | (state === s_idle && in1Request && in2Request) -> s_in2, 22 | (state === s_idle && in1Request && !in2Request) -> s_in1, 23 | (state === s_idle && !in1Request && in2Request) -> s_in2, 24 | (state === s_in1 && in1done && !in2Request) -> s_idle, 25 | (state === s_in1 && in1done && in2Request) -> s_in2, 26 | (state === s_in2 && in2done) -> s_idle 27 | )) 28 | when(state === s_idle){ 29 | io.in1 <> DontCare 30 | io.in2 <> DontCare 31 | io.out <> DontCare 32 | io.in1.readAddr.ready := 0.U 33 | io.in1.readData.valid := 0.U 34 | io.in1.writeAddr.ready := 0.U 35 | io.in1.writeData.ready := 0.U 36 | io.in1.writeResp.valid := 0.U 37 | io.in2.readAddr.ready := 0.U 38 | io.in2.readData.valid := 0.U 39 | io.in2.writeAddr.ready := 0.U 40 | io.in2.writeData.ready := 0.U 41 | io.in2.writeResp.valid := 0.U 42 | io.out.readAddr.valid := 0.U 43 | io.out.readData.ready := 0.U 44 | io.out.writeAddr.valid := 0.U 45 | io.out.writeData.valid := 0.U 46 | io.out.writeResp.ready := 0.U 47 | }.elsewhen(state === s_in1){ 48 | io.in1 <> io.out 49 | io.in2 <> DontCare 50 | io.in2.readAddr.ready := 0.U 51 | io.in2.readData.valid := 0.U 52 | io.in2.writeAddr.ready := 0.U 53 | io.in2.writeData.ready := 0.U 54 | io.in2.writeResp.valid := 0.U 55 | 56 | }.elsewhen(state === s_in2){ 57 | io.in2 <> io.out 58 | io.in1 <> DontCare 59 | io.in1.readAddr.ready := 0.U 60 | io.in1.readData.valid := 0.U 61 | io.in1.writeAddr.ready := 0.U 62 | io.in1.writeData.ready := 0.U 63 | io.in1.writeResp.valid := 0.U 64 | }.otherwise{ 65 | io.in1 <> DontCare 66 | io.in2 <> DontCare 67 | io.out <> DontCare 68 | io.in1.readAddr.ready := 0.U 69 | io.in1.readData.valid := 0.U 70 | io.in1.writeAddr.ready := 0.U 71 | io.in1.writeData.ready := 0.U 72 | io.in1.writeResp.valid := 0.U 73 | io.in2.readAddr.ready := 0.U 74 | io.in2.readData.valid := 0.U 75 | io.in2.writeAddr.ready := 0.U 76 | io.in2.writeData.ready := 0.U 77 | io.in2.writeResp.valid := 0.U 78 | io.out.readAddr.valid := 0.U 79 | io.out.readData.ready := 0.U 80 | io.out.writeAddr.valid := 0.U 81 | io.out.writeData.valid := 0.U 82 | io.out.writeResp.ready := 0.U 83 | } 84 | } 85 | /* 86 | import chisel3._ 87 | import chisel3.util._ 88 | 89 | class Axi4LiteArbiter extends Module { 90 | val io = IO(new Bundle { 91 | val in1 = Flipped(new Axi4Lite) 92 | val in2 = Flipped(new Axi4Lite) 93 | val out = new Axi4Lite 94 | }) 95 | 96 | val in1Request = io.in1.aw.valid || io.in1.ar.valid || io.in1.w.valid 97 | val in2Request = io.in2.aw.valid || io.in2.ar.valid || io.in2.w.valid 98 | 99 | val arbiter = Module(new Arbiter(UInt(1.W), 2)) 100 | 101 | arbiter.io.in(0).valid := io.in1Request 102 | arbiter.io.in(1).valid := io.in2Request 103 | 104 | io.out.aw.valid := arbiter.io.out.valid && (io.in1.aw.valid && arbiter.io.chosen === 0.U || io.in2.aw.valid && arbiter.io.chosen === 1.U) 105 | io.out.aw.bits := Mux(io.in2.aw.valid && arbiter.io.chosen === 1.U, io.in2.aw.bits, io.in1.aw.bits) 106 | io.out.aw.ready := Mux(arbiter.io.chosen === 0.U, io.in1.aw.ready, io.in2.aw.ready) 107 | io.in1.aw.ready := arbiter.io.out.valid && arbiter.io.chosen === 0.U && io.out.aw.ready 108 | io.in2.aw.ready := arbiter.io.out.valid && arbiter.io.chosen === 1.U && io.out.aw.ready 109 | 110 | io.out.ar.valid := arbiter.io.out.valid && (io.in1.ar.valid && arbiter.io.chosen === 0.U || io.in2.ar.valid && arbiter.io.chosen === 1.U) 111 | io.out.ar.bits := Mux(io.in2.ar.valid && arbiter.io.chosen === 1.U, io.in2.ar.bits, io.in1.ar.bits) 112 | io.out.ar.ready := Mux(arbiter.io.chosen === 0.U, io.in1.ar.ready, io.in2.ar.ready) 113 | io.in1.ar.ready := arbiter.io.out.valid && arbiter.io.chosen === 0.U && io.out.ar.ready 114 | io.in2.ar.ready := arbiter.io.out.valid && arbiter.io.chosen === 1.U && io.out.ar.ready 115 | 116 | io.out.w.valid := arbiter.io.out.valid && (io.in1.w.valid && arbiter.io.chosen === 0.U || io.in2.w.valid && arbiter.io.chosen === 1.U) 117 | io.out.w.bits := Mux(io.in2.w.valid && arbiter.io.chosen === 1.U, io.in2.w.bits, io.in1.w.bits) 118 | io.out.w.ready := Mux(arbiter.io.chosen === 0.U, io.in1.w.ready, io.in2.w.ready) 119 | io.in1.w.ready := arbiter.io.out.valid && arbiter.io.chosen === 0.U && io.out.w.ready 120 | io.in2.w.ready := arbiter.io.out.valid && arbiter.io.chosen === 1.U && io.out.w.ready 121 | 122 | io.out.r.valid := io.in1.r.valid || io.in2.r.valid 123 | 124 | 125 | */ 126 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-39/results.json: -------------------------------------------------------------------------------- 1 | {"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Multiplier.v":{"language":"Verilog","code":238,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Queue.v":{"language":"Verilog","code":353,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/MUL.v":{"language":"Verilog","code":268,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/PC_Gen.v":{"language":"Verilog","code":85,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/LSU.v":{"language":"Verilog","code":282,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Partial_Products_Gen.v":{"language":"Verilog","code":958,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/IF2_IF3.v":{"language":"Verilog","code":121,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Full_Adder.v":{"language":"Verilog","code":10,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Rename.v":{"language":"Verilog","code":1017,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/IF1_IF2.v":{"language":"Verilog","code":120,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/front_end_control.v":{"language":"Verilog","code":25,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Front_End.anno.json":{"language":"JSON","code":32,"comment":0,"blank":0},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Fetch_Res.v":{"language":"Verilog","code":30,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Front_End.v":{"language":"Verilog","code":378,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Fetch_Queue.v":{"language":"Verilog","code":102,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/RegFile.v":{"language":"Verilog","code":3149,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Divider.v":{"language":"Verilog","code":173,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/DIV.v":{"language":"Verilog","code":255,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Execute.v":{"language":"Verilog","code":1251,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Dispatch.v":{"language":"Verilog","code":635,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/CSR_BF.v":{"language":"Verilog","code":197,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/CSR.v":{"language":"Verilog","code":239,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Busy_Table.v":{"language":"Verilog","code":565,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Decoder.v":{"language":"Verilog","code":1740,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reservation_Station_Slot.v":{"language":"Verilog","code":564,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Rename_Table.v":{"language":"Verilog","code":1676,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/BRU.v":{"language":"Verilog","code":312,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Wallace_Tree_Cell.v":{"language":"Verilog","code":334,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Branch_Presolve.v":{"language":"Verilog","code":61,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Wallace_Tree.v":{"language":"Verilog","code":6091,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Back_End_With_Decode.v":{"language":"Verilog","code":2556,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/ALU.v":{"language":"Verilog","code":349,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Arch_RegFile.v":{"language":"Verilog","code":4259,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Back_End_With_Decode.anno.json":{"language":"JSON","code":17589,"comment":0,"blank":0},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reorder_Buffer.v":{"language":"Verilog","code":25665,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reservation_Station.v":{"language":"Verilog","code":21036,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/BPU.v":{"language":"Verilog","code":56061,"comment":1,"blank":1}} -------------------------------------------------------------------------------- /.VSCodeCounter/2023-02-01_21-02-12/results.json: -------------------------------------------------------------------------------- 1 | {"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/CSR_BF.v":{"language":"Verilog","code":197,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/CSR.v":{"language":"Verilog","code":239,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Dispatch.v":{"language":"Verilog","code":635,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Busy_Table.v":{"language":"Verilog","code":565,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Branch_Presolve.v":{"language":"Verilog","code":61,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/BRU.v":{"language":"Verilog","code":312,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Decoder.v":{"language":"Verilog","code":1740,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Back_End_With_Decode.v":{"language":"Verilog","code":2556,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/DIV.v":{"language":"Verilog","code":255,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/ALU.v":{"language":"Verilog","code":349,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Wallace_Tree_Cell.v":{"language":"Verilog","code":334,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reservation_Station_Slot.v":{"language":"Verilog","code":564,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Arch_RegFile.v":{"language":"Verilog","code":4259,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Wallace_Tree.v":{"language":"Verilog","code":6091,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Rename.v":{"language":"Verilog","code":1017,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Queue.v":{"language":"Verilog","code":353,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/PC_Gen.v":{"language":"Verilog","code":85,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Rename_Table.v":{"language":"Verilog","code":1676,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Multiplier.v":{"language":"Verilog","code":238,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/MUL.v":{"language":"Verilog","code":268,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Partial_Products_Gen.v":{"language":"Verilog","code":958,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/LSU.v":{"language":"Verilog","code":282,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/IF2_IF3.v":{"language":"Verilog","code":121,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/IF1_IF2.v":{"language":"Verilog","code":120,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/RegFile.v":{"language":"Verilog","code":3149,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Full_Adder.v":{"language":"Verilog","code":10,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Front_End.anno.json":{"language":"JSON","code":32,"comment":0,"blank":0},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Front_End.v":{"language":"Verilog","code":378,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Fetch_Res.v":{"language":"Verilog","code":30,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/front_end_control.v":{"language":"Verilog","code":25,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Fetch_Queue.v":{"language":"Verilog","code":102,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Divider.v":{"language":"Verilog","code":173,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Execute.v":{"language":"Verilog","code":1251,"comment":0,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Back_End_With_Decode.anno.json":{"language":"JSON","code":17589,"comment":0,"blank":0},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reservation_Station.v":{"language":"Verilog","code":21036,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/Reorder_Buffer.v":{"language":"Verilog","code":25665,"comment":1,"blank":1},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/genrtl/BPU.v":{"language":"Verilog","code":56061,"comment":1,"blank":1}} -------------------------------------------------------------------------------- /src/test/scala/ladder/CPU_top_with_dpic.scala1: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Ladder extends Module { 12 | val io = IO(new Bundle { 13 | //icache io 14 | //val icache_io = new IcacheIO() 15 | //axiport for both icache and dcache, should be connected to a arbiter. 16 | //4 now, just used 4 icache and mem 17 | val axi_master = new AxiLiteMaster(64,128) 18 | 19 | //dcache io 20 | val dcache_io = new DcacheIO() 21 | val i_interrupt = Input(Bool()) 22 | //cmt_dbg 23 | val o_dbg_commit_packs = Output(Vec(2,new valid_uop_pack())) 24 | }) 25 | dontTouch(io.axi_master) 26 | val front_end = Module(new Front_End()) 27 | val back_end = Module(new Back_End_With_Decode()) 28 | val icache = Module(new Icache()) 29 | val dpic = Module(new dpic()) 30 | 31 | //connect front end input 32 | val last_branch_resolve_pack = RegInit(0.U.asTypeOf(new branch_resolve_pack())) 33 | last_branch_resolve_pack := back_end.io.o_branch_resolve_pack 34 | //when backend branch resolve flush, the front end just have to flush one cycle 35 | front_end.io.i_branch_resolve_pack := Mux(last_branch_resolve_pack.asUInt === back_end.io.o_branch_resolve_pack.asUInt, 36 | 0.U.asTypeOf(new branch_resolve_pack()), back_end.io.o_branch_resolve_pack) 37 | front_end.io.i_pc_redirect_valid := back_end.io.o_pc_redirect_valid 38 | front_end.io.i_pc_redirect_target := back_end.io.o_pc_redirect_target 39 | 40 | front_end.io.icache_io.i_addr_ready := icache.io.cpu_if.i_addr_ready 41 | front_end.io.icache_io.i_data_valid := icache.io.cpu_if.i_data_valid 42 | icache.io.cpu_if.o_wen := front_end.io.icache_io.o_wen 43 | icache.io.cpu_if.o_addr := front_end.io.icache_io.o_addr 44 | icache.io.cpu_if.o_addr_valid := front_end.io.icache_io.o_addr_valid 45 | icache.io.cpu_if.o_stall1 := front_end.io.icache_io.o_stall1 46 | icache.io.cpu_if.o_stall2 := front_end.io.icache_io.o_stall2 47 | front_end.io.icache_io.i_data := icache.io.cpu_if.i_data 48 | 49 | //dbg usage 50 | front_end.io.icache_io.dbg_i_addr2 := icache.io.cpu_if.dbg_i_addr2 51 | front_end.io.icache_io.dbg_i_addr3 := icache.io.cpu_if.dbg_i_addr3 52 | 53 | //connect icache and axi bus 54 | io.axi_master :<>= icache.io.mem_master 55 | 56 | //connect back end input 57 | back_end.io.i_fetch_pack <> front_end.io.o_fetch_pack 58 | back_end.io.i_interrupt := io.i_interrupt 59 | 60 | back_end.io.dcache_io.data_valid := dpic.io.data_valid//io.dcache_io.data_valid 61 | back_end.io.dcache_io.MdataIn := dpic.io.MdataIn//io.dcache_io.MdataIn 62 | io.dcache_io.addr_valid :=back_end.io.dcache_io.addr_valid 63 | io.dcache_io.data_ready :=back_end.io.dcache_io.data_ready 64 | back_end.io.dcache_io.addr_ready := dpic.io.addr_ready //io.dcache_io.addr_ready 65 | 66 | io.dcache_io.Mwout :=back_end.io.dcache_io.Mwout 67 | io.dcache_io.Maddr :=back_end.io.dcache_io.Maddr 68 | io.dcache_io.Men :=back_end.io.dcache_io.Men 69 | io.dcache_io.Mlen :=back_end.io.dcache_io.Mlen 70 | io.dcache_io.MdataOut :=back_end.io.dcache_io.MdataOut 71 | 72 | io.o_dbg_commit_packs := back_end.io.o_dbg_commit_packs 73 | 74 | //connect dpi-c ports 75 | dpic.io.clk := clock 76 | dpic.io.stop := back_end.io.o_dbg_stop 77 | dpic.io.data_ready := back_end.io.dcache_io.data_ready 78 | dpic.io.addr_valid := back_end.io.dcache_io.addr_valid 79 | dpic.io.Mwout := back_end.io.dcache_io.Mwout 80 | dpic.io.Maddr := back_end.io.dcache_io.Maddr 81 | dpic.io.Men :=back_end.io.dcache_io.Men 82 | dpic.io.Mlen :=back_end.io.dcache_io.Mlen 83 | dpic.io.MdataOut :=back_end.io.dcache_io.MdataOut 84 | 85 | dpic.io.regs0 := back_end.io.o_dbg_arch_regs(0) 86 | dpic.io.regs1 := back_end.io.o_dbg_arch_regs(1) 87 | dpic.io.regs2 := back_end.io.o_dbg_arch_regs(2) 88 | dpic.io.regs3 := back_end.io.o_dbg_arch_regs(3) 89 | dpic.io.regs4 := back_end.io.o_dbg_arch_regs(4) 90 | dpic.io.regs5 := back_end.io.o_dbg_arch_regs(5) 91 | dpic.io.regs6 := back_end.io.o_dbg_arch_regs(6) 92 | dpic.io.regs7 := back_end.io.o_dbg_arch_regs(7) 93 | dpic.io.regs8 := back_end.io.o_dbg_arch_regs(8) 94 | dpic.io.regs9 := back_end.io.o_dbg_arch_regs(9) 95 | dpic.io.regs10 := back_end.io.o_dbg_arch_regs(10) 96 | dpic.io.regs11 := back_end.io.o_dbg_arch_regs(11) 97 | dpic.io.regs12 := back_end.io.o_dbg_arch_regs(12) 98 | dpic.io.regs13 := back_end.io.o_dbg_arch_regs(13) 99 | dpic.io.regs14 := back_end.io.o_dbg_arch_regs(14) 100 | dpic.io.regs15 := back_end.io.o_dbg_arch_regs(15) 101 | dpic.io.regs16 := back_end.io.o_dbg_arch_regs(16) 102 | dpic.io.regs17 := back_end.io.o_dbg_arch_regs(17) 103 | dpic.io.regs18 := back_end.io.o_dbg_arch_regs(18) 104 | dpic.io.regs19 := back_end.io.o_dbg_arch_regs(19) 105 | dpic.io.regs20 := back_end.io.o_dbg_arch_regs(20) 106 | dpic.io.regs21 := back_end.io.o_dbg_arch_regs(21) 107 | dpic.io.regs22 := back_end.io.o_dbg_arch_regs(22) 108 | dpic.io.regs23 := back_end.io.o_dbg_arch_regs(23) 109 | dpic.io.regs24 := back_end.io.o_dbg_arch_regs(24) 110 | dpic.io.regs25 := back_end.io.o_dbg_arch_regs(25) 111 | dpic.io.regs26 := back_end.io.o_dbg_arch_regs(26) 112 | dpic.io.regs27 := back_end.io.o_dbg_arch_regs(27) 113 | dpic.io.regs28 := back_end.io.o_dbg_arch_regs(28) 114 | dpic.io.regs29 := back_end.io.o_dbg_arch_regs(29) 115 | dpic.io.regs30 := back_end.io.o_dbg_arch_regs(30) 116 | dpic.io.regs31 := back_end.io.o_dbg_arch_regs(31) 117 | } 118 | -------------------------------------------------------------------------------- /src/test/scala/ladder/cache/icache.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chiseltest._ 5 | import org.scalatest.freespec.AnyFreeSpec 6 | import chisel3.util._ 7 | import chisel3.util.experimental.decode._ 8 | import chisel3.experimental.BundleLiterals._ 9 | 10 | class IcacheIOreg extends Bundle{ 11 | val o_wen = Bool() 12 | val o_addr = UInt(64.W) 13 | val o_addr_valid = Bool() 14 | } 15 | class Icache extends Module{ 16 | val io = IO(new Bundle{ 17 | val cpu_if = Flipped(new IcacheIO()) 18 | val mem_master = new AxiLiteMaster(64,128) 19 | }) 20 | //icache pipeline--------------------------------------- 21 | //2 way associate cache, 128 sets, 16 bytes per line 22 | //4KB total, 64bits of paddr 23 | //tag: 53 bits, index: 7 bits, offset: 4 bits 24 | val cpu_if1 = RegInit((0.U).asTypeOf(new IcacheIOreg())) 25 | val cpu_if2 = RegInit((0.U).asTypeOf(new IcacheIOreg())) 26 | //val fetch_res_buf = RegInit(0.U(128.W)) 27 | //icache components------------------------------------- 28 | val tags0 = RegInit(VecInit(Seq.fill(128)(0.U(53.W))))//tag array 29 | val tags1 = RegInit(VecInit(Seq.fill(128)(0.U(53.W))))//tag array 30 | val valid0 = RegInit(VecInit(Seq.fill(128)(0.U(1.W))))//valid array 31 | val valid1 = RegInit(VecInit(Seq.fill(128)(0.U(1.W))))//valid array 32 | val data_array = Seq.fill(2)(Module(new Data_Array())) 33 | //query the cache--------------------------------------- 34 | val tag = Wire(UInt(53.W)) 35 | val index = Wire(UInt(7.W)) 36 | val offset = Wire(UInt(4.W)) 37 | val hit_bank = Wire(Vec(2,Bool())) 38 | val hit_bank2 = Wire(Vec(2,Bool())) 39 | val hit = Wire(Bool()) 40 | val victim = Wire(UInt(1.W)) 41 | //----------------------------------------------- 42 | val s_reset :: s_idle :: s_bus :: Nil = Enum(3) 43 | val state = RegInit(s_reset) 44 | val next_state = Wire(UInt(2.W)) 45 | //assign the parts 46 | when(io.cpu_if.o_stall1){ 47 | cpu_if1 := cpu_if1 48 | }.otherwise{ 49 | cpu_if1 := io.cpu_if 50 | } 51 | cpu_if2 := Mux(!io.cpu_if.o_stall2,cpu_if1,cpu_if2) 52 | /* 53 | fetch_res_buf := Mux(state===s_bus,io.mem_master.readData.bits.data,fetch_res_buf) 54 | fetch_res_buf := MuxCase(fetch_res_buf, Seq( 55 | //(!io.cpu_if.o_stall2) -> MuxCase(fetch_res_buf,Seq( 56 | (state === s_idle) -> MuxCase(0.U,Seq( 57 | hit_bank(0) -> data_array(0).io.o_rdata, 58 | hit_bank(1) -> data_array(1).io.o_rdata 59 | )), 60 | (state === s_bus) -> io.mem_master.readData.bits.data 61 | ) 62 | ) 63 | */ 64 | val last_stall = RegInit(false.B) 65 | val out_reg = RegInit(0.U(128.W)) 66 | val dout = Mux(hit_bank2(0),data_array(0).io.o_rdata,data_array(1).io.o_rdata) 67 | val dout2 = Mux(last_stall,out_reg,dout) 68 | val index2 = Wire(UInt(7.W)) 69 | val tag2 = Wire(UInt(53.W)) 70 | tag2 := cpu_if2.o_addr(63,11) 71 | last_stall := io.cpu_if.o_stall2 72 | out_reg := Mux(state===s_bus,io.mem_master.readData.bits.data,dout2) 73 | io.cpu_if.i_data := Mux(!cpu_if2.o_addr(3), dout2(63,0),dout2(127,64)) 74 | io.cpu_if.i_data_valid := (state =/= s_bus) 75 | io.cpu_if.i_addr_ready := (state =/= s_bus) 76 | 77 | tag := cpu_if1.o_addr(63,11) 78 | index := cpu_if1.o_addr(10,4) 79 | offset := cpu_if1.o_addr(3,0) 80 | hit_bank(0) := (valid0(index) & (tags0(index) === tag)) 81 | hit_bank(1) := (valid1(index) & (tags1(index) === tag)) 82 | hit_bank2(0) := (valid0(index2) & (tags0(index2) === tag2)) 83 | hit_bank2(1) := (valid1(index2) & (tags1(index2) === tag2)) 84 | 85 | hit := hit_bank(0) || hit_bank(1) 86 | victim := MuxCase(0.U,Seq( 87 | (!valid0(index2).asBool) -> 0.U, 88 | (valid0(index2).asBool && !valid1(index2).asBool) -> 1.U , 89 | (valid0(index2).asBool && valid1(index2).asBool) -> 0.U 90 | ) 91 | ) 92 | //victim := ~index(6) 93 | index2 := cpu_if2.o_addr(10,4) 94 | //connect data array 95 | for(i <- 0 to 1){ 96 | data_array(i).io.i_ren := true.B 97 | data_array(i).io.i_wen := (next_state === s_idle) && (state === s_bus) && (i.U===victim) 98 | data_array(i).io.i_wstrb := 0xffff.U 99 | data_array(i).io.i_addr := Mux(state === s_bus,index2,index) 100 | data_array(i).io.i_wdata := io.mem_master.readData.bits.data 101 | } 102 | when((next_state === s_idle) && (state === s_bus) && (victim === 0.U)){ 103 | valid0(index2) := true.B 104 | tags0(index2) := cpu_if2.o_addr(63,11) 105 | } 106 | when((next_state === s_idle) && (state === s_bus) && (victim === 1.U)){ 107 | valid1(index2) := true.B 108 | tags1(index2) := cpu_if2.o_addr(63,11) 109 | } 110 | //state machine----------------------------------------- 111 | state := next_state 112 | next_state := MuxCase(state,Seq( 113 | (state === s_reset) -> s_idle, 114 | (state === s_idle && (!hit)) -> s_bus, 115 | (state === s_bus && (io.mem_master.readData.valid)) -> s_idle, 116 | (state === s_idle && (hit)) -> s_idle 117 | )) 118 | 119 | //axi control signals 120 | io.mem_master.readAddr.valid := (state === s_bus) 121 | io.mem_master.readAddr.bits.addr := Cat(cpu_if2.o_addr(63,4),0.U(4.W)) 122 | io.mem_master.readData.ready := (state === s_bus) 123 | 124 | io.mem_master.writeResp.ready := 0.U 125 | io.mem_master.writeAddr.bits.addr := 0.U 126 | io.mem_master.readAddr.bits.prot := 0.U 127 | io.mem_master.writeAddr.valid := 0.U 128 | io.mem_master.writeData.bits.strb := 0.U 129 | io.mem_master.writeData.valid := 0.U 130 | io.mem_master.writeData.bits.data:= 0.U 131 | io.mem_master.writeAddr.bits.prot := 0.U 132 | io.mem_master.writeResp.ready := 0.U 133 | io.mem_master.writeAddr.bits.addr := 0.U 134 | io.mem_master.readAddr.bits.prot := 0.U 135 | } 136 | -------------------------------------------------------------------------------- /src/test/scala/ladder/back_end/rename/rename.scala: -------------------------------------------------------------------------------- 1 | package Ladder 2 | 3 | import chisel3._ 4 | import chisel3.ExplicitCompileOptions.Strict 5 | import chiseltest._ 6 | import org.scalatest.freespec.AnyFreeSpec 7 | import chisel3.util._ 8 | import chisel3.util.experimental.decode._ 9 | import chisel3.experimental.BundleLiterals._ 10 | 11 | class Rename extends Module{ 12 | val io=IO(new Bundle{ 13 | val i_decode_packs=Input(Vec(2,new uop())) 14 | val i_commit_packs=Input(Vec(2,new commit_pack())) 15 | //the 2 below are all necessary. 16 | //rollback packs is for rename/busy table rbk information 17 | //and when the mispred branch is at the end of the rob, rob won't be valid, 18 | //but still needs to flush the stage, and that's when flush_for_branch is used 19 | val i_rollback_packs=Input(Vec(2,new rollback_pack())) 20 | val i_flush_for_branch =Input(Bool()) 21 | 22 | val o_free_list_empty = Output(Bool()) 23 | val o_rename_packs=Output(Vec(2,new uop())) 24 | val o_written_back_table=Output(UInt(128.W)) 25 | 26 | val i_exception = Input(Bool()) 27 | val i_stall = Input(Bool()) 28 | 29 | //for decode and dpi-c arch regs 30 | val o_commit_rename_table = Output(Vec(32,UInt(7.W))) 31 | }) 32 | val rename_table=Module(new Rename_Table()) 33 | //val free_list=Module(new Free_List()) 34 | val busy_table=Module(new Busy_Table()) 35 | val invalidify = Wire(Bool()) 36 | invalidify := io.i_exception || io.i_stall || io.i_rollback_packs(0).valid || io.i_rollback_packs(1).valid ||io.i_flush_for_branch 37 | 38 | io.o_commit_rename_table := rename_table.io.o_commit_rename_table 39 | 40 | //exchange 0,1 if invalid , valid 41 | val uops = RegInit(0.U.asTypeOf(Vec(2,new uop()))) 42 | uops(0) := Mux(io.i_stall, uops(0), Mux((!io.i_decode_packs(0).valid && io.i_decode_packs(1).valid), io.i_decode_packs(1), io.i_decode_packs(0))) 43 | uops(1) := Mux(io.i_stall, uops(1), Mux((!io.i_decode_packs(0).valid && io.i_decode_packs(1).valid), io.i_decode_packs(0), io.i_decode_packs(1))) 44 | when(io.i_exception || io.i_rollback_packs(0).valid || io.i_rollback_packs(1).valid || io.i_flush_for_branch){ 45 | uops(0).valid := false.B 46 | uops(1).valid := false.B 47 | } 48 | 49 | //rename table ------------------- 50 | for(i <- 0 until 2){ 51 | rename_table.io.i_rename_req_packs(i).arch_rs1 := Mux(uops(i).valid && !invalidify && !io.i_stall,uops(i).arch_rs1,0.U) 52 | rename_table.io.i_rename_req_packs(i).arch_rs2 := Mux(uops(i).valid && !invalidify && !io.i_stall,uops(i).arch_rs2,0.U) 53 | rename_table.io.i_rename_req_packs(i).arch_dst := Mux(uops(i).valid && !invalidify && !io.i_stall,uops(i).arch_dst,0.U) 54 | } 55 | rename_table.io.i_commit_packs := io.i_commit_packs 56 | rename_table.io.i_rollback_packs := io.i_rollback_packs 57 | rename_table.io.i_allocation_pack:=io.o_rename_packs 58 | 59 | rename_table.io.i_exception:= io.i_exception 60 | /* 61 | //free list----------------------- 62 | free_list.io.i_free_list_reqs(0):= uops(0).valid && (uops(0).arch_dst =/= 0.U) 63 | free_list.io.i_free_list_reqs(1):= uops(1).valid && (uops(1).arch_dst =/= 0.U) 64 | 65 | free_list.io.i_commit_packs := io.i_commit_packs 66 | free_list.io.i_rollback_packs := io.i_rollback_packs 67 | */ 68 | 69 | io.o_rename_packs := uops 70 | io.o_rename_packs(0).valid := Mux(invalidify ,false.B,uops(0).valid) 71 | io.o_rename_packs(1).valid := Mux(invalidify ,false.B,uops(1).valid) 72 | io.o_free_list_empty := busy_table.io.o_empty 73 | 74 | io.o_rename_packs(0).phy_rs1 := rename_table.io.o_rename_res_packs(0).phy_rs1 75 | io.o_rename_packs(0).phy_rs2 := rename_table.io.o_rename_res_packs(0).phy_rs2 76 | io.o_rename_packs(0).stale_dst := rename_table.io.o_rename_res_packs(0).phy_dst 77 | io.o_rename_packs(0).phy_dst := busy_table.io.o_allocated_pregs(0) 78 | 79 | io.o_rename_packs(1).phy_rs1 := Mux(uops(0).arch_dst === uops(1).arch_rs1, busy_table.io.o_allocated_pregs(0), rename_table.io.o_rename_res_packs(1).phy_rs1) 80 | io.o_rename_packs(1).phy_rs2 := Mux(uops(0).arch_dst === uops(1).arch_rs2, busy_table.io.o_allocated_pregs(0), rename_table.io.o_rename_res_packs(1).phy_rs2) 81 | io.o_rename_packs(1).stale_dst := Mux(uops(0).arch_dst === uops(1).arch_dst, busy_table.io.o_allocated_pregs(0), rename_table.io.o_rename_res_packs(1).phy_dst) 82 | io.o_rename_packs(1).phy_dst := busy_table.io.o_allocated_pregs(1) 83 | 84 | //busy table---------------------- 85 | busy_table.io.i_allocated_uops := io.o_rename_packs 86 | busy_table.io.i_commit_packs := io.i_commit_packs 87 | busy_table.io.i_rollback_packs := io.i_rollback_packs 88 | //it is implied that for any inst that does not write a reg, the arch_dst field in uop in already set to 0 in the decode stage. 89 | busy_table.io.i_free_list_reqs(0):= uops(0).valid && (uops(0).arch_dst =/= 0.U) && !invalidify 90 | busy_table.io.i_free_list_reqs(1):= uops(1).valid && (uops(1).arch_dst =/= 0.U) && !invalidify 91 | busy_table.io.i_exception := io.i_exception 92 | 93 | io.o_written_back_table := busy_table.io.o_written_back 94 | 95 | //printf("phydst0=%d ,phy_dst1=%d\n",io.o_rename_packs(0).phy_dst,io.o_rename_packs(1).phy_dst) 96 | } 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | -------------------------------------------------------------------------------- /.VSCodeCounter/2023-01-31_16-38-27/results.json: -------------------------------------------------------------------------------- 1 | {"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/ladder.scala":{"language":"Scala","code":18,"comment":51,"blank":2},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/muldiv_test.scala":{"language":"Scala","code":35,"comment":7,"blank":11},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/insts.scala":{"language":"Scala","code":154,"comment":10,"blank":8},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/backend_with_decode.scala":{"language":"Scala","code":103,"comment":23,"blank":21},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/consts.scala":{"language":"Scala","code":80,"comment":25,"blank":7},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/defs.scala":{"language":"Scala","code":118,"comment":84,"blank":22},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/regfile.scala":{"language":"Scala","code":53,"comment":2,"blank":12},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/branch_presolve.scala":{"language":"Scala","code":48,"comment":8,"blank":3},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/if2_if3.scala":{"language":"Scala","code":31,"comment":0,"blank":6},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/if1_if2.scala":{"language":"Scala","code":30,"comment":0,"blank":7},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/pc_gen.scala":{"language":"Scala","code":36,"comment":0,"blank":7},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/front_end.scala":{"language":"Scala","code":62,"comment":12,"blank":19},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/front_end_control.scala":{"language":"Scala","code":31,"comment":0,"blank":5},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/fetch_queue.scala":{"language":"Scala","code":26,"comment":0,"blank":4},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/decoder.scala":{"language":"Scala","code":115,"comment":9,"blank":10},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/fetchres.scala":{"language":"Scala","code":24,"comment":0,"blank":3},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/csr.scala":{"language":"Scala","code":86,"comment":7,"blank":8},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/arch_regfile.scala":{"language":"Scala","code":17,"comment":0,"blank":3},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/front_end/branch_predictor.scala":{"language":"Scala","code":87,"comment":20,"blank":9},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/dispatch/dispatch.scala":{"language":"Scala","code":38,"comment":8,"blank":6},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/rename/busy_table.scala":{"language":"Scala","code":69,"comment":14,"blank":18},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/commit/rob.scala":{"language":"Scala","code":161,"comment":40,"blank":31},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/issue/reservation_station_slot.scala":{"language":"Scala","code":137,"comment":9,"blank":31},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/issue/reservation_station.scala":{"language":"Scala","code":109,"comment":32,"blank":30},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/rename/free_list.scala":{"language":"Scala","code":89,"comment":27,"blank":21},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/execute.scala":{"language":"Scala","code":120,"comment":33,"blank":33},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/rename/rename.scala":{"language":"Scala","code":54,"comment":14,"blank":15},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/rename/rename_table.scala":{"language":"Scala","code":60,"comment":5,"blank":9},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/mul_div/wallace_tree.scala":{"language":"Scala","code":127,"comment":11,"blank":23},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/mul_div/mul.scala":{"language":"Scala","code":71,"comment":9,"blank":13},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/execute_unit.scala":{"language":"Scala","code":343,"comment":30,"blank":68},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/mul_div/div.scala":{"language":"Scala","code":103,"comment":2,"blank":18},"file:///d%3A/StudyDocuments/OOOCoreDesign/sbttest/chisel-template%20-%20ladder_be/src/test/scala/ladder/back_end/execute/mul_div/booth.scala":{"language":"Scala","code":56,"comment":1,"blank":6}} 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