├── BrianHG_DDR3 ├── 4096Mb_ddr3_parameters.vh ├── BrianHG_DDR3_CMD_SEQUENCER_v16.sv ├── BrianHG_DDR3_CMD_SEQUENCER_v16_tb.sv ├── BrianHG_DDR3_COMMANDER_v16.sv ├── BrianHG_DDR3_COMMANDER_v16_tb.sv ├── BrianHG_DDR3_CONTROLLER_v16_top.sv ├── BrianHG_DDR3_CONTROLLER_v16_top_tb.sv ├── BrianHG_DDR3_FIFOs.sv ├── BrianHG_DDR3_GEN_tCK.sv ├── BrianHG_DDR3_IO_PORT_ALTERA.sv ├── BrianHG_DDR3_PHY_SEQ_v16.sv ├── BrianHG_DDR3_PHY_SEQ_v16_tb.sv ├── BrianHG_DDR3_PLL.sv ├── BrianHG_DDR3_PLL_tb.sv ├── BrianHG_DDR3_v15_and_v16_Block_Diagram.png ├── DDR3_CMD_SEQ_script_v16.txt ├── DDR3_CMD_SEQ_script_v16_log.txt ├── DDR3_COMMAND_v16_script.txt ├── DDR3_COMMAND_v16_script_log.txt ├── DDR3_CONTROLLER_v16_top_script.txt ├── DDR3_CONTROLLER_v16_top_script_log.txt ├── DDR3_Micron_Verilog_Model │ ├── 1024Mb_ddr3_parameters.vh │ ├── 2048Mb_ddr3_parameters.vh │ ├── 4096Mb_ddr3_parameters.vh │ ├── 8192Mb_ddr3_parameters.vh │ ├── ddr3.v │ ├── ddr3_dimm.v │ ├── ddr3_mcp.v │ ├── ddr3_module.v │ ├── readme.txt │ ├── subtest.vh │ └── tb.v ├── DDR3_PHY_script_v16.txt ├── DDR3_PHY_script_v16_log.txt ├── allreq.txt ├── altera_gpio_lite.sv ├── ddr3.v ├── rs232_DEBUGGER.v ├── run_com_v16.do ├── run_phy_v16.do ├── run_pll.do ├── run_seq_v16.do ├── run_tCK.do ├── run_top_v16.do ├── setup_com_v16.do ├── setup_phy_v16.do ├── setup_pll.do ├── setup_seq_v16.do ├── setup_tCK.do ├── setup_top_v16.do └── sync_rs232_uart.v ├── BrianHG_DDR3_CIII_GFX_TEST_v16_1_LAYER_Q13.0sp1 ├── AUDIO_IF.v ├── BrianHG_DDR3_CIII.sdc ├── BrianHG_DDR3_CIII_top.qpf ├── BrianHG_DDR3_CIII_top.qsf ├── BrianHG_DDR3_CIII_top.qws ├── BrianHG_DDR3_CIII_top.sv ├── BrianHG_DDR3_CIII_top_assignment_defaults.qdf ├── I2C_Controller.v ├── I2C_HDMI_Config.v └── PLLJ_PLLSPE_INFO.txt ├── BrianHG_DDR3_CIV_GFX_TEST_v16_1_LAYER ├── AUDIO_IF.v ├── BrianHG_DDR3_CIV.sdc ├── BrianHG_DDR3_CIV_top.qpf ├── BrianHG_DDR3_CIV_top.qsf ├── BrianHG_DDR3_CIV_top.qws ├── BrianHG_DDR3_CIV_top.sv ├── I2C_Controller.v ├── I2C_HDMI_Config.v └── line_buf_init.mif ├── BrianHG_DDR3_CV_GFX_TEST_v16_1_LAYER_350MHz ├── AUDIO_IF.v ├── BrianHG_DDR3_CV.sdc ├── BrianHG_DDR3_CV_top.qpf ├── BrianHG_DDR3_CV_top.qsf ├── BrianHG_DDR3_CV_top.qws ├── BrianHG_DDR3_CV_top.sv ├── I2C_Controller.v ├── I2C_HDMI_Config.v ├── c5_pin_model_dump.txt └── serv_req_info.txt ├── BrianHG_DDR3_DECA_GFX_DEMOS_v16.zip ├── BrianHG_DDR3_DECA_GFX_DEMO_v16_1_LAYER ├── AUDIO_IF.v ├── BrianHG_DDR3_DECA.sdc ├── BrianHG_DDR3_DECA_top.qpf ├── BrianHG_DDR3_DECA_top.qsf ├── BrianHG_DDR3_DECA_top.qws ├── BrianHG_DDR3_DECA_top.sv ├── I2C_Controller.v └── I2C_HDMI_Config.v ├── BrianHG_DDR3_DECA_GFX_DEMO_v16_2_LAYERS ├── AUDIO_IF.v ├── BrianHG_DDR3_DECA.sdc ├── BrianHG_DDR3_DECA_top.qpf ├── BrianHG_DDR3_DECA_top.qsf ├── BrianHG_DDR3_DECA_top.qws ├── BrianHG_DDR3_DECA_top.sv ├── I2C_Controller.v └── I2C_HDMI_Config.v ├── BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS ├── AUDIO_IF.v ├── BrianHG_DDR3_DECA.sdc ├── BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS.sof ├── BrianHG_DDR3_DECA_top.qpf ├── BrianHG_DDR3_DECA_top.qsf ├── BrianHG_DDR3_DECA_top.qws ├── BrianHG_DDR3_DECA_top.sv ├── I2C_Controller.v ├── I2C_HDMI_Config.v ├── RS232_debugger │ ├── 14layer480p.bin │ ├── 3layer1080p.bin │ ├── 4layer1080p.bin │ ├── 8layer720p.bin │ ├── BrianHG_DDR3_DECA_GFX_HWREGS_1.png │ ├── BrianHG_DDR3_DECA_GFX_HWREGS_2.png │ └── RS232_Debugger.exe └── ReadMe.txt ├── BrianHG_DDR3_DECA_GFX_HWREGS_v16_16_LAYERS_test.zip ├── BrianHG_DDR3_DECA_PHY_SEQ_only_v16 ├── BrianHG_DDR3_DECA.sdc ├── BrianHG_DDR3_DECA_test1.qpf ├── BrianHG_DDR3_DECA_test1_top.qsf ├── BrianHG_DDR3_DECA_test1_top.qws └── BrianHG_DDR3_DECA_test1_top.sv ├── BrianHG_DDR3_DECA_RS232_DEBUG_TEST_v16 ├── BrianHG_DDR3_DECA.sdc ├── BrianHG_DDR3_DECA_top.qpf ├── BrianHG_DDR3_DECA_top.qsf ├── BrianHG_DDR3_DECA_top.qws └── BrianHG_DDR3_DECA_top.sv ├── BrianHG_DDR3_GFX_source_v16 ├── BrianHG_GFX_Layer_mixer.sv ├── BrianHG_GFX_PLL_i50_o297.sv ├── BrianHG_GFX_Sync_Gen.sv ├── BrianHG_GFX_Sync_Gen_tb.sv ├── BrianHG_GFX_VGA_Window_System.pdf ├── BrianHG_GFX_VGA_Window_System.sv ├── BrianHG_GFX_VGA_Window_System.txt ├── BrianHG_GFX_VGA_Window_System_DDR3_REGS.sv ├── BrianHG_GFX_VGA_Window_System_tb.sv ├── BrianHG_GFX_Video_Line_Buffer.sv ├── BrianHG_GFX_Video_Line_Buffer_tb.sv ├── BrianHG_GFX_Window_DDR3_Reader.sv ├── BrianHG_GFX_Window_DDR3_Reader_tb.sv ├── BrianHG_draw_test_patterns.sv ├── BrianHG_draw_test_patterns_tb.sv ├── BrianHG_scroll_screen.sv ├── HW_Regs.sv ├── LBUF_BLANK.mif ├── LBUF_BLANK.ver ├── VGA_FONT_8x16_mono32.mif ├── VGA_FONT_8x16_mono32.ver ├── VGA_PALETTE_RGBA32.mif ├── VGA_PALETTE_RGBA32.ver ├── ellipse_generator.sv ├── run_VGASYS.do ├── run_gfx.do ├── run_sg.do ├── run_vlb.do ├── run_wdr.do ├── setup_VGASYS.do ├── setup_gfx.do ├── setup_sg.do ├── setup_vlb.do └── setup_wdr.do ├── BrianHG_DDR3_README_V1.00.txt ├── BrianHG_DDR3_README_V1.50.txt ├── BrianHG_DDR3_v15_Block_Diagram.png ├── BrianHG_DDR3_v15_and_v16_Block_Diagram.png ├── BrianHG_GFX_VGA_Window_System.pdf ├── BrianHG_GFX_VGA_Window_System.txt ├── README.md ├── Screenshots ├── FMAX_screenshots │ ├── Cyclone III-6_400MHz_EP3C40F484C6_GFX.png │ ├── Cyclone III-8_300MHz_EP3C40F484C8_GFX.png │ ├── Cyclone IV-E-6_400MHz_EP4CE30F23C6_GFX.png │ ├── Cyclone IV-E-8_300MHz_EP4CE30F23C8_GFX.png │ ├── Cyclone V-E-6_300MHz_5CEFA4F23C6_GFX.png │ ├── Cyclone V-E-6_375MHz_5CEFA4F23C6_PHY_ONLY.png │ ├── Cyclone V-E-6_400MHz_5CEFA4F23C6_GFX_FAIL.png │ ├── Cyclone V-E-7_300MHz_5CEFA4F23C7_PHY_ONLY.png │ ├── Example_400MHz_lemmon_333MHz_timing.png │ ├── Max 10-6_400MHz_10M50DAF484C6GES_GFX_DECA.png │ ├── Max 10-8_300MHz_10M50DAF484C8GES_GFX_DECA.png │ └── Readme.txt └── LC-LUT_screenshots │ ├── 300MHz-8_ellipse.png │ ├── 300MHz_PHY_only.png │ ├── 300MHz_ellipse.png │ ├── 400MHz_ellipse.png │ ├── 450MHz_ellipse.png │ ├── 500MHz_ellipse.png │ └── Readme.txt └── Screenshots_Pin_Planner ├── Cyclone_IV_pinplanner.png ├── Max10_pinplanner.png └── README.txt /BrianHG_DDR3/4096Mb_ddr3_parameters.vh: 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