├── README.md ├── hdl ├── BHG_FP_clk_divider.v ├── BHG_FP_clk_divider_tb.v ├── run_fpd.do └── setup_fpd.do └── screenshots ├── Modelsim_FPD_fp_off.png ├── Modelsim_FPD_fp_on.png ├── Quartus_FPD_fp_off.png └── Quartus_FPD_fp_on.png /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/README.md -------------------------------------------------------------------------------- /hdl/BHG_FP_clk_divider.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/hdl/BHG_FP_clk_divider.v -------------------------------------------------------------------------------- /hdl/BHG_FP_clk_divider_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/hdl/BHG_FP_clk_divider_tb.v -------------------------------------------------------------------------------- /hdl/run_fpd.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/hdl/run_fpd.do -------------------------------------------------------------------------------- /hdl/setup_fpd.do: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/hdl/setup_fpd.do -------------------------------------------------------------------------------- /screenshots/Modelsim_FPD_fp_off.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/screenshots/Modelsim_FPD_fp_off.png -------------------------------------------------------------------------------- /screenshots/Modelsim_FPD_fp_on.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/screenshots/Modelsim_FPD_fp_on.png -------------------------------------------------------------------------------- /screenshots/Quartus_FPD_fp_off.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/screenshots/Quartus_FPD_fp_off.png -------------------------------------------------------------------------------- /screenshots/Quartus_FPD_fp_on.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider/HEAD/screenshots/Quartus_FPD_fp_on.png --------------------------------------------------------------------------------