├── AHB_Slave.v ├── Arbiter.v ├── Bus.v ├── Bustest.v ├── Decoder1_3.v ├── Mux2_1_Write.v ├── Mux_2_1_Write_Data.v ├── Mux_3_1.v ├── Mux_3_1_Resp.v ├── README.md ├── Top_top_module.v ├── mux2_1.v ├── myarbiterTest1.v ├── test_decoder.v ├── test_slave.v ├── tom_module_test.v └── top_module.v /AHB_Slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/AHB_Slave.v -------------------------------------------------------------------------------- /Arbiter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Arbiter.v -------------------------------------------------------------------------------- /Bus.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Bus.v -------------------------------------------------------------------------------- /Bustest.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Bustest.v -------------------------------------------------------------------------------- /Decoder1_3.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Decoder1_3.v -------------------------------------------------------------------------------- /Mux2_1_Write.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Mux2_1_Write.v -------------------------------------------------------------------------------- /Mux_2_1_Write_Data.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Mux_2_1_Write_Data.v -------------------------------------------------------------------------------- /Mux_3_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Mux_3_1.v -------------------------------------------------------------------------------- /Mux_3_1_Resp.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Mux_3_1_Resp.v -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/README.md -------------------------------------------------------------------------------- /Top_top_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/Top_top_module.v -------------------------------------------------------------------------------- /mux2_1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/mux2_1.v -------------------------------------------------------------------------------- /myarbiterTest1.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/myarbiterTest1.v -------------------------------------------------------------------------------- /test_decoder.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/test_decoder.v -------------------------------------------------------------------------------- /test_slave.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/test_slave.v -------------------------------------------------------------------------------- /tom_module_test.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/tom_module_test.v -------------------------------------------------------------------------------- /top_module.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/Buddhimah/System-Bus-Design-Verilog/HEAD/top_module.v --------------------------------------------------------------------------------