├── README.md ├── debug └── Makefile ├── debug_netlist └── Makefile ├── scc28nhkcp_hsc35p140_rvt.v ├── scripts ├── FileList.f ├── FileList_netlist.f └── filelist ├── src ├── accum.v ├── addr_decode.v ├── adr.v ├── alu.v ├── clk_gen.v ├── counter.v ├── cpu.v ├── cputop.v ├── datactl.v ├── machine.v ├── machinectl.v ├── ram.v ├── register.v └── rom.v ├── syn ├── exec │ ├── command.log │ ├── default.svf │ ├── run │ └── synthesis.tcl ├── formality │ ├── FM_WORK │ │ ├── GTECH │ │ │ └── GTECH_COMPONENTS.pkg │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ ├── GTECH_COMPONENTS.dmp │ │ │ │ └── GTECH_COMPONENTS.pbd │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ └── GTECH_COMPONENTS.dmp │ │ ├── fmbxaKDEH │ │ ├── i │ │ │ └── WORK │ │ │ │ └── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ └── r │ │ │ ├── DW01 │ │ │ └── DW01_COMPONENTS.pkg │ │ │ │ ├── DW01_COMPONENTS.dep │ │ │ │ ├── DW01_COMPONENTS.dmp │ │ │ │ └── DW01_COMPONENTS.pbd │ │ │ │ ├── DW01_COMPONENTS.dep │ │ │ │ └── DW01_COMPONENTS.dmp │ │ │ ├── DW02 │ │ │ └── DW02_COMPONENTS.pkg │ │ │ │ ├── DW02_COMPONENTS.dep │ │ │ │ ├── DW02_COMPONENTS.dmp │ │ │ │ └── DW02_COMPONENTS.pbd │ │ │ │ ├── DW02_COMPONENTS.dep │ │ │ │ └── DW02_COMPONENTS.dmp │ │ │ ├── DW03 │ │ │ └── DW03_COMPONENTS.pkg │ │ │ │ ├── DW03_COMPONENTS.dep │ │ │ │ └── DW03_COMPONENTS.dmp │ │ │ ├── DW04 │ │ │ └── DW04_COMPONENTS.pkg │ │ │ │ ├── DW04_COMPONENTS.dep │ │ │ │ ├── DW04_COMPONENTS.dmp │ │ │ │ └── DW04_COMPONENTS.pbd │ │ │ │ ├── DW04_COMPONENTS.dep │ │ │ │ └── DW04_COMPONENTS.dmp │ │ │ ├── DW05 │ │ │ └── DW05_COMPONENTS.pkg │ │ │ │ ├── DW05_COMPONENTS.dep │ │ │ │ └── DW05_COMPONENTS.dmp │ │ │ ├── DW06 │ │ │ └── DW06_COMPONENTS.pkg │ │ │ │ ├── DW06_COMPONENTS.dep │ │ │ │ └── DW06_COMPONENTS.dmp │ │ │ ├── DWARE │ │ │ ├── DWMATH.pkg │ │ │ │ ├── DWMATH.dep │ │ │ │ ├── DWMATH.dmp │ │ │ │ └── DWMATH.pbd │ │ │ │ │ ├── DWMATH.dep │ │ │ │ │ └── DWMATH.dmp │ │ │ ├── DWPACKAGES.pkg │ │ │ │ ├── DWPACKAGES.dep │ │ │ │ ├── DWPACKAGES.dmp │ │ │ │ └── DWPACKAGES.pbd │ │ │ │ │ ├── DWPACKAGES.dep │ │ │ │ │ └── DWPACKAGES.dmp │ │ │ ├── DWPACKAGES_N.pkg │ │ │ │ ├── DWPACKAGES_N.dep │ │ │ │ ├── DWPACKAGES_N.dmp │ │ │ │ └── DWPACKAGES_N.pbd │ │ │ │ │ ├── DWPACKAGES_N.dep │ │ │ │ │ └── DWPACKAGES_N.dmp │ │ │ ├── DW_DP_FUNCTIONS.pkg │ │ │ │ ├── DW_DP_FUNCTIONS.dep │ │ │ │ ├── DW_DP_FUNCTIONS.dmp │ │ │ │ └── DW_DP_FUNCTIONS.pbd │ │ │ │ │ ├── DW_DP_FUNCTIONS.dep │ │ │ │ │ └── DW_DP_FUNCTIONS.dmp │ │ │ ├── DW_DP_FUNCTIONS_ARITH.pkg │ │ │ │ ├── DW_DP_FUNCTIONS_ARITH.dep │ │ │ │ ├── DW_DP_FUNCTIONS_ARITH.dmp │ │ │ │ └── DW_DP_FUNCTIONS_ARITH.pbd │ │ │ │ │ ├── DW_DP_FUNCTIONS_ARITH.dep │ │ │ │ │ └── DW_DP_FUNCTIONS_ARITH.dmp │ │ │ ├── DW_FOUNDATION.pkg │ │ │ │ ├── DW_FOUNDATION.dep │ │ │ │ ├── DW_FOUNDATION.dmp │ │ │ │ └── DW_FOUNDATION.pbd │ │ │ │ │ ├── DW_FOUNDATION.dep │ │ │ │ │ └── DW_FOUNDATION.dmp │ │ │ ├── DW_FOUNDATION_ARITH.pkg │ │ │ │ ├── DW_FOUNDATION_ARITH.dep │ │ │ │ ├── DW_FOUNDATION_ARITH.dmp │ │ │ │ └── DW_FOUNDATION_ARITH.pbd │ │ │ │ │ ├── DW_FOUNDATION_ARITH.dep │ │ │ │ │ └── DW_FOUNDATION_ARITH.dmp │ │ │ ├── DW_FOUNDATION_COMP.pkg │ │ │ │ ├── DW_FOUNDATION_COMP.dep │ │ │ │ └── DW_FOUNDATION_COMP.dmp │ │ │ └── DW_FOUNDATION_COMP_ARITH.pkg │ │ │ │ ├── DW_FOUNDATION_COMP_ARITH.dep │ │ │ │ └── DW_FOUNDATION_COMP_ARITH.dmp │ │ │ └── WORK │ │ │ ├── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ │ ├── accum.mod │ │ │ └── accum.dmp │ │ │ ├── accum.recent │ │ │ ├── accum.sns │ │ │ ├── adr.mod │ │ │ └── adr.dmp │ │ │ ├── adr.recent │ │ │ ├── alu.mod │ │ │ └── alu.dmp │ │ │ ├── alu.recent │ │ │ ├── alu.sns │ │ │ ├── clk_gen.mod │ │ │ └── clk_gen.dmp │ │ │ ├── clk_gen.recent │ │ │ ├── clk_gen.sns │ │ │ ├── counter.mod │ │ │ └── counter.dmp │ │ │ ├── counter.recent │ │ │ ├── counter.sns │ │ │ ├── datactl.mod │ │ │ └── datactl.dmp │ │ │ ├── datactl.recent │ │ │ ├── datactl.sns │ │ │ ├── machine.mod │ │ │ └── machine.dmp │ │ │ ├── machine.recent │ │ │ ├── machine.sns │ │ │ ├── machine.ss │ │ │ ├── machine0.ss │ │ │ ├── machine1.ss │ │ │ ├── machine2.ss │ │ │ ├── machine3.ss │ │ │ ├── machinectl.mod │ │ │ └── machinectl.dmp │ │ │ ├── machinectl.recent │ │ │ ├── register.mod │ │ │ └── register.dmp │ │ │ ├── register.recent │ │ │ └── register.sns │ ├── FM_WORK1 │ │ ├── GTECH │ │ │ └── GTECH_COMPONENTS.pkg │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ ├── GTECH_COMPONENTS.dmp │ │ │ │ └── GTECH_COMPONENTS.pbd │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ └── GTECH_COMPONENTS.dmp │ │ ├── fmbaxUgz5 │ │ ├── i │ │ │ └── WORK │ │ │ │ └── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ └── r │ │ │ └── WORK │ │ │ ├── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ │ ├── accum.mod │ │ │ └── accum.dmp │ │ │ ├── accum.recent │ │ │ ├── accum.sns │ │ │ ├── adr.mod │ │ │ └── adr.dmp │ │ │ ├── adr.recent │ │ │ ├── alu.mod │ │ │ └── alu.dmp │ │ │ ├── alu.recent │ │ │ ├── alu.sns │ │ │ ├── clk_gen.mod │ │ │ └── clk_gen.dmp │ │ │ ├── clk_gen.recent │ │ │ ├── clk_gen.sns │ │ │ ├── counter.mod │ │ │ └── counter.dmp │ │ │ ├── counter.recent │ │ │ ├── counter.sns │ │ │ ├── datactl.mod │ │ │ └── datactl.dmp │ │ │ ├── datactl.recent │ │ │ ├── datactl.sns │ │ │ ├── machine.mod │ │ │ └── machine.dmp │ │ │ ├── machine.recent │ │ │ ├── machine.sns │ │ │ ├── machine.ss │ │ │ ├── machinectl.mod │ │ │ └── machinectl.dmp │ │ │ ├── machinectl.recent │ │ │ ├── register.mod │ │ │ └── register.dmp │ │ │ ├── register.recent │ │ │ └── register.sns │ ├── FM_WORK3 │ │ ├── GTECH │ │ │ └── GTECH_COMPONENTS.pkg │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ ├── GTECH_COMPONENTS.dmp │ │ │ │ └── GTECH_COMPONENTS.pbd │ │ │ │ ├── GTECH_COMPONENTS.dep │ │ │ │ └── GTECH_COMPONENTS.dmp │ │ ├── fmbeCHZk5 │ │ ├── i │ │ │ └── WORK │ │ │ │ └── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ └── r │ │ │ └── WORK │ │ │ ├── SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df │ │ │ ├── accum.mod │ │ │ └── accum.dmp │ │ │ ├── accum.recent │ │ │ ├── accum.sns │ │ │ ├── adr.mod │ │ │ └── adr.dmp │ │ │ ├── adr.recent │ │ │ ├── alu.mod │ │ │ └── alu.dmp │ │ │ ├── alu.recent │ │ │ ├── alu.sns │ │ │ ├── clk_gen.mod │ │ │ └── clk_gen.dmp │ │ │ ├── clk_gen.recent │ │ │ ├── clk_gen.sns │ │ │ ├── counter.mod │ │ │ └── counter.dmp │ │ │ ├── counter.recent │ │ │ ├── counter.sns │ │ │ ├── datactl.mod │ │ │ └── datactl.dmp │ │ │ ├── datactl.recent │ │ │ ├── datactl.sns │ │ │ ├── machine.mod │ │ │ └── machine.dmp │ │ │ ├── machine.recent │ │ │ ├── machine.sns │ │ │ ├── machine.ss │ │ │ ├── machinectl.mod │ │ │ └── machinectl.dmp │ │ │ ├── machinectl.recent │ │ │ ├── register.mod │ │ │ └── register.dmp │ │ │ ├── register.recent │ │ │ └── register.sns │ ├── fm.tcl │ ├── fm_shell_command.lck │ ├── fm_shell_command.log │ ├── fm_shell_command1.lck │ ├── fm_shell_command1.log │ ├── fm_shell_command2.log │ ├── fm_shell_command3.lck │ ├── fm_shell_command3.log │ ├── formality.lck │ ├── formality.log │ ├── formality1.lck │ ├── formality1.log │ ├── formality1_svf │ │ ├── .attributes │ │ └── svf.txt │ ├── formality2.log │ ├── formality2_svf │ │ ├── .attributes │ │ └── svf.txt │ ├── formality3.lck │ ├── formality3.log │ ├── formality3_svf │ │ ├── .attributes │ │ └── svf.txt │ ├── formality_svf │ │ ├── .attributes │ │ └── svf.txt │ └── log │ │ ├── matched.info │ │ ├── unmatched.info │ │ ├── verify_aborted_points.info │ │ ├── verify_failing_points.info │ │ └── verify_passing_points.info ├── lib │ ├── RRAM_IP_32Kx32_ECC_SS_0d81V_125C.db │ ├── SPC28NHKCPD18RNP_ss_V0p81_125C.db │ ├── scc28nhkcp_hsc35p140_rvt_ss_v0p81_125c_basic.db │ └── sram_sp_1024X32_ssg_cworstt_0p81v_0p81v_125c.db ├── logs │ └── sythesis.log ├── rpts │ ├── reportQOR.rpt │ ├── reportarea.rpt │ ├── reportcell.rpt │ ├── reportcheckdesign.rpt │ ├── reportconstraint.rpt │ ├── reportdesign.rpt │ ├── reporttiming.rpt │ ├── reporttimingmax.rpt │ └── reporttimingmin.rpt ├── temp │ ├── ACCUM.mr │ ├── ADR.mr │ ├── ALU.mr │ ├── CLK_GEN.mr │ ├── COUNTER.mr │ ├── CPU.mr │ ├── DATACTL.mr │ ├── MACHINE.mr │ ├── MACHINECTL.mr │ ├── REGISTER.mr │ ├── accum-verilog.pvl │ ├── accum-verilog.syn │ ├── adr-verilog.pvl │ ├── adr-verilog.syn │ ├── alu-verilog.pvl │ ├── alu-verilog.syn │ ├── clk_gen-verilog.pvl │ ├── clk_gen-verilog.syn │ ├── counter-verilog.pvl │ ├── counter-verilog.syn │ ├── cpu-verilog.pvl │ ├── cpu-verilog.syn │ ├── datactl-verilog.pvl │ ├── datactl-verilog.syn │ ├── machine-verilog.pvl │ ├── machine-verilog.syn │ ├── machinectl-verilog.pvl │ ├── machinectl-verilog.syn │ ├── register-verilog.pvl │ └── register-verilog.syn └── work │ ├── cpu.sdc │ ├── cpu.sdf │ ├── cpu.svf │ └── cpu.v └── test ├── test1.dat ├── test1.pro ├── test2.dat ├── test2.pro ├── test3.dat └── test3.pro /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/README.md -------------------------------------------------------------------------------- /debug/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/debug/Makefile -------------------------------------------------------------------------------- /debug_netlist/Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/debug_netlist/Makefile -------------------------------------------------------------------------------- /scc28nhkcp_hsc35p140_rvt.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/scc28nhkcp_hsc35p140_rvt.v -------------------------------------------------------------------------------- /scripts/FileList.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/scripts/FileList.f -------------------------------------------------------------------------------- /scripts/FileList_netlist.f: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/scripts/FileList_netlist.f -------------------------------------------------------------------------------- /scripts/filelist: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/scripts/filelist -------------------------------------------------------------------------------- /src/accum.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/accum.v -------------------------------------------------------------------------------- /src/addr_decode.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/addr_decode.v -------------------------------------------------------------------------------- /src/adr.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/adr.v -------------------------------------------------------------------------------- /src/alu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/alu.v -------------------------------------------------------------------------------- /src/clk_gen.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/clk_gen.v -------------------------------------------------------------------------------- /src/counter.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/counter.v -------------------------------------------------------------------------------- /src/cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/cpu.v -------------------------------------------------------------------------------- /src/cputop.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/cputop.v -------------------------------------------------------------------------------- /src/datactl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/datactl.v -------------------------------------------------------------------------------- /src/machine.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/machine.v -------------------------------------------------------------------------------- /src/machinectl.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/machinectl.v -------------------------------------------------------------------------------- /src/ram.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/ram.v -------------------------------------------------------------------------------- /src/register.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/register.v -------------------------------------------------------------------------------- /src/rom.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/src/rom.v -------------------------------------------------------------------------------- /syn/exec/command.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/exec/command.log -------------------------------------------------------------------------------- /syn/exec/default.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/exec/default.svf -------------------------------------------------------------------------------- /syn/exec/run: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/exec/run -------------------------------------------------------------------------------- /syn/exec/synthesis.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/exec/synthesis.tcl -------------------------------------------------------------------------------- /syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/fmbxaKDEH: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/fmbxaKDEH -------------------------------------------------------------------------------- /syn/formality/FM_WORK/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.pbd/DW01_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.pbd/DW01_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.pbd/DW01_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW01/DW01_COMPONENTS.pkg/DW01_COMPONENTS.pbd/DW01_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.pbd/DW02_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.pbd/DW02_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.pbd/DW02_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW02/DW02_COMPONENTS.pkg/DW02_COMPONENTS.pbd/DW02_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW03/DW03_COMPONENTS.pkg/DW03_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW03/DW03_COMPONENTS.pkg/DW03_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW03/DW03_COMPONENTS.pkg/DW03_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW03/DW03_COMPONENTS.pkg/DW03_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.pbd/DW04_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.pbd/DW04_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.pbd/DW04_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW04/DW04_COMPONENTS.pkg/DW04_COMPONENTS.pbd/DW04_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW05/DW05_COMPONENTS.pkg/DW05_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW05/DW05_COMPONENTS.pkg/DW05_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW05/DW05_COMPONENTS.pkg/DW05_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW05/DW05_COMPONENTS.pkg/DW05_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW06/DW06_COMPONENTS.pkg/DW06_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW06/DW06_COMPONENTS.pkg/DW06_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DW06/DW06_COMPONENTS.pkg/DW06_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DW06/DW06_COMPONENTS.pkg/DW06_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.dep: -------------------------------------------------------------------------------- 1 | 1623462807.957161 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.pbd/DWMATH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.pbd/DWMATH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.pbd/DWMATH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWMATH.pkg/DWMATH.pbd/DWMATH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.pbd/DWPACKAGES.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.pbd/DWPACKAGES.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.pbd/DWPACKAGES.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES.pkg/DWPACKAGES.pbd/DWPACKAGES.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.pbd/DWPACKAGES_N.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.pbd/DWPACKAGES_N.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.pbd/DWPACKAGES_N.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DWPACKAGES_N.pkg/DWPACKAGES_N.pbd/DWPACKAGES_N.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.pbd/DW_DP_FUNCTIONS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.pbd/DW_DP_FUNCTIONS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.pbd/DW_DP_FUNCTIONS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS.pkg/DW_DP_FUNCTIONS.pbd/DW_DP_FUNCTIONS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.pbd/DW_DP_FUNCTIONS_ARITH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.pbd/DW_DP_FUNCTIONS_ARITH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.pbd/DW_DP_FUNCTIONS_ARITH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_DP_FUNCTIONS_ARITH.pkg/DW_DP_FUNCTIONS_ARITH.pbd/DW_DP_FUNCTIONS_ARITH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.pbd/DW_FOUNDATION.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.pbd/DW_FOUNDATION.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.pbd/DW_FOUNDATION.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION.pkg/DW_FOUNDATION.pbd/DW_FOUNDATION.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.pbd/DW_FOUNDATION_ARITH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.pbd/DW_FOUNDATION_ARITH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.pbd/DW_FOUNDATION_ARITH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_ARITH.pkg/DW_FOUNDATION_ARITH.pbd/DW_FOUNDATION_ARITH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP.pkg/DW_FOUNDATION_COMP.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP.pkg/DW_FOUNDATION_COMP.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP.pkg/DW_FOUNDATION_COMP.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP.pkg/DW_FOUNDATION_COMP.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP_ARITH.pkg/DW_FOUNDATION_COMP_ARITH.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP_ARITH.pkg/DW_FOUNDATION_COMP_ARITH.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP_ARITH.pkg/DW_FOUNDATION_COMP_ARITH.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/DWARE/DW_FOUNDATION_COMP_ARITH.pkg/DW_FOUNDATION_COMP_ARITH.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/accum.mod/accum.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/accum.mod/accum.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/accum.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/accum.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/accum.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/adr.mod/adr.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/adr.mod/adr.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/adr.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/alu.mod/alu.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/alu.mod/alu.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/alu.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/alu.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/alu.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/clk_gen.mod/clk_gen.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/clk_gen.mod/clk_gen.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/clk_gen.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/clk_gen.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/clk_gen.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/counter.mod/counter.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/counter.mod/counter.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/counter.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/counter.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/counter.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/datactl.mod/datactl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/datactl.mod/datactl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/datactl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/datactl.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/datactl.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine.mod/machine.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine.mod/machine.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine0.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine0.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine1.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine1.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine2.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine2.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machine3.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machine3.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machinectl.mod/machinectl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/machinectl.mod/machinectl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/machinectl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/register.mod/register.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/register.mod/register.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/register.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK/r/WORK/register.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK/r/WORK/register.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/fmbaxUgz5: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/fmbaxUgz5 -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/accum.mod/accum.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/accum.mod/accum.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/accum.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/accum.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/accum.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/adr.mod/adr.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/adr.mod/adr.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/adr.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/alu.mod/alu.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/alu.mod/alu.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/alu.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/alu.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/alu.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/clk_gen.mod/clk_gen.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/clk_gen.mod/clk_gen.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/clk_gen.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/clk_gen.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/clk_gen.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/counter.mod/counter.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/counter.mod/counter.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/counter.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/counter.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/counter.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/datactl.mod/datactl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/datactl.mod/datactl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/datactl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/datactl.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/datactl.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machine.mod/machine.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/machine.mod/machine.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machine.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machine.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/machine.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machine.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/machine.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machinectl.mod/machinectl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/machinectl.mod/machinectl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/machinectl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/register.mod/register.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/register.mod/register.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/register.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK1/r/WORK/register.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK1/r/WORK/register.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dep -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/GTECH/GTECH_COMPONENTS.pkg/GTECH_COMPONENTS.pbd/GTECH_COMPONENTS.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/fmbeCHZk5: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/fmbeCHZk5 -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/i/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/SCC28NHKCP_HSC35P140_RVT_SS_V0P81_125C_BASIC.df -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/accum.mod/accum.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/accum.mod/accum.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/accum.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/accum.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/accum.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/adr.mod/adr.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/adr.mod/adr.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/adr.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/alu.mod/alu.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/alu.mod/alu.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/alu.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/alu.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/alu.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/clk_gen.mod/clk_gen.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/clk_gen.mod/clk_gen.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/clk_gen.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/clk_gen.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/clk_gen.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/counter.mod/counter.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/counter.mod/counter.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/counter.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/counter.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/counter.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/datactl.mod/datactl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/datactl.mod/datactl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/datactl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/datactl.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/datactl.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machine.mod/machine.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/machine.mod/machine.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machine.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machine.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/machine.sns -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machine.ss: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/machine.ss -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machinectl.mod/machinectl.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/machinectl.mod/machinectl.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/machinectl.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/register.mod/register.dmp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/register.mod/register.dmp -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/register.recent: -------------------------------------------------------------------------------- 1 | 0 2 | -------------------------------------------------------------------------------- /syn/formality/FM_WORK3/r/WORK/register.sns: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/FM_WORK3/r/WORK/register.sns -------------------------------------------------------------------------------- /syn/formality/fm.tcl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/fm.tcl -------------------------------------------------------------------------------- /syn/formality/fm_shell_command.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/fm_shell_command.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/fm_shell_command.log -------------------------------------------------------------------------------- /syn/formality/fm_shell_command1.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/fm_shell_command1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/fm_shell_command1.log -------------------------------------------------------------------------------- /syn/formality/fm_shell_command2.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/fm_shell_command2.log -------------------------------------------------------------------------------- /syn/formality/fm_shell_command3.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/fm_shell_command3.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/fm_shell_command3.log -------------------------------------------------------------------------------- /syn/formality/formality.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/formality.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality.log -------------------------------------------------------------------------------- /syn/formality/formality1.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/formality1.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality1.log -------------------------------------------------------------------------------- /syn/formality/formality1_svf/.attributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality1_svf/.attributes -------------------------------------------------------------------------------- /syn/formality/formality1_svf/svf.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality1_svf/svf.txt -------------------------------------------------------------------------------- /syn/formality/formality2.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality2.log -------------------------------------------------------------------------------- /syn/formality/formality2_svf/.attributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality2_svf/.attributes -------------------------------------------------------------------------------- /syn/formality/formality2_svf/svf.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality2_svf/svf.txt -------------------------------------------------------------------------------- /syn/formality/formality3.lck: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /syn/formality/formality3.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality3.log -------------------------------------------------------------------------------- /syn/formality/formality3_svf/.attributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality3_svf/.attributes -------------------------------------------------------------------------------- /syn/formality/formality3_svf/svf.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality3_svf/svf.txt -------------------------------------------------------------------------------- /syn/formality/formality_svf/.attributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality_svf/.attributes -------------------------------------------------------------------------------- /syn/formality/formality_svf/svf.txt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/formality_svf/svf.txt -------------------------------------------------------------------------------- /syn/formality/log/matched.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/log/matched.info -------------------------------------------------------------------------------- /syn/formality/log/unmatched.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/log/unmatched.info -------------------------------------------------------------------------------- /syn/formality/log/verify_aborted_points.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/log/verify_aborted_points.info -------------------------------------------------------------------------------- /syn/formality/log/verify_failing_points.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/log/verify_failing_points.info -------------------------------------------------------------------------------- /syn/formality/log/verify_passing_points.info: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/formality/log/verify_passing_points.info -------------------------------------------------------------------------------- /syn/lib/RRAM_IP_32Kx32_ECC_SS_0d81V_125C.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/lib/RRAM_IP_32Kx32_ECC_SS_0d81V_125C.db -------------------------------------------------------------------------------- /syn/lib/SPC28NHKCPD18RNP_ss_V0p81_125C.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/lib/SPC28NHKCPD18RNP_ss_V0p81_125C.db -------------------------------------------------------------------------------- /syn/lib/scc28nhkcp_hsc35p140_rvt_ss_v0p81_125c_basic.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/lib/scc28nhkcp_hsc35p140_rvt_ss_v0p81_125c_basic.db -------------------------------------------------------------------------------- /syn/lib/sram_sp_1024X32_ssg_cworstt_0p81v_0p81v_125c.db: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/lib/sram_sp_1024X32_ssg_cworstt_0p81v_0p81v_125c.db -------------------------------------------------------------------------------- /syn/logs/sythesis.log: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/logs/sythesis.log -------------------------------------------------------------------------------- /syn/rpts/reportQOR.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportQOR.rpt -------------------------------------------------------------------------------- /syn/rpts/reportarea.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportarea.rpt -------------------------------------------------------------------------------- /syn/rpts/reportcell.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportcell.rpt -------------------------------------------------------------------------------- /syn/rpts/reportcheckdesign.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportcheckdesign.rpt -------------------------------------------------------------------------------- /syn/rpts/reportconstraint.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportconstraint.rpt -------------------------------------------------------------------------------- /syn/rpts/reportdesign.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reportdesign.rpt -------------------------------------------------------------------------------- /syn/rpts/reporttiming.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reporttiming.rpt -------------------------------------------------------------------------------- /syn/rpts/reporttimingmax.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reporttimingmax.rpt -------------------------------------------------------------------------------- /syn/rpts/reporttimingmin.rpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/rpts/reporttimingmin.rpt -------------------------------------------------------------------------------- /syn/temp/ACCUM.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/ACCUM.mr -------------------------------------------------------------------------------- /syn/temp/ADR.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/ADR.mr -------------------------------------------------------------------------------- /syn/temp/ALU.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/ALU.mr -------------------------------------------------------------------------------- /syn/temp/CLK_GEN.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/CLK_GEN.mr -------------------------------------------------------------------------------- /syn/temp/COUNTER.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/COUNTER.mr -------------------------------------------------------------------------------- /syn/temp/CPU.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/CPU.mr -------------------------------------------------------------------------------- /syn/temp/DATACTL.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/DATACTL.mr -------------------------------------------------------------------------------- /syn/temp/MACHINE.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/MACHINE.mr -------------------------------------------------------------------------------- /syn/temp/MACHINECTL.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/MACHINECTL.mr -------------------------------------------------------------------------------- /syn/temp/REGISTER.mr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/REGISTER.mr -------------------------------------------------------------------------------- /syn/temp/accum-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/accum-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/accum-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/accum-verilog.syn -------------------------------------------------------------------------------- /syn/temp/adr-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/adr-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/adr-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/adr-verilog.syn -------------------------------------------------------------------------------- /syn/temp/alu-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/alu-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/alu-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/alu-verilog.syn -------------------------------------------------------------------------------- /syn/temp/clk_gen-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/clk_gen-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/clk_gen-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/clk_gen-verilog.syn -------------------------------------------------------------------------------- /syn/temp/counter-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/counter-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/counter-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/counter-verilog.syn -------------------------------------------------------------------------------- /syn/temp/cpu-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/cpu-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/cpu-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/cpu-verilog.syn -------------------------------------------------------------------------------- /syn/temp/datactl-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/datactl-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/datactl-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/datactl-verilog.syn -------------------------------------------------------------------------------- /syn/temp/machine-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/machine-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/machine-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/machine-verilog.syn -------------------------------------------------------------------------------- /syn/temp/machinectl-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/machinectl-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/machinectl-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/machinectl-verilog.syn -------------------------------------------------------------------------------- /syn/temp/register-verilog.pvl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/register-verilog.pvl -------------------------------------------------------------------------------- /syn/temp/register-verilog.syn: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/temp/register-verilog.syn -------------------------------------------------------------------------------- /syn/work/cpu.sdc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/work/cpu.sdc -------------------------------------------------------------------------------- /syn/work/cpu.sdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/work/cpu.sdf -------------------------------------------------------------------------------- /syn/work/cpu.svf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/work/cpu.svf -------------------------------------------------------------------------------- /syn/work/cpu.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/syn/work/cpu.v -------------------------------------------------------------------------------- /test/test1.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test1.dat -------------------------------------------------------------------------------- /test/test1.pro: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test1.pro -------------------------------------------------------------------------------- /test/test2.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test2.dat -------------------------------------------------------------------------------- /test/test2.pro: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test2.pro -------------------------------------------------------------------------------- /test/test3.dat: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test3.dat -------------------------------------------------------------------------------- /test/test3.pro: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CJH8668/risc_cpu/HEAD/test/test3.pro --------------------------------------------------------------------------------