├── sfa ├── adc1.sfa ├── adc2.sfa ├── ADC_CORE.sfa ├── CTDTDSM_V3.sfa ├── CTDSM_CORE_NEW.sfa ├── CP_branch_LVT_v5.sfa ├── DAC.sfa ├── 2019_10_01_5t_OTA.sfa ├── Gm1_v5_Practice.sfa ├── Current_mirror_OTA.sfa ├── NRZ_TRI_DAC_v3_dnw.sfa ├── COMPARATOR_PRE_AMP.sfa ├── OTA_FF_2s_v3e.sfa ├── Comparator_not_clocked.sfa ├── myComparator_v3.sfa ├── Retiming_Latch_common.sfa ├── Comparator_1to7_0p7_lvt.sfa ├── Cascode_current_mirrot_OTA.sfa ├── Telescopic_OTA_stacked_single_ended.sfa └── CLK_COMP.sfa ├── pku ├── sym2 │ ├── CP_branch_LVT_v5.sym │ ├── DAC.sym │ ├── DAC_SEN_RVT_CDS_P.sym │ ├── 2019_10_01_5t_OTA.sym │ ├── Current_mirror_OTA.sym │ ├── NRZ_TRI_DAC_v3_dnw.sym │ ├── Gm1_v5_Practice.sym │ ├── myComparator_v3.sym │ ├── COMPARATOR_PRE_AMP.sym │ ├── Comparator_not_clocked.sym │ ├── Cascode_current_mirrot_OTA.sym │ ├── OTA_FF_2s_v3e.sym │ ├── Retiming_Latch_common.sym │ ├── CLK_COMP.sym │ ├── Telescopic_OTA_stacked_single_ended.sym │ ├── Comparator_clocked.sym │ ├── Latch_D_new_V1.sym │ ├── Comparator_1to7_0p7_lvt.sym │ ├── COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW.sym │ ├── COMP_GM_STAGE_0415.sym │ ├── INT_V3.sym │ ├── V2I_VCO_v4.sym │ └── CTDSM_CORE_NEW.sym └── netlist │ ├── CP_branch_LVT_v5.sp │ ├── DAC.sp │ ├── 2019_10_01_5t_OTA.sp │ ├── NRZ_TRI_DAC_v3_dnw.sp │ ├── Current_mirror_OTA.sp │ ├── Gm1_v5_Practice.sp │ ├── myComparator_v3.sp │ ├── COMPARATOR_PRE_AMP.sp │ ├── Cascode_current_mirrot_OTA.sp │ ├── Comparator_not_clocked.sp │ ├── Retiming_Latch_common.sp │ ├── Comparator_1to7_0p7_lvt.sp │ ├── OTA_FF_2s_v3e.sp │ ├── Telescopic_OTA_stacked_single_ended.sp │ └── CLK_COMP.sp ├── sym ├── Gm1_v5_Practice.sym ├── COMPARATOR_PRE_AMP.sym ├── OTA_FF_2s_v3e.sym ├── adc2.sym ├── CTDSM_CORE_NEW.sym ├── adc1.sym ├── ADC_CORE.sym └── CTDTDSM_V3.sym ├── INV.sp ├── s3det ├── adc1.s3det ├── CTDSM_CORE_NEW.s3det ├── adc2.s3det ├── adc2.pair ├── adc2_labeled.pair ├── CTDTDSM_V3.s3det ├── ADC_CORE.s3det ├── adc1.pair ├── adc1_labeled.pair └── CTDSM_CORE_NEW.pair ├── BUFF.sp ├── .gitignore ├── open ├── block │ ├── comp2.sp │ ├── dac1.sp │ ├── dac2.sp │ ├── ota1.sp │ ├── ota3.sp │ ├── ota6.sp │ ├── comp5.sp │ ├── comp6.sp │ ├── comp4.sp │ ├── ota2.sp │ ├── latch1.sp │ ├── comp3.sp │ ├── ota5.sp │ ├── ota4.sp │ └── comp1.sp └── adc │ ├── adc2.sp │ ├── adc1.sp │ └── adc4.sp ├── comp_mod.sp ├── Gm1_v5_Practice.sp ├── COMPARATOR_PRE_AMP.sp ├── LICENSE ├── Comparator_1to7_0p7_lvt.sp ├── OTA_FF_2s_v3e.sp ├── README.md ├── AND_PREAMP_v5.sp ├── COMP_GM_STAGE_0415.sp ├── COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW.sp ├── CTDSM_CORE_NEW.sp ├── ADC_CORE.sp └── adc1.sp /sfa/adc1.sfa: -------------------------------------------------------------------------------- 1 | adc1 2 | 3 | -------------------------------------------------------------------------------- /sfa/adc2.sfa: -------------------------------------------------------------------------------- 1 | adc2 2 | 3 | -------------------------------------------------------------------------------- /sfa/ADC_CORE.sfa: -------------------------------------------------------------------------------- 1 | ADC_CORE 2 | 3 | -------------------------------------------------------------------------------- /sfa/CTDTDSM_V3.sfa: -------------------------------------------------------------------------------- 1 | CTDTDSM_V3 2 | 3 | -------------------------------------------------------------------------------- /sfa/CTDSM_CORE_NEW.sfa: -------------------------------------------------------------------------------- 1 | CTDSM_CORE_NEW 2 | 3 | -------------------------------------------------------------------------------- /sfa/CP_branch_LVT_v5.sfa: -------------------------------------------------------------------------------- 1 | CP_branch_LVT_v5 2 | xm41 xm39 3 | xm3 xm4 4 | 5 | -------------------------------------------------------------------------------- /pku/sym2/CP_branch_LVT_v5.sym: -------------------------------------------------------------------------------- 1 | CP_branch_LVT_v5 2 | xm39 xm41 3 | xm4 xm3 4 | 5 | -------------------------------------------------------------------------------- /sfa/DAC.sfa: -------------------------------------------------------------------------------- 1 | DAC 2 | xm11 xm7 3 | xm12 xm10 4 | xm1 xm0 5 | xm3 xm2 6 | xr2 xr0 7 | 8 | -------------------------------------------------------------------------------- /pku/sym2/DAC.sym: -------------------------------------------------------------------------------- 1 | DAC 2 | xm12 xm10 3 | xm11 xm7 4 | xm2 xm3 5 | xm0 xm1 6 | xr0 xr2 7 | 8 | -------------------------------------------------------------------------------- /pku/sym2/DAC_SEN_RVT_CDS_P.sym: -------------------------------------------------------------------------------- 1 | DAC_SEN_RVT_CDS_P 2 | m32 m35 3 | xm16 xm18 4 | xm6 xm8 5 | 6 | -------------------------------------------------------------------------------- /sfa/2019_10_01_5t_OTA.sfa: -------------------------------------------------------------------------------- 1 | 2019_10_01_5t_OTA 2 | m0s m3s 3 | m0 m3 4 | m1 m2 5 | m1s m2s 6 | 7 | -------------------------------------------------------------------------------- /sfa/Gm1_v5_Practice.sfa: -------------------------------------------------------------------------------- 1 | Gm1_v5_Practice 2 | xm27 xm26 3 | xc21 xc22 4 | xr11 xr12 5 | xm11 xm14 6 | 7 | -------------------------------------------------------------------------------- /sfa/Current_mirror_OTA.sfa: -------------------------------------------------------------------------------- 1 | Current_mirror_OTA 2 | m10 m16 3 | m18 m20 4 | m18s m20s 5 | m10 m11 6 | m17 m15 7 | m21 m19 8 | 9 | -------------------------------------------------------------------------------- /pku/sym2/2019_10_01_5t_OTA.sym: -------------------------------------------------------------------------------- 1 | 2019_10_01_5t_OTA 2 | m0s m3s 3 | m0 m3 4 | m1s m2s 5 | m1 m2 6 | m5 m4 7 | m5s m4s 8 | 9 | -------------------------------------------------------------------------------- /sfa/NRZ_TRI_DAC_v3_dnw.sfa: -------------------------------------------------------------------------------- 1 | NRZ_TRI_DAC_v3_dnw 2 | xm7 xm6 3 | xm14 xm15 4 | xm7 xm17 5 | xm14 xm18 6 | xm6 xm17 7 | xm15 xm18 8 | 9 | -------------------------------------------------------------------------------- /pku/sym2/Current_mirror_OTA.sym: -------------------------------------------------------------------------------- 1 | Current_mirror_OTA 2 | m17 m15 3 | m21 m18 4 | m20 m18 5 | m20s m18s 6 | m14 m16 7 | m11 m10 8 | 9 | -------------------------------------------------------------------------------- /pku/sym2/NRZ_TRI_DAC_v3_dnw.sym: -------------------------------------------------------------------------------- 1 | NRZ_TRI_DAC_v3_dnw 2 | xm17 xm7 3 | xm6 xm7 4 | xm17 xm6 5 | xm18 xm14 6 | xm18 xm15 7 | xm14 xm15 8 | 9 | -------------------------------------------------------------------------------- /sym/Gm1_v5_Practice.sym: -------------------------------------------------------------------------------- 1 | Gm1_v5_Practice 2 | xm11 xm14 3 | xm15 xm12 4 | xr11 xr12 5 | xc21 xc22 6 | xm27 xm26 7 | xm0 xm3 8 | xm2 xm4 9 | 10 | -------------------------------------------------------------------------------- /pku/sym2/Gm1_v5_Practice.sym: -------------------------------------------------------------------------------- 1 | Gm1_v5_Practice 2 | xm11 xm14 3 | xm15 xm12 4 | xr11 xr12 5 | xc21 xc22 6 | xm27 xm26 7 | xm0 xm3 8 | xm2 xm4 9 | 10 | -------------------------------------------------------------------------------- /pku/sym2/myComparator_v3.sym: -------------------------------------------------------------------------------- 1 | myComparator_v3 2 | xm18 xm2 3 | xm1 xm12 4 | xm14 xm13 5 | xm4 xm3 6 | xm5 xm6 7 | xm0 xm22 8 | xm15 xm8 9 | xm17 xm16 10 | 11 | -------------------------------------------------------------------------------- /sfa/COMPARATOR_PRE_AMP.sfa: -------------------------------------------------------------------------------- 1 | COMPARATOR_PRE_AMP 2 | xm17 xm16 3 | xm15 xm8 4 | xm14 xm13 5 | xm10 xm12 6 | xm4 xm3 7 | xm5 xm6 8 | xm18 xm19 9 | xm0 xm22 10 | 11 | -------------------------------------------------------------------------------- /sym/COMPARATOR_PRE_AMP.sym: -------------------------------------------------------------------------------- 1 | COMPARATOR_PRE_AMP 2 | xm5 xm6 3 | xm4 xm3 4 | xm14 xm13 5 | xm10 xm12 6 | xm18 xm19 7 | xm15 xm8 8 | xm16 xm17 9 | xm0 xm22 10 | 11 | -------------------------------------------------------------------------------- /INV.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt INV i vdd vss zn 5 | m1 zn i vss vss nch_lvt l=40e-9 w=155e-9 m=1 nf=1 6 | m0 zn i vdd vdd pch_lvt l=40e-9 w=205e-9 m=1 nf=1 7 | .ends INV 8 | -------------------------------------------------------------------------------- /pku/sym2/COMPARATOR_PRE_AMP.sym: -------------------------------------------------------------------------------- 1 | COMPARATOR_PRE_AMP 2 | xm5 xm6 3 | xm4 xm3 4 | xm14 xm13 5 | xm10 xm12 6 | xm18 xm19 7 | xm15 xm8 8 | xm16 xm17 9 | xm0 xm22 10 | 11 | -------------------------------------------------------------------------------- /pku/sym2/Comparator_not_clocked.sym: -------------------------------------------------------------------------------- 1 | Comparator_not_clocked 2 | M10 M8 3 | M6 M7 4 | M1 M4 5 | M2 M3 6 | M0 M5 7 | M11 M9 8 | M13 M15 9 | M12 M14 10 | 11 | -------------------------------------------------------------------------------- /pku/sym2/Cascode_current_mirrot_OTA.sym: -------------------------------------------------------------------------------- 1 | Cascode_current_mirrot_OTA 2 | m17 m15 3 | m26 m27 4 | m21 m19 5 | m20 m18 6 | m22 m23 7 | m24 m25 8 | m11 m10 9 | m14 m16 10 | 11 | -------------------------------------------------------------------------------- /sfa/OTA_FF_2s_v3e.sfa: -------------------------------------------------------------------------------- 1 | OTA_FF_2s_v3e 2 | m19 m21 3 | xc5 xc4 4 | xr12 xr13 5 | m37 m23 6 | m33 m34 7 | m59 m56 8 | m30 m29 9 | m20 m50 10 | m64 m66 11 | m7 m2 12 | m14 m13 13 | 14 | -------------------------------------------------------------------------------- /sfa/Comparator_not_clocked.sfa: -------------------------------------------------------------------------------- 1 | Comparator_not_clocked 2 | M16 M18 3 | M3 M4 4 | M6 M7 5 | M6 M8 6 | M10 M7 7 | M10 M8 8 | M17 M19 9 | M5 M0 10 | M1 M2 11 | M12 M14 12 | M13 M15 13 | 14 | -------------------------------------------------------------------------------- /sym/OTA_FF_2s_v3e.sym: -------------------------------------------------------------------------------- 1 | OTA_FF_2s_v3e 2 | m4 m6 3 | m50 m20 4 | m13 m14 5 | m64 m66 6 | m2 m7 7 | m37 m23 8 | m19 m21 9 | m58 m48 10 | m29 m30 11 | m56 m59 12 | xc5 xc4 13 | xr12 xr13 14 | 15 | -------------------------------------------------------------------------------- /pku/sym2/OTA_FF_2s_v3e.sym: -------------------------------------------------------------------------------- 1 | OTA_FF_2s_v3e 2 | m4 m6 3 | m50 m20 4 | m13 m14 5 | m64 m66 6 | m2 m7 7 | m37 m23 8 | m19 m21 9 | xc5 xc4 10 | xr12 xr13 11 | m58 m48 12 | m29 m30 13 | m56 m59 14 | 15 | -------------------------------------------------------------------------------- /pku/sym2/Retiming_Latch_common.sym: -------------------------------------------------------------------------------- 1 | Retiming_Latch_common 2 | xm16 xm12 3 | xm20 xm21 4 | xm10 xm0 5 | xm11 xm1 6 | xm13 xm17 7 | xm19 xm18 8 | xm37 xm39 9 | xm36 xm38 10 | xm33 xm35 11 | xm32 xm34 12 | 13 | -------------------------------------------------------------------------------- /pku/sym2/CLK_COMP.sym: -------------------------------------------------------------------------------- 1 | CLK_COMP 2 | xm16 xm19 3 | xm20 xm21 4 | xm55 xm70 5 | xm115 xm116 6 | xm35 xm73 7 | xm57 xm68 8 | xm56 xm69 9 | xm22 xm113 10 | xm1 xm3 11 | xm8 xm5 12 | xm24 xm114 13 | xm25 xm26 14 | xm119 xm122 15 | xm120 xm121 16 | 17 | -------------------------------------------------------------------------------- /pku/sym2/Telescopic_OTA_stacked_single_ended.sym: -------------------------------------------------------------------------------- 1 | Telescopic_OTA_stacked_single_ended 2 | m0s m3s 3 | m0 m3 4 | m9s m8s 5 | m9 m8 6 | m6 m7 7 | m6s m7s 8 | m1 m2 9 | m1s m2s 10 | m12 m15 11 | m12s m15s 12 | m16s m17s 13 | m16 m17 14 | 15 | -------------------------------------------------------------------------------- /pku/sym2/Comparator_clocked.sym: -------------------------------------------------------------------------------- 1 | Comparator_clocked 2 | I1/M0 I1/M1 3 | I1/M3 I1/M2 4 | I0/M0 I0/M1 5 | I0/M3 I0/M2 6 | M0 M1 7 | M4 M2 8 | M11 M12 9 | M7 M6 10 | M8 M9 11 | I0/M0 I1/M0 12 | I0/M1 I1/M1 13 | I0/M3 I1/M3 14 | I0/M2 I1/M2 15 | 16 | -------------------------------------------------------------------------------- /sfa/myComparator_v3.sfa: -------------------------------------------------------------------------------- 1 | myComparator_v3 2 | xm17 xm16 3 | xm15 xm8 4 | xm8 xm18 5 | xm8 xm2 6 | xm8 xm1 7 | xm8 xm12 8 | xm18 xm15 9 | xm15 xm2 10 | xm15 xm1 11 | xm15 xm12 12 | xm14 xm13 13 | xm1 xm12 14 | xm4 xm3 15 | xm5 xm6 16 | xm18 xm2 17 | xm0 xm22 18 | 19 | -------------------------------------------------------------------------------- /s3det/adc1.s3det: -------------------------------------------------------------------------------- 1 | adc1/input_res 2 | xr13 xr14 3 | 4 | adc1 5 | xr19 xr18 6 | xr17 xr16 7 | xi22 xi20 8 | xr28 xr47 9 | xr20 xr21 10 | xr20 xr22 11 | xr20 xr23 12 | xr21 xr22 13 | xr21 xr23 14 | xr22 xr23 15 | xr24 xr25 16 | xc2 xc1 17 | xc0 xc4 18 | rr2 rr1 19 | 20 | -------------------------------------------------------------------------------- /pku/sym2/Latch_D_new_V1.sym: -------------------------------------------------------------------------------- 1 | Latch_D_new_V1 2 | m2 m1 3 | m5 m3 4 | m4 m0 5 | m6 m7 6 | xi24/m1 xi16/m1 7 | xi24/m0 xi16/m0 8 | xi23/m1 xi18/m1 9 | xi23/m0 xi18/m0 10 | xi11/m11 xi26/m11 11 | xi11/m9 xi26/m9 12 | xi25/m1 xi20/m1 13 | xi25/m0 xi20/m0 14 | m13 m10 15 | m12 m9 16 | 17 | -------------------------------------------------------------------------------- /BUFF.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .subckt INV i vdd vss zn 5 | m1 zn i vss vss nch_lvt l=40e-9 w=155e-9 m=1 nf=1 6 | m0 zn i vdd vdd pch_lvt l=40e-9 w=205e-9 m=1 nf=1 7 | .ends INV 8 | 9 | .topckt BUF11 in out vdd vss 10 | xi1 net11 vdd vss out INV 11 | xi0 in vdd vss net11 INV 12 | .ends BUF11 13 | -------------------------------------------------------------------------------- /pku/sym2/Comparator_1to7_0p7_lvt.sym: -------------------------------------------------------------------------------- 1 | Comparator_1to7_0p7_lvt 2 | xm34 xm28 3 | xm21 xm14 4 | xm33 xm25 5 | xm32 xm29 6 | xm10 xm11 7 | xm13 xm12 8 | xm11 xm13 9 | xm10 xm12 10 | xm10 xm13 11 | xm11 xm12 12 | xm35 xm40 13 | xm36 xm37 14 | m0 m2 15 | m3 m1 16 | xm8 xm7 17 | xm6 xm9 18 | 19 | -------------------------------------------------------------------------------- /sfa/Retiming_Latch_common.sfa: -------------------------------------------------------------------------------- 1 | Retiming_Latch_common 2 | xm39 xm31 3 | xm39 xm37 4 | xm38 xm36 5 | xm39 xm26 6 | xm31 xm37 7 | xm31 xm26 8 | xm30 xm27 9 | xm37 xm26 10 | xm10 xm0 11 | xm11 xm1 12 | xm21 xm20 13 | xm13 xm17 14 | xm19 xm18 15 | xm12 xm16 16 | xm18 xm38 17 | xm18 xm36 18 | xm19 xm36 19 | 20 | -------------------------------------------------------------------------------- /sfa/Comparator_1to7_0p7_lvt.sfa: -------------------------------------------------------------------------------- 1 | Comparator_1to7_0p7_lvt 2 | xm19 xm33 3 | xm19 xm25 4 | xm7 xm8 5 | xm6 xm9 6 | xm28 xm34 7 | m2 m0 8 | xm14 xm21 9 | xm12 xm13 10 | xm12 xm10 11 | xm40 xm35 12 | xm37 xm36 13 | xm11 xm13 14 | xm11 xm10 15 | xm29 xm32 16 | xm25 xm33 17 | m3 m1 18 | xm27 xm6 19 | xm27 xm9 20 | 21 | -------------------------------------------------------------------------------- /sym/adc2.sym: -------------------------------------------------------------------------------- 1 | adc2 2 | input_resp input_resm 3 | dac1a dac1b 4 | dac3a dac3b 5 | 6 | adc2/cap1 7 | xc1_0_ xc1_3_ xc1_1_ xc1_2_ 8 | 9 | adc2/cap2_res2 10 | xr51 xr25 11 | 12 | adc2/digital0 13 | xm6 xm5 14 | xm2 xm18 15 | xm3 xm4 16 | xm12 xm1 17 | xm8 xm15 18 | xm13 xm14 19 | xm16 xm17 20 | xm22 xm0 21 | 22 | -------------------------------------------------------------------------------- /sym/CTDSM_CORE_NEW.sym: -------------------------------------------------------------------------------- 1 | CTDSM_CORE_NEW 2 | xr16 xr47 3 | xr25 xr51 4 | xi152 xi153 5 | xi88 xi92 6 | xi155 xi154 7 | xi99 xi97 8 | 9 | CTDSM_CORE_NEW/xi128 10 | xi0 xi1 11 | 12 | CTDSM_CORE_NEW/xi164 13 | xc0<0> xc0<1> 14 | xc0<0> xc0<2> 15 | xc0<0> xc0<3> 16 | xc0<1> xc0<2> 17 | xc0<1> xc0<3> 18 | xc0<2> xc0<3> 19 | 20 | -------------------------------------------------------------------------------- /sfa/Cascode_current_mirrot_OTA.sfa: -------------------------------------------------------------------------------- 1 | Cascode_current_mirrot_OTA 2 | m16 m10 3 | m15 m25 4 | m27 m23 5 | m19 m18 6 | m17 m25 7 | m26 m23 8 | m21 m18 9 | m16 m11 10 | m15 m24 11 | m27 m22 12 | m19 m20 13 | m17 m24 14 | m26 m22 15 | m21 m20 16 | m18 m20 17 | m23 m22 18 | m25 m24 19 | m10 m11 20 | m21 m19 21 | m26 m27 22 | m17 m15 23 | 24 | -------------------------------------------------------------------------------- /pku/sym2/COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW.sym: -------------------------------------------------------------------------------- 1 | COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW 2 | xm48 xm49 3 | xm46 xm47 4 | xm42 xm43 5 | xm44 xm45 6 | xm9 xm2 7 | xm6 xm16 8 | xm40 xm36 9 | xm41 xm37 10 | xm10 xm12 11 | xm0 xm1 12 | xm18 xm17 13 | xm14 xm13 14 | xm28 xm29 15 | xm61 xm62 16 | xm34 xm33 17 | xm34 xm32 18 | xm33 xm32 19 | xi3/xc2 xi3/xc3 20 | 21 | -------------------------------------------------------------------------------- /pku/sym2/COMP_GM_STAGE_0415.sym: -------------------------------------------------------------------------------- 1 | COMP_GM_STAGE_0415 2 | xm18 xm79 3 | xm2 xm78 4 | xm26 xm75 5 | xm23 xm80 6 | xm6 xm82 7 | xm83 xm21 8 | xm13 xm81 9 | d0 d2 10 | xm19 xm74 11 | xm73 xm17 12 | xm11 xm55 13 | xm4 xm7 14 | xm91 xm0 15 | xm92 xm89 16 | xm87 xm88 17 | xm63 xm77 18 | xm38 xm33 19 | xm43 xm44 20 | xm10 xm5 21 | xm8 xm9 22 | xm64 xm76 23 | xm52 xm0 24 | xm51 xm0 25 | 26 | -------------------------------------------------------------------------------- /s3det/CTDSM_CORE_NEW.s3det: -------------------------------------------------------------------------------- 1 | CTDSM_CORE_NEW/xi128 2 | xi0 xi1 3 | 4 | CTDSM_CORE_NEW 5 | xr51 xr25 6 | xi97 xi88 7 | xi99 xi97 8 | xi92 xi97 9 | xi99 xi88 10 | xi92 xi88 11 | xr47 xr16 12 | xi152 xi153 13 | xi92 xi99 14 | xi154 xi155 15 | 16 | CTDSM_CORE_NEW/xi164 17 | xc0<3> xc0<1> 18 | xc0<3> xc0<2> 19 | xc0<3> xc0<0> 20 | xc0<1> xc0<2> 21 | xc0<1> xc0<0> 22 | xc0<2> xc0<0> 23 | 24 | -------------------------------------------------------------------------------- /pku/sym2/INT_V3.sym: -------------------------------------------------------------------------------- 1 | INT_V3 2 | xm2 xm8 3 | xc8 xc6 4 | xm1 xm7 5 | xc5 xc9 6 | xm6 xm0 7 | xc7 xc1 8 | xc10 xc0 9 | xi181/m50 xi181/m20 10 | xi181/m66 xi181/m64 11 | xi181/m11 xi181/m10 12 | xi181/m13 xi181/m14 13 | xi181/m19 xi181/m21 14 | xi181/xr12 xi181/xr13 15 | xi181/xc5 xi181/xc4 16 | xi181/m37 xi181/m23 17 | xi181/m56 xi181/m59 18 | xi181/m29 xi181/m30 19 | xi181/m34 xi181/m33 20 | xi181/m58 xi181/m48 21 | 22 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Compiled Object files 5 | *.slo 6 | *.lo 7 | *.o 8 | *.obj 9 | 10 | # Precompiled Headers 11 | *.gch 12 | *.pch 13 | 14 | # Compiled Dynamic libraries 15 | *.so 16 | *.dylib 17 | *.dll 18 | 19 | # Fortran module files 20 | *.mod 21 | *.smod 22 | 23 | # Compiled Static libraries 24 | *.lai 25 | *.la 26 | *.a 27 | *.lib 28 | 29 | # Executables 30 | *.exe 31 | *.out 32 | *.app 33 | 34 | # MAC file system 35 | .DS_Store 36 | -------------------------------------------------------------------------------- /pku/sym2/V2I_VCO_v4.sym: -------------------------------------------------------------------------------- 1 | V2I_VCO_v4 2 | xm4 xm10 3 | xm5 xm8 4 | m7 m11 5 | m6 m9 6 | xi1<0>/m0 xi1<3>/m0 7 | xi1<0>/m1 xi1<3>/m1 8 | xi1<0>/m2 xi1<3>/m2 9 | xi1<0>/m3 xi1<3>/m3 10 | xi1<0>/m4 xi1<3>/m4 11 | xi1<0>/m5 xi1<3>/m5 12 | xi1<0>/m6 xi1<3>/m6 13 | xi1<0>/m7 xi1<3>/m7 14 | xi1<1>/m0 xi1<2>/m0 15 | xi1<1>/m1 xi1<2>/m1 16 | xi1<1>/m2 xi1<2>/m2 17 | xi1<1>/m3 xi1<2>/m3 18 | xi1<1>/m4 xi1<2>/m4 19 | xi1<1>/m5 xi1<2>/m5 20 | xi1<1>/m6 xi1<2>/m6 21 | xi1<1>/m7 xi1<2>/m7 22 | 23 | -------------------------------------------------------------------------------- /s3det/adc2.s3det: -------------------------------------------------------------------------------- 1 | adc2/digital0/xi128 2 | xi0 xi1 3 | 4 | adc2/dac3b 5 | xi97 xi94 6 | 7 | adc2/dac3a 8 | xi97 xi94 9 | 10 | adc2/cap2_res2 11 | xr51 xr25 12 | 13 | adc2 14 | dac1b dac1a 15 | dac1b dac3a 16 | dac1b dac3b 17 | input_resm input_resp 18 | dac3a dac1a 19 | dac3b dac1a 20 | dac3a dac3b 21 | 22 | adc2/dac1a 23 | xi86 xi88 24 | 25 | adc2/dac1b 26 | xi86 xi88 27 | 28 | adc2/cap1 29 | xc1_3_ xc1_2_ 30 | xc1_3_ xc1_1_ 31 | xc1_3_ xc1_0_ 32 | xc1_2_ xc1_1_ 33 | xc1_2_ xc1_0_ 34 | xc1_1_ xc1_0_ 35 | 36 | -------------------------------------------------------------------------------- /open/block/comp2.sp: -------------------------------------------------------------------------------- 1 | .topckt CP_branch_LVT_v5 dn dnb iout up upb vbn_cm vbn_cs vbp_cm vbp_cs vdd vdm vss vss_sub 2 | xm41 vdm up net38 vdd pch w=800e-9 l=40e-9 3 | xm39 iout upb net38 vdd pch w=800e-9 l=40e-9 4 | xm3 vdm dnb net37 vss nch w=800e-9 l=40e-9 5 | xm4 iout dn net37 vss nch w=800e-9 l=40e-9 6 | xm10 net41 vbn_cm vss vss nch_lvt w=2.2e-6 l=2e-6 7 | xm9 net37 vbn_cs net41 vss nch_lvt w=2e-6 l=80e-9 8 | xm13 net40 vbp_cm vdd vdd pch_lvt w=11.4e-6 l=2e-6 9 | xm36 net38 vbp_cs net40 vdd pch_lvt w=11.2e-6 l=80e-9 10 | .ends CP_branch_LVT_v5 11 | 12 | -------------------------------------------------------------------------------- /pku/netlist/CP_branch_LVT_v5.sp: -------------------------------------------------------------------------------- 1 | .topckt CP_branch_LVT_v5 dn dnb iout up upb vbn_cm vbn_cs vbp_cm vbp_cs vdd vdm vss vss_sub 2 | xm41 vdm up net38 vdd pch w=800e-9 l=40e-9 nf=4 3 | xm39 iout upb net38 vdd pch w=800e-9 l=40e-9 nf=4 4 | xm3 vdm dnb net37 vss nch w=800e-9 l=40e-9 nf=4 5 | xm4 iout dn net37 vss nch w=800e-9 l=40e-9 nf=4 6 | xm10 net41 vbn_cm vss vss nch_lvt w=2.2e-6 l=2e-6 nf=2 7 | xm9 net37 vbn_cs net41 vss nch_lvt w=2e-6 l=80e-9 nf=4 8 | xm13 net40 vbp_cm vdd vdd pch_lvt w=11.4e-6 l=2e-6 nf=2 9 | xm36 net38 vbp_cs net40 vdd pch_lvt w=11.2e-6 l=80e-9 nf=8 10 | .ends CP_branch_LVT_v5 11 | 12 | -------------------------------------------------------------------------------- /open/block/dac1.sp: -------------------------------------------------------------------------------- 1 | .topckt DAC dn dp ion iop vrefn vrefp vss_dac 2 | xm11 net09 dn vrefn vss_dac nch_lvt w=200e-9 l=40e-9 3 | xm7 net016 dp vrefn vss_dac nch_lvt w=200e-9 l=40e-9 4 | xm1 net018 net016 vrefn vss_dac nch_lvt w=400e-9 l=40e-9 5 | xm0 net010 net09 vrefn vss_dac nch_lvt w=400e-9 l=40e-9 6 | xm10 net016 dp vrefp vrefp pch_lvt w=300e-9 l=40e-9 7 | xm3 net018 net016 vrefp vrefp pch_lvt w=600e-9 l=40e-9 8 | xm2 net010 net09 vrefp vrefp pch_lvt w=600e-9 l=40e-9 9 | xm12 net09 dn vrefp vrefp pch_lvt w=300e-9 l=40e-9 10 | xr2 iop net018 rppolywo l=49e-6 w=1e-6 11 | xr0 net010 ion rppolywo l=49e-6 w=1e-6 12 | .ends DAC 13 | -------------------------------------------------------------------------------- /pku/netlist/DAC.sp: -------------------------------------------------------------------------------- 1 | .topckt DAC dn dp ion iop vrefn vrefp vss_dac 2 | xm11 net09 dn vrefn vss_dac nch_lvt w=200e-9 l=40e-9 nf=1 3 | xm7 net016 dp vrefn vss_dac nch_lvt w=200e-9 l=40e-9 nf=1 4 | xm1 net018 net016 vrefn vss_dac nch_lvt w=400e-9 l=40e-9 nf=1 5 | xm0 net010 net09 vrefn vss_dac nch_lvt w=400e-9 l=40e-9 nf=1 6 | xm10 net016 dp vrefp vrefp pch_lvt w=300e-9 l=40e-9 nf=1 7 | xm3 net018 net016 vrefp vrefp pch_lvt w=600e-9 l=40e-9 nf=1 8 | xm2 net010 net09 vrefp vrefp pch_lvt w=600e-9 l=40e-9 nf=1 9 | xm12 net09 dn vrefp vrefp pch_lvt w=300e-9 l=40e-9 nf=1 10 | xr2 iop net018 rppolywo l=49e-6 w=1e-6 11 | xr0 net010 ion rppolywo l=49e-6 w=1e-6 12 | .ends DAC 13 | -------------------------------------------------------------------------------- /sfa/Telescopic_OTA_stacked_single_ended.sfa: -------------------------------------------------------------------------------- 1 | Telescopic_OTA_stacked_single_ended 2 | m14s m17s 3 | m14 m17 4 | m14s m16s 5 | m14s m1s 6 | m14 m1 7 | m13s m6s 8 | m13 m6 9 | m12 m9 10 | m12s m9s 11 | m14s m2s 12 | m14 m2 13 | m13s m7s 14 | m13 m7 15 | m12 m8 16 | m12s m8s 17 | m17s m1s 18 | m17 m1 19 | m17s m2s 20 | m17 m2 21 | m16s m1s 22 | m16s m2s 23 | m12s m4s 24 | m12 m4 25 | m12s m5s 26 | m15s m4s 27 | m15 m4 28 | m15s m5s 29 | m11s m3s 30 | m11 m3 31 | m10s m8s 32 | m10 m8 33 | m17 m7 34 | m17s m7s 35 | m11s m0s 36 | m11 m0 37 | m10s m9s 38 | m10 m9 39 | m17 m6 40 | m17s m6s 41 | m3s m0s 42 | m3 m0 43 | m8s m9s 44 | m8 m9 45 | m7 m6 46 | m7s m6s 47 | m2 m1 48 | m2s m1s 49 | 50 | -------------------------------------------------------------------------------- /sym/adc1.sym: -------------------------------------------------------------------------------- 1 | adc1 2 | xr47 xr28 3 | xr21 xr20 4 | xr23 xr22 5 | xr25 xr24 6 | xr19 xr18 7 | xr16 xr17 8 | xc0 xc4 9 | xc2 xc1 10 | rr1 rr2 11 | 12 | adc1/input_res 13 | xr13 xr14 14 | 15 | adc1/xi20 16 | xm40 xm43 17 | xm49 xm50 18 | xm56 xm57 19 | xm61 xm8 20 | xr8 xr2 21 | xc1 xc0 22 | xm9 xm67 23 | xr1 xr10 24 | xc7 xc6 25 | xc4 xc3 26 | xm7 xm10 27 | xm53 xm12 28 | xm66 xm64 29 | 30 | adc1/xi22 31 | xm40 xm43 32 | xm49 xm50 33 | xm56 xm57 34 | xm61 xm8 35 | xr8 xr2 36 | xc1 xc0 37 | xm9 xm67 38 | xr1 xr10 39 | xc7 xc6 40 | xc4 xc3 41 | xm7 xm10 42 | xm53 xm12 43 | xm66 xm64 44 | 45 | adc1/xi19 46 | xm6 xm5 47 | xm2 xm18 48 | xm3 xm4 49 | xm12 xm1 50 | xm8 xm15 51 | xm13 xm14 52 | xm16 xm17 53 | xm22 xm0 54 | 55 | -------------------------------------------------------------------------------- /open/block/dac2.sp: -------------------------------------------------------------------------------- 1 | .topckt NRZ_TRI_DAC_v3_dnw dinn dinnb dinp dinpb ein einb gnd ioutn ioutp vbn1 vbn2 vbp1 vbp2 vcm vdddac 2 | xm16 vbp2 vbp2 vbp2 vdddac pch w=4e-6 l=500e-9 3 | xm2 vcm2 vbp2 v2 vdddac pch w=4e-6 l=500e-9 4 | xm7 vcm einb vcm2 vdddac pch w=800e-9 l=40e-9 5 | xm17 ioutp dinnb vcm2 vdddac pch w=800e-9 l=40e-9 6 | xm6 ioutn dinpb vcm2 vdddac pch w=800e-9 l=40e-9 7 | xm3 v2 vbp1 vdddac vdddac pch w=6e-6 l=1.5e-6 8 | xm12 v1 vbn1 gnd gnd nch w=2.1e-6 l=1.5e-6 9 | xm13 vcm1 vbn2 v1 gnd nch w=4e-6 l=500e-9 10 | xm21 vbn2 vbn2 vbn2 gnd nch w=4e-6 l=500e-9 11 | xm18 ioutp dinp vcm1 gnd nch w=400e-9 l=40e-9 12 | xm15 ioutn dinn vcm1 gnd nch w=400e-9 l=40e-9 13 | xm14 vcm ein vcm1 gnd nch w=400e-9 l=40e-9 14 | .ends NRZ_TRI_DAC_v3_dnw 15 | 16 | -------------------------------------------------------------------------------- /open/block/ota1.sp: -------------------------------------------------------------------------------- 1 | .topckt 2019_10_01_5t_OTA gnd vout vdd 2 | m5 net2 net2 net5s gnd nch_lvt w=270e-9 l=20e-9 nf=10 3 | m5s net5s net2 gnd gnd nch_lvt w=270e-9 l=20e-9 nf=10 4 | m4 net10 net2 net4s gnd nch_lvt w=270e-9 l=20e-9 nf=40 5 | m4s net4s net2 gnd gnd nch_lvt w=270e-9 l=20e-9 nf=40 6 | m3 vout net15 net3s gnd nch_lvt w=270e-9 l=20e-9 nf=160 7 | m3s net3s net15 net10 gnd nch_lvt w=270e-9 l=20e-9 nf=160 8 | m0 net8 net17 net0s gnd nch_lvt w=270e-9 l=20e-9 nf=160 9 | m0s net0s net17 net10 gnd nch_lvt w=270e-9 l=20e-9 nf=160 10 | m2 vout net8 net2s vdd pch_lvt w=270e-9 l=20e-9 nf=100 11 | m2s net2s net8 vdd vdd pch_lvt w=270e-9 l=20e-9 nf=100 12 | m1 net8 net8 net1s vdd pch_lvt w=270e-9 l=20e-9 nf=100 13 | m1s net1s net8 vdd vdd pch_lvt w=270e-9 l=20e-9 nf=100 14 | .ends 2019_10_01_5t_OTA 15 | -------------------------------------------------------------------------------- /pku/netlist/2019_10_01_5t_OTA.sp: -------------------------------------------------------------------------------- 1 | .topckt 2019_10_01_5t_OTA gnd vout vdd 2 | m5 net2 net2 net5s gnd nch_lvt w=270e-9 l=20e-9 nf=10 3 | m5s net5s net2 gnd gnd nch_lvt w=270e-9 l=20e-9 nf=10 4 | m4 net10 net2 net4s gnd nch_lvt w=270e-9 l=20e-9 nf=40 5 | m4s net4s net2 gnd gnd nch_lvt w=270e-9 l=20e-9 nf=40 6 | m3 vout net15 net3s gnd nch_lvt w=270e-9 l=20e-9 nf=160 7 | m3s net3s net15 net10 gnd nch_lvt w=270e-9 l=20e-9 nf=160 8 | m0 net8 net17 net0s gnd nch_lvt w=270e-9 l=20e-9 nf=160 9 | m0s net0s net17 net10 gnd nch_lvt w=270e-9 l=20e-9 nf=160 10 | m2 vout net8 net2s vdd pch_lvt w=270e-9 l=20e-9 nf=100 11 | m2s net2s net8 vdd vdd pch_lvt w=270e-9 l=20e-9 nf=100 12 | m1 net8 net8 net1s vdd pch_lvt w=270e-9 l=20e-9 nf=100 13 | m1s net1s net8 vdd vdd pch_lvt w=270e-9 l=20e-9 nf=100 14 | .ends 2019_10_01_5t_OTA 15 | -------------------------------------------------------------------------------- /pku/netlist/NRZ_TRI_DAC_v3_dnw.sp: -------------------------------------------------------------------------------- 1 | .topckt NRZ_TRI_DAC_v3_dnw dinn dinnb dinp dinpb ein einb gnd ioutn ioutp vbn1 vbn2 vbp1 vbp2 vcm vdddac 2 | xm16 vbp2 vbp2 vbp2 vdddac pch w=4e-6 l=500e-9 nf=4 3 | xm2 vcm2 vbp2 v2 vdddac pch w=4e-6 l=500e-9 nf=4 4 | xm7 vcm einb vcm2 vdddac pch w=800e-9 l=40e-9 nf=2 5 | xm17 ioutp dinnb vcm2 vdddac pch w=800e-9 l=40e-9 nf=2 6 | xm6 ioutn dinpb vcm2 vdddac pch w=800e-9 l=40e-9 nf=2 7 | xm3 v2 vbp1 vdddac vdddac pch w=6e-6 l=1.5e-6 nf=6 8 | xm12 v1 vbn1 gnd gnd nch w=2.1e-6 l=1.5e-6 nf=6 9 | xm13 vcm1 vbn2 v1 gnd nch w=4e-6 l=500e-9 nf=4 10 | xm21 vbn2 vbn2 vbn2 gnd nch w=4e-6 l=500e-9 nf=4 11 | xm18 ioutp dinp vcm1 gnd nch w=400e-9 l=40e-9 nf=2 12 | xm15 ioutn dinn vcm1 gnd nch w=400e-9 l=40e-9 nf=2 13 | xm14 vcm ein vcm1 gnd nch w=400e-9 l=40e-9 nf=2 14 | .ends NRZ_TRI_DAC_v3_dnw 15 | 16 | -------------------------------------------------------------------------------- /open/block/ota3.sp: -------------------------------------------------------------------------------- 1 | .topckt Current_mirror_OTA voutp gnd vinn id vinp vbiasnd vdd! 2 | m17 net16 vinn net24 gnd nch_lvt w=27e-9 l=20e-9 nf=28 3 | m16 net24 id gnd gnd nch_lvt w=27e-9 l=20e-9 nf=10 4 | m15 net27 vinp net24 gnd nch_lvt w=27e-9 l=20e-9 nf=28 5 | m14 id id gnd gnd nch_lvt w=27e-9 l=20e-9 nf=10 6 | m11 vbiasnd vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nf=24 7 | m10 voutp vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nf=24 8 | m21 net16 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=60 9 | m20 m20stack net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=240 10 | m20s vbiasnd net16 m20stack vdd! pch_lvt w=27e-9 l=20e-9 nf=240 11 | m19 net27 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=60 12 | m18 m18stack net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=240 13 | m18s voutp net27 m18stack vdd! pch_lvt w=27e-9 l=20e-9 nf=240 14 | .ends Current_mirror_OTA 15 | -------------------------------------------------------------------------------- /pku/netlist/Current_mirror_OTA.sp: -------------------------------------------------------------------------------- 1 | .topckt Current_mirror_OTA voutp gnd vinn id vinp vbiasnd vdd! 2 | m17 net16 vinn net24 gnd nch_lvt w=27e-9 l=20e-9 nf=28 3 | m16 net24 id gnd gnd nch_lvt w=27e-9 l=20e-9 nf=10 4 | m15 net27 vinp net24 gnd nch_lvt w=27e-9 l=20e-9 nf=28 5 | m14 id id gnd gnd nch_lvt w=27e-9 l=20e-9 nf=10 6 | m11 vbiasnd vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nf=24 7 | m10 voutp vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nf=24 8 | m21 net16 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=60 9 | m20 m20stack net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=240 10 | m20s vbiasnd net16 m20stack vdd! pch_lvt w=27e-9 l=20e-9 nf=240 11 | m19 net27 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=60 12 | m18 m18stack net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nf=240 13 | m18s voutp net27 m18stack vdd! pch_lvt w=27e-9 l=20e-9 nf=240 14 | .ends Current_mirror_OTA 15 | -------------------------------------------------------------------------------- /open/block/ota6.sp: -------------------------------------------------------------------------------- 1 | .topckt Gm1_v5_Practice ibias vdd vim vip vom vop vss 2 | xm8 net074 ntail1 vss vss nch_lvt w=3.22e-6 l=120e-9 3 | xm2 vdd ibias vdd vdd pch_lvt w=2.95e-6 l=3.3e-6 4 | xm4 vdd ibias vdd vdd pch_lvt w=2.95e-6 l=3.3e-6 5 | xm12 ibias ibias vdd vdd pch_lvt w=585e-9 l=120e-9 6 | xm11 vom ibias vdd vdd pch_lvt w=2.34e-6 l=120e-9 7 | xm15 ibias ibias vdd vdd pch_lvt w=585e-9 l=120e-9 8 | xm14 vop ibias vdd vdd pch_lvt w=2.34e-6 l=120e-9 9 | xm26 vop vim net074 net074 nch_lvt w=1.7e-6 l=120e-9 10 | xm27 vom vip net074 net074 nch_lvt w=1.7e-6 l=120e-9 11 | xc21 ntail1 vom vss cap 12 | xc22 vop ntail1 vss cap 13 | xr12 ntail1 vop vss rppolywo l=49e-6 w=1e-6 14 | xr11 vom ntail1 vss rppolywo l=49e-6 w=1e-6 15 | xm3 vss ntail1 vss vss nch_lvt w=2.5e-6 l=2.2e-6 16 | xm0 vss ntail1 vss vss nch_lvt w=2.5e-6 l=2.2e-6 17 | .ends Gm1_v5_Practice 18 | 19 | -------------------------------------------------------------------------------- /pku/netlist/Gm1_v5_Practice.sp: -------------------------------------------------------------------------------- 1 | .topckt Gm1_v5_Practice ibias vdd vim vip vom vop vss 2 | xm8 net074 ntail1 vss vss nch_lvt w=3.22e-6 l=120e-9 nf=4 3 | xm2 vdd ibias vdd vdd pch_lvt w=2.95e-6 l=3.3e-6 nf=1 4 | xm4 vdd ibias vdd vdd pch_lvt w=2.95e-6 l=3.3e-6 nf=1 5 | xm12 ibias ibias vdd vdd pch_lvt w=585e-9 l=120e-9 nf=1 6 | xm11 vom ibias vdd vdd pch_lvt w=2.34e-6 l=120e-9 nf=4 7 | xm15 ibias ibias vdd vdd pch_lvt w=585e-9 l=120e-9 nf=1 8 | xm14 vop ibias vdd vdd pch_lvt w=2.34e-6 l=120e-9 nf=4 9 | xm26 vop vim net074 net074 nch_lvt w=1.7e-6 l=120e-9 nf=4 10 | xm27 vom vip net074 net074 nch_lvt w=1.7e-6 l=120e-9 nf=4 11 | xc21 ntail1 vom vss cap 12 | xc22 vop ntail1 vss cap 13 | xr12 ntail1 vop vss rppolywo l=49e-6 w=1e-6 14 | xr11 vom ntail1 vss rppolywo l=49e-6 w=1e-6 15 | xm3 vss ntail1 vss vss nch_lvt w=2.5e-6 l=2.2e-6 nf=1 16 | xm0 vss ntail1 vss vss nch_lvt w=2.5e-6 l=2.2e-6 nf=1 17 | .ends Gm1_v5_Practice 18 | 19 | -------------------------------------------------------------------------------- /open/block/comp5.sp: -------------------------------------------------------------------------------- 1 | .topckt myComparator_v3 clk gnd outm outp vdd _net0 _net1 2 | xm0 gnd intern gnd gnd nch_lvt w=1.05e-6 l=1e-6 3 | xm22 gnd interp gnd gnd nch_lvt w=1.05e-6 l=1e-6 4 | xm16 outm crossp gnd gnd nch_lvt w=1.44e-6 l=40e-9 5 | xm17 outp crossn gnd gnd nch_lvt w=1.44e-6 l=40e-9 6 | xm4 crossn crossp intern gnd nch_lvt w=1.92e-6 l=40e-9 7 | xm3 crossp crossn interp gnd nch_lvt w=1.92e-6 l=40e-9 8 | xm7 net069 clk gnd gnd nch_lvt w=6.9e-6 l=40e-9 9 | xm5 intern _net0 net069 gnd nch_lvt w=14.4e-6 l=40e-9 10 | xm6 interp _net1 net069 gnd nch_lvt w=14.4e-6 l=40e-9 11 | xm8 outm crossp vdd vdd pch_lvt w=1.92e-6 l=40e-9 12 | xm18 intern clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 13 | xm15 outp crossn vdd vdd pch_lvt w=1.92e-6 l=40e-9 14 | xm2 interp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 15 | xm1 crossn clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 16 | xm12 crossp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 17 | xm14 crossn crossp vdd vdd pch_lvt w=3.84e-6 l=40e-9 18 | xm13 crossp crossn vdd vdd pch_lvt w=3.84e-6 l=40e-9 19 | .ends myComparator_v3 20 | -------------------------------------------------------------------------------- /open/block/comp6.sp: -------------------------------------------------------------------------------- 1 | .topckt COMPARATOR_PRE_AMP clk crossn crossp gnd intern interp outm outp vdd _net0 _net1 2 | xm0 gnd intern gnd gnd nch_lvt w=1.05e-6 l=1e-6 3 | xm22 gnd interp gnd gnd nch_lvt w=1.05e-6 l=1e-6 4 | xm16 outm crossp gnd gnd nch_lvt w=1.44e-6 l=40e-9 5 | xm17 outp crossn gnd gnd nch_lvt w=1.44e-6 l=40e-9 6 | xm4 crossn crossp intern gnd nch_lvt w=1.92e-6 l=40e-9 7 | xm3 crossp crossn interp gnd nch_lvt w=1.92e-6 l=40e-9 8 | xm7 net050 clk gnd gnd nch_lvt w=8.64e-6 l=40e-9 9 | xm5 intern _net0 net050 gnd nch_lvt w=9.6e-6 l=40e-9 10 | xm6 interp _net1 net050 gnd nch_lvt w=9.6e-6 l=40e-9 11 | xm8 outm crossp vdd vdd pch_lvt w=2.88e-6 l=40e-9 12 | xm18 intern clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 13 | xm15 outp crossn vdd vdd pch_lvt w=2.88e-6 l=40e-9 14 | xm19 interp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 15 | xm10 crossn clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 16 | xm12 crossp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 17 | xm14 crossn crossp vdd vdd pch_lvt w=3.84e-6 l=40e-9 18 | xm13 crossp crossn vdd vdd pch_lvt w=3.84e-6 l=40e-9 19 | .ends COMPARATOR_PRE_AMP 20 | 21 | -------------------------------------------------------------------------------- /sym/ADC_CORE.sym: -------------------------------------------------------------------------------- 1 | ADC_CORE 2 | xi11 xi12 3 | xi0 xi1 4 | 5 | ADC_CORE/xi13 6 | xi1 xi0 7 | 8 | ADC_CORE/xi3/xi1 9 | xi0 xi1<1> xi1<2> xi1<3> xi1<4> xi1<5> xi1<6> xi1<7> xi1<8> xi1<9> 10 | xi2<1> xi2<2> xi2<3> xi2<4> xi2<5> xi2<6> xi2<7> xi2<8> xi2<9> xi3<1> xi3<2> xi3<3> xi3<4> xi3<5> xi3<6> xi3<7> xi3<8> xi3<9> 11 | 12 | ADC_CORE/xi3/xi0 13 | xi18<1> xi18<2> xi18<3> xi18<4> xi18<5> xi18<6> xi18<7> xi18<8> xi18<9> xi18<10> xi17 14 | xi16<1> xi16<2> xi16<3> xi16<4> xi16<5> xi16<6> xi16<7> xi16<8> xi16<9> xi16<10> 15 | 16 | ADC_CORE/xi0/xi2 17 | xi3 xi4 xi5 xi6 xi7 xi8 xi9 xi1 xi2 18 | 19 | ADC_CORE/xi1/xi2 20 | xi3 xi4 xi5 xi6 xi7 xi8 xi9 xi1 xi2 21 | 22 | ADC_CORE/xi3/xi1/xi0 23 | xi0 xi1 24 | 25 | ADC_CORE/xi3/xi1/xi1<1> 26 | xi0 xi1 27 | 28 | ADC_CORE/xi3/xi1/xi1<2> 29 | xi0 xi1 30 | 31 | ADC_CORE/xi3/xi1/xi1<3> 32 | xi0 xi1 33 | 34 | ADC_CORE/xi3/xi1/xi1<4> 35 | xi0 xi1 36 | 37 | ADC_CORE/xi3/xi1/xi1<5> 38 | xi0 xi1 39 | 40 | ADC_CORE/xi3/xi1/xi1<6> 41 | xi0 xi1 42 | 43 | ADC_CORE/xi3/xi1/xi1<7> 44 | xi0 xi1 45 | 46 | ADC_CORE/xi3/xi1/xi1<8> 47 | xi0 xi1 48 | 49 | ADC_CORE/xi3/xi1/xi1<9> 50 | xi0 xi1 51 | 52 | -------------------------------------------------------------------------------- /pku/netlist/myComparator_v3.sp: -------------------------------------------------------------------------------- 1 | .topckt myComparator_v3 clk gnd outm outp vdd _net0 _net1 2 | xm0 gnd intern gnd gnd nch_lvt w=1.05e-6 l=1e-6 nf=1 3 | xm22 gnd interp gnd gnd nch_lvt w=1.05e-6 l=1e-6 nf=1 4 | xm16 outm crossp gnd gnd nch_lvt w=1.44e-6 l=40e-9 nf=4 5 | xm17 outp crossn gnd gnd nch_lvt w=1.44e-6 l=40e-9 nf=4 6 | xm4 crossn crossp intern gnd nch_lvt w=1.92e-6 l=40e-9 nf=4 7 | xm3 crossp crossn interp gnd nch_lvt w=1.92e-6 l=40e-9 nf=4 8 | xm7 net069 clk gnd gnd nch_lvt w=6.9e-6 l=40e-9 nf=15 9 | xm5 intern _net0 net069 gnd nch_lvt w=14.4e-6 l=40e-9 nf=15 10 | xm6 interp _net1 net069 gnd nch_lvt w=14.4e-6 l=40e-9 nf=15 11 | xm8 outm crossp vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 12 | xm18 intern clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 13 | xm15 outp crossn vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 14 | xm2 interp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 15 | xm1 crossn clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 16 | xm12 crossp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 17 | xm14 crossn crossp vdd vdd pch_lvt w=3.84e-6 l=40e-9 nf=8 18 | xm13 crossp crossn vdd vdd pch_lvt w=3.84e-6 l=40e-9 nf=8 19 | .ends myComparator_v3 20 | -------------------------------------------------------------------------------- /pku/netlist/COMPARATOR_PRE_AMP.sp: -------------------------------------------------------------------------------- 1 | .topckt COMPARATOR_PRE_AMP clk crossn crossp gnd intern interp outm outp vdd _net0 _net1 2 | xm0 gnd intern gnd gnd nch_lvt w=1.05e-6 l=1e-6 nf=1 3 | xm22 gnd interp gnd gnd nch_lvt w=1.05e-6 l=1e-6 nf=1 4 | xm16 outm crossp gnd gnd nch_lvt w=1.44e-6 l=40e-9 nf=12 5 | xm17 outp crossn gnd gnd nch_lvt w=1.44e-6 l=40e-9 nf=12 6 | xm4 crossn crossp intern gnd nch_lvt w=1.92e-6 l=40e-9 nf=16 7 | xm3 crossp crossn interp gnd nch_lvt w=1.92e-6 l=40e-9 nf=16 8 | xm7 net050 clk gnd gnd nch_lvt w=8.64e-6 l=40e-9 nf=72 9 | xm5 intern _net0 net050 gnd nch_lvt w=9.6e-6 l=40e-9 nf=10 10 | xm6 interp _net1 net050 gnd nch_lvt w=9.6e-6 l=40e-9 nf=10 11 | xm8 outm crossp vdd vdd pch_lvt w=2.88e-6 l=40e-9 nf=6 12 | xm18 intern clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=1 13 | xm15 outp crossn vdd vdd pch_lvt w=2.88e-6 l=40e-9 nf=6 14 | xm19 interp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=1 15 | xm10 crossn clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=1 16 | xm12 crossp clk vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=1 17 | xm14 crossn crossp vdd vdd pch_lvt w=3.84e-6 l=40e-9 nf=32 18 | xm13 crossp crossn vdd vdd pch_lvt w=3.84e-6 l=40e-9 nf=32 19 | .ends COMPARATOR_PRE_AMP 20 | 21 | -------------------------------------------------------------------------------- /sfa/CLK_COMP.sfa: -------------------------------------------------------------------------------- 1 | CLK_COMP 2 | xm103 xm14 3 | xm103 xm71 4 | xm124 xm14 5 | xm124 xm71 6 | xm16 xm35 7 | xm20 xm115 8 | xm16 xm73 9 | xm20 xm116 10 | xm16 xm19 11 | xm20 xm21 12 | xm114 xm24 13 | xm5 xm8 14 | xm3 xm1 15 | xm113 xm22 16 | xm26 xm25 17 | xm114 xm85 18 | xm5 xm9 19 | xm3 xm10 20 | xm113 xm17 21 | xm114 xm8 22 | xm5 xm24 23 | xm3 xm1 24 | xm113 xm22 25 | xm26 xm25 26 | xm114 xm9 27 | xm5 xm85 28 | xm3 xm10 29 | xm113 xm17 30 | xm122 xm25 31 | xm122 xm6 32 | xm121 xm7 33 | xm122 xm119 34 | xm121 xm120 35 | xm122 xm26 36 | xm25 xm6 37 | xm25 xm119 38 | xm24 xm85 39 | xm1 xm10 40 | xm22 xm17 41 | xm8 xm9 42 | xm24 xm9 43 | xm1 xm10 44 | xm22 xm17 45 | xm8 xm85 46 | xm6 xm119 47 | xm7 xm120 48 | xm6 xm26 49 | xm119 xm26 50 | xm35 xm19 51 | xm115 xm21 52 | xm73 xm19 53 | xm116 xm21 54 | xm68 xm57 55 | xm70 xm55 56 | xm116 xm115 57 | xm73 xm35 58 | xm69 xm56 59 | xm17 xm21 60 | xm17 xm12 61 | xm17 xm27 62 | xm17 xm20 63 | xm102 xm70 64 | xm102 xm55 65 | xm21 xm113 66 | xm21 xm22 67 | xm21 xm12 68 | xm21 xm27 69 | xm113 xm12 70 | xm113 xm27 71 | xm113 xm20 72 | xm22 xm12 73 | xm22 xm27 74 | xm22 xm20 75 | xm70 xm125 76 | xm125 xm55 77 | xm12 xm27 78 | xm12 xm20 79 | xm27 xm20 80 | 81 | -------------------------------------------------------------------------------- /comp_mod.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt myComparator_v3 clk gnd outm outp vdd _net0 _net1 5 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 6 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 7 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 8 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 9 | xm7 net069 clk gnd gnd nch_lvt_mac l=40e-9 w=6.9e-6 multi=1 nf=15 10 | xm5 intern _net0 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 multi=1 nf=15 11 | xm6 interp _net1 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 multi=1 nf=15 12 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 13 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 14 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 15 | xm2 interp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 16 | xm1 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 17 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 18 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 19 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 20 | .ends myComparator_v3 21 | -------------------------------------------------------------------------------- /sym/CTDTDSM_V3.sym: -------------------------------------------------------------------------------- 1 | CTDTDSM_V3 2 | xi7<1> xi7<2> xi7<3> xi7<4> xi7<5> xi7<6> xi7<7> xi7<8> xi7<9> xi7<10> xi7<11> xi7<12> xi7<13> xi7<14> xi7<15> 3 | xr6 xr7 4 | 5 | CTDTDSM_V3/xi58 6 | xi197<1> xi197<2> 7 | xi170 xi172 8 | 9 | CTDTDSM_V3/xi58/xi173 10 | xi14 xi18 11 | xi15 xi17 xi19 xi12 12 | xi134 xi16 13 | 14 | CTDTDSM_V3/xi58/xi177 15 | xi18 xi34 xi35 xi36 16 | xi1<0> xi1<1> xi1<2> xi1<3> 17 | 18 | CTDTDSM_V3/xi58/xi174 19 | xi352 xi373 20 | 21 | CTDTDSM_V3/xi58/xi174/xi358/xi334 22 | xi11 xi8 23 | xi12 xi15 24 | xi14 xi16 25 | xi17 xi18 26 | 27 | CTDTDSM_V3/xi58/xi174/xi345 28 | xi4<0> xi4<1> xi4<2> xi4<3> 29 | xi3<1> xi3<2> xi3<3> xi3<4> 30 | 31 | CTDTDSM_V3/xi58/xi174/xi345/xi3<1> 32 | xi23 xi18 33 | xi11 xi26 34 | xi16 xi24 35 | 36 | CTDTDSM_V3/xi58/xi176 37 | xi14 xi18 38 | xi15 xi17 xi19 xi12 39 | xi134 xi16 40 | 41 | CTDTDSM_V3/xi58/xi172 42 | xi150 xi151 xi152 xi153 43 | xm1 xm0 44 | xi2<1> xi2<2> 45 | xi162 xi163 xi164 xi165 xi167 xi170 46 | xi169 xi161 47 | 48 | CTDTDSM_V3/xi58/xi170 49 | xi150 xi151 xi152 xi153 50 | xm1 xm0 51 | xi2<1> xi2<2> 52 | xi169 xi161 53 | xi162 xi163 xi164 xi165 xi167 xi170 54 | 55 | CTDTDSM_V3/xi39 56 | xc0 xc10 57 | xc1 xc7 58 | xc6 xc8 59 | xc5 xc9 60 | xm0 xm6 61 | xm2 xm8 62 | xm1 xm7 63 | 64 | -------------------------------------------------------------------------------- /Gm1_v5_Practice.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt Gm1_v5_Practice ibias vdd vim vip vom vop vss 5 | 6 | xm8 net074 ntail1 vss vss nch_hvt_mac l=120e-9 w=3.22e-6 multi=1 nf=4 7 | 8 | xm2 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 multi=1 nf=1 9 | 10 | xm4 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 multi=1 nf=1 11 | 12 | xm12 ibias ibias vdd vdd pch_lvt_mac l=120e-9 w=585e-9 multi=1 nf=1 13 | 14 | xm11 vom ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 multi=1 nf=4 15 | 16 | xm15 ibias ibias vdd vdd pch_lvt_mac l=120e-9 w=585e-9 multi=1 nf=1 17 | 18 | xm14 vop ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 multi=1 nf=4 19 | 20 | xm26 vop vim net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 multi=1 nf=4 21 | 22 | xm27 vom vip net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 multi=1 nf=4 23 | 24 | xc21 ntail1 vom vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 25 | 26 | xc22 vop ntail1 vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 27 | xr12 ntail1 vop vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 28 | 29 | xr11 vom ntail1 vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 30 | 31 | 32 | xm3 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 multi=1 nf=1 33 | 34 | xm0 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 multi=1 nf=1 35 | 36 | 37 | .ends Gm1_v5_Practice 38 | -------------------------------------------------------------------------------- /open/block/comp4.sp: -------------------------------------------------------------------------------- 1 | .topckt Comparator_not_clocked cgnd Vdd Vn Vp Von Vop Vout 2 | M21 net44 cgnd Vdd Vdd pch_lvt l=1.32e-6 w=120.0e-9 3 | M5 net10 Vn net7 cgnd nch_lvt l=120.0e-9 w=600e-9 4 | M0 net5 Vp net7 cgnd nch_lvt l=120.0e-9 w=600e-9 5 | M11 net7 net44 cgnd cgnd nch_lvt l=120.0e-9 w=1.2e-6 6 | M9 net44 net44 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 7 | M10 Vop Von net18 cgnd nch_lvt l=120.0e-9 w=600e-9 8 | M8 Von Vop net18 cgnd nch_lvt l=120.0e-9 w=600e-9 9 | M7 Von Von net18 cgnd nch_lvt l=120.0e-9 w=600e-9 10 | M6 Vop Vop net18 cgnd nch_lvt l=120.0e-9 w=600e-9 11 | M20 net18 net18 cgnd cgnd nch_lvt l=120.0e-9 w=6e-6 12 | M18 net17 net13 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 13 | M16 Vout net23 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 14 | M14 net23 Vop net17 cgnd nch_lvt l=120.0e-9 w=600e-9 15 | M12 net13 Von net17 cgnd nch_lvt l=120.0e-9 w=600e-9 16 | M3 Vop net5 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 17 | M2 net5 net5 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 18 | M4 Von net10 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 19 | M1 net10 net10 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 20 | M19 net14 net13 Vdd Vdd pch_lvt l=120.0e-9 w=900e-9 21 | M17 Vout net23 Vdd Vdd pch_lvt l=120.0e-9 w=900e-9 22 | M15 net23 Vop net14 net14 pch_lvt l=120.0e-9 w=900e-9 23 | M13 net13 Von net14 net14 pch_lvt l=120.0e-9 w=900e-9 24 | .ends Comparator_not_clocked 25 | -------------------------------------------------------------------------------- /open/block/ota2.sp: -------------------------------------------------------------------------------- 1 | .topckt Cascode_current_mirrot_OTA voutp gnd vbiasn vbiasnd vinn vinp vbiasp vdd! 2 | m25 voutp vbiasn net034 gnd nch_lvt w=27e-9 l=20e-9 nfin=24 3 | m24 vbiasnd vbiasn net033 gnd nch_lvt w=27e-9 l=20e-9 nfin=24 4 | m17 net16 vinn net24 gnd nch_lvt w=27e-9 l=20e-9 nfin=30 5 | m16 net24 net17 gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=15 6 | m15 net27 vinp net24 gnd nch_lvt w=27e-9 l=20e-9 nfin=30 7 | m14 net17 net17 gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=15 8 | m11 net033 vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=30 9 | m10 net034 vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=30 10 | m1nup vbiasn vbiasn net9b gnd nch_lvt w=270e-9 l=20e-9 nfin=3 11 | m1ndown net9b net9b gnd gnd nch_lvt w=270e-9 l=20e-9 nfin=5 12 | m1pup net8b net8b vdd! vdd! pch_lvt w=270e-9 l=20e-9 nfin=5 13 | m1pdown vbiasp vbiasp net8b net8b pch_lvt w=270e-9 l=20e-9 nfin=5 14 | m27 net27 vbiasp net021 net021 pch_lvt w=27e-9 l=20e-9 nfin=60 15 | m26 net16 vbiasp net015 net015 pch_lvt w=27e-9 l=20e-9 nfin=60 16 | m23 voutp vbiasp net024 net024 pch_lvt w=27e-9 l=20e-9 nfin=120 17 | m22 vbiasnd vbiasp net06 net06 pch_lvt w=27e-9 l=20e-9 nfin=120 18 | m21 net015 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=5 19 | m20 net06 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=10 20 | m19 net021 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=5 21 | m18 net024 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=10 22 | .ends Cascode_current_mirrot_OTA 23 | -------------------------------------------------------------------------------- /pku/netlist/Cascode_current_mirrot_OTA.sp: -------------------------------------------------------------------------------- 1 | .topckt Cascode_current_mirrot_OTA voutp gnd vbiasn vbiasnd vinn vinp vbiasp vdd! 2 | m25 voutp vbiasn net034 gnd nch_lvt w=27e-9 l=20e-9 nfin=24 3 | m24 vbiasnd vbiasn net033 gnd nch_lvt w=27e-9 l=20e-9 nfin=24 4 | m17 net16 vinn net24 gnd nch_lvt w=27e-9 l=20e-9 nfin=30 5 | m16 net24 net17 gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=15 6 | m15 net27 vinp net24 gnd nch_lvt w=27e-9 l=20e-9 nfin=30 7 | m14 net17 net17 gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=15 8 | m11 net033 vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=30 9 | m10 net034 vbiasnd gnd gnd nch_lvt w=27e-9 l=20e-9 nfin=30 10 | m1nup vbiasn vbiasn net9b gnd nch_lvt w=270e-9 l=20e-9 nfin=3 11 | m1ndown net9b net9b gnd gnd nch_lvt w=270e-9 l=20e-9 nfin=5 12 | m1pup net8b net8b vdd! vdd! pch_lvt w=270e-9 l=20e-9 nfin=5 13 | m1pdown vbiasp vbiasp net8b net8b pch_lvt w=270e-9 l=20e-9 nfin=5 14 | m27 net27 vbiasp net021 net021 pch_lvt w=27e-9 l=20e-9 nfin=60 15 | m26 net16 vbiasp net015 net015 pch_lvt w=27e-9 l=20e-9 nfin=60 16 | m23 voutp vbiasp net024 net024 pch_lvt w=27e-9 l=20e-9 nfin=120 17 | m22 vbiasnd vbiasp net06 net06 pch_lvt w=27e-9 l=20e-9 nfin=120 18 | m21 net015 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=5 19 | m20 net06 net16 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=10 20 | m19 net021 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=5 21 | m18 net024 net27 vdd! vdd! pch_lvt w=27e-9 l=20e-9 nfin=10 22 | .ends Cascode_current_mirrot_OTA 23 | -------------------------------------------------------------------------------- /open/block/latch1.sp: -------------------------------------------------------------------------------- 1 | .topckt Retiming_Latch_common clkb d do dob vdd_d vss_d 2 | xm39 net025 net017 vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 3 | xm31 clk clkb vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 4 | xm33 vdd_d vss_d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 5 | xm16 do dob vdd_d vdd_d pch_lvt w=320e-9 l=40e-9 6 | xm26 clkn clk vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 7 | xm12 dob do vdd_d vdd_d pch_lvt w=320e-9 l=40e-9 8 | xm1 do clkn net36 vdd_d pch_lvt w=640e-9 l=40e-9 9 | xm0 net36 net025 vdd_d vdd_d pch_lvt w=640e-9 l=40e-9 10 | xm11 dob clkn net39 vdd_d pch_lvt w=640e-9 l=40e-9 11 | xm10 net39 net017 vdd_d vdd_d pch_lvt w=640e-9 l=40e-9 12 | xm37 net017 d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 13 | xm35 vdd_d vss_d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 14 | xm38 net025 net017 vss_d vss_d nch_lvt w=320e-9 l=40e-9 15 | xm30 clk clkb vss_d vss_d nch_lvt w=240e-9 l=40e-9 16 | xm17 do clk net37 vss_d nch_lvt w=320e-9 l=40e-9 17 | xm32 vdd_d vss_d vdd_d vss_d nch_lvt w=320e-9 l=40e-9 18 | xm27 clkn clk vss_d vss_d nch_lvt w=240e-9 l=40e-9 19 | xm13 dob clk net38 vss_d nch_lvt w=320e-9 l=40e-9 20 | xm36 net017 d vss_d vss_d nch_lvt w=320e-9 l=40e-9 21 | xm21 dob do vss_d vss_d nch_lvt w=160e-9 l=40e-9 22 | xm20 do dob vss_d vss_d nch_lvt w=160e-9 l=40e-9 23 | xm19 net38 net017 vss_d vss_d nch_lvt w=320e-9 l=40e-9 24 | xm34 vdd_d vss_d vdd_d vss_d nch_lvt w=320e-9 l=40e-9 25 | xm18 net37 net025 vss_d vss_d nch_lvt w=320e-9 l=40e-9 26 | .ends Retiming_Latch_common 27 | -------------------------------------------------------------------------------- /pku/netlist/Comparator_not_clocked.sp: -------------------------------------------------------------------------------- 1 | .topckt Comparator_not_clocked cgnd Vdd Vn Vp Von Vop Vout 2 | M21 net44 cgnd Vdd Vdd pch_lvt l=1.32e-6 w=120.0e-9 nf=1 3 | M5 net10 Vn net7 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 4 | M0 net5 Vp net7 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 5 | M11 net7 net44 cgnd cgnd nch_lvt l=120.0e-9 w=1.2e-6 nf=1 6 | M9 net44 net44 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 7 | M10 Vop Von net18 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 8 | M8 Von Vop net18 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 9 | M7 Von Von net18 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 10 | M6 Vop Vop net18 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 11 | M20 net18 net18 cgnd cgnd nch_lvt l=120.0e-9 w=6e-6 nf=1 12 | M18 net17 net13 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 13 | M16 Vout net23 cgnd cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 14 | M14 net23 Vop net17 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 15 | M12 net13 Von net17 cgnd nch_lvt l=120.0e-9 w=600e-9 nf=1 16 | M3 Vop net5 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 nf=1 17 | M2 net5 net5 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 nf=1 18 | M4 Von net10 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 nf=1 19 | M1 net10 net10 Vdd Vdd pch_lvt l=240.0e-9 w=1.8e-6 nf=1 20 | M19 net14 net13 Vdd Vdd pch_lvt l=120.0e-9 w=900e-9 nf=1 21 | M17 Vout net23 Vdd Vdd pch_lvt l=120.0e-9 w=900e-9 nf=1 22 | M15 net23 Vop net14 net14 pch_lvt l=120.0e-9 w=900e-9 nf=1 23 | M13 net13 Von net14 net14 pch_lvt l=120.0e-9 w=900e-9 nf=1 24 | .ends Comparator_not_clocked 25 | -------------------------------------------------------------------------------- /COMPARATOR_PRE_AMP.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt COMPARATOR_PRE_AMP clk crossn crossp gnd intern interp outm outp vdd _net0 _net1 5 | 6 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 7 | 8 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 9 | 10 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=12 11 | 12 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=12 13 | 14 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 15 | 16 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 17 | 18 | xm7 net050 clk gnd gnd nch_lvt_mac l=40e-9 w=8.64e-6 multi=1 nf=72 19 | 20 | xm5 intern _net0 net050 gnd nch_lvt_mac l=40e-9 w=9.6e-6 multi=1 nf=10 21 | 22 | xm6 interp _net1 net050 gnd nch_lvt_mac l=40e-9 w=9.6e-6 multi=1 nf=10 23 | 24 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=2.88e-6 multi=1 nf=6 25 | 26 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 27 | 28 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=2.88e-6 multi=1 nf=6 29 | 30 | xm19 interp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 31 | 32 | xm10 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 33 | 34 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 35 | 36 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=32 37 | 38 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=32 39 | .ends COMPARATOR_PRE_AMP 40 | -------------------------------------------------------------------------------- /pku/netlist/Retiming_Latch_common.sp: -------------------------------------------------------------------------------- 1 | .topckt Retiming_Latch_common clkb d do dob vdd_d vss_d 2 | xm39 net025 net017 vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 3 | xm31 clk clkb vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 4 | xm33 vdd_d vss_d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 5 | xm16 do dob vdd_d vdd_d pch_lvt w=320e-9 l=40e-9 nf=1 6 | xm26 clkn clk vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 7 | xm12 dob do vdd_d vdd_d pch_lvt w=320e-9 l=40e-9 nf=1 8 | xm1 do clkn net36 vdd_d pch_lvt w=640e-9 l=40e-9 nf=1 9 | xm0 net36 net025 vdd_d vdd_d pch_lvt w=640e-9 l=40e-9 nf=1 10 | xm11 dob clkn net39 vdd_d pch_lvt w=640e-9 l=40e-9 nf=1 11 | xm10 net39 net017 vdd_d vdd_d pch_lvt w=640e-9 l=40e-9 nf=1 12 | xm37 net017 d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 13 | xm35 vdd_d vss_d vdd_d vdd_d pch_lvt w=480e-9 l=40e-9 nf=1 14 | xm38 net025 net017 vss_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 15 | xm30 clk clkb vss_d vss_d nch_lvt w=240e-9 l=40e-9 nf=1 16 | xm17 do clk net37 vss_d nch_lvt w=320e-9 l=40e-9 nf=1 17 | xm32 vdd_d vss_d vdd_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 18 | xm27 clkn clk vss_d vss_d nch_lvt w=240e-9 l=40e-9 nf=1 19 | xm13 dob clk net38 vss_d nch_lvt w=320e-9 l=40e-9 nf=1 20 | xm36 net017 d vss_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 21 | xm21 dob do vss_d vss_d nch_lvt w=160e-9 l=40e-9 nf=1 22 | xm20 do dob vss_d vss_d nch_lvt w=160e-9 l=40e-9 nf=1 23 | xm19 net38 net017 vss_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 24 | xm34 vdd_d vss_d vdd_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 25 | xm18 net37 net025 vss_d vss_d nch_lvt w=320e-9 l=40e-9 nf=1 26 | .ends Retiming_Latch_common 27 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 3-Clause License 2 | 3 | Copyright (c) 2024, CODA-Team 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | 3. Neither the name of the copyright holder nor the names of its 16 | contributors may be used to endorse or promote products derived from 17 | this software without specific prior written permission. 18 | 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 23 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 26 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 27 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 28 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 | -------------------------------------------------------------------------------- /open/block/comp3.sp: -------------------------------------------------------------------------------- 1 | .topckt Comparator_1to7_0p7_lvt caln calp clke d db inm<0> inm<1> inp<0> inp<1> vb vdd vss 2 | xm29 vout1p clk vdd vdd pch_lvt w=1.6e-6 l=40e-9 3 | xm32 vout1m clk vdd vdd pch_lvt w=1.6e-6 l=40e-9 4 | xm18 clk net043 vdd vdd pch_lvt w=3.2e-6 l=40e-9 5 | xm19 net043 clke vdd vdd pch_lvt w=800e-9 l=40e-9 6 | xm7 db vout2p vdd vdd pch_lvt w=600e-9 l=40e-9 7 | xm28 vout2p vout2m vdd vdd pch_lvt w=12.8e-6 l=120e-9 8 | xm38 vdd vss vdd vdd pch_lvt w=800e-9 l=40e-9 9 | xm39 vdd vss vdd vdd pch_lvt w=3.2e-6 l=40e-9 10 | xm34 vout2m vout2p vdd vdd pch_lvt w=12.8e-6 l=120e-9 11 | xm25 vout2p clk vdd vdd pch_lvt w=800e-9 l=40e-9 12 | xm8 d vout2m vdd vdd pch_lvt w=600e-9 l=40e-9 13 | xm33 vout2m clk vdd vdd pch_lvt w=800e-9 l=40e-9 14 | xm35 net058 clk net040 vss nch_lvt w=1e-6 l=40e-9 15 | xm10 vout1m inp<0> net058 vss nch_lvt w=1.2e-6 l=200e-9 16 | xm36 net040 vb vss vss nch_lvt w=1e-6 l=40e-9 17 | xm9 d vout2m vss vss nch_lvt w=400e-9 l=40e-9 18 | xm48 vss vdd vss vss nch_lvt w=2.4e-6 l=160e-9 19 | xm41 vss vdd vss vss nch_lvt w=400e-9 l=40e-9 20 | xm43 vss vdd vss vss nch_lvt w=6e-6 l=40e-9 21 | xm42 vss vdd vss vss nch_lvt w=800e-9 l=40e-9 22 | xm11 vout1p inm<0> net058 vss nch_lvt w=1.2e-6 l=200e-9 23 | xm26 clk net043 vss vss nch_lvt w=800e-9 l=40e-9 24 | xm14 vout2p vout2m vout1p vss nch_lvt w=6.4e-6 l=120e-9 25 | xm12 vout1p inm<1> net057 vss nch_lvt w=1.2e-6 l=200e-9 26 | xm37 net041 vb vss vss nch_lvt w=1e-6 l=40e-9 27 | xm40 net057 clk net041 vss nch_lvt w=1e-6 l=40e-9 28 | xm6 db vout2p vss vss nch_lvt w=400e-9 l=40e-9 29 | xm27 net043 clke vss vss nch_lvt w=400e-9 l=40e-9 30 | xm13 vout1m inp<1> net057 vss nch_lvt w=1.2e-6 l=200e-9 31 | xm21 vout2m vout2p vout1m vss nch_lvt w=6.4e-6 l=120e-9 32 | m1 vout2m calp vout2m vout2m pch_lvt w=16e-6 l=500e-9 33 | m2 vout2p vss vout2p vout2p pch_lvt w=64e-6 l=500e-9 34 | m3 vout2p caln vout2p vout2p pch_lvt w=16e-6 l=500e-9 35 | m0 vout2m vss vout2m vout2m pch_lvt w=64e-6 l=500e-9 36 | .ends Comparator_1to7_0p7_lvt 37 | 38 | -------------------------------------------------------------------------------- /pku/netlist/Comparator_1to7_0p7_lvt.sp: -------------------------------------------------------------------------------- 1 | .topckt Comparator_1to7_0p7_lvt caln calp clke d db inm<0> inm<1> inp<0> inp<1> vb vdd vss 2 | xm29 vout1p clk vdd vdd pch_lvt w=1.6e-6 l=40e-9 nf=2 3 | xm32 vout1m clk vdd vdd pch_lvt w=1.6e-6 l=40e-9 nf=2 4 | xm18 clk net043 vdd vdd pch_lvt w=3.2e-6 l=40e-9 nf=4 5 | xm19 net043 clke vdd vdd pch_lvt w=800e-9 l=40e-9 nf=2 6 | xm7 db vout2p vdd vdd pch_lvt w=600e-9 l=40e-9 nf=1 7 | xm28 vout2p vout2m vdd vdd pch_lvt w=12.8e-6 l=120e-9 nf=8 8 | xm38 vdd vss vdd vdd pch_lvt w=800e-9 l=40e-9 nf=2 9 | xm39 vdd vss vdd vdd pch_lvt w=3.2e-6 l=40e-9 nf=4 10 | xm34 vout2m vout2p vdd vdd pch_lvt w=12.8e-6 l=120e-9 nf=8 11 | xm25 vout2p clk vdd vdd pch_lvt w=800e-9 l=40e-9 nf=2 12 | xm8 d vout2m vdd vdd pch_lvt w=600e-9 l=40e-9 nf=1 13 | xm33 vout2m clk vdd vdd pch_lvt w=800e-9 l=40e-9 nf=2 14 | xm35 net058 clk net040 vss nch_lvt w=1e-6 l=40e-9 nf=1 15 | xm10 vout1m inp<0> net058 vss nch_lvt w=1.2e-6 l=200e-9 nf=1 16 | xm36 net040 vb vss vss nch_lvt w=1e-6 l=40e-9 nf=1 17 | xm9 d vout2m vss vss nch_lvt w=400e-9 l=40e-9 nf=1 18 | xm48 vss vdd vss vss nch_lvt w=2.4e-6 l=160e-9 nf=2 19 | xm41 vss vdd vss vss nch_lvt w=400e-9 l=40e-9 nf=2 20 | xm43 vss vdd vss vss nch_lvt w=6e-6 l=40e-9 nf=6 21 | xm42 vss vdd vss vss nch_lvt w=800e-9 l=40e-9 nf=2 22 | xm11 vout1p inm<0> net058 vss nch_lvt w=1.2e-6 l=200e-9 nf=1 23 | xm26 clk net043 vss vss nch_lvt w=800e-9 l=40e-9 nf=2 24 | xm14 vout2p vout2m vout1p vss nch_lvt w=6.4e-6 l=120e-9 nf=8 25 | xm12 vout1p inm<1> net057 vss nch_lvt w=1.2e-6 l=200e-9 nf=1 26 | xm37 net041 vb vss vss nch_lvt w=1e-6 l=40e-9 nf=1 27 | xm40 net057 clk net041 vss nch_lvt w=1e-6 l=40e-9 nf=1 28 | xm6 db vout2p vss vss nch_lvt w=400e-9 l=40e-9 nf=1 29 | xm27 net043 clke vss vss nch_lvt w=400e-9 l=40e-9 nf=2 30 | xm13 vout1m inp<1> net057 vss nch_lvt w=1.2e-6 l=200e-9 nf=1 31 | xm21 vout2m vout2p vout1m vss nch_lvt w=6.4e-6 l=120e-9 nf=8 32 | m1 vout2m calp vout2m vout2m pch_lvt w=16e-6 l=500e-9 nf=2 33 | m2 vout2p vss vout2p vout2p pch_lvt w=64e-6 l=500e-9 nf=8 34 | m3 vout2p caln vout2p vout2p pch_lvt w=16e-6 l=500e-9 nf=2 35 | m0 vout2m vss vout2m vout2m pch_lvt w=64e-6 l=500e-9 nf=8 36 | .ends Comparator_1to7_0p7_lvt 37 | 38 | -------------------------------------------------------------------------------- /open/block/ota5.sp: -------------------------------------------------------------------------------- 1 | .topckt OTA_FF_2s_v3e avdd avss ibin in ip on op vcas vcmi 2 | m35 net057 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 3 | m34 cmfb vcmo net057 net057 pch_lvt w=5e-6 l=120e-9 4 | m33 net044 vcmi net057 net057 pch_lvt w=5e-6 l=120e-9 5 | m62 avdd ibin avdd avdd pch_lvt w=52.5e-6 l=120e-9 6 | m54 net59 net59 net59 net59 pch_lvt w=30e-6 l=120e-9 7 | m43 net5 net5 net5 net5 pch_lvt w=15e-6 l=120e-9 8 | m53 avdd ibin avdd avdd pch_lvt w=15e-6 l=120e-9 9 | m57 avdd ibin avdd avdd pch_lvt w=10e-6 l=120e-9 10 | m37 op in net59 net59 pch_lvt w=60e-6 l=120e-9 11 | m23 on ip net59 net59 pch_lvt w=60e-6 l=120e-9 12 | m63 net75 vcas net75 net75 pch_lvt w=20e-6 l=120e-9 13 | m58 net057 vcmo net057 net057 pch_lvt w=5e-6 l=120e-9 14 | m36 net59 ibin avdd avdd pch_lvt w=120e-6 l=120e-9 15 | m41 avdd ibin avdd avdd pch_lvt w=7.5e-6 l=120e-9 16 | m16 ibin vcas net75 net75 pch_lvt w=10e-6 l=120e-9 17 | m50 on1 ip net5 net5 pch_lvt w=5e-6 l=120e-9 18 | m48 net057 vcmi net057 net057 pch_lvt w=15e-6 l=120e-9 19 | m6 net75 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 20 | m4 net5 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 21 | m20 op1 in net5 net5 pch_lvt w=5e-6 l=120e-9 22 | m7 avss op1 avss avss nch_lvt w=4e-6 l=500e-9 23 | m2 avss on1 avss avss nch_lvt w=4e-6 l=500e-9 24 | m0 avss cmfb avss avss nch_lvt w=10e-6 l=120e-9 25 | m66 avss on1 avss avss nch_lvt w=2e-6 l=120e-9 26 | m64 avss op1 avss avss nch_lvt w=2e-6 l=120e-9 27 | m55 avss avss avss avss nch_lvt w=2e-6 l=120e-9 28 | m21 on op1 avss avss nch_lvt w=12e-6 l=120e-9 29 | m19 op on1 avss avss nch_lvt w=12e-6 l=120e-9 30 | m29 cmfb cmfb avss avss nch_lvt w=1e-6 l=120e-9 31 | m14 op1 cmfb avss avss nch_lvt w=1e-6 l=120e-9 32 | m13 on1 cmfb avss avss nch_lvt w=1e-6 l=120e-9 33 | m59 avss net044 avss avss nch_lvt w=2e-6 l=120e-9 34 | m30 net044 net044 avss avss nch_lvt w=1e-6 l=120e-9 35 | m56 avss cmfb avss avss nch_lvt w=2e-6 l=120e-9 36 | xc4 on vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 37 | xc5 op vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 38 | xr12 vcmo op avss rppolywo_m lr=20e-6 wr=1e-6 39 | xr13 on vcmo avss rppolywo_m lr=20e-6 wr=1e-6 40 | .ends OTA_FF_2s_v3e 41 | 42 | -------------------------------------------------------------------------------- /pku/netlist/OTA_FF_2s_v3e.sp: -------------------------------------------------------------------------------- 1 | .topckt OTA_FF_2s_v3e avdd avss ibin in ip on op vcas vcmi 2 | m35 net057 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 nf=2 3 | m34 cmfb vcmo net057 net057 pch_lvt w=5e-6 l=120e-9 nf=1 4 | m33 net044 vcmi net057 net057 pch_lvt w=5e-6 l=120e-9 nf=1 5 | m62 avdd ibin avdd avdd pch_lvt w=52.5e-6 l=120e-9 nf=21 6 | m54 net59 net59 net59 net59 pch_lvt w=30e-6 l=120e-9 nf=12 7 | m43 net5 net5 net5 net5 pch_lvt w=15e-6 l=120e-9 nf=6 8 | m53 avdd ibin avdd avdd pch_lvt w=15e-6 l=120e-9 nf=6 9 | m57 avdd ibin avdd avdd pch_lvt w=10e-6 l=120e-9 nf=4 10 | m37 op in net59 net59 pch_lvt w=60e-6 l=120e-9 nf=12 11 | m23 on ip net59 net59 pch_lvt w=60e-6 l=120e-9 nf=12 12 | m63 net75 vcas net75 net75 pch_lvt w=20e-6 l=120e-9 nf=8 13 | m58 net057 vcmo net057 net057 pch_lvt w=5e-6 l=120e-9 nf=2 14 | m36 net59 ibin avdd avdd pch_lvt w=120e-6 l=120e-9 nf=24 15 | m41 avdd ibin avdd avdd pch_lvt w=7.5e-6 l=120e-9 nf=3 16 | m16 ibin vcas net75 net75 pch_lvt w=10e-6 l=120e-9 nf=2 17 | m50 on1 ip net5 net5 pch_lvt w=5e-6 l=120e-9 nf=1 18 | m48 net057 vcmi net057 net057 pch_lvt w=15e-6 l=120e-9 nf=6 19 | m6 net75 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 nf=2 20 | m4 net5 ibin avdd avdd pch_lvt w=10e-6 l=120e-9 nf=2 21 | m20 op1 in net5 net5 pch_lvt w=5e-6 l=120e-9 nf=1 22 | m7 avss op1 avss avss nch_lvt w=4e-6 l=500e-9 nf=4 23 | m2 avss on1 avss avss nch_lvt w=4e-6 l=500e-9 nf=4 24 | m0 avss cmfb avss avss nch_lvt w=10e-6 l=120e-9 nf=10 25 | m66 avss on1 avss avss nch_lvt w=2e-6 l=120e-9 nf=2 26 | m64 avss op1 avss avss nch_lvt w=2e-6 l=120e-9 nf=2 27 | m55 avss avss avss avss nch_lvt w=2e-6 l=120e-9 nf=2 28 | m21 on op1 avss avss nch_lvt w=12e-6 l=120e-9 nf=12 29 | m19 op on1 avss avss nch_lvt w=12e-6 l=120e-9 nf=12 30 | m29 cmfb cmfb avss avss nch_lvt w=1e-6 l=120e-9 nf=1 31 | m14 op1 cmfb avss avss nch_lvt w=1e-6 l=120e-9 nf=1 32 | m13 on1 cmfb avss avss nch_lvt w=1e-6 l=120e-9 nf=1 33 | m59 avss net044 avss avss nch_lvt w=2e-6 l=120e-9 nf=2 34 | m30 net044 net044 avss avss nch_lvt w=1e-6 l=120e-9 nf=1 35 | m56 avss cmfb avss avss nch_lvt w=2e-6 l=120e-9 nf=2 36 | xc4 on vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 37 | xc5 op vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 38 | xr12 vcmo op avss rppolywo_m lr=20e-6 wr=1e-6 multi=1 m=1 39 | xr13 on vcmo avss rppolywo_m lr=20e-6 wr=1e-6 multi=1 m=1 40 | .ends OTA_FF_2s_v3e 41 | 42 | -------------------------------------------------------------------------------- /open/block/ota4.sp: -------------------------------------------------------------------------------- 1 | .topckt Telescopic_OTA_stacked_single_ended vpgate vbiasn D1 vdd vinn vinp vss vout vbiasp d1 2 | m9 vpgate vbiasn net8s vss nch_lvt w=270e-9 l=20e-9 nfin=70 3 | m9s net8s vbiasn net8 vss nch_lvt w=270e-9 l=20e-9 nfin=70 4 | m8 vout vbiasn net014s vss nch_lvt w=270e-9 l=20e-9 nfin=70 5 | m8s net014s vbiasn net014 vss nch_lvt w=270e-9 l=20e-9 nfin=70 6 | m5 D1 D1 netm5s vss nch_lvt w=270e-9 l=20e-9 nfin=20 7 | m5s netm5s D1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=20 8 | m4 net10 D1 netm4s vss nch_lvt w=270e-9 l=20e-9 nfin=100 9 | m4s netm4s D1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=100 10 | m3 net014 vinn netm3s vss nch_lvt w=270e-9 l=20e-9 nfin=140 11 | m3s netm3s vinn net10 vss nch_lvt w=270e-9 l=20e-9 nfin=140 12 | m0 net8 vinp netm0s vss nch_lvt w=270e-9 l=20e-9 nfin=140 13 | m0s netm0s vinp net10 vss nch_lvt w=270e-9 l=20e-9 nfin=140 14 | m7 vout vbiasp net012s vdd pch_lvt w=270e-9 l=20e-9 nfin=110 15 | m7s net012s vbiasp net012 vdd pch_lvt w=270e-9 l=20e-9 nfin=110 16 | m6 vpgate vbiasp net06s vdd pch_lvt w=270e-9 l=20e-9 nfin=110 17 | m6s net06s vbiasp net06 vdd pch_lvt w=270e-9 l=20e-9 nfin=110 18 | m2 net012 vpgate netm2s vdd pch_lvt w=270e-9 l=20e-9 nfin=45 19 | m2s netm2s vpgate vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=45 20 | m1 net06 vpgate netm1s vdd pch_lvt w=270e-9 l=20e-9 nfin=45 21 | m1s netm1s vpgate vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=45 22 | m10 vbiasn vbiasn net5s vss nch_lvt w=270e-9 l=20e-9 nfin=5 23 | m10s net5s vbiasn net5 vss nch_lvt w=270e-9 l=20e-9 nfin=5 24 | m11 net5 vbiasn netm11s vss nch_lvt w=270e-9 l=20e-9 nfin=10 25 | m11s netm11s vbiasn net10 vss nch_lvt w=270e-9 l=20e-9 nfin=10 26 | m15 net9 d1 netm15s vss nch_lvt w=270e-9 l=20e-9 nfin=10 27 | m15s netm15s d1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=10 28 | m16 net9 net9 netm16s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 29 | m16s netm16s net9 vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 30 | m17 vbiasn net9 netm17s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 31 | m17s netm17s net9 vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 32 | m12 vbiasp d1 netm12s vss nch_lvt w=270e-9 l=20e-9 nfin=10 33 | m12s netm12s d1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=10 34 | m13 vbiasp vbiasp netm13s vdd pch_lvt w=270e-9 l=20e-9 nfin=5 35 | m13s netm13s vbiasp net7 vdd pch_lvt w=270e-9 l=20e-9 nfin=5 36 | m14 net7 vbiasp netm14s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 37 | m14s netm14s vbiasp vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 38 | .ends Telescopic_OTA_stacked_single_ended 39 | -------------------------------------------------------------------------------- /pku/netlist/Telescopic_OTA_stacked_single_ended.sp: -------------------------------------------------------------------------------- 1 | .topckt Telescopic_OTA_stacked_single_ended vpgate vbiasn D1 vdd vinn vinp vss vout vbiasp d1 2 | m9 vpgate vbiasn net8s vss nch_lvt w=270e-9 l=20e-9 nfin=70 3 | m9s net8s vbiasn net8 vss nch_lvt w=270e-9 l=20e-9 nfin=70 4 | m8 vout vbiasn net014s vss nch_lvt w=270e-9 l=20e-9 nfin=70 5 | m8s net014s vbiasn net014 vss nch_lvt w=270e-9 l=20e-9 nfin=70 6 | m5 D1 D1 netm5s vss nch_lvt w=270e-9 l=20e-9 nfin=20 7 | m5s netm5s D1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=20 8 | m4 net10 D1 netm4s vss nch_lvt w=270e-9 l=20e-9 nfin=100 9 | m4s netm4s D1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=100 10 | m3 net014 vinn netm3s vss nch_lvt w=270e-9 l=20e-9 nfin=140 11 | m3s netm3s vinn net10 vss nch_lvt w=270e-9 l=20e-9 nfin=140 12 | m0 net8 vinp netm0s vss nch_lvt w=270e-9 l=20e-9 nfin=140 13 | m0s netm0s vinp net10 vss nch_lvt w=270e-9 l=20e-9 nfin=140 14 | m7 vout vbiasp net012s vdd pch_lvt w=270e-9 l=20e-9 nfin=110 15 | m7s net012s vbiasp net012 vdd pch_lvt w=270e-9 l=20e-9 nfin=110 16 | m6 vpgate vbiasp net06s vdd pch_lvt w=270e-9 l=20e-9 nfin=110 17 | m6s net06s vbiasp net06 vdd pch_lvt w=270e-9 l=20e-9 nfin=110 18 | m2 net012 vpgate netm2s vdd pch_lvt w=270e-9 l=20e-9 nfin=45 19 | m2s netm2s vpgate vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=45 20 | m1 net06 vpgate netm1s vdd pch_lvt w=270e-9 l=20e-9 nfin=45 21 | m1s netm1s vpgate vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=45 22 | m10 vbiasn vbiasn net5s vss nch_lvt w=270e-9 l=20e-9 nfin=5 23 | m10s net5s vbiasn net5 vss nch_lvt w=270e-9 l=20e-9 nfin=5 24 | m11 net5 vbiasn netm11s vss nch_lvt w=270e-9 l=20e-9 nfin=10 25 | m11s netm11s vbiasn net10 vss nch_lvt w=270e-9 l=20e-9 nfin=10 26 | m15 net9 d1 netm15s vss nch_lvt w=270e-9 l=20e-9 nfin=10 27 | m15s netm15s d1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=10 28 | m16 net9 net9 netm16s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 29 | m16s netm16s net9 vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 30 | m17 vbiasn net9 netm17s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 31 | m17s netm17s net9 vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 32 | m12 vbiasp d1 netm12s vss nch_lvt w=270e-9 l=20e-9 nfin=10 33 | m12s netm12s d1 vss vss nch_lvt w=270e-9 l=20e-9 nfin=10 34 | m13 vbiasp vbiasp netm13s vdd pch_lvt w=270e-9 l=20e-9 nfin=5 35 | m13s netm13s vbiasp net7 vdd pch_lvt w=270e-9 l=20e-9 nfin=5 36 | m14 net7 vbiasp netm14s vdd pch_lvt w=270e-9 l=20e-9 nfin=10 37 | m14s netm14s vbiasp vdd vdd pch_lvt w=270e-9 l=20e-9 nfin=10 38 | .ends Telescopic_OTA_stacked_single_ended 39 | -------------------------------------------------------------------------------- /open/block/comp1.sp: -------------------------------------------------------------------------------- 1 | .topckt CLK_COMP clk clkbo dn dp gt vb vdd vin vinb vintn<2> vintn<1> vintp<2> vintp<1> vss 2 | xm103 clkb clk vdd vdd pch_lvt w=480e-9 l=40e-9 3 | xm30 clk net030 vdd vdd pch_lvt w=3.84e-6 l=40e-9 4 | xm124 clkbo clk vdd vdd pch_lvt w=480e-9 l=40e-9 5 | xm16 v2p vxn vdd _net0 pch_lvt w=2.88e-6 l=40e-9 6 | xm114 d v2n vdd vdd pch_lvt w=1.92e-6 l=40e-9 7 | xm122 dp db vdd vdd pch_lvt w=960e-9 l=40e-9 8 | xm25 vmid v2p vdd vdd pch_lvt w=960e-9 l=40e-9 9 | xm14 net027 d vdd vdd pch_lvt w=480e-9 l=40e-9 10 | xm24 db v2p vdd vdd pch_lvt w=1.92e-6 l=40e-9 11 | xm85 net030 gt vdd vdd pch_lvt w=1.92e-6 l=40e-9 12 | xm6 net031 net027 vdd vdd pch_lvt w=960e-9 l=40e-9 13 | xm8 db d vdd vdd pch_lvt w=1.92e-6 l=40e-9 14 | xm5 d db vdd vdd pch_lvt w=1.92e-6 l=40e-9 15 | xm119 dn d vdd vdd pch_lvt w=960e-9 l=40e-9 16 | xm71 net027 db vdd vdd pch_lvt w=480e-9 l=40e-9 17 | xm9 net030 net031 vdd vdd pch_lvt w=1.92e-6 l=40e-9 18 | xm35 vxn clk vdd vdd pch_lvt w=2.88e-6 l=40e-9 19 | xm73 vxp clk vdd vdd pch_lvt w=2.88e-6 l=40e-9 20 | xm19 v2n vxp vdd _net0 pch_lvt w=2.88e-6 l=40e-9 21 | xm26 vmidb v2n vdd vdd pch_lvt w=960e-9 l=40e-9 22 | xm10 net030 net031 net032 vss nch_lvt w=1.92e-6 l=40e-9 23 | xm69 v1p vintn<1> vss vss nch_lvt w=720e-9 l=40e-9 24 | xm17 net032 gt vss vss nch_lvt w=1.92e-6 l=40e-9 25 | xm116 vxp clk v1p vss nch_lvt w=1.92e-6 l=40e-9 26 | xm102 clkb clk vss vss nch_lvt w=240e-9 l=40e-9 27 | xm120 dn d vss vss nch_lvt w=480e-9 l=40e-9 28 | xm1 db d vmid vss nch_lvt w=1.92e-6 l=40e-9 29 | xm113 vmidb v2n vss vss nch_lvt w=1.92e-6 l=40e-9 30 | xm7 net031 net027 vss vss nch_lvt w=480e-9 l=40e-9 31 | xm28 vss vss v1p vss nch_lvt w=240e-9 l=40e-9 32 | xm70 v1p vinb vss vss nch_lvt w=240e-9 l=40e-9 33 | xm97 net027 clkb net0107 vss nch_lvt w=480e-9 l=40e-9 34 | xm12 net0107 vb vss vss nch_lvt w=1.92e-6 l=40e-9 35 | xm121 dp db vss vss nch_lvt w=480e-9 l=40e-9 36 | xm115 vxn clk v1n vss nch_lvt w=1.92e-6 l=40e-9 37 | xm27 clk net030 vss vss nch_lvt w=1.92e-6 l=40e-9 38 | xm20 v2p vxn vss vss nch_lvt w=1.92e-6 l=40e-9 39 | xm3 d db vmidb vss nch_lvt w=1.92e-6 l=40e-9 40 | xm18 vss vss vss vss nch_lvt w=240e-9 l=40e-9 41 | xm55 v1n vin vss vss nch_lvt w=240e-9 l=40e-9 42 | xm23 vss vss v1n vss nch_lvt w=240e-9 l=40e-9 43 | xm57 v1n vintp<2> vss vss nch_lvt w=2.88e-6 l=40e-9 44 | xm125 clkbo clk vss vss nch_lvt w=240e-9 l=40e-9 45 | xm22 vmid v2p vss vss nch_lvt w=1.92e-6 l=40e-9 46 | xm21 v2n vxp vss vss nch_lvt w=1.92e-6 l=40e-9 47 | xm56 v1n vintp<1> vss vss nch_lvt w=720e-9 l=40e-9 48 | xm68 v1p vintn<2> vss vss nch_lvt w=2.88e-6 l=40e-9 49 | .ends CLK_COMP 50 | -------------------------------------------------------------------------------- /Comparator_1to7_0p7_lvt.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt Comparator_1to7_0p7_lvt caln calp clke d db inm<0> inm<1> inp<0> inp<1> vb vdd vss 5 | 6 | xm29 vout1p clk vdd vdd pch_lvt_mac l=40e-9 w=1.6e-6 multi=1 nf=2 7 | 8 | xm32 vout1m clk vdd vdd pch_lvt_mac l=40e-9 w=1.6e-6 multi=1 nf=2 9 | 10 | xm18 clk net043 vdd vdd pch_lvt_mac l=40e-9 w=3.2e-6 multi=1 nf=4 11 | 12 | xm19 net043 clke vdd vdd pch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 13 | 14 | xm7 db vout2p vdd vdd pch_lvt_mac l=40e-9 w=600e-9 multi=1 nf=1 15 | 16 | xm28 vout2p vout2m vdd vdd pch_lvt_mac l=120e-9 w=12.8e-6 multi=1 nf=8 17 | 18 | xm38 vdd vss vdd vdd pch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 19 | 20 | xm39 vdd vss vdd vdd pch_lvt_mac l=40e-9 w=3.2e-6 multi=1 nf=4 21 | 22 | xm34 vout2m vout2p vdd vdd pch_lvt_mac l=120e-9 w=12.8e-6 multi=1 nf=8 23 | 24 | xm25 vout2p clk vdd vdd pch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 25 | 26 | xm8 d vout2m vdd vdd pch_lvt_mac l=40e-9 w=600e-9 multi=1 nf=1 27 | 28 | xm33 vout2m clk vdd vdd pch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 29 | 30 | xm35 net058 clk net040 vss nch_lvt_mac l=40e-9 w=1e-6 multi=1 nf=1 31 | 32 | xm10 vout1m inp<0> net058 vss nch_lvt_mac l=200e-9 w=1.2e-6 multi=1 nf=1 33 | 34 | xm36 net040 vb vss vss nch_lvt_mac l=40e-9 w=1e-6 multi=1 nf=1 35 | 36 | xm9 d vout2m vss vss nch_lvt_mac l=40e-9 w=400e-9 multi=1 nf=1 37 | 38 | xm48 vss vdd vss vss nch_lvt_mac l=160e-9 w=2.4e-6 multi=1 nf=2 39 | 40 | xm41 vss vdd vss vss nch_lvt_mac l=40e-9 w=400e-9 multi=1 nf=2 41 | 42 | xm43 vss vdd vss vss nch_lvt_mac l=40e-9 w=6e-6 multi=1 nf=6 43 | 44 | xm42 vss vdd vss vss nch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 45 | 46 | xm11 vout1p inm<0> net058 vss nch_lvt_mac l=200e-9 w=1.2e-6 multi=1 nf=1 47 | 48 | xm26 clk net043 vss vss nch_lvt_mac l=40e-9 w=800e-9 multi=1 nf=2 49 | 50 | xm14 vout2p vout2m vout1p vss nch_lvt_mac l=120e-9 w=6.4e-6 multi=1 nf=8 51 | 52 | xm12 vout1p inm<1> net057 vss nch_lvt_mac l=200e-9 w=1.2e-6 multi=7 nf=1 53 | 54 | xm37 net041 vb vss vss nch_lvt_mac l=40e-9 w=1e-6 multi=7 nf=1 55 | 56 | xm40 net057 clk net041 vss nch_lvt_mac l=40e-9 w=1e-6 multi=7 nf=1 57 | 58 | xm6 db vout2p vss vss nch_lvt_mac l=40e-9 w=400e-9 multi=1 nf=1 59 | 60 | xm27 net043 clke vss vss nch_lvt_mac l=40e-9 w=400e-9 multi=1 nf=2 61 | 62 | xm13 vout1m inp<1> net057 vss nch_lvt_mac l=200e-9 w=1.2e-6 multi=7 nf=1 63 | 64 | xm21 vout2m vout2p vout1m vss nch_lvt_mac l=120e-9 w=6.4e-6 multi=1 nf=8 65 | 66 | m1 vout2m calp vout2m vout2m pch_lvt l=500e-9 w=16e-6 m=1 nf=2 67 | 68 | m2 vout2p vss vout2p vout2p pch_lvt l=500e-9 w=64e-6 m=1 nf=8 69 | 70 | m3 vout2p caln vout2p vout2p pch_lvt l=500e-9 w=16e-6 m=1 nf=2 71 | 72 | m0 vout2m vss vout2m vout2m pch_lvt l=500e-9 w=64e-6 m=1 nf=8 73 | .ends Comparator_1to7_0p7_lvt 74 | -------------------------------------------------------------------------------- /OTA_FF_2s_v3e.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .topckt OTA_FF_2s_v3e avdd avss ibin in ip on op vcas vcmi 5 | 6 | m35 net057 ibin avdd avdd pch_lvt l=120e-9 w=10e-6 m=1 nf=2 7 | 8 | m34 cmfb vcmo net057 net057 pch_lvt l=120e-9 w=5e-6 m=1 nf=1 9 | 10 | m33 net044 vcmi net057 net057 pch_lvt l=120e-9 w=5e-6 m=1 nf=1 11 | 12 | m62 avdd ibin avdd avdd pch_lvt l=120e-9 w=52.5e-6 m=1 nf=21 13 | 14 | m54 net59 net59 net59 net59 pch_lvt l=120e-9 w=30e-6 m=1 nf=12 15 | 16 | m43 net5 net5 net5 net5 pch_lvt l=120e-9 w=15e-6 m=1 nf=6 17 | 18 | m53 avdd ibin avdd avdd pch_lvt l=120e-9 w=15e-6 m=1 nf=6 19 | 20 | m57 avdd ibin avdd avdd pch_lvt l=120e-9 w=10e-6 m=1 nf=4 21 | 22 | m37 op in net59 net59 pch_lvt l=120e-9 w=60e-6 m=1 nf=12 23 | 24 | m23 on ip net59 net59 pch_lvt l=120e-9 w=60e-6 m=1 nf=12 25 | 26 | m63 net75 vcas net75 net75 pch_lvt l=120e-9 w=20e-6 m=1 nf=8 27 | 28 | m58 net057 vcmo net057 net057 pch_lvt l=120e-9 w=5e-6 m=1 nf=2 29 | 30 | m36 net59 ibin avdd avdd pch_lvt l=120e-9 w=120e-6 m=1 nf=24 31 | 32 | m41 avdd ibin avdd avdd pch_lvt l=120e-9 w=7.5e-6 m=1 nf=3 33 | 34 | m16 ibin vcas net75 net75 pch_lvt l=120e-9 w=10e-6 m=1 nf=2 35 | 36 | m50 on1 ip net5 net5 pch_lvt l=120e-9 w=5e-6 m=1 nf=1 37 | 38 | m48 net057 vcmi net057 net057 pch_lvt l=120e-9 w=15e-6 m=1 nf=6 39 | 40 | m6 net75 ibin avdd avdd pch_lvt l=120e-9 w=10e-6 m=1 nf=2 41 | 42 | m4 net5 ibin avdd avdd pch_lvt l=120e-9 w=10e-6 m=1 nf=2 43 | 44 | m20 op1 in net5 net5 pch_lvt l=120e-9 w=5e-6 m=1 nf=1 45 | 46 | m7 avss op1 avss avss nch_lvt l=500e-9 w=4e-6 m=1 nf=4 47 | 48 | m2 avss on1 avss avss nch_lvt l=500e-9 w=4e-6 m=1 nf=4 49 | 50 | m0 avss cmfb avss avss nch_lvt l=120e-9 w=10e-6 m=1 nf=10 51 | 52 | m66 avss on1 avss avss nch_lvt l=120e-9 w=2e-6 m=1 nf=2 53 | 54 | m64 avss op1 avss avss nch_lvt l=120e-9 w=2e-6 m=1 nf=2 55 | 56 | m55 avss avss avss avss nch_lvt l=120e-9 w=2e-6 m=1 nf=2 57 | 58 | m21 on op1 avss avss nch_lvt l=120e-9 w=12e-6 m=1 nf=12 59 | 60 | m19 op on1 avss avss nch_lvt l=120e-9 w=12e-6 m=1 nf=12 61 | 62 | m29 cmfb cmfb avss avss nch_lvt l=120e-9 w=1e-6 m=1 nf=1 63 | 64 | m14 op1 cmfb avss avss nch_lvt l=120e-9 w=1e-6 m=1 nf=1 65 | 66 | m13 on1 cmfb avss avss nch_lvt l=120e-9 w=1e-6 m=1 nf=1 67 | 68 | m59 avss net044 avss avss nch_lvt l=120e-9 w=2e-6 m=1 nf=2 69 | 70 | m30 net044 net044 avss avss nch_lvt l=120e-9 w=1e-6 m=1 nf=1 71 | 72 | m56 avss cmfb avss avss nch_lvt l=120e-9 w=2e-6 m=1 nf=2 73 | 74 | xc4 on vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 multi=1 ftip=140e-9 dmflag=0 75 | 76 | xc5 op vcmo avss cfmom nr=24 lr=3.8e-6 w=100e-9 s=100e-9 stm=2 spm=6 multi=1 ftip=140e-9 dmflag=0 77 | xr12 op avss rppolywo_m lr=20e-6 wr=1e-6 multi=1 m=1 78 | 79 | xr13 vcmo avss rppolywo_m lr=20e-6 wr=1e-6 multi=1 m=1 80 | 81 | .ends OTA_FF_2s_v3e 82 | -------------------------------------------------------------------------------- /pku/netlist/CLK_COMP.sp: -------------------------------------------------------------------------------- 1 | .topckt CLK_COMP clk clkbo dn dp gt vb vdd vin vinb vintn<2> vintn<1> vintp<2> vintp<1> vss 2 | xm103 clkb clk vdd vdd pch_lvt w=480e-9 l=40e-9 nf=1 3 | xm30 clk net030 vdd vdd pch_lvt w=3.84e-6 l=40e-9 nf=8 4 | xm124 clkbo clk vdd vdd pch_lvt w=480e-9 l=40e-9 nf=1 5 | xm16 v2p vxn vdd _net0 pch_lvt w=2.88e-6 l=40e-9 nf=6 6 | xm114 d v2n vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 7 | xm122 dp db vdd vdd pch_lvt w=960e-9 l=40e-9 nf=2 8 | xm25 vmid v2p vdd vdd pch_lvt w=960e-9 l=40e-9 nf=2 9 | xm14 net027 d vdd vdd pch_lvt w=480e-9 l=40e-9 nf=1 10 | xm24 db v2p vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 11 | xm85 net030 gt vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=2 12 | xm6 net031 net027 vdd vdd pch_lvt w=960e-9 l=40e-9 nf=1 13 | xm8 db d vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 14 | xm5 d db vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=4 15 | xm119 dn d vdd vdd pch_lvt w=960e-9 l=40e-9 nf=2 16 | xm71 net027 db vdd vdd pch_lvt w=480e-9 l=40e-9 nf=1 17 | xm9 net030 net031 vdd vdd pch_lvt w=1.92e-6 l=40e-9 nf=2 18 | xm35 vxn clk vdd vdd pch_lvt w=2.88e-6 l=40e-9 nf=6 19 | xm73 vxp clk vdd vdd pch_lvt w=2.88e-6 l=40e-9 nf=6 20 | xm19 v2n vxp vdd _net0 pch_lvt w=2.88e-6 l=40e-9 nf=6 21 | xm26 vmidb v2n vdd vdd pch_lvt w=960e-9 l=40e-9 nf=2 22 | xm10 net030 net031 net032 vss nch_lvt w=1.92e-6 l=40e-9 nf=4 23 | xm69 v1p vintn<1> vss vss nch_lvt w=720e-9 l=40e-9 nf=3 24 | xm17 net032 gt vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 25 | xm116 vxp clk v1p vss nch_lvt w=1.92e-6 l=40e-9 nf=4 26 | xm102 clkb clk vss vss nch_lvt w=240e-9 l=40e-9 nf=1 27 | xm120 dn d vss vss nch_lvt w=480e-9 l=40e-9 nf=1 28 | xm1 db d vmid vss nch_lvt w=1.92e-6 l=40e-9 nf=4 29 | xm113 vmidb v2n vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 30 | xm7 net031 net027 vss vss nch_lvt w=480e-9 l=40e-9 nf=1 31 | xm28 vss vss v1p vss nch_lvt w=240e-9 l=40e-9 nf=1 32 | xm70 v1p vinb vss vss nch_lvt w=240e-9 l=40e-9 nf=1 33 | xm97 net027 clkb net0107 vss nch_lvt w=480e-9 l=40e-9 nf=1 34 | xm12 net0107 vb vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 35 | xm121 dp db vss vss nch_lvt w=480e-9 l=40e-9 nf=1 36 | xm115 vxn clk v1n vss nch_lvt w=1.92e-6 l=40e-9 nf=4 37 | xm27 clk net030 vss vss nch_lvt w=1.92e-6 l=40e-9 nf=2 38 | xm20 v2p vxn vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 39 | xm3 d db vmidb vss nch_lvt w=1.92e-6 l=40e-9 nf=4 40 | xm18 vss vss vss vss nch_lvt w=240e-9 l=40e-9 nf=1 41 | xm55 v1n vin vss vss nch_lvt w=240e-9 l=40e-9 nf=1 42 | xm23 vss vss v1n vss nch_lvt w=240e-9 l=40e-9 nf=1 43 | xm57 v1n vintp<2> vss vss nch_lvt w=2.88e-6 l=40e-9 nf=12 44 | xm125 clkbo clk vss vss nch_lvt w=240e-9 l=40e-9 nf=1 45 | xm22 vmid v2p vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 46 | xm21 v2n vxp vss vss nch_lvt w=1.92e-6 l=40e-9 nf=4 47 | xm56 v1n vintp<1> vss vss nch_lvt w=720e-9 l=40e-9 nf=3 48 | xm68 v1p vintn<2> vss vss nch_lvt w=2.88e-6 l=40e-9 nf=12 49 | .ends CLK_COMP 50 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # AncstrGNN Benchmark 2 | 3 | ## About 4 | 5 | This is the sanitized benchmark suites for analog IC symmetry constraint extraction method [AncstrGNN](https://github.com/baloneymath/AncstrGNN). 6 | 7 | AncstrGNN is proposed by Dr. Hao Chen (now with Google Deepmind) and Prof. David Z. Pan at The University of Texas at Austin. The work was published at DAC'21. 8 | 9 | >[Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks](https://ieeexplore.ieee.org/document/9586211) 10 | > * Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, and David Z. Pan 11 | > * ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, December 5-9, 2021. 12 | 13 | The benchmark suite include several sources of circuits from other publications. 14 | 15 | The ``sfa`` refers to "signal flow analysis", which is detailed in the paper. 16 | 17 | > [MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence](https://ieeexplore.ieee.org/document/8942060) 18 | > * Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, and David Z. Pan 19 | > * IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, USA, November 4-7, 2019. 20 | 21 | The ``open`` refers to several circuits from MAGICAL 1.0 release. 22 | 23 | > [MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC](https://ieeexplore.ieee.org/document/9431521) 24 | > * Hao Chen\*, Mingjie Liu\*, Xiyuan Tang\*, Keren Zhu\*, Abhishek Mukherjee, Nan Sun and David Z. Pan 25 | > * 2021 IEEE Custom Integrated Circuits Conference (CICC), Virtual Event, April 25-30,S 2021. 26 | > * \*indicates equal contributions 27 | 28 | The ``s3det`` refers to the system-level symmetry constraint extraction method S^3DET. 29 | 30 | >[S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity](https://ieeexplore.ieee.org/document/9045109) 31 | > * Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun and David Z. Pan 32 | > * IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Beijing, China, January 13-16, 2020. 33 | 34 | The ``pku`` refers to the circuits annotated by Peking University team lead by Prof. Yibo Lin and his PhD student Xiaohan Gao. 35 | 36 | >[Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks](https://doi.org/10.1145/3394885.3431545) 37 | > * Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan and Yibo Lin 38 | > * IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan 18-21, 2021. 39 | 40 | ## Use 41 | 42 | Please refer to [AncstrGNN](https://github.com/baloneymath/AncstrGNN) for the usage. 43 | 44 | ## Acknowledgement 45 | 46 | This benchmark suite is a combined efforts with multiple people, from both the UT (Prof. David Z. Pan group) and Peking University (Prof. Yibo Lin group). 47 | 48 | Some of those important contributors to the annotation efforts include (not limited to): 49 | * Hao Chen (UT, now with Google Deepmind) 50 | * Mingjie Liu (UT, now with Nvidia Research) 51 | * Xiaohan Gao (PKU) 52 | * Xiyuan Tang (UT, now with Peking University) 53 | * Shaolan Li (UT, now with GaTech) 54 | 55 | Many circuits are originally designed by Prof. Nan Sun's group (UT, now with Tsinghua University). 56 | 57 | 58 | 59 | -------------------------------------------------------------------------------- /s3det/adc2.pair: -------------------------------------------------------------------------------- 1 | adc2/ota2 adc2/ota1 2 | adc2/ota2 adc2/cap2_res2 3 | adc2/ota2 adc2/cap1 4 | adc2/ota2 adc2/cap3 5 | adc2/ota2 adc2/dac1b 6 | adc2/ota2 adc2/digital0 7 | adc2/ota2 adc2/input_resm 8 | adc2/ota2 adc2/dac1a 9 | adc2/ota2 adc2/w1 10 | adc2/ota2 adc2/dac3a 11 | adc2/ota2 adc2/dac3b 12 | adc2/ota2 adc2/input_resp 13 | adc2/ota1 adc2/cap2_res2 14 | adc2/ota1 adc2/cap1 15 | adc2/ota1 adc2/cap3 16 | adc2/ota1 adc2/dac1b 17 | adc2/ota1 adc2/digital0 18 | adc2/ota1 adc2/input_resm 19 | adc2/ota1 adc2/dac1a 20 | adc2/ota1 adc2/w1 21 | adc2/ota1 adc2/dac3a 22 | adc2/ota1 adc2/dac3b 23 | adc2/ota1 adc2/input_resp 24 | adc2/cap2_res2 adc2/cap1 25 | adc2/cap2_res2 adc2/cap3 26 | adc2/cap2_res2 adc2/dac1b 27 | adc2/cap2_res2 adc2/digital0 28 | adc2/cap2_res2 adc2/input_resm 29 | adc2/cap2_res2 adc2/dac1a 30 | adc2/cap2_res2 adc2/w1 31 | adc2/cap2_res2 adc2/dac3a 32 | adc2/cap2_res2 adc2/dac3b 33 | adc2/cap2_res2 adc2/input_resp 34 | adc2/cap1 adc2/cap3 35 | adc2/cap1 adc2/dac1b 36 | adc2/cap1 adc2/digital0 37 | adc2/cap1 adc2/input_resm 38 | adc2/cap1 adc2/dac1a 39 | adc2/cap1 adc2/w1 40 | adc2/cap1 adc2/dac3a 41 | adc2/cap1 adc2/dac3b 42 | adc2/cap1 adc2/input_resp 43 | adc2/cap3 adc2/dac1b 44 | adc2/cap3 adc2/digital0 45 | adc2/cap3 adc2/input_resm 46 | adc2/cap3 adc2/dac1a 47 | adc2/cap3 adc2/w1 48 | adc2/cap3 adc2/dac3a 49 | adc2/cap3 adc2/dac3b 50 | adc2/cap3 adc2/input_resp 51 | adc2/dac1b adc2/digital0 52 | adc2/dac1b adc2/input_resm 53 | adc2/dac1b adc2/dac1a 54 | adc2/dac1b adc2/w1 55 | adc2/dac1b adc2/dac3a 56 | adc2/dac1b adc2/dac3b 57 | adc2/dac1b adc2/input_resp 58 | adc2/digital0 adc2/input_resm 59 | adc2/digital0 adc2/dac1a 60 | adc2/digital0 adc2/w1 61 | adc2/digital0 adc2/dac3a 62 | adc2/digital0 adc2/dac3b 63 | adc2/digital0 adc2/input_resp 64 | adc2/input_resm adc2/dac1a 65 | adc2/input_resm adc2/w1 66 | adc2/input_resm adc2/dac3a 67 | adc2/input_resm adc2/dac3b 68 | adc2/input_resm adc2/input_resp 69 | adc2/dac1a adc2/w1 70 | adc2/dac1a adc2/dac3a 71 | adc2/dac1a adc2/dac3b 72 | adc2/dac1a adc2/input_resp 73 | adc2/w1 adc2/dac3a 74 | adc2/w1 adc2/dac3b 75 | adc2/w1 adc2/input_resp 76 | adc2/dac3a adc2/dac3b 77 | adc2/dac3a adc2/input_resp 78 | adc2/dac3b adc2/input_resp 79 | adc2/cap2_res2/xc0 adc2/cap2_res2/xr51 80 | adc2/cap2_res2/xc0 adc2/cap2_res2/xr25 81 | adc2/cap2_res2/xr51 adc2/cap2_res2/xr25 82 | adc2/cap1/xc1_3_ adc2/cap1/xc1_2_ 83 | adc2/cap1/xc1_3_ adc2/cap1/xc1_1_ 84 | adc2/cap1/xc1_3_ adc2/cap1/xc1_0_ 85 | adc2/cap1/xc1_2_ adc2/cap1/xc1_1_ 86 | adc2/cap1/xc1_2_ adc2/cap1/xc1_0_ 87 | adc2/cap1/xc1_1_ adc2/cap1/xc1_0_ 88 | adc2/dac1b/xr19 adc2/dac1b/xr48 89 | adc2/dac1b/xr19 adc2/dac1b/xi86 90 | adc2/dac1b/xr19 adc2/dac1b/xi88 91 | adc2/dac1b/xr48 adc2/dac1b/xi86 92 | adc2/dac1b/xr48 adc2/dac1b/xi88 93 | adc2/dac1b/xi86 adc2/dac1b/xi88 94 | adc2/digital0/xi128/xi0 adc2/digital0/xi128/xi1 95 | adc2/dac1a/xr19 adc2/dac1a/xr48 96 | adc2/dac1a/xr19 adc2/dac1a/xi86 97 | adc2/dac1a/xr19 adc2/dac1a/xi88 98 | adc2/dac1a/xr48 adc2/dac1a/xi86 99 | adc2/dac1a/xr48 adc2/dac1a/xi88 100 | adc2/dac1a/xi86 adc2/dac1a/xi88 101 | adc2/dac3a/xr64 adc2/dac3a/xi97 102 | adc2/dac3a/xr64 adc2/dac3a/xi94 103 | adc2/dac3a/xr64 adc2/dac3a/xr27 104 | adc2/dac3a/xi97 adc2/dac3a/xi94 105 | adc2/dac3a/xi97 adc2/dac3a/xr27 106 | adc2/dac3a/xi94 adc2/dac3a/xr27 107 | adc2/dac3b/xr64 adc2/dac3b/xi97 108 | adc2/dac3b/xr64 adc2/dac3b/xi94 109 | adc2/dac3b/xr64 adc2/dac3b/xr27 110 | adc2/dac3b/xi97 adc2/dac3b/xi94 111 | adc2/dac3b/xi97 adc2/dac3b/xr27 112 | adc2/dac3b/xi94 adc2/dac3b/xr27 113 | -------------------------------------------------------------------------------- /s3det/adc2_labeled.pair: -------------------------------------------------------------------------------- 1 | adc2/ota2 adc2/ota1 2 | adc2/ota2 adc2/cap2_res2 3 | adc2/ota2 adc2/cap1 4 | adc2/ota2 adc2/cap3 5 | adc2/ota2 adc2/dac1b 6 | adc2/ota2 adc2/digital0 7 | adc2/ota2 adc2/input_resm 8 | adc2/ota2 adc2/dac1a 9 | adc2/ota2 adc2/w1 10 | adc2/ota2 adc2/dac3a 11 | adc2/ota2 adc2/dac3b 12 | adc2/ota2 adc2/input_resp 13 | adc2/ota1 adc2/cap2_res2 14 | adc2/ota1 adc2/cap1 15 | adc2/ota1 adc2/cap3 16 | adc2/ota1 adc2/dac1b 17 | adc2/ota1 adc2/digital0 18 | adc2/ota1 adc2/input_resm 19 | adc2/ota1 adc2/dac1a 20 | adc2/ota1 adc2/w1 21 | adc2/ota1 adc2/dac3a 22 | adc2/ota1 adc2/dac3b 23 | adc2/ota1 adc2/input_resp 24 | adc2/cap2_res2 adc2/cap1 25 | adc2/cap2_res2 adc2/cap3 26 | adc2/cap2_res2 adc2/dac1b 27 | adc2/cap2_res2 adc2/digital0 28 | adc2/cap2_res2 adc2/input_resm 29 | adc2/cap2_res2 adc2/dac1a 30 | adc2/cap2_res2 adc2/w1 31 | adc2/cap2_res2 adc2/dac3a 32 | adc2/cap2_res2 adc2/dac3b 33 | adc2/cap2_res2 adc2/input_resp 34 | adc2/cap1 adc2/cap3 35 | adc2/cap1 adc2/dac1b 36 | adc2/cap1 adc2/digital0 37 | adc2/cap1 adc2/input_resm 38 | adc2/cap1 adc2/dac1a 39 | adc2/cap1 adc2/w1 40 | adc2/cap1 adc2/dac3a 41 | adc2/cap1 adc2/dac3b 42 | adc2/cap1 adc2/input_resp 43 | adc2/cap3 adc2/dac1b 44 | adc2/cap3 adc2/digital0 45 | adc2/cap3 adc2/input_resm 46 | adc2/cap3 adc2/dac1a 47 | adc2/cap3 adc2/w1 48 | adc2/cap3 adc2/dac3a 49 | adc2/cap3 adc2/dac3b 50 | adc2/cap3 adc2/input_resp 51 | adc2/dac1b adc2/digital0 52 | adc2/dac1b adc2/input_resm 53 | adc2/dac1b adc2/dac1a 54 | adc2/dac1b adc2/w1 55 | adc2/dac1b adc2/dac3a 56 | adc2/dac1b adc2/dac3b 57 | adc2/dac1b adc2/input_resp 58 | adc2/digital0 adc2/input_resm 59 | adc2/digital0 adc2/dac1a 60 | adc2/digital0 adc2/w1 61 | adc2/digital0 adc2/dac3a 62 | adc2/digital0 adc2/dac3b 63 | adc2/digital0 adc2/input_resp 64 | adc2/input_resm adc2/dac1a 65 | adc2/input_resm adc2/w1 66 | adc2/input_resm adc2/dac3a 67 | adc2/input_resm adc2/dac3b 68 | adc2/input_resm adc2/input_resp 69 | adc2/dac1a adc2/w1 70 | adc2/dac1a adc2/dac3a 71 | adc2/dac1a adc2/dac3b 72 | adc2/dac1a adc2/input_resp 73 | adc2/w1 adc2/dac3a 74 | adc2/w1 adc2/dac3b 75 | adc2/w1 adc2/input_resp 76 | adc2/dac3a adc2/dac3b 77 | adc2/dac3a adc2/input_resp 78 | adc2/dac3b adc2/input_resp 79 | adc2/cap2_res2/xc0 adc2/cap2_res2/xr51 80 | adc2/cap2_res2/xc0 adc2/cap2_res2/xr25 81 | adc2/cap2_res2/xr51 adc2/cap2_res2/xr25 82 | adc2/cap1/xc1_3_ adc2/cap1/xc1_2_ 83 | adc2/cap1/xc1_3_ adc2/cap1/xc1_1_ 84 | adc2/cap1/xc1_3_ adc2/cap1/xc1_0_ 85 | adc2/cap1/xc1_2_ adc2/cap1/xc1_1_ 86 | adc2/cap1/xc1_2_ adc2/cap1/xc1_0_ 87 | adc2/cap1/xc1_1_ adc2/cap1/xc1_0_ 88 | adc2/dac1b/xr19 adc2/dac1b/xr48 89 | adc2/dac1b/xr19 adc2/dac1b/xi86 90 | adc2/dac1b/xr19 adc2/dac1b/xi88 91 | adc2/dac1b/xr48 adc2/dac1b/xi86 92 | adc2/dac1b/xr48 adc2/dac1b/xi88 93 | adc2/dac1b/xi86 adc2/dac1b/xi88 94 | adc2/digital0/xi128/xi0 adc2/digital0/xi128/xi1 95 | adc2/dac1a/xr19 adc2/dac1a/xr48 96 | adc2/dac1a/xr19 adc2/dac1a/xi86 97 | adc2/dac1a/xr19 adc2/dac1a/xi88 98 | adc2/dac1a/xr48 adc2/dac1a/xi86 99 | adc2/dac1a/xr48 adc2/dac1a/xi88 100 | adc2/dac1a/xi86 adc2/dac1a/xi88 101 | adc2/dac3a/xr64 adc2/dac3a/xi97 102 | adc2/dac3a/xr64 adc2/dac3a/xi94 103 | adc2/dac3a/xr64 adc2/dac3a/xr27 104 | adc2/dac3a/xi97 adc2/dac3a/xi94 105 | adc2/dac3a/xi97 adc2/dac3a/xr27 106 | adc2/dac3a/xi94 adc2/dac3a/xr27 107 | adc2/dac3b/xr64 adc2/dac3b/xi97 108 | adc2/dac3b/xr64 adc2/dac3b/xi94 109 | adc2/dac3b/xr64 adc2/dac3b/xr27 110 | adc2/dac3b/xi97 adc2/dac3b/xi94 111 | adc2/dac3b/xi97 adc2/dac3b/xr27 112 | adc2/dac3b/xi94 adc2/dac3b/xr27 113 | -------------------------------------------------------------------------------- /s3det/CTDTDSM_V3.s3det: -------------------------------------------------------------------------------- 1 | CTDTDSM_V3/xi58/xi177/xi18 2 | xi187 xi186 3 | xi186 xi184 4 | 5 | CTDTDSM_V3/xi58/xi172 6 | xi161 xi169 7 | xi2<1> xi2<2> 8 | xi150 xi151 9 | xi150 xi152 10 | xi150 xi153 11 | xi151 xi152 12 | xi151 xi153 13 | xi165 xi164 14 | xi165 xi163 15 | xi165 xi162 16 | xi164 xi163 17 | xi164 xi162 18 | xi163 xi162 19 | xi152 xi153 20 | 21 | CTDTDSM_V3/xi58/xi170 22 | xi161 xi169 23 | xi2<1> xi2<2> 24 | xi150 xi151 25 | xi150 xi152 26 | xi150 xi153 27 | xi151 xi152 28 | xi151 xi153 29 | xi165 xi164 30 | xi165 xi163 31 | xi165 xi162 32 | xi164 xi163 33 | xi164 xi162 34 | xi163 xi162 35 | xi152 xi153 36 | 37 | CTDTDSM_V3/xi58/xi177 38 | xi34 xi35 39 | xi34 xi36 40 | xi34 xi18 41 | xi35 xi36 42 | xi35 xi18 43 | xi36 xi18 44 | xi1<0> xi1<1> 45 | xi1<0> xi1<2> 46 | xi1<0> xi1<3> 47 | xi1<2> xi1<1> 48 | xi1<1> xi1<3> 49 | xi1<2> xi1<3> 50 | 51 | CTDTDSM_V3 52 | xi7<4> xi7<2> 53 | xi7<14> xi7<4> 54 | xi7<10> xi7<4> 55 | xi7<9> xi7<4> 56 | xi7<12> xi7<4> 57 | xi7<4> xi7<7> 58 | xi7<3> xi7<4> 59 | xi7<4> xi7<5> 60 | xi7<1> xi7<4> 61 | xi7<6> xi7<4> 62 | xi7<15> xi7<4> 63 | xi7<8> xi7<4> 64 | xi7<13> xi7<4> 65 | xi7<4> xi7<11> 66 | xi7<14> xi7<2> 67 | xi7<10> xi7<2> 68 | xi7<9> xi7<2> 69 | xi7<12> xi7<2> 70 | xi7<7> xi7<2> 71 | xi7<3> xi7<2> 72 | xi7<2> xi7<5> 73 | xi7<1> xi7<2> 74 | xi7<6> xi7<2> 75 | xi7<15> xi7<2> 76 | xi7<8> xi7<2> 77 | xi7<13> xi7<2> 78 | xi7<2> xi7<11> 79 | xi7<10> xi7<14> 80 | xi7<9> xi7<14> 81 | xi7<12> xi7<14> 82 | xi7<14> xi7<7> 83 | xi7<3> xi7<14> 84 | xi7<14> xi7<5> 85 | xi7<1> xi7<14> 86 | xi7<6> xi7<14> 87 | xi7<15> xi7<14> 88 | xi7<8> xi7<14> 89 | xi7<13> xi7<14> 90 | xi7<14> xi7<11> 91 | xi7<10> xi7<9> 92 | xi7<10> xi7<12> 93 | xi7<10> xi7<7> 94 | xi7<10> xi7<3> 95 | xi7<10> xi7<5> 96 | xi7<10> xi7<1> 97 | xi7<10> xi7<6> 98 | xi7<10> xi7<15> 99 | xi7<10> xi7<8> 100 | xi7<10> xi7<13> 101 | xi7<10> xi7<11> 102 | xi7<12> xi7<9> 103 | xi7<9> xi7<7> 104 | xi7<3> xi7<9> 105 | xi7<9> xi7<5> 106 | xi7<1> xi7<9> 107 | xi7<6> xi7<9> 108 | xi7<15> xi7<9> 109 | xi7<8> xi7<9> 110 | xi7<13> xi7<9> 111 | xi7<9> xi7<11> 112 | xi7<12> xi7<7> 113 | xi7<3> xi7<12> 114 | xi7<12> xi7<5> 115 | xi7<12> xi7<1> 116 | xi7<12> xi7<6> 117 | xi7<12> xi7<15> 118 | xi7<8> xi7<12> 119 | xi7<13> xi7<12> 120 | xi7<12> xi7<11> 121 | xi7<3> xi7<7> 122 | xi7<7> xi7<5> 123 | xi7<1> xi7<7> 124 | xi7<6> xi7<7> 125 | xi7<15> xi7<7> 126 | xi7<8> xi7<7> 127 | xi7<13> xi7<7> 128 | xi7<7> xi7<11> 129 | xi7<3> xi7<5> 130 | xi7<3> xi7<1> 131 | xi7<3> xi7<6> 132 | xi7<3> xi7<15> 133 | xi7<8> xi7<3> 134 | xi7<3> xi7<13> 135 | xi7<3> xi7<11> 136 | xi7<1> xi7<5> 137 | xi7<6> xi7<5> 138 | xi7<15> xi7<5> 139 | xi7<8> xi7<5> 140 | xi7<13> xi7<5> 141 | xi7<11> xi7<5> 142 | xi7<6> xi7<1> 143 | xi7<15> xi7<1> 144 | xi7<8> xi7<1> 145 | xi7<13> xi7<1> 146 | xi7<1> xi7<11> 147 | xi7<6> xi7<15> 148 | xi7<8> xi7<6> 149 | xi7<13> xi7<6> 150 | xi7<6> xi7<11> 151 | xi7<8> xi7<15> 152 | xi7<13> xi7<15> 153 | xi7<15> xi7<11> 154 | xi7<8> xi7<13> 155 | xi7<8> xi7<11> 156 | xi7<13> xi7<11> 157 | xr7 xr6 158 | 159 | CTDTDSM_V3/xi58/xi174/xi345/xi3<1> 160 | xi26 xi11 161 | xi24 xi16 162 | xi18 xi23 163 | 164 | CTDTDSM_V3/xi58/xi174/xi345/xi3<3> 165 | xi26 xi11 166 | xi24 xi16 167 | xi18 xi23 168 | 169 | CTDTDSM_V3/xi58/xi173 170 | xi12 xi17 171 | xi12 xi15 172 | xi12 xi19 173 | xi16 xi134 174 | xi19 xi17 175 | xi18 xi14 176 | 177 | CTDTDSM_V3/xi58/xi174/xi345/xi3<2> 178 | xi26 xi11 179 | xi25 xi24 180 | xi18 xi23 181 | 182 | CTDTDSM_V3/xi58/xi174/xi345/xi3<4> 183 | xi26 xi11 184 | xi24 xi16 185 | 186 | CTDTDSM_V3/xi58/xi177/xi36 187 | xi186 xi184 188 | 189 | CTDTDSM_V3/xi58/xi174/xi358/xi334 190 | xi12 xi15 191 | xi17 xi14 192 | 193 | CTDTDSM_V3/xi58/xi177/xi34 194 | xi186 xi184 195 | 196 | CTDTDSM_V3/xi58 197 | xi176 xi173 198 | xi197<2> xi197<1> 199 | xi172 xi170 200 | 201 | CTDTDSM_V3/xi39 202 | xc8 xc9 203 | xc8 xc1 204 | xc8 xc5 205 | xc8 xc6 206 | xc8 xc7 207 | xc9 xc1 208 | xc9 xc5 209 | xc9 xc6 210 | xc9 xc7 211 | xc0 xc10 212 | xc1 xc5 213 | xc1 xc6 214 | xc1 xc7 215 | xc6 xc5 216 | xc7 xc5 217 | xc6 xc7 218 | 219 | CTDTDSM_V3/xi58/xi206 220 | xi187 xi185 221 | 222 | CTDTDSM_V3/xi58/xi174/xi345 223 | xi3<4> xi3<1> 224 | xi3<2> xi3<1> 225 | xi3<3> xi3<1> 226 | xi4<0> xi4<1> 227 | xi4<3> xi4<2> 228 | xi4<3> xi4<1> 229 | xi4<2> xi4<1> 230 | xi3<2> xi3<3> 231 | 232 | CTDTDSM_V3/xi58/xi177/xi35 233 | xi186 xi184 234 | 235 | CTDTDSM_V3/xi58/xi174/xi354 236 | xi282 xi283 237 | 238 | CTDTDSM_V3/xi58/xi174/xi355 239 | xi2 xi252 240 | xi3 xi252 241 | xi252 xi319 242 | xi2 xi3 243 | xi2 xi319 244 | xi3 xi319 245 | 246 | CTDTDSM_V3/xi58/xi176 247 | xi12 xi17 248 | xi12 xi15 249 | xi12 xi19 250 | xi16 xi134 251 | xi17 xi15 252 | xi19 xi17 253 | xi18 xi14 254 | xi19 xi15 255 | 256 | -------------------------------------------------------------------------------- /pku/sym2/CTDSM_CORE_NEW.sym: -------------------------------------------------------------------------------- 1 | CTDSM_CORE_NEW 2 | m0 m1 3 | xr16 xr47 4 | xr25 xr51 5 | xi152/xr19 xi153/xr19 6 | xi152/xr48 xi153/xr48 7 | xi152/xi86/m0 xi153/xi86/m0 8 | xi152/xi86/mi4 xi153/xi86/mi4 9 | xi152/xi86/m1 xi153/xi86/m1 10 | xi152/xi86/m2 xi153/xi86/m2 11 | xi152/xi86/mi29 xi153/xi86/mi29 12 | xi152/xi86/mi15 xi153/xi86/mi15 13 | xi152/xi86/m3 xi153/xi86/m3 14 | xi152/xi86/m4 xi153/xi86/m4 15 | xi152/xi86/m5 xi153/xi86/m5 16 | xi152/xi86/mi5 xi153/xi86/mi5 17 | xi152/xi86/mi49 xi153/xi86/mi49 18 | xi152/xi86/m6 xi153/xi86/m6 19 | xi152/xi86/mi26 xi153/xi86/mi26 20 | xi152/xi86/mi48 xi153/xi86/mi48 21 | xi152/xi86/m7 xi153/xi86/m7 22 | xi152/xi86/m8 xi153/xi86/m8 23 | xi152/xi86/mi47 xi153/xi86/mi47 24 | xi152/xi86/mi33 xi153/xi86/mi33 25 | xi152/xi86/m9 xi153/xi86/m9 26 | xi152/xi86/m10 xi153/xi86/m10 27 | xi152/xi86/mi43 xi153/xi86/mi43 28 | xi152/xi86/mi6 xi153/xi86/mi6 29 | xi152/xi86/m11 xi153/xi86/m11 30 | xi152/xi86/m12 xi153/xi86/m12 31 | xi152/xi86/m13 xi153/xi86/m13 32 | xi152/xi86/mi44 xi153/xi86/mi44 33 | xi152/xi86/m14 xi153/xi86/m14 34 | xi152/xi86/m15 xi153/xi86/m15 35 | xi152/xi86/m16 xi153/xi86/m16 36 | xi152/xi86/mi16 xi153/xi86/mi16 37 | xi152/xi86/m17 xi153/xi86/m17 38 | xi152/xi86/mi32 xi153/xi86/mi32 39 | xi152/xi86/mi45 xi153/xi86/mi45 40 | xi152/xi86/mi7 xi153/xi86/mi7 41 | xi88/m0 xi92/m0 42 | xi88/mi4 xi92/mi4 43 | xi88/m1 xi92/m1 44 | xi88/m2 xi92/m2 45 | xi88/mi29 xi92/mi29 46 | xi88/mi15 xi92/mi15 47 | xi88/m3 xi92/m3 48 | xi88/m4 xi92/m4 49 | xi88/m5 xi92/m5 50 | xi88/mi5 xi92/mi5 51 | xi88/mi49 xi92/mi49 52 | xi88/m6 xi92/m6 53 | xi88/mi26 xi92/mi26 54 | xi88/mi48 xi92/mi48 55 | xi88/m7 xi92/m7 56 | xi88/m8 xi92/m8 57 | xi88/mi47 xi92/mi47 58 | xi88/mi33 xi92/mi33 59 | xi88/m9 xi92/m9 60 | xi88/m10 xi92/m10 61 | xi88/mi43 xi92/mi43 62 | xi88/mi6 xi92/mi6 63 | xi88/m11 xi92/m11 64 | xi88/m12 xi92/m12 65 | xi88/m13 xi92/m13 66 | xi88/mi44 xi92/mi44 67 | xi88/m14 xi92/m14 68 | xi88/m15 xi92/m15 69 | xi88/m16 xi92/m16 70 | xi88/mi16 xi92/mi16 71 | xi88/m17 xi92/m17 72 | xi88/mi32 xi92/mi32 73 | xi88/mi45 xi92/mi45 74 | xi88/mi7 xi92/mi7 75 | xi155/xr19 xi154/xr19 76 | xi155/xr48 xi154/xr48 77 | xi155/xi86/m0 xi154/xi86/m0 78 | xi155/xi86/mi4 xi154/xi86/mi4 79 | xi155/xi86/m1 xi154/xi86/m1 80 | xi155/xi86/m2 xi154/xi86/m2 81 | xi155/xi86/mi29 xi154/xi86/mi29 82 | xi155/xi86/mi15 xi154/xi86/mi15 83 | xi155/xi86/m3 xi154/xi86/m3 84 | xi155/xi86/m4 xi154/xi86/m4 85 | xi155/xi86/m5 xi154/xi86/m5 86 | xi155/xi86/mi5 xi154/xi86/mi5 87 | xi155/xi86/mi49 xi154/xi86/mi49 88 | xi155/xi86/m6 xi154/xi86/m6 89 | xi155/xi86/mi26 xi154/xi86/mi26 90 | xi155/xi86/mi48 xi154/xi86/mi48 91 | xi155/xi86/m7 xi154/xi86/m7 92 | xi155/xi86/m8 xi154/xi86/m8 93 | xi155/xi86/mi47 xi154/xi86/mi47 94 | xi155/xi86/mi33 xi154/xi86/mi33 95 | xi155/xi86/m9 xi154/xi86/m9 96 | xi155/xi86/m10 xi154/xi86/m10 97 | xi155/xi86/mi43 xi154/xi86/mi43 98 | xi155/xi86/mi6 xi154/xi86/mi6 99 | xi155/xi86/m11 xi154/xi86/m11 100 | xi155/xi86/m12 xi154/xi86/m12 101 | xi155/xi86/m13 xi154/xi86/m13 102 | xi155/xi86/mi44 xi154/xi86/mi44 103 | xi155/xi86/m14 xi154/xi86/m14 104 | xi155/xi86/m15 xi154/xi86/m15 105 | xi155/xi86/m16 xi154/xi86/m16 106 | xi155/xi86/mi16 xi154/xi86/mi16 107 | xi155/xi86/m17 xi154/xi86/m17 108 | xi155/xi86/mi32 xi154/xi86/mi32 109 | xi155/xi86/mi45 xi154/xi86/mi45 110 | xi155/xi86/mi7 xi154/xi86/mi7 111 | xi99/m0 xi97/m0 112 | xi99/mi4 xi97/mi4 113 | xi99/m1 xi97/m1 114 | xi99/m2 xi97/m2 115 | xi99/mi29 xi97/mi29 116 | xi99/mi15 xi97/mi15 117 | xi99/m3 xi97/m3 118 | xi99/m4 xi97/m4 119 | xi99/m5 xi97/m5 120 | xi99/mi5 xi97/mi5 121 | xi99/mi49 xi97/mi49 122 | xi99/m6 xi97/m6 123 | xi99/mi26 xi97/mi26 124 | xi99/mi48 xi97/mi48 125 | xi99/m7 xi97/m7 126 | xi99/m8 xi97/m8 127 | xi99/mi47 xi97/mi47 128 | xi99/mi33 xi97/mi33 129 | xi99/m9 xi97/m9 130 | xi99/m10 xi97/m10 131 | xi99/mi43 xi97/mi43 132 | xi99/mi6 xi97/mi6 133 | xi99/m11 xi97/m11 134 | xi99/m12 xi97/m12 135 | xi99/m13 xi97/m13 136 | xi99/mi44 xi97/mi44 137 | xi99/m14 xi97/m14 138 | xi99/m15 xi97/m15 139 | xi99/m16 xi97/m16 140 | xi99/mi16 xi97/mi16 141 | xi99/m17 xi97/m17 142 | xi99/mi32 xi97/mi32 143 | xi99/mi45 xi97/mi45 144 | xi99/mi7 xi97/mi7 145 | xi164/xc0<3> xi164/xc0<0> 146 | xi164/xc0<2> xi164/xc0<1> 147 | xi160/xm11 xi160/xm14 148 | xi160/xm15 xi160/xm12 149 | xi160/xr11 xi160/xr12 150 | xi160/xc21 xi160/xc22 151 | xi160/xm27 xi160/xm26 152 | xi160/xm0 xi160/xm3 153 | xi160/xm2 xi160/xm4 154 | xi161/xm11 xi161/xm14 155 | xi161/xm15 xi161/xm12 156 | xi161/xr11 xi161/xr12 157 | xi161/xc21 xi161/xc22 158 | xi161/xm27 xi161/xm26 159 | xi161/xm0 xi161/xm3 160 | xi161/xm2 xi161/xm4 161 | xi146/xm18 xi146/xm2 162 | xi146/xm1 xi146/xm12 163 | xi146/xm14 xi146/xm13 164 | xi146/xm4 xi146/xm3 165 | xi146/xm5 xi146/xm6 166 | xi146/xm0 xi146/xm22 167 | xi146/xm15 xi146/xm8 168 | xi146/xm17 xi146/xm16 169 | xi128/xi0/m0 xi128/xi1/m0 170 | xi128/xi0/m1 xi128/xi1/m1 171 | xi128/xi0/m2 xi128/xi1/m2 172 | xi128/xi0/m3 xi128/xi1/m3 173 | xi154/xr19 xi154/xr48 174 | xi152/xr19 xi152/xr48 175 | xi153/xr19 xi153/xr48 176 | xi155/xr19 xi155/xr48 177 | -------------------------------------------------------------------------------- /AND_PREAMP_v5.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .subckt AND8_half_v5 begin_b cbbb1 gnd l<6> l<5> l<4> r1b<6> r1b<5> r1b<4> vdd_and 5 | 6 | xm104 cbbb1 r1b<5> net024 vdd_and pch_lvt_mac l=40e-9 w=820e-9 multi=1 nf=4 7 | 8 | xm112 net024 l<4> vdd_and vdd_and pch_lvt_mac l=40e-9 w=4.1e-6 multi=1 nf=5 9 | 10 | xm103 cbbb1 r1b<4> vdd_and vdd_and pch_lvt_mac l=40e-9 w=1.23e-6 multi=1 nf=2 11 | 12 | xm113 net027 l<5> vdd_and vdd_and pch_lvt_mac l=40e-9 w=3.28e-6 multi=1 nf=16 13 | 14 | xm105 cbbb1 r1b<6> net027 vdd_and pch_lvt_mac l=40e-9 w=820e-9 multi=1 nf=4 15 | 16 | xm107 net028 begin_b vdd_and vdd_and pch_lvt_mac l=40e-9 w=3.28e-6 multi=1 nf=16 17 | 18 | xm98 cbbb1 l<6> net028 vdd_and pch_lvt_mac l=40e-9 w=820e-9 multi=1 nf=4 19 | 20 | xm92 cbbb1 l<6> net026 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 21 | 22 | xm86 net026 r1b<6> gnd gnd nch_lvt_mac l=40e-9 w=2.48e-6 multi=1 nf=16 23 | 24 | xm91 net025 r1b<5> gnd gnd nch_lvt_mac l=40e-9 w=2.48e-6 multi=1 nf=16 25 | 26 | xm96 cbbb1 l<5> net025 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 27 | 28 | xm90 net023 r1b<4> gnd gnd nch_lvt_mac l=40e-9 w=3.1e-6 multi=1 nf=5 29 | 30 | xm132 cbbb1 begin_b gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 31 | 32 | xm97 cbbb1 l<4> net023 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 33 | .ends AND8_half_v5 34 | 35 | .subckt AND8_half2_v5 cbbb2 gnd l<3> l<2> l<1> r1b<3> r1b<2> r1b<1> vdd_and 36 | 37 | xm143 cbbb2 r1b<2> net020 vdd_and pch_lvt_mac l=40e-9 w=820e-9 multi=1 nf=4 38 | 39 | xm144 cbbb2 r1b<1> vdd_and vdd_and pch_lvt_mac l=40e-9 w=1.23e-6 multi=1 nf=2 40 | 41 | xm102 cbbb2 l<3> vdd_and vdd_and pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 42 | 43 | xm146 net020 l<1> vdd_and vdd_and pch_lvt_mac l=40e-9 w=3.28e-6 multi=1 nf=16 44 | 45 | xm142 cbbb2 r1b<3> net022 vdd_and pch_lvt_mac l=40e-9 w=820e-9 multi=1 nf=4 46 | 47 | xm145 net022 l<2> vdd_and vdd_and pch_lvt_mac l=40e-9 w=3.28e-6 multi=1 nf=16 48 | 49 | xm130 cbbb2 l<2> net021 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 50 | 51 | xm128 net021 r1b<2> gnd gnd nch_lvt_mac l=40e-9 w=2.48e-6 multi=1 nf=16 52 | 53 | xm129 net019 r1b<1> gnd gnd nch_lvt_mac l=40e-9 w=3.1e-6 multi=1 nf=5 54 | 55 | xm131 cbbb2 l<1> net019 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 56 | 57 | xm206 cbbb2 l<3> net023 gnd nch_lvt_mac l=40e-9 w=620e-9 multi=1 nf=4 58 | 59 | xm127 net023 r1b<3> gnd gnd nch_lvt_mac l=40e-9 w=2.48e-6 multi=1 nf=16 60 | .ends AND8_half2_v5 61 | 62 | .subckt NAND_s2 a1 a2 zn vdd vss 63 | 64 | xm2 zn a2 vdd vdd pch_lvt_mac l=40e-9 w=3.6e-6 multi=1 nf=30 65 | 66 | xm4 zn a1 vdd vdd pch_lvt_mac l=40e-9 w=3.6e-6 multi=1 nf=30 67 | 68 | xm0 net16 a2 vss vss nch_lvt_mac l=40e-9 w=3.6e-6 multi=1 nf=30 69 | 70 | xm5 zn a1 net16 vss nch_lvt_mac l=40e-9 w=3.6e-6 multi=1 nf=30 71 | .ends NAND_s2 72 | 73 | .subckt INVD12BWP i zn vdd vss 74 | 75 | xm6 zn i vdd vdd pch_lvt_mac l=40e-9 w=4.92e-6 multi=1 nf=1 76 | 77 | xm5 zn i vss vss nch_lvt_mac l=40e-9 w=3.72e-6 multi=1 nf=1 78 | .ends INVD12BWP 79 | 80 | .subckt COMPARATOR_PRE_AMP clk crossn crossp gnd intern interp outm outp vdd _net0 _net1 81 | 82 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 83 | 84 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 85 | 86 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=12 87 | 88 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=12 89 | 90 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 91 | 92 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 93 | 94 | xm7 net050 clk gnd gnd nch_lvt_mac l=40e-9 w=8.64e-6 multi=1 nf=72 95 | 96 | xm5 intern _net0 net050 gnd nch_lvt_mac l=40e-9 w=9.6e-6 multi=1 nf=10 97 | 98 | xm6 interp _net1 net050 gnd nch_lvt_mac l=40e-9 w=9.6e-6 multi=1 nf=10 99 | 100 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=2.88e-6 multi=1 nf=6 101 | 102 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 103 | 104 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=2.88e-6 multi=1 nf=6 105 | 106 | xm19 interp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 107 | 108 | xm10 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 109 | 110 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=1 111 | 112 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=32 113 | 114 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=32 115 | .ends COMPARATOR_PRE_AMP 116 | 117 | .topckt AND_PREAMP_v5 begin_b cbbb1 cbbb2 crossn crossp fire_pre_amp gnd inn inp intern interp l<6> l<5> l<4> l<3> l<2> l<1> r1b<6> r1b<5> r1b<4> r1b<3> r1b<2> r1b<1> rn rp vdd_and vdd_c 118 | 119 | xi144 begin_b cbbb1 gnd l<6> l<5> l<4> r1b<6> r1b<5> r1b<4> vdd_and AND8_half_v5 120 | 121 | xi145 cbbb2 gnd l<3> l<2> l<1> r1b<3> r1b<2> r1b<1> vdd_and AND8_half2_v5 122 | 123 | xi83 cbbb1 cbbb2 net26 vdd_and gnd NAND_s2 124 | 125 | xi82 net26 fire_pre_amp vdd_and gnd INVD12BWP 126 | 127 | xi127 fire_pre_amp crossn crossp gnd intern interp rn rp vdd_c inp inn COMPARATOR_PRE_AMP 128 | .ends AND_PREAMP_v5 129 | -------------------------------------------------------------------------------- /s3det/ADC_CORE.s3det: -------------------------------------------------------------------------------- 1 | ADC_CORE/xi1/xi2 2 | xi1 xi3 3 | xi1 xi4 4 | xi1 xi5 5 | xi1 xi6 6 | xi1 xi7 7 | xi8 xi1 8 | xi3 xi4 9 | xi3 xi5 10 | xi3 xi6 11 | xi3 xi7 12 | xi8 xi3 13 | xi4 xi5 14 | xi4 xi6 15 | xi4 xi7 16 | xi8 xi4 17 | xi5 xi6 18 | xi5 xi7 19 | xi8 xi5 20 | xi6 xi7 21 | xi8 xi6 22 | xi8 xi7 23 | 24 | ADC_CORE 25 | xi12 xi11 26 | xi0 xi1 27 | 28 | ADC_CORE/xi3/xi1 29 | xi3<2> xi2<2> 30 | xi2<6> xi2<4> 31 | xi2<6> xi3<3> 32 | xi2<6> xi3<7> 33 | xi2<6> xi2<8> 34 | xi2<6> xi3<5> 35 | xi2<6> xi2<3> 36 | xi2<6> xi3<8> 37 | xi2<5> xi2<6> 38 | xi2<6> xi2<7> 39 | xi3<4> xi2<6> 40 | xi2<6> xi3<6> 41 | xi2<4> xi3<9> 42 | xi2<8> xi3<9> 43 | xi3<5> xi3<9> 44 | xi2<9> xi3<9> 45 | xi2<4> xi3<3> 46 | xi3<7> xi2<4> 47 | xi2<4> xi2<8> 48 | xi2<4> xi3<5> 49 | xi2<3> xi2<4> 50 | xi2<4> xi3<8> 51 | xi2<5> xi2<4> 52 | xi2<4> xi2<7> 53 | xi3<4> xi2<4> 54 | xi2<4> xi3<1> 55 | xi2<4> xi3<6> 56 | xi1<6> xi1<2> 57 | xi1<2> xi1<4> 58 | xi1<8> xi1<2> 59 | xi1<7> xi1<2> 60 | xi1<2> xi1<9> 61 | xi0 xi1<2> 62 | xi3<7> xi3<3> 63 | xi3<3> xi2<8> 64 | xi3<5> xi3<3> 65 | xi2<3> xi3<3> 66 | xi3<8> xi3<3> 67 | xi2<5> xi3<3> 68 | xi3<3> xi2<7> 69 | xi3<4> xi3<3> 70 | xi3<3> xi3<6> 71 | xi1<6> xi1<4> 72 | xi1<6> xi1<8> 73 | xi1<6> xi1<7> 74 | xi1<6> xi1<9> 75 | xi1<6> xi0 76 | xi3<7> xi2<8> 77 | xi3<7> xi3<5> 78 | xi3<7> xi2<3> 79 | xi3<7> xi3<8> 80 | xi2<5> xi3<7> 81 | xi3<7> xi2<7> 82 | xi3<4> xi3<7> 83 | xi3<7> xi3<6> 84 | xi1<8> xi1<4> 85 | xi1<9> xi1<4> 86 | xi0 xi1<4> 87 | xi3<5> xi2<8> 88 | xi2<3> xi2<8> 89 | xi3<8> xi2<8> 90 | xi2<5> xi2<8> 91 | xi2<7> xi2<8> 92 | xi3<4> xi2<8> 93 | xi3<1> xi2<8> 94 | xi3<6> xi2<8> 95 | xi1<8> xi1<7> 96 | xi1<8> xi1<9> 97 | xi0 xi1<8> 98 | xi2<3> xi3<5> 99 | xi3<5> xi3<8> 100 | xi2<5> xi3<5> 101 | xi3<5> xi2<7> 102 | xi3<4> xi3<5> 103 | xi3<5> xi3<1> 104 | xi3<5> xi3<6> 105 | xi2<3> xi3<8> 106 | xi2<5> xi2<3> 107 | xi2<3> xi2<7> 108 | xi3<4> xi2<3> 109 | xi2<3> xi3<6> 110 | xi2<5> xi3<8> 111 | xi3<8> xi2<7> 112 | xi3<4> xi3<8> 113 | xi3<8> xi3<6> 114 | xi2<1> xi3<1> 115 | xi2<5> xi2<7> 116 | xi2<5> xi3<4> 117 | xi2<5> xi3<6> 118 | xi1<5> xi1<1> 119 | xi3<4> xi2<7> 120 | xi3<6> xi2<7> 121 | xi3<4> xi3<6> 122 | xi0 xi1<9> 123 | 124 | ADC_CORE/xi3/xi0 125 | xi18<1> xi18<7> 126 | xi18<1> xi18<3> 127 | xi18<1> xi18<8> 128 | xi18<1> xi18<4> 129 | xi18<1> xi18<6> 130 | xi18<1> xi18<2> 131 | xi18<1> xi18<9> 132 | xi18<1> xi18<10> 133 | xi18<1> xi18<5> 134 | xi16<2> xi16<10> 135 | xi16<4> xi16<10> 136 | xi16<10> xi16<6> 137 | xi16<10> xi16<9> 138 | xi16<10> xi16<3> 139 | xi16<7> xi16<10> 140 | xi16<10> xi16<1> 141 | xi16<5> xi16<10> 142 | xi16<10> xi16<8> 143 | xi18<3> xi18<7> 144 | xi18<7> xi18<8> 145 | xi18<4> xi18<7> 146 | xi18<6> xi18<7> 147 | xi18<2> xi18<7> 148 | xi18<9> xi18<7> 149 | xi18<10> xi18<7> 150 | xi18<5> xi18<7> 151 | xi18<3> xi18<8> 152 | xi18<3> xi18<4> 153 | xi18<3> xi18<6> 154 | xi18<2> xi18<3> 155 | xi18<9> xi18<3> 156 | xi18<3> xi18<10> 157 | xi18<3> xi18<5> 158 | xi16<4> xi16<2> 159 | xi16<2> xi16<6> 160 | xi16<2> xi16<9> 161 | xi16<2> xi16<3> 162 | xi16<7> xi16<2> 163 | xi16<2> xi16<1> 164 | xi16<5> xi16<2> 165 | xi16<2> xi16<8> 166 | xi16<4> xi16<6> 167 | xi16<4> xi16<9> 168 | xi16<4> xi16<3> 169 | xi16<7> xi16<4> 170 | xi16<4> xi16<1> 171 | xi16<4> xi16<5> 172 | xi16<4> xi16<8> 173 | xi16<9> xi16<6> 174 | xi16<3> xi16<6> 175 | xi16<7> xi16<6> 176 | xi16<1> xi16<6> 177 | xi16<5> xi16<6> 178 | xi16<8> xi16<6> 179 | xi18<4> xi18<8> 180 | xi18<6> xi18<8> 181 | xi18<2> xi18<8> 182 | xi18<9> xi18<8> 183 | xi18<10> xi18<8> 184 | xi18<5> xi18<8> 185 | xi18<4> xi18<6> 186 | xi18<2> xi18<4> 187 | xi18<9> xi18<4> 188 | xi18<4> xi18<10> 189 | xi18<4> xi18<5> 190 | xi16<3> xi16<9> 191 | xi16<7> xi16<9> 192 | xi16<1> xi16<9> 193 | xi16<5> xi16<9> 194 | xi16<8> xi16<9> 195 | xi18<2> xi18<6> 196 | xi18<9> xi18<6> 197 | xi18<6> xi18<10> 198 | xi18<5> xi18<6> 199 | xi18<9> xi18<2> 200 | xi18<2> xi18<10> 201 | xi18<2> xi18<5> 202 | xi16<7> xi16<3> 203 | xi16<3> xi16<1> 204 | xi16<5> xi16<3> 205 | xi16<3> xi16<8> 206 | xi16<7> xi16<1> 207 | xi16<7> xi16<5> 208 | xi16<7> xi16<8> 209 | xi16<5> xi16<1> 210 | xi16<8> xi16<1> 211 | xi16<5> xi16<8> 212 | xi18<9> xi18<10> 213 | xi18<9> xi18<5> 214 | xi18<5> xi18<10> 215 | 216 | ADC_CORE/xi3/xi1/xi1<2> 217 | xi0 xi1 218 | 219 | ADC_CORE/xi3/xi1/xi1<3> 220 | xi0 xi1 221 | 222 | ADC_CORE/xi3/xi1/xi1<6> 223 | xi0 xi1 224 | 225 | ADC_CORE/xi3/xi1/xi0 226 | xi0 xi1 227 | 228 | ADC_CORE/xi3/xi1/xi1<1> 229 | xi0 xi1 230 | 231 | ADC_CORE/xi0/xi2 232 | xi1 xi3 233 | xi1 xi4 234 | xi1 xi5 235 | xi1 xi6 236 | xi1 xi7 237 | xi8 xi1 238 | xi3 xi4 239 | xi3 xi5 240 | xi3 xi6 241 | xi3 xi7 242 | xi8 xi3 243 | xi4 xi5 244 | xi4 xi6 245 | xi4 xi7 246 | xi8 xi4 247 | xi5 xi6 248 | xi5 xi7 249 | xi8 xi5 250 | xi6 xi7 251 | xi8 xi7 252 | 253 | ADC_CORE/xi3/xi1/xi1<5> 254 | xi0 xi1 255 | 256 | ADC_CORE/xi3/xi1/xi1<4> 257 | xi0 xi1 258 | 259 | ADC_CORE/xi3/xi1/xi1<9> 260 | xi0 xi1 261 | 262 | ADC_CORE/xi3/xi1/xi1<8> 263 | xi0 xi1 264 | 265 | ADC_CORE/xi3/xi1/xi1<7> 266 | xi0 xi1 267 | 268 | -------------------------------------------------------------------------------- /COMP_GM_STAGE_0415.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .subckt INVD1BWP i zn vdd vss 5 | 6 | m0 zn i vss vss nch l=40e-9 w=310e-9 m=1 nf=1 7 | 8 | m1 zn i vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 9 | .ends INVD1BWP 10 | 11 | .subckt COMP_GM_STAGE_BIAS_0415 gnd vbn vbp vcm vdd_a 12 | 13 | xm4 gnd vbn gnd gnd nch_lvt_mac l=2e-6 w=2e-6 multi=5 nf=1 14 | 15 | xm0 vbn vbn gnd gnd nch_lvt_mac l=2e-6 w=2e-6 multi=1 nf=1 16 | 17 | xm1 vbp vcm net5 net5 pch_mac l=500e-9 w=10e-6 multi=1 nf=2 18 | 19 | xm5 vbp vbp vbp net5 pch_mac l=500e-9 w=10e-6 multi=1 nf=2 20 | 21 | xm8 net5 vbp vdd_a vdd_a pch_lvt_mac l=1e-6 w=8e-6 multi=1 nf=2 22 | 23 | xm3 vdd_a vbp vdd_a vdd_a pch_lvt_mac l=1e-6 w=8e-6 multi=5 nf=2 24 | .ends COMP_GM_STAGE_BIAS_0415 25 | 26 | .topckt COMP_GM_STAGE_0415 calm calp cco_icalm cco_icalp clk gnd ictrm ictrp inm inp outm outp valid_vco vbn vbp vcc_comp vcc_gm vcm pre_charge 27 | 28 | xm91 net89 valid_vco_d vcc_gm vcc_gm pch_mac l=40e-9 w=480e-9 multi=1 nf=2 29 | 30 | xm89 net073 valid_vco_b cco_icalm vcc_gm pch_mac l=40e-9 w=960e-9 multi=1 nf=4 31 | 32 | xm90 net073 valid_vco_d vcc_gm vcc_gm pch_mac l=40e-9 w=480e-9 multi=1 nf=2 33 | 34 | xm92 net89 valid_vco_b cco_icalp vcc_gm pch_mac l=40e-9 w=960e-9 multi=1 nf=4 35 | 36 | xm87 ictrp net89 vcc_gm vcc_gm pch_mac l=4e-6 w=4e-6 multi=1 nf=1 37 | 38 | xm7 net78 valid_vco_b vbp vcc_gm pch_mac l=40e-9 w=960e-9 multi=1 nf=4 39 | 40 | xm4 net78 valid_vco_d vcc_gm vcc_gm pch_mac l=40e-9 w=480e-9 multi=1 nf=2 41 | 42 | xm88 ictrm net073 vcc_gm vcc_gm pch_mac l=4e-6 w=4e-6 multi=1 nf=1 43 | 44 | xm45 net070 net070 net070 net070 pch_mac l=500e-9 w=10e-6 multi=1 nf=2 45 | 46 | xm86 vcc_comp vcc_comp vcc_comp vcc_comp pch_mac l=500e-9 w=20e-6 multi=1 nf=4 47 | 48 | xm64 ictrm valid_vco_b net019 vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 49 | 50 | xm82 outm net054 vcc_comp vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 51 | 52 | xm17 net83 valid_vco_d net019 vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 53 | 54 | xm81 net054 calm net054 net054 pch_mac l=300e-9 w=900e-9 multi=1 nf=1 55 | 56 | xm11 net019 inp net070 net070 pch_mac l=500e-9 w=50e-6 multi=1 nf=4 57 | 58 | xm55 net042 inm net070 net070 pch_mac l=500e-9 w=50e-6 multi=1 nf=4 59 | 60 | xm2 net030 net054 net83 vcc_comp pch_mac l=100e-9 w=7.68e-6 multi=1 nf=8 61 | 62 | xm6 outp net030 vcc_comp vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 63 | 64 | xm76 ictrp valid_vco_b net042 vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 65 | 66 | xm78 net054 net030 net90 vcc_comp pch_mac l=100e-9 w=7.68e-6 multi=1 nf=8 67 | 68 | xm73 net90 valid_vco_d net042 vcc_comp pch_mac l=40e-9 w=960e-9 multi=1 nf=2 69 | 70 | xm13 net030 calp net030 net030 pch_mac l=300e-9 w=900e-9 multi=1 nf=1 71 | 72 | xm44 ictrp valid_vco_b pre_charge gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 73 | 74 | xm43 ictrm valid_vco_b pre_charge gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 75 | 76 | xm63 ictrm valid_vco_d net019 gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 77 | 78 | xm83 outm net054 gnd gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 79 | 80 | xm19 net83 valid_vco_b net019 gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 81 | 82 | xm80 net054 clkb gnd gnd nch_mac l=40e-9 w=240e-9 multi=1 nf=1 83 | 84 | xm74 net90 valid_vco_b net042 gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 85 | 86 | xm26 net83 clkb gnd gnd nch_mac l=40e-9 w=240e-9 multi=1 nf=1 87 | 88 | xm75 net90 clkb gnd gnd nch_mac l=40e-9 w=240e-9 multi=1 nf=1 89 | 90 | xm77 ictrp valid_vco_d net042 gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 91 | 92 | xm21 outp net030 gnd gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 93 | 94 | xm79 net054 net030 gnd gnd nch_mac l=100e-9 w=3.84e-6 multi=1 nf=8 95 | 96 | xm23 net030 clkb gnd gnd nch_mac l=40e-9 w=240e-9 multi=1 nf=1 97 | 98 | xm18 net030 net054 gnd gnd nch_mac l=100e-9 w=3.84e-6 multi=1 nf=8 99 | 100 | xm57 vcc_gm vbp vcc_gm vcc_gm pch_lvt_mac l=4.5e-6 w=5e-6 multi=2 nf=1 101 | 102 | xm56 vcc_gm vbp vcc_gm vcc_gm pch_lvt_mac l=5e-6 w=5e-6 multi=8 nf=1 103 | 104 | xm52 net070 clkb net036 net036 pch_lvt_mac l=40e-9 w=2e-6 multi=1 nf=1 105 | 106 | xm51 net036 vbp vcc_comp vcc_gm pch_lvt_mac l=1e-6 w=8e-6 multi=10 nf=2 107 | 108 | xm0 net070 net78 vcc_gm vcc_gm pch_lvt_mac l=1e-6 w=8e-6 multi=10 nf=2 109 | 110 | xi4<1> valid_vco valid_vco_b vcc_comp gnd INVD1BWP 111 | 112 | xi4<0> valid_vco valid_vco_b vcc_comp gnd INVD1BWP 113 | 114 | xi5<1> valid_vco_b valid_vco_d vcc_comp gnd INVD1BWP 115 | 116 | xi5<0> valid_vco_b valid_vco_d vcc_comp gnd INVD1BWP 117 | 118 | xi6<1> clk clkb vcc_comp gnd INVD1BWP 119 | 120 | xi6<0> clk clkb vcc_comp gnd INVD1BWP 121 | 122 | xm38 ictrm net089 gnd gnd nch_lvt_mac l=2e-6 w=2e-6 multi=10 nf=1 123 | 124 | xm33 ictrp net059 gnd gnd nch_lvt_mac l=2e-6 w=2e-6 multi=10 nf=1 125 | 126 | d2 gnd vcc_gm dnwpsub area=678.97e-12 pj=106.16e-6 m=1 127 | 128 | d0 gnd vcc_gm pwdnw area=495.033e-12 pj=103.03e-6 m=1 129 | 130 | xm9 net089 valid_vco_d vbn gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 131 | 132 | xm8 net059 valid_vco_d vbn gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 133 | 134 | xm5 net059 valid_vco_b gnd gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 135 | 136 | xm10 net089 valid_vco_b gnd gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=2 137 | 138 | xm12 gnd vbn gnd gnd nch_lvt_mac l=2e-6 w=4e-6 multi=2 nf=1 139 | 140 | xm3 gnd vbn gnd gnd nch_lvt_mac l=4e-6 w=2e-6 multi=12 nf=1 141 | 142 | xm1 gnd vbn gnd gnd nch_lvt_mac l=4e-6 w=4e-6 multi=4 nf=1 143 | 144 | xi0 gnd vbn vbp vcm vcc_gm COMP_GM_STAGE_BIAS_0415 145 | .ends COMP_GM_STAGE_0415 146 | -------------------------------------------------------------------------------- /COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .subckt NR2D2BWP a1 a2 zn vdd vss 5 | 6 | m0 zn a2 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 7 | 8 | m1 zn a1 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 9 | 10 | m2 zn a1 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 11 | 12 | m3 zn a2 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 13 | 14 | m4 zn a1 net17 vdd pch l=40e-9 w=410e-9 m=1 nf=1 15 | 16 | m5 net25 a2 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 17 | 18 | m6 zn a1 net25 vdd pch l=40e-9 w=410e-9 m=1 nf=1 19 | 20 | m7 net17 a2 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 21 | .ends NR2D2BWP 22 | 23 | .subckt INVD0BWP i zn vdd vss 24 | 25 | m0 zn i vss vss nch l=40e-9 w=155e-9 m=1 nf=1 26 | 27 | m1 zn i vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 28 | .ends INVD0BWP 29 | 30 | .subckt CLK_BOOST_COMP bypass clk_boost clk_in gnd vdd 31 | 32 | xm5 net8 net5 vdd vdd pch_mac l=40e-9 w=960e-9 multi=1 nf=2 33 | 34 | xm4 clk_boost net6 net8 vdd pch_mac l=40e-9 w=960e-9 multi=1 nf=4 35 | 36 | xm1 net5 net6 net8 vdd pch_mac l=40e-9 w=120e-9 multi=1 nf=1 37 | 38 | xm6 clk_boost net6 clk_in gnd nch_mac l=40e-9 w=480e-9 multi=1 nf=4 39 | 40 | xm2 net5 net6 net013 gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 41 | 42 | xi1 net6 bypass net013 vdd gnd NR2D2BWP 43 | 44 | xi2 clk_in net6 vdd gnd INVD0BWP 45 | 46 | xc2 net013 net8 vdd crtmom nv=70 nh=30 w=70e-9 s=70e-9 stm=2 spm=6 multi=1 ftip=140e-9 dmflag=0 47 | 48 | xc3 net013 net8 vdd crtmom nv=70 nh=30 w=70e-9 s=70e-9 stm=2 spm=6 multi=1 ftip=140e-9 dmflag=0 49 | .ends CLK_BOOST_COMP 50 | 51 | .topckt COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW clk clkn fine fine_boost flip flipb gnd intern interp outm outp vdd _net0 _net1 vmid vmidb vxn vxn2 vxp vxp2 52 | 53 | xi3 gnd fine_boost fine gnd vdd CLK_BOOST_COMP 54 | 55 | xi4 gnd net073 vdd gnd INVD0BWP 56 | 57 | xi0 clk clkb vdd gnd INVD0BWP 58 | 59 | xm0 gnd net066 gnd gnd nch_mac l=1e-6 w=2e-6 multi=1 nf=1 60 | 61 | xm1 gnd net065 gnd gnd nch_mac l=1e-6 w=2e-6 multi=1 nf=1 62 | 63 | xm56 gnd gnd gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 64 | 65 | xm52 gnd gnd gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 66 | 67 | xm51 gnd gnd gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 68 | 69 | xm50 gnd gnd gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 70 | 71 | xm12 vxn fine_boost net065 gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=1 72 | 73 | xm10 vxp fine_boost net066 gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=1 74 | 75 | xm31 flipb flip gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 76 | 77 | xm16 outm intern gnd gnd nch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=4 78 | 79 | xm21 flip clkb gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 80 | 81 | xm15 net05 clkn gnd gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 82 | 83 | xm14 vxn _net0 net05 gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 84 | 85 | xm32 clkn flip gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 86 | 87 | xm37 vxn2 flipb gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 88 | 89 | xm13 vxp _net1 net05 gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 90 | 91 | xm38 vmidb vxn2 gnd gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 92 | 93 | xm43 intern interp vmidb gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=2 94 | 95 | xm41 vxp2 flipb gnd gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 96 | 97 | xm42 interp intern vmid gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=2 98 | 99 | xm39 vmid vxp2 gnd gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 100 | 101 | xm33 clk flipb clkn gnd nch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 102 | 103 | xm6 outp interp gnd gnd nch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=4 104 | 105 | xm62 vdd clk vxp vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 106 | 107 | xm61 vdd clk vxn vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 108 | 109 | xm58 gnd gnd gnd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 110 | 111 | xm57 gnd gnd gnd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 112 | 113 | xm55 gnd gnd gnd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 114 | 115 | xm54 gnd gnd gnd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 116 | 117 | xm53 gnd gnd gnd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 118 | 119 | xm17 vxp _net1 net04 vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 120 | 121 | xm30 flipb clk vdd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 122 | 123 | xm28 flip vxn net027 vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 124 | 125 | xm20 net027 clkb vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 126 | 127 | xm2 outm intern vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=1 128 | 129 | xm29 flip vxp net027 vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 130 | 131 | xm36 vxn2 flipb vxn vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 132 | 133 | xm19 net04 flipb vdd vdd pch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=8 134 | 135 | xm18 vxn _net0 net04 vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 136 | 137 | xm34 clk flip clkn vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 138 | 139 | xm40 vxp2 flipb vxp vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 140 | 141 | xm47 intern vxn2 vdd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 142 | 143 | xm48 intern interp vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 144 | 145 | xm45 vmidb vxn2 vdd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 146 | 147 | xm49 interp intern vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 148 | 149 | xm44 vmid vxp2 vdd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 150 | 151 | xm9 outp interp vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=1 152 | 153 | xm46 interp vxp2 vdd vdd pch_lvt_mac l=40e-9 w=120e-9 multi=1 nf=1 154 | .ends COMPARATOR_2LEVEL_BIDIRECTIONAL_MAC_SKEW 155 | -------------------------------------------------------------------------------- /s3det/adc1.pair: -------------------------------------------------------------------------------- 1 | adc1/xr19 adc1/xr18 2 | adc1/xr19 adc1/input_res 3 | adc1/xr19 adc1/xr16 4 | adc1/xr19 adc1/xi22 5 | adc1/xr19 adc1/xi20 6 | adc1/xr19 adc1/xr47 7 | adc1/xr19 adc1/xr20 8 | adc1/xr19 adc1/xr21 9 | adc1/xr19 adc1/xr22 10 | adc1/xr19 adc1/xr23 11 | adc1/xr19 adc1/xr24 12 | adc1/xr19 adc1/xr25 13 | adc1/xr19 adc1/xr28 14 | adc1/xr19 adc1/xc2 15 | adc1/xr19 adc1/xc0 16 | adc1/xr19 adc1/xc1 17 | adc1/xr19 adc1/xr17 18 | adc1/xr19 adc1/xc4 19 | adc1/xr19 adc1/rr2 20 | adc1/xr19 adc1/rr1 21 | adc1/xr19 adc1/xi19 22 | adc1/xr19 adc1/rrr1 23 | adc1/xr18 adc1/input_res 24 | adc1/xr18 adc1/xr16 25 | adc1/xr18 adc1/xi22 26 | adc1/xr18 adc1/xi20 27 | adc1/xr18 adc1/xr47 28 | adc1/xr18 adc1/xr20 29 | adc1/xr18 adc1/xr21 30 | adc1/xr18 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-------------------------------------------------------------------------------- /s3det/adc1_labeled.pair: -------------------------------------------------------------------------------- 1 | adc1/xr19 adc1/xr18 2 | adc1/xr19 adc1/input_res 3 | adc1/xr19 adc1/xr16 4 | adc1/xr19 adc1/xi22 5 | adc1/xr19 adc1/xi20 6 | adc1/xr19 adc1/xr47 7 | adc1/xr19 adc1/xr20 8 | adc1/xr19 adc1/xr21 9 | adc1/xr19 adc1/xr22 10 | adc1/xr19 adc1/xr23 11 | adc1/xr19 adc1/xr24 12 | adc1/xr19 adc1/xr25 13 | adc1/xr19 adc1/xr28 14 | adc1/xr19 adc1/xc2 15 | adc1/xr19 adc1/xc0 16 | adc1/xr19 adc1/xc1 17 | adc1/xr19 adc1/xr17 18 | adc1/xr19 adc1/xc4 19 | adc1/xr19 adc1/rr2 20 | adc1/xr19 adc1/rr1 21 | adc1/xr19 adc1/xi19 22 | adc1/xr19 adc1/rrr1 23 | adc1/xr18 adc1/input_res 24 | adc1/xr18 adc1/xr16 25 | adc1/xr18 adc1/xi22 26 | adc1/xr18 adc1/xi20 27 | adc1/xr18 adc1/xr47 28 | adc1/xr18 adc1/xr20 29 | adc1/xr18 adc1/xr21 30 | adc1/xr18 adc1/xr22 31 | adc1/xr18 adc1/xr23 32 | adc1/xr18 adc1/xr24 33 | adc1/xr18 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adc1/xi20 adc1/xc0 111 | adc1/xi20 adc1/xc1 112 | adc1/xi20 adc1/xr17 113 | adc1/xi20 adc1/xc4 114 | adc1/xi20 adc1/rr2 115 | adc1/xi20 adc1/rr1 116 | adc1/xi20 adc1/xi19 117 | adc1/xi20 adc1/rrr1 118 | adc1/xr47 adc1/xr20 119 | adc1/xr47 adc1/xr21 120 | adc1/xr47 adc1/xr22 121 | adc1/xr47 adc1/xr23 122 | adc1/xr47 adc1/xr24 123 | adc1/xr47 adc1/xr25 124 | adc1/xr47 adc1/xr28 125 | adc1/xr47 adc1/xc2 126 | adc1/xr47 adc1/xc0 127 | adc1/xr47 adc1/xc1 128 | adc1/xr47 adc1/xr17 129 | adc1/xr47 adc1/xc4 130 | adc1/xr47 adc1/rr2 131 | adc1/xr47 adc1/rr1 132 | adc1/xr47 adc1/xi19 133 | adc1/xr47 adc1/rrr1 134 | adc1/xr20 adc1/xr21 135 | adc1/xr20 adc1/xr22 136 | adc1/xr20 adc1/xr23 137 | adc1/xr20 adc1/xr24 138 | adc1/xr20 adc1/xr25 139 | adc1/xr20 adc1/xr28 140 | adc1/xr20 adc1/xc2 141 | adc1/xr20 adc1/xc0 142 | adc1/xr20 adc1/xc1 143 | adc1/xr20 adc1/xr17 144 | adc1/xr20 adc1/xc4 145 | adc1/xr20 adc1/rr2 146 | adc1/xr20 adc1/rr1 147 | adc1/xr20 adc1/xi19 148 | adc1/xr20 adc1/rrr1 149 | adc1/xr21 adc1/xr22 150 | adc1/xr21 adc1/xr23 151 | adc1/xr21 adc1/xr24 152 | adc1/xr21 adc1/xr25 153 | adc1/xr21 adc1/xr28 154 | adc1/xr21 adc1/xc2 155 | adc1/xr21 adc1/xc0 156 | adc1/xr21 adc1/xc1 157 | adc1/xr21 adc1/xr17 158 | adc1/xr21 adc1/xc4 159 | adc1/xr21 adc1/rr2 160 | adc1/xr21 adc1/rr1 161 | adc1/xr21 adc1/xi19 162 | adc1/xr21 adc1/rrr1 163 | adc1/xr22 adc1/xr23 164 | adc1/xr22 adc1/xr24 165 | adc1/xr22 adc1/xr25 166 | adc1/xr22 adc1/xr28 167 | adc1/xr22 adc1/xc2 168 | adc1/xr22 adc1/xc0 169 | adc1/xr22 adc1/xc1 170 | adc1/xr22 adc1/xr17 171 | adc1/xr22 adc1/xc4 172 | adc1/xr22 adc1/rr2 173 | adc1/xr22 adc1/rr1 174 | adc1/xr22 adc1/xi19 175 | adc1/xr22 adc1/rrr1 176 | adc1/xr23 adc1/xr24 177 | adc1/xr23 adc1/xr25 178 | adc1/xr23 adc1/xr28 179 | adc1/xr23 adc1/xc2 180 | adc1/xr23 adc1/xc0 181 | adc1/xr23 adc1/xc1 182 | adc1/xr23 adc1/xr17 183 | adc1/xr23 adc1/xc4 184 | adc1/xr23 adc1/rr2 185 | adc1/xr23 adc1/rr1 186 | adc1/xr23 adc1/xi19 187 | adc1/xr23 adc1/rrr1 188 | adc1/xr24 adc1/xr25 189 | adc1/xr24 adc1/xr28 190 | adc1/xr24 adc1/xc2 191 | adc1/xr24 adc1/xc0 192 | adc1/xr24 adc1/xc1 193 | adc1/xr24 adc1/xr17 194 | adc1/xr24 adc1/xc4 195 | adc1/xr24 adc1/rr2 196 | adc1/xr24 adc1/rr1 197 | adc1/xr24 adc1/xi19 198 | adc1/xr24 adc1/rrr1 199 | adc1/xr25 adc1/xr28 200 | adc1/xr25 adc1/xc2 201 | adc1/xr25 adc1/xc0 202 | adc1/xr25 adc1/xc1 203 | adc1/xr25 adc1/xr17 204 | adc1/xr25 adc1/xc4 205 | adc1/xr25 adc1/rr2 206 | adc1/xr25 adc1/rr1 207 | adc1/xr25 adc1/xi19 208 | adc1/xr25 adc1/rrr1 209 | adc1/xr28 adc1/xc2 210 | adc1/xr28 adc1/xc0 211 | adc1/xr28 adc1/xc1 212 | adc1/xr28 adc1/xr17 213 | adc1/xr28 adc1/xc4 214 | adc1/xr28 adc1/rr2 215 | adc1/xr28 adc1/rr1 216 | adc1/xr28 adc1/xi19 217 | adc1/xr28 adc1/rrr1 218 | adc1/xc2 adc1/xc0 219 | adc1/xc2 adc1/xc1 220 | adc1/xc2 adc1/xr17 221 | adc1/xc2 adc1/xc4 222 | adc1/xc2 adc1/rr2 223 | adc1/xc2 adc1/rr1 224 | adc1/xc2 adc1/xi19 225 | adc1/xc2 adc1/rrr1 226 | adc1/xc0 adc1/xc1 227 | adc1/xc0 adc1/xr17 228 | adc1/xc0 adc1/xc4 229 | adc1/xc0 adc1/rr2 230 | adc1/xc0 adc1/rr1 231 | adc1/xc0 adc1/xi19 232 | adc1/xc0 adc1/rrr1 233 | adc1/xc1 adc1/xr17 234 | adc1/xc1 adc1/xc4 235 | adc1/xc1 adc1/rr2 236 | adc1/xc1 adc1/rr1 237 | adc1/xc1 adc1/xi19 238 | adc1/xc1 adc1/rrr1 239 | adc1/xr17 adc1/xc4 240 | adc1/xr17 adc1/rr2 241 | adc1/xr17 adc1/rr1 242 | adc1/xr17 adc1/xi19 243 | adc1/xr17 adc1/rrr1 244 | adc1/xc4 adc1/rr2 245 | adc1/xc4 adc1/rr1 246 | adc1/xc4 adc1/xi19 247 | adc1/xc4 adc1/rrr1 248 | adc1/rr2 adc1/rr1 249 | adc1/rr2 adc1/xi19 250 | adc1/rr2 adc1/rrr1 251 | adc1/rr1 adc1/xi19 252 | adc1/rr1 adc1/rrr1 253 | adc1/xi19 adc1/rrr1 254 | adc1/input_res/xr13 adc1/input_res/xr14 255 | adc1/rr2/xi25 adc1/rr2/xi24 256 | adc1/rr1/xi25 adc1/rr1/xi24 257 | adc1/rrr1/xi12 adc1/rrr1/xi4 258 | adc1/rrr1/xi12 adc1/rrr1/xi6 259 | adc1/rrr1/xi4 adc1/rrr1/xi6 260 | adc1/rrr1/xi6/xi0 adc1/rrr1/xi6/xi1 261 | -------------------------------------------------------------------------------- /open/adc/adc2.sp: -------------------------------------------------------------------------------- 1 | .subckt type:analog Gm1_v5_Practice ibias vdd vim vip vom vop vss 2 | xm8 net074 ntail1 vss vss nch_hvt_mac l=120e-9 w=3.22e-6 3 | xm2 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 4 | xm4 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 5 | xm12 ibias ibias vdd vdd pch_lvt_mac l=120e-9 w=585e-9 6 | xm11 vom ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 7 | xm14 vop ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 8 | xm26 vop vim net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 9 | xm27 vom vip net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 10 | xc21 ntail1 vom vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 11 | xc22 vop ntail1 vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 12 | xr12 ntail1 vop vss rppolywo_m lr=6.6e-6 wr=400e-9 13 | xr11 vom ntail1 vss rppolywo_m lr=6.6e-6 wr=400e-9 14 | xm3 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 15 | xm0 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 16 | .ends Gm1_v5_Practice 17 | 18 | .subckt type:digital DFCNQD2BWP d cp cdn q vdd vss 19 | m0 net63 cp vss vss nch l=40e-9 w=155e-9 20 | mi4 net61 net63 vss vss nch l=40e-9 w=310e-9 21 | m1 net97 cdn net60 vss nch l=40e-9 w=210e-9 22 | m2 net123 net95 vss vss nch l=40e-9 w=150e-9 23 | mi29 net49 net63 net17 vss nch l=40e-9 w=120e-9 24 | mi15 net123 net81 net49 vss nch l=40e-9 w=150e-9 25 | m3 net60 net49 vss vss nch l=40e-9 w=210e-9 26 | m4 net97 cdn net21 vss nch l=40e-9 w=210e-9 27 | m5 net81 net63 vss vss nch l=40e-9 w=155e-9 28 | mi5 net95 d net61 vss nch l=40e-9 w=310e-9 29 | mi49 net25 cdn vss vss nch l=40e-9 w=120e-9 30 | m6 net21 net49 vss vss nch l=40e-9 w=210e-9 31 | mi26 net17 net97 vss vss nch l=40e-9 w=120e-9 32 | mi48 net13 net123 net25 vss nch l=40e-9 w=120e-9 33 | m7 q net97 vss vss nch l=40e-9 w=310e-9 34 | m8 q net97 vss vss nch l=40e-9 w=310e-9 35 | mi47 net95 net81 net13 vss nch l=40e-9 w=120e-9 36 | mi33 net80 net97 vdd vdd pch l=40e-9 w=120e-9 37 | m9 q net97 vdd vdd pch l=40e-9 w=410e-9 38 | m10 net97 net49 vdd vdd pch l=40e-9 w=370e-9 39 | mi43 net101 net123 vdd vdd pch l=40e-9 w=120e-9 40 | mi6 net95 d net120 vdd pch l=40e-9 w=340e-9 41 | m11 q net97 vdd vdd pch l=40e-9 w=410e-9 42 | m12 net97 net49 vdd vdd pch l=40e-9 w=370e-9 43 | m13 net97 cdn vdd vdd pch l=40e-9 w=370e-9 44 | mi44 net101 cdn vdd vdd pch l=40e-9 w=120e-9 45 | m14 net97 cdn vdd vdd pch l=40e-9 w=370e-9 46 | m15 net123 net95 vdd vdd pch l=40e-9 w=180e-9 47 | m16 net63 cp vdd vdd pch l=40e-9 w=205e-9 48 | mi16 net123 net63 net49 vdd pch l=40e-9 w=180e-9 49 | m17 net81 net63 vdd vdd pch l=40e-9 w=205e-9 50 | mi32 net49 net81 net80 vdd pch l=40e-9 w=120e-9 51 | mi45 net95 net63 net101 vdd pch l=40e-9 w=120e-9 52 | mi7 net120 net81 vdd vdd pch l=40e-9 w=340e-9 53 | .ends DFCNQD2BWP 54 | 55 | .subckt type:analog C_DAC clkb in r3 r4 rstb vdd vss 56 | xr27 r3 net10 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 57 | xr64 r4 in vss rppolywo_m lr=18.67e-6 wr=1.2e-6 58 | xi94 in clkb rstb net10 vdd vss DFCNQD2BWP 59 | .ends C_DAC 60 | 61 | .subckt type:mixed FIR_DAC clk in r1 r2 rstb vdd vss 62 | xr19 r1 net3 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 63 | xr48 r2 in vss rppolywo_m lr=19.92e-6 wr=1.2e-6 64 | xi86 in clk rstb net3 vdd vss DFCNQD2BWP 65 | .ends FIR_DAC 66 | 67 | .subckt type:analog C1 a b vss 68 | xc0<3> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 69 | xc0<2> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 70 | xc0<1> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 71 | xc0<0> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 72 | .ends C1 73 | 74 | .subckt type:digital NR2D8BWP a1 a2 zn vdd vss 75 | m0 zn a2 vss vss nch l=40e-9 w=2.48e-6 76 | m1 zn a1 vss vss nch l=40e-9 w=2.48e-6 77 | m2 net13 a2 vdd vdd pch l=40e-9 w=3.28e-6 78 | m3 zn a1 net13 vdd pch l=40e-9 w=3.28e-6 79 | .ends NR2D8BWP 80 | 81 | .subckt type:digital SR_Latch q qb r s vdd vss 82 | xi1 r qb q vdd vss NR2D8BWP 83 | xi0 s q qb vdd vss NR2D8BWP 84 | .ends SR_Latch 85 | 86 | .subckt type:analog Gm2_v5_Practice ibias vdd vim vip vom vop vss 87 | xm20 vdd ibias vdd vdd pch_lvt_mac l=3.6e-6 w=2.8e-6 88 | xm18 vdd ibias vdd vdd pch_lvt_mac l=3.6e-6 w=2.8e-6 89 | xm13 vop vim net100 net100 nch_lvt_mac l=160e-9 w=1.16e-6 90 | xm21 vom vip net100 net100 nch_lvt_mac l=160e-9 w=1.16e-6 91 | xm0 ibias ibias vdd vdd pch_mac l=160e-9 w=700e-9 92 | xm24 ibias ibias vdd vdd pch_mac l=160e-9 w=700e-9 93 | xm23 vop ibias vdd vdd pch_mac l=160e-9 w=1.4e-6 94 | xm14 vom ibias vdd vdd pch_mac l=160e-9 w=1.4e-6 95 | xc22 vop ntail2 vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 96 | xc21 ntail2 vom vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 97 | xr11 vom ntail2 vss rppolywo_m lr=6.6e-6 wr=400e-9 98 | xr12 ntail2 vop vss rppolywo_m lr=6.6e-6 wr=400e-9 99 | xm22 net100 ntail2 vss vss nch_mac l=160e-9 w=3.12e-6 100 | d1 vss vdd dnwpsub area=15.12e-12 pj=16.08e-6 m=1 101 | xm12 vss ntail2 vss vss nch_lvt_mac l=2.2e-6 w=2.1e-6 102 | xm11 vss ntail2 vss vss nch_lvt_mac l=2.2e-6 w=2.1e-6 103 | d0 net100 vdd pwdnw area=9.328e-12 pj=12.88e-6 m=1 104 | .ends Gm2_v5_Practice 105 | 106 | .subckt type:analog myComparator_v3 clk gnd outm outp vdd _net0 _net1 107 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 108 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 109 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 110 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 111 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 112 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 113 | xm7 net069 clk gnd gnd nch_lvt_mac l=40e-9 w=6.9e-6 114 | xm5 intern _net0 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 115 | xm6 interp _net1 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 116 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 117 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 118 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 119 | xm2 interp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 120 | xm1 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 121 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 122 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 123 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 124 | .ends myComparator_v3 125 | 126 | .subckt type:mixed FIR_DAC_schematic clk in r1 r2 rstb vdd vss 127 | xr19 r1 net3 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 128 | xr48 r2 in vss rppolywo_m lr=19.92e-6 wr=1.2e-6 129 | xi86 in clk rstb net3 vdd vss DFCNQD2BWP 130 | .ends FIR_DAC_schematic 131 | 132 | .subckt type:analog C_DAC_schematic clkb in r3 r4 rstb vdd vss 133 | xr27 r3 net10 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 134 | xr64 r4 in vss rppolywo_m lr=18.67e-6 wr=1.2e-6 135 | xi94 in clkb rstb net10 vdd vss DFCNQD2BWP 136 | .ends C_DAC_schematic 137 | 138 | .topckt CTDSM_CORE_NEW clk clkb1 clkb2 ibias1 ibias2 outm outp rstb vdda vddd vim vip vss 139 | xi160 ibias1 vdda vo1m vo1p vo2p vo2m vss Gm1_v5_Practice 140 | xi154 clkb1 net062 vo3m vo3p rstb vdda vss FIR_DAC 141 | xi152 clk net052 vo1p vo1p rstb vdda vss FIR_DAC 142 | m1 vss clkb2 vss vss nch l=280e-9 w=280e-9 143 | m0 vss clkb1 vss vss nch l=280e-9 w=280e-9 144 | xi164 vo1p vo1m vss C1 145 | xi128 outm outp net072 net071 vddd vss SR_Latch 146 | xc6 vo3p vo3m vss crtmom nv=184 nh=182 w=70e-9 s=70e-9 stm=1 spm=6 147 | xc3 net074 net073 vss crtmom nv=178 nh=178 w=70e-9 s=70e-9 stm=1 spm=6 148 | xr16 vip vo1p vss rppolywo_m lr=19.92e-6 wr=1.2e-6 149 | xr51 net073 vo2m vss rppolywo_m lr=19.92e-6 wr=1.2e-6 150 | xr25 vo2p net074 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 151 | xr47 vim vo1m vss rppolywo_m lr=19.92e-6 wr=1.2e-6 152 | xi161 ibias2 vdda vo2m vo2p vo3p vo3m vss Gm1_v5_Practice 153 | xi88 net062 clk rstb net052 vdda vss DFCNQD2BWP 154 | xi97 outp clkb1 rstb net062 vdda vss DFCNQD2BWP 155 | xi92 net063 clk rstb net051 vdda vss DFCNQD2BWP 156 | xi99 outm clkb2 rstb net063 vdda vss DFCNQD2BWP 157 | xi146 clk vss net072 net071 vddd vo3p vo3m myComparator_v3 158 | xi153 clk net051 vo1m vo1m rstb vdda vss FIR_DAC 159 | xi155 clkb2 net063 vo3p vo3m rstb vdda vss FIR_DAC 160 | .ends CTDSM_CORE_NEW 161 | -------------------------------------------------------------------------------- /s3det/CTDSM_CORE_NEW.pair: -------------------------------------------------------------------------------- 1 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xr51 2 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xr25 3 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi128 4 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi97 5 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi88 6 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xr16 7 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi153 8 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi164 9 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xc3 10 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi99 11 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi160 12 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi155 13 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi154 14 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xc6 15 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi146 16 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi92 17 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xr47 18 | CTDSM_CORE_NEW/xi161 CTDSM_CORE_NEW/xi152 19 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xr25 20 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi128 21 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi97 22 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi88 23 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xr16 24 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi153 25 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi164 26 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xc3 27 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi99 28 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi160 29 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi155 30 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi154 31 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xc6 32 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi146 33 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi92 34 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xr47 35 | CTDSM_CORE_NEW/xr51 CTDSM_CORE_NEW/xi152 36 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi128 37 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi97 38 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi88 39 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xr16 40 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi153 41 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi164 42 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xc3 43 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi99 44 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi160 45 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi155 46 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi154 47 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xc6 48 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi146 49 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi92 50 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xr47 51 | CTDSM_CORE_NEW/xr25 CTDSM_CORE_NEW/xi152 52 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi97 53 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi88 54 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xr16 55 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi153 56 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi164 57 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xc3 58 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi99 59 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi160 60 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi155 61 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi154 62 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xc6 63 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi146 64 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi92 65 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xr47 66 | CTDSM_CORE_NEW/xi128 CTDSM_CORE_NEW/xi152 67 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi88 68 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xr16 69 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi153 70 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi164 71 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xc3 72 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi99 73 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi160 74 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi155 75 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi154 76 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xc6 77 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi146 78 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi92 79 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xr47 80 | CTDSM_CORE_NEW/xi97 CTDSM_CORE_NEW/xi152 81 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xr16 82 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi153 83 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi164 84 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xc3 85 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi99 86 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi160 87 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi155 88 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi154 89 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xc6 90 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi146 91 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi92 92 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xr47 93 | CTDSM_CORE_NEW/xi88 CTDSM_CORE_NEW/xi152 94 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi153 95 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi164 96 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xc3 97 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi99 98 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi160 99 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi155 100 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi154 101 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xc6 102 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi146 103 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi92 104 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xr47 105 | CTDSM_CORE_NEW/xr16 CTDSM_CORE_NEW/xi152 106 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi164 107 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xc3 108 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi99 109 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi160 110 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi155 111 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi154 112 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xc6 113 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi146 114 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi92 115 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xr47 116 | CTDSM_CORE_NEW/xi153 CTDSM_CORE_NEW/xi152 117 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xc3 118 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi99 119 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi160 120 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi155 121 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi154 122 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xc6 123 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi146 124 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi92 125 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xr47 126 | CTDSM_CORE_NEW/xi164 CTDSM_CORE_NEW/xi152 127 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi99 128 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi160 129 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi155 130 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi154 131 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xc6 132 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi146 133 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi92 134 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xr47 135 | CTDSM_CORE_NEW/xc3 CTDSM_CORE_NEW/xi152 136 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi160 137 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi155 138 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi154 139 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xc6 140 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi146 141 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi92 142 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xr47 143 | CTDSM_CORE_NEW/xi99 CTDSM_CORE_NEW/xi152 144 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xi155 145 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xi154 146 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xc6 147 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xi146 148 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xi92 149 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xr47 150 | CTDSM_CORE_NEW/xi160 CTDSM_CORE_NEW/xi152 151 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xi154 152 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xc6 153 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xi146 154 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xi92 155 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xr47 156 | CTDSM_CORE_NEW/xi155 CTDSM_CORE_NEW/xi152 157 | CTDSM_CORE_NEW/xi154 CTDSM_CORE_NEW/xc6 158 | CTDSM_CORE_NEW/xi154 CTDSM_CORE_NEW/xi146 159 | CTDSM_CORE_NEW/xi154 CTDSM_CORE_NEW/xi92 160 | CTDSM_CORE_NEW/xi154 CTDSM_CORE_NEW/xr47 161 | CTDSM_CORE_NEW/xi154 CTDSM_CORE_NEW/xi152 162 | CTDSM_CORE_NEW/xc6 CTDSM_CORE_NEW/xi146 163 | CTDSM_CORE_NEW/xc6 CTDSM_CORE_NEW/xi92 164 | CTDSM_CORE_NEW/xc6 CTDSM_CORE_NEW/xr47 165 | CTDSM_CORE_NEW/xc6 CTDSM_CORE_NEW/xi152 166 | CTDSM_CORE_NEW/xi146 CTDSM_CORE_NEW/xi92 167 | CTDSM_CORE_NEW/xi146 CTDSM_CORE_NEW/xr47 168 | CTDSM_CORE_NEW/xi146 CTDSM_CORE_NEW/xi152 169 | CTDSM_CORE_NEW/xi92 CTDSM_CORE_NEW/xr47 170 | CTDSM_CORE_NEW/xi92 CTDSM_CORE_NEW/xi152 171 | CTDSM_CORE_NEW/xr47 CTDSM_CORE_NEW/xi152 172 | CTDSM_CORE_NEW/xi128/xi0 CTDSM_CORE_NEW/xi128/xi1 173 | CTDSM_CORE_NEW/xi153/xr19 CTDSM_CORE_NEW/xi153/xr48 174 | CTDSM_CORE_NEW/xi153/xr19 CTDSM_CORE_NEW/xi153/xi86 175 | CTDSM_CORE_NEW/xi153/xr48 CTDSM_CORE_NEW/xi153/xi86 176 | CTDSM_CORE_NEW/xi164/xc0<3> CTDSM_CORE_NEW/xi164/xc0<1> 177 | CTDSM_CORE_NEW/xi164/xc0<3> CTDSM_CORE_NEW/xi164/xc0<2> 178 | CTDSM_CORE_NEW/xi164/xc0<3> CTDSM_CORE_NEW/xi164/xc0<0> 179 | CTDSM_CORE_NEW/xi164/xc0<1> CTDSM_CORE_NEW/xi164/xc0<2> 180 | CTDSM_CORE_NEW/xi164/xc0<1> CTDSM_CORE_NEW/xi164/xc0<0> 181 | CTDSM_CORE_NEW/xi164/xc0<2> CTDSM_CORE_NEW/xi164/xc0<0> 182 | CTDSM_CORE_NEW/xi155/xr19 CTDSM_CORE_NEW/xi155/xr48 183 | CTDSM_CORE_NEW/xi155/xr19 CTDSM_CORE_NEW/xi155/xi86 184 | CTDSM_CORE_NEW/xi155/xr48 CTDSM_CORE_NEW/xi155/xi86 185 | CTDSM_CORE_NEW/xi154/xr19 CTDSM_CORE_NEW/xi154/xr48 186 | CTDSM_CORE_NEW/xi154/xr19 CTDSM_CORE_NEW/xi154/xi86 187 | CTDSM_CORE_NEW/xi154/xr48 CTDSM_CORE_NEW/xi154/xi86 188 | CTDSM_CORE_NEW/xi152/xr19 CTDSM_CORE_NEW/xi152/xr48 189 | CTDSM_CORE_NEW/xi152/xr19 CTDSM_CORE_NEW/xi152/xi86 190 | CTDSM_CORE_NEW/xi152/xr48 CTDSM_CORE_NEW/xi152/xi86 191 | -------------------------------------------------------------------------------- /CTDSM_CORE_NEW.sp: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | .subckt type:analog Gm1_v5_Practice ibias vdd vim vip vom vop vss 5 | 6 | xm8 net074 ntail1 vss vss nch_hvt_mac l=120e-9 w=3.22e-6 multi=1 nf=4 7 | 8 | xm2 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 multi=1 nf=1 9 | 10 | xm4 vdd ibias vdd vdd pch_lvt_mac l=3.3e-6 w=2.95e-6 multi=1 nf=1 11 | 12 | xm12 ibias ibias vdd vdd pch_lvt_mac l=120e-9 w=585e-9 multi=1 nf=1 13 | 14 | xm11 vom ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 multi=1 nf=4 15 | 16 | 17 | xm14 vop ibias vdd vdd pch_lvt_mac l=120e-9 w=2.34e-6 multi=1 nf=4 18 | 19 | xm26 vop vim net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 multi=1 nf=4 20 | 21 | xm27 vom vip net074 net074 nch_lvt_mac l=120e-9 w=1.7e-6 multi=1 nf=4 22 | 23 | xc21 ntail1 vom vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 24 | 25 | xc22 vop ntail1 vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 26 | xr12 ntail1 vop vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 27 | 28 | xr11 vom ntail1 vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 29 | 30 | 31 | xm3 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 multi=1 nf=1 32 | 33 | xm0 vss ntail1 vss vss nch_lvt_mac l=2.2e-6 w=2.5e-6 multi=1 nf=1 34 | 35 | 36 | .ends Gm1_v5_Practice 37 | 38 | .subckt type:digital DFCNQD2BWP d cp cdn q vdd vss 39 | 40 | m0 net63 cp vss vss nch l=40e-9 w=155e-9 m=1 nf=1 41 | 42 | mi4 net61 net63 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 43 | 44 | m1 net97 cdn net60 vss nch l=40e-9 w=210e-9 m=1 nf=1 45 | 46 | m2 net123 net95 vss vss nch l=40e-9 w=150e-9 m=1 nf=1 47 | 48 | mi29 net49 net63 net17 vss nch l=40e-9 w=120e-9 m=1 nf=1 49 | 50 | mi15 net123 net81 net49 vss nch l=40e-9 w=150e-9 m=1 nf=1 51 | 52 | m3 net60 net49 vss vss nch l=40e-9 w=210e-9 m=1 nf=1 53 | 54 | m4 net97 cdn net21 vss nch l=40e-9 w=210e-9 m=1 nf=1 55 | 56 | m5 net81 net63 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 57 | 58 | mi5 net95 d net61 vss nch l=40e-9 w=310e-9 m=1 nf=1 59 | 60 | mi49 net25 cdn vss vss nch l=40e-9 w=120e-9 m=1 nf=1 61 | 62 | m6 net21 net49 vss vss nch l=40e-9 w=210e-9 m=1 nf=1 63 | 64 | mi26 net17 net97 vss vss nch l=40e-9 w=120e-9 m=1 nf=1 65 | 66 | mi48 net13 net123 net25 vss nch l=40e-9 w=120e-9 m=1 nf=1 67 | 68 | m7 q net97 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 69 | 70 | m8 q net97 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 71 | 72 | mi47 net95 net81 net13 vss nch l=40e-9 w=120e-9 m=1 nf=1 73 | 74 | mi33 net80 net97 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 75 | 76 | m9 q net97 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 77 | 78 | m10 net97 net49 vdd vdd pch l=40e-9 w=370e-9 m=1 nf=1 79 | 80 | mi43 net101 net123 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 81 | 82 | mi6 net95 d net120 vdd pch l=40e-9 w=340e-9 m=1 nf=1 83 | 84 | m11 q net97 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 85 | 86 | m12 net97 net49 vdd vdd pch l=40e-9 w=370e-9 m=1 nf=1 87 | 88 | m13 net97 cdn vdd vdd pch l=40e-9 w=370e-9 m=1 nf=1 89 | 90 | mi44 net101 cdn vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 91 | 92 | m14 net97 cdn vdd vdd pch l=40e-9 w=370e-9 m=1 nf=1 93 | 94 | m15 net123 net95 vdd vdd pch l=40e-9 w=180e-9 m=1 nf=1 95 | 96 | m16 net63 cp vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 97 | 98 | mi16 net123 net63 net49 vdd pch l=40e-9 w=180e-9 m=1 nf=1 99 | 100 | m17 net81 net63 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 101 | 102 | mi32 net49 net81 net80 vdd pch l=40e-9 w=120e-9 m=1 nf=1 103 | 104 | mi45 net95 net63 net101 vdd pch l=40e-9 w=120e-9 m=1 nf=1 105 | 106 | mi7 net120 net81 vdd vdd pch l=40e-9 w=340e-9 m=1 nf=1 107 | .ends DFCNQD2BWP 108 | 109 | .subckt type:analog C_DAC clkb in r3 r4 rstb vdd vss 110 | xr27 r3 net10 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 111 | 112 | xr64 r4 in vss rppolywo_m lr=18.67e-6 wr=1.2e-6 multi=1 m=1 113 | 114 | 115 | xi94 in clkb rstb net10 vdd vss DFCNQD2BWP 116 | .ends C_DAC 117 | 118 | .subckt type:mixed FIR_DAC clk in r1 r2 rstb vdd vss 119 | xr19 r1 net3 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 120 | 121 | xr48 r2 in vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 122 | 123 | 124 | xi86 in clk rstb net3 vdd vss DFCNQD2BWP 125 | .ends FIR_DAC 126 | 127 | .subckt type:analog C1 a b vss 128 | 129 | xc0<3> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 130 | 131 | xc0<2> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 132 | 133 | xc0<1> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 134 | 135 | xc0<0> a b vss crtmom nv=204 nh=204 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 136 | .ends C1 137 | 138 | .subckt type:digital NR2D8BWP a1 a2 zn vdd vss 139 | 140 | m0 zn a2 vss vss nch l=40e-9 w=2.48e-6 m=1 nf=1 141 | 142 | m1 zn a1 vss vss nch l=40e-9 w=2.48e-6 m=1 nf=1 143 | 144 | m2 net13 a2 vdd vdd pch l=40e-9 w=3.28e-6 m=1 nf=1 145 | 146 | m3 zn a1 net13 vdd pch l=40e-9 w=3.28e-6 m=1 nf=1 147 | .ends NR2D8BWP 148 | 149 | .subckt type:digital SR_Latch q qb r s vdd vss 150 | 151 | xi1 r qb q vdd vss NR2D8BWP 152 | 153 | xi0 s q qb vdd vss NR2D8BWP 154 | .ends SR_Latch 155 | 156 | .subckt type:analog Gm2_v5_Practice ibias vdd vim vip vom vop vss 157 | 158 | xm20 vdd ibias vdd vdd pch_lvt_mac l=3.6e-6 w=2.8e-6 multi=1 nf=1 159 | 160 | xm18 vdd ibias vdd vdd pch_lvt_mac l=3.6e-6 w=2.8e-6 multi=1 nf=1 161 | 162 | xm13 vop vim net100 net100 nch_lvt_mac l=160e-9 w=1.16e-6 multi=1 nf=4 163 | 164 | xm21 vom vip net100 net100 nch_lvt_mac l=160e-9 w=1.16e-6 multi=1 nf=4 165 | 166 | xm0 ibias ibias vdd vdd pch_mac l=160e-9 w=700e-9 multi=1 nf=2 167 | 168 | xm24 ibias ibias vdd vdd pch_mac l=160e-9 w=700e-9 multi=1 nf=2 169 | 170 | xm23 vop ibias vdd vdd pch_mac l=160e-9 w=1.4e-6 multi=1 nf=4 171 | 172 | xm14 vom ibias vdd vdd pch_mac l=160e-9 w=1.4e-6 multi=1 nf=4 173 | 174 | xc22 vop ntail2 vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 175 | 176 | xc21 ntail2 vom vss crtmom nv=16 nh=16 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 177 | xr11 vom ntail2 vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 178 | 179 | xr12 ntail2 vop vss rppolywo_m lr=6.6e-6 wr=400e-9 multi=1 m=1 180 | 181 | 182 | xm22 net100 ntail2 vss vss nch_mac l=160e-9 w=3.12e-6 multi=1 nf=4 183 | 184 | d1 vss vdd dnwpsub area=15.12e-12 pj=16.08e-6 m=1 185 | 186 | xm12 vss ntail2 vss vss nch_lvt_mac l=2.2e-6 w=2.1e-6 multi=1 nf=1 187 | 188 | xm11 vss ntail2 vss vss nch_lvt_mac l=2.2e-6 w=2.1e-6 multi=1 nf=1 189 | 190 | d0 net100 vdd pwdnw area=9.328e-12 pj=12.88e-6 m=1 191 | .ends Gm2_v5_Practice 192 | 193 | .subckt type:analog myComparator_v3 clk gnd outm outp vdd _net0 _net1 194 | 195 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 196 | 197 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 198 | 199 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 200 | 201 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 202 | 203 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 204 | 205 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 206 | 207 | xm7 net069 clk gnd gnd nch_lvt_mac l=40e-9 w=6.9e-6 multi=1 nf=15 208 | 209 | xm5 intern _net0 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 multi=1 nf=15 210 | 211 | xm6 interp _net1 net069 gnd nch_lvt_mac l=40e-9 w=14.4e-6 multi=1 nf=15 212 | 213 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 214 | 215 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 216 | 217 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 218 | 219 | xm2 interp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 220 | 221 | xm1 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 222 | 223 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 224 | 225 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 226 | 227 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 228 | .ends myComparator_v3 229 | 230 | .subckt type:mixed FIR_DAC_schematic clk in r1 r2 rstb vdd vss 231 | xr19 r1 net3 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 232 | 233 | xr48 r2 in vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 234 | 235 | 236 | xi86 in clk rstb net3 vdd vss DFCNQD2BWP 237 | .ends FIR_DAC_schematic 238 | 239 | .subckt type:analog C_DAC_schematic clkb in r3 r4 rstb vdd vss 240 | xr27 r3 net10 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=1 m=1 241 | 242 | xr64 r4 in vss rppolywo_m lr=18.67e-6 wr=1.2e-6 multi=1 m=1 243 | 244 | 245 | xi94 in clkb rstb net10 vdd vss DFCNQD2BWP 246 | .ends C_DAC_schematic 247 | 248 | .topckt CTDSM_CORE_NEW clk clkb1 clkb2 ibias1 ibias2 outm outp rstb vdda vddd vim vip vss 249 | 250 | xi160 ibias1 vdda vo1m vo1p vo2p vo2m vss Gm1_v5_Practice 251 | 252 | xi154 clkb1 net062 vo3m vo3p rstb vdda vss FIR_DAC 253 | 254 | xi152 clk net052 vo1p vo1p rstb vdda vss FIR_DAC 255 | 256 | m1 vss clkb2 vss vss nch l=280e-9 w=280e-9 m=1 nf=1 257 | 258 | m0 vss clkb1 vss vss nch l=280e-9 w=280e-9 m=1 nf=1 259 | 260 | xi164 vo1p vo1m vss C1 261 | 262 | xi128 outm outp net072 net071 vddd vss SR_Latch 263 | 264 | xc6 vo3p vo3m vss crtmom nv=184 nh=182 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 265 | 266 | xc3 net074 net073 vss crtmom nv=178 nh=178 w=70e-9 s=70e-9 stm=1 spm=6 multi=1 ftip=140e-9 dmflag=0 267 | xr16 vip vo1p vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=2 m=1 268 | 269 | xr51 net073 vo2m vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=5 m=1 270 | 271 | xr25 vo2p net074 vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=5 m=1 272 | 273 | xr47 vim vo1m vss rppolywo_m lr=19.92e-6 wr=1.2e-6 multi=2 m=1 274 | 275 | 276 | xi161 ibias2 vdda vo2m vo2p vo3p vo3m vss Gm1_v5_Practice 277 | 278 | xi88 net062 clk rstb net052 vdda vss DFCNQD2BWP 279 | 280 | xi97 outp clkb1 rstb net062 vdda vss DFCNQD2BWP 281 | 282 | xi92 net063 clk rstb net051 vdda vss DFCNQD2BWP 283 | 284 | xi99 outm clkb2 rstb net063 vdda vss DFCNQD2BWP 285 | 286 | xi146 clk vss net072 net071 vddd vo3p vo3m myComparator_v3 287 | 288 | xi153 clk net051 vo1m vo1m rstb vdda vss FIR_DAC 289 | 290 | xi155 clkb2 net063 vo3p vo3m rstb vdda vss FIR_DAC 291 | .ends CTDSM_CORE_NEW 292 | -------------------------------------------------------------------------------- /open/adc/adc1.sp: -------------------------------------------------------------------------------- 1 | 2 | .subckt INPUT_RES VINP VINN OTA1_INP OTA1_INN GND 3 | xr13 OTA1_INP VINP GND rppolywo_m lr=10e-6 wr=600e-9 4 | xr14 VINN OTA1_INN GND rppolywo_m lr=10e-6 wr=600e-9 5 | .ends INPUT_RES 6 | 7 | 8 | .subckt INVD4BWP_LVT i zn vdd vss 9 | x0 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 10 | x1 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 11 | x2 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 12 | x3 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 13 | x4 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 14 | x5 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 15 | x6 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 16 | x7 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 17 | .ends INVD4BWP_LVT 18 | 19 | .subckt DFCND4BWP_LVT_stupid d cp q qn vdd vss 20 | x0 net175 net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 21 | x1 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 22 | x2 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 23 | x3 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 24 | xmi43 net12 net145 vdd vdd pch_lvt_mac l=80e-9 w=240e-9 25 | x4 net95 net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 26 | xmi6 net9 d net1 vdd pch_lvt_mac l=80e-9 w=680e-9 27 | x5 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 28 | x6 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 29 | x7 net11 cp vdd vdd pch_lvt_mac l=80e-9 w=820e-9 30 | x8 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 31 | x9 net149 cdn vdd vdd pch_lvt_mac l=80e-9 w=820e-9 32 | xmi44 net12 cdn vdd vdd pch_lvt_mac l=80e-9 w=240e-9 33 | xmi17 net175 net95 net24 vdd pch_lvt_mac l=80e-9 w=240e-9 34 | x10 net149 net24 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 35 | x11 net145 net9 vdd vdd pch_lvt_mac l=80e-9 w=360e-9 36 | x12 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 37 | xmi16 net145 net11 net24 vdd pch_lvt_mac l=80e-9 w=360e-9 38 | x13 net149 net24 vdd vdd pch_lvt_mac l=80e-9 w=560e-9 39 | x14 net149 cdn vdd vdd pch_lvt_mac l=80e-9 w=560e-9 40 | xmi45 net9 net11 net12 vdd pch_lvt_mac l=80e-9 w=240e-9 41 | x15 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 42 | xmi7 net1 net95 vdd vdd pch_lvt_mac l=80e-9 w=680e-9 43 | x16 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 44 | x17 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 45 | x18 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 46 | x19 net169 cdn vss vss nch_lvt_mac l=80e-9 w=400e-9 47 | xmi4 net128 net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 48 | x20 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 49 | xmi18 net175 net11 net24 vss nch_lvt_mac l=80e-9 w=240e-9 50 | x21 net145 net9 vss vss nch_lvt_mac l=80e-9 w=300e-9 51 | x22 net149 net24 net169 vss nch_lvt_mac l=80e-9 w=400e-9 52 | xmi15 net145 net95 net24 vss nch_lvt_mac l=80e-9 w=300e-9 53 | x23 net175 net149 vss vss nch_lvt_mac l=80e-9 w=380e-9 54 | x24 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 55 | x25 net95 net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 56 | x26 net149 net24 net132 vss nch_lvt_mac l=80e-9 w=400e-9 57 | xmi5 net9 d net128 vss nch_lvt_mac l=80e-9 w=620e-9 58 | x27 net11 cp vss vss nch_lvt_mac l=80e-9 w=620e-9 59 | xmi49 net112 cdn vss vss nch_lvt_mac l=80e-9 w=240e-9 60 | x28 net132 cdn vss vss nch_lvt_mac l=80e-9 w=400e-9 61 | xmi48 net96 net145 net112 vss nch_lvt_mac l=80e-9 w=240e-9 62 | x29 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 63 | x30 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 64 | x31 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 65 | xmi47 net9 net95 net96 vss nch_lvt_mac l=80e-9 w=240e-9 66 | .ends DFCND4BWP_LVT_stupid 67 | 68 | .subckt OTA_XT_MAGICAL gnd ncas vcm vdd vim vip vom vop 69 | xm29 vs vcmon gnd gnd nch_hvt_mac l=120e-9 w=40.5e-6 70 | xm5 pcas vcm bias2 gnd nch_lvt_mac l=120e-9 w=4.8e-6 71 | xm30 tail1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=20e-6 72 | xm53 vcmop net0108 vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 73 | xm12 vcmon vcm vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 74 | xm50 vo1p ncas casn gnd nch_lvt_mac l=120e-9 w=9e-6 75 | xm49 vo1m ncas casp gnd nch_lvt_mac l=120e-9 w=9e-6 76 | xm51 ncas ncas nbias_tail gnd nch_lvt_mac l=120e-9 w=4e-6 77 | xm47 nbias_tail vcm bias1 gnd nch_lvt_mac l=120e-9 w=4.8e-6 78 | xm38 bias1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 79 | xm7 vop vim vs gnd nch_lvt_mac l=120e-9 w=36e-6 80 | xm43 casn vim tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 81 | xm10 vom vip vs gnd nch_lvt_mac l=120e-9 w=36e-6 82 | xm40 casp vip tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 83 | xm41 vs2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=14.4e-6 84 | xm31 bias2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 85 | xc0 vo1p net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 86 | xc1 vo1m net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 87 | xc4 vcmon vop cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 88 | xc7 net0108 vop cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 89 | xc3 vcmon vom cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 90 | xc6 net0108 vom cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 91 | xr10 net0108 vom gnd rppolywo_m lr=3.6e-6 wr=400e-9 92 | xr1 vop net0108 gnd rppolywo_m lr=3.6e-6 wr=400e-9 93 | xr8 vo1m net096 gnd rppolywo_m lr=7.86e-6 wr=400e-9 94 | xr2 net096 vo1p gnd rppolywo_m lr=7.86e-6 wr=400e-9 95 | xm57 vo1p pcas cas2n vdd pch_lvt_mac l=120e-9 w=18e-6 96 | xm64 vcmon vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 97 | xm67 vom vo1p vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 98 | xm66 vcmop vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 99 | xm8 cas2n net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 100 | xm61 cas2p net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 101 | xm56 vo1m pcas cas2p vdd pch_lvt_mac l=120e-9 w=18e-6 102 | xm9 vop vo1m vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 103 | xm58 pcas pcas net088 vdd pch_lvt_mac l=120e-9 w=6.4e-6 104 | xm63 net088 pcas vdd vdd pch_hvt_mac l=120e-9 w=1.07e-6 105 | .ends OTA_XT_MAGICAL 106 | 107 | .subckt OTA_XT_MAGICAL_2 gnd ncas vcm vdd vim vip vom vop 108 | xm29 vs vcmon gnd gnd nch_hvt_mac l=120e-9 w=40.5e-6 109 | xm5 pcas vcm bias2 gnd nch_lvt_mac l=120e-9 w=4.8e-6 110 | xm30 tail1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=20e-6 111 | xm53 vcmop net0108 vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 112 | xm12 vcmon vcm vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 113 | xm50 vo1p ncas casn gnd nch_lvt_mac l=120e-9 w=9e-6 114 | xm49 vo1m ncas casp gnd nch_lvt_mac l=120e-9 w=9e-6 115 | xm51 ncas ncas nbias_tail gnd nch_lvt_mac l=120e-9 w=4e-6 116 | xm47 nbias_tail vcm bias1 gnd nch_lvt_mac l=120e-9 w=4.8e-6 117 | xm38 bias1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 118 | xm7 vop vim vs gnd nch_lvt_mac l=120e-9 w=36e-6 119 | xm43 casn vim tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 120 | xm10 vom vip vs gnd nch_lvt_mac l=120e-9 w=36e-6 121 | xm40 casp vip tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 122 | xm41 vs2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=14.4e-6 123 | xm31 bias2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 124 | xc0 vo1p net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 125 | xc1 vo1m net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 126 | xc4 vcmon vop cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 127 | xc7 net0108 vop cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 128 | xc3 vcmon vom cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 129 | xc6 net0108 vom cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 130 | xr10 net0108 vom gnd rppolywo_m lr=3.6e-6 wr=400e-9 131 | xr1 vop net0108 gnd rppolywo_m lr=3.6e-6 wr=400e-9 132 | xr8 vo1m net096 gnd rppolywo_m lr=7.86e-6 wr=400e-9 133 | xr2 net096 vo1p gnd rppolywo_m lr=7.86e-6 wr=400e-9 134 | xm57 vo1p pcas cas2n vdd pch_lvt_mac l=120e-9 w=18e-6 135 | xm64 vcmon vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 136 | xm67 vom vo1p vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 137 | xm66 vcmop vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 138 | xm8 cas2n net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 139 | xm61 cas2p net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 140 | xm56 vo1m pcas cas2p vdd pch_lvt_mac l=120e-9 w=18e-6 141 | xm9 vop vo1m vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 142 | xm58 pcas pcas net088 vdd pch_lvt_mac l=120e-9 w=6.4e-6 143 | xm63 net088 pcas vdd vdd pch_hvt_mac l=120e-9 w=1.07e-6 144 | .ends OTA_XT_MAGICAL_2 145 | 146 | 147 | .subckt BUFFD4BWP_LVT i z vdd vss 148 | x0 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 149 | x1 net11 i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 150 | x2 net11 i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 151 | x3 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 152 | x4 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 153 | x5 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 154 | x6 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 155 | x7 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 156 | x8 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 157 | x9 net11 i vss vss nch_lvt_mac l=80e-9 w=620e-9 158 | x10 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 159 | x11 net11 i vss vss nch_lvt_mac l=80e-9 w=620e-9 160 | .ends BUFFD4BWP_LVT 161 | 162 | .subckt NR2D8BWP_LVT a1 a2 zn vdd vss 163 | x0 net13 a2 vdd vdd pch_lvt_mac l=80e-9 w=6.56e-6 164 | x1 zn a1 net13 vdd pch_lvt_mac l=80e-9 w=6.56e-6 165 | x2 zn a2 vss vss nch_lvt_mac l=80e-9 w=4.96e-6 166 | x3 zn a1 vss vss nch_lvt_mac l=80e-9 w=4.96e-6 167 | .ends NR2D8BWP_LVT 168 | 169 | .subckt SR_Latch_LVT q qb r s vdd vss 170 | xi1 r qb q vdd vss NR2D8BWP_LVT 171 | xi0 s q qb vdd vss NR2D8BWP_LVT 172 | .ends SR_Latch_LVT 173 | 174 | .subckt COMPARATOR_schematic clk gnd outm outp vdd _net0 _net1 175 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 176 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 177 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 178 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 179 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 180 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 181 | xm7 net069 clk gnd gnd nch_lvt_mac l=40e-9 w=3.68e-6 182 | xm5 intern _net0 net069 gnd nch_lvt_mac l=40e-9 w=7.68e-6 183 | xm6 interp _net1 net069 gnd nch_lvt_mac l=40e-9 w=7.68e-6 184 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 185 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 186 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 187 | xm2 interp clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 188 | xm1 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 189 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 190 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 191 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 192 | .ends COMPARATOR_schematic 193 | 194 | .subckt RR1 net040 net010 VREF GND net025 SYS_CLKB VDD net035 195 | xi24 net040 net010 VREF GND BUFFD4BWP_LVT 196 | xi25 net025 SYS_CLKB net040 net035 VDD GND DFCND4BWP_LVT_stupid 197 | .ends RR1 198 | 199 | .subckt RRR1 net046 SYS_CLKB VDD DO net038 GND net025 net028 net020 SYS_CLK 200 | xi12 net046 SYS_CLKB DO net038 VDD GND DFCND4BWP_LVT_stupid 201 | xi6 net046 net025 net028 net020 VDD GND SR_Latch_LVT 202 | xi4 SYS_CLK SYS_CLKB VDD GND INVD4BWP_LVT 203 | .ends RRR1 204 | 205 | .topckt adc1 DO GND IBIAS1 IBIAS2 SYS_CLK VCM VDD VINN VINP OTA1_INN OTA1_INP OTA2_INN OTA2_INP SUM_N SUM_P VINT1N VINT1P VINT2N VINT2P VREF 206 | input_res VINP VINN OTA1_INP OTA1_INN GND INPUT_RES 207 | xr47 OTA1_INN VINT2P GND rppolywo_m lr=34.8e-6 wr=400e-9 208 | xr28 OTA1_INP VINT2N GND rppolywo_m lr=34.8e-6 wr=400e-9 209 | xr21 net010 OTA1_INP GND rppolywo_m lr=10e-6 wr=600e-9 210 | xr20 net012 OTA1_INN GND rppolywo_m lr=10e-6 wr=600e-9 211 | xr23 net010 OTA2_INP GND rppolywo_m lr=10e-6 wr=600e-9 212 | xr25 net012 SUM_N GND rppolywo_m lr=10e-6 wr=600e-9 213 | xr24 net010 SUM_P GND rppolywo_m lr=10e-6 wr=600e-9 214 | xr22 net012 OTA2_INN GND rppolywo_m lr=10e-6 wr=600e-9 215 | xr19 VINT2N SUM_N GND rppolywo_m lr=10e-6 wr=600e-9 216 | xr16 VINT1N OTA2_INN GND rppolywo_m lr=10e-6 wr=600e-9 217 | xr17 VINT1P OTA2_INP GND rppolywo_m lr=10e-6 wr=600e-9 218 | xr18 VINT2P SUM_P GND rppolywo_m lr=10e-6 wr=600e-9 219 | xc4 OTA1_INP VINT1N cfmom_2t nr=96 lr=12.4e-6 w=70e-9 s=70e-9 stm=2 spm=5 220 | xc2 OTA2_INN VINT2P cfmom_2t nr=70 lr=9.85e-6 w=70e-9 s=70e-9 stm=2 spm=5 221 | xc0 OTA1_INN VINT1P cfmom_2t nr=96 lr=12.4e-6 w=70e-9 s=70e-9 stm=2 spm=5 222 | xc1 OTA2_INP VINT2N cfmom_2t nr=70 lr=9.85e-6 w=70e-9 s=70e-9 stm=2 spm=5 223 | xi22 GND IBIAS2 VCM VDD OTA2_INN OTA2_INP VINT2N VINT2P OTA_XT_MAGICAL 224 | xi20 GND IBIAS1 VCM VDD OTA1_INP OTA1_INN VINT1P VINT1N OTA_XT_MAGICAL 225 | xi19 SYS_CLK GND net028 net020 VDD SUM_P SUM_N COMPARATOR_schematic 226 | rr1 net040 net010 VREF GND net025 SYS_CLKB VDD net035 RR1 227 | rr2 net026 net012 VREF GND net046 SYS_CLKB VDD net022 RR1 228 | rrr1 net046 SYS_CLKB VDD DO net038 GND net025 net028 net020 SYS_CLK RRR1 229 | .ends adc1 230 | -------------------------------------------------------------------------------- /open/adc/adc4.sp: -------------------------------------------------------------------------------- 1 | .subckt type:digital INV0_LVT i zn vdd vss 2 | xm0 zn i vss vss nch_lvt_mac l=40e-9 w=155e-9 3 | xm1 zn i vdd vdd pch_lvt_mac l=40e-9 w=205e-9 4 | .ends INV0_LVT 5 | 6 | .subckt type:analog DAC_SWITCHES dac<9> dac<8> dac<7> dac<6> dac<5> dac<4> dac<3> dac<2> dac<1> gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp 7 | xi5 in<5> dac<5> vrefp vrefn INV0_LVT 8 | xi3 in<7> dac<7> vrefp vrefn INV0_LVT 9 | xi4 in<6> dac<6> vrefp vrefn INV0_LVT 10 | xi6 in<2> dac<2> vrefp vrefn INV0_LVT 11 | xi7 in<3> dac<3> vrefp vrefn INV0_LVT 12 | xi10 in<8> net07 vdd gnd INV0_LVT 13 | xi9 in<1> dac<1> vrefp vcm INV0_LVT 14 | xi8 in<4> dac<4> vrefp vrefn INV0_LVT 15 | xi0 in<9> net91 vdd gnd INV0_LVT 16 | xi1 net91 dac<9> vrefp vrefn INV0_LVT 17 | xi2 net07 dac<8> vrefp vrefn INV0_LVT 18 | .ends DAC_SWITCHES 19 | 20 | .subckt type:analog SAMPLE_NETWORK comp_in gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp 21 | xi2 dac<9> dac<8> dac<7> dac<6> dac<5> dac<4> dac<3> dac<2> dac<1> gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp DAC_SWITCHES 22 | .ends SAMPLE_NETWORK 23 | 24 | .subckt type:analog COMPARATOR clk crossn crossp gnd intern interp outm outp vdd _net1 _net0 25 | xm1 gnd interp gnd gnd nch_mac l=1e-6 w=2e-6 26 | xm0 gnd intern gnd gnd nch_mac l=1e-6 w=2e-6 27 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=240e-9 28 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=240e-9 29 | xm26 net050 clk gnd gnd nch_lvt_mac l=40e-9 w=480e-9 30 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=240e-9 31 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=240e-9 32 | xm25 interp _net0 net050 gnd nch_lvt_mac l=40e-9 w=1.92e-6 33 | xm24 intern _net1 net050 gnd nch_lvt_mac l=40e-9 w=1.92e-6 34 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=480e-9 35 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 36 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=480e-9 37 | xm19 interp clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 38 | xm10 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 39 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 40 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=480e-9 41 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=480e-9 42 | .ends COMPARATOR 43 | 44 | .subckt type:digital INVD0BWP i zn vdd vss 45 | m0 zn i vss vss nch l=40e-9 w=155e-9 46 | m1 zn i vdd vdd pch l=40e-9 w=205e-9 47 | .ends INVD0BWP 48 | 49 | .subckt type:analog LATCH clk gnd inm inp outm outp vcc 50 | xi1 net67 outp vcc gnd INVD0BWP 51 | xi0 net64 outm vcc gnd INVD0BWP 52 | xm10 net64 clk vcc vcc pch_mac l=40e-9 w=120e-9 53 | xm9 net67 clk vcc vcc pch_mac l=40e-9 w=120e-9 54 | xm13 net67 net64 vcc vcc pch_mac l=40e-9 w=240e-9 55 | xm4 net64 net67 vcc vcc pch_mac l=40e-9 w=240e-9 56 | xm8 net65 clk vcc vcc pch_mac l=40e-9 w=120e-9 57 | xm12 net012 clk vcc vcc pch_mac l=40e-9 w=120e-9 58 | xm11 net60 clk gnd gnd nch_mac l=40e-9 w=120e-9 59 | xm0 net65 inp net60 gnd nch_mac l=40e-9 w=120e-9 60 | xm2 net67 net64 net65 gnd nch_mac l=40e-9 w=120e-9 61 | xm3 net64 net67 net012 gnd nch_mac l=40e-9 w=120e-9 62 | xm1 net012 inm net60 gnd nch_mac l=40e-9 w=120e-9 63 | .ends LATCH 64 | 65 | .subckt type:mixed SAR_LOGIC_2ND_STAGE comp compb gnd q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> vdd q<0> qb<0> s<0> 66 | xi1<9> s<9> gnd compb comp net03<0> net04<0> vdd LATCH 67 | xi1<8> s<8> gnd compb comp net03<1> net04<1> vdd LATCH 68 | xi1<7> s<7> gnd compb comp net03<2> net04<2> vdd LATCH 69 | xi1<6> s<6> gnd compb comp net03<3> net04<3> vdd LATCH 70 | xi1<5> s<5> gnd compb comp net03<4> net04<4> vdd LATCH 71 | xi1<4> s<4> gnd compb comp net03<5> net04<5> vdd LATCH 72 | xi1<3> s<3> gnd compb comp net03<6> net04<6> vdd LATCH 73 | xi1<2> s<2> gnd compb comp net03<7> net04<7> vdd LATCH 74 | xi1<1> s<1> gnd compb comp net03<8> net04<8> vdd LATCH 75 | xi0 s<10> gnd compb comp qb<9> q<9> vdd LATCH 76 | xi2<9> net04<0> qb<8> vdd gnd INVD0BWP 77 | xi2<8> net04<1> qb<7> vdd gnd INVD0BWP 78 | xi2<7> net04<2> qb<6> vdd gnd INVD0BWP 79 | xi2<6> net04<3> qb<5> vdd gnd INVD0BWP 80 | xi2<5> net04<4> qb<4> vdd gnd INVD0BWP 81 | xi2<4> net04<5> qb<3> vdd gnd INVD0BWP 82 | xi2<3> net04<6> qb<2> vdd gnd INVD0BWP 83 | xi2<2> net04<7> qb<1> vdd gnd INVD0BWP 84 | xi2<1> net04<8> qb<0> vdd gnd INVD0BWP 85 | xi3<9> net03<0> q<8> vdd gnd INVD0BWP 86 | xi3<8> net03<1> q<7> vdd gnd INVD0BWP 87 | xi3<7> net03<2> q<6> vdd gnd INVD0BWP 88 | xi3<6> net03<3> q<5> vdd gnd INVD0BWP 89 | xi3<5> net03<4> q<4> vdd gnd INVD0BWP 90 | xi3<4> net03<5> q<3> vdd gnd INVD0BWP 91 | xi3<3> net03<6> q<2> vdd gnd INVD0BWP 92 | xi3<2> net03<7> q<1> vdd gnd INVD0BWP 93 | xi3<1> net03<8> q<0> vdd gnd INVD0BWP 94 | .ends SAR_LOGIC_2ND_STAGE 95 | 96 | .subckt type:digital DFSNQD1BWP d cp sdn q vdd vss 97 | m0 net44 net25 vss vss nch l=40e-9 w=310e-9 98 | m1 net11 cp vss vss nch l=40e-9 w=155e-9 99 | m2 q net13 vss vss nch l=40e-9 w=310e-9 100 | m3 net7 sdn net44 vss nch l=40e-9 w=310e-9 101 | m4 net37 net13 vss vss nch l=40e-9 w=120e-9 102 | m5 net33 sdn net37 vss nch l=40e-9 w=120e-9 103 | mi20 net7 net83 net63 vss nch l=40e-9 w=310e-9 104 | mi23 net25 net83 net5 vss nch l=40e-9 w=120e-9 105 | mi22 net33 net11 net63 vss nch l=40e-9 w=120e-9 106 | mi21 net25 d net20 vss nch l=40e-9 w=310e-9 107 | m6 net13 net63 vss vss nch l=40e-9 w=310e-9 108 | mi19 net20 net11 vss vss nch l=40e-9 w=310e-9 109 | mi24 net5 net7 vss vss nch l=40e-9 w=120e-9 110 | m7 net83 net11 vss vss nch l=40e-9 w=155e-9 111 | m8 net11 cp vdd vdd pch l=40e-9 w=205e-9 112 | mi33 net33 net83 net63 vdd pch l=40e-9 w=120e-9 113 | m9 net7 sdn vdd vdd pch l=40e-9 w=410e-9 114 | m10 q net13 vdd vdd pch l=40e-9 w=410e-9 115 | mi34 net25 net11 net96 vdd pch l=40e-9 w=120e-9 116 | mi30 net7 net11 net63 vdd pch l=40e-9 w=250e-9 117 | m11 net7 net25 vdd vdd pch l=40e-9 w=410e-9 118 | mi28 net81 net83 vdd vdd pch l=40e-9 w=340e-9 119 | m12 net83 net11 vdd vdd pch l=40e-9 w=205e-9 120 | m13 net33 net13 vdd vdd pch l=40e-9 w=120e-9 121 | mi35 net96 net7 vdd vdd pch l=40e-9 w=120e-9 122 | m14 net33 sdn vdd vdd pch l=40e-9 w=120e-9 123 | m15 net13 net63 vdd vdd pch l=40e-9 w=410e-9 124 | mi26 net25 d net81 vdd pch l=40e-9 w=340e-9 125 | .ends DFSNQD1BWP 126 | 127 | .subckt type:digital AN3D0BWP a1 a2 a3 z vdd vss 128 | m0 net13 a3 vss vss nch l=40e-9 w=155e-9 129 | m1 z net11 vss vss nch l=40e-9 w=155e-9 130 | m2 net5 a2 net13 vss nch l=40e-9 w=155e-9 131 | m3 net11 a1 net5 vss nch l=40e-9 w=155e-9 132 | m4 z net11 vdd vdd pch l=40e-9 w=205e-9 133 | m5 net11 a3 vdd vdd pch l=40e-9 w=205e-9 134 | m6 net11 a1 vdd vdd pch l=40e-9 w=205e-9 135 | m7 net11 a2 vdd vdd pch l=40e-9 w=205e-9 136 | .ends AN3D0BWP 137 | 138 | .subckt type:digital AN2D0BWP a1 a2 z vdd vss 139 | m0 z net5 vdd vdd pch l=40e-9 w=205e-9 140 | m1 net5 a1 vdd vdd pch l=40e-9 w=205e-9 141 | m2 net5 a2 vdd vdd pch l=40e-9 w=205e-9 142 | m3 z net5 vss vss nch l=40e-9 w=155e-9 143 | m4 net17 a2 vss vss nch l=40e-9 w=155e-9 144 | m5 net5 a1 net17 vss nch l=40e-9 w=155e-9 145 | .ends AN2D0BWP 146 | 147 | .subckt type:digital DFNCND1BWP d cpn cdn q qn vdd vss 148 | m0 net49 cdn vdd vdd pch l=40e-9 w=280e-9 149 | mi43 net53 net9 vdd vdd pch l=40e-9 w=120e-9 150 | m1 net49 net20 vdd vdd pch l=40e-9 w=280e-9 151 | mi6 net5 d net1 vdd pch l=40e-9 w=340e-9 152 | m2 net11 net67 vdd vdd pch l=40e-9 w=205e-9 153 | m3 net37 net49 vdd vdd pch l=40e-9 w=205e-9 154 | m4 qn net37 vdd vdd pch l=40e-9 w=410e-9 155 | m5 net67 cpn vdd vdd pch l=40e-9 w=205e-9 156 | m6 q net49 vdd vdd pch l=40e-9 w=410e-9 157 | mi44 net53 cdn vdd vdd pch l=40e-9 w=120e-9 158 | mi17 net37 net67 net20 vdd pch l=40e-9 w=120e-9 159 | m7 net9 net5 vdd vdd pch l=40e-9 w=180e-9 160 | mi16 net9 net11 net20 vdd pch l=40e-9 w=180e-9 161 | mi45 net5 net11 net53 vdd pch l=40e-9 w=120e-9 162 | mi7 net1 net67 vdd vdd pch l=40e-9 w=340e-9 163 | m8 qn net37 vss vss nch l=40e-9 w=310e-9 164 | m9 net37 net49 vss vss nch l=40e-9 w=155e-9 165 | mi4 net109 net11 vss vss nch l=40e-9 w=310e-9 166 | mi18 net37 net11 net20 vss nch l=40e-9 w=120e-9 167 | m10 net49 net20 net104 vss nch l=40e-9 w=280e-9 168 | m11 net104 cdn vss vss nch l=40e-9 w=280e-9 169 | m12 net9 net5 vss vss nch l=40e-9 w=150e-9 170 | mi15 net9 net67 net20 vss nch l=40e-9 w=150e-9 171 | mi5 net5 d net109 vss nch l=40e-9 w=310e-9 172 | m13 net67 cpn vss vss nch l=40e-9 w=155e-9 173 | mi49 net77 cdn vss vss nch l=40e-9 w=120e-9 174 | mi48 net64 net9 net77 vss nch l=40e-9 w=120e-9 175 | m14 q net49 vss vss nch l=40e-9 w=310e-9 176 | m15 net11 net67 vss vss nch l=40e-9 w=155e-9 177 | mi47 net5 net67 net64 vss nch l=40e-9 w=120e-9 178 | .ends DFNCND1BWP 179 | 180 | .subckt type:digital SAR_LOGIC_1ST_STAGE_CLKGATING clk clksb gnd s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> s<0> vdd sb<1> 181 | xi16<10> clkb s<10> sb<9> clkff<9> vdd gnd AN3D0BWP 182 | xi16<9> clkb s<9> sb<8> clkff<8> vdd gnd AN3D0BWP 183 | xi16<8> clkb s<8> sb<7> clkff<7> vdd gnd AN3D0BWP 184 | xi16<7> clkb s<7> sb<6> clkff<6> vdd gnd AN3D0BWP 185 | xi16<6> clkb s<6> sb<5> clkff<5> vdd gnd AN3D0BWP 186 | xi16<5> clkb s<5> sb<4> clkff<4> vdd gnd AN3D0BWP 187 | xi16<4> clkb s<4> sb<3> clkff<3> vdd gnd AN3D0BWP 188 | xi16<3> clkb s<3> sb<2> clkff<2> vdd gnd AN3D0BWP 189 | xi16<2> clkb s<2> sb<1> clkff<1> vdd gnd AN3D0BWP 190 | xi16<1> clkb s<1> sb<0> clkff<0> vdd gnd AN3D0BWP 191 | xi19 clk clkb vdd gnd INVD0BWP 192 | xi13 clkb sb<10> clkff<10> vdd gnd AN2D0BWP 193 | xi18<10> s<10> clkff<9> clksb s<9> sb<9> vdd gnd DFNCND1BWP 194 | xi18<9> s<9> clkff<8> clksb s<8> sb<8> vdd gnd DFNCND1BWP 195 | xi18<8> s<8> clkff<7> clksb s<7> sb<7> vdd gnd DFNCND1BWP 196 | xi18<7> s<7> clkff<6> clksb s<6> sb<6> vdd gnd DFNCND1BWP 197 | xi18<6> s<6> clkff<5> clksb s<5> sb<5> vdd gnd DFNCND1BWP 198 | xi18<5> s<5> clkff<4> clksb s<4> sb<4> vdd gnd DFNCND1BWP 199 | xi18<4> s<4> clkff<3> clksb s<3> sb<3> vdd gnd DFNCND1BWP 200 | xi18<3> s<3> clkff<2> clksb s<2> sb<2> vdd gnd DFNCND1BWP 201 | xi18<2> s<2> clkff<1> clksb s<1> sb<1> vdd gnd DFNCND1BWP 202 | xi18<1> s<1> clkff<0> clksb s<0> sb<0> vdd gnd DFNCND1BWP 203 | xi17 vdd clkff<10> clksb s<10> sb<10> vdd gnd DFNCND1BWP 204 | .ends SAR_LOGIC_1ST_STAGE_CLKGATING 205 | 206 | .subckt type:digital SAR_LOGIC clk clksb gnd outn outp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vdd q<0> qb<0> s<0> sb<1> 207 | xi1 outp outn gnd q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> vdd q<0> qb<0> s<0> SAR_LOGIC_2ND_STAGE 208 | xi0 clk clksb gnd s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> s<0> vdd sb<1> SAR_LOGIC_1ST_STAGE_CLKGATING 209 | .ends SAR_LOGIC 210 | 211 | .subckt type:analog SAMPLER clks_boost gnd vin vout 212 | xm0 vout clks_boost vin gnd nch_lvt_mac l=40e-9 w=240e-9 213 | .ends SAMPLER 214 | 215 | .subckt type:digital DFCND1BWP d cp cdn q qn vdd vss 216 | m0 qn net33 vss vss nch l=40e-9 w=310e-9 217 | mi4 net53 net5 vss vss nch l=40e-9 w=310e-9 218 | mi18 net33 net5 net79 vss nch l=40e-9 w=120e-9 219 | m1 net95 net79 net9 vss nch l=40e-9 w=280e-9 220 | m2 net81 net25 vss vss nch l=40e-9 w=150e-9 221 | mi15 net81 net67 net79 vss nch l=40e-9 w=150e-9 222 | m3 net33 net95 vss vss nch l=40e-9 w=155e-9 223 | m4 net67 net5 vss vss nch l=40e-9 w=155e-9 224 | mi5 net25 d net53 vss nch l=40e-9 w=310e-9 225 | mi49 net20 cdn vss vss nch l=40e-9 w=120e-9 226 | mi48 net17 net81 net20 vss nch l=40e-9 w=120e-9 227 | m5 q net95 vss vss nch l=40e-9 w=310e-9 228 | m6 net9 cdn vss vss nch l=40e-9 w=280e-9 229 | m7 net5 cp vss vss nch l=40e-9 w=155e-9 230 | mi47 net25 net67 net17 vss nch l=40e-9 w=120e-9 231 | m8 net33 net95 vdd vdd pch l=40e-9 w=205e-9 232 | m9 net5 cp vdd vdd pch l=40e-9 w=205e-9 233 | m10 net67 net5 vdd vdd pch l=40e-9 w=205e-9 234 | mi43 net72 net81 vdd vdd pch l=40e-9 w=120e-9 235 | mi6 net25 d net104 vdd pch l=40e-9 w=340e-9 236 | m11 qn net33 vdd vdd pch l=40e-9 w=410e-9 237 | m12 q net95 vdd vdd pch l=40e-9 w=410e-9 238 | mi44 net72 cdn vdd vdd pch l=40e-9 w=120e-9 239 | mi17 net33 net67 net79 vdd pch l=40e-9 w=120e-9 240 | m13 net81 net25 vdd vdd pch l=40e-9 w=180e-9 241 | m14 net95 net79 vdd vdd pch l=40e-9 w=280e-9 242 | mi16 net81 net5 net79 vdd pch l=40e-9 w=180e-9 243 | mi45 net25 net5 net72 vdd pch l=40e-9 w=120e-9 244 | mi7 net104 net67 vdd vdd pch l=40e-9 w=340e-9 245 | m15 net95 cdn vdd vdd pch l=40e-9 w=280e-9 246 | .ends DFCND1BWP 247 | 248 | .subckt type:digital NR2D0BWP a1 a2 zn vdd vss 249 | m0 zn a2 vss vss nch l=40e-9 w=155e-9 250 | m1 zn a1 vss vss nch l=40e-9 w=155e-9 251 | m2 net13 a2 vdd vdd pch l=40e-9 w=205e-9 252 | m3 zn a1 net13 vdd pch l=40e-9 w=205e-9 253 | .ends NR2D0BWP 254 | 255 | .subckt type:digital COUNTER clksb ctrl d<1> d<0> gnd in vdd 256 | xi1 net9 d<0> clksb d<1> net9 vdd gnd DFCND1BWP 257 | xi0 net6 net12 clksb d<0> net6 vdd gnd DFCND1BWP 258 | xi2 in ctrl net12 vdd gnd NR2D0BWP 259 | .ends COUNTER 260 | 261 | .topckt ADC_CORE clkc clks gnd inn inp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> q<0> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> qb<0> vdd bypass est_delay vcm vrefn vrefp 262 | xi1 cpinn gnd q<9> q<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vcm vdd vrefn vrefp SAMPLE_NETWORK 263 | xi0 cpinp gnd qb<9> qb<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> vcm vdd vrefn vrefp SAMPLE_NETWORK 264 | xi2 clkc net3 net4 gnd net1 net2 coutn coutp vdd cpinp cpinn COMPARATOR 265 | xi3 clkc clksb gnd coutn coutp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vdd q<0> qb<0> est_delay est SAR_LOGIC 266 | xi11 clks net05 inp cpinp SAMPLER 267 | xi12 clks net06 inn cpinn SAMPLER 268 | xi13 clksb est_delay estimator<1> estimator<0> gnd coutp vdd COUNTER 269 | .ends ADC_CORE 270 | -------------------------------------------------------------------------------- /ADC_CORE.sp: -------------------------------------------------------------------------------- 1 | .subckt type:digital INV0_LVT i zn vdd vss 2 | 3 | xm0 zn i vss vss nch_lvt_mac l=40e-9 w=155e-9 multi=1 nf=1 4 | xm1 zn i vdd vdd pch_lvt_mac l=40e-9 w=205e-9 multi=1 nf=1 5 | .ends INV0_LVT 6 | .subckt type:analog DAC_SWITCHES dac<9> dac<8> dac<7> dac<6> dac<5> dac<4> dac<3> dac<2> dac<1> gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp 7 | 8 | xi5 in<5> dac<5> vrefp vrefn INV0_LVT 9 | xi3 in<7> dac<7> vrefp vrefn INV0_LVT 10 | xi4 in<6> dac<6> vrefp vrefn INV0_LVT 11 | xi6 in<2> dac<2> vrefp vrefn INV0_LVT 12 | xi7 in<3> dac<3> vrefp vrefn INV0_LVT 13 | xi10 in<8> net07 vdd gnd INV0_LVT 14 | xi9 in<1> dac<1> vrefp vcm INV0_LVT 15 | xi8 in<4> dac<4> vrefp vrefn INV0_LVT 16 | xi0 in<9> net91 vdd gnd INV0_LVT 17 | xi1 net91 dac<9> vrefp vrefn INV0_LVT 18 | xi2 net07 dac<8> vrefp vrefn INV0_LVT 19 | .ends DAC_SWITCHES 20 | 21 | 22 | .subckt type:analog SAMPLE_NETWORK comp_in gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp 23 | xi2 dac<9> dac<8> dac<7> dac<6> dac<5> dac<4> dac<3> dac<2> dac<1> gnd in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> vcm vdd vrefn vrefp DAC_SWITCHES 24 | .ends SAMPLE_NETWORK 25 | 26 | 27 | 28 | 29 | .subckt type:analog COMPARATOR clk crossn crossp gnd intern interp outm outp vdd _net1 _net0 30 | 31 | xm1 gnd interp gnd gnd nch_mac l=1e-6 w=2e-6 multi=1 nf=1 32 | xm0 gnd intern gnd gnd nch_mac l=1e-6 w=2e-6 multi=1 nf=1 33 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 34 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 35 | 36 | xm26 net050 clk gnd gnd nch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 37 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 38 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=2 39 | xm25 interp _net0 net050 gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 40 | xm24 intern _net1 net050 gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=16 41 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 42 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 43 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 44 | xm19 interp clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 45 | xm10 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 46 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 47 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 48 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=480e-9 multi=1 nf=4 49 | .ends COMPARATOR 50 | 51 | 52 | 53 | .subckt type:digital INVD0BWP i zn vdd vss 54 | m0 zn i vss vss nch l=40e-9 w=155e-9 m=1 nf=1 55 | m1 zn i vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 56 | .ends INVD0BWP 57 | .subckt type:analog LATCH clk gnd inm inp outm outp vcc 58 | 59 | xi1 net67 outp vcc gnd INVD0BWP 60 | xi0 net64 outm vcc gnd INVD0BWP 61 | xm10 net64 clk vcc vcc pch_mac l=40e-9 w=120e-9 multi=1 nf=1 62 | xm9 net67 clk vcc vcc pch_mac l=40e-9 w=120e-9 multi=1 nf=1 63 | xm13 net67 net64 vcc vcc pch_mac l=40e-9 w=240e-9 multi=1 nf=2 64 | xm4 net64 net67 vcc vcc pch_mac l=40e-9 w=240e-9 multi=1 nf=2 65 | xm8 net65 clk vcc vcc pch_mac l=40e-9 w=120e-9 multi=1 nf=1 66 | 67 | xm12 net012 clk vcc vcc pch_mac l=40e-9 w=120e-9 multi=1 nf=1 68 | 69 | xm11 net60 clk gnd gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 70 | 71 | xm0 net65 inp net60 gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 72 | 73 | xm2 net67 net64 net65 gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 74 | 75 | xm3 net64 net67 net012 gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 76 | 77 | xm1 net012 inm net60 gnd nch_mac l=40e-9 w=120e-9 multi=1 nf=1 78 | .ends LATCH 79 | 80 | .subckt type:mixed SAR_LOGIC_2ND_STAGE comp compb gnd q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> vdd q<0> qb<0> s<0> 81 | 82 | xi1<9> s<9> gnd compb comp net03<0> net04<0> vdd LATCH 83 | 84 | xi1<8> s<8> gnd compb comp net03<1> net04<1> vdd LATCH 85 | 86 | xi1<7> s<7> gnd compb comp net03<2> net04<2> vdd LATCH 87 | 88 | xi1<6> s<6> gnd compb comp net03<3> net04<3> vdd LATCH 89 | 90 | xi1<5> s<5> gnd compb comp net03<4> net04<4> vdd LATCH 91 | 92 | xi1<4> s<4> gnd compb comp net03<5> net04<5> vdd LATCH 93 | 94 | xi1<3> s<3> gnd compb comp net03<6> net04<6> vdd LATCH 95 | 96 | xi1<2> s<2> gnd compb comp net03<7> net04<7> vdd LATCH 97 | 98 | xi1<1> s<1> gnd compb comp net03<8> net04<8> vdd LATCH 99 | 100 | xi0 s<10> gnd compb comp qb<9> q<9> vdd LATCH 101 | 102 | xi2<9> net04<0> qb<8> vdd gnd INVD0BWP 103 | 104 | xi2<8> net04<1> qb<7> vdd gnd INVD0BWP 105 | 106 | xi2<7> net04<2> qb<6> vdd gnd INVD0BWP 107 | 108 | xi2<6> net04<3> qb<5> vdd gnd INVD0BWP 109 | 110 | xi2<5> net04<4> qb<4> vdd gnd INVD0BWP 111 | 112 | xi2<4> net04<5> qb<3> vdd gnd INVD0BWP 113 | 114 | xi2<3> net04<6> qb<2> vdd gnd INVD0BWP 115 | 116 | xi2<2> net04<7> qb<1> vdd gnd INVD0BWP 117 | 118 | xi2<1> net04<8> qb<0> vdd gnd INVD0BWP 119 | 120 | xi3<9> net03<0> q<8> vdd gnd INVD0BWP 121 | 122 | xi3<8> net03<1> q<7> vdd gnd INVD0BWP 123 | 124 | xi3<7> net03<2> q<6> vdd gnd INVD0BWP 125 | 126 | xi3<6> net03<3> q<5> vdd gnd INVD0BWP 127 | 128 | xi3<5> net03<4> q<4> vdd gnd INVD0BWP 129 | 130 | xi3<4> net03<5> q<3> vdd gnd INVD0BWP 131 | 132 | xi3<3> net03<6> q<2> vdd gnd INVD0BWP 133 | 134 | xi3<2> net03<7> q<1> vdd gnd INVD0BWP 135 | 136 | xi3<1> net03<8> q<0> vdd gnd INVD0BWP 137 | .ends SAR_LOGIC_2ND_STAGE 138 | 139 | .subckt type:digital DFSNQD1BWP d cp sdn q vdd vss 140 | 141 | m0 net44 net25 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 142 | 143 | m1 net11 cp vss vss nch l=40e-9 w=155e-9 m=1 nf=1 144 | 145 | m2 q net13 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 146 | 147 | m3 net7 sdn net44 vss nch l=40e-9 w=310e-9 m=1 nf=1 148 | 149 | m4 net37 net13 vss vss nch l=40e-9 w=120e-9 m=1 nf=1 150 | 151 | m5 net33 sdn net37 vss nch l=40e-9 w=120e-9 m=1 nf=1 152 | 153 | mi20 net7 net83 net63 vss nch l=40e-9 w=310e-9 m=1 nf=1 154 | 155 | mi23 net25 net83 net5 vss nch l=40e-9 w=120e-9 m=1 nf=1 156 | 157 | mi22 net33 net11 net63 vss nch l=40e-9 w=120e-9 m=1 nf=1 158 | 159 | mi21 net25 d net20 vss nch l=40e-9 w=310e-9 m=1 nf=1 160 | 161 | m6 net13 net63 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 162 | 163 | mi19 net20 net11 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 164 | 165 | mi24 net5 net7 vss vss nch l=40e-9 w=120e-9 m=1 nf=1 166 | 167 | m7 net83 net11 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 168 | 169 | m8 net11 cp vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 170 | 171 | mi33 net33 net83 net63 vdd pch l=40e-9 w=120e-9 m=1 nf=1 172 | 173 | m9 net7 sdn vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 174 | 175 | m10 q net13 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 176 | 177 | mi34 net25 net11 net96 vdd pch l=40e-9 w=120e-9 m=1 nf=1 178 | 179 | mi30 net7 net11 net63 vdd pch l=40e-9 w=250e-9 m=1 nf=1 180 | 181 | m11 net7 net25 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 182 | 183 | mi28 net81 net83 vdd vdd pch l=40e-9 w=340e-9 m=1 nf=1 184 | 185 | m12 net83 net11 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 186 | 187 | m13 net33 net13 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 188 | 189 | mi35 net96 net7 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 190 | 191 | m14 net33 sdn vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 192 | 193 | m15 net13 net63 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 194 | 195 | mi26 net25 d net81 vdd pch l=40e-9 w=340e-9 m=1 nf=1 196 | .ends DFSNQD1BWP 197 | 198 | .subckt type:digital AN3D0BWP a1 a2 a3 z vdd vss 199 | 200 | m0 net13 a3 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 201 | 202 | m1 z net11 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 203 | 204 | m2 net5 a2 net13 vss nch l=40e-9 w=155e-9 m=1 nf=1 205 | 206 | m3 net11 a1 net5 vss nch l=40e-9 w=155e-9 m=1 nf=1 207 | 208 | m4 z net11 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 209 | 210 | m5 net11 a3 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 211 | 212 | m6 net11 a1 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 213 | 214 | m7 net11 a2 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 215 | .ends AN3D0BWP 216 | 217 | .subckt type:digital AN2D0BWP a1 a2 z vdd vss 218 | 219 | m0 z net5 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 220 | 221 | m1 net5 a1 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 222 | 223 | m2 net5 a2 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 224 | 225 | m3 z net5 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 226 | 227 | m4 net17 a2 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 228 | 229 | m5 net5 a1 net17 vss nch l=40e-9 w=155e-9 m=1 nf=1 230 | .ends AN2D0BWP 231 | 232 | .subckt type:digital DFNCND1BWP d cpn cdn q qn vdd vss 233 | 234 | m0 net49 cdn vdd vdd pch l=40e-9 w=280e-9 m=1 nf=1 235 | 236 | mi43 net53 net9 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 237 | 238 | m1 net49 net20 vdd vdd pch l=40e-9 w=280e-9 m=1 nf=1 239 | 240 | mi6 net5 d net1 vdd pch l=40e-9 w=340e-9 m=1 nf=1 241 | 242 | m2 net11 net67 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 243 | 244 | m3 net37 net49 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 245 | 246 | m4 qn net37 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 247 | 248 | m5 net67 cpn vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 249 | 250 | m6 q net49 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 251 | 252 | mi44 net53 cdn vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 253 | 254 | mi17 net37 net67 net20 vdd pch l=40e-9 w=120e-9 m=1 nf=1 255 | 256 | m7 net9 net5 vdd vdd pch l=40e-9 w=180e-9 m=1 nf=1 257 | 258 | mi16 net9 net11 net20 vdd pch l=40e-9 w=180e-9 m=1 nf=1 259 | 260 | mi45 net5 net11 net53 vdd pch l=40e-9 w=120e-9 m=1 nf=1 261 | 262 | mi7 net1 net67 vdd vdd pch l=40e-9 w=340e-9 m=1 nf=1 263 | 264 | m8 qn net37 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 265 | 266 | m9 net37 net49 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 267 | 268 | mi4 net109 net11 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 269 | 270 | mi18 net37 net11 net20 vss nch l=40e-9 w=120e-9 m=1 nf=1 271 | 272 | m10 net49 net20 net104 vss nch l=40e-9 w=280e-9 m=1 nf=1 273 | 274 | m11 net104 cdn vss vss nch l=40e-9 w=280e-9 m=1 nf=1 275 | 276 | m12 net9 net5 vss vss nch l=40e-9 w=150e-9 m=1 nf=1 277 | 278 | mi15 net9 net67 net20 vss nch l=40e-9 w=150e-9 m=1 nf=1 279 | 280 | mi5 net5 d net109 vss nch l=40e-9 w=310e-9 m=1 nf=1 281 | 282 | m13 net67 cpn vss vss nch l=40e-9 w=155e-9 m=1 nf=1 283 | 284 | mi49 net77 cdn vss vss nch l=40e-9 w=120e-9 m=1 nf=1 285 | 286 | mi48 net64 net9 net77 vss nch l=40e-9 w=120e-9 m=1 nf=1 287 | 288 | m14 q net49 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 289 | 290 | m15 net11 net67 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 291 | 292 | mi47 net5 net67 net64 vss nch l=40e-9 w=120e-9 m=1 nf=1 293 | .ends DFNCND1BWP 294 | 295 | .subckt type:digital SAR_LOGIC_1ST_STAGE_CLKGATING clk clksb gnd s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> s<0> vdd sb<1> 296 | 297 | 298 | xi16<10> clkb s<10> sb<9> clkff<9> vdd gnd AN3D0BWP 299 | 300 | xi16<9> clkb s<9> sb<8> clkff<8> vdd gnd AN3D0BWP 301 | 302 | xi16<8> clkb s<8> sb<7> clkff<7> vdd gnd AN3D0BWP 303 | 304 | xi16<7> clkb s<7> sb<6> clkff<6> vdd gnd AN3D0BWP 305 | 306 | xi16<6> clkb s<6> sb<5> clkff<5> vdd gnd AN3D0BWP 307 | 308 | xi16<5> clkb s<5> sb<4> clkff<4> vdd gnd AN3D0BWP 309 | 310 | xi16<4> clkb s<4> sb<3> clkff<3> vdd gnd AN3D0BWP 311 | 312 | xi16<3> clkb s<3> sb<2> clkff<2> vdd gnd AN3D0BWP 313 | 314 | xi16<2> clkb s<2> sb<1> clkff<1> vdd gnd AN3D0BWP 315 | 316 | xi16<1> clkb s<1> sb<0> clkff<0> vdd gnd AN3D0BWP 317 | 318 | xi19 clk clkb vdd gnd INVD0BWP 319 | 320 | xi13 clkb sb<10> clkff<10> vdd gnd AN2D0BWP 321 | 322 | xi18<10> s<10> clkff<9> clksb s<9> sb<9> vdd gnd DFNCND1BWP 323 | 324 | xi18<9> s<9> clkff<8> clksb s<8> sb<8> vdd gnd DFNCND1BWP 325 | 326 | xi18<8> s<8> clkff<7> clksb s<7> sb<7> vdd gnd DFNCND1BWP 327 | 328 | xi18<7> s<7> clkff<6> clksb s<6> sb<6> vdd gnd DFNCND1BWP 329 | 330 | xi18<6> s<6> clkff<5> clksb s<5> sb<5> vdd gnd DFNCND1BWP 331 | 332 | xi18<5> s<5> clkff<4> clksb s<4> sb<4> vdd gnd DFNCND1BWP 333 | 334 | xi18<4> s<4> clkff<3> clksb s<3> sb<3> vdd gnd DFNCND1BWP 335 | 336 | xi18<3> s<3> clkff<2> clksb s<2> sb<2> vdd gnd DFNCND1BWP 337 | 338 | xi18<2> s<2> clkff<1> clksb s<1> sb<1> vdd gnd DFNCND1BWP 339 | 340 | xi18<1> s<1> clkff<0> clksb s<0> sb<0> vdd gnd DFNCND1BWP 341 | 342 | xi17 vdd clkff<10> clksb s<10> sb<10> vdd gnd DFNCND1BWP 343 | .ends SAR_LOGIC_1ST_STAGE_CLKGATING 344 | 345 | .subckt type:digital SAR_LOGIC clk clksb gnd outn outp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vdd q<0> qb<0> s<0> sb<1> 346 | 347 | xi1 outp outn gnd q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> vdd q<0> qb<0> s<0> SAR_LOGIC_2ND_STAGE 348 | 349 | xi0 clk clksb gnd s<10> s<9> s<8> s<7> s<6> s<5> s<4> s<3> s<2> s<1> s<0> vdd sb<1> SAR_LOGIC_1ST_STAGE_CLKGATING 350 | .ends SAR_LOGIC 351 | 352 | .subckt type:analog SAMPLER clks_boost gnd vin vout 353 | 354 | xm0 vout clks_boost vin gnd nch_lvt_mac l=40e-9 w=240e-9 multi=1 nf=1 355 | .ends SAMPLER 356 | 357 | .subckt type:digital DFCND1BWP d cp cdn q qn vdd vss 358 | 359 | m0 qn net33 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 360 | 361 | mi4 net53 net5 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 362 | 363 | mi18 net33 net5 net79 vss nch l=40e-9 w=120e-9 m=1 nf=1 364 | 365 | m1 net95 net79 net9 vss nch l=40e-9 w=280e-9 m=1 nf=1 366 | 367 | m2 net81 net25 vss vss nch l=40e-9 w=150e-9 m=1 nf=1 368 | 369 | mi15 net81 net67 net79 vss nch l=40e-9 w=150e-9 m=1 nf=1 370 | 371 | m3 net33 net95 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 372 | 373 | m4 net67 net5 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 374 | 375 | mi5 net25 d net53 vss nch l=40e-9 w=310e-9 m=1 nf=1 376 | 377 | mi49 net20 cdn vss vss nch l=40e-9 w=120e-9 m=1 nf=1 378 | 379 | mi48 net17 net81 net20 vss nch l=40e-9 w=120e-9 m=1 nf=1 380 | 381 | m5 q net95 vss vss nch l=40e-9 w=310e-9 m=1 nf=1 382 | 383 | m6 net9 cdn vss vss nch l=40e-9 w=280e-9 m=1 nf=1 384 | 385 | m7 net5 cp vss vss nch l=40e-9 w=155e-9 m=1 nf=1 386 | 387 | mi47 net25 net67 net17 vss nch l=40e-9 w=120e-9 m=1 nf=1 388 | 389 | m8 net33 net95 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 390 | 391 | m9 net5 cp vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 392 | 393 | m10 net67 net5 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 394 | 395 | mi43 net72 net81 vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 396 | 397 | mi6 net25 d net104 vdd pch l=40e-9 w=340e-9 m=1 nf=1 398 | 399 | m11 qn net33 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 400 | 401 | m12 q net95 vdd vdd pch l=40e-9 w=410e-9 m=1 nf=1 402 | 403 | mi44 net72 cdn vdd vdd pch l=40e-9 w=120e-9 m=1 nf=1 404 | 405 | mi17 net33 net67 net79 vdd pch l=40e-9 w=120e-9 m=1 nf=1 406 | 407 | m13 net81 net25 vdd vdd pch l=40e-9 w=180e-9 m=1 nf=1 408 | 409 | m14 net95 net79 vdd vdd pch l=40e-9 w=280e-9 m=1 nf=1 410 | 411 | mi16 net81 net5 net79 vdd pch l=40e-9 w=180e-9 m=1 nf=1 412 | 413 | mi45 net25 net5 net72 vdd pch l=40e-9 w=120e-9 m=1 nf=1 414 | 415 | mi7 net104 net67 vdd vdd pch l=40e-9 w=340e-9 m=1 nf=1 416 | 417 | m15 net95 cdn vdd vdd pch l=40e-9 w=280e-9 m=1 nf=1 418 | .ends DFCND1BWP 419 | 420 | .subckt type:digital NR2D0BWP a1 a2 zn vdd vss 421 | 422 | m0 zn a2 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 423 | 424 | m1 zn a1 vss vss nch l=40e-9 w=155e-9 m=1 nf=1 425 | 426 | m2 net13 a2 vdd vdd pch l=40e-9 w=205e-9 m=1 nf=1 427 | 428 | m3 zn a1 net13 vdd pch l=40e-9 w=205e-9 m=1 nf=1 429 | .ends NR2D0BWP 430 | 431 | .subckt type:digital COUNTER clksb ctrl d<1> d<0> gnd in vdd 432 | 433 | xi1 net9 d<0> clksb d<1> net9 vdd gnd DFCND1BWP 434 | 435 | xi0 net6 net12 clksb d<0> net6 vdd gnd DFCND1BWP 436 | 437 | xi2 in ctrl net12 vdd gnd NR2D0BWP 438 | .ends COUNTER 439 | 440 | .topckt ADC_CORE clkc clks gnd inn inp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> q<0> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> qb<0> vdd bypass est_delay vcm vrefn vrefp 441 | 442 | xi1 cpinn gnd q<9> q<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vcm vdd vrefn vrefp SAMPLE_NETWORK 443 | 444 | xi0 cpinp gnd qb<9> qb<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> vcm vdd vrefn vrefp SAMPLE_NETWORK 445 | 446 | xi2 clkc net3 net4 gnd net1 net2 coutn coutp vdd cpinp cpinn COMPARATOR 447 | 448 | xi3 clkc clksb gnd coutn coutp q<9> q<8> q<7> q<6> q<5> q<4> q<3> q<2> q<1> qb<9> qb<8> qb<7> qb<6> qb<5> qb<4> qb<3> qb<2> qb<1> vdd q<0> qb<0> est_delay est SAR_LOGIC 449 | 450 | 451 | xi11 clks net05 inp cpinp SAMPLER 452 | 453 | xi12 clks net06 inn cpinn SAMPLER 454 | 455 | xi13 clksb est_delay estimator<1> estimator<0> gnd coutp vdd COUNTER 456 | .ends ADC_CORE 457 | -------------------------------------------------------------------------------- /adc1.sp: -------------------------------------------------------------------------------- 1 | 2 | .subckt INPUT_RES VINP VINN OTA1_INP OTA1_INN GND 3 | xr13 OTA1_INP VINP GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 4 | xr14 VINN OTA1_INN GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 5 | .ends INPUT_RES 6 | 7 | 8 | 9 | .subckt INVD4BWP_LVT i zn vdd vss 10 | 11 | x0 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 12 | 13 | x1 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 14 | 15 | x2 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 16 | 17 | x3 zn i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 18 | 19 | x4 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 20 | 21 | x5 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 22 | 23 | x6 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 24 | 25 | x7 zn i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 26 | .ends INVD4BWP_LVT 27 | 28 | .subckt DFCND4BWP_LVT_stupid d cp q qn vdd vss 29 | 30 | x0 net175 net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 31 | 32 | x1 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 33 | 34 | x2 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 35 | 36 | x3 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 37 | 38 | xmi43 net12 net145 vdd vdd pch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 39 | 40 | x4 net95 net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 41 | 42 | xmi6 net9 d net1 vdd pch_lvt_mac l=80e-9 w=680e-9 multi=1 nf=1 43 | 44 | x5 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 45 | 46 | x6 qn net175 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 47 | 48 | x7 net11 cp vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 49 | 50 | x8 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 51 | 52 | x9 net149 cdn vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 53 | 54 | xmi44 net12 cdn vdd vdd pch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 55 | 56 | xmi17 net175 net95 net24 vdd pch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 57 | 58 | x10 net149 net24 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 59 | 60 | x11 net145 net9 vdd vdd pch_lvt_mac l=80e-9 w=360e-9 multi=1 nf=1 61 | 62 | x12 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 63 | 64 | xmi16 net145 net11 net24 vdd pch_lvt_mac l=80e-9 w=360e-9 multi=1 nf=1 65 | 66 | x13 net149 net24 vdd vdd pch_lvt_mac l=80e-9 w=560e-9 multi=1 nf=1 67 | 68 | x14 net149 cdn vdd vdd pch_lvt_mac l=80e-9 w=560e-9 multi=1 nf=1 69 | 70 | xmi45 net9 net11 net12 vdd pch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 71 | 72 | x15 q net149 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 73 | 74 | xmi7 net1 net95 vdd vdd pch_lvt_mac l=80e-9 w=680e-9 multi=1 nf=1 75 | 76 | x16 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 77 | 78 | x17 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 79 | 80 | x18 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 81 | 82 | x19 net169 cdn vss vss nch_lvt_mac l=80e-9 w=400e-9 multi=1 nf=1 83 | 84 | xmi4 net128 net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 85 | 86 | x20 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 87 | 88 | xmi18 net175 net11 net24 vss nch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 89 | 90 | x21 net145 net9 vss vss nch_lvt_mac l=80e-9 w=300e-9 multi=1 nf=1 91 | 92 | x22 net149 net24 net169 vss nch_lvt_mac l=80e-9 w=400e-9 multi=1 nf=1 93 | 94 | xmi15 net145 net95 net24 vss nch_lvt_mac l=80e-9 w=300e-9 multi=1 nf=1 95 | 96 | x23 net175 net149 vss vss nch_lvt_mac l=80e-9 w=380e-9 multi=1 nf=1 97 | 98 | x24 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 99 | 100 | x25 net95 net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 101 | 102 | x26 net149 net24 net132 vss nch_lvt_mac l=80e-9 w=400e-9 multi=1 nf=1 103 | 104 | xmi5 net9 d net128 vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 105 | 106 | x27 net11 cp vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 107 | 108 | xmi49 net112 cdn vss vss nch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 109 | 110 | x28 net132 cdn vss vss nch_lvt_mac l=80e-9 w=400e-9 multi=1 nf=1 111 | 112 | xmi48 net96 net145 net112 vss nch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 113 | 114 | x29 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 115 | 116 | x30 qn net175 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 117 | 118 | x31 q net149 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 119 | 120 | xmi47 net9 net95 net96 vss nch_lvt_mac l=80e-9 w=240e-9 multi=1 nf=1 121 | .ends DFCND4BWP_LVT_stupid 122 | 123 | .subckt OTA_XT_MAGICAL gnd ncas vcm vdd vim vip vom vop 124 | 125 | xm29 vs vcmon gnd gnd nch_hvt_mac l=120e-9 w=40.5e-6 multi=1 nf=15 126 | 127 | xm5 pcas vcm bias2 gnd nch_lvt_mac l=120e-9 w=4.8e-6 multi=1 nf=5 128 | 129 | xm30 tail1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=20e-6 multi=1 nf=25 130 | 131 | xm53 vcmop net0108 vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 multi=1 nf=8 132 | 133 | xm12 vcmon vcm vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 multi=1 nf=8 134 | 135 | xm50 vo1p ncas casn gnd nch_lvt_mac l=120e-9 w=9e-6 multi=1 nf=10 136 | 137 | xm49 vo1m ncas casp gnd nch_lvt_mac l=120e-9 w=9e-6 multi=1 nf=10 138 | 139 | xm51 ncas ncas nbias_tail gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 140 | 141 | xm47 nbias_tail vcm bias1 gnd nch_lvt_mac l=120e-9 w=4.8e-6 multi=1 nf=5 142 | 143 | xm38 bias1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 144 | 145 | xm7 vop vim vs gnd nch_lvt_mac l=120e-9 w=36e-6 multi=1 nf=15 146 | 147 | xm43 casn vim tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 multi=1 nf=5 148 | 149 | xm10 vom vip vs gnd nch_lvt_mac l=120e-9 w=36e-6 multi=1 nf=15 150 | 151 | xm40 casp vip tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 multi=1 nf=5 152 | 153 | xm41 vs2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=14.4e-6 multi=1 nf=10 154 | 155 | xm31 bias2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 156 | 157 | xc0 vo1p net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 158 | 159 | xc1 vo1m net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 160 | 161 | xc4 vcmon vop cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 162 | 163 | xc7 net0108 vop cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 multi=1 ftip=140e-9 164 | 165 | xc3 vcmon vom cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 166 | 167 | xc6 net0108 vom cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 multi=1 ftip=140e-9 168 | xr10 net0108 vom gnd rppolywo_m lr=3.6e-6 wr=400e-9 multi=1 m=1 series=6 segspace=250e-9 169 | 170 | xr1 vop net0108 gnd rppolywo_m lr=3.6e-6 wr=400e-9 multi=1 m=1 series=6 segspace=250e-9 171 | 172 | xr8 vo1m net096 gnd rppolywo_m lr=7.86e-6 wr=400e-9 multi=1 m=1 series=10 segspace=250e-9 173 | 174 | xr2 net096 vo1p gnd rppolywo_m lr=7.86e-6 wr=400e-9 multi=1 m=1 series=10 segspace=250e-9 175 | 176 | 177 | xm57 vo1p pcas cas2n vdd pch_lvt_mac l=120e-9 w=18e-6 multi=1 nf=10 178 | 179 | xm64 vcmon vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 multi=1 nf=10 180 | 181 | xm67 vom vo1p vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 multi=1 nf=20 182 | 183 | xm66 vcmop vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 multi=1 nf=10 184 | 185 | xm8 cas2n net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 multi=1 nf=10 186 | 187 | xm61 cas2p net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 multi=1 nf=10 188 | 189 | xm56 vo1m pcas cas2p vdd pch_lvt_mac l=120e-9 w=18e-6 multi=1 nf=10 190 | 191 | xm9 vop vo1m vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 multi=1 nf=20 192 | 193 | xm58 pcas pcas net088 vdd pch_lvt_mac l=120e-9 w=6.4e-6 multi=1 nf=4 194 | 195 | xm63 net088 pcas vdd vdd pch_hvt_mac l=120e-9 w=1.07e-6 multi=1 nf=1 196 | .ends OTA_XT_MAGICAL 197 | 198 | .subckt OTA_XT_MAGICAL_2 gnd ncas vcm vdd vim vip vom vop 199 | 200 | xm29 vs vcmon gnd gnd nch_hvt_mac l=120e-9 w=40.5e-6 multi=1 nf=20 201 | 202 | xm5 pcas vcm bias2 gnd nch_lvt_mac l=120e-9 w=4.8e-6 multi=1 nf=5 203 | 204 | xm30 tail1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=20e-6 multi=1 nf=25 205 | 206 | xm53 vcmop net0108 vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 multi=1 nf=8 207 | 208 | xm12 vcmon vcm vs2 gnd nch_lvt_mac l=120e-9 w=7.2e-6 multi=1 nf=8 209 | 210 | xm50 vo1p ncas casn gnd nch_lvt_mac l=120e-9 w=9e-6 multi=1 nf=10 211 | 212 | xm49 vo1m ncas casp gnd nch_lvt_mac l=120e-9 w=9e-6 multi=1 nf=10 213 | 214 | xm51 ncas ncas nbias_tail gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 215 | 216 | xm47 nbias_tail vcm bias1 gnd nch_lvt_mac l=120e-9 w=4.8e-6 multi=1 nf=5 217 | 218 | xm38 bias1 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 219 | 220 | xm7 vop vim vs gnd nch_lvt_mac l=120e-9 w=36e-6 multi=1 nf=15 221 | 222 | xm43 casn vim tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 multi=1 nf=5 223 | 224 | xm10 vom vip vs gnd nch_lvt_mac l=120e-9 w=36e-6 multi=1 nf=15 225 | 226 | xm40 casp vip tail1 gnd nch_lvt_mac l=120e-9 w=13.5e-6 multi=1 nf=5 227 | 228 | xm41 vs2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=14.4e-6 multi=1 nf=10 229 | 230 | xm31 bias2 nbias_tail gnd gnd nch_lvt_mac l=120e-9 w=4e-6 multi=1 nf=5 231 | 232 | xc0 vo1p net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 233 | 234 | xc1 vo1m net096 cfmom_2t nr=26 lr=1.9e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 235 | 236 | xc4 vcmon vop cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 237 | 238 | xc7 net0108 vop cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 multi=1 ftip=140e-9 239 | 240 | xc3 vcmon vom cfmom_2t nr=36 lr=4.17e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 241 | 242 | xc6 net0108 vom cfmom_2t nr=18 lr=1.91e-6 w=70e-9 s=70e-9 stm=2 spm=4 multi=1 ftip=140e-9 243 | xr10 net0108 vom gnd rppolywo_m lr=3.6e-6 wr=400e-9 multi=1 m=1 series=6 segspace=250e-9 244 | 245 | xr1 vop net0108 gnd rppolywo_m lr=3.6e-6 wr=400e-9 multi=1 m=1 series=6 segspace=250e-9 246 | 247 | xr8 vo1m net096 gnd rppolywo_m lr=7.86e-6 wr=400e-9 multi=1 m=1 series=10 segspace=250e-9 248 | 249 | xr2 net096 vo1p gnd rppolywo_m lr=7.86e-6 wr=400e-9 multi=1 m=1 series=10 segspace=250e-9 250 | 251 | 252 | xm57 vo1p pcas cas2n vdd pch_lvt_mac l=120e-9 w=18e-6 multi=1 nf=10 253 | 254 | xm64 vcmon vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 multi=1 nf=10 255 | 256 | xm67 vom vo1p vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 multi=1 nf=20 257 | 258 | xm66 vcmop vcmop vdd vdd pch_lvt_mac l=120e-9 w=9.6e-6 multi=1 nf=10 259 | 260 | xm8 cas2n net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 multi=1 nf=10 261 | 262 | xm61 cas2p net096 vdd vdd pch_lvt_mac l=120e-9 w=12e-6 multi=1 nf=10 263 | 264 | xm56 vo1m pcas cas2p vdd pch_lvt_mac l=120e-9 w=18e-6 multi=1 nf=10 265 | 266 | xm9 vop vo1m vdd vdd pch_lvt_mac l=120e-9 w=28.8e-6 multi=1 nf=20 267 | 268 | xm58 pcas pcas net088 vdd pch_lvt_mac l=120e-9 w=6.4e-6 multi=1 nf=4 269 | 270 | xm63 net088 pcas vdd vdd pch_hvt_mac l=120e-9 w=1.07e-6 multi=1 nf=1 271 | .ends OTA_XT_MAGICAL_2 272 | 273 | 274 | 275 | .subckt BUFFD4BWP_LVT i z vdd vss 276 | 277 | x0 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 278 | 279 | x1 net11 i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 280 | 281 | x2 net11 i vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 282 | 283 | x3 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 284 | 285 | x4 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 286 | 287 | x5 z net11 vdd vdd pch_lvt_mac l=80e-9 w=820e-9 multi=1 nf=1 288 | 289 | x6 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 290 | 291 | x7 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 292 | 293 | x8 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 294 | 295 | x9 net11 i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 296 | 297 | x10 z net11 vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 298 | 299 | x11 net11 i vss vss nch_lvt_mac l=80e-9 w=620e-9 multi=1 nf=1 300 | .ends BUFFD4BWP_LVT 301 | 302 | .subckt NR2D8BWP_LVT a1 a2 zn vdd vss 303 | 304 | x0 net13 a2 vdd vdd pch_lvt_mac l=80e-9 w=6.56e-6 multi=1 nf=1 305 | 306 | x1 zn a1 net13 vdd pch_lvt_mac l=80e-9 w=6.56e-6 multi=1 nf=1 307 | 308 | x2 zn a2 vss vss nch_lvt_mac l=80e-9 w=4.96e-6 multi=1 nf=1 309 | 310 | x3 zn a1 vss vss nch_lvt_mac l=80e-9 w=4.96e-6 multi=1 nf=1 311 | .ends NR2D8BWP_LVT 312 | 313 | .subckt SR_Latch_LVT q qb r s vdd vss 314 | 315 | 316 | xi1 r qb q vdd vss NR2D8BWP_LVT 317 | 318 | 319 | xi0 s q qb vdd vss NR2D8BWP_LVT 320 | .ends SR_Latch_LVT 321 | 322 | .subckt COMPARATOR_schematic clk gnd outm outp vdd _net0 _net1 323 | 324 | xm0 gnd intern gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 325 | 326 | xm22 gnd interp gnd gnd nch_lvt_mac l=1e-6 w=1.05e-6 multi=1 nf=1 327 | 328 | xm16 outm crossp gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 329 | 330 | xm17 outp crossn gnd gnd nch_lvt_mac l=40e-9 w=1.44e-6 multi=1 nf=4 331 | 332 | xm4 crossn crossp intern gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 333 | 334 | xm3 crossp crossn interp gnd nch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 335 | 336 | xm7 net069 clk gnd gnd nch_lvt_mac l=40e-9 w=3.68e-6 multi=1 nf=8 337 | 338 | xm5 intern _net0 net069 gnd nch_lvt_mac l=40e-9 w=7.68e-6 multi=1 nf=8 339 | 340 | xm6 interp _net1 net069 gnd nch_lvt_mac l=40e-9 w=7.68e-6 multi=1 nf=8 341 | 342 | xm8 outm crossp vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 343 | 344 | xm18 intern clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=2 345 | 346 | xm15 outp crossn vdd vdd pch_lvt_mac l=40e-9 w=1.92e-6 multi=1 nf=4 347 | 348 | xm2 interp clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=2 349 | 350 | xm1 crossn clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=2 351 | 352 | xm12 crossp clk vdd vdd pch_lvt_mac l=40e-9 w=960e-9 multi=1 nf=2 353 | 354 | xm14 crossn crossp vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 355 | 356 | xm13 crossp crossn vdd vdd pch_lvt_mac l=40e-9 w=3.84e-6 multi=1 nf=8 357 | .ends COMPARATOR_schematic 358 | 359 | .subckt RR1 net040 net010 VREF GND net025 SYS_CLKB VDD net035 360 | xi24 net040 net010 VREF GND BUFFD4BWP_LVT 361 | xi25 net025 SYS_CLKB net040 net035 VDD GND DFCND4BWP_LVT_stupid 362 | .ends RR1 363 | 364 | .subckt RRR1 net046 SYS_CLKB VDD DO net038 GND net025 net028 net020 SYS_CLK 365 | xi12 net046 SYS_CLKB DO net038 VDD GND DFCND4BWP_LVT_stupid 366 | xi6 net046 net025 net028 net020 VDD GND SR_Latch_LVT 367 | xi4 SYS_CLK SYS_CLKB VDD GND INVD4BWP_LVT 368 | .ends RRR1 369 | 370 | .topckt adc1 DO GND IBIAS1 IBIAS2 SYS_CLK VCM VDD VINN VINP OTA1_INN OTA1_INP OTA2_INN OTA2_INP SUM_N SUM_P VINT1N VINT1P VINT2N VINT2P VREF 371 | 372 | input_res VINP VINN OTA1_INP OTA1_INN GND INPUT_RES 373 | 374 | xr47 OTA1_INN VINT2P GND rppolywo_m lr=34.8e-6 wr=400e-9 multi=1 m=1 series=46 segspace=250e-9 375 | 376 | xr28 OTA1_INP VINT2N GND rppolywo_m lr=34.8e-6 wr=400e-9 multi=1 m=1 series=46 segspace=250e-9 377 | 378 | xr21 net010 OTA1_INP GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 379 | 380 | xr20 net012 OTA1_INN GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 381 | 382 | xr23 net010 OTA2_INP GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=10 segspace=250e-9 383 | 384 | xr25 net012 SUM_N GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=15 segspace=250e-9 385 | 386 | xr24 net010 SUM_P GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=15 segspace=250e-9 387 | 388 | xr22 net012 OTA2_INN GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=10 segspace=250e-9 389 | 390 | xr19 VINT2N SUM_N GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=1 segspace=250e-9 391 | 392 | xr16 VINT1N OTA2_INN GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 393 | 394 | xr17 VINT1P OTA2_INP GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=5 segspace=250e-9 395 | 396 | 397 | xr18 VINT2P SUM_P GND rppolywo_m lr=10e-6 wr=600e-9 multi=1 m=1 series=1 segspace=250e-9 398 | 399 | 400 | 401 | 402 | xc4 OTA1_INP VINT1N cfmom_2t nr=96 lr=12.4e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 403 | 404 | xc2 OTA2_INN VINT2P cfmom_2t nr=70 lr=9.85e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 405 | 406 | xc0 OTA1_INN VINT1P cfmom_2t nr=96 lr=12.4e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 407 | 408 | xc1 OTA2_INP VINT2N cfmom_2t nr=70 lr=9.85e-6 w=70e-9 s=70e-9 stm=2 spm=5 multi=1 ftip=140e-9 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | xi22 GND IBIAS2 VCM VDD OTA2_INN OTA2_INP VINT2N VINT2P OTA_XT_MAGICAL 418 | 419 | 420 | xi20 GND IBIAS1 VCM VDD OTA1_INP OTA1_INN VINT1P VINT1N OTA_XT_MAGICAL 421 | 422 | 423 | 424 | 425 | 426 | 427 | 428 | 429 | xi19 SYS_CLK GND net028 net020 VDD SUM_P SUM_N COMPARATOR_schematic 430 | 431 | rr1 net040 net010 VREF GND net025 SYS_CLKB VDD net035 RR1 432 | rr2 net026 net012 VREF GND net046 SYS_CLKB VDD net022 RR1 433 | 434 | 435 | rrr1 net046 SYS_CLKB VDD DO net038 GND net025 net028 net020 SYS_CLK RRR1 436 | 437 | .ends adc1 438 | --------------------------------------------------------------------------------