├── .ci-scripts ├── bits.tcl └── run-linter.py ├── .gitignore ├── .gitlab-ci.yml ├── .gitmodules ├── .vscode └── settings.json ├── CPU设计搞.pptx ├── CPU设计表.xlsx ├── LICENSE ├── README.md ├── asm ├── Makefile ├── bak.txt ├── final_code.code-workspace ├── nrt.txt ├── onlySoftware_bak.txt ├── soft_no_optimize.txt ├── sort.txt ├── template.txt ├── test-data.txt └── user-sample.s ├── design.pdf ├── ramfile └── BRAM_Curing_inst.coe ├── tb_behav_2.wcfg ├── tb_top.wcfg ├── thinpad_top.srcs ├── constrs_1 │ └── imports │ │ └── new │ │ └── thinpad_top.xdc ├── sim_1 │ ├── imports │ │ ├── CFImemory64Mb_bottom.mem │ │ └── CFImemory64Mb_top.mem │ └── new │ │ ├── 28F640P30.v │ │ ├── clock.v │ │ ├── cpld_model.v │ │ ├── flag_sync_cpld.v │ │ ├── include │ │ ├── BankLib.h │ │ ├── CUIcommandData.h │ │ ├── TimingData.h │ │ ├── UserData.h │ │ ├── data.h │ │ └── def.h │ │ ├── sram_model.v │ │ └── tb.sv └── sources_1 │ ├── imports │ └── new │ │ ├── EX │ │ ├── ALU.v │ │ ├── ALU_ctl.v │ │ └── data_hazard_ex.v │ │ ├── EX_MEM.v │ │ ├── ID │ │ ├── central_ctl.v │ │ ├── data_hazard_jump.v │ │ ├── data_hazard_lwalu.v │ │ ├── data_j_hazard_lw.v │ │ ├── imm_extension.v │ │ ├── jump_ident.v │ │ ├── rW_select.v │ │ ├── reg_files.v │ │ └── stall_pipeline.v │ │ ├── ID_EX.v │ │ ├── IF │ │ ├── fast_start_transition.v │ │ ├── inst_i_ctl.v │ │ ├── pc.v │ │ └── pc_stall.v │ │ ├── IF_ID.v │ │ ├── MEM │ │ ├── data_hazard_lwsw.v │ │ ├── loaddata_stall.v │ │ ├── r_w_instram_stall.v │ │ └── sw_stall.v │ │ ├── MEM_WB.v │ │ ├── SEG7_LUT.v │ │ ├── UART │ │ └── uart_buffer.v │ │ ├── arbitration.v │ │ ├── async.v │ │ ├── base_ram_ctl.v │ │ ├── define.v │ │ ├── ext_ram_ctl.v │ │ ├── mode_convert.v │ │ ├── my_cpu.v │ │ ├── sram_ctl.v │ │ ├── thinpad_top.v │ │ └── vga.v │ ├── ip │ ├── BRAM_Curing_inst.coe │ ├── blk_mem_gen_0 │ │ ├── blk_mem_gen_0.mif │ │ ├── blk_mem_gen_0.xci │ │ ├── blk_mem_gen_0.xml │ │ ├── blk_mem_gen_0_ooc.xdc │ │ ├── doc │ │ │ └── blk_mem_gen_v8_4_changelog.txt │ │ ├── hdl │ │ │ └── blk_mem_gen_v8_4_vhsyn_rfs.vhd │ │ ├── misc │ │ │ └── blk_mem_gen_v8_4.vhd │ │ ├── sim │ │ │ └── blk_mem_gen_0.v │ │ ├── simulation │ │ │ └── blk_mem_gen_v8_4.v │ │ └── synth │ │ │ └── blk_mem_gen_0.vhd │ ├── mult_gen_0 │ │ ├── doc │ │ │ └── mult_gen_v12_0_changelog.txt │ │ ├── hdl │ │ │ ├── mult_gen_v12_0_vh_rfs.vhd │ │ │ ├── xbip_bram18k_v3_0_vh_rfs.vhd │ │ │ ├── xbip_pipe_v3_0_vh_rfs.vhd │ │ │ └── xbip_utils_v3_0_vh_rfs.vhd │ │ ├── mult_gen_0.xci │ │ ├── mult_gen_0.xml │ │ ├── sim │ │ │ └── mult_gen_0.vhd │ │ └── synth │ │ │ └── mult_gen_0.vhd │ └── pll_example │ │ ├── doc │ │ └── clk_wiz_v6_0_changelog.txt │ │ ├── mmcm_pll_drp_func_7s_mmcm.vh │ │ ├── mmcm_pll_drp_func_7s_pll.vh │ │ ├── mmcm_pll_drp_func_us_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_pll.vh │ │ ├── mmcm_pll_drp_func_us_plus_mmcm.vh │ │ ├── mmcm_pll_drp_func_us_plus_pll.vh │ │ ├── pll_example.v │ │ ├── pll_example.xci │ │ ├── pll_example.xdc │ │ ├── pll_example.xml │ │ ├── pll_example_board.xdc │ │ ├── pll_example_clk_wiz.v │ │ └── pll_example_ooc.xdc │ └── new │ ├── accelerator.v │ └── mem_speed.v ├── thinpad_top.xpr ├── vivado_pid1536.str ├── vivado_pid38980.zip ├── vivado_pid44580.zip └── vivado_pid47984.str /.ci-scripts/bits.tcl: -------------------------------------------------------------------------------- 1 | update_compile_order -fileset sources_1 2 | 3 | # If IP cores are used 4 | if { [llength [get_ips]] != 0} { 5 | upgrade_ip [get_ips] 6 | 7 | foreach ip [get_ips] { 8 | create_ip_run [get_ips $ip] 9 | } 10 | 11 | set ip_runs [get_runs -filter {SRCSET != sources_1 && IS_SYNTHESIS && NEEDS_REFRESH}] 12 | 13 | if { [llength $ip_runs] != 0} { 14 | launch_runs -quiet -jobs 2 {*}$ip_runs 15 | 16 | foreach r $ip_runs { 17 | wait_on_run $r 18 | } 19 | } 20 | 21 | } 22 | 23 | reset_run impl_1 24 | reset_run synth_1 25 | launch_runs -jobs 2 impl_1 -to_step write_bitstream 26 | wait_on_run impl_1 27 | 28 | exit -------------------------------------------------------------------------------- /.ci-scripts/run-linter.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | from lxml import etree 3 | import chardet 4 | import sys 5 | import os 6 | from pathlib import Path 7 | from typing import Tuple, List, Set 8 | import shutil 9 | import subprocess 10 | import traceback 11 | 12 | def is_header(f: Path): 13 | with f.open('rb') as fd: 14 | return -1 == fd.read().find(b'endmodule') 15 | 16 | def transcoding(src: Path, target: Path): 17 | with src.open("rb") as fd: 18 | rawdata = fd.read() 19 | res = chardet.detect(rawdata) 20 | encoding = res['encoding'] if res['confidence'] > 0.5 else "GBK" 21 | try: 22 | s = rawdata.decode(encoding) 23 | except: 24 | print("Transcoding", src, ':') 25 | traceback.print_exc() 26 | s = rawdata.decode(encoding, 'replace') 27 | with target.open("wb") as wfd: 28 | wfd.write(s.encode('utf-8')) 29 | 30 | def parse_project(xpr: Path) -> Tuple[str, Set[str], Set[str]]: 31 | prjname = os.path.splitext(xpr.name)[0] 32 | prjdir = xpr.parent 33 | srcdir = prjdir / (prjname + ".srcs") 34 | topname = '' 35 | target = prjdir / '.lint' 36 | 37 | tree = etree.parse(str(xpr)) 38 | srclist = set() 39 | inclist = set() 40 | for fileset in tree.xpath("/Project/FileSets/FileSet"): 41 | if fileset.attrib['Type'] != 'DesignSrcs' and \ 42 | fileset.attrib['Type'] != 'BlockSrcs': 43 | continue 44 | for child in fileset: 45 | if child.tag == 'File': 46 | tmp = child.attrib['Path'] 47 | tmp = tmp.replace('$PSRCDIR', str(srcdir)) 48 | tmp = tmp.replace('$PPRDIR', str(prjdir)) 49 | tmp = tmp.replace(".xci", '_stub.v') 50 | vlog = Path(tmp) 51 | if not vlog.is_file(): 52 | print("Source file", vlog, "does not exist") 53 | continue 54 | vlog_target = target / vlog.relative_to(prjdir) 55 | vlog_target.parent.mkdir(exist_ok=True, parents=True) 56 | # shutil.copy(vlog, vlog_target) 57 | transcoding(vlog, vlog_target) 58 | inclist.add(str(vlog_target.parent)) 59 | if not is_header(vlog_target): 60 | srclist.add(str(vlog_target)) 61 | elif child.tag == 'Config' and fileset.attrib['Type'] == 'DesignSrcs': 62 | topname = child.xpath("./Option[@Name='TopModule']")[0].attrib['Val'] 63 | 64 | return (topname, srclist, inclist) 65 | 66 | def run_linter(prjdir: Path, topname: str, srclist: Set[str], inclist: Set[str]): 67 | linter_log = prjdir / "linter.log" 68 | args = ["verilator","--lint-only","-Wall","-Wno-DECLFILENAME","-Wno-PINCONNECTEMPTY","-Wno-UNUSED"] 69 | args += ['--top-module', topname] 70 | incargs = [ '-I' + i for i in inclist] 71 | args += incargs 72 | args += srclist 73 | # print(args) 74 | res = subprocess.run(args) 75 | if res.returncode != 0: 76 | print("Return code of verilator is", res.returncode) 77 | 78 | if __name__ == "__main__": 79 | try: 80 | xpr = Path(sys.argv[1]) 81 | topname, srclist, inclist = parse_project(xpr) 82 | run_linter(xpr.parent, topname, srclist, inclist) 83 | except: 84 | traceback.print_exc() 85 | 86 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.bin 2 | *.o 3 | *.elf 4 | ipshared/ 5 | *_netlist.* 6 | *_stub.* 7 | *.dcp 8 | *.veo 9 | *.vho 10 | *.hwh 11 | *.hdf 12 | thinpad_top.tmp/ 13 | thinpad_top.cache/ 14 | thinpad_top.hw/ 15 | thinpad_top.ip_user_files/ 16 | thinpad_top.runs/ 17 | thinpad_top.sim/sim_1/behav/xsim/ 18 | .Xil/ 19 | *.jou 20 | *.log 21 | *.dcp 22 | /.lint/ -------------------------------------------------------------------------------- /.gitlab-ci.yml: -------------------------------------------------------------------------------- 1 | variables: 2 | GIT_SUBMODULE_STRATEGY: recursive 3 | 4 | stages: 5 | - build 6 | 7 | bitstream: 8 | stage: build 9 | image: vivado2019:2019.2-mips-gcc 10 | before_script: 11 | - source /opt/Xilinx/Vivado/2019.2/settings64.sh 12 | - export PATH=/opt/mips-mti-elf/2016.05-06/bin:${PATH} 13 | script: 14 | - make -C asm 15 | - python3 ./.ci-scripts/run-linter.py thinpad_top.xpr 2>linter.log 16 | - str="thinpad_top.srcs" 17 | - diff=$(git diff --name-only $CI_COMMIT_BEFORE_SHA $CI_COMMIT_SHA) 18 | - > 19 | if [[ $diff =~ $str ]] 20 | then vivado -mode tcl -source .ci-scripts/bits.tcl thinpad_top.xpr 21 | fi 22 | - test -f thinpad_top.runs/impl_1/*.bit 23 | cache: 24 | key : bit 25 | paths : 26 | - thinpad_top.runs/impl_1/*.bit 27 | 28 | artifacts: 29 | name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME" 30 | when: always 31 | paths: 32 | - asm/*.bin 33 | - thinpad_top.runs/impl_1/*.bit 34 | - thinpad_top.runs/*/runme.log 35 | - linter.log -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/.gitmodules -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "debug.allowBreakpointsEverywhere": true, 3 | "files.exclude": { 4 | "**/.vscode": true, 5 | "compile_commands.json": true, 6 | "*.hrccproj": true, 7 | "*.sln": true, 8 | "*.suo": true 9 | }, 10 | "git.ignoreLimitWarning": true 11 | } -------------------------------------------------------------------------------- /CPU设计搞.pptx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/CPU设计搞.pptx -------------------------------------------------------------------------------- /CPU设计表.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/CPU设计表.xlsx -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2021 HaitianJiang 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/README.md -------------------------------------------------------------------------------- /asm/Makefile: -------------------------------------------------------------------------------- 1 | GCCPREFIX?=mips-mti-elf- 2 | 3 | override CFLAGS += -mips32r2 -mno-abicalls -mno-shared -EL -nostdlib -nostdinc -g 4 | override LDFLAGS += -nostdlib -EL -static 5 | 6 | CC :=$(GCCPREFIX)gcc 7 | LD := $(GCCPREFIX)ld 8 | AR := $(GCCPREFIX)ar 9 | OBJCOPY := $(GCCPREFIX)objcopy 10 | OBJDUMP := $(GCCPREFIX)objdump 11 | 12 | SRC := $(wildcard *.s) 13 | BINS := $(patsubst %.s, %.bin, $(SRC)) 14 | 15 | all: $(BINS) 16 | 17 | %.bin: %.elf 18 | $(OBJCOPY) -j .text -O binary $^ $@ 19 | 20 | %.elf: %.o 21 | $(LD) $(LDFLAGS) -Ttext 0x80100000 -o $@ $^ 22 | 23 | %.o: %.s 24 | $(CC) $(CFLAGS) -x assembler-with-cpp -c -o $@ $^ 25 | -------------------------------------------------------------------------------- /asm/bak.txt: -------------------------------------------------------------------------------- 1 | # # 假设要计算的数，存储在了 地址0x8040_0000 2 | # lui $t7,0x8040 # 第一个要计算的数的地址 3 | # lui $t3,0x8048 # 总数 512K t3 = 0x8048_0000，加到这个数之后，就停下来了 4 | # lui $t4,0x8050 # 存储计算结果 0x8050_0000 -- SRAM 0x4_0000 5 | 6 | # # addu $t3,$t3,2 # 展开1次 7 | 8 | # out_loop: 9 | # lw $t0,0($t7) # t0 = number 10 | # ori $t2,$zero,0x0 # t2 = 0,save result 11 | 12 | # # ##### 13 | # # 内循环 14 | # ori $t6,$zero,32 # t6 = xx 循环8次，循环展开3次 15 | # ori $t5,$zero,0 # t5 = 0 16 | # loop: 17 | # # 1 18 | # ori $t1,$t0,0x0 # t1 = t0 19 | # andi $t1,$t1,0x1 # t1 &= 0x1 20 | # addu $t2,$t2,$t1 # t2 += t1 21 | # srl $t0,$t0,0x1 # t0 >>= 0x1 22 | # # 2 23 | # ori $t1,$t0,0x0 # t1 = t0 24 | # andi $t1,$t1,0x1 # t1 &= 0x1 25 | # addu $t2,$t2,$t1 # t2 += t1 26 | # srl $t0,$t0,0x1 # t0 >>= 0x1 27 | # # 3 28 | # ori $t1,$t0,0x0 # t1 = t0 29 | # andi $t1,$t1,0x1 # t1 &= 0x1 30 | # addu $t2,$t2,$t1 # t2 += t1 31 | # srl $t0,$t0,0x1 # t0 >>= 0x1 32 | # # 4 33 | # ori $t1,$t0,0x0 # t1 = t0 34 | # andi $t1,$t1,0x1 # t1 &= 0x1 35 | # addu $t2,$t2,$t1 # t2 += t1 36 | # srl $t0,$t0,0x1 # t0 >>= 0x1 37 | 38 | # addiu $t5,$t5,0x4 # t5 += 4 39 | # bne $t6,$t5,loop 40 | # nop 41 | 42 | # # write to SRAM 43 | # sw $t2,0($t4) # save result 44 | # addiu $t4,$t4,4 # t4 += 4 45 | 46 | 47 | 48 | # # ##### 49 | # addiu $t7,$t7,4 # t7 += 4 50 | # bne $t7,$t3,out_loop 51 | # nop 52 | 53 | 54 | 55 | # .text 56 | # ori $t0, $zero, 0x1 # t0 = 1 57 | # ori $t1, $zero, 0x1 # t1 = 1 58 | # xor $v0, $v0, $v0 # v0 = 0 59 | # ori $v1, $zero, 8 # v1 = 8 60 | # lui $a0, 0x8040 # a0 = 0x80400000 61 | # 62 | # loop: 63 | # addu $t2, $t0, $t1 # t2 = t0+t1 64 | # ori $t0, $t1, 0x0 # t0 = t1 65 | # ori $t1, $t2, 0x0 # t1 = t2 66 | # sw $t1, 0($a0) 67 | # addiu $a0, $a0, 4 # a0 += 4 68 | # addiu $v0, $v0, 1 # v0 += 1 69 | # 70 | # bne $v0, $v1, loop 71 | # ori $zero, $zero, 0 # nop -------------------------------------------------------------------------------- /asm/final_code.code-workspace: -------------------------------------------------------------------------------- 1 | { 2 | "folders": [], 3 | "settings": { 4 | "debug.allowBreakpointsEverywhere": true, 5 | "files.exclude": { 6 | "**/.vscode": true, 7 | "compile_commands.json": true, 8 | "*.hrccproj": true, 9 | "*.sln": true, 10 | "*.suo": true 11 | } 12 | } 13 | } -------------------------------------------------------------------------------- /asm/nrt.txt: -------------------------------------------------------------------------------- 1 | .set noreorder 2 | .set noat 3 | .globl __start 4 | .section text 5 | 6 | __start: 7 | .text 8 | li $1,0x31111 9 | ori $2, $zero, 0 # t0 = 0 10 | ori $3, $zero, 0 # t1 = 0 11 | ori $4, $0 , 1 #1 12 | sll $5, $4 , 1 #2 13 | sll $6, $5 , 1 #3 14 | sll $7, $6 , 1 #4 15 | sll $8, $7 , 1 #5 16 | sll $9, $8 , 1 #6 17 | sll $10, $9 , 1 #7 18 | sll $11, $10 , 1 #8 19 | sll $12, $11 , 1 #9 20 | sll $13, $12 , 1 #10 21 | sll $14, $13 , 1 #11 22 | sll $15, $14 , 1 #12 23 | sll $16, $15 , 1 #13 24 | sll $17, $16 , 1 #14 25 | sll $18, $17 , 1 26 | sll $19, $18 , 1 27 | sll $20, $19 , 1 28 | sll $21, $20 , 1 29 | sll $22, $21 , 1 30 | 31 | # 特殊化处理，因为0x31111一共18位，所以才到$22，18个0 32 | 33 | # sum = $3 34 | # num = $2 35 | # condition = $1,$2 36 | loop: 37 | addiu $2,$2, 1 # $2 ++ (0的1的个数是0，直接忽略) 38 | 39 | and $23,$4,$2 40 | srl $23,$23,0 # >> 41 | addu $3,$3,$23 42 | 43 | and $23,$5,$2 44 | srl $23,$23,1 45 | addu $3,$3,$23 46 | 47 | and $23,$6,$2 48 | srl $23,$23,2 49 | addu $3,$3,$23 50 | 51 | and $23,$7,$2 52 | srl $23,$23,3 53 | addu $3,$3,$23 54 | 55 | and $23,$8,$2 56 | srl $23,$23,4 57 | addu $3,$3,$23 58 | 59 | and $23,$9,$2 60 | srl $23,$23,5 61 | addu $3,$3,$23 62 | 63 | and $23,$10,$2 64 | srl $23,$23,6 65 | addu $3,$3,$23 66 | 67 | and $23,$11,$2 68 | srl $23,$23,7 69 | addu $3,$3,$23 70 | 71 | and $23,$12,$2 72 | srl $23,$23,8 73 | addu $3,$3,$23 74 | 75 | and $23,$13,$2 76 | srl $23,$23,9 77 | addu $3,$3,$23 78 | 79 | and $23,$14,$2 80 | srl $23,$23,10 81 | addu $3,$3,$23 82 | 83 | and $23,$15,$2 84 | srl $23,$23,11 85 | addu $3,$3,$23 86 | 87 | and $23,$16,$2 88 | srl $23,$23,12 89 | addu $3,$3,$23 90 | 91 | and $23,$17,$2 92 | srl $23,$23,13 93 | addu $3,$3,$23 94 | 95 | and $23,$18,$2 96 | srl $23,$23,14 97 | addu $3,$3,$23 98 | 99 | and $23,$19,$2 100 | srl $23,$23,15 101 | addu $3,$3,$23 102 | 103 | and $23,$20,$2 104 | srl $23,$23,16 105 | addu $3,$3,$23 106 | 107 | and $23,$21,$2 108 | srl $23,$23,17 109 | addu $3,$3,$23 110 | 111 | and $23,$22,$2 112 | srl $23,$23,18 113 | addu $3,$3,$23 114 | 115 | # ################# 116 | bne $2, $1, loop 117 | ori $zero, $zero, 0 # nop 118 | 119 | ori $1,$zero,0 120 | lui $1, 0x8040 121 | sw $3,0($1) 122 | 123 | jr $ra 124 | ori $zero, $zero, 0 # nop -------------------------------------------------------------------------------- /asm/onlySoftware_bak.txt: -------------------------------------------------------------------------------- 1 | # 本文件备份优化后版本的纯软件程序 -------------------------------------------------------------------------------- /asm/soft_no_optimize.txt: -------------------------------------------------------------------------------- 1 | # 本文件用于备份 未优化版本的程序 -------------------------------------------------------------------------------- /asm/sort.txt: -------------------------------------------------------------------------------- 1 | 2 | # //swap a and b if a> sa; 66 | `add_op: 67 | alu_result_o <= op1 + op2; 68 | `mul_op: //// multipling unit: 0 cycle 69 | alu_result_o <= mul_result; 70 | `lui_op: 71 | alu_result_o <= {op2[15:0],16'h0000}; 72 | 73 | `sllv_op: // 还得有rs……注意移位最大32位 74 | alu_result_o <= op2 << op1[4:0]; 75 | 76 | //////////////////////////////// 77 | `sltu_op: 78 | alu_result_o <= (op1 < op2)? 1 : 0; 79 | //////////////////////////////// 80 | 81 | 82 | default: 83 | alu_result_o <= 0; 84 | endcase 85 | end 86 | 87 | endmodule 88 | 89 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/EX/ALU_ctl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/03 21:30:52 7 | // Design Name: 8 | // Module Name: ALU_ctl 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "../define.v" 24 | 25 | module ALU_ctl( 26 | input wire [3:0] alu_op_i, 27 | input wire [5:0] func, 28 | 29 | output reg [3:0] op_o 30 | ); 31 | 32 | always@(*) 33 | begin 34 | case(alu_op_i) 35 | `Rtype_alu_op: 36 | begin 37 | case (func) 38 | `and_func: 39 | op_o <= `and_op; 40 | `or_func: 41 | op_o <= `or_op; 42 | `xor_func: 43 | op_o <= `xor_op; 44 | `sll_func: 45 | op_o <= `sll_op; 46 | `srl_func: 47 | op_o <= `srl_op; 48 | `sllv_func: 49 | op_o <= `sllv_op; 50 | `addu_func: 51 | op_o <= `add_op; 52 | //////////////////////////////// 53 | `sltu_func: 54 | op_o <= `sltu_op; 55 | //////////////////////////////// 56 | 57 | default: 58 | op_o <= `other_op; 59 | endcase 60 | end 61 | `mul_alu_op: 62 | op_o <= `mul_op; 63 | `lui_alu_op: 64 | op_o <= `lui_op; 65 | `andi_alu_op: 66 | op_o <= `and_op; 67 | `ori_alu_op: 68 | op_o <= `or_op; 69 | `xori_alu_op: 70 | op_o <= `xor_op; 71 | `add_alu_op: 72 | op_o <= `add_op; 73 | 74 | default: 75 | op_o <= `other_op; 76 | endcase 77 | end 78 | 79 | endmodule 80 | 81 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/EX/data_hazard_ex.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/06 14:05:44 7 | // Design Name: 8 | // Module Name: data_hazard_ex 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 位于EX阶段的数据冒险旁路处理单元 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | 24 | module data_hazard_ex( 25 | input wire ex_mem_w_i, // write enable signal 26 | input wire mem_wb_w_i, 27 | input wire [4:0] ex_mem_rd_i, 28 | input wire [4:0] mem_wb_rd_i, 29 | 30 | input wire [4:0] id_ex_rs_i, 31 | input wire [4:0] id_ex_rt_i, 32 | 33 | output reg [1:0] bypass_a_o, 34 | output reg [1:0] bypass_b_o 35 | ); 36 | 37 | 38 | // bypass A 39 | always@(*) 40 | begin 41 | if( 42 | (ex_mem_w_i == `reg_write_enable) && 43 | (ex_mem_rd_i != `zero_register) && 44 | (ex_mem_rd_i == id_ex_rs_i) 45 | ) 46 | begin 47 | bypass_a_o <= `data_from_EX_MEM; 48 | end 49 | else if( 50 | (mem_wb_w_i == `reg_write_enable) && 51 | (mem_wb_rd_i != `zero_register) && 52 | (mem_wb_rd_i == id_ex_rs_i) 53 | ) 54 | begin 55 | bypass_a_o <= `data_from_MEM_WB; 56 | end 57 | else 58 | begin 59 | bypass_a_o <= `data_from_regfile; 60 | end 61 | end 62 | 63 | 64 | // bypass B 65 | always@(*) 66 | begin 67 | if( 68 | (ex_mem_w_i == `reg_write_enable) && 69 | (ex_mem_rd_i != `zero_register) && 70 | (ex_mem_rd_i == id_ex_rt_i) 71 | ) 72 | begin 73 | bypass_b_o <= `data_from_EX_MEM; 74 | end 75 | else if( 76 | (mem_wb_w_i == `reg_write_enable) && 77 | (mem_wb_rd_i != `zero_register) && 78 | (mem_wb_rd_i == id_ex_rt_i) 79 | ) 80 | begin 81 | bypass_b_o <= `data_from_MEM_WB; 82 | end 83 | else 84 | begin 85 | bypass_b_o <= `data_from_regfile; 86 | end 87 | end 88 | 89 | endmodule 90 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/EX_MEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/06 09:05:39 7 | // Design Name: 8 | // Module Name: EX_MEM 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "define.v" 24 | 25 | module EX_MEM( 26 | input wire clk, 27 | input wire rst_n, 28 | input wire ex_mem_w_i, 29 | 30 | input wire [31:0] data_to_mem_i, 31 | input wire [31:0] alu_result_i, 32 | input wire [4:0] rW_i, 33 | 34 | output reg [31:0] data_to_mem_o, 35 | output reg [31:0] alu_result_o, 36 | output reg [4:0] rW_o, 37 | 38 | /* jump identifier */ 39 | input wire [31:0] jal_i, 40 | output reg [31:0] jal_o, 41 | 42 | /* control */ 43 | // MEM // 44 | input wire [1:0] mode_i, 45 | input wire data_w_i, 46 | input wire data_r_i, 47 | input wire mem_reg_i, 48 | input wire is_jump_inst_i, 49 | 50 | output reg [1:0] mode_o, 51 | output reg data_w_o, 52 | output reg data_r_o, 53 | output reg mem_reg_o, 54 | output reg is_jump_inst_o, 55 | 56 | // WB // 57 | input wire reg_we_i, 58 | input wire jal_en_i, 59 | output reg reg_we_o, 60 | output reg jal_en_o 61 | ); 62 | 63 | always@(posedge clk or posedge rst_n) 64 | begin 65 | if(rst_n == `rst_enable) 66 | begin 67 | data_to_mem_o <= 0; 68 | alu_result_o <= 0; 69 | rW_o <= 0; 70 | 71 | /* jump identifier */ 72 | jal_o <= 0; 73 | 74 | /* control */ 75 | // MEM // 76 | mode_o <= `byte_mode; 77 | data_w_o <= `data_w_disable; 78 | data_r_o <= `data_r_disable; 79 | mem_reg_o <= `data_from_reg; 80 | is_jump_inst_o <= `is_not_jump_inst; 81 | 82 | // WB // 83 | reg_we_o <= `reg_write_disable; 84 | jal_en_o <= `jal_disable; 85 | end 86 | else if(ex_mem_w_i == `ex_mem_write_enable) 87 | begin 88 | data_to_mem_o <= data_to_mem_i; 89 | if(jal_en_i == `jal_disable) 90 | begin 91 | alu_result_o <= alu_result_i; 92 | end 93 | else 94 | begin 95 | alu_result_o <= jal_i; 96 | end 97 | rW_o <= rW_i; 98 | 99 | /* jump identifier */ 100 | jal_o <= jal_i; 101 | 102 | /* control */ 103 | // MEM // 104 | mode_o <= mode_i; 105 | data_w_o <= data_w_i; 106 | data_r_o <= data_r_i; 107 | mem_reg_o <= mem_reg_i; 108 | is_jump_inst_o <= is_jump_inst_i; 109 | 110 | // WB // 111 | reg_we_o <= reg_we_i; 112 | jal_en_o <= jal_en_i; 113 | end 114 | else 115 | begin 116 | ; 117 | end 118 | end 119 | 120 | endmodule 121 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/data_hazard_jump.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/15 18:49:29 7 | // Design Name: 8 | // Module Name: data_hazard_jump 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module data_hazard_jump( 24 | // source 25 | input wire [4:0] if_id_rs_i, 26 | input wire [4:0] if_id_rt_i, 27 | 28 | // EX ALU 29 | input wire id_ex_w_i, 30 | input wire [4:0] id_ex_rd_i, 31 | 32 | // EX/MEM 33 | input wire ex_mem_w_i, 34 | input wire [4:0] ex_mem_rd_i, 35 | 36 | // MEM/WB 37 | input wire mem_wb_w_i, 38 | input wire [4:0] mem_wb_rd_i, 39 | 40 | // output 41 | output reg [1:0] bypass_dataA_o, 42 | output reg [1:0] bypass_dataB_o 43 | ); 44 | 45 | // dataA 46 | always @(*) 47 | begin 48 | if( 49 | (id_ex_w_i == `reg_write_enable) && 50 | (id_ex_rd_i != `zero_register) && 51 | (id_ex_rd_i == if_id_rs_i) 52 | ) 53 | begin 54 | bypass_dataA_o <= `j_data_from_alu_result; 55 | end 56 | else if( 57 | (ex_mem_w_i == `reg_write_enable) && 58 | (ex_mem_rd_i != `zero_register) && 59 | (ex_mem_rd_i == if_id_rs_i) 60 | ) 61 | begin 62 | bypass_dataA_o <= `j_data_from_ex_mem; 63 | end 64 | else if( 65 | (mem_wb_w_i == `reg_write_enable) && 66 | (mem_wb_rd_i != `zero_register) && 67 | (mem_wb_rd_i == if_id_rs_i) 68 | ) 69 | begin 70 | bypass_dataA_o <= `j_data_from_mem_wb; 71 | end 72 | else 73 | begin 74 | bypass_dataA_o <= `j_data_from_regfiles; 75 | end 76 | end 77 | 78 | 79 | // dataB 80 | always @(*) 81 | begin 82 | if( 83 | (id_ex_w_i == `reg_write_enable) && 84 | (id_ex_rd_i != `zero_register) && 85 | (id_ex_rd_i == if_id_rt_i) 86 | ) 87 | begin 88 | bypass_dataB_o <= `j_data_from_alu_result; 89 | end 90 | else if( 91 | (ex_mem_w_i == `reg_write_enable) && 92 | (ex_mem_rd_i != `zero_register) && 93 | (ex_mem_rd_i == if_id_rt_i) 94 | ) 95 | begin 96 | bypass_dataB_o <= `j_data_from_ex_mem; 97 | end 98 | else if( 99 | (mem_wb_w_i == `reg_write_enable) && 100 | (mem_wb_rd_i != `zero_register) && 101 | (mem_wb_rd_i == if_id_rt_i) 102 | ) 103 | begin 104 | bypass_dataB_o <= `j_data_from_mem_wb; 105 | end 106 | else 107 | begin 108 | bypass_dataB_o <= `j_data_from_regfiles; 109 | end 110 | end 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/data_hazard_lwalu.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/20 15:51:05 7 | // Design Name: 8 | // Module Name: data_hazard_lwalu 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 解决加载指令导致流水线暂停的数据冒险 13 | // lw/lb $1,0($4) 14 | // add $2,$1,$3 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | // 弃用！ 24 | // `include "../define.v" 25 | // module data_hazard_lwalu( 26 | // input wire id_ex_data_r_i, // load instruction 27 | // input wire [4:0] id_ex_rd_i, 28 | // input wire [4:0] if_id_rs_i, 29 | // input wire [4:0] if_id_rt_i, 30 | 31 | // output reg pc_w_o, 32 | // output reg if_id_w_o, 33 | // output reg data_clear_o 34 | // ); 35 | 36 | // always @(*) 37 | // begin 38 | // if ( 39 | // (id_ex_data_r_i == `data_r_enable) && 40 | // (id_ex_rd_i != `zero_register) && 41 | // ( 42 | // (id_ex_rd_i == if_id_rs_i) || 43 | // (id_ex_rd_i == if_id_rt_i) 44 | // ) 45 | // ) 46 | // begin 47 | // // stall pipeline 48 | // pc_w_o <= `pc_write_disable; 49 | // if_id_w_o <= `if_id_write_disable; 50 | // data_clear_o <= `data_clear_enable; 51 | // end 52 | // else 53 | // begin 54 | // pc_w_o <= `pc_write_enable; 55 | // if_id_w_o <= `if_id_write_enable; 56 | // data_clear_o <= `data_clear_disable; 57 | // end 58 | // end 59 | 60 | // endmodule 61 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/data_j_hazard_lw.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/20 20:48:09 7 | // Design Name: 8 | // Module Name: data_j_hazard_lw 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | // 弃用！ 23 | // module data_j_hazard_lw( 24 | 25 | // ); 26 | // endmodule 27 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/imm_extension.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/21 20:49:19 7 | // Design Name: 8 | // Module Name: imm_extension 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "../define.v" 24 | 25 | module imm_extension( 26 | // control 27 | input wire zero_sign_ext_i, 28 | 29 | input wire [15:0] imm, 30 | 31 | output reg [31:0] imm_ext_o 32 | ); 33 | 34 | always@(*) 35 | begin 36 | if(zero_sign_ext_i == `imm_zero_extension) 37 | begin 38 | imm_ext_o <= {16'b0,imm}; 39 | end 40 | else if(zero_sign_ext_i == `imm_sign_extension) 41 | begin 42 | imm_ext_o <= (imm[15] == 0)? {16'b0,imm}: {16'hFFFF,imm}; 43 | end 44 | end 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/jump_ident.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/21 21:42:09 7 | // Design Name: 8 | // Module Name: jump_ident 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: jump instruction decision in ID stage 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | 24 | module jump_ident( 25 | // input wire fast_mode_start_i, 26 | 27 | input wire [5:0] op, 28 | input wire [31:0] pc, 29 | input wire [25:0] offset, 30 | input wire [31:0] dataA, 31 | input wire [31:0] dataB, 32 | 33 | output reg isjump_o, 34 | output reg jal_en_o, 35 | 36 | output reg [31:0] pc_o, 37 | output reg [31:0] jal_o, // jal 执行之后保持的地址 pc+8 38 | 39 | output reg is_jump_inst_o 40 | ); 41 | 42 | // beq bne 43 | wire [31:0] data_sub = dataA - dataB; 44 | // b inst target 45 | wire [31:0] b_target_offset = { {15{offset[15]}}, offset[14:0], 2'b00 }; 46 | // pc + 4 47 | // wire [31:0] pc_add_4 = pc + 4; 48 | // wire [31:0] pc_add_4 = pc; // 【访存需要2周期就不用+4了】 49 | 50 | // normal Mode下，pc+4与指令对应 51 | // Fast Mode下，pc+4和指令一一对应 52 | wire [31:0] pc_add = pc; 53 | 54 | // 注意部分指令的无条件跳转！ 55 | always@(*) 56 | begin 57 | case(op) // 注意是 pc + 4，因为延迟槽指令必执行 58 | `jr_inst_op: // NOTE: jr_inst_op == Rtype_inst_op 59 | begin 60 | if(offset[5:0] == `jr_func) 61 | begin 62 | isjump_o <= 1; 63 | jal_en_o <= 0; 64 | pc_o <= dataA; 65 | jal_o <= 0; 66 | is_jump_inst_o <= `is_jump_inst; 67 | end 68 | else 69 | begin 70 | isjump_o <= `jump_disable; 71 | jal_en_o <= `jal_disable; 72 | pc_o <= 0; 73 | jal_o <= 0; 74 | is_jump_inst_o <= `is_not_jump_inst; 75 | end 76 | end 77 | `beq_inst_op: 78 | begin 79 | isjump_o <= (data_sub == 0); 80 | jal_en_o <= 0; 81 | pc_o <= pc_add + b_target_offset; 82 | jal_o <= 0; 83 | is_jump_inst_o <= `is_jump_inst; 84 | end 85 | `bne_inst_op: 86 | begin 87 | isjump_o <= (data_sub != 0); 88 | jal_en_o <= 0; 89 | pc_o <= pc_add + b_target_offset; 90 | jal_o <= 0; 91 | is_jump_inst_o <= `is_jump_inst; 92 | end 93 | // ################ NOTE: condition is sign bit is 0 but value not zero. 94 | `bgtz_inst_op: 95 | begin 96 | isjump_o <= (dataA[31] == 0 && dataA != 0); 97 | jal_en_o <= 0; 98 | pc_o <= pc_add + b_target_offset; 99 | jal_o <= 0; 100 | is_jump_inst_o <= `is_jump_inst; 101 | end 102 | // ################ NOTE: condition is sign bit is 0. 103 | // dataA此时是带符号数！ 104 | `bgez_inst_op: 105 | begin 106 | isjump_o <= (dataA[31] == 0); 107 | jal_en_o <= 0; 108 | pc_o <= pc_add + b_target_offset; 109 | jal_o <= 0; 110 | is_jump_inst_o <= `is_jump_inst; 111 | end 112 | `j_inst_op: 113 | begin 114 | isjump_o <= 1; 115 | jal_en_o <= 0; 116 | pc_o <= { pc_add[31:28], offset, 2'b00 }; 117 | jal_o <= 0; 118 | is_jump_inst_o <= `is_jump_inst; 119 | end 120 | `jal_inst_op: 121 | begin 122 | isjump_o <= 1; 123 | jal_en_o <= 1; 124 | pc_o <= { pc_add[31:28], offset, 2'b00 }; 125 | jal_o <= pc_add + 4; // 当前pc值就是延迟槽指令的pc 126 | is_jump_inst_o <= `is_jump_inst; 127 | end 128 | default: 129 | begin 130 | isjump_o <= `jump_disable; 131 | jal_en_o <= `jal_disable; 132 | pc_o <= 0; 133 | jal_o <= 0; 134 | is_jump_inst_o <= `is_not_jump_inst; 135 | end 136 | endcase 137 | end 138 | 139 | endmodule 140 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/rW_select.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/21 20:45:04 7 | // Design Name: 8 | // Module Name: rW_select 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "../define.v" 24 | 25 | module rW_select( 26 | // control 27 | input wire reg_dst_i, 28 | 29 | input wire [4:0] rd, 30 | input wire [4:0] rt, 31 | 32 | output reg [4:0] rW_o 33 | ); 34 | 35 | always@(*) 36 | begin 37 | if(reg_dst_i == `reg_dst_rd) 38 | rW_o <= rd; 39 | else if(reg_dst_i == `reg_dst_rt) 40 | rW_o <= rt; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/reg_files.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/21 15:26:48 7 | // Design Name: 8 | // Module Name: reg_files 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "../define.v" 24 | 25 | module reg_files( 26 | input wire clk, 27 | input wire rst_n, 28 | 29 | // write port 30 | input wire reg_we_i, // reg write enable 31 | input wire [4:0] rW, 32 | input wire [31:0] wr_data_i, 33 | 34 | // input wire [31:0] jal_i, 35 | // input wire jal_en_i, 36 | 37 | // read port A 38 | input wire [4:0] rA, 39 | output reg [31:0] A, 40 | 41 | // read port B 42 | input wire [4:0] rB, 43 | output reg [31:0] B 44 | ); 45 | 46 | 47 | reg [31:0] register [31:0]; 48 | // initial 49 | // begin 50 | // register[0] <= 0; 51 | // register[1] <= 0; 52 | // register[2] <= 0; 53 | // register[3] <= 0; 54 | // register[4] <= 0; 55 | // register[5] <= 0; 56 | // register[6] <= 0; 57 | // register[7] <= 0; 58 | // register[8] <= 0; 59 | // register[9] <= 0; 60 | // register[10] <= 0; 61 | // register[11] <= 0; 62 | // register[12] <= 0; 63 | // register[13] <= 0; 64 | // register[14] <= 0; 65 | // register[15] <= 0; 66 | // register[16] <= 0; 67 | // register[17] <= 0; 68 | // register[18] <= 0; 69 | // register[19] <= 0; 70 | // register[20] <= 0; 71 | // register[21] <= 0; 72 | // register[22] <= 0; 73 | // register[23] <= 0; 74 | // register[24] <= 0; 75 | // register[25] <= 0; 76 | // register[26] <= 0; 77 | // register[27] <= 0; 78 | // register[28] <= 0; 79 | // register[29] <= 0; 80 | // register[30] <= 0; 81 | // register[31] <= 0; 82 | // end 83 | 84 | /***********************/ 85 | /***** read port A *****/ 86 | /***********************/ 87 | 88 | always@(*) 89 | begin 90 | if(rst_n == `rst_enable) 91 | begin 92 | A <= 0; 93 | end 94 | else if(rA == `zero_register) 95 | begin 96 | A <= 0; 97 | end 98 | else 99 | begin 100 | A <= register[rA]; 101 | end 102 | end 103 | 104 | /***********************/ 105 | /***** read port B *****/ 106 | /***********************/ 107 | 108 | always@(*) 109 | begin 110 | if(rst_n == `rst_enable) 111 | begin 112 | B <= 0; 113 | end 114 | else if(rB == `zero_register) 115 | begin 116 | B <= 0; 117 | end 118 | else 119 | begin 120 | B <= register[rB]; 121 | end 122 | end 123 | 124 | /***********************/ 125 | /***** write port *****/ 126 | /***********************/ 127 | 128 | 129 | // NOTE: first write; second read 130 | always@(negedge clk) 131 | begin 132 | if(rst_n == `rst_disable) 133 | begin 134 | if((reg_we_i == `reg_write_enable) && (rW != `zero_register)) 135 | begin 136 | // if(jal_en_i == `jal_disable) 137 | register[rW] <= wr_data_i; 138 | // else 139 | // register[31] <= jal_i; // jal instruction 140 | end 141 | else 142 | ; 143 | end 144 | else 145 | begin 146 | ; 147 | end 148 | end 149 | 150 | endmodule 151 | 152 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID/stall_pipeline.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/20 22:14:03 7 | // Design Name: 8 | // Module Name: stall_pipeline 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 针对跳转指令/运算指令，被load指令束缚，需要暂停流水线 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module stall_pipeline( 24 | input wire id_ex_data_r_i, 25 | input wire [4:0] id_ex_rd_i, 26 | 27 | input wire ex_mem_data_r_i, 28 | input wire [4:0] ex_mem_rd_i, 29 | 30 | input wire is_jump_inst_i, 31 | 32 | input wire [4:0] if_id_rs_i, 33 | input wire [4:0] if_id_rt_i, 34 | 35 | input wire if_id_data_r_i, 36 | input wire if_id_data_w_i, 37 | 38 | output wire pc_w_o, 39 | output wire if_id_w_o, 40 | output wire clear_o 41 | ); 42 | 43 | // [lw; bne/add;] stall 1 cycle 44 | // 注意可能的误识别：（lw/sw的base字段，是bne的rs字段） 45 | // lw v0,0(a0) 46 | // lw/sw v0,-4(a1) 47 | // 补充逻辑：if_id_data_r/w_i disable 48 | reg pc_w_o_1; 49 | reg if_id_w_o_1; 50 | reg clear_o_1; 51 | always @(*) 52 | begin 53 | if ( 54 | (id_ex_data_r_i == `data_r_enable) && 55 | (id_ex_rd_i != `zero_register) && 56 | ( 57 | (id_ex_rd_i == if_id_rs_i) || 58 | (id_ex_rd_i == if_id_rt_i) 59 | ) && 60 | (if_id_data_r_i == `data_r_disable) && 61 | (if_id_data_w_i == `data_w_disable) 62 | ) 63 | begin 64 | // stall pipeline 65 | pc_w_o_1 <= `pc_write_disable; 66 | if_id_w_o_1 <= `if_id_write_disable; 67 | clear_o_1 <= `clear_enable; 68 | end 69 | else 70 | begin 71 | pc_w_o_1 <= `pc_write_enable; 72 | if_id_w_o_1 <= `if_id_write_enable; 73 | clear_o_1 <= `clear_disable; 74 | end 75 | end 76 | 77 | // [lw; other inst; bne;] stall 1 cycle 78 | reg pc_w_o_2; 79 | reg if_id_w_o_2; 80 | reg clear_o_2; 81 | always @(*) 82 | begin 83 | if ( 84 | (ex_mem_data_r_i == `data_r_enable) && 85 | (ex_mem_rd_i != `zero_register) && 86 | ( 87 | (ex_mem_rd_i == if_id_rs_i) || 88 | (ex_mem_rd_i == if_id_rt_i) 89 | ) 90 | ) 91 | begin 92 | // stall pipeline 93 | pc_w_o_2 <= `pc_write_disable; 94 | if_id_w_o_2 <= `if_id_write_disable; 95 | clear_o_2 <= `clear_enable; 96 | end 97 | else 98 | begin 99 | pc_w_o_2 <= `pc_write_enable; 100 | if_id_w_o_2 <= `if_id_write_enable; 101 | clear_o_2 <= `clear_disable; 102 | end 103 | end 104 | 105 | // result 106 | /// NOTE: [lw; other inst; not jump inst;] not stall 107 | /// 仅识别跳转指令，不会被误识别 108 | assign pc_w_o = (!is_jump_inst_i && pc_w_o_1) || 109 | (is_jump_inst_i && pc_w_o_1 && pc_w_o_2); 110 | 111 | assign if_id_w_o = (!is_jump_inst_i && if_id_w_o_1) || 112 | (is_jump_inst_i && if_id_w_o_1 && if_id_w_o_2); 113 | // clear logic is different 114 | assign clear_o = clear_o_1 || 115 | (is_jump_inst_i && !clear_o_1 && clear_o_2); 116 | 117 | endmodule 118 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/ID_EX.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/06 09:05:17 7 | // Design Name: 8 | // Module Name: ID_EX 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "define.v" 24 | 25 | module ID_EX( 26 | input wire clk, 27 | input wire rst_n, 28 | input wire clear_i, 29 | input wire id_ex_w_i, 30 | 31 | /* reg files */ 32 | input wire [31:0] A_i, 33 | input wire [31:0] B_i, 34 | output reg [31:0] A_o, 35 | output reg [31:0] B_o, 36 | 37 | 38 | /* rW select */ 39 | input wire [4:0] rW_i, 40 | output reg [4:0] rW_o, 41 | 42 | /* imm extension */ 43 | input wire [31:0] imm_ext_i, 44 | output reg [31:0] imm_ext_o, 45 | 46 | /* jump identifier */ 47 | input wire [31:0] jal_i, 48 | output reg [31:0] jal_o, 49 | 50 | /* rs rt */ 51 | input wire [4:0] rs_i, 52 | input wire [4:0] rt_i, 53 | output reg [4:0] rs_o, 54 | output reg [4:0] rt_o, 55 | 56 | /* control */ 57 | // EX // 58 | input wire alu_src_i, 59 | input wire [3:0] alu_op_i, 60 | input wire isjump_i, 61 | 62 | output reg alu_src_o, 63 | output reg [3:0] alu_op_o, 64 | output reg isjump_o, 65 | 66 | // MEM // 67 | input wire [1:0] mode_i, 68 | input wire data_w_i, 69 | input wire data_r_i, 70 | input wire mem_reg_i, 71 | input wire is_jump_inst_i, 72 | 73 | output reg [1:0] mode_o, 74 | output reg data_w_o, 75 | output reg data_r_o, 76 | output reg mem_reg_o, 77 | output reg is_jump_inst_o, 78 | 79 | // WB // 80 | input wire reg_we_i, 81 | input wire jal_en_i, 82 | output reg reg_we_o, 83 | output reg jal_en_o 84 | ); 85 | 86 | 87 | always@(posedge clk or posedge rst_n) 88 | begin 89 | if(rst_n == `rst_enable) 90 | begin 91 | /* reg files */ 92 | A_o <= 0; 93 | B_o <= 0; 94 | 95 | /* rW select */ 96 | rW_o <= 0; 97 | 98 | /* imm extension */ 99 | imm_ext_o <= 0; 100 | 101 | /* jump identifier */ 102 | jal_o <= 0; 103 | 104 | /* rs rt */ 105 | rs_o <= 0; 106 | rt_o <= 0; 107 | 108 | /* control */ 109 | // EX // 110 | alu_src_o <= `B_calculate; 111 | alu_op_o <= `other_alu_op; 112 | isjump_o <= `jump_disable; 113 | 114 | // MEM // 115 | mode_o <= `byte_mode; 116 | data_w_o <= `data_w_disable; 117 | data_r_o <= `data_r_disable; 118 | mem_reg_o <= `data_from_reg; 119 | is_jump_inst_o <= `is_not_jump_inst; 120 | 121 | // WB // 122 | reg_we_o <= `reg_write_disable; 123 | jal_en_o <= `jal_disable; 124 | end 125 | // 正常写入 126 | else if(id_ex_w_i == `id_ex_write_enable && clear_i == `clear_disable) 127 | begin 128 | /* reg files */ 129 | A_o <= A_i; 130 | B_o <= B_i; 131 | 132 | /* rW select */ 133 | if(jal_en_i == `jal_disable) 134 | begin 135 | rW_o <= rW_i; 136 | end 137 | else 138 | begin 139 | rW_o <= 31; // jal指令向$31写入PC 140 | end 141 | /* imm extension */ 142 | imm_ext_o <= imm_ext_i; 143 | 144 | /* jump identifier */ 145 | jal_o <= jal_i; 146 | 147 | /* rs rt */ 148 | rs_o <= rs_i; 149 | rt_o <= rt_i; 150 | 151 | /* control */ 152 | // EX // 153 | alu_src_o <= alu_src_i; 154 | alu_op_o <= alu_op_i; 155 | isjump_o <= isjump_i; 156 | 157 | // MEM // 158 | mode_o <= mode_i; 159 | data_w_o <= data_w_i; 160 | data_r_o <= data_r_i; 161 | mem_reg_o <= mem_reg_i; 162 | is_jump_inst_o <= is_jump_inst_i; 163 | 164 | // WB // 165 | if(jal_en_i == `jal_disable) 166 | begin 167 | reg_we_o <= reg_we_i; 168 | end 169 | else 170 | begin 171 | reg_we_o <= jal_en_i; 172 | end 173 | jal_en_o <= jal_en_i; 174 | end 175 | // id_ex_w_i的优先级比clear_i优先级高 176 | // 如果 不允许写入，【不管是否clear】，都保持原状（配合load全流水暂停） 177 | // 如果允许写入，并且clear有效，则clear，以下就是这种情况 178 | // insert nop instruction 179 | else if(id_ex_w_i == `id_ex_write_enable && clear_i == `clear_enable) 180 | begin 181 | /* control */ 182 | // EX // 183 | alu_src_o <= `B_calculate; 184 | alu_op_o <= `other_alu_op; 185 | 186 | // MEM // 187 | mode_o <= `byte_mode; 188 | data_w_o <= `data_w_disable; 189 | data_r_o <= `data_r_disable; 190 | mem_reg_o <= `data_from_reg; 191 | // 此信号在clear时候依然正常传递，保证 192 | // jump冒险时候，第二拍能够正常暂停 193 | is_jump_inst_o <= is_jump_inst_i; // NOTE! 194 | 195 | // clear代表向ID/EX插入了nop，说明存在load_jump冒险，只有在最后一个 196 | // 周期的时候，isjump_i的值才稳定下来，之前不能写入，稳定的时候不clear了 197 | // isjump_o <= isjump_i; // clear有效的时候不写入，是否跳转悬而未决 198 | 199 | // WB // 200 | reg_we_o <= `reg_write_disable; 201 | jal_en_o <= `jal_disable; 202 | end 203 | else 204 | begin 205 | ; 206 | end 207 | end 208 | 209 | endmodule 210 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/IF/fast_start_transition.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/04 17:01:40 7 | // Design Name: 8 | // Module Name: fast_start_transition 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: mode_convert切换到PREPARE_OPEN状态之后还需要等待2个周期，插入两个nop 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module fast_start_transition( 24 | input wire clk, 25 | input wire rst_n, 26 | 27 | input wire fast_mode_start_i, 28 | 29 | output reg if_id_clear_o 30 | ); 31 | 32 | localparam WAIT = 3'b001; // 等待Fast Mode启动 33 | localparam INSERT_NOP = 3'b010; // 插入nop 34 | localparam WAIT_RECOVREY = 3'b100; // 等待Normal Mode，恢复到WAIT状态 35 | reg [2:0] state; 36 | 37 | always@(posedge clk or posedge rst_n) 38 | begin 39 | if (rst_n == `rst_enable) 40 | begin 41 | if_id_clear_o <= `clear_disable; 42 | state <= WAIT; 43 | end 44 | else 45 | begin 46 | case(state) 47 | WAIT: 48 | begin 49 | if(fast_mode_start_i == `fast_mode) 50 | begin 51 | if_id_clear_o <= `clear_enable; 52 | state <= INSERT_NOP; 53 | end 54 | else 55 | begin 56 | if_id_clear_o <= `clear_disable; 57 | state <= WAIT; 58 | end 59 | end 60 | 61 | INSERT_NOP: 62 | begin 63 | if_id_clear_o <= `clear_enable; 64 | state <= WAIT_RECOVREY; 65 | end 66 | 67 | WAIT_RECOVREY: 68 | begin 69 | if(fast_mode_start_i == `normal_mode) 70 | begin 71 | state <= WAIT; 72 | end 73 | else 74 | begin 75 | if_id_clear_o <= `clear_disable; 76 | end 77 | end 78 | endcase 79 | end 80 | end 81 | 82 | endmodule 83 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/IF/inst_i_ctl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/04 23:32:47 7 | // Design Name: 8 | // Module Name: inst_i_ctl 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: Fast Mode下的指令输入处理逻辑 13 | // 核心：保证PC + 4和inst(pc)上下的一一对应的 14 | // 1. 当跳转指令成立，对读入的延迟槽之后的指令置nop 15 | // 2. 当pc不允许写入，暂存当前指令并输出暂存指令 16 | // 直到pc允许写入，输出读取到的指令（状态机） 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | ////////////////////////////////////////////////////////////////////////////////// 24 | 25 | `include "../define.v" 26 | module inst_i_ctl( 27 | input wire clk, 28 | input wire rst_n, 29 | 30 | input wire id_ex_isjump_i, 31 | input wire [31:0] inst_i, 32 | input wire pc_w_i, 33 | 34 | input wire fast_mode_start_i, 35 | 36 | output reg [31:0] inst_to_ifid_o 37 | ); 38 | 39 | localparam USE_DRAM_INST = 2'b01; // 正常状态，使用来自dram的指令 40 | localparam USE_INST_BUFFER = 2'b10; // PC禁止写导致暂时使用指令缓存 41 | reg [1:0] state; 42 | reg [31:0] inst_buffer; // 暂存指令 43 | 44 | always@(posedge clk or posedge rst_n) 45 | begin 46 | if (rst_n == `rst_enable) 47 | begin 48 | inst_buffer <= 0; 49 | state <= USE_DRAM_INST; 50 | end 51 | else if(fast_mode_start_i == `fast_mode) 52 | begin 53 | case(state) 54 | USE_DRAM_INST: 55 | begin 56 | if(!pc_w_i) // pc write disable 57 | begin 58 | inst_buffer <= inst_i; // save instruction 59 | state <= USE_INST_BUFFER; 60 | end 61 | end 62 | 63 | USE_INST_BUFFER: 64 | begin 65 | if(pc_w_i) 66 | begin 67 | state <= USE_DRAM_INST; 68 | end 69 | end 70 | endcase 71 | end 72 | end 73 | 74 | 75 | // get instruction 76 | always@(*) 77 | begin 78 | if(rst_n == `rst_enable) 79 | begin 80 | inst_to_ifid_o <= 0; 81 | end 82 | else if(fast_mode_start_i == `fast_mode) 83 | begin 84 | if(id_ex_isjump_i == `jump_enable) 85 | begin 86 | inst_to_ifid_o <= 0; 87 | end 88 | else if(state == USE_INST_BUFFER) 89 | begin 90 | inst_to_ifid_o <= inst_buffer; 91 | end 92 | else 93 | begin 94 | inst_to_ifid_o <= inst_i; 95 | end 96 | end 97 | else // normal mode 98 | begin 99 | inst_to_ifid_o <= inst_i; 100 | end 101 | end 102 | 103 | 104 | // (id_ex_isjump_i == `jump_enable && fast_mode_start_i == `fast_mode) ? 105 | // 32'h0000_0000 : inst_i; 106 | 107 | 108 | endmodule 109 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/IF/pc.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/06/22 14:35:32 7 | // Design Name: 8 | // Module Name: pc 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "../define.v" 24 | 25 | module pc( 26 | input wire clk, 27 | input wire rst_n, 28 | 29 | input wire [31:0] pc_i, 30 | input wire pc_w_i, 31 | 32 | (*mark_debug = "true"*)output reg [31:0] pc_o 33 | ); 34 | 35 | // reg pc_ce; 36 | 37 | // // reset pc? 38 | // always@(*) 39 | // begin 40 | // if(rst_n == `rst_enable) 41 | // pc_ce = `pc_disable; 42 | // else 43 | // pc_ce = `pc_enable; 44 | // end 45 | 46 | // // change: the value of pc 47 | // always@(posedge clk) 48 | // begin 49 | // if(pc_ce == `pc_enable) 50 | // pc_o <= pc_i; 51 | // else 52 | // pc_o <= `initial_pc; 53 | // end 54 | 55 | always @(posedge clk or posedge rst_n) 56 | begin 57 | if(rst_n == `rst_enable) 58 | begin 59 | pc_o <= `initial_pc; 60 | end 61 | else if(pc_w_i == `pc_write_enable) 62 | begin 63 | pc_o <= pc_i; 64 | end 65 | else 66 | begin 67 | ; // keep current pc value constant 68 | end 69 | end 70 | 71 | endmodule 72 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/IF/pc_stall.v: -------------------------------------------------------------------------------- 1 | // `timescale 1ns / 1ps 2 | // ////////////////////////////////////////////////////////////////////////////////// 3 | // // Company: 4 | // // Engineer: 5 | // // 6 | // // Create Date: 2021/07/27 18:48:21 7 | // // Design Name: 8 | // // Module Name: pc_stall 9 | // // Project Name: 10 | // // Target Devices: 11 | // // Tool Versions: 12 | // // Description: 13 | // // 14 | // // Dependencies: 15 | // // 16 | // // Revision: 17 | // // Revision 0.01 - File Created 18 | // // Additional Comments: 19 | // // 20 | // ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module pc_stall( 24 | input wire fast_mode_start_i, 25 | 26 | input wire inst_r_finish_i, 27 | input wire baseram_w_finish_i, 28 | 29 | output reg pc_w_o, 30 | output reg if_id_clear_o 31 | ); 32 | 33 | always@(*) 34 | begin 35 | if(fast_mode_start_i == `normal_mode) 36 | begin 37 | if(baseram_w_finish_i == `inst_write_unfinish) 38 | begin 39 | pc_w_o <= `pc_disable; 40 | if_id_clear_o <= `clear_enable; 41 | end 42 | else if(inst_r_finish_i == `inst_read_unfinish) 43 | begin 44 | pc_w_o <= `pc_enable; 45 | if_id_clear_o <= `clear_enable; // clear IF/ID inst -- nop 46 | end 47 | else 48 | begin 49 | pc_w_o <= `pc_disable; 50 | if_id_clear_o <= `clear_disable; 51 | end 52 | end 53 | else // fast mode 情况下 54 | begin 55 | pc_w_o <= `pc_enable; 56 | if_id_clear_o <= `clear_disable; 57 | end 58 | end 59 | 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/IF_ID.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/06 09:05:01 7 | // Design Name: 8 | // Module Name: IF_ID 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "define.v" 23 | 24 | module IF_ID( 25 | input wire clk, 26 | input wire rst_n, 27 | 28 | input wire if_id_w_i, 29 | input wire if_id_clear_i, 30 | 31 | input wire [31:0] inst_i, 32 | input wire [31:0] pc_i, 33 | 34 | (*mark_debug = "true"*)output reg [31:0] inst_o, 35 | output reg [31:0] pc_o 36 | ); 37 | 38 | always@(posedge clk or posedge rst_n) 39 | begin 40 | if(rst_n == `rst_enable) 41 | begin 42 | inst_o <= 32'b0; 43 | pc_o <= 32'b0; 44 | end 45 | else if(if_id_w_i == `if_id_write_enable && 46 | if_id_clear_i == `clear_disable) 47 | begin 48 | inst_o <= inst_i; 49 | pc_o <= pc_i; 50 | end // clear 优先级 比 write 低 51 | else if(if_id_w_i == `if_id_write_enable && 52 | if_id_clear_i == `clear_enable) 53 | begin 54 | inst_o <= 32'h0000_0000; // insert nop 55 | end 56 | else 57 | begin 58 | ; 59 | end 60 | end 61 | 62 | endmodule 63 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/MEM/data_hazard_lwsw.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/15 18:49:55 7 | // Design Name: 8 | // Module Name: data_hazard_lwsw 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 解决 lw/lb $1,($2) sw/sb $1,($3) 数据冒险问题 13 | // 需要唯一地识别出 lw在WB阶段 && sw在MEM阶段 14 | // 特征：lw:data_r enable; sw:data_w enable 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | `include "../define.v" 24 | 25 | module data_hazard_lwsw( 26 | // for sw instruction in EX stage 27 | input wire [4:0] ex_mem_rd_i, // store rt field (source) 28 | input wire ex_mem_data_w_i, // sw/sb data write enable 29 | 30 | // for lw instruction in MEM stage 31 | input wire [4:0] mem_wb_rd_i, // load rt field (dentisnan) 32 | input wire mem_wb_data_r_i, // lw/lb read data enable 33 | 34 | // output 35 | output reg bypass_mem_data_o 36 | ); 37 | 38 | always@(*) 39 | begin 40 | if( 41 | (mem_wb_rd_i != `zero_register) && 42 | (ex_mem_data_w_i == `data_w_enable) && 43 | (mem_wb_data_r_i == `data_r_enable) && 44 | (ex_mem_rd_i == mem_wb_rd_i) 45 | ) 46 | begin 47 | bypass_mem_data_o <= `mem_data_from_mem_wb; 48 | end 49 | else 50 | begin 51 | bypass_mem_data_o <= `mem_data_from_ex_mem; 52 | end 53 | end 54 | 55 | endmodule 56 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/MEM/loaddata_stall.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/27 11:57:32 7 | // Design Name: 8 | // Module Name: loaddata_stall 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 当load指令处于MEM的时候，整个流水线暂停一拍，等待数据从SRAM读出 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module loaddata_stall( 24 | // input wire clk, 25 | // input wire rst_n, 26 | 27 | input wire ex_mem_data_r_i, 28 | input wire data_r_finish_i, 29 | input wire [31:0] data_addr_i, 30 | 31 | output reg pc_w_o, 32 | output reg if_id_w_o, 33 | output reg id_ex_w_o, 34 | output reg ex_mem_w_o, 35 | output reg mem_wb_w_o 36 | ); 37 | 38 | 39 | 40 | // 如果是load指令，且不读串口，不读加速器，则需要暂停，直到read_finish_enable 41 | wire load_stall = 42 | (ex_mem_data_r_i == `data_r_enable) && 43 | (data_addr_i[31:24] != 8'hBF) && 44 | (data_addr_i[31:24] != 8'hFF); 45 | 46 | always@(*) 47 | begin 48 | if(load_stall && data_r_finish_i == `data_read_unfinish) 49 | begin 50 | pc_w_o <= `pc_write_disable; 51 | if_id_w_o <= `if_id_write_disable; 52 | id_ex_w_o <= `id_ex_write_disable; 53 | ex_mem_w_o <= `ex_mem_write_disable; 54 | mem_wb_w_o <= `mem_wb_write_disable; 55 | end 56 | else // if((load_stall && data_r_finish_i == `data_read_finish)) 57 | begin 58 | pc_w_o <= `pc_write_enable; 59 | if_id_w_o <= `if_id_write_enable; 60 | id_ex_w_o <= `id_ex_write_enable; 61 | ex_mem_w_o <= `ex_mem_write_enable; 62 | mem_wb_w_o <= `mem_wb_write_enable; 63 | end 64 | end 65 | 66 | endmodule 67 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/MEM/r_w_instram_stall.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/24 22:48:28 7 | // Design Name: 8 | // Module Name: r_w_instram_stall 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 当 CPU 向 base_inst RAM 读/写 数据的时候 13 | // 的流水线暂停逻辑 14 | // 启动Fast Mode之后，就不需要暂停了 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | 23 | ////////////////////////////////////// 24 | // 不能弃用的啊....... 25 | ////////////////////////////////////// 26 | `include "../define.v" 27 | module r_w_instram_stall( 28 | input wire fast_mode_start_i, 29 | 30 | input wire ex_mem_data_w_i, 31 | input wire ex_mem_data_r_i, 32 | input wire [31:0] data_addr_i, 33 | 34 | output wire pc_w_o, 35 | output wire if_id_w_o, 36 | output wire clear_o 37 | ); 38 | 39 | // Normal Mode下，为1则说明数据会读/写到instRAM 40 | // Fast Mode下不暂停 41 | wire is_data_to_inst_ram = (fast_mode_start_i == `normal_mode)? 42 | (data_addr_i[31:22] == 10'b1000_0000_00 && ex_mem_data_r_i) : 43 | 0; 44 | // (ex_mem_data_w_i || ex_mem_data_r_i); 45 | 46 | assign pc_w_o = !is_data_to_inst_ram; 47 | assign if_id_w_o = !is_data_to_inst_ram; 48 | assign clear_o = is_data_to_inst_ram; 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/MEM/sw_stall.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/03 13:22:54 7 | // Design Name: 8 | // Module Name: sw_stall 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 当启动Fast Mode之后，遇到连续store（非串口）需要暂停逻辑 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../define.v" 23 | module sw_stall( 24 | input wire id_ex_w_i, 25 | input wire [31:0] id_ex_data_addr_i, 26 | 27 | input wire if_id_w_i, 28 | 29 | input wire fast_mode_start_i, 30 | 31 | output reg pc_w_o, 32 | output reg if_id_w_o, 33 | output reg clear_o 34 | ); 35 | 36 | // 为1，说明EX stage的sw的不是写串口，不写加速器，且ID，EX均为store指令 37 | // 需要向中间插入nop 38 | wire stall_sw = if_id_w_i && id_ex_w_i && 39 | (id_ex_data_addr_i[31:24] != 8'hBF) && 40 | (id_ex_data_addr_i[31:24] != 8'hFF); 41 | 42 | always@(*) 43 | begin 44 | if(fast_mode_start_i == `fast_mode) 45 | begin 46 | if(stall_sw) 47 | begin 48 | pc_w_o <= `pc_write_disable; 49 | if_id_w_o <= `if_id_write_disable; 50 | clear_o <= `clear_enable; 51 | end 52 | else 53 | begin 54 | pc_w_o <= `pc_write_enable; 55 | if_id_w_o <= `if_id_write_enable; 56 | clear_o <= `clear_disable; 57 | end 58 | end 59 | else // normal mode下不会暂停 60 | begin 61 | pc_w_o <= `pc_write_enable; 62 | if_id_w_o <= `if_id_write_enable; 63 | clear_o <= `clear_disable; 64 | end 65 | end 66 | 67 | endmodule 68 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/MEM_WB.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/06 09:05:58 7 | // Design Name: 8 | // Module Name: MEM_WB 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | 23 | `include "define.v" 24 | 25 | module MEM_WB( 26 | input wire clk, 27 | input wire rst_n, 28 | input wire mem_wb_w_i, 29 | 30 | input wire [31:0] data_result_i, 31 | (*mark_debug = "true"*)output reg [31:0] data_result_o, 32 | 33 | input wire [4:0] rW_i, 34 | (*mark_debug = "true"*)output reg [4:0] rW_o, 35 | 36 | /* jump identifier */ 37 | input wire [31:0] jal_i, 38 | output reg [31:0] jal_o, 39 | 40 | /* control */ 41 | // MEM // for data hazard 42 | input wire data_r_i, 43 | output reg data_r_o, 44 | 45 | // WB // 46 | input reg_we_i, 47 | input wire jal_en_i, 48 | (*mark_debug = "true"*)output reg reg_we_o, 49 | output reg jal_en_o 50 | ); 51 | 52 | always@(posedge clk or posedge rst_n) 53 | begin 54 | if(rst_n == `rst_enable) 55 | begin 56 | data_result_o <= 0; 57 | rW_o <= 0; 58 | 59 | /* jump identifier */ 60 | jal_o <= 0; 61 | 62 | /* control */ 63 | // MEM // for data hazard 64 | data_r_o <= `data_r_disable; 65 | 66 | // WB // 67 | reg_we_o <= `reg_write_disable; 68 | jal_en_o <= `jal_disable; 69 | end 70 | else if(mem_wb_w_i == `mem_wb_write_enable) 71 | begin 72 | data_result_o <= data_result_i; 73 | rW_o <= rW_i; 74 | 75 | /* jump identifier */ 76 | jal_o <= jal_i; 77 | 78 | /* control */ 79 | // MEM // for data hazard 80 | data_r_o <= data_r_i; 81 | 82 | // WB // 83 | reg_we_o <= reg_we_i; 84 | jal_en_o <= jal_en_i; 85 | end 86 | else 87 | begin 88 | ; 89 | end 90 | end 91 | 92 | endmodule 93 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/SEG7_LUT.v: -------------------------------------------------------------------------------- 1 | module SEG7_LUT ( oSEG1,iDIG ); 2 | input wire[3:0] iDIG; // 4位二进制，能够表示数字 0 ~ F 3 | output wire[7:0] oSEG1; // 能够通过7段数码管，显示A-F，小数点恒不亮 4 | reg [6:0] oSEG; 5 | 6 | always @(iDIG) 7 | begin 8 | case(iDIG) 9 | 4'h1: // gfabedc // if (bit value= 0), A digital tube will be lightened. 10 | oSEG = 7'b1110110; // ---t---- // rt rb lighten, show '1' 11 | 4'h2: 12 | oSEG = 7'b0100001; // | | // show '2' 13 | 4'h3: 14 | oSEG = 7'b0100100; // lt rt // '3' 15 | 4'h4: 16 | oSEG = 7'b0010110; // | | // '4' 17 | 4'h5: 18 | oSEG = 7'b0001100; // ---m---- // '5' 19 | 4'h6: 20 | oSEG = 7'b0001000; // | | // '6' 21 | 4'h7: 22 | oSEG = 7'b1100110; // lb rb 23 | 4'h8: 24 | oSEG = 7'b0000000; // | | 25 | 4'h9: 26 | oSEG = 7'b0000110; // ---b---- 27 | 4'ha: 28 | oSEG = 7'b0000010; // 'A' 29 | 4'hb: 30 | oSEG = 7'b0011000; 31 | 4'hc: 32 | oSEG = 7'b1001001; 33 | 4'hd: 34 | oSEG = 7'b0110000; 35 | 4'he: 36 | oSEG = 7'b0001001; 37 | 4'hf: 38 | oSEG = 7'b0001011; // 'F' 39 | 4'h0: 40 | oSEG = 7'b1000000; // '0' 41 | endcase 42 | end 43 | 44 | assign oSEG1 = {~oSEG,1'b0}; // 此处小数点永远不会亮 45 | 46 | endmodule 47 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/UART/uart_buffer.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/22 13:09:03 7 | // Design Name: 8 | // Module Name: uart_buffer 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 用于存储串口数据，以及串口状态 13 | // 属于数据内存空间 14 | // 【输入的地址范围】0xBFD0_03F8 - 0xBFD0_03FD 15 | // 假定该模块接收到的地址，就是符合范围的32位地址，其他的事情交给地址仲裁模块 16 | // 17 | // 0xBFD0_03F8 - 0xBFD0_03FD <=映射=> 0x0 - 0x7 18 | // Dependencies: 19 | // 20 | // Revision: 21 | // Revision 0.01 - File Created 22 | // Additional Comments: 23 | // 24 | ////////////////////////////////////////////////////////////////////////////////// 25 | 26 | // 其实这个类似于reg files 27 | `include "../define.v" 28 | module uart_buffer( 29 | input wire clk, 30 | input wire rst_n, 31 | 32 | // 为0时，锁死buffer数据，禁止任何写入，同时禁止开启发送器 33 | input wire trans_enable_i, 34 | 35 | // from cpu 36 | (*mark_debug = "true"*)input wire [31:0] uart_addr_i, 37 | (*mark_debug = "true"*)input wire [31:0] uart_data_i, 38 | (*mark_debug = "true"*)input wire uart_data_r_i, // read data,high level active 39 | (*mark_debug = "true"*)input wire uart_data_w_i, 40 | 41 | // from receiver 42 | input wire [7:0] r_data_i, // receiver's data 43 | input wire r_data_w_i, // ready = 1 => can write 44 | 45 | // to transmitter 46 | (*mark_debug = "true"*)input wire TxD_busy_i, 47 | (*mark_debug = "true"*)output reg TxD_start_o, 48 | (*mark_debug = "true"*)output wire [7:0] TxD_data_o, 49 | 50 | // to cpu 51 | (*mark_debug = "true"*)output wire [31:0] buffer_data_o 52 | ); 53 | 54 | 55 | // transform address 56 | /// 0xBFD0_03F8 - 0xBFD0_03FD <=映射=> [0] - [1] 57 | wire addr; 58 | assign addr = uart_addr_i[2]; // 8 -- 0 ; C -- 1 59 | 60 | 61 | ////// 以下三个数据的读写逻辑，应该与SRAM一致，都是下降沿进行读/写 62 | // data buffer 63 | (*mark_debug = "true"*)reg [7:0] serial_data; 64 | // status 65 | (*mark_debug = "true"*)reg idle; // 0xBFD0_03FC[0]; 1 --> idle 66 | (*mark_debug = "true"*)reg avai; // 0xBFD0_03FC[1]; 1 --> receive data 67 | ////////// 68 | 69 | 70 | // 不同的信号在不同的逻辑下做不同的事情，因此每个信号分开写！ 71 | 72 | 73 | ////////////////////////////////////////////// 74 | // 在阻止0x06发送期间，还应该锁定0x06，暂时没加 75 | ////////////////////////////////////////////// 76 | 77 | 78 | // write avai and serial_data 内部数据 79 | always@(negedge clk) 80 | begin 81 | if(rst_n == `rst_enable) 82 | begin 83 | serial_data <= 0; 84 | avai <= `uart_data_avai_disable; 85 | end 86 | // receiver to buffer 87 | else if(r_data_w_i == `r_data_write_enable && idle == `uart_data_idle) 88 | begin 89 | avai <= `uart_data_avai_enable; 90 | serial_data <= r_data_i; 91 | end 92 | // CPU to buffer idle的检测通过软件（指令序列），能写就说明idle_enable 93 | else if(uart_data_w_i == `uart_data_write_enable) 94 | begin 95 | avai <= `uart_data_avai_enable; 96 | serial_data <= uart_data_i[7:0]; 97 | end 98 | // CPU read data from buffer, and clear avai status bit 99 | else if(uart_data_r_i == `uart_data_read_enable && addr == `cpu_read_serial_data) 100 | begin 101 | avai <= `uart_data_avai_disable; 102 | end 103 | end 104 | 105 | 106 | // write idle 内部数据 107 | always@(negedge clk) 108 | begin 109 | if(rst_n == `rst_enable) 110 | begin 111 | idle <= `uart_data_idle; 112 | end 113 | else if(uart_data_w_i == `uart_data_write_enable || TxD_busy_i || TxD_start_o) 114 | begin 115 | idle <= `uart_data_busy; // buffer的busy是0，发送器的busy是1. 116 | end 117 | else 118 | begin 119 | idle <= `uart_data_idle; 120 | end 121 | end 122 | 123 | localparam DATA_W_START = 2'b01; // uart_data_w_i导致启动发送器 124 | localparam TRANS_START = 2'b10; // trans_enable_i导致启动发送器 125 | reg [1:0] state; 126 | 127 | // 处理start 128 | always@(posedge clk or posedge rst_n) 129 | begin 130 | if(rst_n == `rst_enable) 131 | begin 132 | TxD_start_o <= `t_start_disable; 133 | state <= DATA_W_START; 134 | end 135 | else if(trans_enable_i == `transmitter_enable) 136 | begin 137 | // 一般状态下启动发送器 138 | if(uart_data_w_i == `uart_data_write_enable && state == DATA_W_START) 139 | begin 140 | TxD_start_o <= `t_start_enable; 141 | end 142 | else if(state == TRANS_START) // 被模式切换机禁止后启动start 143 | begin 144 | TxD_start_o <= `t_start_enable; 145 | state <= DATA_W_START; 146 | end 147 | else 148 | begin 149 | TxD_start_o <= `t_start_disable; 150 | end 151 | end 152 | else if(trans_enable_i == `transmitter_disable) 153 | begin 154 | state <= TRANS_START; 155 | end 156 | end 157 | 158 | // assign TxD_start_o = !idle; // 注意是start --启动--> busy 159 | assign TxD_data_o = serial_data; 160 | 161 | // read data from buffer 162 | assign buffer_data_o = 163 | // avai的检测通过软件，能读就说明avai_enable了 164 | (uart_data_r_i == `uart_data_read_enable)? 165 | ( 166 | (addr == `cpu_read_serial_data) ? 167 | {{24{serial_data[7]}}, serial_data}: //读串口数据 168 | {30'h0, avai, idle} // 读串口状态 169 | ) 170 | :0; // 数据读取失败 171 | 172 | 173 | 174 | // // data buffer 175 | // reg [7:0] serial_memory[7:0]; // 多余2个是为了凑2的倍数8 176 | 177 | 178 | // // write logic 179 | // // 如果CPU和接收器同时准备好数据，又同时写入 180 | // // 按当前逻辑，接收器会优先写入，CPU写的数据会丢失 181 | // reg TxD_start_o_1; 182 | // always@(posedge clk) 183 | // begin 184 | // if(rst_n == `rst_enable) 185 | // begin 186 | // serial_memory[0] <= 0; // serial port data 187 | // serial_memory[1] <= 0; 188 | // serial_memory[2] <= 0; 189 | // serial_memory[3] <= 0; 190 | // //serial_memory[4] <= 1; // status bit; NOTE！[0] = 1 -- idle 191 | // serial_memory[5] <= 0; 192 | // serial_memory[6] <= 0; 193 | // serial_memory[7] <= 0; 194 | // TxD_start_o_1 <= `t_start_disable; 195 | // end 196 | // // receiver write data 197 | // // 如果写之前是avai_enable，则之前的数据会被新的帧覆盖 198 | // else if(r_data_w_i == `r_data_write_enable && !TxD_busy_i) 199 | // begin 200 | // serial_memory[0] <= r_data_i; 201 | // serial_memory[4][1] <= `uart_data_avai_enable; // 收到数据 202 | // //serial_memory[4][0] <= `uart_data_idle; // 串口空闲 203 | // TxD_start_o_1 <= `t_start_disable; 204 | // end 205 | // // CPU write data（之前通过状态位确定“空闲”）了 206 | // else if(uart_data_w_i == `uart_data_write_enable) 207 | // begin 208 | // serial_memory[0] <= uart_data_i[7:0]; 209 | // serial_memory[4][1] <= `uart_data_avai_disable; // 不是串口发过来的，不可用 210 | // //serial_memory[4][0] <= `uart_data_busy; // 串口忙碌 211 | // TxD_start_o_1 <= `t_start_enable; // 发送器开始工作 212 | // end 213 | // else if(uart_data_r_i == `uart_data_read_enable) // 不能和下降沿读取写一起，会导致多驱动 214 | // begin 215 | // serial_memory[4][1] <= `uart_data_avai_disable; // clear 216 | // end 217 | // else if(!TxD_busy_i) 218 | // begin 219 | // TxD_start_o_1 <= `t_start_disable; 220 | // //serial_memory[4][0] <= `uart_data_idle; // 串口空闲 221 | // end 222 | // end 223 | 224 | 225 | // // // 二级流水，使得start晚一个周期出现，保证数据准备好 226 | // // always@(posedge clk) 227 | // // begin 228 | // // TxD_start_o <= TxD_start_o_1; 229 | // // end 230 | 231 | // assign TxD_start_o = TxD_start_o_1; 232 | 233 | 234 | // // 针对串口忙碌状态的处理 235 | // always@(posedge clk) 236 | // begin 237 | // if(rst_n == `rst_enable) 238 | // begin 239 | // serial_memory[4][0] <= `uart_data_idle; 240 | // end 241 | // else if(uart_data_w_i == `uart_data_write_enable || TxD_busy_i || TxD_start_o_1) 242 | // begin 243 | // serial_memory[4][0] <= `uart_data_busy; 244 | // end 245 | // else 246 | // begin 247 | // serial_memory[4][0] <= `uart_data_idle; 248 | // end 249 | // end 250 | 251 | 252 | 253 | // // read logic 254 | // reg [7:0] temp_data; 255 | // always@(negedge clk) 256 | // begin 257 | // if(rst_n == `rst_enable) 258 | // begin 259 | // temp_data = 1; // idle 260 | // end 261 | // // CPU read data 262 | // else if(uart_data_r_i == `uart_data_read_enable) 263 | // begin 264 | // // read status 265 | // if(serial_addr == 4) 266 | // begin 267 | // temp_data <= serial_memory[4]; 268 | // end 269 | // // read data 270 | // else if(serial_addr == 0) 271 | // begin 272 | // temp_data <= serial_memory[0]; 273 | // end 274 | // end 275 | // end 276 | 277 | 278 | 279 | // // output cpu data (8 --> 32) sign extend 280 | // assign buffer_data_o = {{24{temp_data[7]}}, temp_data}; 281 | 282 | // assign TxD_data_o = serial_memory[0]; // transmitter data 283 | 284 | endmodule 285 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/mode_convert.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/02 20:50:44 7 | // Design Name: 8 | // Module Name: mode_convert 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: CPU运行模式切换，在执行G命令的时候进入 13 | // Fast Mode，流水线全速运行 14 | // Normal Mode <--> Fast Mode 15 | // Dependencies: 16 | // 17 | // Revision: 18 | // Revision 0.01 - File Created 19 | // Additional Comments: 20 | // 21 | ////////////////////////////////////////////////////////////////////////////////// 22 | `include "define.v" 23 | 24 | module mode_convert( 25 | input wire clk, 26 | input wire rst_n, 27 | 28 | // CLOSE状态，保存v0，写入v0的时候，就保存起来 29 | input wire [4:0] mem_wb_rW_i, 30 | input wire [31:0] mem_wb_wdata_i, 31 | input wire mem_wb_reg_w_i, 32 | 33 | // 识别0x06信号 34 | input wire [31:0] id_G_start_i, // 识别指令 ori a0,zero,TIMERSET(0x06) 35 | output reg [31:0] prgm_start_addr_o, // 程序起始地址，也就是v0 36 | output reg lock_addr_o,// 若收到0x06通知仲裁模块锁住v0地址 37 | 38 | 39 | // 识别串口写 40 | /// 0x06 EX stage 41 | input wire id_ex_data_w_i, // 应为1 42 | input wire [31:0] id_ex_data_addr_i, // 应为串口数据地址 43 | 44 | /// 0x07 MEM stage 45 | input wire ex_mem_data_w_i, // 应为1 46 | input wire [31:0] ex_mem_data_addr_i, // 应为串口数据地址 47 | 48 | output reg bram_w_start_o, // 为1，则即将执行的程序写入到bram中 49 | (*mark_debug = "true"*)output reg trans_enable_o, // 若为0，串口发送器不工作 50 | output reg stall_entire_cpu_o,// 为1，暂停整个CPU，所有寄存器写disable 51 | 52 | // 即将切换到Fast Mode 53 | input wire bram_w_finish_i, // 为1，写入bram完成 54 | (*mark_debug = "true"*)output reg fast_mode_start_o // 为1，切换到fast，为0则是noramlMode 55 | ); 56 | 57 | localparam CLOSE = 7'b0000_001; // 关闭fast 58 | localparam PREPARE_OPEN_G = 7'b0000_010; // 识别G命令 59 | localparam PREPARE_OPEN_INST = 7'b0000_100; // 准备写入指令到BRAM 60 | localparam PREPARE_OPEN = 7'b0001_000; // 写入完成后稳定期 61 | localparam OPEN = 7'b0010_000; // 开启Fast Mode 62 | localparam PREPARE_CLOSE = 7'b0100_000; // 识别0x07，准备关闭Fast Mode 63 | localparam PREPARE_CLOSE_2 = 7'b1000_000; // 过渡 64 | reg [6:0] state; // 若增加状态，别忘记修改位宽！ 65 | 66 | 67 | wire is_write_v0 = 68 | (mem_wb_reg_w_i == `reg_write_enable) && 69 | (mem_wb_rW_i == `reg_v0); // 为1代表即将写入到v0 70 | 71 | 72 | // 记录之前识别的信号，为了区分ID和MEM阶段识别到的sb指令 73 | localparam NO_SIGNAL = 2'b00; 74 | localparam SIGNAL_0x6 = 2'b01; 75 | localparam SIGNAL_0x7 = 2'b10; 76 | reg [1:0] current_signal; 77 | 78 | // 为1，则是准备0x06信号指令 79 | wire is_0x06 = (id_G_start_i == 32'h34040006); 80 | 81 | wire is_0x07 = (id_G_start_i == 32'h34040007); 82 | 83 | 84 | wire is_sb_serial_exstage = // 为1，则是写串口指令 0x06 85 | (id_ex_data_w_i == `data_w_enable) && 86 | (id_ex_data_addr_i[31:24] == 8'hBF) && 87 | (current_signal == SIGNAL_0x6); 88 | 89 | wire is_sb_serial_memstage = // 为1，则是写串口指令 0x07 90 | (ex_mem_data_w_i == `data_w_enable) && 91 | (ex_mem_data_addr_i[31:24] == 8'hBF) && 92 | (current_signal == SIGNAL_0x7); 93 | 94 | always @(posedge clk or posedge rst_n) 95 | begin 96 | if(rst_n == `rst_enable) 97 | begin 98 | state <= CLOSE; 99 | prgm_start_addr_o <= 32'h0000_0000; 100 | bram_w_start_o <= `bram_write_disable; 101 | trans_enable_o <= `transmitter_enable; 102 | fast_mode_start_o <= `normal_mode; 103 | lock_addr_o <= `lock_addr_disable; 104 | stall_entire_cpu_o <= `all_reg_w_enable; 105 | current_signal <= NO_SIGNAL; 106 | end 107 | else 108 | begin 109 | case(state) 110 | CLOSE: 111 | begin 112 | if(is_write_v0) 113 | begin 114 | prgm_start_addr_o <= mem_wb_wdata_i; 115 | state <= CLOSE; 116 | end 117 | else if(is_0x06) // 若识别到0x06启动信号 118 | begin 119 | lock_addr_o <= `lock_addr_enable; 120 | state <= PREPARE_OPEN_G; 121 | current_signal <= SIGNAL_0x6; 122 | end 123 | end 124 | 125 | PREPARE_OPEN_G: 126 | begin 127 | if(is_sb_serial_exstage) // 若写入0x06到串口buffer 128 | begin 129 | bram_w_start_o <= `bram_write_enable; 130 | trans_enable_o <= `transmitter_disable; 131 | // trans_enable_o <= `transmitter_enable; 132 | stall_entire_cpu_o <= `all_reg_w_disable; 133 | state <= PREPARE_OPEN_INST; 134 | current_signal <= NO_SIGNAL; 135 | end 136 | end 137 | 138 | PREPARE_OPEN_INST: 139 | begin 140 | if(bram_w_finish_i == `bram_write_finish) // BRAM写入完成 141 | begin 142 | fast_mode_start_o <= `fast_mode; 143 | 144 | bram_w_start_o <= `bram_write_disable; 145 | trans_enable_o <= `transmitter_enable; 146 | // stall_entire_cpu_o <= `all_reg_w_enable; 147 | 148 | state <= PREPARE_OPEN; 149 | end 150 | end 151 | 152 | PREPARE_OPEN: // 刚进入Fast Mode的过渡期 153 | begin 154 | stall_entire_cpu_o <= `all_reg_w_enable; 155 | 156 | state <= OPEN; 157 | end 158 | 159 | OPEN: 160 | begin 161 | if(is_0x07) 162 | begin 163 | current_signal <= SIGNAL_0x7; 164 | 165 | state <= PREPARE_CLOSE; 166 | end 167 | end 168 | 169 | PREPARE_CLOSE: 170 | begin 171 | if(is_sb_serial_memstage) 172 | begin 173 | lock_addr_o <= `lock_addr_disable; 174 | // fast_mode_start_o <= `normal_mode; 175 | 176 | current_signal <= NO_SIGNAL; 177 | 178 | state <= PREPARE_CLOSE_2; 179 | end 180 | end 181 | 182 | PREPARE_CLOSE_2: 183 | begin 184 | fast_mode_start_o <= `normal_mode; 185 | state <= CLOSE; 186 | end 187 | endcase 188 | end 189 | end 190 | 191 | 192 | endmodule 193 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/sram_ctl.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/07/28 16:52:25 7 | // Design Name: 8 | // Module Name: sram_ctl 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: SRAM控制器，能够控制baseRAM和extRAM 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "define.v" 23 | module sram_ctl( 24 | input wire clk, 25 | input wire rst_n, 26 | 27 | // from CPU IF stage 28 | // input wire [1:0] base_mode_i, 29 | input wire [3:0] data_sel_i, 30 | 31 | input wire data_w_i, // 写使能，高有效 32 | input wire data_r_i, // 读使能，高有效 33 | input wire data_ce_i, // 芯片使能，高有效，留有端口但是内部不使用 34 | 35 | input wire [31:0] data_addr_i, 36 | (*mark_debug = "true"*)input wire [31:0] data_i, 37 | (*mark_debug = "true"*)output wire [31:0] data_o, 38 | 39 | 40 | // signal to cpu active-high 41 | output reg sram_ctl_busy_o, 42 | output reg data_r_finish_o, 43 | output reg data_w_finish_o, 44 | 45 | 46 | // from Base RAM, inst RAM 47 | inout wire[31:0] sram_data, //BaseRAM数据，低8位与CPLD串口控制器共享，暂时恒输出 48 | 49 | output reg [19:0] sram_addr, //BaseRAM地址 50 | output reg [3:0] sram_be_n, //BaseRAM字节使能，低有效。如果不使用字节使能，请保持为0 51 | output reg sram_ce_n, //BaseRAM片选，低有效 52 | output reg sram_oe_n, //BaseRAM读使能，低有效 53 | output reg sram_we_n //BaseRAM写使能，低有效 54 | ); 55 | 56 | // FSM state 独热码 57 | localparam IDLE = 3'b001; 58 | localparam READ = 3'b010; 59 | localparam WRITE = 3'b100; 60 | 61 | // tristate. if(W_ENBALE) inout --> output,write data to SRAM 62 | localparam W_ENABLE = 2'b01; 63 | localparam W_DISABLE = 2'b10; // rear data from SRAM 64 | 65 | reg [2:0] current_state; 66 | reg [31:0] data_from_SRAM; 67 | reg [31:0] data_to_SRAM; 68 | reg [1:0] tristate; 69 | 70 | 71 | // initial 72 | // begin 73 | // // cpu 74 | // sram_ctl_busy_o <= `sram_idle; 75 | // data_r_finish_o <= `data_read_unfinish; 76 | // // 写入完成，意味着当前没有数据被写入，平时就是这个状态！ 77 | // // 还有成功写入数据之后，也会从unfinish进入finish状态 78 | // data_w_finish_o <= `data_write_finish; // NOTE 79 | 80 | // // base ram 81 | // sram_addr <= 0; 82 | // sram_be_n <= 0; 83 | // sram_ce_n <= 1; 84 | // sram_oe_n <= 1; 85 | // sram_we_n <= 1; 86 | 87 | // // internal data 88 | // current_state <= IDLE; 89 | // data_from_SRAM <= 32'h0000_0000; 90 | // data_to_SRAM <= 32'h0000_0000; 91 | // tristate <= W_DISABLE; 92 | // end 93 | 94 | always @(posedge clk or posedge rst_n) 95 | begin 96 | if(rst_n == `rst_enable) 97 | begin 98 | // cpu 99 | sram_ctl_busy_o <= `sram_idle; 100 | data_r_finish_o <= `data_read_unfinish; 101 | // 写入完成，意味着当前没有数据被写入，平时就是这个状态！ 102 | // 还有成功写入数据之后，也会从unfinish进入finish状态 103 | data_w_finish_o <= `data_write_finish; // NOTE 104 | 105 | // base ram 106 | sram_addr <= 0; 107 | sram_be_n <= 0; 108 | sram_ce_n <= 1; 109 | sram_oe_n <= 1; 110 | sram_we_n <= 1; 111 | 112 | // internal data 113 | current_state <= IDLE; 114 | data_from_SRAM <= 32'h0000_0000; 115 | data_to_SRAM <= 32'h0000_0000; 116 | tristate <= W_DISABLE; 117 | end 118 | else 119 | begin 120 | case (current_state) 121 | IDLE: 122 | begin 123 | // internal data 124 | tristate <= W_DISABLE; 125 | 126 | // cpu 127 | sram_ctl_busy_o <= `sram_idle; 128 | data_r_finish_o <= `data_read_unfinish; 129 | data_w_finish_o <= `data_write_finish; 130 | 131 | // base ram 132 | sram_ce_n <= 0; 133 | sram_oe_n <= 0; 134 | sram_we_n <= 1; 135 | // ########################################### 136 | // NOTE！与取指不同，取指一直连续读，关注不读的部分 137 | // 取数据只是偶尔取，数据准备好之后，data_read 138 | // 依然是高电平，需要上升沿之后才下降（进入MEM） 139 | // 这会导致ext控制器再一次读取，但实际上已经读完 140 | // 这会导致连续load出错！ 141 | // ########################################### 142 | if(data_r_i == `data_read_enable && data_r_finish_o == `data_read_unfinish) 143 | begin 144 | sram_be_n <= data_sel_i; 145 | sram_addr <= data_addr_i[21:2]; 146 | current_state <= READ; 147 | end 148 | else if(data_w_i == `data_write_enable) 149 | begin 150 | data_to_SRAM <= data_i; 151 | sram_be_n <= data_sel_i; 152 | sram_addr <= data_addr_i[21:2]; 153 | current_state <= WRITE; 154 | end 155 | else // not read and write 156 | begin 157 | sram_be_n <= 0; 158 | current_state <= IDLE; 159 | end 160 | end 161 | 162 | READ: 163 | begin 164 | data_from_SRAM <= sram_data; 165 | data_r_finish_o <= `data_read_finish; 166 | sram_ctl_busy_o <= `sram_busy; 167 | 168 | current_state <= IDLE; 169 | end 170 | 171 | WRITE: 172 | begin 173 | data_w_finish_o <= `data_write_unfinish; 174 | sram_we_n <= 0; 175 | sram_ctl_busy_o <= `sram_busy; 176 | 177 | current_state <= IDLE; 178 | tristate <= W_ENABLE; 179 | end 180 | endcase 181 | end 182 | end 183 | 184 | assign sram_data = 185 | (tristate == W_ENABLE)? 186 | data_to_SRAM : 32'hzzzz_zzzz; 187 | 188 | assign data_o = data_from_SRAM; 189 | 190 | endmodule 191 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/imports/new/vga.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | // 3 | // WIDTH: bits in register hdata & vdata 4 | // HSIZE: horizontal size of visible field 5 | // HFP: horizontal front of pulse 6 | // HSP: horizontal stop of pulse 7 | // HMAX: horizontal max size of value 8 | // VSIZE: vertical size of visible field 9 | // VFP: vertical front of pulse 10 | // VSP: vertical stop of pulse 11 | // VMAX: vertical max size of value 12 | // HSPP: horizontal synchro pulse polarity (0 - negative, 1 - positive) 13 | // VSPP: vertical synchro pulse polarity (0 - negative, 1 - positive) 14 | // 15 | module vga 16 | #(parameter WIDTH = 0, HSIZE = 0, HFP = 0, HSP = 0, HMAX = 0, VSIZE = 0, VFP = 0, VSP = 0, VMAX = 0, HSPP = 0, VSPP = 0) 17 | ( 18 | input wire clk, 19 | output wire hsync, 20 | output wire vsync, 21 | output reg [WIDTH - 1:0] hdata, 22 | output reg [WIDTH - 1:0] vdata, 23 | output wire data_enable 24 | ); 25 | 26 | // hdata 27 | always @ (posedge clk) 28 | begin 29 | if (hdata == (HMAX - 1)) 30 | hdata <= 0; 31 | else 32 | hdata <= hdata + 1; 33 | end 34 | 35 | // vdata 36 | always @ (posedge clk) 37 | begin 38 | if (hdata == (HMAX - 1)) 39 | begin 40 | if (vdata == (VMAX - 1)) 41 | vdata <= 0; 42 | else 43 | vdata <= vdata + 1; 44 | end 45 | end 46 | 47 | // hsync & vsync & blank 48 | assign hsync = ((hdata >= HFP) && (hdata < HSP)) ? HSPP : !HSPP; 49 | assign vsync = ((vdata >= VFP) && (vdata < VSP)) ? VSPP : !VSPP; 50 | assign data_enable = ((hdata < HSIZE) & (vdata < VSIZE)); 51 | 52 | endmodule -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/BRAM_Curing_inst.coe: -------------------------------------------------------------------------------- 1 | memory_initialization_radix = 16; 2 | memory_initialization_vector = 3 | 00000000, 4 | 0040d025, 5 | 3c1f807f, 6 | 27ff0000, 7 | afe20078, 8 | affd007c, 9 | 8fe10000, 10 | 8fe20004, 11 | 8fe30008, 12 | 8fe4000c, 13 | 8fe50010, 14 | 8fe60014, 15 | 8fe70018, 16 | 8fe8001c, 17 | 8fe90020, 18 | 8fea0024, 19 | 8feb0028, 20 | 8fec002c, 21 | 8fed0030, 22 | 8fee0034, 23 | 8fef0038, 24 | 8ff0003c, 25 | 8ff10040, 26 | 8ff20044, 27 | 8ff30048, 28 | 8ff4004c, 29 | 8ff50050, 30 | 8ff60054, 31 | 8ff70058, 32 | 8ff8005c, 33 | 8ff90060, 34 | 8ffc006c, 35 | 8ffd0070, 36 | 8ffe0074, 37 | 3c1f8000, 38 | 27ff231c, 39 | 00000000, 40 | 03400008, 41 | 00000000, 42 | 00000000, 43 | 3c1f807f, 44 | 27ff0000, 45 | afe10000, 46 | afe20004, 47 | afe30008, 48 | afe4000c, 49 | afe50010, 50 | afe60014, 51 | afe70018, 52 | afe8001c, 53 | afe90020, 54 | afea0024, 55 | afeb0028, 56 | afec002c, 57 | afed0030, 58 | afee0034, 59 | afef0038, 60 | aff0003c, 61 | aff10040, 62 | aff20044, 63 | aff30048, 64 | aff4004c, 65 | aff50050, 66 | aff60054, 67 | aff70058, 68 | aff8005c, 69 | aff90060, 70 | affc006c, 71 | affd0070, 72 | affe0074, 73 | 8ffd007c, 74 | 34040007, 75 | 0c0008ee, 76 | 00000000, 77 | 080008ec, 78 | 00000000, 79 | 08000850, 80 | 00000000, 81 | 3c09bfd0, 82 | 812803fc, 83 | 31080001, 84 | 15000003, 85 | 00000000, 86 | 080008ef, 87 | 00000000, 88 | 3c09bfd0, 89 | a12403f8, 90 | 03e00008, 91 | 00000000; -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0.mif: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000 2 | 00000000010000001101000000100101 3 | 00111100000111111000000001111111 4 | 00100111111111110000000000000000 5 | 10101111111000100000000001111000 6 | 10101111111111010000000001111100 7 | 10001111111000010000000000000000 8 | 10001111111000100000000000000100 9 | 10001111111000110000000000001000 10 | 10001111111001000000000000001100 11 | 10001111111001010000000000010000 12 | 10001111111001100000000000010100 13 | 10001111111001110000000000011000 14 | 10001111111010000000000000011100 15 | 10001111111010010000000000100000 16 | 10001111111010100000000000100100 17 | 10001111111010110000000000101000 18 | 10001111111011000000000000101100 19 | 10001111111011010000000000110000 20 | 10001111111011100000000000110100 21 | 10001111111011110000000000111000 22 | 10001111111100000000000000111100 23 | 10001111111100010000000001000000 24 | 10001111111100100000000001000100 25 | 10001111111100110000000001001000 26 | 10001111111101000000000001001100 27 | 10001111111101010000000001010000 28 | 10001111111101100000000001010100 29 | 10001111111101110000000001011000 30 | 10001111111110000000000001011100 31 | 10001111111110010000000001100000 32 | 10001111111111000000000001101100 33 | 10001111111111010000000001110000 34 | 10001111111111100000000001110100 35 | 00111100000111111000000000000000 36 | 00100111111111110010001100011100 37 | 00000000000000000000000000000000 38 | 00000011010000000000000000001000 39 | 00000000000000000000000000000000 40 | 00000000000000000000000000000000 41 | 00111100000111111000000001111111 42 | 00100111111111110000000000000000 43 | 10101111111000010000000000000000 44 | 10101111111000100000000000000100 45 | 10101111111000110000000000001000 46 | 10101111111001000000000000001100 47 | 10101111111001010000000000010000 48 | 10101111111001100000000000010100 49 | 10101111111001110000000000011000 50 | 10101111111010000000000000011100 51 | 10101111111010010000000000100000 52 | 10101111111010100000000000100100 53 | 10101111111010110000000000101000 54 | 10101111111011000000000000101100 55 | 10101111111011010000000000110000 56 | 10101111111011100000000000110100 57 | 10101111111011110000000000111000 58 | 10101111111100000000000000111100 59 | 10101111111100010000000001000000 60 | 10101111111100100000000001000100 61 | 10101111111100110000000001001000 62 | 10101111111101000000000001001100 63 | 10101111111101010000000001010000 64 | 10101111111101100000000001010100 65 | 10101111111101110000000001011000 66 | 10101111111110000000000001011100 67 | 10101111111110010000000001100000 68 | 10101111111111000000000001101100 69 | 10101111111111010000000001110000 70 | 10101111111111100000000001110100 71 | 10001111111111010000000001111100 72 | 00110100000001000000000000000111 73 | 00001100000000000000100011101110 74 | 00000000000000000000000000000000 75 | 00001000000000000000100011101100 76 | 00000000000000000000000000000000 77 | 00001000000000000000100001010000 78 | 00000000000000000000000000000000 79 | 00111100000010011011111111010000 80 | 10000001001010000000001111111100 81 | 00110001000010000000000000000001 82 | 00010101000000000000000000000011 83 | 00000000000000000000000000000000 84 | 00001000000000000000100011101111 85 | 00000000000000000000000000000000 86 | 00111100000010011011111111010000 87 | 10100001001001000000001111111000 88 | 00000011111000000000000000001000 89 | 00000000000000000000000000000000 90 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_ooc.xdc: -------------------------------------------------------------------------------- 1 | ################################################################################ 2 | # 3 | # (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved. 4 | # 5 | # This file contains confidential and proprietary information 6 | # of Xilinx, Inc. and is protected under U.S. and 7 | # international copyright and other intellectual property 8 | # laws. 9 | # 10 | # DISCLAIMER 11 | # This disclaimer is not a license and does not grant any 12 | # rights to the materials distributed herewith. Except as 13 | # otherwise provided in a valid license issued to you by 14 | # Xilinx, and to the maximum extent permitted by applicable 15 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 16 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 17 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 18 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 19 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 20 | # (2) Xilinx shall not be liable (whether in contract or tort, 21 | # including negligence, or under any other theory of 22 | # liability) for any loss or damage of any kind or nature 23 | # related to, arising under or in connection with these 24 | # materials, including for any direct, or any indirect, 25 | # special, incidental, or consequential loss or damage 26 | # (including loss of data, profits, goodwill, or any type of 27 | # loss or damage suffered as a result of any action brought 28 | # by a third party) even if such damage or loss was 29 | # reasonably foreseeable or Xilinx had been advised of the 30 | # possibility of the same. 31 | # 32 | # CRITICAL APPLICATIONS 33 | # Xilinx products are not designed or intended to be fail- 34 | # safe, or for use in any application requiring fail-safe 35 | # performance, such as life-support or safety devices or 36 | # systems, Class III medical devices, nuclear facilities, 37 | # applications related to the deployment of airbags, or any 38 | # other applications that could lead to death, personal 39 | # injury, or severe property or environmental damage 40 | # (individually and collectively, "Critical 41 | # Applications"). Customer assumes the sole risk and 42 | # liability of any use of Xilinx products in Critical 43 | # Applications, subject only to applicable laws and 44 | # regulations governing limitations on product liability. 45 | # 46 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 47 | # PART OF THIS FILE AT ALL TIMES. 48 | # 49 | ################################################################################ 50 | 51 | # Core Period Constraint. This constraint can be modified, and is 52 | # valid as long as it is met after place and route. 53 | create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ] 54 | set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ] 55 | ################################################################################ 56 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/blk_mem_gen_0/doc/blk_mem_gen_v8_4_changelog.txt: -------------------------------------------------------------------------------- 1 | 2019.2: 2 | * Version 8.4 (Rev. 4) 3 | * Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations 4 | 5 | 2019.1.3: 6 | * Version 8.4 (Rev. 3) 7 | * No changes 8 | 9 | 2019.1.2: 10 | * Version 8.4 (Rev. 3) 11 | * No changes 12 | 13 | 2019.1.1: 14 | * Version 8.4 (Rev. 3) 15 | * No changes 16 | 17 | 2019.1: 18 | * Version 8.4 (Rev. 3) 19 | * General: Internal device family change, no functional changes 20 | 21 | 2018.3.1: 22 | * Version 8.4 (Rev. 2) 23 | * No changes 24 | 25 | 2018.3: 26 | * Version 8.4 (Rev. 2) 27 | * Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator 28 | * Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes 29 | * Other: Internal device family change, no functional changes 30 | 31 | 2018.2: 32 | * Version 8.4 (Rev. 1) 33 | * No changes 34 | 35 | 2018.1: 36 | * Version 8.4 (Rev. 1) 37 | * No changes 38 | 39 | 2017.4: 40 | * Version 8.4 (Rev. 1) 41 | * General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes 42 | 43 | 2017.3: 44 | * Version 8.4 45 | * General: Safety Circuit option is enabled by default if reset option in any one port is enabled 46 | 47 | 2017.2: 48 | * Version 8.3 (Rev. 6) 49 | * No changes 50 | 51 | 2017.1: 52 | * Version 8.3 (Rev. 6) 53 | * General: Internal device family change, no functional changes 54 | * General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode 55 | 56 | 2016.4: 57 | * Version 8.3 (Rev. 5) 58 | * General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL) 59 | 60 | 2016.3: 61 | * Version 8.3 (Rev. 4) 62 | * Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled 63 | * Other: Enable support for future devices 64 | * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user 65 | 66 | 2016.2: 67 | * Version 8.3 (Rev. 3) 68 | * updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller 69 | * Updated the IP to support the device package changes 70 | 71 | 2016.1: 72 | * Version 8.3 (Rev. 2) 73 | * Updated the IP to deliver only verilog behavioral model 74 | * Updated the IP to support UltraRAM in IP Integrator 75 | * Updated the IP to support the device package changes 76 | 77 | 2015.4.2: 78 | * Version 8.3 (Rev. 1) 79 | * No changes 80 | 81 | 2015.4.1: 82 | * Version 8.3 (Rev. 1) 83 | * No changes 84 | 85 | 2015.4: 86 | * Version 8.3 (Rev. 1) 87 | * Updated the IP to support the device package changes 88 | 89 | 2015.3: 90 | * Version 8.3 91 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 92 | * New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption 93 | * Simulation models are delivered in VHDL only 94 | 95 | 2015.2.1: 96 | * Version 8.2 (Rev. 5) 97 | * No changes 98 | 99 | 2015.2: 100 | * Version 8.2 (Rev. 5) 101 | * No changes 102 | 103 | 2015.1: 104 | * Version 8.2 (Rev. 5) 105 | * Delivering non encrypted behavioral models 106 | * Supported memory depth is increased up to 1M words 107 | * Added the power saving feature (RDADDRCHG) for ultrascale devices 108 | * Supported devices and production status are now determined automatically, to simplify support for future devices 109 | 110 | 2014.4.1: 111 | * Version 8.2 (Rev. 4) 112 | * Updated the IP to support the device package changes 113 | 114 | 2014.4: 115 | * Version 8.2 (Rev. 3) 116 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 117 | * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices 118 | * Internal device family change, no functional changes 119 | 120 | 2014.3: 121 | * Version 8.2 (Rev. 2) 122 | * Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used 123 | * Fixed the GUI crash in Simple Dual Port RAM 124 | * Added support of all write modes in Simple Dual Port RAM when ECC is not used 125 | * Increased the supported depth to a maximum value of 256k 126 | 127 | 2014.2: 128 | * Version 8.2 (Rev. 1) 129 | * Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI 130 | 131 | 2014.1: 132 | * Version 8.2 133 | * Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices 134 | * Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices 135 | * Added support of the dynamic power saving for ultra-scale devices 136 | * Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices 137 | * Internal device family name change, no functional changes 138 | 139 | 2013.4: 140 | * Version 8.1 141 | * The Primitive output registers are made "ON" by default in the stand alone mode 142 | * Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives 143 | * Added support for ultrascale devices 144 | 145 | 2013.3: 146 | * Version 8.0 (Rev. 2) 147 | * Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator. 148 | * Improved GUI speed and responsivness, no functional changes 149 | * Reduced synthesis and simulation warnings 150 | * Added support for Cadence IES and Synopsys VCS simulators 151 | * Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN" 152 | * Changed BRAM Interface DIN and DOUT to match bus interface directions. 153 | 154 | 2013.2: 155 | * Version 8.0 (Rev. 1) 156 | * No Changes 157 | 158 | 2013.1: 159 | * Version 8.0 160 | * Native Vivado Release 161 | * There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 162 | 163 | (c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved. 164 | 165 | This file contains confidential and proprietary information 166 | of Xilinx, Inc. and is protected under U.S. and 167 | international copyright and other intellectual property 168 | laws. 169 | 170 | DISCLAIMER 171 | This disclaimer is not a license and does not grant any 172 | rights to the materials distributed herewith. Except as 173 | otherwise provided in a valid license issued to you by 174 | Xilinx, and to the maximum extent permitted by applicable 175 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 176 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 177 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 178 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 179 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 180 | (2) Xilinx shall not be liable (whether in contract or tort, 181 | including negligence, or under any other theory of 182 | liability) for any loss or damage of any kind or nature 183 | related to, arising under or in connection with these 184 | materials, including for any direct, or any indirect, 185 | special, incidental, or consequential loss or damage 186 | (including loss of data, profits, goodwill, or any type of 187 | loss or damage suffered as a result of any action brought 188 | by a third party) even if such damage or loss was 189 | reasonably foreseeable or Xilinx had been advised of the 190 | possibility of the same. 191 | 192 | CRITICAL APPLICATIONS 193 | Xilinx products are not designed or intended to be fail- 194 | safe, or for use in any application requiring fail-safe 195 | performance, such as life-support or safety devices or 196 | systems, Class III medical devices, nuclear facilities, 197 | applications related to the deployment of airbags, or any 198 | other applications that could lead to death, personal 199 | injury, or severe property or environmental damage 200 | (individually and collectively, "Critical 201 | Applications"). Customer assumes the sole risk and 202 | liability of any use of Xilinx products in Critical 203 | Applications, subject only to applicable laws and 204 | regulations governing limitations on product liability. 205 | 206 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 207 | PART OF THIS FILE AT ALL TIMES. 208 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/blk_mem_gen_0/misc/blk_mem_gen_v8_4.vhd: -------------------------------------------------------------------------------- 1 | library ieee; 2 | use ieee.std_logic_1164.all; 3 | 4 | entity blk_mem_gen_v8_4_4 is 5 | generic ( 6 | C_FAMILY : string := "virtex7"; 7 | C_XDEVICEFAMILY : string := "virtex7"; 8 | C_ELABORATION_DIR : string := ""; 9 | C_INTERFACE_TYPE : integer := 0; 10 | C_AXI_TYPE : integer := 1; 11 | C_AXI_SLAVE_TYPE : integer := 0; 12 | C_USE_BRAM_BLOCK : integer := 0; 13 | C_ENABLE_32BIT_ADDRESS : integer := 0; 14 | C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7"; 15 | C_HAS_AXI_ID : integer := 0; 16 | C_AXI_ID_WIDTH : integer := 4; 17 | C_MEM_TYPE : integer := 2; 18 | C_BYTE_SIZE : integer := 9; 19 | C_ALGORITHM : integer := 0; 20 | C_PRIM_TYPE : integer := 3; 21 | C_LOAD_INIT_FILE : integer := 0; 22 | C_INIT_FILE_NAME : string := "no_coe_file_loaded"; 23 | C_INIT_FILE : string := "no_mem_file_loaded"; 24 | C_USE_DEFAULT_DATA : integer := 0; 25 | C_DEFAULT_DATA : string := "0"; 26 | C_HAS_RSTA : integer := 0; 27 | C_RST_PRIORITY_A : string := "ce"; 28 | C_RSTRAM_A : integer := 0; 29 | C_INITA_VAL : string := "0"; 30 | C_HAS_ENA : integer := 1; 31 | C_HAS_REGCEA : integer := 0; 32 | C_USE_BYTE_WEA : integer := 0; 33 | C_WEA_WIDTH : integer := 1; 34 | C_WRITE_MODE_A : string := "WRITE_FIRST"; 35 | C_WRITE_WIDTH_A : integer := 9; 36 | C_READ_WIDTH_A : integer := 9; 37 | C_WRITE_DEPTH_A : integer := 2048; 38 | C_READ_DEPTH_A : integer := 2048; 39 | C_ADDRA_WIDTH : integer := 11; 40 | C_HAS_RSTB : integer := 0; 41 | C_RST_PRIORITY_B : string := "ce"; 42 | C_RSTRAM_B : integer := 0; 43 | C_INITB_VAL : string := "0"; 44 | C_HAS_ENB : integer := 1; 45 | C_HAS_REGCEB : integer := 0; 46 | C_USE_BYTE_WEB : integer := 0; 47 | C_WEB_WIDTH : integer := 1; 48 | C_WRITE_MODE_B : string := "WRITE_FIRST"; 49 | C_WRITE_WIDTH_B : integer := 9; 50 | C_READ_WIDTH_B : integer := 9; 51 | C_WRITE_DEPTH_B : integer := 2048; 52 | C_READ_DEPTH_B : integer := 2048; 53 | C_ADDRB_WIDTH : integer := 11; 54 | C_HAS_MEM_OUTPUT_REGS_A : integer := 0; 55 | C_HAS_MEM_OUTPUT_REGS_B : integer := 0; 56 | C_HAS_MUX_OUTPUT_REGS_A : integer := 0; 57 | C_HAS_MUX_OUTPUT_REGS_B : integer := 0; 58 | C_MUX_PIPELINE_STAGES : integer := 0; 59 | C_HAS_SOFTECC_INPUT_REGS_A : integer := 0; 60 | C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0; 61 | C_USE_SOFTECC : integer := 0; 62 | C_USE_ECC : integer := 0; 63 | C_EN_ECC_PIPE : integer := 0; 64 | C_HAS_INJECTERR : integer := 0; 65 | C_SIM_COLLISION_CHECK : string := "none"; 66 | C_COMMON_CLK : integer := 0; 67 | C_DISABLE_WARN_BHV_COLL : integer := 0; 68 | C_EN_SLEEP_PIN : integer := 0; 69 | C_USE_URAM : integer := 0; 70 | C_EN_RDADDRA_CHG : integer := 0; 71 | C_EN_RDADDRB_CHG : integer := 0; 72 | C_EN_DEEPSLEEP_PIN : integer := 0; 73 | C_EN_SHUTDOWN_PIN : integer := 0; 74 | C_EN_SAFETY_CKT : integer := 0; 75 | C_DISABLE_WARN_BHV_RANGE : integer := 0; 76 | C_COUNT_36K_BRAM : string := ""; 77 | C_COUNT_18K_BRAM : string := ""; 78 | C_EST_POWER_SUMMARY : string := "" 79 | ); 80 | port ( 81 | clka : in std_logic := '0'; 82 | rsta : in std_logic := '0'; 83 | ena : in std_logic := '0'; 84 | regcea : in std_logic := '0'; 85 | wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); 86 | addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0'); 87 | dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); 88 | douta : out std_logic_vector(c_read_width_a - 1 downto 0); 89 | clkb : in std_logic := '0'; 90 | rstb : in std_logic := '0'; 91 | enb : in std_logic := '0'; 92 | regceb : in std_logic := '0'; 93 | web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0'); 94 | addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0'); 95 | dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0'); 96 | doutb : out std_logic_vector(c_read_width_b - 1 downto 0); 97 | injectsbiterr : in std_logic := '0'; 98 | injectdbiterr : in std_logic := '0'; 99 | eccpipece : in std_logic := '0'; 100 | sbiterr : out std_logic; 101 | dbiterr : out std_logic; 102 | rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0); 103 | sleep : in std_logic := '0'; 104 | deepsleep : in std_logic := '0'; 105 | shutdown : in std_logic := '0'; 106 | rsta_busy : out std_logic; 107 | rstb_busy : out std_logic; 108 | s_aclk : in std_logic := '0'; 109 | s_aresetn : in std_logic := '0'; 110 | s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); 111 | s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0'); 112 | s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0'); 113 | s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0'); 114 | s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0'); 115 | s_axi_awvalid : in std_logic := '0'; 116 | s_axi_awready : out std_logic; 117 | s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0'); 118 | s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0'); 119 | s_axi_wlast : in std_logic := '0'; 120 | s_axi_wvalid : in std_logic := '0'; 121 | s_axi_wready : out std_logic; 122 | s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0); 123 | s_axi_bresp : out std_logic_vector(1 downto 0); 124 | s_axi_bvalid : out std_logic; 125 | s_axi_bready : in std_logic := '0'; 126 | s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0'); 127 | s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0'); 128 | s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0'); 129 | s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0'); 130 | s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0'); 131 | s_axi_arvalid : in std_logic := '0'; 132 | s_axi_arready : out std_logic; 133 | s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0); 134 | s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0); 135 | s_axi_rresp : out std_logic_vector(2 - 1 downto 0); 136 | s_axi_rlast : out std_logic; 137 | s_axi_rvalid : out std_logic; 138 | s_axi_rready : in std_logic := '0'; 139 | s_axi_injectsbiterr : in std_logic := '0'; 140 | s_axi_injectdbiterr : in std_logic := '0'; 141 | s_axi_sbiterr : out std_logic; 142 | s_axi_dbiterr : out std_logic; 143 | s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0) 144 | ); 145 | end entity blk_mem_gen_v8_4_4; 146 | 147 | architecture xilinx of blk_mem_gen_v8_4_4 is 148 | begin 149 | end 150 | architecture xilinx; 151 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/blk_mem_gen_0/sim/blk_mem_gen_0.v: -------------------------------------------------------------------------------- 1 | // (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | // 3 | // This file contains confidential and proprietary information 4 | // of Xilinx, Inc. and is protected under U.S. and 5 | // international copyright and other intellectual property 6 | // laws. 7 | // 8 | // DISCLAIMER 9 | // This disclaimer is not a license and does not grant any 10 | // rights to the materials distributed herewith. Except as 11 | // otherwise provided in a valid license issued to you by 12 | // Xilinx, and to the maximum extent permitted by applicable 13 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | // (2) Xilinx shall not be liable (whether in contract or tort, 19 | // including negligence, or under any other theory of 20 | // liability) for any loss or damage of any kind or nature 21 | // related to, arising under or in connection with these 22 | // materials, including for any direct, or any indirect, 23 | // special, incidental, or consequential loss or damage 24 | // (including loss of data, profits, goodwill, or any type of 25 | // loss or damage suffered as a result of any action brought 26 | // by a third party) even if such damage or loss was 27 | // reasonably foreseeable or Xilinx had been advised of the 28 | // possibility of the same. 29 | // 30 | // CRITICAL APPLICATIONS 31 | // Xilinx products are not designed or intended to be fail- 32 | // safe, or for use in any application requiring fail-safe 33 | // performance, such as life-support or safety devices or 34 | // systems, Class III medical devices, nuclear facilities, 35 | // applications related to the deployment of airbags, or any 36 | // other applications that could lead to death, personal 37 | // injury, or severe property or environmental damage 38 | // (individually and collectively, "Critical 39 | // Applications"). Customer assumes the sole risk and 40 | // liability of any use of Xilinx products in Critical 41 | // Applications, subject only to applicable laws and 42 | // regulations governing limitations on product liability. 43 | // 44 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | // PART OF THIS FILE AT ALL TIMES. 46 | // 47 | // DO NOT MODIFY THIS FILE. 48 | 49 | 50 | // IP VLNV: xilinx.com:ip:blk_mem_gen:8.4 51 | // IP Revision: 4 52 | 53 | `timescale 1ns/1ps 54 | 55 | (* DowngradeIPIdentifiedWarnings = "yes" *) 56 | module blk_mem_gen_0 ( 57 | clka, 58 | wea, 59 | addra, 60 | dina, 61 | douta 62 | ); 63 | 64 | (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) 65 | input wire clka; 66 | (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) 67 | input wire [0 : 0] wea; 68 | (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) 69 | input wire [9 : 0] addra; 70 | (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) 71 | input wire [31 : 0] dina; 72 | (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) 73 | (* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) 74 | output wire [31 : 0] douta; 75 | 76 | blk_mem_gen_v8_4_4 #( 77 | .C_FAMILY("artix7"), 78 | .C_XDEVICEFAMILY("artix7"), 79 | .C_ELABORATION_DIR("./"), 80 | .C_INTERFACE_TYPE(0), 81 | .C_AXI_TYPE(1), 82 | .C_AXI_SLAVE_TYPE(0), 83 | .C_USE_BRAM_BLOCK(0), 84 | .C_ENABLE_32BIT_ADDRESS(0), 85 | .C_CTRL_ECC_ALGO("NONE"), 86 | .C_HAS_AXI_ID(0), 87 | .C_AXI_ID_WIDTH(4), 88 | .C_MEM_TYPE(0), 89 | .C_BYTE_SIZE(9), 90 | .C_ALGORITHM(1), 91 | .C_PRIM_TYPE(1), 92 | .C_LOAD_INIT_FILE(1), 93 | .C_INIT_FILE_NAME("blk_mem_gen_0.mif"), 94 | .C_INIT_FILE("blk_mem_gen_0.mem"), 95 | .C_USE_DEFAULT_DATA(1), 96 | .C_DEFAULT_DATA("0"), 97 | .C_HAS_RSTA(0), 98 | .C_RST_PRIORITY_A("CE"), 99 | .C_RSTRAM_A(0), 100 | .C_INITA_VAL("0"), 101 | .C_HAS_ENA(0), 102 | .C_HAS_REGCEA(0), 103 | .C_USE_BYTE_WEA(0), 104 | .C_WEA_WIDTH(1), 105 | .C_WRITE_MODE_A("WRITE_FIRST"), 106 | .C_WRITE_WIDTH_A(32), 107 | .C_READ_WIDTH_A(32), 108 | .C_WRITE_DEPTH_A(1024), 109 | .C_READ_DEPTH_A(1024), 110 | .C_ADDRA_WIDTH(10), 111 | .C_HAS_RSTB(0), 112 | .C_RST_PRIORITY_B("CE"), 113 | .C_RSTRAM_B(0), 114 | .C_INITB_VAL("0"), 115 | .C_HAS_ENB(0), 116 | .C_HAS_REGCEB(0), 117 | .C_USE_BYTE_WEB(0), 118 | .C_WEB_WIDTH(1), 119 | .C_WRITE_MODE_B("WRITE_FIRST"), 120 | .C_WRITE_WIDTH_B(32), 121 | .C_READ_WIDTH_B(32), 122 | .C_WRITE_DEPTH_B(1024), 123 | .C_READ_DEPTH_B(1024), 124 | .C_ADDRB_WIDTH(10), 125 | .C_HAS_MEM_OUTPUT_REGS_A(0), 126 | .C_HAS_MEM_OUTPUT_REGS_B(0), 127 | .C_HAS_MUX_OUTPUT_REGS_A(0), 128 | .C_HAS_MUX_OUTPUT_REGS_B(0), 129 | .C_MUX_PIPELINE_STAGES(0), 130 | .C_HAS_SOFTECC_INPUT_REGS_A(0), 131 | .C_HAS_SOFTECC_OUTPUT_REGS_B(0), 132 | .C_USE_SOFTECC(0), 133 | .C_USE_ECC(0), 134 | .C_EN_ECC_PIPE(0), 135 | .C_READ_LATENCY_A(1), 136 | .C_READ_LATENCY_B(1), 137 | .C_HAS_INJECTERR(0), 138 | .C_SIM_COLLISION_CHECK("ALL"), 139 | .C_COMMON_CLK(0), 140 | .C_DISABLE_WARN_BHV_COLL(0), 141 | .C_EN_SLEEP_PIN(0), 142 | .C_USE_URAM(0), 143 | .C_EN_RDADDRA_CHG(0), 144 | .C_EN_RDADDRB_CHG(0), 145 | .C_EN_DEEPSLEEP_PIN(0), 146 | .C_EN_SHUTDOWN_PIN(0), 147 | .C_EN_SAFETY_CKT(0), 148 | .C_DISABLE_WARN_BHV_RANGE(0), 149 | .C_COUNT_36K_BRAM("1"), 150 | .C_COUNT_18K_BRAM("0"), 151 | .C_EST_POWER_SUMMARY("Estimated Power for IP : 2.95215 mW") 152 | ) inst ( 153 | .clka(clka), 154 | .rsta(1'D0), 155 | .ena(1'D0), 156 | .regcea(1'D0), 157 | .wea(wea), 158 | .addra(addra), 159 | .dina(dina), 160 | .douta(douta), 161 | .clkb(1'D0), 162 | .rstb(1'D0), 163 | .enb(1'D0), 164 | .regceb(1'D0), 165 | .web(1'B0), 166 | .addrb(10'B0), 167 | .dinb(32'B0), 168 | .doutb(), 169 | .injectsbiterr(1'D0), 170 | .injectdbiterr(1'D0), 171 | .eccpipece(1'D0), 172 | .sbiterr(), 173 | .dbiterr(), 174 | .rdaddrecc(), 175 | .sleep(1'D0), 176 | .deepsleep(1'D0), 177 | .shutdown(1'D0), 178 | .rsta_busy(), 179 | .rstb_busy(), 180 | .s_aclk(1'H0), 181 | .s_aresetn(1'D0), 182 | .s_axi_awid(4'B0), 183 | .s_axi_awaddr(32'B0), 184 | .s_axi_awlen(8'B0), 185 | .s_axi_awsize(3'B0), 186 | .s_axi_awburst(2'B0), 187 | .s_axi_awvalid(1'D0), 188 | .s_axi_awready(), 189 | .s_axi_wdata(32'B0), 190 | .s_axi_wstrb(1'B0), 191 | .s_axi_wlast(1'D0), 192 | .s_axi_wvalid(1'D0), 193 | .s_axi_wready(), 194 | .s_axi_bid(), 195 | .s_axi_bresp(), 196 | .s_axi_bvalid(), 197 | .s_axi_bready(1'D0), 198 | .s_axi_arid(4'B0), 199 | .s_axi_araddr(32'B0), 200 | .s_axi_arlen(8'B0), 201 | .s_axi_arsize(3'B0), 202 | .s_axi_arburst(2'B0), 203 | .s_axi_arvalid(1'D0), 204 | .s_axi_arready(), 205 | .s_axi_rid(), 206 | .s_axi_rdata(), 207 | .s_axi_rresp(), 208 | .s_axi_rlast(), 209 | .s_axi_rvalid(), 210 | .s_axi_rready(1'D0), 211 | .s_axi_injectsbiterr(1'D0), 212 | .s_axi_injectdbiterr(1'D0), 213 | .s_axi_sbiterr(), 214 | .s_axi_dbiterr(), 215 | .s_axi_rdaddrecc() 216 | ); 217 | endmodule 218 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/mult_gen_0/doc/mult_gen_v12_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2019.2: 2 | * Version 12.0 (Rev. 16) 3 | * General: Support for Versal devices 4 | 5 | 2019.1.3: 6 | * Version 12.0 (Rev. 15) 7 | * No changes 8 | 9 | 2019.1.2: 10 | * Version 12.0 (Rev. 15) 11 | * No changes 12 | 13 | 2019.1.1: 14 | * Version 12.0 (Rev. 15) 15 | * No changes 16 | 17 | 2019.1: 18 | * Version 12.0 (Rev. 15) 19 | * Revision change in one or more subcores 20 | 21 | 2018.3.1: 22 | * Version 12.0 (Rev. 14) 23 | * No changes 24 | 25 | 2018.3: 26 | * Version 12.0 (Rev. 14) 27 | * No changes 28 | 29 | 2018.2: 30 | * Version 12.0 (Rev. 14) 31 | * No changes 32 | 33 | 2018.1: 34 | * Version 12.0 (Rev. 14) 35 | * Revision change in one or more subcores 36 | 37 | 2017.4: 38 | * Version 12.0 (Rev. 13) 39 | * No changes 40 | 41 | 2017.3: 42 | * Version 12.0 (Rev. 13) 43 | * Revision change in one or more subcores 44 | 45 | 2017.2: 46 | * Version 12.0 (Rev. 12) 47 | * No changes 48 | 49 | 2017.1: 50 | * Version 12.0 (Rev. 12) 51 | * No changes 52 | 53 | 2016.4: 54 | * Version 12.0 (Rev. 12) 55 | * No changes 56 | 57 | 2016.3: 58 | * Version 12.0 (Rev. 12) 59 | * General: Support for Spartan7 devices 60 | * Revision change in one or more subcores 61 | 62 | 2016.2: 63 | * Version 12.0 (Rev. 11) 64 | * No changes 65 | 66 | 2016.1: 67 | * Version 12.0 (Rev. 11) 68 | * Updated DSP48 register settings for improved power characterisics as suggested by report_drc. No functional changes. 69 | * Revision change in one or more subcores 70 | 71 | 2015.4.2: 72 | * Version 12.0 (Rev. 10) 73 | * No changes 74 | 75 | 2015.4.1: 76 | * Version 12.0 (Rev. 10) 77 | * No changes 78 | 79 | 2015.4: 80 | * Version 12.0 (Rev. 10) 81 | * Revision change in one or more subcores 82 | 83 | 2015.3: 84 | * Version 12.0 (Rev. 9) 85 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 86 | * Revision change in one or more subcores 87 | 88 | 2015.2.1: 89 | * Version 12.0 (Rev. 8) 90 | * No changes 91 | 92 | 2015.2: 93 | * Version 12.0 (Rev. 8) 94 | * Rephrased RTL to work around issue when simulating with Cadence IES. No functional changes. 95 | * Corrected output pipeline widths for some DSP48 multiplier configurations targeting UltraScale devices. 96 | 97 | 2015.1: 98 | * Version 12.0 (Rev. 7) 99 | * Rephrased RTL to work around range checking issue when simulating with Vivado Simulator. No functional changes. 100 | * Addition of Beta support for future devices 101 | * Supported devices and production status are now determined automatically, to simplify support for future devices 102 | * Modified constant-coefficient multiplier distributed ROM RTL for consistency with Vivado Synthesis inference template. No functional changes. 103 | 104 | 2014.4.1: 105 | * Version 12.0 (Rev. 6) 106 | * No changes 107 | 108 | 2014.4: 109 | * Version 12.0 (Rev. 6) 110 | * Disable symmetric rounding checkbox on the GUI when rounding is not supported 111 | * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time 112 | * Internal GUI updates, no functional changes. 113 | * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk_intf 114 | 115 | 2014.3: 116 | * Version 12.0 (Rev. 5) 117 | * No changes 118 | 119 | 2014.2: 120 | * Version 12.0 (Rev. 5) 121 | * Removed component statement for DSP48E2, no functional changes 122 | 123 | 2014.1: 124 | * Version 12.0 (Rev. 4) 125 | * Core will always deliver an ooc_xdc file, even when PipeStages (latency) = 0. 126 | * Internal device family name change, no functional changes 127 | * Netlists created by write_verilog and write_vhdl are IEEE P1735 encrypted, with keys for supported simulators so that netlist simulation can still be done 128 | * Enable third party synthesis tools to read encrypted netlists (but not source HDL) 129 | * Support for Virtex Ultrascale devices at Pre-Production Status 130 | 131 | 2013.4: 132 | * Version 12.0 (Rev. 3) 133 | * Fixed bug in generation of DSP48-based multipliers for UltraScale devices 134 | * Support for Kintex Ultrascale devices at Pre-Production Status 135 | 136 | 2013.3: 137 | * Version 12.0 (Rev. 2) 138 | * Behavioral VHDL model replaced by Encrypted RTL. For more information on this change please refer to the Migrating and Upgrading section in the Product Guide 139 | * Internal standardization in source file delivery, does not change behavior 140 | * Support for Automotive Artix-7, Automotive Zynq, Defense Grade Artix-7, Defense Grade Zynq and Lower Power Artix-7 devices at Production Status 141 | * Added default constraints for out of context flow 142 | * Added support for IP Integrator 143 | * Added support for Cadence IES and Synopsys VCS simulators 144 | * Optimized support for UltraScale devices 145 | 146 | 2013.2: 147 | * Version 12.0 (Rev. 1) 148 | * Support for Series 7 devices at Production status 149 | * Updated clock and bus interface associations for IP Integrator support 150 | * Repackaged IP to remove internal debug ports from GUI symbol 151 | * Fixed GUI resource estimation bug for DSP48-based area-optimized multipliers 152 | * Fixed bug in generation of LUT-based area-optimized multipliers 153 | * Changed distributed memory constant-coefficient multiplier implementation to use ROM instead of RAM 154 | * Fixed bug related to 31x18 DSP48-based multiplier resource usage 155 | * Removing support for Defense Grade Low Power Artix7 156 | 157 | 2013.1: 158 | * Version 12.0 159 | * Native Vivado Release 160 | * Changed all port names to upper case 161 | * There have been no functional changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1. 162 | 163 | (c) Copyright 2000 - 2019 Xilinx, Inc. All rights reserved. 164 | 165 | This file contains confidential and proprietary information 166 | of Xilinx, Inc. and is protected under U.S. and 167 | international copyright and other intellectual property 168 | laws. 169 | 170 | DISCLAIMER 171 | This disclaimer is not a license and does not grant any 172 | rights to the materials distributed herewith. Except as 173 | otherwise provided in a valid license issued to you by 174 | Xilinx, and to the maximum extent permitted by applicable 175 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 176 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 177 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 178 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 179 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 180 | (2) Xilinx shall not be liable (whether in contract or tort, 181 | including negligence, or under any other theory of 182 | liability) for any loss or damage of any kind or nature 183 | related to, arising under or in connection with these 184 | materials, including for any direct, or any indirect, 185 | special, incidental, or consequential loss or damage 186 | (including loss of data, profits, goodwill, or any type of 187 | loss or damage suffered as a result of any action brought 188 | by a third party) even if such damage or loss was 189 | reasonably foreseeable or Xilinx had been advised of the 190 | possibility of the same. 191 | 192 | CRITICAL APPLICATIONS 193 | Xilinx products are not designed or intended to be fail- 194 | safe, or for use in any application requiring fail-safe 195 | performance, such as life-support or safety devices or 196 | systems, Class III medical devices, nuclear facilities, 197 | applications related to the deployment of airbags, or any 198 | other applications that could lead to death, personal 199 | injury, or severe property or environmental damage 200 | (individually and collectively, "Critical 201 | Applications"). Customer assumes the sole risk and 202 | liability of any use of Xilinx products in Critical 203 | Applications, subject only to applicable laws and 204 | regulations governing limitations on product liability. 205 | 206 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 207 | PART OF THIS FILE AT ALL TIMES. 208 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/mult_gen_0/sim/mult_gen_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:mult_gen:12.0 50 | -- IP Revision: 16 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY mult_gen_v12_0_16; 57 | USE mult_gen_v12_0_16.mult_gen_v12_0_16; 58 | 59 | ENTITY mult_gen_0 IS 60 | PORT ( 61 | A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 63 | P : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END mult_gen_0; 66 | 67 | ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 69 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes"; 70 | COMPONENT mult_gen_v12_0_16 IS 71 | GENERIC ( 72 | C_VERBOSITY : INTEGER; 73 | C_MODEL_TYPE : INTEGER; 74 | C_OPTIMIZE_GOAL : INTEGER; 75 | C_XDEVICEFAMILY : STRING; 76 | C_HAS_CE : INTEGER; 77 | C_HAS_SCLR : INTEGER; 78 | C_LATENCY : INTEGER; 79 | C_A_WIDTH : INTEGER; 80 | C_A_TYPE : INTEGER; 81 | C_B_WIDTH : INTEGER; 82 | C_B_TYPE : INTEGER; 83 | C_OUT_HIGH : INTEGER; 84 | C_OUT_LOW : INTEGER; 85 | C_MULT_TYPE : INTEGER; 86 | C_CE_OVERRIDES_SCLR : INTEGER; 87 | C_CCM_IMP : INTEGER; 88 | C_B_VALUE : STRING; 89 | C_HAS_ZERO_DETECT : INTEGER; 90 | C_ROUND_OUTPUT : INTEGER; 91 | C_ROUND_PT : INTEGER 92 | ); 93 | PORT ( 94 | CLK : IN STD_LOGIC; 95 | A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 96 | B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 97 | CE : IN STD_LOGIC; 98 | SCLR : IN STD_LOGIC; 99 | P : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 100 | ); 101 | END COMPONENT mult_gen_v12_0_16; 102 | ATTRIBUTE X_INTERFACE_INFO : STRING; 103 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 104 | ATTRIBUTE X_INTERFACE_PARAMETER OF P: SIGNAL IS "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef"; 105 | ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; 106 | ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef"; 107 | ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; 108 | ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef"; 109 | ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; 110 | BEGIN 111 | U0 : mult_gen_v12_0_16 112 | GENERIC MAP ( 113 | C_VERBOSITY => 0, 114 | C_MODEL_TYPE => 0, 115 | C_OPTIMIZE_GOAL => 1, 116 | C_XDEVICEFAMILY => "artix7", 117 | C_HAS_CE => 0, 118 | C_HAS_SCLR => 0, 119 | C_LATENCY => 0, 120 | C_A_WIDTH => 32, 121 | C_A_TYPE => 0, 122 | C_B_WIDTH => 32, 123 | C_B_TYPE => 0, 124 | C_OUT_HIGH => 31, 125 | C_OUT_LOW => 0, 126 | C_MULT_TYPE => 1, 127 | C_CE_OVERRIDES_SCLR => 0, 128 | C_CCM_IMP => 0, 129 | C_B_VALUE => "10000001", 130 | C_HAS_ZERO_DETECT => 0, 131 | C_ROUND_OUTPUT => 0, 132 | C_ROUND_PT => 0 133 | ) 134 | PORT MAP ( 135 | CLK => '1', 136 | A => A, 137 | B => B, 138 | CE => '1', 139 | SCLR => '0', 140 | P => P 141 | ); 142 | END mult_gen_0_arch; 143 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/mult_gen_0/synth/mult_gen_0.vhd: -------------------------------------------------------------------------------- 1 | -- (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved. 2 | -- 3 | -- This file contains confidential and proprietary information 4 | -- of Xilinx, Inc. and is protected under U.S. and 5 | -- international copyright and other intellectual property 6 | -- laws. 7 | -- 8 | -- DISCLAIMER 9 | -- This disclaimer is not a license and does not grant any 10 | -- rights to the materials distributed herewith. Except as 11 | -- otherwise provided in a valid license issued to you by 12 | -- Xilinx, and to the maximum extent permitted by applicable 13 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 14 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 15 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 16 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 17 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 18 | -- (2) Xilinx shall not be liable (whether in contract or tort, 19 | -- including negligence, or under any other theory of 20 | -- liability) for any loss or damage of any kind or nature 21 | -- related to, arising under or in connection with these 22 | -- materials, including for any direct, or any indirect, 23 | -- special, incidental, or consequential loss or damage 24 | -- (including loss of data, profits, goodwill, or any type of 25 | -- loss or damage suffered as a result of any action brought 26 | -- by a third party) even if such damage or loss was 27 | -- reasonably foreseeable or Xilinx had been advised of the 28 | -- possibility of the same. 29 | -- 30 | -- CRITICAL APPLICATIONS 31 | -- Xilinx products are not designed or intended to be fail- 32 | -- safe, or for use in any application requiring fail-safe 33 | -- performance, such as life-support or safety devices or 34 | -- systems, Class III medical devices, nuclear facilities, 35 | -- applications related to the deployment of airbags, or any 36 | -- other applications that could lead to death, personal 37 | -- injury, or severe property or environmental damage 38 | -- (individually and collectively, "Critical 39 | -- Applications"). Customer assumes the sole risk and 40 | -- liability of any use of Xilinx products in Critical 41 | -- Applications, subject only to applicable laws and 42 | -- regulations governing limitations on product liability. 43 | -- 44 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 45 | -- PART OF THIS FILE AT ALL TIMES. 46 | -- 47 | -- DO NOT MODIFY THIS FILE. 48 | 49 | -- IP VLNV: xilinx.com:ip:mult_gen:12.0 50 | -- IP Revision: 16 51 | 52 | LIBRARY ieee; 53 | USE ieee.std_logic_1164.ALL; 54 | USE ieee.numeric_std.ALL; 55 | 56 | LIBRARY mult_gen_v12_0_16; 57 | USE mult_gen_v12_0_16.mult_gen_v12_0_16; 58 | 59 | ENTITY mult_gen_0 IS 60 | PORT ( 61 | A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 62 | B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 63 | P : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 64 | ); 65 | END mult_gen_0; 66 | 67 | ARCHITECTURE mult_gen_0_arch OF mult_gen_0 IS 68 | ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; 69 | ATTRIBUTE DowngradeIPIdentifiedWarnings OF mult_gen_0_arch: ARCHITECTURE IS "yes"; 70 | COMPONENT mult_gen_v12_0_16 IS 71 | GENERIC ( 72 | C_VERBOSITY : INTEGER; 73 | C_MODEL_TYPE : INTEGER; 74 | C_OPTIMIZE_GOAL : INTEGER; 75 | C_XDEVICEFAMILY : STRING; 76 | C_HAS_CE : INTEGER; 77 | C_HAS_SCLR : INTEGER; 78 | C_LATENCY : INTEGER; 79 | C_A_WIDTH : INTEGER; 80 | C_A_TYPE : INTEGER; 81 | C_B_WIDTH : INTEGER; 82 | C_B_TYPE : INTEGER; 83 | C_OUT_HIGH : INTEGER; 84 | C_OUT_LOW : INTEGER; 85 | C_MULT_TYPE : INTEGER; 86 | C_CE_OVERRIDES_SCLR : INTEGER; 87 | C_CCM_IMP : INTEGER; 88 | C_B_VALUE : STRING; 89 | C_HAS_ZERO_DETECT : INTEGER; 90 | C_ROUND_OUTPUT : INTEGER; 91 | C_ROUND_PT : INTEGER 92 | ); 93 | PORT ( 94 | CLK : IN STD_LOGIC; 95 | A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 96 | B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); 97 | CE : IN STD_LOGIC; 98 | SCLR : IN STD_LOGIC; 99 | P : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) 100 | ); 101 | END COMPONENT mult_gen_v12_0_16; 102 | ATTRIBUTE X_CORE_INFO : STRING; 103 | ATTRIBUTE X_CORE_INFO OF mult_gen_0_arch: ARCHITECTURE IS "mult_gen_v12_0_16,Vivado 2019.2"; 104 | ATTRIBUTE CHECK_LICENSE_TYPE : STRING; 105 | ATTRIBUTE CHECK_LICENSE_TYPE OF mult_gen_0_arch : ARCHITECTURE IS "mult_gen_0,mult_gen_v12_0_16,{}"; 106 | ATTRIBUTE CORE_GENERATION_INFO : STRING; 107 | ATTRIBUTE CORE_GENERATION_INFO OF mult_gen_0_arch: ARCHITECTURE IS "mult_gen_0,mult_gen_v12_0_16,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=mult_gen,x_ipVersion=12.0,x_ipCoreRevision=16,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_VERBOSITY=0,C_MODEL_TYPE=0,C_OPTIMIZE_GOAL=1,C_XDEVICEFAMILY=artix7,C_HAS_CE=0,C_HAS_SCLR=0,C_LATENCY=0,C_A_WIDTH=32,C_A_TYPE=0,C_B_WIDTH=32,C_B_TYPE=0,C_OUT_HIGH=31,C_OUT_LOW=0,C_MULT_TYPE=1,C_CE_OVERRIDES_SCLR=0,C_CCM_IMP=0,C_B_VALUE=10000001,C_HAS_ZERO_DETECT=0,C_ROUND_OUTPUT=0,C_ROUND_PT=0}"; 108 | ATTRIBUTE X_INTERFACE_INFO : STRING; 109 | ATTRIBUTE X_INTERFACE_PARAMETER : STRING; 110 | ATTRIBUTE X_INTERFACE_PARAMETER OF P: SIGNAL IS "XIL_INTERFACENAME p_intf, LAYERED_METADATA undef"; 111 | ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA"; 112 | ATTRIBUTE X_INTERFACE_PARAMETER OF B: SIGNAL IS "XIL_INTERFACENAME b_intf, LAYERED_METADATA undef"; 113 | ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA"; 114 | ATTRIBUTE X_INTERFACE_PARAMETER OF A: SIGNAL IS "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef"; 115 | ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA"; 116 | BEGIN 117 | U0 : mult_gen_v12_0_16 118 | GENERIC MAP ( 119 | C_VERBOSITY => 0, 120 | C_MODEL_TYPE => 0, 121 | C_OPTIMIZE_GOAL => 1, 122 | C_XDEVICEFAMILY => "artix7", 123 | C_HAS_CE => 0, 124 | C_HAS_SCLR => 0, 125 | C_LATENCY => 0, 126 | C_A_WIDTH => 32, 127 | C_A_TYPE => 0, 128 | C_B_WIDTH => 32, 129 | C_B_TYPE => 0, 130 | C_OUT_HIGH => 31, 131 | C_OUT_LOW => 0, 132 | C_MULT_TYPE => 1, 133 | C_CE_OVERRIDES_SCLR => 0, 134 | C_CCM_IMP => 0, 135 | C_B_VALUE => "10000001", 136 | C_HAS_ZERO_DETECT => 0, 137 | C_ROUND_OUTPUT => 0, 138 | C_ROUND_PT => 0 139 | ) 140 | PORT MAP ( 141 | CLK => '1', 142 | A => A, 143 | B => B, 144 | CE => '1', 145 | SCLR => '0', 146 | P => P 147 | ); 148 | END mult_gen_0_arch; 149 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/doc/clk_wiz_v6_0_changelog.txt: -------------------------------------------------------------------------------- 1 | 2019.2: 2 | * Version 6.0 (Rev. 4) 3 | * Bug Fix: Internal GUI fixes 4 | * Other: CR Fixes 5 | 6 | 2019.1.3: 7 | * Version 6.0 (Rev. 3) 8 | * No changes 9 | 10 | 2019.1.2: 11 | * Version 6.0 (Rev. 3) 12 | * No changes 13 | 14 | 2019.1.1: 15 | * Version 6.0 (Rev. 3) 16 | * No changes 17 | 18 | 2019.1: 19 | * Version 6.0 (Rev. 3) 20 | * Bug Fix: Internal GUI fixes 21 | * Other: New family support added 22 | 23 | 2018.3.1: 24 | * Version 6.0 (Rev. 2) 25 | * No changes 26 | 27 | 2018.3: 28 | * Version 6.0 (Rev. 2) 29 | * Bug Fix: Made input source independent for primary and secondary clock 30 | * Other: New family support added 31 | 32 | 2018.2: 33 | * Version 6.0 (Rev. 1) 34 | * Bug Fix: Removed vco freq check when Primitive is None 35 | * Other: New family support added 36 | 37 | 2018.1: 38 | * Version 6.0 39 | * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature 40 | * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI 41 | * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals. 42 | * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support 43 | * Other: DRCs added for invalid input values in Override mode 44 | 45 | 2017.4: 46 | * Version 5.4 (Rev. 3) 47 | * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL 48 | * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4 49 | 50 | 2017.3: 51 | * Version 5.4 (Rev. 2) 52 | * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices 53 | 54 | 2017.2: 55 | * Version 5.4 (Rev. 1) 56 | * General: Internal GUI changes. No effect on the customer design. 57 | 58 | 2017.1: 59 | * Version 5.4 60 | * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices. 61 | * Other: Added support for new zynq ultrascale plus devices. 62 | 63 | 2016.4: 64 | * Version 5.3 (Rev. 3) 65 | * Bug Fix: Internal GUI issues are fixed. 66 | 67 | 2016.3: 68 | * Version 5.3 (Rev. 2) 69 | * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs. 70 | * Feature Enhancement: Added Matched Routing Option for better timing solutions. 71 | * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list. 72 | * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user 73 | * Other: Added support for Spartan7 devices. 74 | 75 | 2016.2: 76 | * Version 5.3 (Rev. 1) 77 | * Internal register bit update, no effect on customer designs. 78 | 79 | 2016.1: 80 | * Version 5.3 81 | * Added Clock Monitor Feature as part of clocking wizard 82 | * DRP registers can be directly written through AXI without resource utilization 83 | * Changes to HDL library management to support Vivado IP simulation library 84 | 85 | 2015.4.2: 86 | * Version 5.2 (Rev. 1) 87 | * No changes 88 | 89 | 2015.4.1: 90 | * Version 5.2 (Rev. 1) 91 | * No changes 92 | 93 | 2015.4: 94 | * Version 5.2 (Rev. 1) 95 | * Internal device family change, no functional changes 96 | 97 | 2015.3: 98 | * Version 5.2 99 | * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances 100 | * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported 101 | * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature 102 | * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format 103 | * Example design and simulation files are delivered in verilog only 104 | 105 | 2015.2.1: 106 | * Version 5.1 (Rev. 6) 107 | * No changes 108 | 109 | 2015.2: 110 | * Version 5.1 (Rev. 6) 111 | * No changes 112 | 113 | 2015.1: 114 | * Version 5.1 (Rev. 6) 115 | * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices 116 | * Supported devices and production status are now determined automatically, to simplify support for future devices 117 | 118 | 2014.4.1: 119 | * Version 5.1 (Rev. 5) 120 | * No changes 121 | 122 | 2014.4: 123 | * Version 5.1 (Rev. 5) 124 | * Internal device family change, no functional changes 125 | * updates related to the source selection based on board interface for zed board 126 | 127 | 2014.3: 128 | * Version 5.1 (Rev. 4) 129 | * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface 130 | 131 | 2014.2: 132 | * Version 5.1 (Rev. 3) 133 | * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065 134 | 135 | 2014.1: 136 | * Version 5.1 (Rev. 2) 137 | * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock 138 | * Internal device family name change, no functional changes 139 | 140 | 2013.4: 141 | * Version 5.1 (Rev. 1) 142 | * Added support for Ultrascale devices 143 | * Updated Board Flow GUI to select the clock interfaces 144 | * Fixed issue with Stub file parameter error for BUFR output driver 145 | 146 | 2013.3: 147 | * Version 5.1 148 | * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL 149 | * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies 150 | * Fixed precision issues between displayed and actual frequencies 151 | * Added tool tips to GUI 152 | * Added Jitter and Phase error values to IP properties 153 | * Added support for Cadence IES and Synopsys VCS simulators 154 | * Reduced warnings in synthesis and simulation 155 | * Enhanced support for IP Integrator 156 | 157 | 2013.2: 158 | * Version 5.0 (Rev. 1) 159 | * Fixed issue with clock constraints for multiple instances of clocking wizard 160 | * Updated Life-Cycle status of devices 161 | 162 | 2013.1: 163 | * Version 5.0 164 | * Lower case ports for Verilog 165 | * Added Safe Clock Startup and Clock Sequencing 166 | 167 | (c) Copyright 2008 - 2019 Xilinx, Inc. All rights reserved. 168 | 169 | This file contains confidential and proprietary information 170 | of Xilinx, Inc. and is protected under U.S. and 171 | international copyright and other intellectual property 172 | laws. 173 | 174 | DISCLAIMER 175 | This disclaimer is not a license and does not grant any 176 | rights to the materials distributed herewith. Except as 177 | otherwise provided in a valid license issued to you by 178 | Xilinx, and to the maximum extent permitted by applicable 179 | law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 180 | WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 181 | AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 182 | BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 183 | INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 184 | (2) Xilinx shall not be liable (whether in contract or tort, 185 | including negligence, or under any other theory of 186 | liability) for any loss or damage of any kind or nature 187 | related to, arising under or in connection with these 188 | materials, including for any direct, or any indirect, 189 | special, incidental, or consequential loss or damage 190 | (including loss of data, profits, goodwill, or any type of 191 | loss or damage suffered as a result of any action brought 192 | by a third party) even if such damage or loss was 193 | reasonably foreseeable or Xilinx had been advised of the 194 | possibility of the same. 195 | 196 | CRITICAL APPLICATIONS 197 | Xilinx products are not designed or intended to be fail- 198 | safe, or for use in any application requiring fail-safe 199 | performance, such as life-support or safety devices or 200 | systems, Class III medical devices, nuclear facilities, 201 | applications related to the deployment of airbags, or any 202 | other applications that could lead to death, personal 203 | injury, or severe property or environmental damage 204 | (individually and collectively, "Critical 205 | Applications"). Customer assumes the sole risk and 206 | liability of any use of Xilinx products in Critical 207 | Applications, subject only to applicable laws and 208 | regulations governing limitations on product liability. 209 | 210 | THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 211 | PART OF THIS FILE AT ALL TIMES. 212 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example.v: -------------------------------------------------------------------------------- 1 | 2 | // file: pll_example.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1__62.00000______0.000______50.0______667.345____894.366 60 | // clk_out2__20.00000______0.000______50.0______788.342____894.366 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary______________50____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | (* CORE_GENERATION_INFO = "pll_example,clk_wiz_v6_0_4_0_0,{component_name=pll_example,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=20.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *) 70 | 71 | module pll_example 72 | ( 73 | // Clock out ports 74 | output clk_out1, 75 | output clk_out2, 76 | // Status and control signals 77 | input reset, 78 | output locked, 79 | // Clock in ports 80 | input clk_in1 81 | ); 82 | 83 | pll_example_clk_wiz inst 84 | ( 85 | // Clock out ports 86 | .clk_out1(clk_out1), 87 | .clk_out2(clk_out2), 88 | // Status and control signals 89 | .reset(reset), 90 | .locked(locked), 91 | // Clock in ports 92 | .clk_in1(clk_in1) 93 | ); 94 | 95 | endmodule 96 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: pll_example.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | # Input clock periods. These duplicate the values entered for the 52 | # input clocks. You can use these to time your system. If required 53 | # commented constraints can be used in the top level xdc 54 | #---------------------------------------------------------------- 55 | # Connect to input port when clock capable pin is selected for input 56 | create_clock -period 20.000 [get_ports clk_in1] 57 | set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.2 58 | 59 | 60 | set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*] 61 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example_board.xdc: -------------------------------------------------------------------------------- 1 | #--------------------Physical Constraints----------------- 2 | 3 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example_clk_wiz.v: -------------------------------------------------------------------------------- 1 | 2 | // file: pll_example.v 3 | // 4 | // (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | // 6 | // This file contains confidential and proprietary information 7 | // of Xilinx, Inc. and is protected under U.S. and 8 | // international copyright and other intellectual property 9 | // laws. 10 | // 11 | // DISCLAIMER 12 | // This disclaimer is not a license and does not grant any 13 | // rights to the materials distributed herewith. Except as 14 | // otherwise provided in a valid license issued to you by 15 | // Xilinx, and to the maximum extent permitted by applicable 16 | // law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | // WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | // AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | // BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | // INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | // (2) Xilinx shall not be liable (whether in contract or tort, 22 | // including negligence, or under any other theory of 23 | // liability) for any loss or damage of any kind or nature 24 | // related to, arising under or in connection with these 25 | // materials, including for any direct, or any indirect, 26 | // special, incidental, or consequential loss or damage 27 | // (including loss of data, profits, goodwill, or any type of 28 | // loss or damage suffered as a result of any action brought 29 | // by a third party) even if such damage or loss was 30 | // reasonably foreseeable or Xilinx had been advised of the 31 | // possibility of the same. 32 | // 33 | // CRITICAL APPLICATIONS 34 | // Xilinx products are not designed or intended to be fail- 35 | // safe, or for use in any application requiring fail-safe 36 | // performance, such as life-support or safety devices or 37 | // systems, Class III medical devices, nuclear facilities, 38 | // applications related to the deployment of airbags, or any 39 | // other applications that could lead to death, personal 40 | // injury, or severe property or environmental damage 41 | // (individually and collectively, "Critical 42 | // Applications"). Customer assumes the sole risk and 43 | // liability of any use of Xilinx products in Critical 44 | // Applications, subject only to applicable laws and 45 | // regulations governing limitations on product liability. 46 | // 47 | // THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | // PART OF THIS FILE AT ALL TIMES. 49 | // 50 | //---------------------------------------------------------------------------- 51 | // User entered comments 52 | //---------------------------------------------------------------------------- 53 | // None 54 | // 55 | //---------------------------------------------------------------------------- 56 | // Output Output Phase Duty Cycle Pk-to-Pk Phase 57 | // Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) 58 | //---------------------------------------------------------------------------- 59 | // clk_out1__62.00000______0.000______50.0______667.345____894.366 60 | // clk_out2__20.00000______0.000______50.0______788.342____894.366 61 | // 62 | //---------------------------------------------------------------------------- 63 | // Input Clock Freq (MHz) Input Jitter (UI) 64 | //---------------------------------------------------------------------------- 65 | // __primary______________50____________0.010 66 | 67 | `timescale 1ps/1ps 68 | 69 | module pll_example_clk_wiz 70 | 71 | (// Clock in ports 72 | // Clock out ports 73 | output clk_out1, 74 | output clk_out2, 75 | // Status and control signals 76 | input reset, 77 | output locked, 78 | input clk_in1 79 | ); 80 | // Input buffering 81 | //------------------------------------ 82 | wire clk_in1_pll_example; 83 | wire clk_in2_pll_example; 84 | IBUF clkin1_ibufg 85 | (.O (clk_in1_pll_example), 86 | .I (clk_in1)); 87 | 88 | 89 | 90 | 91 | // Clocking PRIMITIVE 92 | //------------------------------------ 93 | 94 | // Instantiation of the MMCM PRIMITIVE 95 | // * Unused inputs are tied off 96 | // * Unused outputs are labeled unused 97 | 98 | wire clk_out1_pll_example; 99 | wire clk_out2_pll_example; 100 | wire clk_out3_pll_example; 101 | wire clk_out4_pll_example; 102 | wire clk_out5_pll_example; 103 | wire clk_out6_pll_example; 104 | wire clk_out7_pll_example; 105 | 106 | wire [15:0] do_unused; 107 | wire drdy_unused; 108 | wire psdone_unused; 109 | wire locked_int; 110 | wire clkfbout_pll_example; 111 | wire clkfbout_buf_pll_example; 112 | wire clkfboutb_unused; 113 | wire clkout0b_unused; 114 | wire clkout1b_unused; 115 | wire clkout2_unused; 116 | wire clkout2b_unused; 117 | wire clkout3_unused; 118 | wire clkout3b_unused; 119 | wire clkout4_unused; 120 | wire clkout5_unused; 121 | wire clkout6_unused; 122 | wire clkfbstopped_unused; 123 | wire clkinstopped_unused; 124 | wire reset_high; 125 | 126 | MMCME2_ADV 127 | #(.BANDWIDTH ("OPTIMIZED"), 128 | .CLKOUT4_CASCADE ("FALSE"), 129 | .COMPENSATION ("ZHOLD"), 130 | .STARTUP_WAIT ("FALSE"), 131 | .DIVCLK_DIVIDE (5), 132 | .CLKFBOUT_MULT_F (62.000), 133 | .CLKFBOUT_PHASE (0.000), 134 | .CLKFBOUT_USE_FINE_PS ("FALSE"), 135 | .CLKOUT0_DIVIDE_F (10.000), 136 | .CLKOUT0_PHASE (0.000), 137 | .CLKOUT0_DUTY_CYCLE (0.500), 138 | .CLKOUT0_USE_FINE_PS ("FALSE"), 139 | .CLKOUT1_DIVIDE (31), 140 | .CLKOUT1_PHASE (0.000), 141 | .CLKOUT1_DUTY_CYCLE (0.500), 142 | .CLKOUT1_USE_FINE_PS ("FALSE"), 143 | .CLKIN1_PERIOD (20.000)) 144 | mmcm_adv_inst 145 | // Output clocks 146 | ( 147 | .CLKFBOUT (clkfbout_pll_example), 148 | .CLKFBOUTB (clkfboutb_unused), 149 | .CLKOUT0 (clk_out1_pll_example), 150 | .CLKOUT0B (clkout0b_unused), 151 | .CLKOUT1 (clk_out2_pll_example), 152 | .CLKOUT1B (clkout1b_unused), 153 | .CLKOUT2 (clkout2_unused), 154 | .CLKOUT2B (clkout2b_unused), 155 | .CLKOUT3 (clkout3_unused), 156 | .CLKOUT3B (clkout3b_unused), 157 | .CLKOUT4 (clkout4_unused), 158 | .CLKOUT5 (clkout5_unused), 159 | .CLKOUT6 (clkout6_unused), 160 | // Input clock control 161 | .CLKFBIN (clkfbout_buf_pll_example), 162 | .CLKIN1 (clk_in1_pll_example), 163 | .CLKIN2 (1'b0), 164 | // Tied to always select the primary input clock 165 | .CLKINSEL (1'b1), 166 | // Ports for dynamic reconfiguration 167 | .DADDR (7'h0), 168 | .DCLK (1'b0), 169 | .DEN (1'b0), 170 | .DI (16'h0), 171 | .DO (do_unused), 172 | .DRDY (drdy_unused), 173 | .DWE (1'b0), 174 | // Ports for dynamic phase shift 175 | .PSCLK (1'b0), 176 | .PSEN (1'b0), 177 | .PSINCDEC (1'b0), 178 | .PSDONE (psdone_unused), 179 | // Other control and status signals 180 | .LOCKED (locked_int), 181 | .CLKINSTOPPED (clkinstopped_unused), 182 | .CLKFBSTOPPED (clkfbstopped_unused), 183 | .PWRDWN (1'b0), 184 | .RST (reset_high)); 185 | assign reset_high = reset; 186 | 187 | assign locked = locked_int; 188 | // Clock Monitor clock assigning 189 | //-------------------------------------- 190 | // Output buffering 191 | //----------------------------------- 192 | 193 | BUFG clkf_buf 194 | (.O (clkfbout_buf_pll_example), 195 | .I (clkfbout_pll_example)); 196 | 197 | 198 | 199 | 200 | 201 | 202 | BUFG clkout1_buf 203 | (.O (clk_out1), 204 | .I (clk_out1_pll_example)); 205 | 206 | 207 | BUFG clkout2_buf 208 | (.O (clk_out2), 209 | .I (clk_out2_pll_example)); 210 | 211 | 212 | 213 | endmodule 214 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/ip/pll_example/pll_example_ooc.xdc: -------------------------------------------------------------------------------- 1 | 2 | # file: pll_example_ooc.xdc 3 | # 4 | # (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved. 5 | # 6 | # This file contains confidential and proprietary information 7 | # of Xilinx, Inc. and is protected under U.S. and 8 | # international copyright and other intellectual property 9 | # laws. 10 | # 11 | # DISCLAIMER 12 | # This disclaimer is not a license and does not grant any 13 | # rights to the materials distributed herewith. Except as 14 | # otherwise provided in a valid license issued to you by 15 | # Xilinx, and to the maximum extent permitted by applicable 16 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND 17 | # WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES 18 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING 19 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- 20 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and 21 | # (2) Xilinx shall not be liable (whether in contract or tort, 22 | # including negligence, or under any other theory of 23 | # liability) for any loss or damage of any kind or nature 24 | # related to, arising under or in connection with these 25 | # materials, including for any direct, or any indirect, 26 | # special, incidental, or consequential loss or damage 27 | # (including loss of data, profits, goodwill, or any type of 28 | # loss or damage suffered as a result of any action brought 29 | # by a third party) even if such damage or loss was 30 | # reasonably foreseeable or Xilinx had been advised of the 31 | # possibility of the same. 32 | # 33 | # CRITICAL APPLICATIONS 34 | # Xilinx products are not designed or intended to be fail- 35 | # safe, or for use in any application requiring fail-safe 36 | # performance, such as life-support or safety devices or 37 | # systems, Class III medical devices, nuclear facilities, 38 | # applications related to the deployment of airbags, or any 39 | # other applications that could lead to death, personal 40 | # injury, or severe property or environmental damage 41 | # (individually and collectively, "Critical 42 | # Applications"). Customer assumes the sole risk and 43 | # liability of any use of Xilinx products in Critical 44 | # Applications, subject only to applicable laws and 45 | # regulations governing limitations on product liability. 46 | # 47 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS 48 | # PART OF THIS FILE AT ALL TIMES. 49 | # 50 | 51 | ################# 52 | #DEFAULT CLOCK CONSTRAINTS 53 | 54 | ############################################################ 55 | # Clock Period Constraints # 56 | ############################################################ 57 | #create_clock -period 20.000 [get_ports clk_in1] 58 | 59 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/accelerator.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/16 11:20:08 7 | // Design Name: 8 | // Module Name: accelerator 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../imports/new/define.v" 23 | module accelerator( 24 | input wire clk, 25 | 26 | input wire [31:0] spe_data_i, // 待处理数据 27 | 28 | output wire [31:0] spe_result_o 29 | ); 30 | 31 | // 获取result的逻辑，就是加速器逻辑 32 | // 尽可能【并行处理数据】 33 | // assign spe_result_o = spe_data_i + spe_data_i; 34 | wire [5:0] temp [31:0]; 35 | 36 | 37 | genvar i; 38 | generate 39 | for(i = 0; i < 16; i = i + 1) 40 | begin 41 | assign temp[i] = spe_data_i[i+i] + spe_data_i[i+i+1]; 42 | end 43 | endgenerate 44 | 45 | generate 46 | for(i = 0; i < 8; i = i + 1) 47 | begin 48 | assign temp[i+16] = temp[2*i] + temp[2*i + 1]; 49 | end 50 | endgenerate 51 | 52 | 53 | // max 32 54 | 55 | // group 1, number = 16 56 | // assign temp[0] = spe_data_i[0] + spe_data_i[1]; 57 | // assign temp[1] = spe_data_i[2] + spe_data_i[3]; 58 | // assign temp[2] = spe_data_i[4] + spe_data_i[5]; 59 | // assign temp[3] = spe_data_i[6] + spe_data_i[7]; 60 | // assign temp[4] = spe_data_i[8] + spe_data_i[9]; 61 | // assign temp[5] = spe_data_i[10] + spe_data_i[11]; 62 | // assign temp[6] = spe_data_i[12] + spe_data_i[13]; 63 | // assign temp[7] = spe_data_i[14] + spe_data_i[15]; 64 | // assign temp[8] = spe_data_i[16] + spe_data_i[17]; 65 | // assign temp[9] = spe_data_i[18] + spe_data_i[19]; 66 | // assign temp[10] = spe_data_i[20] + spe_data_i[21]; 67 | // assign temp[11] = spe_data_i[22] + spe_data_i[23]; 68 | // assign temp[12] = spe_data_i[24] + spe_data_i[25]; 69 | // assign temp[13] = spe_data_i[26] + spe_data_i[27]; 70 | // assign temp[14] = spe_data_i[28] + spe_data_i[29]; 71 | // assign temp[15] = spe_data_i[30] + spe_data_i[31]; 72 | 73 | 74 | // group 2, number = 8 75 | // assign temp[16] = temp[0] + temp[1]; 76 | // assign temp[17] = temp[2] + temp[3]; 77 | // assign temp[18] = temp[4] + temp[5]; 78 | // assign temp[19] = temp[6] + temp[7]; 79 | // assign temp[20] = temp[8] + temp[9]; 80 | // assign temp[21] = temp[10] + temp[11]; 81 | // assign temp[22] = temp[12] + temp[13]; 82 | // assign temp[23] = temp[14] + temp[15]; 83 | 84 | 85 | // group 3, number = 4 86 | assign temp[24] = temp[16] + temp[17]; 87 | assign temp[25] = temp[18] + temp[19]; 88 | assign temp[26] = temp[20] + temp[21]; 89 | assign temp[27] = temp[22] + temp[23]; 90 | 91 | // group 4, number = 2 92 | assign temp[28] = temp[24] + temp[25]; 93 | assign temp[29] = temp[26] + temp[27]; 94 | 95 | // group 5, number = 1 96 | assign temp[30] = temp[28] + temp[29]; 97 | 98 | // final 99 | assign spe_result_o = {26'b0, temp[30]}; 100 | 101 | endmodule 102 | -------------------------------------------------------------------------------- /thinpad_top.srcs/sources_1/new/mem_speed.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 2021/08/16 09:30:00 7 | // Design Name: 8 | // Module Name: mem_speed 9 | // Project Name: 10 | // Target Devices: 11 | // Tool Versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | 22 | `include "../imports/new/define.v" 23 | module mem_speed( 24 | input wire clk, 25 | input wire rst_n, 26 | 27 | input wire [31:0] spe_addr_i, 28 | input wire [31:0] spe_data_i, 29 | 30 | input wire [1:0] spe_mode_i, 31 | input wire spe_data_w_i, 32 | input wire spe_data_r_i, 33 | 34 | output wire spe_stall_pipe_o, 35 | output wire spe_or_mem_o, // spe data or other mem data 36 | output reg [31:0] spe_data_o 37 | ); 38 | 39 | ////////////////////////////////////////////// 40 | reg [31:0] spe_buffer; 41 | 42 | localparam READY = 1'b1; 43 | localparam NOT_READY = 1'b0; 44 | reg ready; // 为1表示处理完毕，可以读取；若为0就读取，暂停流水等待 45 | 46 | // localparam AVAI = 1'b1; 47 | // localparam NOT_AVAI = 1'b0; 48 | // reg avai; // 表示当前buffer数据是待处理数据，1代表数据可用 49 | 50 | localparam BUSY = 1'b1; 51 | localparam NOT_BUSY = 1'b0; 52 | reg busy; // 1代表忙碌，不允许写入，如果要写入，就暂停流水线等待 53 | ////////////////////////////////////////////// 54 | 55 | 56 | 57 | /*************************************************/ 58 | /**** 以下两个参数可能需要需修改 ****/ 59 | /*************************************************/ 60 | // 该参数用于指明，需要多少个周期使得ready信号有效（置1） 61 | // 根据实际情况修改，注意是【从0开始】计数！ 62 | // 若修改频率，需要改【pll】和【串口收发器参数】 63 | // 若降频后硬件加速器能够运行，则降频是值得的！ 64 | // 频率与WAIT_COUNT的范围 65 | // 64MHZ: [-1,2] 且为整数 66 | // 61MHz: [3,4] 67 | localparam WAIT_COUNT = 1; // 等待周期数 = WAIT_COUNT + 1 68 | 69 | 70 | // 计数器位宽，与WAIT_COUNT有关，比log2(WAIT_COUNT)大一点儿 71 | localparam COUNTER_SIZE = 5; 72 | 73 | /////////////////////////////////////////////////// 74 | ////////////////// 加速器 /////////////////// 75 | /////////////////////////////////////////////////// 76 | // accelerator 77 | // 加速器处理逻辑，壳子默认不需要处理，直连 78 | 79 | /// input 80 | wire [31:0] spe_data_i_acc; 81 | assign spe_data_i_acc = spe_buffer; 82 | 83 | /// output 84 | wire [31:0] spe_result_o; 85 | 86 | // 通过加速器，获取spe_result 87 | // 需要修改模块内部逻辑 88 | // (* use_dsp = "yes" *) // 综合实现，使用DSP加速器，这个看情况！ 89 | accelerator u_accelerator ( 90 | .clk ( clk ), 91 | 92 | .spe_data_i ( spe_data_i_acc ), 93 | 94 | .spe_result_o ( spe_result_o ) 95 | ); 96 | 97 | /////////////////////////////////////////////////// 98 | ////////////////// 加速器 /////////////////// 99 | /////////////////////////////////////////////////// 100 | /*************************************************/ 101 | 102 | 103 | // ready signal 104 | wire data_w_buffer_pre; // for WAIT_COUNT == -1 105 | 106 | reg [COUNTER_SIZE - 1:0] counter; // 计数器 107 | 108 | localparam IDLE = 2'b01; 109 | localparam START = 2'b10; 110 | reg [1:0] state; 111 | 112 | always @(posedge clk or posedge rst_n) 113 | begin 114 | if(rst_n == `rst_enable) 115 | begin 116 | counter <= 0; 117 | ready <= NOT_READY; 118 | state <= IDLE; 119 | end 120 | else if(WAIT_COUNT == -1) // 等待0周期 121 | begin 122 | if(data_w_buffer_pre) 123 | begin 124 | ready <= READY; 125 | end 126 | 127 | if(spe_data_r_i == `data_r_enable) 128 | begin 129 | ready <= NOT_READY; 130 | end 131 | end 132 | else 133 | begin 134 | case(state) 135 | IDLE: 136 | begin 137 | if(spe_data_r_i == `data_r_enable) 138 | begin 139 | ready <= NOT_READY; 140 | end 141 | counter <= 0; 142 | 143 | if(busy == BUSY) 144 | begin 145 | state <= START; 146 | end 147 | end 148 | 149 | START: 150 | begin 151 | counter <= counter + 1; 152 | if(counter == WAIT_COUNT) 153 | begin 154 | ready <= READY; 155 | state <= IDLE; 156 | end 157 | end 158 | endcase 159 | end 160 | end 161 | 162 | 163 | 164 | // 根据CPU给出的mode处理sel 165 | reg [3:0] sel; 166 | always@(*) 167 | begin 168 | if(rst_n == `rst_enable) 169 | begin 170 | sel <= 4'b0000; 171 | end 172 | else if(spe_mode_i == `word_mode) 173 | begin 174 | sel <= 4'b0000; 175 | end 176 | else if(spe_mode_i == `byte_mode) 177 | begin 178 | case(spe_addr_i[1:0]) 179 | 2'b00: 180 | sel <= 4'b1110; 181 | 2'b01: 182 | sel <= 4'b1101; 183 | 2'b10: 184 | sel <= 4'b1011; 185 | 2'b11: 186 | sel <= 4'b0111; 187 | default: 188 | sel <= 4'b0000; 189 | endcase 190 | end 191 | else 192 | begin 193 | sel <= 4'b0000; 194 | end 195 | end 196 | 197 | // 根据sel结果转换要写入的数据 198 | reg [31:0] data_i_convert; 199 | always @(*) 200 | begin 201 | case(sel) 202 | 4'b0000: 203 | data_i_convert <= spe_data_i; 204 | 4'b0111: 205 | data_i_convert <= {spe_data_i[7:0], 24'h00_0000}; 206 | 4'b1011: 207 | data_i_convert <= {8'h00, spe_data_i[7:0], 16'h0000}; 208 | 4'b1101: 209 | data_i_convert <= {16'h0000, spe_data_i[7:0], 8'h00}; 210 | 4'b1110: 211 | data_i_convert <= {24'h00_0000, spe_data_i[7:0]}; 212 | default: 213 | data_i_convert <= 32'h0000_0000; // 其他情况非法 214 | endcase 215 | end 216 | 217 | ////////////////////// 218 | // write logic 219 | ////////////////////// 220 | 221 | // 为1代表允许写入到buffer 222 | wire data_w_buffer = 223 | (spe_data_w_i == `data_w_enable) && 224 | (spe_addr_i[31:24] == 8'hFF) && 225 | (busy == NOT_BUSY); 226 | 227 | assign data_w_buffer_pre = data_w_buffer; 228 | 229 | always @(posedge clk or posedge rst_n) 230 | begin 231 | if(rst_n == `rst_enable) 232 | begin 233 | spe_buffer <= 0; 234 | end 235 | else 236 | begin 237 | if(data_w_buffer) 238 | begin 239 | spe_buffer <= data_i_convert; 240 | end 241 | end 242 | end 243 | 244 | // busy signal 245 | always @(posedge clk or posedge rst_n) 246 | begin 247 | if(rst_n == `rst_enable) 248 | begin 249 | busy <= NOT_BUSY; 250 | end 251 | else 252 | begin 253 | if(data_w_buffer && (WAIT_COUNT != -1)) 254 | begin 255 | busy <= BUSY; 256 | end 257 | else if(counter == WAIT_COUNT) 258 | begin 259 | busy <= NOT_BUSY; 260 | end 261 | end 262 | end 263 | 264 | ////////////////////// 265 | // read logic 266 | ////////////////////// 267 | 268 | 269 | 270 | // 处理即将输出的数据，lb/lw 271 | always @(*) 272 | begin 273 | case(sel) 274 | 4'b0000: 275 | spe_data_o <= spe_result_o; 276 | 4'b0111: 277 | spe_data_o <= {{24{spe_result_o[31]}}, spe_result_o[31:24]}; 278 | 4'b1011: 279 | spe_data_o <= {{24{spe_result_o[23]}}, spe_result_o[23:16]}; 280 | 4'b1101: 281 | spe_data_o <= {{24{spe_result_o[15]}}, spe_result_o[15:8]}; 282 | 4'b1110: 283 | spe_data_o <= {{24{spe_result_o[7]}}, spe_result_o[7:0]}; 284 | default: 285 | spe_data_o <= 32'h0000_0000; 286 | endcase 287 | end 288 | 289 | // stall pipeline logic, active-low 290 | // NOTE:addr is 0xFFFF_0000 - 0xFFFF_0003 291 | assign spe_stall_pipe_o = 292 | !( 293 | ( 294 | (spe_data_r_i == `data_r_enable) && 295 | (spe_addr_i[31:24] == 8'hFF) && 296 | (ready == NOT_READY) 297 | ) || 298 | ( 299 | (spe_data_w_i == `data_w_enable) && 300 | (spe_addr_i[31:24] == 8'hFF) && 301 | (busy == BUSY) 302 | ) 303 | ); 304 | 305 | // speed data or memory data 306 | // 1 -- speed data; 0 -- memory data 307 | assign spe_or_mem_o = 308 | (spe_data_r_i == `data_r_enable) && 309 | (spe_addr_i[31:24] == 8'hFF); 310 | 311 | 312 | endmodule 313 | -------------------------------------------------------------------------------- /vivado_pid1536.str: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/vivado_pid1536.str -------------------------------------------------------------------------------- /vivado_pid38980.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/vivado_pid38980.zip -------------------------------------------------------------------------------- /vivado_pid44580.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/vivado_pid44580.zip -------------------------------------------------------------------------------- /vivado_pid47984.str: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/CSerht/NSCSCC2021FinalCode/cc6a76f970bb5e865df645e3566bf26f65f8303a/vivado_pid47984.str --------------------------------------------------------------------------------